Added missing tegra files.HEADmaster

29 files changed, 20083 insertions, 0 deletions

diff --git a/drivers/tty/hvc/hvc_iseries.c b/drivers/tty/hvc/hvc_iseries.c
new file mode 100644
index 00000000000..21c54955084
--- /dev/null
+++ b/drivers/tty/hvc/hvc_iseries.c
@@ -0,0 +1,598 @@
+/*
+ * iSeries vio driver interface to hvc_console.c
+ *
+ * This code is based heavily on hvc_vio.c and viocons.c
+ *
+ * Copyright (C) 2006 Stephen Rothwell, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#include <stdarg.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/spinlock.h>
+#include <linux/console.h>
+
+#include <asm/hvconsole.h>
+#include <asm/vio.h>
+#include <asm/prom.h>
+#include <asm/firmware.h>
+#include <asm/iseries/vio.h>
+#include <asm/iseries/hv_call.h>
+#include <asm/iseries/hv_lp_config.h>
+#include <asm/iseries/hv_lp_event.h>
+
+#include "hvc_console.h"
+
+#define VTTY_PORTS 10
+
+static DEFINE_SPINLOCK(consolelock);
+static DEFINE_SPINLOCK(consoleloglock);
+
+static const char hvc_driver_name[] = "hvc_console";
+
+#define IN_BUF_SIZE     200
+
+/*
+ * Our port information.
+ */
+static struct port_info {
+        HvLpIndex lp;
+        u64 seq;        /* sequence number of last HV send */
+        u64 ack;        /* last ack from HV */
+        struct hvc_struct *hp;
+        int in_start;
+        int in_end;
+        unsigned char in_buf[IN_BUF_SIZE];
+} port_info[VTTY_PORTS] = {
+        [ 0 ... VTTY_PORTS - 1 ] = {
+                .lp = HvLpIndexInvalid
+        }
+};
+
+#define viochar_is_console(pi)  ((pi) == &port_info[0])
+
+static struct vio_device_id hvc_driver_table[] __devinitdata = {
+        {"serial", "IBM,iSeries-vty"},
+        { "", "" }
+};
+MODULE_DEVICE_TABLE(vio, hvc_driver_table);
+
+static void hvlog(char *fmt, ...)
+{
+        int i;
+        unsigned long flags;
+        va_list args;
+        static char buf[256];
+
+        spin_lock_irqsave(&consoleloglock, flags);
+        va_start(args, fmt);
+        i = vscnprintf(buf, sizeof(buf) - 1, fmt, args);
+        va_end(args);
+        buf[i++] = '\r';
+        HvCall_writeLogBuffer(buf, i);
+        spin_unlock_irqrestore(&consoleloglock, flags);
+}
+
+/*
+ * Initialize the common fields in a charLpEvent
+ */
+static void init_data_event(struct viocharlpevent *viochar, HvLpIndex lp)
+{
+        struct HvLpEvent *hev = &viochar->event;
+
+        memset(viochar, 0, sizeof(struct viocharlpevent));
+
+        hev->flags = HV_LP_EVENT_VALID | HV_LP_EVENT_DEFERRED_ACK |
+                HV_LP_EVENT_INT;
+        hev->xType = HvLpEvent_Type_VirtualIo;
+        hev->xSubtype = viomajorsubtype_chario | viochardata;
+        hev->xSourceLp = HvLpConfig_getLpIndex();
+        hev->xTargetLp = lp;
+        hev->xSizeMinus1 = sizeof(struct viocharlpevent);
+        hev->xSourceInstanceId = viopath_sourceinst(lp);
+        hev->xTargetInstanceId = viopath_targetinst(lp);
+}
+
+static int get_chars(uint32_t vtermno, char *buf, int count)
+{
+        struct port_info *pi;
+        int n = 0;
+        unsigned long flags;
+
+        if (vtermno >= VTTY_PORTS)
+                return -EINVAL;
+        if (count == 0)
+                return 0;
+
+        pi = &port_info[vtermno];
+        spin_lock_irqsave(&consolelock, flags);
+
+        if (pi->in_end == 0)
+                goto done;
+
+        n = pi->in_end - pi->in_start;
+        if (n > count)
+                n = count;
+        memcpy(buf, &pi->in_buf[pi->in_start], n);
+        pi->in_start += n;
+        if (pi->in_start == pi->in_end) {
+                pi->in_start = 0;
+                pi->in_end = 0;
+        }
+done:
+        spin_unlock_irqrestore(&consolelock, flags);
+        return n;
+}
+
+static int put_chars(uint32_t vtermno, const char *buf, int count)
+{
+        struct viocharlpevent *viochar;
+        struct port_info *pi;
+        HvLpEvent_Rc hvrc;
+        unsigned long flags;
+        int sent = 0;
+
+        if (vtermno >= VTTY_PORTS)
+                return -EINVAL;
+
+        pi = &port_info[vtermno];
+
+        spin_lock_irqsave(&consolelock, flags);
+
+        if (viochar_is_console(pi) && !viopath_isactive(pi->lp)) {
+                HvCall_writeLogBuffer(buf, count);
+                sent = count;
+                goto done;
+        }
+
+        viochar = vio_get_event_buffer(viomajorsubtype_chario);
+        if (viochar == NULL) {
+                hvlog("\n\rviocons: Can't get viochar buffer.");
+                goto done;
+        }
+
+        while ((count > 0) && ((pi->seq - pi->ack) < VIOCHAR_WINDOW)) {
+                int len;
+
+                len = (count > VIOCHAR_MAX_DATA) ? VIOCHAR_MAX_DATA : count;
+
+                if (viochar_is_console(pi))
+                        HvCall_writeLogBuffer(buf, len);
+
+                init_data_event(viochar, pi->lp);
+
+                viochar->len = len;
+                viochar->event.xCorrelationToken = pi->seq++;
+                viochar->event.xSizeMinus1 =
+                        offsetof(struct viocharlpevent, data) + len;
+
+                memcpy(viochar->data, buf, len);
+
+                hvrc = HvCallEvent_signalLpEvent(&viochar->event);
+                if (hvrc)
+                        hvlog("\n\rerror sending event! return code %d\n\r",
+                                (int)hvrc);
+                sent += len;
+                count -= len;
+                buf += len;
+        }
+
+        vio_free_event_buffer(viomajorsubtype_chario, viochar);
+done:
+        spin_unlock_irqrestore(&consolelock, flags);
+        return sent;
+}
+
+static const struct hv_ops hvc_get_put_ops = {
+        .get_chars = get_chars,
+        .put_chars = put_chars,
+        .notifier_add = notifier_add_irq,
+        .notifier_del = notifier_del_irq,
+        .notifier_hangup = notifier_hangup_irq,
+};
+
+static int __devinit hvc_vio_probe(struct vio_dev *vdev,
+                        const struct vio_device_id *id)
+{
+        struct hvc_struct *hp;
+        struct port_info *pi;
+
+        /* probed with invalid parameters. */
+        if (!vdev || !id)
+                return -EPERM;
+
+        if (vdev->unit_address >= VTTY_PORTS)
+                return -ENODEV;
+
+        pi = &port_info[vdev->unit_address];
+
+        hp = hvc_alloc(vdev->unit_address, vdev->irq, &hvc_get_put_ops,
+                        VIOCHAR_MAX_DATA);
+        if (IS_ERR(hp))
+                return PTR_ERR(hp);
+        pi->hp = hp;
+        dev_set_drvdata(&vdev->dev, pi);
+
+        return 0;
+}
+
+static int __devexit hvc_vio_remove(struct vio_dev *vdev)
+{
+        struct port_info *pi = dev_get_drvdata(&vdev->dev);
+        struct hvc_struct *hp = pi->hp;
+
+        return hvc_remove(hp);
+}
+
+static struct vio_driver hvc_vio_driver = {
+        .id_table       = hvc_driver_table,
+        .probe          = hvc_vio_probe,
+        .remove         = __devexit_p(hvc_vio_remove),
+        .driver         = {
+                .name   = hvc_driver_name,
+                .owner  = THIS_MODULE,
+        }
+};
+
+static void hvc_open_event(struct HvLpEvent *event)
+{
+        unsigned long flags;
+        struct viocharlpevent *cevent = (struct viocharlpevent *)event;
+        u8 port = cevent->virtual_device;
+        struct port_info *pi;
+        int reject = 0;
+
+        if (hvlpevent_is_ack(event)) {
+                if (port >= VTTY_PORTS)
+                        return;
+
+                spin_lock_irqsave(&consolelock, flags);
+
+                pi = &port_info[port];
+                if (event->xRc == HvLpEvent_Rc_Good) {
+                        pi->seq = pi->ack = 0;
+                        /*
+                         * This line allows connections from the primary
+                         * partition but once one is connected from the
+                         * primary partition nothing short of a reboot
+                         * of linux will allow access from the hosting
+                         * partition again without a required iSeries fix.
+                         */
+                        pi->lp = event->xTargetLp;
+                }
+
+                spin_unlock_irqrestore(&consolelock, flags);
+                if (event->xRc != HvLpEvent_Rc_Good)
+                        printk(KERN_WARNING
+                               "hvc: handle_open_event: event->xRc == (%d).\n",
+                               event->xRc);
+
+                if (event->xCorrelationToken != 0) {
+                        atomic_t *aptr= (atomic_t *)event->xCorrelationToken;
+                        atomic_set(aptr, 1);
+                } else
+                        printk(KERN_WARNING
+                               "hvc: weird...got open ack without atomic\n");
+                return;
+        }
+
+        /* This had better require an ack, otherwise complain */
+        if (!hvlpevent_need_ack(event)) {
+                printk(KERN_WARNING "hvc: viocharopen without ack bit!\n");
+                return;
+        }
+
+        spin_lock_irqsave(&consolelock, flags);
+
+        /* Make sure this is a good virtual tty */
+        if (port >= VTTY_PORTS) {
+                event->xRc = HvLpEvent_Rc_SubtypeError;
+                cevent->subtype_result_code = viorc_openRejected;
+                /*
+                 * Flag state here since we can't printk while holding
+                 * the consolelock spinlock.
+                 */
+                reject = 1;
+        } else {
+                pi = &port_info[port];
+                if ((pi->lp != HvLpIndexInvalid) &&
+                                (pi->lp != event->xSourceLp)) {
+                        /*
+                         * If this is tty is already connected to a different
+                         * partition, fail.
+                         */
+                        event->xRc = HvLpEvent_Rc_SubtypeError;
+                        cevent->subtype_result_code = viorc_openRejected;
+                        reject = 2;
+                } else {
+                        pi->lp = event->xSourceLp;
+                        event->xRc = HvLpEvent_Rc_Good;
+                        cevent->subtype_result_code = viorc_good;
+                        pi->seq = pi->ack = 0;
+                }
+        }
+
+        spin_unlock_irqrestore(&consolelock, flags);
+
+        if (reject == 1)
+                printk(KERN_WARNING "hvc: open rejected: bad virtual tty.\n");
+        else if (reject == 2)
+                printk(KERN_WARNING "hvc: open rejected: console in exclusive "
+                                "use by another partition.\n");
+
+        /* Return the acknowledgement */
+        HvCallEvent_ackLpEvent(event);
+}
+
+/*
+ * Handle a close charLpEvent.  This should ONLY be an Interrupt because the
+ * virtual console should never actually issue a close event to the hypervisor
+ * because the virtual console never goes away.  A close event coming from the
+ * hypervisor simply means that there are no client consoles connected to the
+ * virtual console.
+ */
+static void hvc_close_event(struct HvLpEvent *event)
+{
+        unsigned long flags;
+        struct viocharlpevent *cevent = (struct viocharlpevent *)event;
+        u8 port = cevent->virtual_device;
+
+        if (!hvlpevent_is_int(event)) {
+                printk(KERN_WARNING
+                        "hvc: got unexpected close acknowledgement\n");
+                return;
+        }
+
+        if (port >= VTTY_PORTS) {
+                printk(KERN_WARNING
+                        "hvc: close message from invalid virtual device.\n");
+                return;
+        }
+
+        /* For closes, just mark the console partition invalid */
+        spin_lock_irqsave(&consolelock, flags);
+
+        if (port_info[port].lp == event->xSourceLp)
+                port_info[port].lp = HvLpIndexInvalid;
+
+        spin_unlock_irqrestore(&consolelock, flags);
+}
+
+static void hvc_data_event(struct HvLpEvent *event)
+{
+        unsigned long flags;
+        struct viocharlpevent *cevent = (struct viocharlpevent *)event;
+        struct port_info *pi;
+        int n;
+        u8 port = cevent->virtual_device;
+
+        if (port >= VTTY_PORTS) {
+                printk(KERN_WARNING "hvc: data on invalid virtual device %d\n",
+                                port);
+                return;
+        }
+        if (cevent->len == 0)
+                return;
+
+        /*
+         * Change 05/01/2003 - Ryan Arnold: If a partition other than
+         * the current exclusive partition tries to send us data
+         * events then just drop them on the floor because we don't
+         * want his stinking data.  He isn't authorized to receive
+         * data because he wasn't the first one to get the console,
+         * therefore he shouldn't be allowed to send data either.
+         * This will work without an iSeries fix.
+         */
+        pi = &port_info[port];
+        if (pi->lp != event->xSourceLp)
+                return;
+
+        spin_lock_irqsave(&consolelock, flags);
+
+        n = IN_BUF_SIZE - pi->in_end;
+        if (n > cevent->len)
+                n = cevent->len;
+        if (n > 0) {
+                memcpy(&pi->in_buf[pi->in_end], cevent->data, n);
+                pi->in_end += n;
+        }
+        spin_unlock_irqrestore(&consolelock, flags);
+        if (n == 0)
+                printk(KERN_WARNING "hvc: input buffer overflow\n");
+}
+
+static void hvc_ack_event(struct HvLpEvent *event)
+{
+        struct viocharlpevent *cevent = (struct viocharlpevent *)event;
+        unsigned long flags;
+        u8 port = cevent->virtual_device;
+
+        if (port >= VTTY_PORTS) {
+                printk(KERN_WARNING "hvc: data on invalid virtual device\n");
+                return;
+        }
+
+        spin_lock_irqsave(&consolelock, flags);
+        port_info[port].ack = event->xCorrelationToken;
+        spin_unlock_irqrestore(&consolelock, flags);
+}
+
+static void hvc_config_event(struct HvLpEvent *event)
+{
+        struct viocharlpevent *cevent = (struct viocharlpevent *)event;
+
+        if (cevent->data[0] == 0x01)
+                printk(KERN_INFO "hvc: window resized to %d: %d: %d: %d\n",
+                       cevent->data[1], cevent->data[2],
+                       cevent->data[3], cevent->data[4]);
+        else
+                printk(KERN_WARNING "hvc: unknown config event\n");
+}
+
+static void hvc_handle_event(struct HvLpEvent *event)
+{
+        int charminor;
+
+        if (event == NULL)
+                return;
+
+        charminor = event->xSubtype & VIOMINOR_SUBTYPE_MASK;
+        switch (charminor) {
+        case viocharopen:
+                hvc_open_event(event);
+                break;
+        case viocharclose:
+                hvc_close_event(event);
+                break;
+        case viochardata:
+                hvc_data_event(event);
+                break;
+        case viocharack:
+                hvc_ack_event(event);
+                break;
+        case viocharconfig:
+                hvc_config_event(event);
+                break;
+        default:
+                if (hvlpevent_is_int(event) && hvlpevent_need_ack(event)) {
+                        event->xRc = HvLpEvent_Rc_InvalidSubtype;
+                        HvCallEvent_ackLpEvent(event);
+                }
+        }
+}
+
+static int __init send_open(HvLpIndex remoteLp, void *sem)
+{
+        return HvCallEvent_signalLpEventFast(remoteLp,
+                        HvLpEvent_Type_VirtualIo,
+                        viomajorsubtype_chario | viocharopen,
+                        HvLpEvent_AckInd_DoAck, HvLpEvent_AckType_ImmediateAck,
+                        viopath_sourceinst(remoteLp),
+                        viopath_targetinst(remoteLp),
+                        (u64)(unsigned long)sem, VIOVERSION << 16,
+                        0, 0, 0, 0);
+}
+
+static int __init hvc_vio_init(void)
+{
+        atomic_t wait_flag;
+        int rc;
+
+        if (!firmware_has_feature(FW_FEATURE_ISERIES))
+                return -EIO;
+
+        /* +2 for fudge */
+        rc = viopath_open(HvLpConfig_getPrimaryLpIndex(),
+                        viomajorsubtype_chario, VIOCHAR_WINDOW + 2);
+        if (rc)
+                printk(KERN_WARNING "hvc: error opening to primary %d\n", rc);
+
+        if (viopath_hostLp == HvLpIndexInvalid)
+                vio_set_hostlp();
+
+        /*
+         * And if the primary is not the same as the hosting LP, open to the
+         * hosting lp
+         */
+        if ((viopath_hostLp != HvLpIndexInvalid) &&
+            (viopath_hostLp != HvLpConfig_getPrimaryLpIndex())) {
+                printk(KERN_INFO "hvc: open path to hosting (%d)\n",
+                                viopath_hostLp);
+                rc = viopath_open(viopath_hostLp, viomajorsubtype_chario,
+                                VIOCHAR_WINDOW + 2);    /* +2 for fudge */
+                if (rc)
+                        printk(KERN_WARNING
+                                "error opening to partition %d: %d\n",
+                                viopath_hostLp, rc);
+        }
+
+        if (vio_setHandler(viomajorsubtype_chario, hvc_handle_event) < 0)
+                printk(KERN_WARNING
+                        "hvc: error seting handler for console events!\n");
+
+        /*
+         * First, try to open the console to the hosting lp.
+         * Wait on a semaphore for the response.
+         */
+        atomic_set(&wait_flag, 0);
+        if ((viopath_isactive(viopath_hostLp)) &&
+            (send_open(viopath_hostLp, &wait_flag) == 0)) {
+                printk(KERN_INFO "hvc: hosting partition %d\n", viopath_hostLp);
+                while (atomic_read(&wait_flag) == 0)
+                        mb();
+                atomic_set(&wait_flag, 0);
+        }
+
+        /*
+         * If we don't have an active console, try the primary
+         */
+        if ((!viopath_isactive(port_info[0].lp)) &&
+            (viopath_isactive(HvLpConfig_getPrimaryLpIndex())) &&
+            (send_open(HvLpConfig_getPrimaryLpIndex(), &wait_flag) == 0)) {
+                printk(KERN_INFO "hvc: opening console to primary partition\n");
+                while (atomic_read(&wait_flag) == 0)
+                        mb();
+        }
+
+        /* Register as a vio device to receive callbacks */
+        rc = vio_register_driver(&hvc_vio_driver);
+
+        return rc;
+}
+module_init(hvc_vio_init); /* after drivers/char/hvc_console.c */
+
+static void __exit hvc_vio_exit(void)
+{
+        vio_unregister_driver(&hvc_vio_driver);
+}
+module_exit(hvc_vio_exit);
+
+/* the device tree order defines our numbering */
+static int __init hvc_find_vtys(void)
+{
+        struct device_node *vty;
+        int num_found = 0;
+
+        for (vty = of_find_node_by_name(NULL, "vty"); vty != NULL;
+                        vty = of_find_node_by_name(vty, "vty")) {
+                const uint32_t *vtermno;
+
+                /* We have statically defined space for only a certain number
+                 * of console adapters.
+                 */
+                if ((num_found >= MAX_NR_HVC_CONSOLES) ||
+                                (num_found >= VTTY_PORTS)) {
+                        of_node_put(vty);
+                        break;
+                }
+
+                vtermno = of_get_property(vty, "reg", NULL);
+                if (!vtermno)
+                        continue;
+
+                if (!of_device_is_compatible(vty, "IBM,iSeries-vty"))
+                        continue;
+
+                if (num_found == 0)
+                        add_preferred_console("hvc", 0, NULL);
+                hvc_instantiate(*vtermno, num_found, &hvc_get_put_ops);
+                ++num_found;
+        }
+
+        return num_found;
+}
+console_initcall(hvc_find_vtys);
diff --git a/drivers/tty/serial/68328serial.h b/drivers/tty/serial/68328serial.h
new file mode 100644
index 00000000000..8c9c3c0745d
--- /dev/null
+++ b/drivers/tty/serial/68328serial.h
@@ -0,0 +1,187 @@
+/* 68328serial.h: Definitions for the mc68328 serial driver.
+ *
+ * Copyright (C) 1995       David S. Miller    <davem@caip.rutgers.edu>
+ * Copyright (C) 1998       Kenneth Albanowski <kjahds@kjahds.com>
+ * Copyright (C) 1998, 1999 D. Jeff Dionne     <jeff@uclinux.org>
+ * Copyright (C) 1999       Vladimir Gurevich  <vgurevic@cisco.com>
+ *
+ * VZ Support/Fixes             Evan Stawnyczy <e@lineo.ca>
+ */
+
+#ifndef _MC683XX_SERIAL_H
+#define _MC683XX_SERIAL_H
+
+
+struct serial_struct {
+        int     type;
+        int     line;
+        int     port;
+        int     irq;
+        int     flags;
+        int     xmit_fifo_size;
+        int     custom_divisor;
+        int     baud_base;
+        unsigned short  close_delay;
+        char    reserved_char[2];
+        int     hub6;  /* FIXME: We don't have AT&T Hub6 boards! */
+        unsigned short  closing_wait; /* time to wait before closing */
+        unsigned short  closing_wait2; /* no longer used... */
+        int     reserved[4];
+};
+
+/*
+ * For the close wait times, 0 means wait forever for serial port to
+ * flush its output.  65535 means don't wait at all.
+ */
+#define S_CLOSING_WAIT_INF      0
+#define S_CLOSING_WAIT_NONE     65535
+
+/*
+ * Definitions for S_struct (and serial_struct) flags field
+ */
+#define S_HUP_NOTIFY 0x0001 /* Notify getty on hangups and closes 
+                                   on the callout port */
+#define S_FOURPORT  0x0002      /* Set OU1, OUT2 per AST Fourport settings */
+#define S_SAK   0x0004  /* Secure Attention Key (Orange book) */
+#define S_SPLIT_TERMIOS 0x0008 /* Separate termios for dialin/callout */
+
+#define S_SPD_MASK      0x0030
+#define S_SPD_HI        0x0010  /* Use 56000 instead of 38400 bps */
+
+#define S_SPD_VHI       0x0020  /* Use 115200 instead of 38400 bps */
+#define S_SPD_CUST      0x0030  /* Use user-specified divisor */
+
+#define S_SKIP_TEST     0x0040 /* Skip UART test during autoconfiguration */
+#define S_AUTO_IRQ  0x0080 /* Do automatic IRQ during autoconfiguration */
+#define S_SESSION_LOCKOUT 0x0100 /* Lock out cua opens based on session */
+#define S_PGRP_LOCKOUT    0x0200 /* Lock out cua opens based on pgrp */
+#define S_CALLOUT_NOHUP   0x0400 /* Don't do hangups for cua device */
+
+#define S_FLAGS 0x0FFF  /* Possible legal S flags */
+#define S_USR_MASK 0x0430       /* Legal flags that non-privileged
+                                 * users can set or reset */
+
+/* Internal flags used only by kernel/chr_drv/serial.c */
+#define S_INITIALIZED   0x80000000 /* Serial port was initialized */
+#define S_CALLOUT_ACTIVE        0x40000000 /* Call out device is active */
+#define S_NORMAL_ACTIVE 0x20000000 /* Normal device is active */
+#define S_BOOT_AUTOCONF 0x10000000 /* Autoconfigure port on bootup */
+#define S_CLOSING               0x08000000 /* Serial port is closing */
+#define S_CTS_FLOW              0x04000000 /* Do CTS flow control */
+#define S_CHECK_CD              0x02000000 /* i.e., CLOCAL */
+
+/* Software state per channel */
+
+#ifdef __KERNEL__
+
+/*
+ * I believe this is the optimal setting that reduces the number of interrupts.
+ * At high speeds the output might become a little "bursted" (use USTCNT_TXHE
+ * if that bothers you), but in most cases it will not, since we try to 
+ * transmit characters every time rs_interrupt is called. Thus, quite often
+ * you'll see that a receive interrupt occures before the transmit one.
+ *                                  -- Vladimir Gurevich
+ */
+#define USTCNT_TX_INTR_MASK (USTCNT_TXEE)
+
+/*
+ * 68328 and 68EZ328 UARTS are a little bit different. EZ328 has special
+ * "Old data interrupt" which occures whenever the data stay in the FIFO
+ * longer than 30 bits time. This allows us to use FIFO without compromising
+ * latency. '328 does not have this feature and without the real  328-based
+ * board I would assume that RXRE is the safest setting.
+ *
+ * For EZ328 I use RXHE (Half empty) interrupt to reduce the number of
+ * interrupts. RXFE (receive queue full) causes the system to lose data
+ * at least at 115200 baud
+ *
+ * If your board is busy doing other stuff, you might consider to use
+ * RXRE (data ready intrrupt) instead.
+ *
+ * The other option is to make these INTR masks run-time configurable, so
+ * that people can dynamically adapt them according to the current usage.
+ *                                  -- Vladimir Gurevich
+ */
+
+/* (es) */
+#if defined(CONFIG_M68EZ328) || defined(CONFIG_M68VZ328)
+#define USTCNT_RX_INTR_MASK (USTCNT_RXHE | USTCNT_ODEN)
+#elif defined(CONFIG_M68328)
+#define USTCNT_RX_INTR_MASK (USTCNT_RXRE)
+#else
+#error Please, define the Rx interrupt events for your CPU
+#endif
+/* (/es) */
+
+/*
+ * This is our internal structure for each serial port's state.
+ * 
+ * Many fields are paralleled by the structure used by the serial_struct
+ * structure.
+ *
+ * For definitions of the flags field, see tty.h
+ */
+
+struct m68k_serial {
+        char soft_carrier;  /* Use soft carrier on this channel */
+        char break_abort;   /* Is serial console in, so process brk/abrt */
+        char is_cons;       /* Is this our console. */
+
+        /* We need to know the current clock divisor
+         * to read the bps rate the chip has currently
+         * loaded.
+         */
+        unsigned char clk_divisor;  /* May be 1, 16, 32, or 64 */
+        int baud;
+        int                     magic;
+        int                     baud_base;
+        int                     port;
+        int                     irq;
+        int                     flags;          /* defined in tty.h */
+        int                     type;           /* UART type */
+        struct tty_struct       *tty;
+        int                     read_status_mask;
+        int                     ignore_status_mask;
+        int                     timeout;
+        int                     xmit_fifo_size;
+        int                     custom_divisor;
+        int                     x_char; /* xon/xoff character */
+        int                     close_delay;
+        unsigned short          closing_wait;
+        unsigned short          closing_wait2;
+        unsigned long           event;
+        unsigned long           last_active;
+        int                     line;
+        int                     count;      /* # of fd on device */
+        int                     blocked_open; /* # of blocked opens */
+        unsigned char           *xmit_buf;
+        int                     xmit_head;
+        int                     xmit_tail;
+        int                     xmit_cnt;
+        struct work_struct      tqueue;
+        wait_queue_head_t       open_wait;
+        wait_queue_head_t       close_wait;
+};
+
+
+#define SERIAL_MAGIC 0x5301
+
+/*
+ * The size of the serial xmit buffer is 1 page, or 4096 bytes
+ */
+#define SERIAL_XMIT_SIZE 4096
+
+/*
+ * Events are used to schedule things to happen at timer-interrupt
+ * time, instead of at rs interrupt time.
+ */
+#define RS_EVENT_WRITE_WAKEUP   0
+
+/* 
+ * Define the number of ports supported and their irqs.
+ */
+#define NR_PORTS 1
+#define UART_IRQ_DEFNS {UART_IRQ_NUM}
+
+#endif /* __KERNEL__ */
+#endif /* !(_MC683XX_SERIAL_H) */
diff --git a/drivers/tty/serial/68360serial.c b/drivers/tty/serial/68360serial.c
new file mode 100644
index 00000000000..0a3e8787ed5
--- /dev/null
+++ b/drivers/tty/serial/68360serial.c
@@ -0,0 +1,2979 @@
+/*
+ *  UART driver for 68360 CPM SCC or SMC
+ *  Copyright (c) 2000 D. Jeff Dionne <jeff@uclinux.org>,
+ *  Copyright (c) 2000 Michael Leslie <mleslie@lineo.ca>
+ *  Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
+ *
+ * I used the serial.c driver as the framework for this driver.
+ * Give credit to those guys.
+ * The original code was written for the MBX860 board.  I tried to make
+ * it generic, but there may be some assumptions in the structures that
+ * have to be fixed later.
+ * To save porting time, I did not bother to change any object names
+ * that are not accessed outside of this file.
+ * It still needs lots of work........When it was easy, I included code
+ * to support the SCCs, but this has never been tested, nor is it complete.
+ * Only the SCCs support modem control, so that is not complete either.
+ *
+ * This module exports the following rs232 io functions:
+ *
+ *      int rs_360_init(void);
+ */
+
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial.h>
+#include <linux/serialP.h> 
+#include <linux/major.h>
+#include <linux/string.h>
+#include <linux/fcntl.h>
+#include <linux/ptrace.h>
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <asm/irq.h>
+#include <asm/m68360.h>
+#include <asm/commproc.h>
+
+ 
+#ifdef CONFIG_KGDB
+extern void breakpoint(void);
+extern void set_debug_traps(void);
+extern int  kgdb_output_string (const char* s, unsigned int count);
+#endif
+
+
+/* #ifdef CONFIG_SERIAL_CONSOLE */ /* This seems to be a post 2.0 thing - mles */
+#include <linux/console.h>
+#include <linux/jiffies.h>
+
+/* this defines the index into rs_table for the port to use
+ */
+#ifndef CONFIG_SERIAL_CONSOLE_PORT
+#define CONFIG_SERIAL_CONSOLE_PORT      1 /* ie SMC2 - note USE_SMC2 must be defined */
+#endif
+/* #endif */
+
+#if 0
+/* SCC2 for console
+ */
+#undef CONFIG_SERIAL_CONSOLE_PORT
+#define CONFIG_SERIAL_CONSOLE_PORT      2
+#endif
+
+
+#define TX_WAKEUP       ASYNC_SHARE_IRQ
+
+static char *serial_name = "CPM UART driver";
+static char *serial_version = "0.03";
+
+static struct tty_driver *serial_driver;
+int serial_console_setup(struct console *co, char *options);
+
+/*
+ * Serial driver configuration section.  Here are the various options:
+ */
+#define SERIAL_PARANOIA_CHECK
+#define CONFIG_SERIAL_NOPAUSE_IO
+#define SERIAL_DO_RESTART
+
+/* Set of debugging defines */
+
+#undef SERIAL_DEBUG_INTR
+#undef SERIAL_DEBUG_OPEN
+#undef SERIAL_DEBUG_FLOW
+#undef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
+
+#define _INLINE_ inline
+  
+#define DBG_CNT(s)
+
+/* We overload some of the items in the data structure to meet our
+ * needs.  For example, the port address is the CPM parameter ram
+ * offset for the SCC or SMC.  The maximum number of ports is 4 SCCs and
+ * 2 SMCs.  The "hub6" field is used to indicate the channel number, with
+ * a flag indicating SCC or SMC, and the number is used as an index into
+ * the CPM parameter area for this device.
+ * The "type" field is currently set to 0, for PORT_UNKNOWN.  It is
+ * not currently used.  I should probably use it to indicate the port
+ * type of SMC or SCC.
+ * The SMCs do not support any modem control signals.
+ */
+#define smc_scc_num     hub6
+#define NUM_IS_SCC      ((int)0x00010000)
+#define PORT_NUM(P)     ((P) & 0x0000ffff)
+
+
+#if defined (CONFIG_UCQUICC)
+
+volatile extern void *_periph_base;
+/* sipex transceiver
+ *   mode bits for       are on pins
+ *
+ *    SCC2                d16..19
+ *    SCC3                d20..23
+ *    SCC4                d24..27
+ */
+#define SIPEX_MODE(n,m) ((m & 0x0f)<<(16+4*(n-1)))
+
+static uint sipex_mode_bits = 0x00000000;
+
+#endif
+
+/* There is no `serial_state' defined back here in 2.0.
+ * Try to get by with serial_struct
+ */
+/* #define serial_state serial_struct */
+
+/* 2.4 -> 2.0 portability problem: async_icount in 2.4 has a few
+ * extras: */
+
+#if 0
+struct async_icount_24 {
+        __u32   cts, dsr, rng, dcd, tx, rx;
+        __u32   frame, parity, overrun, brk;
+        __u32   buf_overrun;
+} icount;
+#endif
+
+#if 0
+
+struct serial_state {
+        int     magic;
+        int     baud_base;
+        unsigned long   port;
+        int     irq;
+        int     flags;
+        int     hub6;
+        int     type;
+        int     line;
+        int     revision;       /* Chip revision (950) */
+        int     xmit_fifo_size;
+        int     custom_divisor;
+        int     count;
+        u8      *iomem_base;
+        u16     iomem_reg_shift;
+        unsigned short  close_delay;
+        unsigned short  closing_wait; /* time to wait before closing */
+        struct async_icount_24     icount; 
+        int     io_type;
+        struct async_struct *info;
+};
+#endif
+
+#define SSTATE_MAGIC 0x5302
+
+
+
+/* SMC2 is sometimes used for low performance TDM interfaces.  Define
+ * this as 1 if you want SMC2 as a serial port UART managed by this driver.
+ * Define this as 0 if you wish to use SMC2 for something else.
+ */
+#define USE_SMC2 1
+
+#if 0
+/* Define SCC to ttySx mapping. */
+#define SCC_NUM_BASE    (USE_SMC2 + 1)  /* SCC base tty "number" */
+
+/* Define which SCC is the first one to use for a serial port.  These
+ * are 0-based numbers, i.e. this assumes the first SCC (SCC1) is used
+ * for Ethernet, and the first available SCC for serial UART is SCC2.
+ * NOTE:  IF YOU CHANGE THIS, you have to change the PROFF_xxx and
+ * interrupt vectors in the table below to match.
+ */
+#define SCC_IDX_BASE    1       /* table index */
+#endif
+
+
+/* Processors other than the 860 only get SMCs configured by default.
+ * Either they don't have SCCs or they are allocated somewhere else.
+ * Of course, there are now 860s without some SCCs, so we will need to
+ * address that someday.
+ * The Embedded Planet Multimedia I/O cards use TDM interfaces to the
+ * stereo codec parts, and we use SMC2 to help support that.
+ */
+static struct serial_state rs_table[] = {
+/*  type   line   PORT           IRQ       FLAGS  smc_scc_num (F.K.A. hub6) */
+        {  0,     0, PRSLOT_SMC1, CPMVEC_SMC1,   0,    0 }    /* SMC1 ttyS0 */
+#if USE_SMC2
+        ,{ 0,     0, PRSLOT_SMC2, CPMVEC_SMC2,   0,    1 }     /* SMC2 ttyS1 */
+#endif
+
+#if defined(CONFIG_SERIAL_68360_SCC)
+        ,{ 0,     0, PRSLOT_SCC2, CPMVEC_SCC2,   0, (NUM_IS_SCC | 1) }    /* SCC2 ttyS2 */
+        ,{ 0,     0, PRSLOT_SCC3, CPMVEC_SCC3,   0, (NUM_IS_SCC | 2) }    /* SCC3 ttyS3 */
+        ,{ 0,     0, PRSLOT_SCC4, CPMVEC_SCC4,   0, (NUM_IS_SCC | 3) }    /* SCC4 ttyS4 */
+#endif
+};
+
+#define NR_PORTS        (sizeof(rs_table)/sizeof(struct serial_state))
+
+/* The number of buffer descriptors and their sizes.
+ */
+#define RX_NUM_FIFO     4
+#define RX_BUF_SIZE     32
+#define TX_NUM_FIFO     4
+#define TX_BUF_SIZE     32
+
+#define CONSOLE_NUM_FIFO 2
+#define CONSOLE_BUF_SIZE 4
+
+char *console_fifos[CONSOLE_NUM_FIFO * CONSOLE_BUF_SIZE];
+
+/* The async_struct in serial.h does not really give us what we
+ * need, so define our own here.
+ */
+typedef struct serial_info {
+        int                     magic;
+        int                     flags;
+
+        struct serial_state     *state;
+        /* struct serial_struct *state; */
+        /* struct async_struct  *state; */
+        
+        struct tty_struct       *tty;
+        int                     read_status_mask;
+        int                     ignore_status_mask;
+        int                     timeout;
+        int                     line;
+        int                     x_char; /* xon/xoff character */
+        int                     close_delay;
+        unsigned short          closing_wait;
+        unsigned short          closing_wait2;
+        unsigned long           event;
+        unsigned long           last_active;
+        int                     blocked_open; /* # of blocked opens */
+        struct work_struct      tqueue;
+        struct work_struct      tqueue_hangup;
+        wait_queue_head_t       open_wait; 
+        wait_queue_head_t       close_wait; 
+
+        
+/* CPM Buffer Descriptor pointers.
+        */
+        QUICC_BD                        *rx_bd_base;
+        QUICC_BD                        *rx_cur;
+        QUICC_BD                        *tx_bd_base;
+        QUICC_BD                        *tx_cur;
+} ser_info_t;
+
+
+/* since kmalloc_init() does not get called until much after this initialization: */
+static ser_info_t  quicc_ser_info[NR_PORTS];
+static char rx_buf_pool[NR_PORTS * RX_NUM_FIFO * RX_BUF_SIZE];
+static char tx_buf_pool[NR_PORTS * TX_NUM_FIFO * TX_BUF_SIZE];
+
+static void change_speed(ser_info_t *info);
+static void rs_360_wait_until_sent(struct tty_struct *tty, int timeout);
+
+static inline int serial_paranoia_check(ser_info_t *info,
+                                        char *name, const char *routine)
+{
+#ifdef SERIAL_PARANOIA_CHECK
+        static const char *badmagic =
+                "Warning: bad magic number for serial struct (%s) in %s\n";
+        static const char *badinfo =
+                "Warning: null async_struct for (%s) in %s\n";
+
+        if (!info) {
+                printk(badinfo, name, routine);
+                return 1;
+        }
+        if (info->magic != SERIAL_MAGIC) {
+                printk(badmagic, name, routine);
+                return 1;
+        }
+#endif
+        return 0;
+}
+
+/*
+ * This is used to figure out the divisor speeds and the timeouts,
+ * indexed by the termio value.  The generic CPM functions are responsible
+ * for setting and assigning baud rate generators for us.
+ */
+static int baud_table[] = {
+        0, 50, 75, 110, 134, 150, 200, 300, 600, 1200, 1800, 2400, 4800,
+        9600, 19200, 38400, 57600, 115200, 230400, 460800, 0 };
+
+/* This sucks. There is a better way: */
+#if defined(CONFIG_CONSOLE_9600)
+  #define CONSOLE_BAUDRATE 9600
+#elif defined(CONFIG_CONSOLE_19200)
+  #define CONSOLE_BAUDRATE 19200
+#elif defined(CONFIG_CONSOLE_115200)
+  #define CONSOLE_BAUDRATE 115200
+#else
+  #warning "console baud rate undefined"
+  #define CONSOLE_BAUDRATE 9600
+#endif
+
+/*
+ * ------------------------------------------------------------
+ * rs_stop() and rs_start()
+ *
+ * This routines are called before setting or resetting tty->stopped.
+ * They enable or disable transmitter interrupts, as necessary.
+ * ------------------------------------------------------------
+ */
+static void rs_360_stop(struct tty_struct *tty)
+{
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+        int     idx;
+        unsigned long flags;
+        volatile struct scc_regs *sccp;
+        volatile struct smc_regs *smcp;
+
+        if (serial_paranoia_check(info, tty->name, "rs_stop"))
+                return;
+        
+        local_irq_save(flags);
+        idx = PORT_NUM(info->state->smc_scc_num);
+        if (info->state->smc_scc_num & NUM_IS_SCC) {
+                sccp = &pquicc->scc_regs[idx];
+                sccp->scc_sccm &= ~UART_SCCM_TX;
+        } else {
+                /* smcp = &cpmp->cp_smc[idx]; */
+                smcp = &pquicc->smc_regs[idx];
+                smcp->smc_smcm &= ~SMCM_TX;
+        }
+        local_irq_restore(flags);
+}
+
+
+static void rs_360_start(struct tty_struct *tty)
+{
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+        int     idx;
+        unsigned long flags;
+        volatile struct scc_regs *sccp;
+        volatile struct smc_regs *smcp;
+
+        if (serial_paranoia_check(info, tty->name, "rs_stop"))
+                return;
+        
+        local_irq_save(flags);
+        idx = PORT_NUM(info->state->smc_scc_num);
+        if (info->state->smc_scc_num & NUM_IS_SCC) {
+                sccp = &pquicc->scc_regs[idx];
+                sccp->scc_sccm |= UART_SCCM_TX;
+        } else {
+                smcp = &pquicc->smc_regs[idx];
+                smcp->smc_smcm |= SMCM_TX;
+        }
+        local_irq_restore(flags);
+}
+
+/*
+ * ----------------------------------------------------------------------
+ *
+ * Here starts the interrupt handling routines.  All of the following
+ * subroutines are declared as inline and are folded into
+ * rs_interrupt().  They were separated out for readability's sake.
+ *
+ * Note: rs_interrupt() is a "fast" interrupt, which means that it
+ * runs with interrupts turned off.  People who may want to modify
+ * rs_interrupt() should try to keep the interrupt handler as fast as
+ * possible.  After you are done making modifications, it is not a bad
+ * idea to do:
+ * 
+ * gcc -S -DKERNEL -Wall -Wstrict-prototypes -O6 -fomit-frame-pointer serial.c
+ *
+ * and look at the resulting assemble code in serial.s.
+ *
+ *                              - Ted Ts'o (tytso@mit.edu), 7-Mar-93
+ * -----------------------------------------------------------------------
+ */
+
+static _INLINE_ void receive_chars(ser_info_t *info)
+{
+        struct tty_struct *tty = info->port.tty;
+        unsigned char ch, flag, *cp;
+        /*int   ignored = 0;*/
+        int     i;
+        ushort  status;
+         struct async_icount *icount; 
+        /* struct       async_icount_24 *icount; */
+        volatile QUICC_BD       *bdp;
+
+        icount = &info->state->icount;
+
+        /* Just loop through the closed BDs and copy the characters into
+         * the buffer.
+         */
+        bdp = info->rx_cur;
+        for (;;) {
+                if (bdp->status & BD_SC_EMPTY)  /* If this one is empty */
+                        break;                  /*   we are all done */
+
+                /* The read status mask tell us what we should do with
+                 * incoming characters, especially if errors occur.
+                 * One special case is the use of BD_SC_EMPTY.  If
+                 * this is not set, we are supposed to be ignoring
+                 * inputs.  In this case, just mark the buffer empty and
+                 * continue.
+                 */
+                if (!(info->read_status_mask & BD_SC_EMPTY)) {
+                        bdp->status |= BD_SC_EMPTY;
+                        bdp->status &=
+                                ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV);
+
+                        if (bdp->status & BD_SC_WRAP)
+                                bdp = info->rx_bd_base;
+                        else
+                                bdp++;
+                        continue;
+                }
+
+                /* Get the number of characters and the buffer pointer.
+                */
+                i = bdp->length;
+                /* cp = (unsigned char *)__va(bdp->buf); */
+                cp = (char *)bdp->buf;
+                status = bdp->status;
+
+                while (i-- > 0) {
+                        ch = *cp++;
+                        icount->rx++;
+
+#ifdef SERIAL_DEBUG_INTR
+                        printk("DR%02x:%02x...", ch, status);
+#endif
+                        flag = TTY_NORMAL;
+
+                        if (status & (BD_SC_BR | BD_SC_FR |
+                                       BD_SC_PR | BD_SC_OV)) {
+                                /*
+                                 * For statistics only
+                                 */
+                                if (status & BD_SC_BR)
+                                        icount->brk++;
+                                else if (status & BD_SC_PR)
+                                        icount->parity++;
+                                else if (status & BD_SC_FR)
+                                        icount->frame++;
+                                if (status & BD_SC_OV)
+                                        icount->overrun++;
+
+                                /*
+                                 * Now check to see if character should be
+                                 * ignored, and mask off conditions which
+                                 * should be ignored.
+                                if (status & info->ignore_status_mask) {
+                                        if (++ignored > 100)
+                                                break;
+                                        continue;
+                                }
+                                 */
+                                status &= info->read_status_mask;
+                
+                                if (status & (BD_SC_BR)) {
+#ifdef SERIAL_DEBUG_INTR
+                                        printk("handling break....");
+#endif
+                                        *tty->flip.flag_buf_ptr = TTY_BREAK;
+                                        if (info->flags & ASYNC_SAK)
+                                                do_SAK(tty);
+                                } else if (status & BD_SC_PR)
+                                        flag = TTY_PARITY;
+                                else if (status & BD_SC_FR)
+                                        flag = TTY_FRAME;
+                        }
+                        tty_insert_flip_char(tty, ch, flag);
+                        if (status & BD_SC_OV)
+                                /*
+                                 * Overrun is special, since it's
+                                 * reported immediately, and doesn't
+                                 * affect the current character
+                                 */
+                                tty_insert_flip_char(tty, 0, TTY_OVERRUN);
+                }
+
+                /* This BD is ready to be used again.  Clear status.
+                 * Get next BD.
+                 */
+                bdp->status |= BD_SC_EMPTY;
+                bdp->status &= ~(BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV);
+
+                if (bdp->status & BD_SC_WRAP)
+                        bdp = info->rx_bd_base;
+                else
+                        bdp++;
+        }
+
+        info->rx_cur = (QUICC_BD *)bdp;
+
+        tty_schedule_flip(tty);
+}
+
+static _INLINE_ void receive_break(ser_info_t *info)
+{
+        struct tty_struct *tty = info->port.tty;
+
+        info->state->icount.brk++;
+        /* Check to see if there is room in the tty buffer for
+         * the break.  If not, we exit now, losing the break.  FIXME
+         */
+        tty_insert_flip_char(tty, 0, TTY_BREAK);
+        tty_schedule_flip(tty);
+}
+
+static _INLINE_ void transmit_chars(ser_info_t *info)
+{
+
+        if ((info->flags & TX_WAKEUP) ||
+            (info->port.tty->flags & (1 << TTY_DO_WRITE_WAKEUP))) {
+                schedule_work(&info->tqueue);
+        }
+
+#ifdef SERIAL_DEBUG_INTR
+        printk("THRE...");
+#endif
+}
+
+#ifdef notdef
+        /* I need to do this for the SCCs, so it is left as a reminder.
+        */
+static _INLINE_ void check_modem_status(struct async_struct *info)
+{
+        int     status;
+        /* struct       async_icount *icount; */
+        struct  async_icount_24 *icount;
+        
+        status = serial_in(info, UART_MSR);
+
+        if (status & UART_MSR_ANY_DELTA) {
+                icount = &info->state->icount;
+                /* update input line counters */
+                if (status & UART_MSR_TERI)
+                        icount->rng++;
+                if (status & UART_MSR_DDSR)
+                        icount->dsr++;
+                if (status & UART_MSR_DDCD) {
+                        icount->dcd++;
+#ifdef CONFIG_HARD_PPS
+                        if ((info->flags & ASYNC_HARDPPS_CD) &&
+                            (status & UART_MSR_DCD))
+                                hardpps();
+#endif
+                }
+                if (status & UART_MSR_DCTS)
+                        icount->cts++;
+                wake_up_interruptible(&info->delta_msr_wait);
+        }
+
+        if ((info->flags & ASYNC_CHECK_CD) && (status & UART_MSR_DDCD)) {
+#if (defined(SERIAL_DEBUG_OPEN) || defined(SERIAL_DEBUG_INTR))
+                printk("ttys%d CD now %s...", info->line,
+                       (status & UART_MSR_DCD) ? "on" : "off");
+#endif          
+                if (status & UART_MSR_DCD)
+                        wake_up_interruptible(&info->open_wait);
+                else {
+#ifdef SERIAL_DEBUG_OPEN
+                        printk("scheduling hangup...");
+#endif
+                        queue_task(&info->tqueue_hangup,
+                                           &tq_scheduler);
+                }
+        }
+        if (info->flags & ASYNC_CTS_FLOW) {
+                if (info->port.tty->hw_stopped) {
+                        if (status & UART_MSR_CTS) {
+#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW))
+                                printk("CTS tx start...");
+#endif
+                                info->port.tty->hw_stopped = 0;
+                                info->IER |= UART_IER_THRI;
+                                serial_out(info, UART_IER, info->IER);
+                                rs_sched_event(info, RS_EVENT_WRITE_WAKEUP);
+                                return;
+                        }
+                } else {
+                        if (!(status & UART_MSR_CTS)) {
+#if (defined(SERIAL_DEBUG_INTR) || defined(SERIAL_DEBUG_FLOW))
+                                printk("CTS tx stop...");
+#endif
+                                info->port.tty->hw_stopped = 1;
+                                info->IER &= ~UART_IER_THRI;
+                                serial_out(info, UART_IER, info->IER);
+                        }
+                }
+        }
+}
+#endif
+
+/*
+ * This is the serial driver's interrupt routine for a single port
+ */
+/* static void rs_360_interrupt(void *dev_id) */ /* until and if we start servicing irqs here */
+static void rs_360_interrupt(int vec, void *dev_id)
+{
+        u_char  events;
+        int     idx;
+        ser_info_t *info;
+        volatile struct smc_regs *smcp;
+        volatile struct scc_regs *sccp;
+        
+        info = dev_id;
+
+        idx = PORT_NUM(info->state->smc_scc_num);
+        if (info->state->smc_scc_num & NUM_IS_SCC) {
+                sccp = &pquicc->scc_regs[idx];
+                events = sccp->scc_scce;
+                if (events & SCCM_RX)
+                        receive_chars(info);
+                if (events & SCCM_TX)
+                        transmit_chars(info);
+                sccp->scc_scce = events;
+        } else {
+                smcp = &pquicc->smc_regs[idx];
+                events = smcp->smc_smce;
+                if (events & SMCM_BRKE)
+                        receive_break(info);
+                if (events & SMCM_RX)
+                        receive_chars(info);
+                if (events & SMCM_TX)
+                        transmit_chars(info);
+                smcp->smc_smce = events;
+        }
+        
+#ifdef SERIAL_DEBUG_INTR
+        printk("rs_interrupt_single(%d, %x)...",
+                                        info->state->smc_scc_num, events);
+#endif
+#ifdef modem_control
+        check_modem_status(info);
+#endif
+        info->last_active = jiffies;
+#ifdef SERIAL_DEBUG_INTR
+        printk("end.\n");
+#endif
+}
+
+
+/*
+ * -------------------------------------------------------------------
+ * Here ends the serial interrupt routines.
+ * -------------------------------------------------------------------
+ */
+
+
+static void do_softint(void *private_)
+{
+        ser_info_t      *info = (ser_info_t *) private_;
+        struct tty_struct       *tty;
+        
+        tty = info->port.tty;
+        if (!tty)
+                return;
+
+        if (test_and_clear_bit(RS_EVENT_WRITE_WAKEUP, &info->event))
+                tty_wakeup(tty);
+}
+
+
+/*
+ * This routine is called from the scheduler tqueue when the interrupt
+ * routine has signalled that a hangup has occurred.  The path of
+ * hangup processing is:
+ *
+ *      serial interrupt routine -> (scheduler tqueue) ->
+ *      do_serial_hangup() -> tty->hangup() -> rs_hangup()
+ * 
+ */
+static void do_serial_hangup(void *private_)
+{
+        struct async_struct     *info = (struct async_struct *) private_;
+        struct tty_struct       *tty;
+        
+        tty = info->port.tty;
+        if (!tty)
+                return;
+
+        tty_hangup(tty);
+}
+
+
+static int startup(ser_info_t *info)
+{
+        unsigned long flags;
+        int     retval=0;
+        int     idx;
+        /*struct serial_state *state = info->state;*/
+        volatile struct smc_regs *smcp;
+        volatile struct scc_regs *sccp;
+        volatile struct smc_uart_pram   *up;
+        volatile struct uart_pram           *scup;
+
+
+        local_irq_save(flags);
+
+        if (info->flags & ASYNC_INITIALIZED) {
+                goto errout;
+        }
+
+#ifdef maybe
+        if (!state->port || !state->type) {
+                if (info->port.tty)
+                        set_bit(TTY_IO_ERROR, &info->port.tty->flags);
+                goto errout;
+        }
+#endif
+
+#ifdef SERIAL_DEBUG_OPEN
+        printk("starting up ttys%d (irq %d)...", info->line, state->irq);
+#endif
+
+
+#ifdef modem_control
+        info->MCR = 0;
+        if (info->port.tty->termios->c_cflag & CBAUD)
+                info->MCR = UART_MCR_DTR | UART_MCR_RTS;
+#endif
+        
+        if (info->port.tty)
+                clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
+
+        /*
+         * and set the speed of the serial port
+         */
+        change_speed(info);
+
+        idx = PORT_NUM(info->state->smc_scc_num);
+        if (info->state->smc_scc_num & NUM_IS_SCC) {
+                sccp = &pquicc->scc_regs[idx];
+                scup = &pquicc->pram[info->state->port].scc.pscc.u;
+
+                scup->mrblr = RX_BUF_SIZE;
+                scup->max_idl = RX_BUF_SIZE;
+
+                sccp->scc_sccm |= (UART_SCCM_TX | UART_SCCM_RX);
+                sccp->scc_gsmr.w.low |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+
+        } else {
+                smcp = &pquicc->smc_regs[idx];
+
+                /* Enable interrupts and I/O.
+                */
+                smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
+                smcp->smc_smcmr |= (SMCMR_REN | SMCMR_TEN);
+
+                /* We can tune the buffer length and idle characters
+                 * to take advantage of the entire incoming buffer size.
+                 * If mrblr is something other than 1, maxidl has to be
+                 * non-zero or we never get an interrupt.  The maxidl
+                 * is the number of character times we wait after reception
+                 * of the last character before we decide no more characters
+                 * are coming.
+                 */
+                /* up = (smc_uart_t *)&pquicc->cp_dparam[state->port]; */
+                /* holy unionized structures, Batman: */
+                up = &pquicc->pram[info->state->port].scc.pothers.idma_smc.psmc.u;
+
+                up->mrblr = RX_BUF_SIZE;
+                up->max_idl = RX_BUF_SIZE;
+
+                up->brkcr = 1;  /* number of break chars */
+        }
+
+        info->flags |= ASYNC_INITIALIZED;
+        local_irq_restore(flags);
+        return 0;
+        
+errout:
+        local_irq_restore(flags);
+        return retval;
+}
+
+/*
+ * This routine will shutdown a serial port; interrupts are disabled, and
+ * DTR is dropped if the hangup on close termio flag is on.
+ */
+static void shutdown(ser_info_t *info)
+{
+        unsigned long   flags;
+        struct serial_state *state;
+        int             idx;
+        volatile struct smc_regs        *smcp;
+        volatile struct scc_regs        *sccp;
+
+        if (!(info->flags & ASYNC_INITIALIZED))
+                return;
+
+        state = info->state;
+
+#ifdef SERIAL_DEBUG_OPEN
+        printk("Shutting down serial port %d (irq %d)....", info->line,
+               state->irq);
+#endif
+        
+        local_irq_save(flags);
+
+        idx = PORT_NUM(state->smc_scc_num);
+        if (state->smc_scc_num & NUM_IS_SCC) {
+                sccp = &pquicc->scc_regs[idx];
+                sccp->scc_gsmr.w.low &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+#ifdef CONFIG_SERIAL_CONSOLE
+                /* We can't disable the transmitter if this is the
+                 * system console.
+                 */
+                if ((state - rs_table) != CONFIG_SERIAL_CONSOLE_PORT)
+#endif
+                sccp->scc_sccm &= ~(UART_SCCM_TX | UART_SCCM_RX);
+        } else {
+                smcp = &pquicc->smc_regs[idx];
+
+                /* Disable interrupts and I/O.
+                 */
+                smcp->smc_smcm &= ~(SMCM_RX | SMCM_TX);
+#ifdef CONFIG_SERIAL_CONSOLE
+                /* We can't disable the transmitter if this is the
+                 * system console.
+                 */
+                if ((state - rs_table) != CONFIG_SERIAL_CONSOLE_PORT)
+#endif
+                        smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
+        }
+        
+        if (info->port.tty)
+                set_bit(TTY_IO_ERROR, &info->port.tty->flags);
+
+        info->flags &= ~ASYNC_INITIALIZED;
+        local_irq_restore(flags);
+}
+
+/*
+ * This routine is called to set the UART divisor registers to match
+ * the specified baud rate for a serial port.
+ */
+static void change_speed(ser_info_t *info)
+{
+        int     baud_rate;
+        unsigned cflag, cval, scval, prev_mode;
+        int     i, bits, sbits, idx;
+        unsigned long   flags;
+        struct serial_state *state;
+        volatile struct smc_regs        *smcp;
+        volatile struct scc_regs        *sccp;
+
+        if (!info->port.tty || !info->port.tty->termios)
+                return;
+        cflag = info->port.tty->termios->c_cflag;
+
+        state = info->state;
+
+        /* Character length programmed into the mode register is the
+         * sum of: 1 start bit, number of data bits, 0 or 1 parity bit,
+         * 1 or 2 stop bits, minus 1.
+         * The value 'bits' counts this for us.
+         */
+        cval = 0;
+        scval = 0;
+
+        /* byte size and parity */
+        switch (cflag & CSIZE) {
+              case CS5: bits = 5; break;
+              case CS6: bits = 6; break;
+              case CS7: bits = 7; break;
+              case CS8: bits = 8; break;
+              /* Never happens, but GCC is too dumb to figure it out */
+              default:  bits = 8; break;
+        }
+        sbits = bits - 5;
+
+        if (cflag & CSTOPB) {
+                cval |= SMCMR_SL;       /* Two stops */
+                scval |= SCU_PMSR_SL;
+                bits++;
+        }
+        if (cflag & PARENB) {
+                cval |= SMCMR_PEN;
+                scval |= SCU_PMSR_PEN;
+                bits++;
+        }
+        if (!(cflag & PARODD)) {
+                cval |= SMCMR_PM_EVEN;
+                scval |= (SCU_PMSR_REVP | SCU_PMSR_TEVP);
+        }
+
+        /* Determine divisor based on baud rate */
+        i = cflag & CBAUD;
+        if (i >= (sizeof(baud_table)/sizeof(int)))
+                baud_rate = 9600;
+        else
+                baud_rate = baud_table[i];
+
+        info->timeout = (TX_BUF_SIZE*HZ*bits);
+        info->timeout += HZ/50;         /* Add .02 seconds of slop */
+
+#ifdef modem_control
+        /* CTS flow control flag and modem status interrupts */
+        info->IER &= ~UART_IER_MSI;
+        if (info->flags & ASYNC_HARDPPS_CD)
+                info->IER |= UART_IER_MSI;
+        if (cflag & CRTSCTS) {
+                info->flags |= ASYNC_CTS_FLOW;
+                info->IER |= UART_IER_MSI;
+        } else
+                info->flags &= ~ASYNC_CTS_FLOW;
+        if (cflag & CLOCAL)
+                info->flags &= ~ASYNC_CHECK_CD;
+        else {
+                info->flags |= ASYNC_CHECK_CD;
+                info->IER |= UART_IER_MSI;
+        }
+        serial_out(info, UART_IER, info->IER);
+#endif
+
+        /*
+         * Set up parity check flag
+         */
+        info->read_status_mask = (BD_SC_EMPTY | BD_SC_OV);
+        if (I_INPCK(info->port.tty))
+                info->read_status_mask |= BD_SC_FR | BD_SC_PR;
+        if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
+                info->read_status_mask |= BD_SC_BR;
+        
+        /*
+         * Characters to ignore
+         */
+        info->ignore_status_mask = 0;
+        if (I_IGNPAR(info->port.tty))
+                info->ignore_status_mask |= BD_SC_PR | BD_SC_FR;
+        if (I_IGNBRK(info->port.tty)) {
+                info->ignore_status_mask |= BD_SC_BR;
+                /*
+                 * If we're ignore parity and break indicators, ignore 
+                 * overruns too.  (For real raw support).
+                 */
+                if (I_IGNPAR(info->port.tty))
+                        info->ignore_status_mask |= BD_SC_OV;
+        }
+        /*
+         * !!! ignore all characters if CREAD is not set
+         */
+        if ((cflag & CREAD) == 0)
+         info->read_status_mask &= ~BD_SC_EMPTY;
+         local_irq_save(flags);
+
+         /* Start bit has not been added (so don't, because we would just
+          * subtract it later), and we need to add one for the number of
+          * stops bits (there is always at least one).
+          */
+         bits++;
+         idx = PORT_NUM(state->smc_scc_num);
+         if (state->smc_scc_num & NUM_IS_SCC) {
+         sccp = &pquicc->scc_regs[idx];
+         sccp->scc_psmr = (sbits << 12) | scval;
+     } else {
+         smcp = &pquicc->smc_regs[idx];
+
+                /* Set the mode register.  We want to keep a copy of the
+                 * enables, because we want to put them back if they were
+                 * present.
+                 */
+                prev_mode = smcp->smc_smcmr;
+                smcp->smc_smcmr = smcr_mk_clen(bits) | cval |  SMCMR_SM_UART;
+                smcp->smc_smcmr |= (prev_mode & (SMCMR_REN | SMCMR_TEN));
+        }
+
+        m360_cpm_setbrg((state - rs_table), baud_rate);
+
+        local_irq_restore(flags);
+}
+
+static void rs_360_put_char(struct tty_struct *tty, unsigned char ch)
+{
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+        volatile QUICC_BD       *bdp;
+
+        if (serial_paranoia_check(info, tty->name, "rs_put_char"))
+                return 0;
+
+        if (!tty)
+                return 0;
+
+        bdp = info->tx_cur;
+        while (bdp->status & BD_SC_READY);
+
+        /* *((char *)__va(bdp->buf)) = ch; */
+        *((char *)bdp->buf) = ch;
+        bdp->length = 1;
+        bdp->status |= BD_SC_READY;
+
+        /* Get next BD.
+        */
+        if (bdp->status & BD_SC_WRAP)
+                bdp = info->tx_bd_base;
+        else
+                bdp++;
+
+        info->tx_cur = (QUICC_BD *)bdp;
+        return 1;
+
+}
+
+static int rs_360_write(struct tty_struct * tty,
+                    const unsigned char *buf, int count)
+{
+        int     c, ret = 0;
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+        volatile QUICC_BD *bdp;
+
+#ifdef CONFIG_KGDB
+        /* Try to let stub handle output. Returns true if it did. */ 
+        if (kgdb_output_string(buf, count))
+                return ret;
+#endif
+
+        if (serial_paranoia_check(info, tty->name, "rs_write"))
+                return 0;
+
+        if (!tty) 
+                return 0;
+
+        bdp = info->tx_cur;
+
+        while (1) {
+                c = min(count, TX_BUF_SIZE);
+
+                if (c <= 0)
+                        break;
+
+                if (bdp->status & BD_SC_READY) {
+                        info->flags |= TX_WAKEUP;
+                        break;
+                }
+
+                /* memcpy(__va(bdp->buf), buf, c); */
+                memcpy((void *)bdp->buf, buf, c);
+
+                bdp->length = c;
+                bdp->status |= BD_SC_READY;
+
+                buf += c;
+                count -= c;
+                ret += c;
+
+                /* Get next BD.
+                */
+                if (bdp->status & BD_SC_WRAP)
+                        bdp = info->tx_bd_base;
+                else
+                        bdp++;
+                info->tx_cur = (QUICC_BD *)bdp;
+        }
+        return ret;
+}
+
+static int rs_360_write_room(struct tty_struct *tty)
+{
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+        int     ret;
+
+        if (serial_paranoia_check(info, tty->name, "rs_write_room"))
+                return 0;
+
+        if ((info->tx_cur->status & BD_SC_READY) == 0) {
+                info->flags &= ~TX_WAKEUP;
+                ret = TX_BUF_SIZE;
+        }
+        else {
+                info->flags |= TX_WAKEUP;
+                ret = 0;
+        }
+        return ret;
+}
+
+/* I could track this with transmit counters....maybe later.
+*/
+static int rs_360_chars_in_buffer(struct tty_struct *tty)
+{
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+                                
+        if (serial_paranoia_check(info, tty->name, "rs_chars_in_buffer"))
+                return 0;
+        return 0;
+}
+
+static void rs_360_flush_buffer(struct tty_struct *tty)
+{
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+                                
+        if (serial_paranoia_check(info, tty->name, "rs_flush_buffer"))
+                return;
+
+        /* There is nothing to "flush", whatever we gave the CPM
+         * is on its way out.
+         */
+        tty_wakeup(tty);
+        info->flags &= ~TX_WAKEUP;
+}
+
+/*
+ * This function is used to send a high-priority XON/XOFF character to
+ * the device
+ */
+static void rs_360_send_xchar(struct tty_struct *tty, char ch)
+{
+        volatile QUICC_BD       *bdp;
+
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+
+        if (serial_paranoia_check(info, tty->name, "rs_send_char"))
+                return;
+
+        bdp = info->tx_cur;
+        while (bdp->status & BD_SC_READY);
+
+        /* *((char *)__va(bdp->buf)) = ch; */
+        *((char *)bdp->buf) = ch;
+        bdp->length = 1;
+        bdp->status |= BD_SC_READY;
+
+        /* Get next BD.
+        */
+        if (bdp->status & BD_SC_WRAP)
+                bdp = info->tx_bd_base;
+        else
+                bdp++;
+
+        info->tx_cur = (QUICC_BD *)bdp;
+}
+
+/*
+ * ------------------------------------------------------------
+ * rs_throttle()
+ * 
+ * This routine is called by the upper-layer tty layer to signal that
+ * incoming characters should be throttled.
+ * ------------------------------------------------------------
+ */
+static void rs_360_throttle(struct tty_struct * tty)
+{
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+#ifdef SERIAL_DEBUG_THROTTLE
+        char    buf[64];
+        
+        printk("throttle %s: %d....\n", _tty_name(tty, buf),
+               tty->ldisc.chars_in_buffer(tty));
+#endif
+
+        if (serial_paranoia_check(info, tty->name, "rs_throttle"))
+                return;
+        
+        if (I_IXOFF(tty))
+                rs_360_send_xchar(tty, STOP_CHAR(tty));
+
+#ifdef modem_control
+        if (tty->termios->c_cflag & CRTSCTS)
+                info->MCR &= ~UART_MCR_RTS;
+
+        local_irq_disable();
+        serial_out(info, UART_MCR, info->MCR);
+        local_irq_enable();
+#endif
+}
+
+static void rs_360_unthrottle(struct tty_struct * tty)
+{
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+#ifdef SERIAL_DEBUG_THROTTLE
+        char    buf[64];
+        
+        printk("unthrottle %s: %d....\n", _tty_name(tty, buf),
+               tty->ldisc.chars_in_buffer(tty));
+#endif
+
+        if (serial_paranoia_check(info, tty->name, "rs_unthrottle"))
+                return;
+        
+        if (I_IXOFF(tty)) {
+                if (info->x_char)
+                        info->x_char = 0;
+                else
+                        rs_360_send_xchar(tty, START_CHAR(tty));
+        }
+#ifdef modem_control
+        if (tty->termios->c_cflag & CRTSCTS)
+                info->MCR |= UART_MCR_RTS;
+        local_irq_disable();
+        serial_out(info, UART_MCR, info->MCR);
+        local_irq_enable();
+#endif
+}
+
+/*
+ * ------------------------------------------------------------
+ * rs_ioctl() and friends
+ * ------------------------------------------------------------
+ */
+
+#ifdef maybe
+/*
+ * get_lsr_info - get line status register info
+ *
+ * Purpose: Let user call ioctl() to get info when the UART physically
+ *          is emptied.  On bus types like RS485, the transmitter must
+ *          release the bus after transmitting. This must be done when
+ *          the transmit shift register is empty, not be done when the
+ *          transmit holding register is empty.  This functionality
+ *          allows an RS485 driver to be written in user space. 
+ */
+static int get_lsr_info(struct async_struct * info, unsigned int *value)
+{
+        unsigned char status;
+        unsigned int result;
+
+        local_irq_disable();
+        status = serial_in(info, UART_LSR);
+        local_irq_enable();
+        result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0);
+        return put_user(result,value);
+}
+#endif
+
+static int rs_360_tiocmget(struct tty_struct *tty)
+{
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+        unsigned int result = 0;
+#ifdef modem_control
+        unsigned char control, status;
+
+        if (serial_paranoia_check(info, tty->name, __func__))
+                return -ENODEV;
+
+        if (tty->flags & (1 << TTY_IO_ERROR))
+                return -EIO;
+
+        control = info->MCR;
+        local_irq_disable();
+        status = serial_in(info, UART_MSR);
+        local_irq_enable();
+        result =  ((control & UART_MCR_RTS) ? TIOCM_RTS : 0)
+                | ((control & UART_MCR_DTR) ? TIOCM_DTR : 0)
+#ifdef TIOCM_OUT1
+                | ((control & UART_MCR_OUT1) ? TIOCM_OUT1 : 0)
+                | ((control & UART_MCR_OUT2) ? TIOCM_OUT2 : 0)
+#endif
+                | ((status  & UART_MSR_DCD) ? TIOCM_CAR : 0)
+                | ((status  & UART_MSR_RI) ? TIOCM_RNG : 0)
+                | ((status  & UART_MSR_DSR) ? TIOCM_DSR : 0)
+                | ((status  & UART_MSR_CTS) ? TIOCM_CTS : 0);
+#endif
+        return result;
+}
+
+static int rs_360_tiocmset(struct tty_struct *tty,
+                           unsigned int set, unsigned int clear)
+{
+#ifdef modem_control
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+        unsigned int arg;
+
+        if (serial_paranoia_check(info, tty->name, __func__))
+                return -ENODEV;
+
+        if (tty->flags & (1 << TTY_IO_ERROR))
+                return -EIO;
+        /* FIXME: locking on info->mcr */
+        if (set & TIOCM_RTS)
+                info->mcr |= UART_MCR_RTS;
+        if (set & TIOCM_DTR)
+                info->mcr |= UART_MCR_DTR;
+        if (clear & TIOCM_RTS)
+                info->MCR &= ~UART_MCR_RTS;
+        if (clear & TIOCM_DTR)
+                info->MCR &= ~UART_MCR_DTR;
+
+#ifdef TIOCM_OUT1
+        if (set & TIOCM_OUT1)
+                info->MCR |= UART_MCR_OUT1;
+        if (set & TIOCM_OUT2)
+                info->MCR |= UART_MCR_OUT2;
+        if (clear & TIOCM_OUT1)
+                info->MCR &= ~UART_MCR_OUT1;
+        if (clear & TIOCM_OUT2)
+                info->MCR &= ~UART_MCR_OUT2;
+#endif
+
+        local_irq_disable();
+        serial_out(info, UART_MCR, info->MCR);
+        local_irq_enable();
+#endif
+        return 0;
+}
+
+/* Sending a break is a two step process on the SMC/SCC.  It is accomplished
+ * by sending a STOP TRANSMIT command followed by a RESTART TRANSMIT
+ * command.  We take advantage of the begin/end functions to make this
+ * happen.
+ */
+static ushort   smc_chan_map[] = {
+        CPM_CR_CH_SMC1,
+        CPM_CR_CH_SMC2
+};
+
+static ushort   scc_chan_map[] = {
+        CPM_CR_CH_SCC1,
+        CPM_CR_CH_SCC2,
+        CPM_CR_CH_SCC3,
+        CPM_CR_CH_SCC4
+};
+
+static void begin_break(ser_info_t *info)
+{
+        volatile QUICC *cp;
+        ushort  chan;
+        int     idx;
+
+        cp = pquicc;
+
+        idx = PORT_NUM(info->state->smc_scc_num);
+        if (info->state->smc_scc_num & NUM_IS_SCC)
+                chan = scc_chan_map[idx];
+        else
+                chan = smc_chan_map[idx];
+
+        cp->cp_cr = mk_cr_cmd(chan, CPM_CR_STOP_TX) | CPM_CR_FLG;
+        while (cp->cp_cr & CPM_CR_FLG);
+}
+
+static void end_break(ser_info_t *info)
+{
+        volatile QUICC *cp;
+        ushort  chan;
+        int idx;
+
+        cp = pquicc;
+
+        idx = PORT_NUM(info->state->smc_scc_num);
+        if (info->state->smc_scc_num & NUM_IS_SCC)
+                chan = scc_chan_map[idx];
+        else
+                chan = smc_chan_map[idx];
+
+        cp->cp_cr = mk_cr_cmd(chan, CPM_CR_RESTART_TX) | CPM_CR_FLG;
+        while (cp->cp_cr & CPM_CR_FLG);
+}
+
+/*
+ * This routine sends a break character out the serial port.
+ */
+static void send_break(ser_info_t *info, unsigned int duration)
+{
+#ifdef SERIAL_DEBUG_SEND_BREAK
+        printk("rs_send_break(%d) jiff=%lu...", duration, jiffies);
+#endif
+        begin_break(info);
+        msleep_interruptible(duration);
+        end_break(info);
+#ifdef SERIAL_DEBUG_SEND_BREAK
+        printk("done jiffies=%lu\n", jiffies);
+#endif
+}
+
+
+/*
+ * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
+ * Return: write counters to the user passed counter struct
+ * NB: both 1->0 and 0->1 transitions are counted except for
+ *     RI where only 0->1 is counted.
+ */
+static int rs_360_get_icount(struct tty_struct *tty,
+                                struct serial_icounter_struct *icount)
+{
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+        struct async_icount cnow;
+
+        local_irq_disable();
+        cnow = info->state->icount;
+        local_irq_enable();
+
+        icount->cts = cnow.cts;
+        icount->dsr = cnow.dsr;
+        icount->rng = cnow.rng;
+        icount->dcd = cnow.dcd;
+
+        return 0;
+}
+
+static int rs_360_ioctl(struct tty_struct *tty,
+                    unsigned int cmd, unsigned long arg)
+{
+        int error;
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+        int retval;
+        struct async_icount cnow; 
+        /* struct async_icount_24 cnow;*/       /* kernel counter temps */
+        struct serial_icounter_struct *p_cuser; /* user space */
+
+        if (serial_paranoia_check(info, tty->name, "rs_ioctl"))
+                return -ENODEV;
+
+        if (cmd != TIOCMIWAIT) {
+                if (tty->flags & (1 << TTY_IO_ERROR))
+                    return -EIO;
+        }
+        
+        switch (cmd) {
+                case TCSBRK:    /* SVID version: non-zero arg --> no break */
+                        retval = tty_check_change(tty);
+                        if (retval)
+                                return retval;
+                        tty_wait_until_sent(tty, 0);
+                        if (signal_pending(current))
+                                return -EINTR;
+                        if (!arg) {
+                                send_break(info, 250);  /* 1/4 second */
+                                if (signal_pending(current))
+                                        return -EINTR;
+                        }
+                        return 0;
+                case TCSBRKP:   /* support for POSIX tcsendbreak() */
+                        retval = tty_check_change(tty);
+                        if (retval)
+                                return retval;
+                        tty_wait_until_sent(tty, 0);
+                        if (signal_pending(current))
+                                return -EINTR;
+                        send_break(info, arg ? arg*100 : 250);
+                        if (signal_pending(current))
+                                return -EINTR;
+                        return 0;
+                case TIOCSBRK:
+                        retval = tty_check_change(tty);
+                        if (retval)
+                                return retval;
+                        tty_wait_until_sent(tty, 0);
+                        begin_break(info);
+                        return 0;
+                case TIOCCBRK:
+                        retval = tty_check_change(tty);
+                        if (retval)
+                                return retval;
+                        end_break(info);
+                        return 0;
+#ifdef maybe
+                case TIOCSERGETLSR: /* Get line status register */
+                        return get_lsr_info(info, (unsigned int *) arg);
+#endif
+                /*
+                 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change
+                 * - mask passed in arg for lines of interest
+                 *   (use |'ed TIOCM_RNG/DSR/CD/CTS for masking)
+                 * Caller should use TIOCGICOUNT to see which one it was
+                 */
+                 case TIOCMIWAIT:
+#ifdef modem_control
+                        local_irq_disable();
+                        /* note the counters on entry */
+                        cprev = info->state->icount;
+                        local_irq_enable();
+                        while (1) {
+                                interruptible_sleep_on(&info->delta_msr_wait);
+                                /* see if a signal did it */
+                                if (signal_pending(current))
+                                        return -ERESTARTSYS;
+                                local_irq_disable();
+                                cnow = info->state->icount; /* atomic copy */
+                                local_irq_enable();
+                                if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr && 
+                                    cnow.dcd == cprev.dcd && cnow.cts == cprev.cts)
+                                        return -EIO; /* no change => error */
+                                if ( ((arg & TIOCM_RNG) && (cnow.rng != cprev.rng)) ||
+                                     ((arg & TIOCM_DSR) && (cnow.dsr != cprev.dsr)) ||
+                                     ((arg & TIOCM_CD)  && (cnow.dcd != cprev.dcd)) ||
+                                     ((arg & TIOCM_CTS) && (cnow.cts != cprev.cts)) ) {
+                                        return 0;
+                                }
+                                cprev = cnow;
+                        }
+                        /* NOTREACHED */
+#else
+                        return 0;
+#endif
+
+
+                default:
+                        return -ENOIOCTLCMD;
+                }
+        return 0;
+}
+
+/* FIX UP modem control here someday......
+*/
+static void rs_360_set_termios(struct tty_struct *tty, struct ktermios *old_termios)
+{
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+
+        change_speed(info);
+
+#ifdef modem_control
+        /* Handle transition to B0 status */
+        if ((old_termios->c_cflag & CBAUD) &&
+            !(tty->termios->c_cflag & CBAUD)) {
+                info->MCR &= ~(UART_MCR_DTR|UART_MCR_RTS);
+                local_irq_disable();
+                serial_out(info, UART_MCR, info->MCR);
+                local_irq_enable();
+        }
+        
+        /* Handle transition away from B0 status */
+        if (!(old_termios->c_cflag & CBAUD) &&
+            (tty->termios->c_cflag & CBAUD)) {
+                info->MCR |= UART_MCR_DTR;
+                if (!tty->hw_stopped ||
+                    !(tty->termios->c_cflag & CRTSCTS)) {
+                        info->MCR |= UART_MCR_RTS;
+                }
+                local_irq_disable();
+                serial_out(info, UART_MCR, info->MCR);
+                local_irq_enable();
+        }
+        
+        /* Handle turning off CRTSCTS */
+        if ((old_termios->c_cflag & CRTSCTS) &&
+            !(tty->termios->c_cflag & CRTSCTS)) {
+                tty->hw_stopped = 0;
+                rs_360_start(tty);
+        }
+#endif
+
+#if 0
+        /*
+         * No need to wake up processes in open wait, since they
+         * sample the CLOCAL flag once, and don't recheck it.
+         * XXX  It's not clear whether the current behavior is correct
+         * or not.  Hence, this may change.....
+         */
+        if (!(old_termios->c_cflag & CLOCAL) &&
+            (tty->termios->c_cflag & CLOCAL))
+                wake_up_interruptible(&info->open_wait);
+#endif
+}
+
+/*
+ * ------------------------------------------------------------
+ * rs_close()
+ * 
+ * This routine is called when the serial port gets closed.  First, we
+ * wait for the last remaining data to be sent.  Then, we unlink its
+ * async structure from the interrupt chain if necessary, and we free
+ * that IRQ if nothing is left in the chain.
+ * ------------------------------------------------------------
+ */
+static void rs_360_close(struct tty_struct *tty, struct file * filp)
+{
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+        /* struct async_state *state; */
+        struct serial_state *state;
+        unsigned long   flags;
+        int             idx;
+        volatile struct smc_regs        *smcp;
+        volatile struct scc_regs        *sccp;
+
+        if (!info || serial_paranoia_check(info, tty->name, "rs_close"))
+                return;
+
+        state = info->state;
+        
+        local_irq_save(flags);
+        
+        if (tty_hung_up_p(filp)) {
+                DBG_CNT("before DEC-hung");
+                local_irq_restore(flags);
+                return;
+        }
+        
+#ifdef SERIAL_DEBUG_OPEN
+        printk("rs_close ttys%d, count = %d\n", info->line, state->count);
+#endif
+        if ((tty->count == 1) && (state->count != 1)) {
+                /*
+                 * Uh, oh.  tty->count is 1, which means that the tty
+                 * structure will be freed.  state->count should always
+                 * be one in these conditions.  If it's greater than
+                 * one, we've got real problems, since it means the
+                 * serial port won't be shutdown.
+                 */
+                printk("rs_close: bad serial port count; tty->count is 1, "
+                       "state->count is %d\n", state->count);
+                state->count = 1;
+        }
+        if (--state->count < 0) {
+                printk("rs_close: bad serial port count for ttys%d: %d\n",
+                       info->line, state->count);
+                state->count = 0;
+        }
+        if (state->count) {
+                DBG_CNT("before DEC-2");
+                local_irq_restore(flags);
+                return;
+        }
+        info->flags |= ASYNC_CLOSING;
+        /*
+         * Now we wait for the transmit buffer to clear; and we notify 
+         * the line discipline to only process XON/XOFF characters.
+         */
+        tty->closing = 1;
+        if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE)
+                tty_wait_until_sent(tty, info->closing_wait);
+        /*
+         * At this point we stop accepting input.  To do this, we
+         * disable the receive line status interrupts, and tell the
+         * interrupt driver to stop checking the data ready bit in the
+         * line status register.
+         */
+        info->read_status_mask &= ~BD_SC_EMPTY;
+        if (info->flags & ASYNC_INITIALIZED) {
+
+                idx = PORT_NUM(info->state->smc_scc_num);
+                if (info->state->smc_scc_num & NUM_IS_SCC) {
+                        sccp = &pquicc->scc_regs[idx];
+                        sccp->scc_sccm &= ~UART_SCCM_RX;
+                        sccp->scc_gsmr.w.low &= ~SCC_GSMRL_ENR;
+                } else {
+                        smcp = &pquicc->smc_regs[idx];
+                        smcp->smc_smcm &= ~SMCM_RX;
+                        smcp->smc_smcmr &= ~SMCMR_REN;
+                }
+                /*
+                 * Before we drop DTR, make sure the UART transmitter
+                 * has completely drained; this is especially
+                 * important if there is a transmit FIFO!
+                 */
+                rs_360_wait_until_sent(tty, info->timeout);
+        }
+        shutdown(info);
+        rs_360_flush_buffer(tty);
+        tty_ldisc_flush(tty);           
+        tty->closing = 0;
+        info->event = 0;
+        info->port.tty = NULL;
+        if (info->blocked_open) {
+                if (info->close_delay) {
+                        msleep_interruptible(jiffies_to_msecs(info->close_delay));
+                }
+                wake_up_interruptible(&info->open_wait);
+        }
+        info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
+        wake_up_interruptible(&info->close_wait);
+        local_irq_restore(flags);
+}
+
+/*
+ * rs_wait_until_sent() --- wait until the transmitter is empty
+ */
+static void rs_360_wait_until_sent(struct tty_struct *tty, int timeout)
+{
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+        unsigned long orig_jiffies, char_time;
+        /*int lsr;*/
+        volatile QUICC_BD *bdp;
+        
+        if (serial_paranoia_check(info, tty->name, "rs_wait_until_sent"))
+                return;
+
+#ifdef maybe
+        if (info->state->type == PORT_UNKNOWN)
+                return;
+#endif
+
+        orig_jiffies = jiffies;
+        /*
+         * Set the check interval to be 1/5 of the estimated time to
+         * send a single character, and make it at least 1.  The check
+         * interval should also be less than the timeout.
+         * 
+         * Note: we have to use pretty tight timings here to satisfy
+         * the NIST-PCTS.
+         */
+        char_time = 1;
+        if (timeout)
+                char_time = min(char_time, (unsigned long)timeout);
+#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
+        printk("In rs_wait_until_sent(%d) check=%lu...", timeout, char_time);
+        printk("jiff=%lu...", jiffies);
+#endif
+
+        /* We go through the loop at least once because we can't tell
+         * exactly when the last character exits the shifter.  There can
+         * be at least two characters waiting to be sent after the buffers
+         * are empty.
+         */
+        do {
+#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
+                printk("lsr = %d (jiff=%lu)...", lsr, jiffies);
+#endif
+/*              current->counter = 0;    make us low-priority */
+                msleep_interruptible(jiffies_to_msecs(char_time));
+                if (signal_pending(current))
+                        break;
+                if (timeout && (time_after(jiffies, orig_jiffies + timeout)))
+                        break;
+                /* The 'tx_cur' is really the next buffer to send.  We
+                 * have to back up to the previous BD and wait for it
+                 * to go.  This isn't perfect, because all this indicates
+                 * is the buffer is available.  There are still characters
+                 * in the CPM FIFO.
+                 */
+                bdp = info->tx_cur;
+                if (bdp == info->tx_bd_base)
+                        bdp += (TX_NUM_FIFO-1);
+                else
+                        bdp--;
+        } while (bdp->status & BD_SC_READY);
+        current->state = TASK_RUNNING;
+#ifdef SERIAL_DEBUG_RS_WAIT_UNTIL_SENT
+        printk("lsr = %d (jiff=%lu)...done\n", lsr, jiffies);
+#endif
+}
+
+/*
+ * rs_hangup() --- called by tty_hangup() when a hangup is signaled.
+ */
+static void rs_360_hangup(struct tty_struct *tty)
+{
+        ser_info_t *info = (ser_info_t *)tty->driver_data;
+        struct serial_state *state = info->state;
+        
+        if (serial_paranoia_check(info, tty->name, "rs_hangup"))
+                return;
+
+        state = info->state;
+        
+        rs_360_flush_buffer(tty);
+        shutdown(info);
+        info->event = 0;
+        state->count = 0;
+        info->flags &= ~ASYNC_NORMAL_ACTIVE;
+        info->port.tty = NULL;
+        wake_up_interruptible(&info->open_wait);
+}
+
+/*
+ * ------------------------------------------------------------
+ * rs_open() and friends
+ * ------------------------------------------------------------
+ */
+static int block_til_ready(struct tty_struct *tty, struct file * filp,
+                           ser_info_t *info)
+{
+#ifdef DO_THIS_LATER
+        DECLARE_WAITQUEUE(wait, current);
+#endif
+        struct serial_state *state = info->state;
+        int             retval;
+        int             do_clocal = 0;
+
+        /*
+         * If the device is in the middle of being closed, then block
+         * until it's done, and then try again.
+         */
+        if (tty_hung_up_p(filp) ||
+            (info->flags & ASYNC_CLOSING)) {
+                if (info->flags & ASYNC_CLOSING)
+                        interruptible_sleep_on(&info->close_wait);
+#ifdef SERIAL_DO_RESTART
+                if (info->flags & ASYNC_HUP_NOTIFY)
+                        return -EAGAIN;
+                else
+                        return -ERESTARTSYS;
+#else
+                return -EAGAIN;
+#endif
+        }
+
+        /*
+         * If non-blocking mode is set, or the port is not enabled,
+         * then make the check up front and then exit.
+         * If this is an SMC port, we don't have modem control to wait
+         * for, so just get out here.
+         */
+        if ((filp->f_flags & O_NONBLOCK) ||
+            (tty->flags & (1 << TTY_IO_ERROR)) ||
+            !(info->state->smc_scc_num & NUM_IS_SCC)) {
+                info->flags |= ASYNC_NORMAL_ACTIVE;
+                return 0;
+        }
+
+        if (tty->termios->c_cflag & CLOCAL)
+                do_clocal = 1;
+        
+        /*
+         * Block waiting for the carrier detect and the line to become
+         * free (i.e., not in use by the callout).  While we are in
+         * this loop, state->count is dropped by one, so that
+         * rs_close() knows when to free things.  We restore it upon
+         * exit, either normal or abnormal.
+         */
+        retval = 0;
+#ifdef DO_THIS_LATER
+        add_wait_queue(&info->open_wait, &wait);
+#ifdef SERIAL_DEBUG_OPEN
+        printk("block_til_ready before block: ttys%d, count = %d\n",
+               state->line, state->count);
+#endif
+        local_irq_disable();
+        if (!tty_hung_up_p(filp)) 
+                state->count--;
+        local_irq_enable();
+        info->blocked_open++;
+        while (1) {
+                local_irq_disable();
+                if (tty->termios->c_cflag & CBAUD)
+                        serial_out(info, UART_MCR,
+                                   serial_inp(info, UART_MCR) |
+                                   (UART_MCR_DTR | UART_MCR_RTS));
+                local_irq_enable();
+                set_current_state(TASK_INTERRUPTIBLE);
+                if (tty_hung_up_p(filp) ||
+                    !(info->flags & ASYNC_INITIALIZED)) {
+#ifdef SERIAL_DO_RESTART
+                        if (info->flags & ASYNC_HUP_NOTIFY)
+                                retval = -EAGAIN;
+                        else
+                                retval = -ERESTARTSYS;  
+#else
+                        retval = -EAGAIN;
+#endif
+                        break;
+                }
+                if (!(info->flags & ASYNC_CLOSING) &&
+                    (do_clocal || (serial_in(info, UART_MSR) &
+                                   UART_MSR_DCD)))
+                        break;
+                if (signal_pending(current)) {
+                        retval = -ERESTARTSYS;
+                        break;
+                }
+#ifdef SERIAL_DEBUG_OPEN
+                printk("block_til_ready blocking: ttys%d, count = %d\n",
+                       info->line, state->count);
+#endif
+                tty_unlock();
+                schedule();
+                tty_lock();
+        }
+        current->state = TASK_RUNNING;
+        remove_wait_queue(&info->open_wait, &wait);
+        if (!tty_hung_up_p(filp))
+                state->count++;
+        info->blocked_open--;
+#ifdef SERIAL_DEBUG_OPEN
+        printk("block_til_ready after blocking: ttys%d, count = %d\n",
+               info->line, state->count);
+#endif
+#endif /* DO_THIS_LATER */
+        if (retval)
+                return retval;
+        info->flags |= ASYNC_NORMAL_ACTIVE;
+        return 0;
+}
+
+static int get_async_struct(int line, ser_info_t **ret_info)
+{
+        struct serial_state *sstate;
+
+        sstate = rs_table + line;
+        if (sstate->info) {
+                sstate->count++;
+                *ret_info = (ser_info_t *)sstate->info;
+                return 0;
+        }
+        else {
+                return -ENOMEM;
+        }
+}
+
+/*
+ * This routine is called whenever a serial port is opened.  It
+ * enables interrupts for a serial port, linking in its async structure into
+ * the IRQ chain.   It also performs the serial-specific
+ * initialization for the tty structure.
+ */
+static int rs_360_open(struct tty_struct *tty, struct file * filp)
+{
+        ser_info_t      *info;
+        int             retval, line;
+
+        line = tty->index;
+        if ((line < 0) || (line >= NR_PORTS))
+                return -ENODEV;
+        retval = get_async_struct(line, &info);
+        if (retval)
+                return retval;
+        if (serial_paranoia_check(info, tty->name, "rs_open"))
+                return -ENODEV;
+
+#ifdef SERIAL_DEBUG_OPEN
+        printk("rs_open %s, count = %d\n", tty->name, info->state->count);
+#endif
+        tty->driver_data = info;
+        info->port.tty = tty;
+
+        /*
+         * Start up serial port
+         */
+        retval = startup(info);
+        if (retval)
+                return retval;
+
+        retval = block_til_ready(tty, filp, info);
+        if (retval) {
+#ifdef SERIAL_DEBUG_OPEN
+                printk("rs_open returning after block_til_ready with %d\n",
+                       retval);
+#endif
+                return retval;
+        }
+
+#ifdef SERIAL_DEBUG_OPEN
+        printk("rs_open %s successful...", tty->name);
+#endif
+        return 0;
+}
+
+/*
+ * /proc fs routines....
+ */
+
+static inline int line_info(char *buf, struct serial_state *state)
+{
+#ifdef notdef
+        struct async_struct *info = state->info, scr_info;
+        char    stat_buf[30], control, status;
+#endif
+        int     ret;
+
+        ret = sprintf(buf, "%d: uart:%s port:%X irq:%d",
+                      state->line,
+                      (state->smc_scc_num & NUM_IS_SCC) ? "SCC" : "SMC",
+                      (unsigned int)(state->port), state->irq);
+
+        if (!state->port || (state->type == PORT_UNKNOWN)) {
+                ret += sprintf(buf+ret, "\n");
+                return ret;
+        }
+
+#ifdef notdef
+        /*
+         * Figure out the current RS-232 lines
+         */
+        if (!info) {
+                info = &scr_info;       /* This is just for serial_{in,out} */
+
+                info->magic = SERIAL_MAGIC;
+                info->port = state->port;
+                info->flags = state->flags;
+                info->quot = 0;
+                info->port.tty = NULL;
+        }
+        local_irq_disable();
+        status = serial_in(info, UART_MSR);
+        control = info ? info->MCR : serial_in(info, UART_MCR);
+        local_irq_enable();
+        
+        stat_buf[0] = 0;
+        stat_buf[1] = 0;
+        if (control & UART_MCR_RTS)
+                strcat(stat_buf, "|RTS");
+        if (status & UART_MSR_CTS)
+                strcat(stat_buf, "|CTS");
+        if (control & UART_MCR_DTR)
+                strcat(stat_buf, "|DTR");
+        if (status & UART_MSR_DSR)
+                strcat(stat_buf, "|DSR");
+        if (status & UART_MSR_DCD)
+                strcat(stat_buf, "|CD");
+        if (status & UART_MSR_RI)
+                strcat(stat_buf, "|RI");
+
+        if (info->quot) {
+                ret += sprintf(buf+ret, " baud:%d",
+                               state->baud_base / info->quot);
+        }
+
+        ret += sprintf(buf+ret, " tx:%d rx:%d",
+                      state->icount.tx, state->icount.rx);
+
+        if (state->icount.frame)
+                ret += sprintf(buf+ret, " fe:%d", state->icount.frame);
+        
+        if (state->icount.parity)
+                ret += sprintf(buf+ret, " pe:%d", state->icount.parity);
+        
+        if (state->icount.brk)
+                ret += sprintf(buf+ret, " brk:%d", state->icount.brk);  
+
+        if (state->icount.overrun)
+                ret += sprintf(buf+ret, " oe:%d", state->icount.overrun);
+
+        /*
+         * Last thing is the RS-232 status lines
+         */
+        ret += sprintf(buf+ret, " %s\n", stat_buf+1);
+#endif
+        return ret;
+}
+
+int rs_360_read_proc(char *page, char **start, off_t off, int count,
+                 int *eof, void *data)
+{
+        int i, len = 0;
+        off_t   begin = 0;
+
+        len += sprintf(page, "serinfo:1.0 driver:%s\n", serial_version);
+        for (i = 0; i < NR_PORTS && len < 4000; i++) {
+                len += line_info(page + len, &rs_table[i]);
+                if (len+begin > off+count)
+                        goto done;
+                if (len+begin < off) {
+                        begin += len;
+                        len = 0;
+                }
+        }
+        *eof = 1;
+done:
+        if (off >= len+begin)
+                return 0;
+        *start = page + (begin-off);
+        return ((count < begin+len-off) ? count : begin+len-off);
+}
+
+/*
+ * ---------------------------------------------------------------------
+ * rs_init() and friends
+ *
+ * rs_init() is called at boot-time to initialize the serial driver.
+ * ---------------------------------------------------------------------
+ */
+
+/*
+ * This routine prints out the appropriate serial driver version
+ * number, and identifies which options were configured into this
+ * driver.
+ */
+static _INLINE_ void show_serial_version(void)
+{
+        printk(KERN_INFO "%s version %s\n", serial_name, serial_version);
+}
+
+
+/*
+ * The serial console driver used during boot.  Note that these names
+ * clash with those found in "serial.c", so we currently can't support
+ * the 16xxx uarts and these at the same time.  I will fix this to become
+ * an indirect function call from tty_io.c (or something).
+ */
+
+#ifdef CONFIG_SERIAL_CONSOLE
+
+/*
+ * Print a string to the serial port trying not to disturb any possible
+ * real use of the port...
+ */
+static void my_console_write(int idx, const char *s,
+                                unsigned count)
+{
+        struct          serial_state    *ser;
+        ser_info_t              *info;
+        unsigned                i;
+        QUICC_BD                *bdp, *bdbase;
+        volatile struct smc_uart_pram   *up;
+        volatile        u_char          *cp;
+
+        ser = rs_table + idx;
+
+
+        /* If the port has been initialized for general use, we have
+         * to use the buffer descriptors allocated there.  Otherwise,
+         * we simply use the single buffer allocated.
+         */
+        if ((info = (ser_info_t *)ser->info) != NULL) {
+                bdp = info->tx_cur;
+                bdbase = info->tx_bd_base;
+        }
+        else {
+                /* Pointer to UART in parameter ram.
+                */
+                /* up = (smc_uart_t *)&cpmp->cp_dparam[ser->port]; */
+                up = &pquicc->pram[ser->port].scc.pothers.idma_smc.psmc.u;
+
+                /* Get the address of the host memory buffer.
+                 */
+                bdp = bdbase = (QUICC_BD *)((uint)pquicc + (uint)up->tbase);
+        }
+
+        /*
+         * We need to gracefully shut down the transmitter, disable
+         * interrupts, then send our bytes out.
+         */
+
+        /*
+         * Now, do each character.  This is not as bad as it looks
+         * since this is a holding FIFO and not a transmitting FIFO.
+         * We could add the complexity of filling the entire transmit
+         * buffer, but we would just wait longer between accesses......
+         */
+        for (i = 0; i < count; i++, s++) {
+                /* Wait for transmitter fifo to empty.
+                 * Ready indicates output is ready, and xmt is doing
+                 * that, not that it is ready for us to send.
+                 */
+                while (bdp->status & BD_SC_READY);
+
+                /* Send the character out.
+                 */
+                cp = bdp->buf;
+                *cp = *s;
+                
+                bdp->length = 1;
+                bdp->status |= BD_SC_READY;
+
+                if (bdp->status & BD_SC_WRAP)
+                        bdp = bdbase;
+                else
+                        bdp++;
+
+                /* if a LF, also do CR... */
+                if (*s == 10) {
+                        while (bdp->status & BD_SC_READY);
+                        /* cp = __va(bdp->buf); */
+                        cp = bdp->buf;
+                        *cp = 13;
+                        bdp->length = 1;
+                        bdp->status |= BD_SC_READY;
+
+                        if (bdp->status & BD_SC_WRAP) {
+                                bdp = bdbase;
+                        }
+                        else {
+                                bdp++;
+                        }
+                }
+        }
+
+        /*
+         * Finally, Wait for transmitter & holding register to empty
+         *  and restore the IER
+         */
+        while (bdp->status & BD_SC_READY);
+
+        if (info)
+                info->tx_cur = (QUICC_BD *)bdp;
+}
+
+static void serial_console_write(struct console *c, const char *s,
+                                unsigned count)
+{
+#ifdef CONFIG_KGDB
+        /* Try to let stub handle output. Returns true if it did. */ 
+        if (kgdb_output_string(s, count))
+                return;
+#endif
+        my_console_write(c->index, s, count);
+}
+
+
+
+/*void console_print_68360(const char *p)
+{
+        const char *cp = p;
+        int i;
+
+        for (i=0;cp[i]!=0;i++);
+
+        serial_console_write (p, i);
+
+        //Comment this if you want to have a strict interrupt-driven output
+        //rs_fair_output();
+
+        return;
+}*/
+
+
+
+
+
+
+#ifdef CONFIG_XMON
+int
+xmon_360_write(const char *s, unsigned count)
+{
+        my_console_write(0, s, count);
+        return(count);
+}
+#endif
+
+#ifdef CONFIG_KGDB
+void
+putDebugChar(char ch)
+{
+        my_console_write(0, &ch, 1);
+}
+#endif
+
+/*
+ * Receive character from the serial port.  This only works well
+ * before the port is initialized for real use.
+ */
+static int my_console_wait_key(int idx, int xmon, char *obuf)
+{
+        struct serial_state             *ser;
+        u_char                  c, *cp;
+        ser_info_t              *info;
+        QUICC_BD                *bdp;
+        volatile struct smc_uart_pram   *up;
+        int                             i;
+
+        ser = rs_table + idx;
+
+        /* Get the address of the host memory buffer.
+         * If the port has been initialized for general use, we must
+         * use information from the port structure.
+         */
+        if ((info = (ser_info_t *)ser->info))
+                bdp = info->rx_cur;
+        else
+                /* bdp = (QUICC_BD *)&cpmp->cp_dpmem[up->smc_rbase]; */
+                bdp = (QUICC_BD *)((uint)pquicc + (uint)up->tbase);
+
+        /* Pointer to UART in parameter ram.
+         */
+        /* up = (smc_uart_t *)&cpmp->cp_dparam[ser->port]; */
+        up = &pquicc->pram[info->state->port].scc.pothers.idma_smc.psmc.u;
+
+        /*
+         * We need to gracefully shut down the receiver, disable
+         * interrupts, then read the input.
+         * XMON just wants a poll.  If no character, return -1, else
+         * return the character.
+         */
+        if (!xmon) {
+                while (bdp->status & BD_SC_EMPTY);
+        }
+        else {
+                if (bdp->status & BD_SC_EMPTY)
+                        return -1;
+        }
+
+        cp = (char *)bdp->buf;
+
+        if (obuf) {
+                i = c = bdp->length;
+                while (i-- > 0)
+                        *obuf++ = *cp++;
+        }
+        else {
+                c = *cp;
+        }
+        bdp->status |= BD_SC_EMPTY;
+
+        if (info) {
+                if (bdp->status & BD_SC_WRAP) {
+                        bdp = info->rx_bd_base;
+                }
+                else {
+                        bdp++;
+                }
+                info->rx_cur = (QUICC_BD *)bdp;
+        }
+
+        return((int)c);
+}
+
+static int serial_console_wait_key(struct console *co)
+{
+        return(my_console_wait_key(co->index, 0, NULL));
+}
+
+#ifdef CONFIG_XMON
+int
+xmon_360_read_poll(void)
+{
+        return(my_console_wait_key(0, 1, NULL));
+}
+
+int
+xmon_360_read_char(void)
+{
+        return(my_console_wait_key(0, 0, NULL));
+}
+#endif
+
+#ifdef CONFIG_KGDB
+static char kgdb_buf[RX_BUF_SIZE], *kgdp;
+static int kgdb_chars;
+
+unsigned char
+getDebugChar(void)
+{
+        if (kgdb_chars <= 0) {
+                kgdb_chars = my_console_wait_key(0, 0, kgdb_buf);
+                kgdp = kgdb_buf;
+        }
+        kgdb_chars--;
+
+        return(*kgdp++);
+}
+
+void kgdb_interruptible(int state)
+{
+}
+void kgdb_map_scc(void)
+{
+        struct          serial_state *ser;
+        uint            mem_addr;
+        volatile        QUICC_BD                *bdp;
+        volatile        smc_uart_t      *up;
+
+        cpmp = (cpm360_t *)&(((immap_t *)IMAP_ADDR)->im_cpm);
+
+        /* To avoid data cache CPM DMA coherency problems, allocate a
+         * buffer in the CPM DPRAM.  This will work until the CPM and
+         * serial ports are initialized.  At that time a memory buffer
+         * will be allocated.
+         * The port is already initialized from the boot procedure, all
+         * we do here is give it a different buffer and make it a FIFO.
+         */
+
+        ser = rs_table;
+
+        /* Right now, assume we are using SMCs.
+        */
+        up = (smc_uart_t *)&cpmp->cp_dparam[ser->port];
+
+        /* Allocate space for an input FIFO, plus a few bytes for output.
+         * Allocate bytes to maintain word alignment.
+         */
+        mem_addr = (uint)(&cpmp->cp_dpmem[0x1000]);
+
+        /* Set the physical address of the host memory buffers in
+         * the buffer descriptors.
+         */
+        bdp = (QUICC_BD *)&cpmp->cp_dpmem[up->smc_rbase];
+        bdp->buf = mem_addr;
+
+        bdp = (QUICC_BD *)&cpmp->cp_dpmem[up->smc_tbase];
+        bdp->buf = mem_addr+RX_BUF_SIZE;
+
+        up->smc_mrblr = RX_BUF_SIZE;            /* receive buffer length */
+        up->smc_maxidl = RX_BUF_SIZE;
+}
+#endif
+
+static struct tty_struct *serial_console_device(struct console *c, int *index)
+{
+        *index = c->index;
+        return serial_driver;
+}
+
+
+struct console sercons = {
+        .name           = "ttyS",
+        .write          = serial_console_write,
+        .device         = serial_console_device,
+        .wait_key       = serial_console_wait_key,
+        .setup          = serial_console_setup,
+        .flags          = CON_PRINTBUFFER,
+        .index          = CONFIG_SERIAL_CONSOLE_PORT, 
+};
+
+
+
+/*
+ *      Register console.
+ */
+long console_360_init(long kmem_start, long kmem_end)
+{
+        register_console(&sercons);
+        /*register_console (console_print_68360); - 2.0.38 only required a write
+      function pointer. */
+        return kmem_start;
+}
+
+#endif
+
+/* Index in baud rate table of the default console baud rate.
+*/
+static  int     baud_idx;
+
+static const struct tty_operations rs_360_ops = {
+        .owner = THIS_MODULE,
+        .open = rs_360_open,
+        .close = rs_360_close,
+        .write = rs_360_write,
+        .put_char = rs_360_put_char,
+        .write_room = rs_360_write_room,
+        .chars_in_buffer = rs_360_chars_in_buffer,
+        .flush_buffer = rs_360_flush_buffer,
+        .ioctl = rs_360_ioctl,
+        .throttle = rs_360_throttle,
+        .unthrottle = rs_360_unthrottle,
+        /* .send_xchar = rs_360_send_xchar, */
+        .set_termios = rs_360_set_termios,
+        .stop = rs_360_stop,
+        .start = rs_360_start,
+        .hangup = rs_360_hangup,
+        /* .wait_until_sent = rs_360_wait_until_sent, */
+        /* .read_proc = rs_360_read_proc, */
+        .tiocmget = rs_360_tiocmget,
+        .tiocmset = rs_360_tiocmset,
+        .get_icount = rs_360_get_icount,
+};
+
+static int __init rs_360_init(void)
+{
+        struct serial_state * state;
+        ser_info_t      *info;
+        void       *mem_addr;
+        uint            dp_addr, iobits;
+        int                 i, j, idx;
+        ushort          chan;
+        QUICC_BD        *bdp;
+        volatile        QUICC           *cp;
+        volatile        struct smc_regs *sp;
+        volatile        struct smc_uart_pram    *up;
+        volatile        struct scc_regs *scp;
+        volatile        struct uart_pram        *sup;
+        /* volatile     immap_t         *immap; */
+        
+        serial_driver = alloc_tty_driver(NR_PORTS);
+        if (!serial_driver)
+                return -1;
+
+        show_serial_version();
+
+        serial_driver->name = "ttyS";
+        serial_driver->major = TTY_MAJOR;
+        serial_driver->minor_start = 64;
+        serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
+        serial_driver->subtype = SERIAL_TYPE_NORMAL;
+        serial_driver->init_termios = tty_std_termios;
+        serial_driver->init_termios.c_cflag =
+                baud_idx | CS8 | CREAD | HUPCL | CLOCAL;
+        serial_driver->flags = TTY_DRIVER_REAL_RAW;
+        tty_set_operations(serial_driver, &rs_360_ops);
+        
+        if (tty_register_driver(serial_driver))
+                panic("Couldn't register serial driver\n");
+
+        cp = pquicc;    /* Get pointer to Communication Processor */
+        /* immap = (immap_t *)IMAP_ADDR; */     /* and to internal registers */
+
+
+        /* Configure SCC2, SCC3, and SCC4 instead of port A parallel I/O.
+         */
+        /* The "standard" configuration through the 860.
+        */
+/*      immap->im_ioport.iop_papar |= 0x00fc; */
+/*      immap->im_ioport.iop_padir &= ~0x00fc; */
+/*      immap->im_ioport.iop_paodr &= ~0x00fc; */
+        cp->pio_papar |= 0x00fc;
+        cp->pio_padir &= ~0x00fc;
+        /* cp->pio_paodr &= ~0x00fc; */
+
+
+        /* Since we don't yet do modem control, connect the port C pins
+         * as general purpose I/O.  This will assert CTS and CD for the
+         * SCC ports.
+         */
+        /* FIXME: see 360um p.7-365 and 860um p.34-12 
+         * I can't make sense of these bits - mleslie*/
+/*      immap->im_ioport.iop_pcdir |= 0x03c6; */
+/*      immap->im_ioport.iop_pcpar &= ~0x03c6; */
+
+/*      cp->pio_pcdir |= 0x03c6; */
+/*      cp->pio_pcpar &= ~0x03c6; */
+
+
+
+        /* Connect SCC2 and SCC3 to NMSI.  Connect BRG3 to SCC2 and
+         * BRG4 to SCC3.
+         */
+        cp->si_sicr &= ~0x00ffff00;
+        cp->si_sicr |=  0x001b1200;
+
+#ifdef CONFIG_PP04
+        /* Frequentis PP04 forced to RS-232 until we know better.
+         * Port C 12 and 13 low enables RS-232 on SCC3 and SCC4.
+         */
+        immap->im_ioport.iop_pcdir |= 0x000c;
+        immap->im_ioport.iop_pcpar &= ~0x000c;
+        immap->im_ioport.iop_pcdat &= ~0x000c;
+
+        /* This enables the TX driver.
+        */
+        cp->cp_pbpar &= ~0x6000;
+        cp->cp_pbdat &= ~0x6000;
+#endif
+
+        for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
+                state->magic = SSTATE_MAGIC;
+                state->line = i;
+                state->type = PORT_UNKNOWN;
+                state->custom_divisor = 0;
+                state->close_delay = 5*HZ/10;
+                state->closing_wait = 30*HZ;
+                state->icount.cts = state->icount.dsr = 
+                        state->icount.rng = state->icount.dcd = 0;
+                state->icount.rx = state->icount.tx = 0;
+                state->icount.frame = state->icount.parity = 0;
+                state->icount.overrun = state->icount.brk = 0;
+                printk(KERN_INFO "ttyS%d at irq 0x%02x is an %s\n",
+                       i, (unsigned int)(state->irq),
+                       (state->smc_scc_num & NUM_IS_SCC) ? "SCC" : "SMC");
+
+#ifdef CONFIG_SERIAL_CONSOLE
+                /* If we just printed the message on the console port, and
+                 * we are about to initialize it for general use, we have
+                 * to wait a couple of character times for the CR/NL to
+                 * make it out of the transmit buffer.
+                 */
+                if (i == CONFIG_SERIAL_CONSOLE_PORT)
+                        mdelay(8);
+
+
+/*              idx = PORT_NUM(info->state->smc_scc_num); */
+/*              if (info->state->smc_scc_num & NUM_IS_SCC) */
+/*                      chan = scc_chan_map[idx]; */
+/*              else */
+/*                      chan = smc_chan_map[idx]; */
+
+/*              cp->cp_cr = mk_cr_cmd(chan, CPM_CR_STOP_TX) | CPM_CR_FLG; */
+/*              while (cp->cp_cr & CPM_CR_FLG); */
+
+#endif
+                /* info = kmalloc(sizeof(ser_info_t), GFP_KERNEL); */
+                info = &quicc_ser_info[i];
+                if (info) {
+                        memset (info, 0, sizeof(ser_info_t));
+                        info->magic = SERIAL_MAGIC;
+                        info->line = i;
+                        info->flags = state->flags;
+                        INIT_WORK(&info->tqueue, do_softint, info);
+                        INIT_WORK(&info->tqueue_hangup, do_serial_hangup, info);
+                        init_waitqueue_head(&info->open_wait);
+                        init_waitqueue_head(&info->close_wait);
+                        info->state = state;
+                        state->info = (struct async_struct *)info;
+
+                        /* We need to allocate a transmit and receive buffer
+                         * descriptors from dual port ram, and a character
+                         * buffer area from host mem.
+                         */
+                        dp_addr = m360_cpm_dpalloc(sizeof(QUICC_BD) * RX_NUM_FIFO);
+
+                        /* Allocate space for FIFOs in the host memory.
+                         *  (for now this is from a static array of buffers :(
+                         */
+                        /* mem_addr = m360_cpm_hostalloc(RX_NUM_FIFO * RX_BUF_SIZE); */
+                        /* mem_addr = kmalloc (RX_NUM_FIFO * RX_BUF_SIZE, GFP_BUFFER); */
+                        mem_addr = &rx_buf_pool[i * RX_NUM_FIFO * RX_BUF_SIZE];
+
+                        /* Set the physical address of the host memory
+                         * buffers in the buffer descriptors, and the
+                         * virtual address for us to work with.
+                         */
+                        bdp = (QUICC_BD *)((uint)pquicc + dp_addr);
+                        info->rx_cur = info->rx_bd_base = bdp;
+
+                        /* initialize rx buffer descriptors */
+                        for (j=0; j<(RX_NUM_FIFO-1); j++) {
+                                bdp->buf = &rx_buf_pool[(i * RX_NUM_FIFO + j ) * RX_BUF_SIZE];
+                                bdp->status = BD_SC_EMPTY | BD_SC_INTRPT;
+                                mem_addr += RX_BUF_SIZE;
+                                bdp++;
+                        }
+                        bdp->buf = &rx_buf_pool[(i * RX_NUM_FIFO + j ) * RX_BUF_SIZE];
+                        bdp->status = BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT;
+
+
+                        idx = PORT_NUM(info->state->smc_scc_num);
+                        if (info->state->smc_scc_num & NUM_IS_SCC) {
+
+#if defined (CONFIG_UCQUICC) && 1
+                                /* set the transceiver mode to RS232 */
+                                sipex_mode_bits &= ~(uint)SIPEX_MODE(idx,0x0f); /* clear current mode */
+                                sipex_mode_bits |= (uint)SIPEX_MODE(idx,0x02);
+                                *(uint *)_periph_base = sipex_mode_bits;
+                                /* printk ("sipex bits = 0x%08x\n", sipex_mode_bits); */
+#endif
+                        }
+
+                        dp_addr = m360_cpm_dpalloc(sizeof(QUICC_BD) * TX_NUM_FIFO);
+
+                        /* Allocate space for FIFOs in the host memory.
+                        */
+                        /* mem_addr = m360_cpm_hostalloc(TX_NUM_FIFO * TX_BUF_SIZE); */
+                        /* mem_addr = kmalloc (TX_NUM_FIFO * TX_BUF_SIZE, GFP_BUFFER); */
+                        mem_addr = &tx_buf_pool[i * TX_NUM_FIFO * TX_BUF_SIZE];
+
+                        /* Set the physical address of the host memory
+                         * buffers in the buffer descriptors, and the
+                         * virtual address for us to work with.
+                         */
+                        /* bdp = (QUICC_BD *)&cp->cp_dpmem[dp_addr]; */
+                        bdp = (QUICC_BD *)((uint)pquicc + dp_addr);
+                        info->tx_cur = info->tx_bd_base = (QUICC_BD *)bdp;
+
+                        /* initialize tx buffer descriptors */
+                        for (j=0; j<(TX_NUM_FIFO-1); j++) {
+                                bdp->buf = &tx_buf_pool[(i * TX_NUM_FIFO + j ) * TX_BUF_SIZE];
+                                bdp->status = BD_SC_INTRPT;
+                                mem_addr += TX_BUF_SIZE;
+                                bdp++;
+                        }
+                        bdp->buf = &tx_buf_pool[(i * TX_NUM_FIFO + j ) * TX_BUF_SIZE];
+                        bdp->status = (BD_SC_WRAP | BD_SC_INTRPT);
+
+                        if (info->state->smc_scc_num & NUM_IS_SCC) {
+                                scp = &pquicc->scc_regs[idx];
+                                sup = &pquicc->pram[info->state->port].scc.pscc.u;
+                                sup->rbase = dp_addr;
+                                sup->tbase = dp_addr;
+
+                                /* Set up the uart parameters in the
+                                 * parameter ram.
+                                 */
+                                sup->rfcr = SMC_EB;
+                                sup->tfcr = SMC_EB;
+
+                                /* Set this to 1 for now, so we get single
+                                 * character interrupts.  Using idle character
+                                 * time requires some additional tuning.
+                                 */
+                                sup->mrblr = 1;
+                                sup->max_idl = 0;
+                                sup->brkcr = 1;
+                                sup->parec = 0;
+                                sup->frmer = 0;
+                                sup->nosec = 0;
+                                sup->brkec = 0;
+                                sup->uaddr1 = 0;
+                                sup->uaddr2 = 0;
+                                sup->toseq = 0;
+                                {
+                                        int i;
+                                        for (i=0;i<8;i++)
+                                                sup->cc[i] = 0x8000;
+                                }
+                                sup->rccm = 0xc0ff;
+
+                                /* Send the CPM an initialize command.
+                                */
+                                chan = scc_chan_map[idx];
+
+                                /* execute the INIT RX & TX PARAMS command for this channel. */
+                                cp->cp_cr = mk_cr_cmd(chan, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+                                while (cp->cp_cr & CPM_CR_FLG);
+
+                                /* Set UART mode, 8 bit, no parity, one stop.
+                                 * Enable receive and transmit.
+                                 */
+                                scp->scc_gsmr.w.high = 0;
+                                scp->scc_gsmr.w.low = 
+                                        (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
+
+                                /* Disable all interrupts and clear all pending
+                                 * events.
+                                 */
+                                scp->scc_sccm = 0;
+                                scp->scc_scce = 0xffff;
+                                scp->scc_dsr = 0x7e7e;
+                                scp->scc_psmr = 0x3000;
+
+                                /* If the port is the console, enable Rx and Tx.
+                                */
+#ifdef CONFIG_SERIAL_CONSOLE
+                                if (i == CONFIG_SERIAL_CONSOLE_PORT)
+                                        scp->scc_gsmr.w.low |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+#endif
+                        }
+                        else {
+                                /* Configure SMCs Tx/Rx instead of port B
+                                 * parallel I/O.
+                                 */
+                                up = &pquicc->pram[info->state->port].scc.pothers.idma_smc.psmc.u;
+                                up->rbase = dp_addr;
+
+                                iobits = 0xc0 << (idx * 4);
+                                cp->pip_pbpar |= iobits;
+                                cp->pip_pbdir &= ~iobits;
+                                cp->pip_pbodr &= ~iobits;
+
+
+                                /* Connect the baud rate generator to the
+                                 * SMC based upon index in rs_table.  Also
+                                 * make sure it is connected to NMSI.
+                                 */
+                                cp->si_simode &= ~(0xffff << (idx * 16));
+                                cp->si_simode |= (i << ((idx * 16) + 12));
+
+                                up->tbase = dp_addr;
+
+                                /* Set up the uart parameters in the
+                                 * parameter ram.
+                                 */
+                                up->rfcr = SMC_EB;
+                                up->tfcr = SMC_EB;
+
+                                /* Set this to 1 for now, so we get single
+                                 * character interrupts.  Using idle character
+                                 * time requires some additional tuning.
+                                 */
+                                up->mrblr = 1;
+                                up->max_idl = 0;
+                                up->brkcr = 1;
+
+                                /* Send the CPM an initialize command.
+                                */
+                                chan = smc_chan_map[idx];
+
+                                cp->cp_cr = mk_cr_cmd(chan,
+                                                                          CPM_CR_INIT_TRX) | CPM_CR_FLG;
+#ifdef CONFIG_SERIAL_CONSOLE
+                                if (i == CONFIG_SERIAL_CONSOLE_PORT)
+                                        printk("");
+#endif
+                                while (cp->cp_cr & CPM_CR_FLG);
+
+                                /* Set UART mode, 8 bit, no parity, one stop.
+                                 * Enable receive and transmit.
+                                 */
+                                sp = &cp->smc_regs[idx];
+                                sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
+
+                                /* Disable all interrupts and clear all pending
+                                 * events.
+                                 */
+                                sp->smc_smcm = 0;
+                                sp->smc_smce = 0xff;
+
+                                /* If the port is the console, enable Rx and Tx.
+                                */
+#ifdef CONFIG_SERIAL_CONSOLE
+                                if (i == CONFIG_SERIAL_CONSOLE_PORT)
+                                        sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
+#endif
+                        }
+
+                        /* Install interrupt handler.
+                        */
+                        /* cpm_install_handler(IRQ_MACHSPEC | state->irq, rs_360_interrupt, info);  */
+                        /*request_irq(IRQ_MACHSPEC | state->irq, rs_360_interrupt, */
+                        request_irq(state->irq, rs_360_interrupt,
+                                                IRQ_FLG_LOCK, "ttyS", (void *)info);
+
+                        /* Set up the baud rate generator.
+                        */
+                        m360_cpm_setbrg(i, baud_table[baud_idx]);
+
+                }
+        }
+
+        return 0;
+}
+module_init(rs_360_init);
+
+/* This must always be called before the rs_360_init() function, otherwise
+ * it blows away the port control information.
+ */
+//static int __init serial_console_setup( struct console *co, char *options)
+int serial_console_setup( struct console *co, char *options)
+{
+        struct          serial_state    *ser;
+        uint            mem_addr, dp_addr, bidx, idx, iobits;
+        ushort          chan;
+        QUICC_BD        *bdp;
+        volatile        QUICC                   *cp;
+        volatile        struct smc_regs *sp;
+        volatile        struct scc_regs *scp;
+        volatile        struct smc_uart_pram    *up;
+        volatile        struct uart_pram                *sup;
+
+/* mleslie TODO:
+ * add something to the 68k bootloader to store a desired initial console baud rate */
+
+/*      bd_t                                            *bd; */ /* a board info struct used by EPPC-bug */
+/*      bd = (bd_t *)__res; */
+
+        for (bidx = 0; bidx < (sizeof(baud_table) / sizeof(int)); bidx++)
+         /* if (bd->bi_baudrate == baud_table[bidx]) */
+                if (CONSOLE_BAUDRATE == baud_table[bidx])
+                        break;
+
+        /* co->cflag = CREAD|CLOCAL|bidx|CS8; */
+        baud_idx = bidx;
+
+        ser = rs_table + CONFIG_SERIAL_CONSOLE_PORT;
+
+        cp = pquicc;    /* Get pointer to Communication Processor */
+
+        idx = PORT_NUM(ser->smc_scc_num);
+        if (ser->smc_scc_num & NUM_IS_SCC) {
+
+                /* TODO: need to set up SCC pin assignment etc. here */
+                
+        }
+        else {
+                iobits = 0xc0 << (idx * 4);
+                cp->pip_pbpar |= iobits;
+                cp->pip_pbdir &= ~iobits;
+                cp->pip_pbodr &= ~iobits;
+
+                /* Connect the baud rate generator to the
+                 * SMC based upon index in rs_table.  Also
+                 * make sure it is connected to NMSI.
+                 */
+                cp->si_simode &= ~(0xffff << (idx * 16));
+                cp->si_simode |= (idx << ((idx * 16) + 12));
+        }
+
+        /* When we get here, the CPM has been reset, so we need
+         * to configure the port.
+         * We need to allocate a transmit and receive buffer descriptor
+         * from dual port ram, and a character buffer area from host mem.
+         */
+
+        /* Allocate space for two buffer descriptors in the DP ram.
+        */
+        dp_addr = m360_cpm_dpalloc(sizeof(QUICC_BD) * CONSOLE_NUM_FIFO);
+
+        /* Allocate space for two 2 byte FIFOs in the host memory.
+         */
+        /* mem_addr = m360_cpm_hostalloc(8); */
+        mem_addr = (uint)console_fifos;
+
+
+        /* Set the physical address of the host memory buffers in
+         * the buffer descriptors.
+         */
+        /* bdp = (QUICC_BD *)&cp->cp_dpmem[dp_addr]; */
+        bdp = (QUICC_BD *)((uint)pquicc + dp_addr);
+        bdp->buf = (char *)mem_addr;
+        (bdp+1)->buf = (char *)(mem_addr+4);
+
+        /* For the receive, set empty and wrap.
+         * For transmit, set wrap.
+         */
+        bdp->status = BD_SC_EMPTY | BD_SC_WRAP;
+        (bdp+1)->status = BD_SC_WRAP;
+
+        /* Set up the uart parameters in the parameter ram.
+         */
+        if (ser->smc_scc_num & NUM_IS_SCC) {
+                scp = &cp->scc_regs[idx];
+                /* sup = (scc_uart_t *)&cp->cp_dparam[ser->port]; */
+                sup = &pquicc->pram[ser->port].scc.pscc.u;
+
+                sup->rbase = dp_addr;
+                sup->tbase = dp_addr + sizeof(QUICC_BD);
+
+                /* Set up the uart parameters in the
+                 * parameter ram.
+                 */
+                sup->rfcr = SMC_EB;
+                sup->tfcr = SMC_EB;
+
+                /* Set this to 1 for now, so we get single
+                 * character interrupts.  Using idle character
+                 * time requires some additional tuning.
+                 */
+                sup->mrblr = 1;
+                sup->max_idl = 0;
+                sup->brkcr = 1;
+                sup->parec = 0;
+                sup->frmer = 0;
+                sup->nosec = 0;
+                sup->brkec = 0;
+                sup->uaddr1 = 0;
+                sup->uaddr2 = 0;
+                sup->toseq = 0;
+                {
+                        int i;
+                        for (i=0;i<8;i++)
+                                sup->cc[i] = 0x8000;
+                }
+                sup->rccm = 0xc0ff;
+
+                /* Send the CPM an initialize command.
+                */
+                chan = scc_chan_map[idx];
+
+                cp->cp_cr = mk_cr_cmd(chan, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+                while (cp->cp_cr & CPM_CR_FLG);
+
+                /* Set UART mode, 8 bit, no parity, one stop.
+                 * Enable receive and transmit.
+                 */
+                scp->scc_gsmr.w.high = 0;
+                scp->scc_gsmr.w.low = 
+                        (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
+
+                /* Disable all interrupts and clear all pending
+                 * events.
+                 */
+                scp->scc_sccm = 0;
+                scp->scc_scce = 0xffff;
+                scp->scc_dsr = 0x7e7e;
+                scp->scc_psmr = 0x3000;
+
+                scp->scc_gsmr.w.low |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+
+        }
+        else {
+                /* up = (smc_uart_t *)&cp->cp_dparam[ser->port]; */
+                up = &pquicc->pram[ser->port].scc.pothers.idma_smc.psmc.u;
+
+                up->rbase = dp_addr;    /* Base of receive buffer desc. */
+                up->tbase = dp_addr+sizeof(QUICC_BD);   /* Base of xmt buffer desc. */
+                up->rfcr = SMC_EB;
+                up->tfcr = SMC_EB;
+
+                /* Set this to 1 for now, so we get single character interrupts.
+                */
+                up->mrblr = 1;          /* receive buffer length */
+                up->max_idl = 0;                /* wait forever for next char */
+
+                /* Send the CPM an initialize command.
+                */
+                chan = smc_chan_map[idx];
+                cp->cp_cr = mk_cr_cmd(chan, CPM_CR_INIT_TRX) | CPM_CR_FLG;
+                while (cp->cp_cr & CPM_CR_FLG);
+
+                /* Set UART mode, 8 bit, no parity, one stop.
+                 * Enable receive and transmit.
+                 */
+                sp = &cp->smc_regs[idx];
+                sp->smc_smcmr = smcr_mk_clen(9) |  SMCMR_SM_UART;
+
+                /* And finally, enable Rx and Tx.
+                */
+                sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
+        }
+
+        /* Set up the baud rate generator.
+        */
+        /* m360_cpm_setbrg((ser - rs_table), bd->bi_baudrate); */
+        m360_cpm_setbrg((ser - rs_table), CONSOLE_BAUDRATE);
+
+        return 0;
+}
+
+/*
+ * Local variables:
+ *  c-indent-level: 4
+ *  c-basic-offset: 4
+ *  tab-width: 4
+ * End:
+ */
diff --git a/drivers/tty/serial/8250.c b/drivers/tty/serial/8250.c
new file mode 100644
index 00000000000..a3f966b3986
--- /dev/null
+++ b/drivers/tty/serial/8250.c
@@ -0,0 +1,3452 @@
+/*
+ *  Driver for 8250/16550-type serial ports
+ *
+ *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
+ *  Copyright (C) 2001 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * A note about mapbase / membase
+ *
+ *  mapbase is the physical address of the IO port.
+ *  membase is an 'ioremapped' cookie.
+ */
+
+#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/ioport.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/tty.h>
+#include <linux/ratelimit.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_reg.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/nmi.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+
+#include "8250.h"
+
+#ifdef CONFIG_SPARC
+#include "suncore.h"
+#endif
+
+/*
+ * Configuration:
+ *   share_irqs - whether we pass IRQF_SHARED to request_irq().  This option
+ *                is unsafe when used on edge-triggered interrupts.
+ */
+static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
+
+static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
+
+static struct uart_driver serial8250_reg;
+
+static int serial_index(struct uart_port *port)
+{
+        return (serial8250_reg.minor - 64) + port->line;
+}
+
+static unsigned int skip_txen_test; /* force skip of txen test at init time */
+
+/*
+ * Debugging.
+ */
+#if 0
+#define DEBUG_AUTOCONF(fmt...)  printk(fmt)
+#else
+#define DEBUG_AUTOCONF(fmt...)  do { } while (0)
+#endif
+
+#if 0
+#define DEBUG_INTR(fmt...)      printk(fmt)
+#else
+#define DEBUG_INTR(fmt...)      do { } while (0)
+#endif
+
+#define PASS_LIMIT      512
+
+#define BOTH_EMPTY      (UART_LSR_TEMT | UART_LSR_THRE)
+
+
+/*
+ * We default to IRQ0 for the "no irq" hack.   Some
+ * machine types want others as well - they're free
+ * to redefine this in their header file.
+ */
+#define is_real_interrupt(irq)  ((irq) != 0)
+
+#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
+#define CONFIG_SERIAL_DETECT_IRQ 1
+#endif
+#ifdef CONFIG_SERIAL_8250_MANY_PORTS
+#define CONFIG_SERIAL_MANY_PORTS 1
+#endif
+
+/*
+ * HUB6 is always on.  This will be removed once the header
+ * files have been cleaned.
+ */
+#define CONFIG_HUB6 1
+
+#include <asm/serial.h>
+/*
+ * SERIAL_PORT_DFNS tells us about built-in ports that have no
+ * standard enumeration mechanism.   Platforms that can find all
+ * serial ports via mechanisms like ACPI or PCI need not supply it.
+ */
+#ifndef SERIAL_PORT_DFNS
+#define SERIAL_PORT_DFNS
+#endif
+
+static const struct old_serial_port old_serial_port[] = {
+        SERIAL_PORT_DFNS /* defined in asm/serial.h */
+};
+
+#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
+
+#ifdef CONFIG_SERIAL_8250_RSA
+
+#define PORT_RSA_MAX 4
+static unsigned long probe_rsa[PORT_RSA_MAX];
+static unsigned int probe_rsa_count;
+#endif /* CONFIG_SERIAL_8250_RSA  */
+
+struct uart_8250_port {
+        struct uart_port        port;
+        struct timer_list       timer;          /* "no irq" timer */
+        struct list_head        list;           /* ports on this IRQ */
+        unsigned short          capabilities;   /* port capabilities */
+        unsigned short          bugs;           /* port bugs */
+        unsigned int            tx_loadsz;      /* transmit fifo load size */
+        unsigned char           acr;
+        unsigned char           ier;
+        unsigned char           lcr;
+        unsigned char           mcr;
+        unsigned char           mcr_mask;       /* mask of user bits */
+        unsigned char           mcr_force;      /* mask of forced bits */
+        unsigned char           cur_iotype;     /* Running I/O type */
+
+        /*
+         * Some bits in registers are cleared on a read, so they must
+         * be saved whenever the register is read but the bits will not
+         * be immediately processed.
+         */
+#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
+        unsigned char           lsr_saved_flags;
+#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
+        unsigned char           msr_saved_flags;
+};
+
+struct irq_info {
+        struct                  hlist_node node;
+        int                     irq;
+        spinlock_t              lock;   /* Protects list not the hash */
+        struct list_head        *head;
+};
+
+#define NR_IRQ_HASH             32      /* Can be adjusted later */
+static struct hlist_head irq_lists[NR_IRQ_HASH];
+static DEFINE_MUTEX(hash_mutex);        /* Used to walk the hash */
+
+/*
+ * Here we define the default xmit fifo size used for each type of UART.
+ */
+static const struct serial8250_config uart_config[] = {
+        [PORT_UNKNOWN] = {
+                .name           = "unknown",
+                .fifo_size      = 1,
+                .tx_loadsz      = 1,
+        },
+        [PORT_8250] = {
+                .name           = "8250",
+                .fifo_size      = 1,
+                .tx_loadsz      = 1,
+        },
+        [PORT_16450] = {
+                .name           = "16450",
+                .fifo_size      = 1,
+                .tx_loadsz      = 1,
+        },
+        [PORT_16550] = {
+                .name           = "16550",
+                .fifo_size      = 1,
+                .tx_loadsz      = 1,
+        },
+        [PORT_16550A] = {
+                .name           = "16550A",
+                .fifo_size      = 16,
+                .tx_loadsz      = 16,
+                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+                .flags          = UART_CAP_FIFO,
+        },
+        [PORT_CIRRUS] = {
+                .name           = "Cirrus",
+                .fifo_size      = 1,
+                .tx_loadsz      = 1,
+        },
+        [PORT_16650] = {
+                .name           = "ST16650",
+                .fifo_size      = 1,
+                .tx_loadsz      = 1,
+                .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
+        },
+        [PORT_16650V2] = {
+                .name           = "ST16650V2",
+                .fifo_size      = 32,
+                .tx_loadsz      = 16,
+                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
+                                  UART_FCR_T_TRIG_00,
+                .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
+        },
+        [PORT_16750] = {
+                .name           = "TI16750",
+                .fifo_size      = 64,
+                .tx_loadsz      = 64,
+                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
+                                  UART_FCR7_64BYTE,
+                .flags          = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
+        },
+        [PORT_STARTECH] = {
+                .name           = "Startech",
+                .fifo_size      = 1,
+                .tx_loadsz      = 1,
+        },
+        [PORT_16C950] = {
+                .name           = "16C950/954",
+                .fifo_size      = 128,
+                .tx_loadsz      = 128,
+                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+                /* UART_CAP_EFR breaks billionon CF bluetooth card. */
+                .flags          = UART_CAP_FIFO | UART_CAP_SLEEP,
+        },
+        [PORT_16654] = {
+                .name           = "ST16654",
+                .fifo_size      = 64,
+                .tx_loadsz      = 32,
+                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
+                                  UART_FCR_T_TRIG_10,
+                .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
+        },
+        [PORT_16850] = {
+                .name           = "XR16850",
+                .fifo_size      = 128,
+                .tx_loadsz      = 128,
+                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+                .flags          = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
+        },
+        [PORT_RSA] = {
+                .name           = "RSA",
+                .fifo_size      = 2048,
+                .tx_loadsz      = 2048,
+                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
+                .flags          = UART_CAP_FIFO,
+        },
+        [PORT_NS16550A] = {
+                .name           = "NS16550A",
+                .fifo_size      = 16,
+                .tx_loadsz      = 16,
+                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+                .flags          = UART_CAP_FIFO | UART_NATSEMI,
+        },
+        [PORT_XSCALE] = {
+                .name           = "XScale",
+                .fifo_size      = 32,
+                .tx_loadsz      = 32,
+                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+                .flags          = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
+        },
+        [PORT_RM9000] = {
+                .name           = "RM9000",
+                .fifo_size      = 16,
+                .tx_loadsz      = 16,
+                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+                .flags          = UART_CAP_FIFO,
+        },
+        [PORT_OCTEON] = {
+                .name           = "OCTEON",
+                .fifo_size      = 64,
+                .tx_loadsz      = 64,
+                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+                .flags          = UART_CAP_FIFO,
+        },
+        [PORT_AR7] = {
+                .name           = "AR7",
+                .fifo_size      = 16,
+                .tx_loadsz      = 16,
+                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
+                .flags          = UART_CAP_FIFO | UART_CAP_AFE,
+        },
+        [PORT_U6_16550A] = {
+                .name           = "U6_16550A",
+                .fifo_size      = 64,
+                .tx_loadsz      = 64,
+                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
+                .flags          = UART_CAP_FIFO | UART_CAP_AFE,
+        },
+        [PORT_TEGRA] = {
+                .name           = "Tegra",
+                .fifo_size      = 32,
+                .tx_loadsz      = 8,
+                .fcr            = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
+                                  UART_FCR_T_TRIG_01,
+                .flags          = UART_CAP_FIFO | UART_CAP_RTOIE |
+                                  UART_CAP_HW_CTSRTS,
+        },
+};
+
+#if defined(CONFIG_MIPS_ALCHEMY)
+
+/* Au1x00 UART hardware has a weird register layout */
+static const u8 au_io_in_map[] = {
+        [UART_RX]  = 0,
+        [UART_IER] = 2,
+        [UART_IIR] = 3,
+        [UART_LCR] = 5,
+        [UART_MCR] = 6,
+        [UART_LSR] = 7,
+        [UART_MSR] = 8,
+};
+
+static const u8 au_io_out_map[] = {
+        [UART_TX]  = 1,
+        [UART_IER] = 2,
+        [UART_FCR] = 4,
+        [UART_LCR] = 5,
+        [UART_MCR] = 6,
+};
+
+/* sane hardware needs no mapping */
+static inline int map_8250_in_reg(struct uart_port *p, int offset)
+{
+        if (p->iotype != UPIO_AU)
+                return offset;
+        return au_io_in_map[offset];
+}
+
+static inline int map_8250_out_reg(struct uart_port *p, int offset)
+{
+        if (p->iotype != UPIO_AU)
+                return offset;
+        return au_io_out_map[offset];
+}
+
+#elif defined(CONFIG_SERIAL_8250_RM9K)
+
+static const u8
+        regmap_in[8] = {
+                [UART_RX]       = 0x00,
+                [UART_IER]      = 0x0c,
+                [UART_IIR]      = 0x14,
+                [UART_LCR]      = 0x1c,
+                [UART_MCR]      = 0x20,
+                [UART_LSR]      = 0x24,
+                [UART_MSR]      = 0x28,
+                [UART_SCR]      = 0x2c
+        },
+        regmap_out[8] = {
+                [UART_TX]       = 0x04,
+                [UART_IER]      = 0x0c,
+                [UART_FCR]      = 0x18,
+                [UART_LCR]      = 0x1c,
+                [UART_MCR]      = 0x20,
+                [UART_LSR]      = 0x24,
+                [UART_MSR]      = 0x28,
+                [UART_SCR]      = 0x2c
+        };
+
+static inline int map_8250_in_reg(struct uart_port *p, int offset)
+{
+        if (p->iotype != UPIO_RM9000)
+                return offset;
+        return regmap_in[offset];
+}
+
+static inline int map_8250_out_reg(struct uart_port *p, int offset)
+{
+        if (p->iotype != UPIO_RM9000)
+                return offset;
+        return regmap_out[offset];
+}
+
+#else
+
+/* sane hardware needs no mapping */
+#define map_8250_in_reg(up, offset) (offset)
+#define map_8250_out_reg(up, offset) (offset)
+
+#endif
+
+static unsigned int hub6_serial_in(struct uart_port *p, int offset)
+{
+        offset = map_8250_in_reg(p, offset) << p->regshift;
+        outb(p->hub6 - 1 + offset, p->iobase);
+        return inb(p->iobase + 1);
+}
+
+static void hub6_serial_out(struct uart_port *p, int offset, int value)
+{
+        offset = map_8250_out_reg(p, offset) << p->regshift;
+        outb(p->hub6 - 1 + offset, p->iobase);
+        outb(value, p->iobase + 1);
+}
+
+static unsigned int mem_serial_in(struct uart_port *p, int offset)
+{
+        offset = map_8250_in_reg(p, offset) << p->regshift;
+        return readb(p->membase + offset);
+}
+
+static void mem_serial_out(struct uart_port *p, int offset, int value)
+{
+        offset = map_8250_out_reg(p, offset) << p->regshift;
+        writeb(value, p->membase + offset);
+}
+
+static void mem32_serial_out(struct uart_port *p, int offset, int value)
+{
+        offset = map_8250_out_reg(p, offset) << p->regshift;
+        writel(value, p->membase + offset);
+}
+
+static unsigned int mem32_serial_in(struct uart_port *p, int offset)
+{
+        offset = map_8250_in_reg(p, offset) << p->regshift;
+        return readl(p->membase + offset);
+}
+
+static unsigned int au_serial_in(struct uart_port *p, int offset)
+{
+        offset = map_8250_in_reg(p, offset) << p->regshift;
+        return __raw_readl(p->membase + offset);
+}
+
+static void au_serial_out(struct uart_port *p, int offset, int value)
+{
+        offset = map_8250_out_reg(p, offset) << p->regshift;
+        __raw_writel(value, p->membase + offset);
+}
+
+static unsigned int tsi_serial_in(struct uart_port *p, int offset)
+{
+        unsigned int tmp;
+        offset = map_8250_in_reg(p, offset) << p->regshift;
+        if (offset == UART_IIR) {
+                tmp = readl(p->membase + (UART_IIR & ~3));
+                return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
+        } else
+                return readb(p->membase + offset);
+}
+
+static void tsi_serial_out(struct uart_port *p, int offset, int value)
+{
+        offset = map_8250_out_reg(p, offset) << p->regshift;
+        if (!((offset == UART_IER) && (value & UART_IER_UUE)))
+                writeb(value, p->membase + offset);
+}
+
+/* Save the LCR value so it can be re-written when a Busy Detect IRQ occurs. */
+static inline void dwapb_save_out_value(struct uart_port *p, int offset,
+                                        int value)
+{
+        struct uart_8250_port *up =
+                container_of(p, struct uart_8250_port, port);
+
+        if (offset == UART_LCR)
+                up->lcr = value;
+}
+
+/* Read the IER to ensure any interrupt is cleared before returning from ISR. */
+static inline void dwapb_check_clear_ier(struct uart_port *p, int offset)
+{
+        if (offset == UART_TX || offset == UART_IER)
+                p->serial_in(p, UART_IER);
+}
+
+static void dwapb_serial_out(struct uart_port *p, int offset, int value)
+{
+        int save_offset = offset;
+        offset = map_8250_out_reg(p, offset) << p->regshift;
+        dwapb_save_out_value(p, save_offset, value);
+        writeb(value, p->membase + offset);
+        dwapb_check_clear_ier(p, save_offset);
+}
+
+static void dwapb32_serial_out(struct uart_port *p, int offset, int value)
+{
+        int save_offset = offset;
+        offset = map_8250_out_reg(p, offset) << p->regshift;
+        dwapb_save_out_value(p, save_offset, value);
+        writel(value, p->membase + offset);
+        dwapb_check_clear_ier(p, save_offset);
+}
+
+static unsigned int io_serial_in(struct uart_port *p, int offset)
+{
+        offset = map_8250_in_reg(p, offset) << p->regshift;
+        return inb(p->iobase + offset);
+}
+
+static void io_serial_out(struct uart_port *p, int offset, int value)
+{
+        offset = map_8250_out_reg(p, offset) << p->regshift;
+        outb(value, p->iobase + offset);
+}
+
+static void set_io_from_upio(struct uart_port *p)
+{
+        struct uart_8250_port *up =
+                container_of(p, struct uart_8250_port, port);
+        switch (p->iotype) {
+        case UPIO_HUB6:
+                p->serial_in = hub6_serial_in;
+                p->serial_out = hub6_serial_out;
+                break;
+
+        case UPIO_MEM:
+                p->serial_in = mem_serial_in;
+                p->serial_out = mem_serial_out;
+                break;
+
+        case UPIO_RM9000:
+        case UPIO_MEM32:
+                p->serial_in = mem32_serial_in;
+                p->serial_out = mem32_serial_out;
+                break;
+
+        case UPIO_AU:
+                p->serial_in = au_serial_in;
+                p->serial_out = au_serial_out;
+                break;
+
+        case UPIO_TSI:
+                p->serial_in = tsi_serial_in;
+                p->serial_out = tsi_serial_out;
+                break;
+
+        case UPIO_DWAPB:
+                p->serial_in = mem_serial_in;
+                p->serial_out = dwapb_serial_out;
+                break;
+
+        case UPIO_DWAPB32:
+                p->serial_in = mem32_serial_in;
+                p->serial_out = dwapb32_serial_out;
+                break;
+
+        default:
+                p->serial_in = io_serial_in;
+                p->serial_out = io_serial_out;
+                break;
+        }
+        /* Remember loaded iotype */
+        up->cur_iotype = p->iotype;
+}
+
+static void
+serial_out_sync(struct uart_8250_port *up, int offset, int value)
+{
+        struct uart_port *p = &up->port;
+        switch (p->iotype) {
+        case UPIO_MEM:
+        case UPIO_MEM32:
+        case UPIO_AU:
+        case UPIO_DWAPB:
+        case UPIO_DWAPB32:
+                p->serial_out(p, offset, value);
+                p->serial_in(p, UART_LCR);      /* safe, no side-effects */
+                break;
+        default:
+                p->serial_out(p, offset, value);
+        }
+}
+
+#define serial_in(up, offset)           \
+        (up->port.serial_in(&(up)->port, (offset)))
+#define serial_out(up, offset, value)   \
+        (up->port.serial_out(&(up)->port, (offset), (value)))
+/*
+ * We used to support using pause I/O for certain machines.  We
+ * haven't supported this for a while, but just in case it's badly
+ * needed for certain old 386 machines, I've left these #define's
+ * in....
+ */
+#define serial_inp(up, offset)          serial_in(up, offset)
+#define serial_outp(up, offset, value)  serial_out(up, offset, value)
+
+/* Uart divisor latch read */
+static inline int _serial_dl_read(struct uart_8250_port *up)
+{
+        return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
+}
+
+/* Uart divisor latch write */
+static inline void _serial_dl_write(struct uart_8250_port *up, int value)
+{
+        serial_outp(up, UART_DLL, value & 0xff);
+        serial_outp(up, UART_DLM, value >> 8 & 0xff);
+}
+
+#if defined(CONFIG_MIPS_ALCHEMY)
+/* Au1x00 haven't got a standard divisor latch */
+static int serial_dl_read(struct uart_8250_port *up)
+{
+        if (up->port.iotype == UPIO_AU)
+                return __raw_readl(up->port.membase + 0x28);
+        else
+                return _serial_dl_read(up);
+}
+
+static void serial_dl_write(struct uart_8250_port *up, int value)
+{
+        if (up->port.iotype == UPIO_AU)
+                __raw_writel(value, up->port.membase + 0x28);
+        else
+                _serial_dl_write(up, value);
+}
+#elif defined(CONFIG_SERIAL_8250_RM9K)
+static int serial_dl_read(struct uart_8250_port *up)
+{
+        return  (up->port.iotype == UPIO_RM9000) ?
+                (((__raw_readl(up->port.membase + 0x10) << 8) |
+                (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
+                _serial_dl_read(up);
+}
+
+static void serial_dl_write(struct uart_8250_port *up, int value)
+{
+        if (up->port.iotype == UPIO_RM9000) {
+                __raw_writel(value, up->port.membase + 0x08);
+                __raw_writel(value >> 8, up->port.membase + 0x10);
+        } else {
+                _serial_dl_write(up, value);
+        }
+}
+#else
+#define serial_dl_read(up) _serial_dl_read(up)
+#define serial_dl_write(up, value) _serial_dl_write(up, value)
+#endif
+
+/*
+ * For the 16C950
+ */
+static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
+{
+        serial_out(up, UART_SCR, offset);
+        serial_out(up, UART_ICR, value);
+}
+
+static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
+{
+        unsigned int value;
+
+        serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
+        serial_out(up, UART_SCR, offset);
+        value = serial_in(up, UART_ICR);
+        serial_icr_write(up, UART_ACR, up->acr);
+
+        return value;
+}
+
+/*
+ * FIFO support.
+ */
+static void serial8250_clear_fifos(struct uart_8250_port *p)
+{
+        if (p->capabilities & UART_CAP_FIFO) {
+                serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
+                serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
+                               UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
+                serial_outp(p, UART_FCR, 0);
+        }
+}
+
+/*
+ * IER sleep support.  UARTs which have EFRs need the "extended
+ * capability" bit enabled.  Note that on XR16C850s, we need to
+ * reset LCR to write to IER.
+ */
+static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
+{
+        if (p->capabilities & UART_CAP_SLEEP) {
+                if (p->capabilities & UART_CAP_EFR) {
+                        serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
+                        serial_outp(p, UART_EFR, UART_EFR_ECB);
+                        serial_outp(p, UART_LCR, 0);
+                }
+                serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
+                if (p->capabilities & UART_CAP_EFR) {
+                        serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
+                        serial_outp(p, UART_EFR, 0);
+                        serial_outp(p, UART_LCR, 0);
+                }
+        }
+}
+
+#ifdef CONFIG_SERIAL_8250_RSA
+/*
+ * Attempts to turn on the RSA FIFO.  Returns zero on failure.
+ * We set the port uart clock rate if we succeed.
+ */
+static int __enable_rsa(struct uart_8250_port *up)
+{
+        unsigned char mode;
+        int result;
+
+        mode = serial_inp(up, UART_RSA_MSR);
+        result = mode & UART_RSA_MSR_FIFO;
+
+        if (!result) {
+                serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
+                mode = serial_inp(up, UART_RSA_MSR);
+                result = mode & UART_RSA_MSR_FIFO;
+        }
+
+        if (result)
+                up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
+
+        return result;
+}
+
+static void enable_rsa(struct uart_8250_port *up)
+{
+        if (up->port.type == PORT_RSA) {
+                if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
+                        spin_lock_irq(&up->port.lock);
+                        __enable_rsa(up);
+                        spin_unlock_irq(&up->port.lock);
+                }
+                if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
+                        serial_outp(up, UART_RSA_FRR, 0);
+        }
+}
+
+/*
+ * Attempts to turn off the RSA FIFO.  Returns zero on failure.
+ * It is unknown why interrupts were disabled in here.  However,
+ * the caller is expected to preserve this behaviour by grabbing
+ * the spinlock before calling this function.
+ */
+static void disable_rsa(struct uart_8250_port *up)
+{
+        unsigned char mode;
+        int result;
+
+        if (up->port.type == PORT_RSA &&
+            up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
+                spin_lock_irq(&up->port.lock);
+
+                mode = serial_inp(up, UART_RSA_MSR);
+                result = !(mode & UART_RSA_MSR_FIFO);
+
+                if (!result) {
+                        serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
+                        mode = serial_inp(up, UART_RSA_MSR);
+                        result = !(mode & UART_RSA_MSR_FIFO);
+                }
+
+                if (result)
+                        up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
+                spin_unlock_irq(&up->port.lock);
+        }
+}
+#endif /* CONFIG_SERIAL_8250_RSA */
+
+/*
+ * This is a quickie test to see how big the FIFO is.
+ * It doesn't work at all the time, more's the pity.
+ */
+static int size_fifo(struct uart_8250_port *up)
+{
+        unsigned char old_fcr, old_mcr, old_lcr;
+        unsigned short old_dl;
+        int count;
+
+        old_lcr = serial_inp(up, UART_LCR);
+        serial_outp(up, UART_LCR, 0);
+        old_fcr = serial_inp(up, UART_FCR);
+        old_mcr = serial_inp(up, UART_MCR);
+        serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
+                    UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
+        serial_outp(up, UART_MCR, UART_MCR_LOOP);
+        serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
+        old_dl = serial_dl_read(up);
+        serial_dl_write(up, 0x0001);
+        serial_outp(up, UART_LCR, 0x03);
+        for (count = 0; count < 256; count++)
+                serial_outp(up, UART_TX, count);
+        mdelay(20);/* FIXME - schedule_timeout */
+        for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
+             (count < 256); count++)
+                serial_inp(up, UART_RX);
+        serial_outp(up, UART_FCR, old_fcr);
+        serial_outp(up, UART_MCR, old_mcr);
+        serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
+        serial_dl_write(up, old_dl);
+        serial_outp(up, UART_LCR, old_lcr);
+
+        return count;
+}
+
+/*
+ * Read UART ID using the divisor method - set DLL and DLM to zero
+ * and the revision will be in DLL and device type in DLM.  We
+ * preserve the device state across this.
+ */
+static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
+{
+        unsigned char old_dll, old_dlm, old_lcr;
+        unsigned int id;
+
+        old_lcr = serial_inp(p, UART_LCR);
+        serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
+
+        old_dll = serial_inp(p, UART_DLL);
+        old_dlm = serial_inp(p, UART_DLM);
+
+        serial_outp(p, UART_DLL, 0);
+        serial_outp(p, UART_DLM, 0);
+
+        id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
+
+        serial_outp(p, UART_DLL, old_dll);
+        serial_outp(p, UART_DLM, old_dlm);
+        serial_outp(p, UART_LCR, old_lcr);
+
+        return id;
+}
+
+/*
+ * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
+ * When this function is called we know it is at least a StarTech
+ * 16650 V2, but it might be one of several StarTech UARTs, or one of
+ * its clones.  (We treat the broken original StarTech 16650 V1 as a
+ * 16550, and why not?  Startech doesn't seem to even acknowledge its
+ * existence.)
+ *
+ * What evil have men's minds wrought...
+ */
+static void autoconfig_has_efr(struct uart_8250_port *up)
+{
+        unsigned int id1, id2, id3, rev;
+
+        /*
+         * Everything with an EFR has SLEEP
+         */
+        up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
+
+        /*
+         * First we check to see if it's an Oxford Semiconductor UART.
+         *
+         * If we have to do this here because some non-National
+         * Semiconductor clone chips lock up if you try writing to the
+         * LSR register (which serial_icr_read does)
+         */
+
+        /*
+         * Check for Oxford Semiconductor 16C950.
+         *
+         * EFR [4] must be set else this test fails.
+         *
+         * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
+         * claims that it's needed for 952 dual UART's (which are not
+         * recommended for new designs).
+         */
+        up->acr = 0;
+        serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
+        serial_out(up, UART_EFR, UART_EFR_ECB);
+        serial_out(up, UART_LCR, 0x00);
+        id1 = serial_icr_read(up, UART_ID1);
+        id2 = serial_icr_read(up, UART_ID2);
+        id3 = serial_icr_read(up, UART_ID3);
+        rev = serial_icr_read(up, UART_REV);
+
+        DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
+
+        if (id1 == 0x16 && id2 == 0xC9 &&
+            (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
+                up->port.type = PORT_16C950;
+
+                /*
+                 * Enable work around for the Oxford Semiconductor 952 rev B
+                 * chip which causes it to seriously miscalculate baud rates
+                 * when DLL is 0.
+                 */
+                if (id3 == 0x52 && rev == 0x01)
+                        up->bugs |= UART_BUG_QUOT;
+                return;
+        }
+
+        /*
+         * We check for a XR16C850 by setting DLL and DLM to 0, and then
+         * reading back DLL and DLM.  The chip type depends on the DLM
+         * value read back:
+         *  0x10 - XR16C850 and the DLL contains the chip revision.
+         *  0x12 - XR16C2850.
+         *  0x14 - XR16C854.
+         */
+        id1 = autoconfig_read_divisor_id(up);
+        DEBUG_AUTOCONF("850id=%04x ", id1);
+
+        id2 = id1 >> 8;
+        if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
+                up->port.type = PORT_16850;
+                return;
+        }
+
+        /*
+         * It wasn't an XR16C850.
+         *
+         * We distinguish between the '654 and the '650 by counting
+         * how many bytes are in the FIFO.  I'm using this for now,
+         * since that's the technique that was sent to me in the
+         * serial driver update, but I'm not convinced this works.
+         * I've had problems doing this in the past.  -TYT
+         */
+        if (size_fifo(up) == 64)
+                up->port.type = PORT_16654;
+        else
+                up->port.type = PORT_16650V2;
+}
+
+/*
+ * We detected a chip without a FIFO.  Only two fall into
+ * this category - the original 8250 and the 16450.  The
+ * 16450 has a scratch register (accessible with LCR=0)
+ */
+static void autoconfig_8250(struct uart_8250_port *up)
+{
+        unsigned char scratch, status1, status2;
+
+        up->port.type = PORT_8250;
+
+        scratch = serial_in(up, UART_SCR);
+        serial_outp(up, UART_SCR, 0xa5);
+        status1 = serial_in(up, UART_SCR);
+        serial_outp(up, UART_SCR, 0x5a);
+        status2 = serial_in(up, UART_SCR);
+        serial_outp(up, UART_SCR, scratch);
+
+        if (status1 == 0xa5 && status2 == 0x5a)
+                up->port.type = PORT_16450;
+}
+
+static int broken_efr(struct uart_8250_port *up)
+{
+        /*
+         * Exar ST16C2550 "A2" devices incorrectly detect as
+         * having an EFR, and report an ID of 0x0201.  See
+         * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html 
+         */
+        if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
+                return 1;
+
+        return 0;
+}
+
+static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
+{
+        unsigned char status;
+
+        status = serial_in(up, 0x04); /* EXCR2 */
+#define PRESL(x) ((x) & 0x30)
+        if (PRESL(status) == 0x10) {
+                /* already in high speed mode */
+                return 0;
+        } else {
+                status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
+                status |= 0x10;  /* 1.625 divisor for baud_base --> 921600 */
+                serial_outp(up, 0x04, status);
+        }
+        return 1;
+}
+
+/*
+ * We know that the chip has FIFOs.  Does it have an EFR?  The
+ * EFR is located in the same register position as the IIR and
+ * we know the top two bits of the IIR are currently set.  The
+ * EFR should contain zero.  Try to read the EFR.
+ */
+static void autoconfig_16550a(struct uart_8250_port *up)
+{
+        unsigned char status1, status2;
+        unsigned int iersave;
+
+        up->port.type = PORT_16550A;
+        up->capabilities |= UART_CAP_FIFO;
+
+        /*
+         * Check for presence of the EFR when DLAB is set.
+         * Only ST16C650V1 UARTs pass this test.
+         */
+        serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
+        if (serial_in(up, UART_EFR) == 0) {
+                serial_outp(up, UART_EFR, 0xA8);
+                if (serial_in(up, UART_EFR) != 0) {
+                        DEBUG_AUTOCONF("EFRv1 ");
+                        up->port.type = PORT_16650;
+                        up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
+                } else {
+                        DEBUG_AUTOCONF("Motorola 8xxx DUART ");
+                }
+                serial_outp(up, UART_EFR, 0);
+                return;
+        }
+
+        /*
+         * Maybe it requires 0xbf to be written to the LCR.
+         * (other ST16C650V2 UARTs, TI16C752A, etc)
+         */
+        serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
+        if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
+                DEBUG_AUTOCONF("EFRv2 ");
+                autoconfig_has_efr(up);
+                return;
+        }
+
+        /*
+         * Check for a National Semiconductor SuperIO chip.
+         * Attempt to switch to bank 2, read the value of the LOOP bit
+         * from EXCR1. Switch back to bank 0, change it in MCR. Then
+         * switch back to bank 2, read it from EXCR1 again and check
+         * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
+         */
+        serial_outp(up, UART_LCR, 0);
+        status1 = serial_in(up, UART_MCR);
+        serial_outp(up, UART_LCR, 0xE0);
+        status2 = serial_in(up, 0x02); /* EXCR1 */
+
+        if (!((status2 ^ status1) & UART_MCR_LOOP)) {
+                serial_outp(up, UART_LCR, 0);
+                serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
+                serial_outp(up, UART_LCR, 0xE0);
+                status2 = serial_in(up, 0x02); /* EXCR1 */
+                serial_outp(up, UART_LCR, 0);
+                serial_outp(up, UART_MCR, status1);
+
+                if ((status2 ^ status1) & UART_MCR_LOOP) {
+                        unsigned short quot;
+
+                        serial_outp(up, UART_LCR, 0xE0);
+
+                        quot = serial_dl_read(up);
+                        quot <<= 3;
+
+                        if (ns16550a_goto_highspeed(up))
+                                serial_dl_write(up, quot);
+
+                        serial_outp(up, UART_LCR, 0);
+
+                        up->port.uartclk = 921600*16;
+                        up->port.type = PORT_NS16550A;
+                        up->capabilities |= UART_NATSEMI;
+                        return;
+                }
+        }
+
+        /*
+         * No EFR.  Try to detect a TI16750, which only sets bit 5 of
+         * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
+         * Try setting it with and without DLAB set.  Cheap clones
+         * set bit 5 without DLAB set.
+         */
+        serial_outp(up, UART_LCR, 0);
+        serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
+        status1 = serial_in(up, UART_IIR) >> 5;
+        serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
+        serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
+        serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
+        status2 = serial_in(up, UART_IIR) >> 5;
+        serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
+        serial_outp(up, UART_LCR, 0);
+
+        DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
+
+        if (status1 == 6 && status2 == 7) {
+                up->port.type = PORT_16750;
+                up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
+                return;
+        }
+
+        /*
+         * Try writing and reading the UART_IER_UUE bit (b6).
+         * If it works, this is probably one of the Xscale platform's
+         * internal UARTs.
+         * We're going to explicitly set the UUE bit to 0 before
+         * trying to write and read a 1 just to make sure it's not
+         * already a 1 and maybe locked there before we even start start.
+         */
+        iersave = serial_in(up, UART_IER);
+        serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
+        if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
+                /*
+                 * OK it's in a known zero state, try writing and reading
+                 * without disturbing the current state of the other bits.
+                 */
+                serial_outp(up, UART_IER, iersave | UART_IER_UUE);
+                if (serial_in(up, UART_IER) & UART_IER_UUE) {
+                        /*
+                         * It's an Xscale.
+                         * We'll leave the UART_IER_UUE bit set to 1 (enabled).
+                         */
+                        DEBUG_AUTOCONF("Xscale ");
+                        up->port.type = PORT_XSCALE;
+                        up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
+                        return;
+                }
+        } else {
+                /*
+                 * If we got here we couldn't force the IER_UUE bit to 0.
+                 * Log it and continue.
+                 */
+                DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
+        }
+        serial_outp(up, UART_IER, iersave);
+
+        /*
+         * We distinguish between 16550A and U6 16550A by counting
+         * how many bytes are in the FIFO.
+         */
+        if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
+                up->port.type = PORT_U6_16550A;
+                up->capabilities |= UART_CAP_AFE;
+        }
+}
+
+/*
+ * This routine is called by rs_init() to initialize a specific serial
+ * port.  It determines what type of UART chip this serial port is
+ * using: 8250, 16450, 16550, 16550A.  The important question is
+ * whether or not this UART is a 16550A or not, since this will
+ * determine whether or not we can use its FIFO features or not.
+ */
+static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
+{
+        unsigned char status1, scratch, scratch2, scratch3;
+        unsigned char save_lcr, save_mcr;
+        unsigned long flags;
+
+        if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
+                return;
+
+        DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
+                       serial_index(&up->port), up->port.iobase, up->port.membase);
+
+        /*
+         * We really do need global IRQs disabled here - we're going to
+         * be frobbing the chips IRQ enable register to see if it exists.
+         */
+        spin_lock_irqsave(&up->port.lock, flags);
+
+        up->capabilities = 0;
+        up->bugs = 0;
+
+        if (!(up->port.flags & UPF_BUGGY_UART)) {
+                /*
+                 * Do a simple existence test first; if we fail this,
+                 * there's no point trying anything else.
+                 *
+                 * 0x80 is used as a nonsense port to prevent against
+                 * false positives due to ISA bus float.  The
+                 * assumption is that 0x80 is a non-existent port;
+                 * which should be safe since include/asm/io.h also
+                 * makes this assumption.
+                 *
+                 * Note: this is safe as long as MCR bit 4 is clear
+                 * and the device is in "PC" mode.
+                 */
+                scratch = serial_inp(up, UART_IER);
+                serial_outp(up, UART_IER, 0);
+#ifdef __i386__
+                outb(0xff, 0x080);
+#endif
+                /*
+                 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
+                 * 16C754B) allow only to modify them if an EFR bit is set.
+                 */
+                scratch2 = serial_inp(up, UART_IER) & 0x0f;
+                serial_outp(up, UART_IER, 0x0F);
+#ifdef __i386__
+                outb(0, 0x080);
+#endif
+                scratch3 = serial_inp(up, UART_IER) & 0x0f;
+                serial_outp(up, UART_IER, scratch);
+                if (scratch2 != 0 || scratch3 != 0x0F) {
+                        /*
+                         * We failed; there's nothing here
+                         */
+                        DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
+                                       scratch2, scratch3);
+                        goto out;
+                }
+        }
+
+        save_mcr = serial_in(up, UART_MCR);
+        save_lcr = serial_in(up, UART_LCR);
+
+        /*
+         * Check to see if a UART is really there.  Certain broken
+         * internal modems based on the Rockwell chipset fail this
+         * test, because they apparently don't implement the loopback
+         * test mode.  So this test is skipped on the COM 1 through
+         * COM 4 ports.  This *should* be safe, since no board
+         * manufacturer would be stupid enough to design a board
+         * that conflicts with COM 1-4 --- we hope!
+         */
+        if (!(up->port.flags & UPF_SKIP_TEST)) {
+                serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
+                status1 = serial_inp(up, UART_MSR) & 0xF0;
+                serial_outp(up, UART_MCR, save_mcr);
+                if (status1 != 0x90) {
+                        DEBUG_AUTOCONF("LOOP test failed (%02x) ",
+                                       status1);
+                        goto out;
+                }
+        }
+
+        /*
+         * We're pretty sure there's a port here.  Lets find out what
+         * type of port it is.  The IIR top two bits allows us to find
+         * out if it's 8250 or 16450, 16550, 16550A or later.  This
+         * determines what we test for next.
+         *
+         * We also initialise the EFR (if any) to zero for later.  The
+         * EFR occupies the same register location as the FCR and IIR.
+         */
+        serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
+        serial_outp(up, UART_EFR, 0);
+        serial_outp(up, UART_LCR, 0);
+
+        serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
+        scratch = serial_in(up, UART_IIR) >> 6;
+
+        DEBUG_AUTOCONF("iir=%d ", scratch);
+
+        switch (scratch) {
+        case 0:
+                autoconfig_8250(up);
+                break;
+        case 1:
+                up->port.type = PORT_UNKNOWN;
+                break;
+        case 2:
+                up->port.type = PORT_16550;
+                break;
+        case 3:
+                autoconfig_16550a(up);
+                break;
+        }
+
+#ifdef CONFIG_SERIAL_8250_RSA
+        /*
+         * Only probe for RSA ports if we got the region.
+         */
+        if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
+                int i;
+
+                for (i = 0 ; i < probe_rsa_count; ++i) {
+                        if (probe_rsa[i] == up->port.iobase &&
+                            __enable_rsa(up)) {
+                                up->port.type = PORT_RSA;
+                                break;
+                        }
+                }
+        }
+#endif
+
+        serial_outp(up, UART_LCR, save_lcr);
+
+        if (up->capabilities != uart_config[up->port.type].flags) {
+                printk(KERN_WARNING
+                       "ttyS%d: detected caps %08x should be %08x\n",
+                       serial_index(&up->port), up->capabilities,
+                       uart_config[up->port.type].flags);
+        }
+
+        up->port.fifosize = uart_config[up->port.type].fifo_size;
+        up->capabilities = uart_config[up->port.type].flags;
+        up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
+
+        if (up->port.type == PORT_UNKNOWN)
+                goto out;
+
+        /*
+         * Reset the UART.
+         */
+#ifdef CONFIG_SERIAL_8250_RSA
+        if (up->port.type == PORT_RSA)
+                serial_outp(up, UART_RSA_FRR, 0);
+#endif
+        serial_outp(up, UART_MCR, save_mcr);
+        serial8250_clear_fifos(up);
+        serial_in(up, UART_RX);
+        if (up->capabilities & UART_CAP_UUE)
+                serial_outp(up, UART_IER, UART_IER_UUE);
+        else
+                serial_outp(up, UART_IER, 0);
+
+ out:
+        spin_unlock_irqrestore(&up->port.lock, flags);
+        DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
+}
+
+static void autoconfig_irq(struct uart_8250_port *up)
+{
+        unsigned char save_mcr, save_ier;
+        unsigned char save_ICP = 0;
+        unsigned int ICP = 0;
+        unsigned long irqs;
+        int irq;
+
+        if (up->port.flags & UPF_FOURPORT) {
+                ICP = (up->port.iobase & 0xfe0) | 0x1f;
+                save_ICP = inb_p(ICP);
+                outb_p(0x80, ICP);
+                (void) inb_p(ICP);
+        }
+
+        /* forget possible initially masked and pending IRQ */
+        probe_irq_off(probe_irq_on());
+        save_mcr = serial_inp(up, UART_MCR);
+        save_ier = serial_inp(up, UART_IER);
+        serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
+
+        irqs = probe_irq_on();
+        serial_outp(up, UART_MCR, 0);
+        udelay(10);
+        if (up->port.flags & UPF_FOURPORT) {
+                serial_outp(up, UART_MCR,
+                            UART_MCR_DTR | UART_MCR_RTS);
+        } else {
+                serial_outp(up, UART_MCR,
+                            UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
+        }
+        serial_outp(up, UART_IER, 0x0f);        /* enable all intrs */
+        (void)serial_inp(up, UART_LSR);
+        (void)serial_inp(up, UART_RX);
+        (void)serial_inp(up, UART_IIR);
+        (void)serial_inp(up, UART_MSR);
+        serial_outp(up, UART_TX, 0xFF);
+        udelay(20);
+        irq = probe_irq_off(irqs);
+
+        serial_outp(up, UART_MCR, save_mcr);
+        serial_outp(up, UART_IER, save_ier);
+
+        if (up->port.flags & UPF_FOURPORT)
+                outb_p(save_ICP, ICP);
+
+        up->port.irq = (irq > 0) ? irq : 0;
+}
+
+static inline void __stop_tx(struct uart_8250_port *p)
+{
+        if (p->ier & UART_IER_THRI) {
+                p->ier &= ~UART_IER_THRI;
+                serial_out(p, UART_IER, p->ier);
+        }
+}
+
+static void serial8250_stop_tx(struct uart_port *port)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+
+        __stop_tx(up);
+
+        /*
+         * We really want to stop the transmitter from sending.
+         */
+        if (up->port.type == PORT_16C950) {
+                up->acr |= UART_ACR_TXDIS;
+                serial_icr_write(up, UART_ACR, up->acr);
+        }
+}
+
+static void transmit_chars(struct uart_8250_port *up);
+
+static void serial8250_start_tx(struct uart_port *port)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+
+        if (!(up->ier & UART_IER_THRI)) {
+                up->ier |= UART_IER_THRI;
+                serial_out(up, UART_IER, up->ier);
+
+                if (up->bugs & UART_BUG_TXEN) {
+                        unsigned char lsr;
+                        lsr = serial_in(up, UART_LSR);
+                        up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
+                        if ((up->port.type == PORT_RM9000) ?
+                                (lsr & UART_LSR_THRE) :
+                                (lsr & UART_LSR_TEMT))
+                                transmit_chars(up);
+                }
+        }
+
+        /*
+         * Re-enable the transmitter if we disabled it.
+         */
+        if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
+                up->acr &= ~UART_ACR_TXDIS;
+                serial_icr_write(up, UART_ACR, up->acr);
+        }
+}
+
+static void serial8250_stop_rx(struct uart_port *port)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+
+        up->ier &= ~UART_IER_RLSI;
+        up->port.read_status_mask &= ~UART_LSR_DR;
+        serial_out(up, UART_IER, up->ier);
+}
+
+static void serial8250_enable_ms(struct uart_port *port)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+
+        /* no MSR capabilities */
+        if (up->bugs & UART_BUG_NOMSR)
+                return;
+
+        up->ier |= UART_IER_MSI;
+        serial_out(up, UART_IER, up->ier);
+}
+
+/*
+ * Clear the Tegra rx fifo after a break
+ *
+ * FIXME: This needs to become a port specific callback once we have a
+ * framework for this
+ */
+static void clear_rx_fifo(struct uart_8250_port *up)
+{
+        unsigned int status, tmout = 10000;
+        do {
+                status = serial_in(up, UART_LSR);
+                if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
+                        status = serial_in(up, UART_RX);
+                else
+                        break;
+                if (--tmout == 0)
+                        break;
+                udelay(1);
+        } while (1);
+}
+
+static void
+receive_chars(struct uart_8250_port *up, unsigned int *status)
+{
+        struct tty_struct *tty = up->port.state->port.tty;
+        unsigned char ch, lsr = *status;
+        int max_count = 256;
+        char flag;
+
+        do {
+                if (likely(lsr & UART_LSR_DR))
+                        ch = serial_inp(up, UART_RX);
+                else
+                        /*
+                         * Intel 82571 has a Serial Over Lan device that will
+                         * set UART_LSR_BI without setting UART_LSR_DR when
+                         * it receives a break. To avoid reading from the
+                         * receive buffer without UART_LSR_DR bit set, we
+                         * just force the read character to be 0
+                         */
+                        ch = 0;
+
+                flag = TTY_NORMAL;
+                up->port.icount.rx++;
+
+                lsr |= up->lsr_saved_flags;
+                up->lsr_saved_flags = 0;
+
+                if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
+                        /*
+                         * For statistics only
+                         */
+                        if (lsr & UART_LSR_BI) {
+                                lsr &= ~(UART_LSR_FE | UART_LSR_PE);
+                                up->port.icount.brk++;
+                                /*
+                                 * If tegra port then clear the rx fifo to
+                                 * accept another break/character.
+                                 */
+                                if (up->port.type == PORT_TEGRA)
+                                        clear_rx_fifo(up);
+
+                                /*
+                                 * We do the SysRQ and SAK checking
+                                 * here because otherwise the break
+                                 * may get masked by ignore_status_mask
+                                 * or read_status_mask.
+                                 */
+                                if (uart_handle_break(&up->port))
+                                        goto ignore_char;
+                        } else if (lsr & UART_LSR_PE)
+                                up->port.icount.parity++;
+                        else if (lsr & UART_LSR_FE)
+                                up->port.icount.frame++;
+                        if (lsr & UART_LSR_OE)
+                                up->port.icount.overrun++;
+
+                        /*
+                         * Mask off conditions which should be ignored.
+                         */
+                        lsr &= up->port.read_status_mask;
+
+                        if (lsr & UART_LSR_BI) {
+                                DEBUG_INTR("handling break....");
+                                flag = TTY_BREAK;
+                        } else if (lsr & UART_LSR_PE)
+                                flag = TTY_PARITY;
+                        else if (lsr & UART_LSR_FE)
+                                flag = TTY_FRAME;
+                }
+                if (uart_handle_sysrq_char(&up->port, ch))
+                        goto ignore_char;
+
+                uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
+
+ignore_char:
+                lsr = serial_inp(up, UART_LSR);
+        } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
+        spin_unlock(&up->port.lock);
+        tty_flip_buffer_push(tty);
+        spin_lock(&up->port.lock);
+        *status = lsr;
+}
+
+static void transmit_chars(struct uart_8250_port *up)
+{
+        struct circ_buf *xmit = &up->port.state->xmit;
+        int count;
+
+        if (up->port.x_char) {
+                serial_outp(up, UART_TX, up->port.x_char);
+                up->port.icount.tx++;
+                up->port.x_char = 0;
+                return;
+        }
+        if (uart_tx_stopped(&up->port)) {
+                serial8250_stop_tx(&up->port);
+                return;
+        }
+        if (uart_circ_empty(xmit)) {
+                __stop_tx(up);
+                return;
+        }
+
+        count = up->tx_loadsz;
+        do {
+                serial_out(up, UART_TX, xmit->buf[xmit->tail]);
+                xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+                up->port.icount.tx++;
+                if (uart_circ_empty(xmit))
+                        break;
+        } while (--count > 0);
+
+        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+                uart_write_wakeup(&up->port);
+
+        DEBUG_INTR("THRE...");
+
+        if (uart_circ_empty(xmit))
+                __stop_tx(up);
+}
+
+static unsigned int check_modem_status(struct uart_8250_port *up)
+{
+        unsigned int status = serial_in(up, UART_MSR);
+
+        status |= up->msr_saved_flags;
+        up->msr_saved_flags = 0;
+        if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
+            up->port.state != NULL) {
+                if (status & UART_MSR_TERI)
+                        up->port.icount.rng++;
+                if (status & UART_MSR_DDSR)
+                        up->port.icount.dsr++;
+                if (status & UART_MSR_DDCD)
+                        uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
+                if (status & UART_MSR_DCTS)
+                        uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
+
+                wake_up_interruptible(&up->port.state->port.delta_msr_wait);
+        }
+
+        return status;
+}
+
+/*
+ * This handles the interrupt from one port.
+ */
+static void serial8250_handle_port(struct uart_8250_port *up)
+{
+        unsigned int status;
+        unsigned long flags;
+
+        spin_lock_irqsave(&up->port.lock, flags);
+
+        status = serial_inp(up, UART_LSR);
+
+        DEBUG_INTR("status = %x...", status);
+
+        if (status & (UART_LSR_DR | UART_LSR_BI))
+                receive_chars(up, &status);
+        check_modem_status(up);
+        if (status & UART_LSR_THRE)
+                transmit_chars(up);
+
+        spin_unlock_irqrestore(&up->port.lock, flags);
+}
+
+/*
+ * This is the serial driver's interrupt routine.
+ *
+ * Arjan thinks the old way was overly complex, so it got simplified.
+ * Alan disagrees, saying that need the complexity to handle the weird
+ * nature of ISA shared interrupts.  (This is a special exception.)
+ *
+ * In order to handle ISA shared interrupts properly, we need to check
+ * that all ports have been serviced, and therefore the ISA interrupt
+ * line has been de-asserted.
+ *
+ * This means we need to loop through all ports. checking that they
+ * don't have an interrupt pending.
+ */
+static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
+{
+        struct irq_info *i = dev_id;
+        struct list_head *l, *end = NULL;
+        int pass_counter = 0, handled = 0;
+
+        DEBUG_INTR("serial8250_interrupt(%d)...", irq);
+
+        spin_lock(&i->lock);
+
+        l = i->head;
+        do {
+                struct uart_8250_port *up;
+                unsigned int iir;
+
+                up = list_entry(l, struct uart_8250_port, list);
+
+                iir = serial_in(up, UART_IIR);
+                if (!(iir & UART_IIR_NO_INT)) {
+                        serial8250_handle_port(up);
+
+                        handled = 1;
+
+                        end = NULL;
+                } else if ((up->port.iotype == UPIO_DWAPB ||
+                            up->port.iotype == UPIO_DWAPB32) &&
+                          (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
+                        /* The DesignWare APB UART has an Busy Detect (0x07)
+                         * interrupt meaning an LCR write attempt occurred while the
+                         * UART was busy. The interrupt must be cleared by reading
+                         * the UART status register (USR) and the LCR re-written. */
+                        unsigned int status;
+                        status = *(volatile u32 *)up->port.private_data;
+                        serial_out(up, UART_LCR, up->lcr);
+
+                        handled = 1;
+
+                        end = NULL;
+                } else if (end == NULL)
+                        end = l;
+
+                l = l->next;
+
+                if (l == i->head && pass_counter++ > PASS_LIMIT) {
+                        /* If we hit this, we're dead. */
+                        printk_ratelimited(KERN_ERR
+                                "serial8250: too much work for irq%d\n", irq);
+                        break;
+                }
+        } while (l != end);
+
+        spin_unlock(&i->lock);
+
+        DEBUG_INTR("end.\n");
+
+        return IRQ_RETVAL(handled);
+}
+
+/*
+ * To support ISA shared interrupts, we need to have one interrupt
+ * handler that ensures that the IRQ line has been deasserted
+ * before returning.  Failing to do this will result in the IRQ
+ * line being stuck active, and, since ISA irqs are edge triggered,
+ * no more IRQs will be seen.
+ */
+static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
+{
+        spin_lock_irq(&i->lock);
+
+        if (!list_empty(i->head)) {
+                if (i->head == &up->list)
+                        i->head = i->head->next;
+                list_del(&up->list);
+        } else {
+                BUG_ON(i->head != &up->list);
+                i->head = NULL;
+        }
+        spin_unlock_irq(&i->lock);
+        /* List empty so throw away the hash node */
+        if (i->head == NULL) {
+                hlist_del(&i->node);
+                kfree(i);
+        }
+}
+
+static int serial_link_irq_chain(struct uart_8250_port *up)
+{
+        struct hlist_head *h;
+        struct hlist_node *n;
+        struct irq_info *i;
+        int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
+
+        mutex_lock(&hash_mutex);
+
+        h = &irq_lists[up->port.irq % NR_IRQ_HASH];
+
+        hlist_for_each(n, h) {
+                i = hlist_entry(n, struct irq_info, node);
+                if (i->irq == up->port.irq)
+                        break;
+        }
+
+        if (n == NULL) {
+                i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
+                if (i == NULL) {
+                        mutex_unlock(&hash_mutex);
+                        return -ENOMEM;
+                }
+                spin_lock_init(&i->lock);
+                i->irq = up->port.irq;
+                hlist_add_head(&i->node, h);
+        }
+        mutex_unlock(&hash_mutex);
+
+        spin_lock_irq(&i->lock);
+
+        if (i->head) {
+                list_add(&up->list, i->head);
+                spin_unlock_irq(&i->lock);
+
+                ret = 0;
+        } else {
+                INIT_LIST_HEAD(&up->list);
+                i->head = &up->list;
+                spin_unlock_irq(&i->lock);
+                irq_flags |= up->port.irqflags;
+                ret = request_irq(up->port.irq, serial8250_interrupt,
+                                  irq_flags, "serial", i);
+                if (ret < 0)
+                        serial_do_unlink(i, up);
+        }
+
+        return ret;
+}
+
+static void serial_unlink_irq_chain(struct uart_8250_port *up)
+{
+        struct irq_info *i;
+        struct hlist_node *n;
+        struct hlist_head *h;
+
+        mutex_lock(&hash_mutex);
+
+        h = &irq_lists[up->port.irq % NR_IRQ_HASH];
+
+        hlist_for_each(n, h) {
+                i = hlist_entry(n, struct irq_info, node);
+                if (i->irq == up->port.irq)
+                        break;
+        }
+
+        BUG_ON(n == NULL);
+        BUG_ON(i->head == NULL);
+
+        if (list_empty(i->head))
+                free_irq(up->port.irq, i);
+
+        serial_do_unlink(i, up);
+        mutex_unlock(&hash_mutex);
+}
+
+/*
+ * This function is used to handle ports that do not have an
+ * interrupt.  This doesn't work very well for 16450's, but gives
+ * barely passable results for a 16550A.  (Although at the expense
+ * of much CPU overhead).
+ */
+static void serial8250_timeout(unsigned long data)
+{
+        struct uart_8250_port *up = (struct uart_8250_port *)data;
+        unsigned int iir;
+
+        iir = serial_in(up, UART_IIR);
+        if (!(iir & UART_IIR_NO_INT))
+                serial8250_handle_port(up);
+        mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
+}
+
+static void serial8250_backup_timeout(unsigned long data)
+{
+        struct uart_8250_port *up = (struct uart_8250_port *)data;
+        unsigned int iir, ier = 0, lsr;
+        unsigned long flags;
+
+        spin_lock_irqsave(&up->port.lock, flags);
+
+        /*
+         * Must disable interrupts or else we risk racing with the interrupt
+         * based handler.
+         */
+        if (is_real_interrupt(up->port.irq)) {
+                ier = serial_in(up, UART_IER);
+                serial_out(up, UART_IER, 0);
+        }
+
+        iir = serial_in(up, UART_IIR);
+
+        /*
+         * This should be a safe test for anyone who doesn't trust the
+         * IIR bits on their UART, but it's specifically designed for
+         * the "Diva" UART used on the management processor on many HP
+         * ia64 and parisc boxes.
+         */
+        lsr = serial_in(up, UART_LSR);
+        up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
+        if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
+            (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
+            (lsr & UART_LSR_THRE)) {
+                iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
+                iir |= UART_IIR_THRI;
+        }
+
+        if (!(iir & UART_IIR_NO_INT))
+                transmit_chars(up);
+
+        if (is_real_interrupt(up->port.irq))
+                serial_out(up, UART_IER, ier);
+
+        spin_unlock_irqrestore(&up->port.lock, flags);
+
+        /* Standard timer interval plus 0.2s to keep the port running */
+        mod_timer(&up->timer,
+                jiffies + uart_poll_timeout(&up->port) + HZ / 5);
+}
+
+static unsigned int serial8250_tx_empty(struct uart_port *port)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+        unsigned long flags;
+        unsigned int lsr;
+
+        spin_lock_irqsave(&up->port.lock, flags);
+        lsr = serial_in(up, UART_LSR);
+        up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
+        spin_unlock_irqrestore(&up->port.lock, flags);
+
+        return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
+}
+
+static unsigned int serial8250_get_mctrl(struct uart_port *port)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+        unsigned int status;
+        unsigned int ret;
+
+        status = check_modem_status(up);
+
+        ret = 0;
+        if (status & UART_MSR_DCD)
+                ret |= TIOCM_CAR;
+        if (status & UART_MSR_RI)
+                ret |= TIOCM_RNG;
+        if (status & UART_MSR_DSR)
+                ret |= TIOCM_DSR;
+        if (status & UART_MSR_CTS)
+                ret |= TIOCM_CTS;
+        return ret;
+}
+
+static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+        unsigned char mcr = 0;
+
+        if (up->port.type == PORT_TEGRA) {
+                if (mctrl & TIOCM_RTS)
+                        mcr |= UART_MCR_HW_RTS;
+        } else {
+                if (mctrl & TIOCM_RTS)
+                        mcr |= UART_MCR_RTS;
+        }
+        if (mctrl & TIOCM_DTR)
+                mcr |= UART_MCR_DTR;
+        if (mctrl & TIOCM_OUT1)
+                mcr |= UART_MCR_OUT1;
+        if (mctrl & TIOCM_OUT2)
+                mcr |= UART_MCR_OUT2;
+        if (mctrl & TIOCM_LOOP)
+                mcr |= UART_MCR_LOOP;
+
+        mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
+
+        serial_out(up, UART_MCR, mcr);
+}
+
+static void serial8250_break_ctl(struct uart_port *port, int break_state)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+        unsigned long flags;
+
+        spin_lock_irqsave(&up->port.lock, flags);
+        if (break_state == -1)
+                up->lcr |= UART_LCR_SBC;
+        else
+                up->lcr &= ~UART_LCR_SBC;
+        serial_out(up, UART_LCR, up->lcr);
+        spin_unlock_irqrestore(&up->port.lock, flags);
+}
+
+/*
+ *      Wait for transmitter & holding register to empty
+ */
+static void wait_for_xmitr(struct uart_8250_port *up, int bits)
+{
+        unsigned int status, tmout = 10000;
+
+        /* Wait up to 10ms for the character(s) to be sent. */
+        for (;;) {
+                status = serial_in(up, UART_LSR);
+
+                up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
+
+                if ((status & bits) == bits)
+                        break;
+                if (--tmout == 0)
+                        break;
+                udelay(1);
+        }
+
+        /* Wait up to 1s for flow control if necessary */
+        if (up->port.flags & UPF_CONS_FLOW) {
+                unsigned int tmout;
+                for (tmout = 1000000; tmout; tmout--) {
+                        unsigned int msr = serial_in(up, UART_MSR);
+                        up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
+                        if (msr & UART_MSR_CTS)
+                                break;
+                        udelay(1);
+                        touch_nmi_watchdog();
+                }
+        }
+}
+
+#ifdef CONFIG_CONSOLE_POLL
+/*
+ * Console polling routines for writing and reading from the uart while
+ * in an interrupt or debug context.
+ */
+
+static int serial8250_get_poll_char(struct uart_port *port)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+        unsigned char lsr = serial_inp(up, UART_LSR);
+
+        if (!(lsr & UART_LSR_DR))
+                return NO_POLL_CHAR;
+
+        return serial_inp(up, UART_RX);
+}
+
+
+static void serial8250_put_poll_char(struct uart_port *port,
+                         unsigned char c)
+{
+        unsigned int ier;
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+
+        /*
+         *      First save the IER then disable the interrupts
+         */
+        ier = serial_in(up, UART_IER);
+        if (up->capabilities & UART_CAP_UUE)
+                serial_out(up, UART_IER, UART_IER_UUE);
+        else
+                serial_out(up, UART_IER, 0);
+
+        wait_for_xmitr(up, BOTH_EMPTY);
+        /*
+         *      Send the character out.
+         *      If a LF, also do CR...
+         */
+        serial_out(up, UART_TX, c);
+        if (c == 10) {
+                wait_for_xmitr(up, BOTH_EMPTY);
+                serial_out(up, UART_TX, 13);
+        }
+
+        /*
+         *      Finally, wait for transmitter to become empty
+         *      and restore the IER
+         */
+        wait_for_xmitr(up, BOTH_EMPTY);
+        serial_out(up, UART_IER, ier);
+}
+
+#endif /* CONFIG_CONSOLE_POLL */
+
+static int serial8250_startup(struct uart_port *port)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+        unsigned long flags;
+        unsigned char lsr, iir;
+        int retval;
+
+        up->port.fifosize = uart_config[up->port.type].fifo_size;
+        up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
+        up->capabilities = uart_config[up->port.type].flags;
+        up->mcr = 0;
+
+        if (up->port.iotype != up->cur_iotype)
+                set_io_from_upio(port);
+
+        if (up->port.type == PORT_16C950) {
+                /* Wake up and initialize UART */
+                up->acr = 0;
+                serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
+                serial_outp(up, UART_EFR, UART_EFR_ECB);
+                serial_outp(up, UART_IER, 0);
+                serial_outp(up, UART_LCR, 0);
+                serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
+                serial_outp(up, UART_LCR, 0xBF);
+                serial_outp(up, UART_EFR, UART_EFR_ECB);
+                serial_outp(up, UART_LCR, 0);
+        }
+
+#ifdef CONFIG_SERIAL_8250_RSA
+        /*
+         * If this is an RSA port, see if we can kick it up to the
+         * higher speed clock.
+         */
+        enable_rsa(up);
+#endif
+
+        /*
+         * Clear the FIFO buffers and disable them.
+         * (they will be reenabled in set_termios())
+         */
+        serial8250_clear_fifos(up);
+
+        /*
+         * Clear the interrupt registers.
+         */
+        (void) serial_inp(up, UART_LSR);
+        (void) serial_inp(up, UART_RX);
+        (void) serial_inp(up, UART_IIR);
+        (void) serial_inp(up, UART_MSR);
+
+        /*
+         * At this point, there's no way the LSR could still be 0xff;
+         * if it is, then bail out, because there's likely no UART
+         * here.
+         */
+        if (!(up->port.flags & UPF_BUGGY_UART) &&
+            (serial_inp(up, UART_LSR) == 0xff)) {
+                printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
+                       serial_index(&up->port));
+                return -ENODEV;
+        }
+
+        /*
+         * For a XR16C850, we need to set the trigger levels
+         */
+        if (up->port.type == PORT_16850) {
+                unsigned char fctr;
+
+                serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
+
+                fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
+                serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
+                serial_outp(up, UART_TRG, UART_TRG_96);
+                serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
+                serial_outp(up, UART_TRG, UART_TRG_96);
+
+                serial_outp(up, UART_LCR, 0);
+        }
+
+        if (is_real_interrupt(up->port.irq)) {
+                unsigned char iir1;
+                /*
+                 * Test for UARTs that do not reassert THRE when the
+                 * transmitter is idle and the interrupt has already
+                 * been cleared.  Real 16550s should always reassert
+                 * this interrupt whenever the transmitter is idle and
+                 * the interrupt is enabled.  Delays are necessary to
+                 * allow register changes to become visible.
+                 */
+                spin_lock_irqsave(&up->port.lock, flags);
+                if (up->port.irqflags & IRQF_SHARED)
+                        disable_irq_nosync(up->port.irq);
+
+                wait_for_xmitr(up, UART_LSR_THRE);
+                serial_out_sync(up, UART_IER, UART_IER_THRI);
+                udelay(1); /* allow THRE to set */
+                iir1 = serial_in(up, UART_IIR);
+                serial_out(up, UART_IER, 0);
+                serial_out_sync(up, UART_IER, UART_IER_THRI);
+                udelay(1); /* allow a working UART time to re-assert THRE */
+                iir = serial_in(up, UART_IIR);
+                serial_out(up, UART_IER, 0);
+
+                if (up->port.irqflags & IRQF_SHARED)
+                        enable_irq(up->port.irq);
+                spin_unlock_irqrestore(&up->port.lock, flags);
+
+                /*
+                 * If the interrupt is not reasserted, setup a timer to
+                 * kick the UART on a regular basis.
+                 */
+                if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
+                        up->bugs |= UART_BUG_THRE;
+                        pr_debug("ttyS%d - using backup timer\n",
+                                 serial_index(port));
+                }
+        }
+
+        /*
+         * The above check will only give an accurate result the first time
+         * the port is opened so this value needs to be preserved.
+         */
+        if (up->bugs & UART_BUG_THRE) {
+                up->timer.function = serial8250_backup_timeout;
+                up->timer.data = (unsigned long)up;
+                mod_timer(&up->timer, jiffies +
+                        uart_poll_timeout(port) + HZ / 5);
+        }
+
+        /*
+         * If the "interrupt" for this port doesn't correspond with any
+         * hardware interrupt, we use a timer-based system.  The original
+         * driver used to do this with IRQ0.
+         */
+        if (!is_real_interrupt(up->port.irq)) {
+                up->timer.data = (unsigned long)up;
+                mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
+        } else {
+                retval = serial_link_irq_chain(up);
+                if (retval)
+                        return retval;
+        }
+
+        /*
+         * Now, initialize the UART
+         */
+        serial_outp(up, UART_LCR, UART_LCR_WLEN8);
+
+        spin_lock_irqsave(&up->port.lock, flags);
+        if (up->port.flags & UPF_FOURPORT) {
+                if (!is_real_interrupt(up->port.irq))
+                        up->port.mctrl |= TIOCM_OUT1;
+        } else
+                /*
+                 * Most PC uarts need OUT2 raised to enable interrupts.
+                 */
+                if (is_real_interrupt(up->port.irq))
+                        up->port.mctrl |= TIOCM_OUT2;
+
+        serial8250_set_mctrl(&up->port, up->port.mctrl);
+
+        /* Serial over Lan (SoL) hack:
+           Intel 8257x Gigabit ethernet chips have a
+           16550 emulation, to be used for Serial Over Lan.
+           Those chips take a longer time than a normal
+           serial device to signalize that a transmission
+           data was queued. Due to that, the above test generally
+           fails. One solution would be to delay the reading of
+           iir. However, this is not reliable, since the timeout
+           is variable. So, let's just don't test if we receive
+           TX irq. This way, we'll never enable UART_BUG_TXEN.
+         */
+        if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
+                goto dont_test_tx_en;
+
+        /*
+         * Do a quick test to see if we receive an
+         * interrupt when we enable the TX irq.
+         */
+        serial_outp(up, UART_IER, UART_IER_THRI);
+        lsr = serial_in(up, UART_LSR);
+        iir = serial_in(up, UART_IIR);
+        serial_outp(up, UART_IER, 0);
+
+        if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
+                if (!(up->bugs & UART_BUG_TXEN)) {
+                        up->bugs |= UART_BUG_TXEN;
+                        pr_debug("ttyS%d - enabling bad tx status workarounds\n",
+                                 serial_index(port));
+                }
+        } else {
+                up->bugs &= ~UART_BUG_TXEN;
+        }
+
+dont_test_tx_en:
+        spin_unlock_irqrestore(&up->port.lock, flags);
+
+        /*
+         * Clear the interrupt registers again for luck, and clear the
+         * saved flags to avoid getting false values from polling
+         * routines or the previous session.
+         */
+        serial_inp(up, UART_LSR);
+        serial_inp(up, UART_RX);
+        serial_inp(up, UART_IIR);
+        serial_inp(up, UART_MSR);
+        up->lsr_saved_flags = 0;
+        up->msr_saved_flags = 0;
+
+        /*
+         * Finally, enable interrupts.  Note: Modem status interrupts
+         * are set via set_termios(), which will be occurring imminently
+         * anyway, so we don't enable them here.
+         */
+        up->ier = UART_IER_RLSI | UART_IER_RDI;
+        serial_outp(up, UART_IER, up->ier);
+
+        if (up->port.flags & UPF_FOURPORT) {
+                unsigned int icp;
+                /*
+                 * Enable interrupts on the AST Fourport board
+                 */
+                icp = (up->port.iobase & 0xfe0) | 0x01f;
+                outb_p(0x80, icp);
+                (void) inb_p(icp);
+        }
+
+        return 0;
+}
+
+static void serial8250_shutdown(struct uart_port *port)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+        unsigned long flags;
+
+        /*
+         * Disable interrupts from this port
+         */
+        up->ier = 0;
+        serial_outp(up, UART_IER, 0);
+
+        spin_lock_irqsave(&up->port.lock, flags);
+        if (up->port.flags & UPF_FOURPORT) {
+                /* reset interrupts on the AST Fourport board */
+                inb((up->port.iobase & 0xfe0) | 0x1f);
+                up->port.mctrl |= TIOCM_OUT1;
+        } else
+                up->port.mctrl &= ~TIOCM_OUT2;
+
+        serial8250_set_mctrl(&up->port, up->port.mctrl);
+        spin_unlock_irqrestore(&up->port.lock, flags);
+
+        /*
+         * Disable break condition and FIFOs
+         */
+        serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
+        serial8250_clear_fifos(up);
+
+#ifdef CONFIG_SERIAL_8250_RSA
+        /*
+         * Reset the RSA board back to 115kbps compat mode.
+         */
+        disable_rsa(up);
+#endif
+
+        /*
+         * Read data port to reset things, and then unlink from
+         * the IRQ chain.
+         */
+        (void) serial_in(up, UART_RX);
+
+        del_timer_sync(&up->timer);
+        up->timer.function = serial8250_timeout;
+        if (is_real_interrupt(up->port.irq))
+                serial_unlink_irq_chain(up);
+}
+
+static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
+{
+        unsigned int quot;
+
+        /*
+         * Handle magic divisors for baud rates above baud_base on
+         * SMSC SuperIO chips.
+         */
+        if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
+            baud == (port->uartclk/4))
+                quot = 0x8001;
+        else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
+                 baud == (port->uartclk/8))
+                quot = 0x8002;
+        else
+                quot = uart_get_divisor(port, baud);
+
+        return quot;
+}
+
+void
+serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
+                          struct ktermios *old)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+        unsigned char cval, fcr = 0;
+        unsigned long flags;
+        unsigned int baud, quot;
+
+        switch (termios->c_cflag & CSIZE) {
+        case CS5:
+                cval = UART_LCR_WLEN5;
+                break;
+        case CS6:
+                cval = UART_LCR_WLEN6;
+                break;
+        case CS7:
+                cval = UART_LCR_WLEN7;
+                break;
+        default:
+        case CS8:
+                cval = UART_LCR_WLEN8;
+                break;
+        }
+
+        if (termios->c_cflag & CSTOPB)
+                cval |= UART_LCR_STOP;
+        if (termios->c_cflag & PARENB)
+                cval |= UART_LCR_PARITY;
+        if (!(termios->c_cflag & PARODD))
+                cval |= UART_LCR_EPAR;
+#ifdef CMSPAR
+        if (termios->c_cflag & CMSPAR)
+                cval |= UART_LCR_SPAR;
+#endif
+
+        /*
+         * Ask the core to calculate the divisor for us.
+         */
+        baud = uart_get_baud_rate(port, termios, old,
+                                  port->uartclk / 16 / 0xffff,
+                                  port->uartclk / 16);
+        quot = serial8250_get_divisor(port, baud);
+
+        /*
+         * Oxford Semi 952 rev B workaround
+         */
+        if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
+                quot++;
+
+        if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
+                if (baud < 2400)
+                        fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
+                else
+                        fcr = uart_config[up->port.type].fcr;
+        }
+
+        /*
+         * MCR-based auto flow control.  When AFE is enabled, RTS will be
+         * deasserted when the receive FIFO contains more characters than
+         * the trigger, or the MCR RTS bit is cleared.  In the case where
+         * the remote UART is not using CTS auto flow control, we must
+         * have sufficient FIFO entries for the latency of the remote
+         * UART to respond.  IOW, at least 32 bytes of FIFO.
+         */
+        if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
+                up->mcr &= ~UART_MCR_AFE;
+                if (termios->c_cflag & CRTSCTS)
+                        up->mcr |= UART_MCR_AFE;
+        }
+
+        /*
+         * Ok, we're now changing the port state.  Do it with
+         * interrupts disabled.
+         */
+        spin_lock_irqsave(&up->port.lock, flags);
+
+        /*
+         * Update the per-port timeout.
+         */
+        uart_update_timeout(port, termios->c_cflag, baud);
+
+        up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
+        if (termios->c_iflag & INPCK)
+                up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
+        if (termios->c_iflag & (BRKINT | PARMRK))
+                up->port.read_status_mask |= UART_LSR_BI;
+
+        /*
+         * Characteres to ignore
+         */
+        up->port.ignore_status_mask = 0;
+        if (termios->c_iflag & IGNPAR)
+                up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
+        if (termios->c_iflag & IGNBRK) {
+                up->port.ignore_status_mask |= UART_LSR_BI;
+                /*
+                 * If we're ignoring parity and break indicators,
+                 * ignore overruns too (for real raw support).
+                 */
+                if (termios->c_iflag & IGNPAR)
+                        up->port.ignore_status_mask |= UART_LSR_OE;
+        }
+
+        /*
+         * ignore all characters if CREAD is not set
+         */
+        if ((termios->c_cflag & CREAD) == 0)
+                up->port.ignore_status_mask |= UART_LSR_DR;
+
+        /*
+         * CTS flow control flag and modem status interrupts
+         */
+        up->ier &= ~UART_IER_MSI;
+        if (!(up->bugs & UART_BUG_NOMSR) &&
+                        UART_ENABLE_MS(&up->port, termios->c_cflag))
+                up->ier |= UART_IER_MSI;
+        if (up->capabilities & UART_CAP_UUE)
+                up->ier |= UART_IER_UUE;
+        if (up->capabilities & UART_CAP_RTOIE)
+                up->ier |= UART_IER_RTOIE;
+
+        serial_out(up, UART_IER, up->ier);
+
+        if (up->capabilities & UART_CAP_EFR) {
+                unsigned char efr = 0;
+                /*
+                 * TI16C752/Startech hardware flow control.  FIXME:
+                 * - TI16C752 requires control thresholds to be set.
+                 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
+                 */
+                if (termios->c_cflag & CRTSCTS)
+                        efr |= UART_EFR_CTS;
+
+                serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
+                serial_outp(up, UART_EFR, efr);
+        }
+
+        if (up->capabilities & UART_CAP_HW_CTSRTS) {
+                unsigned char mcr = serial_inp(up, UART_MCR);
+                /*
+                 * TEGRA UART core support the auto control of the RTS and CTS
+                 * flow control.
+                 */
+                if (termios->c_cflag & CRTSCTS)
+                        mcr |= UART_MCR_HW_CTS;
+                else
+                        mcr &= ~UART_MCR_HW_CTS;
+                serial_outp(up, UART_MCR, mcr);
+        }
+
+#ifdef CONFIG_ARCH_OMAP
+        /* Workaround to enable 115200 baud on OMAP1510 internal ports */
+        if (cpu_is_omap1510() && is_omap_port(up)) {
+                if (baud == 115200) {
+                        quot = 1;
+                        serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
+                } else
+                        serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
+        }
+#endif
+
+        if (up->capabilities & UART_NATSEMI) {
+                /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
+                serial_outp(up, UART_LCR, 0xe0);
+        } else {
+                serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
+        }
+
+        serial_dl_write(up, quot);
+
+        /*
+         * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
+         * is written without DLAB set, this mode will be disabled.
+         */
+        if (up->port.type == PORT_16750)
+                serial_outp(up, UART_FCR, fcr);
+
+        serial_outp(up, UART_LCR, cval);                /* reset DLAB */
+        up->lcr = cval;                                 /* Save LCR */
+        if (up->port.type != PORT_16750) {
+                if (fcr & UART_FCR_ENABLE_FIFO) {
+                        /* emulated UARTs (Lucent Venus 167x) need two steps */
+                        serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
+                }
+                serial_outp(up, UART_FCR, fcr);         /* set fcr */
+        }
+        serial8250_set_mctrl(&up->port, up->port.mctrl);
+        spin_unlock_irqrestore(&up->port.lock, flags);
+        /* Don't rewrite B0 */
+        if (tty_termios_baud_rate(termios))
+                tty_termios_encode_baud_rate(termios, baud, baud);
+}
+EXPORT_SYMBOL(serial8250_do_set_termios);
+
+static void
+serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
+                       struct ktermios *old)
+{
+        if (port->set_termios)
+                port->set_termios(port, termios, old);
+        else
+                serial8250_do_set_termios(port, termios, old);
+}
+
+static void
+serial8250_set_ldisc(struct uart_port *port, int new)
+{
+        if (new == N_PPS) {
+                port->flags |= UPF_HARDPPS_CD;
+                serial8250_enable_ms(port);
+        } else
+                port->flags &= ~UPF_HARDPPS_CD;
+}
+
+
+void serial8250_do_pm(struct uart_port *port, unsigned int state,
+                      unsigned int oldstate)
+{
+        struct uart_8250_port *p =
+                container_of(port, struct uart_8250_port, port);
+
+        serial8250_set_sleep(p, state != 0);
+}
+EXPORT_SYMBOL(serial8250_do_pm);
+
+static void
+serial8250_pm(struct uart_port *port, unsigned int state,
+              unsigned int oldstate)
+{
+        if (port->pm)
+                port->pm(port, state, oldstate);
+        else
+                serial8250_do_pm(port, state, oldstate);
+}
+
+static unsigned int serial8250_port_size(struct uart_8250_port *pt)
+{
+        if (pt->port.iotype == UPIO_AU)
+                return 0x1000;
+#ifdef CONFIG_ARCH_OMAP
+        if (is_omap_port(pt))
+                return 0x16 << pt->port.regshift;
+#endif
+        return 8 << pt->port.regshift;
+}
+
+/*
+ * Resource handling.
+ */
+static int serial8250_request_std_resource(struct uart_8250_port *up)
+{
+        unsigned int size = serial8250_port_size(up);
+        int ret = 0;
+
+        switch (up->port.iotype) {
+        case UPIO_AU:
+        case UPIO_TSI:
+        case UPIO_MEM32:
+        case UPIO_MEM:
+        case UPIO_DWAPB:
+        case UPIO_DWAPB32:
+                if (!up->port.mapbase)
+                        break;
+
+                if (!request_mem_region(up->port.mapbase, size, "serial")) {
+                        ret = -EBUSY;
+                        break;
+                }
+
+                if (up->port.flags & UPF_IOREMAP) {
+                        up->port.membase = ioremap_nocache(up->port.mapbase,
+                                                                        size);
+                        if (!up->port.membase) {
+                                release_mem_region(up->port.mapbase, size);
+                                ret = -ENOMEM;
+                        }
+                }
+                break;
+
+        case UPIO_HUB6:
+        case UPIO_PORT:
+                if (!request_region(up->port.iobase, size, "serial"))
+                        ret = -EBUSY;
+                break;
+        }
+        return ret;
+}
+
+static void serial8250_release_std_resource(struct uart_8250_port *up)
+{
+        unsigned int size = serial8250_port_size(up);
+
+        switch (up->port.iotype) {
+        case UPIO_AU:
+        case UPIO_TSI:
+        case UPIO_MEM32:
+        case UPIO_MEM:
+        case UPIO_DWAPB:
+        case UPIO_DWAPB32:
+                if (!up->port.mapbase)
+                        break;
+
+                if (up->port.flags & UPF_IOREMAP) {
+                        iounmap(up->port.membase);
+                        up->port.membase = NULL;
+                }
+
+                release_mem_region(up->port.mapbase, size);
+                break;
+
+        case UPIO_HUB6:
+        case UPIO_PORT:
+                release_region(up->port.iobase, size);
+                break;
+        }
+}
+
+static int serial8250_request_rsa_resource(struct uart_8250_port *up)
+{
+        unsigned long start = UART_RSA_BASE << up->port.regshift;
+        unsigned int size = 8 << up->port.regshift;
+        int ret = -EINVAL;
+
+        switch (up->port.iotype) {
+        case UPIO_HUB6:
+        case UPIO_PORT:
+                start += up->port.iobase;
+                if (request_region(start, size, "serial-rsa"))
+                        ret = 0;
+                else
+                        ret = -EBUSY;
+                break;
+        }
+
+        return ret;
+}
+
+static void serial8250_release_rsa_resource(struct uart_8250_port *up)
+{
+        unsigned long offset = UART_RSA_BASE << up->port.regshift;
+        unsigned int size = 8 << up->port.regshift;
+
+        switch (up->port.iotype) {
+        case UPIO_HUB6:
+        case UPIO_PORT:
+                release_region(up->port.iobase + offset, size);
+                break;
+        }
+}
+
+static void serial8250_release_port(struct uart_port *port)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+
+        serial8250_release_std_resource(up);
+        if (up->port.type == PORT_RSA)
+                serial8250_release_rsa_resource(up);
+}
+
+static int serial8250_request_port(struct uart_port *port)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+        int ret = 0;
+
+        ret = serial8250_request_std_resource(up);
+        if (ret == 0 && up->port.type == PORT_RSA) {
+                ret = serial8250_request_rsa_resource(up);
+                if (ret < 0)
+                        serial8250_release_std_resource(up);
+        }
+
+        return ret;
+}
+
+static void serial8250_config_port(struct uart_port *port, int flags)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+        int probeflags = PROBE_ANY;
+        int ret;
+
+        /*
+         * Find the region that we can probe for.  This in turn
+         * tells us whether we can probe for the type of port.
+         */
+        ret = serial8250_request_std_resource(up);
+        if (ret < 0)
+                return;
+
+        ret = serial8250_request_rsa_resource(up);
+        if (ret < 0)
+                probeflags &= ~PROBE_RSA;
+
+        if (up->port.iotype != up->cur_iotype)
+                set_io_from_upio(port);
+
+        if (flags & UART_CONFIG_TYPE)
+                autoconfig(up, probeflags);
+
+        /* if access method is AU, it is a 16550 with a quirk */
+        if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
+                up->bugs |= UART_BUG_NOMSR;
+
+        if (up->port.type == PORT_TEGRA)
+                up->bugs |= UART_BUG_NOMSR;
+
+        if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
+                autoconfig_irq(up);
+
+        if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
+                serial8250_release_rsa_resource(up);
+        if (up->port.type == PORT_UNKNOWN)
+                serial8250_release_std_resource(up);
+}
+
+static int
+serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+        if (ser->irq >= nr_irqs || ser->irq < 0 ||
+            ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
+            ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
+            ser->type == PORT_STARTECH)
+                return -EINVAL;
+        return 0;
+}
+
+static const char *
+serial8250_type(struct uart_port *port)
+{
+        int type = port->type;
+
+        if (type >= ARRAY_SIZE(uart_config))
+                type = 0;
+        return uart_config[type].name;
+}
+
+static struct uart_ops serial8250_pops = {
+        .tx_empty       = serial8250_tx_empty,
+        .set_mctrl      = serial8250_set_mctrl,
+        .get_mctrl      = serial8250_get_mctrl,
+        .stop_tx        = serial8250_stop_tx,
+        .start_tx       = serial8250_start_tx,
+        .stop_rx        = serial8250_stop_rx,
+        .enable_ms      = serial8250_enable_ms,
+        .break_ctl      = serial8250_break_ctl,
+        .startup        = serial8250_startup,
+        .shutdown       = serial8250_shutdown,
+        .set_termios    = serial8250_set_termios,
+        .set_ldisc      = serial8250_set_ldisc,
+        .pm             = serial8250_pm,
+        .type           = serial8250_type,
+        .release_port   = serial8250_release_port,
+        .request_port   = serial8250_request_port,
+        .config_port    = serial8250_config_port,
+        .verify_port    = serial8250_verify_port,
+#ifdef CONFIG_CONSOLE_POLL
+        .poll_get_char = serial8250_get_poll_char,
+        .poll_put_char = serial8250_put_poll_char,
+#endif
+};
+
+static struct uart_8250_port serial8250_ports[UART_NR];
+
+static void (*serial8250_isa_config)(int port, struct uart_port *up,
+        unsigned short *capabilities);
+
+void serial8250_set_isa_configurator(
+        void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
+{
+        serial8250_isa_config = v;
+}
+EXPORT_SYMBOL(serial8250_set_isa_configurator);
+
+static void __init serial8250_isa_init_ports(void)
+{
+        struct uart_8250_port *up;
+        static int first = 1;
+        int i, irqflag = 0;
+
+        if (!first)
+                return;
+        first = 0;
+
+        for (i = 0; i < nr_uarts; i++) {
+                struct uart_8250_port *up = &serial8250_ports[i];
+
+                up->port.line = i;
+                spin_lock_init(&up->port.lock);
+
+                init_timer(&up->timer);
+                up->timer.function = serial8250_timeout;
+
+                /*
+                 * ALPHA_KLUDGE_MCR needs to be killed.
+                 */
+                up->mcr_mask = ~ALPHA_KLUDGE_MCR;
+                up->mcr_force = ALPHA_KLUDGE_MCR;
+
+                up->port.ops = &serial8250_pops;
+        }
+
+        if (share_irqs)
+                irqflag = IRQF_SHARED;
+
+        for (i = 0, up = serial8250_ports;
+             i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
+             i++, up++) {
+                up->port.iobase   = old_serial_port[i].port;
+                up->port.irq      = irq_canonicalize(old_serial_port[i].irq);
+                up->port.irqflags = old_serial_port[i].irqflags;
+                up->port.uartclk  = old_serial_port[i].baud_base * 16;
+                up->port.flags    = old_serial_port[i].flags;
+                up->port.hub6     = old_serial_port[i].hub6;
+                up->port.membase  = old_serial_port[i].iomem_base;
+                up->port.iotype   = old_serial_port[i].io_type;
+                up->port.regshift = old_serial_port[i].iomem_reg_shift;
+                set_io_from_upio(&up->port);
+                up->port.irqflags |= irqflag;
+                if (serial8250_isa_config != NULL)
+                        serial8250_isa_config(i, &up->port, &up->capabilities);
+
+        }
+}
+
+static void
+serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
+{
+        up->port.type = type;
+        up->port.fifosize = uart_config[type].fifo_size;
+        up->capabilities = uart_config[type].flags;
+        up->tx_loadsz = uart_config[type].tx_loadsz;
+}
+
+static void __init
+serial8250_register_ports(struct uart_driver *drv, struct device *dev)
+{
+        int i;
+
+        for (i = 0; i < nr_uarts; i++) {
+                struct uart_8250_port *up = &serial8250_ports[i];
+                up->cur_iotype = 0xFF;
+        }
+
+        serial8250_isa_init_ports();
+
+        for (i = 0; i < nr_uarts; i++) {
+                struct uart_8250_port *up = &serial8250_ports[i];
+
+                up->port.dev = dev;
+
+                if (up->port.flags & UPF_FIXED_TYPE)
+                        serial8250_init_fixed_type_port(up, up->port.type);
+
+                uart_add_one_port(drv, &up->port);
+        }
+}
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+
+static void serial8250_console_putchar(struct uart_port *port, int ch)
+{
+        struct uart_8250_port *up =
+                container_of(port, struct uart_8250_port, port);
+
+        wait_for_xmitr(up, UART_LSR_THRE);
+        serial_out(up, UART_TX, ch);
+}
+
+/*
+ *      Print a string to the serial port trying not to disturb
+ *      any possible real use of the port...
+ *
+ *      The console_lock must be held when we get here.
+ */
+static void
+serial8250_console_write(struct console *co, const char *s, unsigned int count)
+{
+        struct uart_8250_port *up = &serial8250_ports[co->index];
+        unsigned long flags;
+        unsigned int ier;
+        int locked = 1;
+
+        touch_nmi_watchdog();
+
+        local_irq_save(flags);
+        if (up->port.sysrq) {
+                /* serial8250_handle_port() already took the lock */
+                locked = 0;
+        } else if (oops_in_progress) {
+                locked = spin_trylock(&up->port.lock);
+        } else
+                spin_lock(&up->port.lock);
+
+        /*
+         *      First save the IER then disable the interrupts
+         */
+        ier = serial_in(up, UART_IER);
+
+        if (up->capabilities & UART_CAP_UUE)
+                serial_out(up, UART_IER, UART_IER_UUE);
+        else
+                serial_out(up, UART_IER, 0);
+
+        uart_console_write(&up->port, s, count, serial8250_console_putchar);
+
+        /*
+         *      Finally, wait for transmitter to become empty
+         *      and restore the IER
+         */
+        wait_for_xmitr(up, BOTH_EMPTY);
+        serial_out(up, UART_IER, ier);
+
+        /*
+         *      The receive handling will happen properly because the
+         *      receive ready bit will still be set; it is not cleared
+         *      on read.  However, modem control will not, we must
+         *      call it if we have saved something in the saved flags
+         *      while processing with interrupts off.
+         */
+        if (up->msr_saved_flags)
+                check_modem_status(up);
+
+        if (locked)
+                spin_unlock(&up->port.lock);
+        local_irq_restore(flags);
+}
+
+static int __init serial8250_console_setup(struct console *co, char *options)
+{
+        struct uart_port *port;
+        int baud = 9600;
+        int bits = 8;
+        int parity = 'n';
+        int flow = 'n';
+
+        /*
+         * Check whether an invalid uart number has been specified, and
+         * if so, search for the first available port that does have
+         * console support.
+         */
+        if (co->index >= nr_uarts)
+                co->index = 0;
+        port = &serial8250_ports[co->index].port;
+        if (!port->iobase && !port->membase)
+                return -ENODEV;
+
+        if (options)
+                uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+        return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+static int serial8250_console_early_setup(void)
+{
+        return serial8250_find_port_for_earlycon();
+}
+
+static struct console serial8250_console = {
+        .name           = "ttyS",
+        .write          = serial8250_console_write,
+        .device         = uart_console_device,
+        .setup          = serial8250_console_setup,
+        .early_setup    = serial8250_console_early_setup,
+        .flags          = CON_PRINTBUFFER | CON_ANYTIME,
+        .index          = -1,
+        .data           = &serial8250_reg,
+};
+
+static int __init serial8250_console_init(void)
+{
+        if (nr_uarts > UART_NR)
+                nr_uarts = UART_NR;
+
+        serial8250_isa_init_ports();
+        register_console(&serial8250_console);
+        return 0;
+}
+console_initcall(serial8250_console_init);
+
+int serial8250_find_port(struct uart_port *p)
+{
+        int line;
+        struct uart_port *port;
+
+        for (line = 0; line < nr_uarts; line++) {
+                port = &serial8250_ports[line].port;
+                if (uart_match_port(p, port))
+                        return line;
+        }
+        return -ENODEV;
+}
+
+#define SERIAL8250_CONSOLE      &serial8250_console
+#else
+#define SERIAL8250_CONSOLE      NULL
+#endif
+
+static struct uart_driver serial8250_reg = {
+        .owner                  = THIS_MODULE,
+        .driver_name            = "serial",
+        .dev_name               = "ttyS",
+        .major                  = TTY_MAJOR,
+        .minor                  = 64,
+        .cons                   = SERIAL8250_CONSOLE,
+};
+
+/*
+ * early_serial_setup - early registration for 8250 ports
+ *
+ * Setup an 8250 port structure prior to console initialisation.  Use
+ * after console initialisation will cause undefined behaviour.
+ */
+int __init early_serial_setup(struct uart_port *port)
+{
+        struct uart_port *p;
+
+        if (port->line >= ARRAY_SIZE(serial8250_ports))
+                return -ENODEV;
+
+        serial8250_isa_init_ports();
+        p = &serial8250_ports[port->line].port;
+        p->iobase       = port->iobase;
+        p->membase      = port->membase;
+        p->irq          = port->irq;
+        p->irqflags     = port->irqflags;
+        p->uartclk      = port->uartclk;
+        p->fifosize     = port->fifosize;
+        p->regshift     = port->regshift;
+        p->iotype       = port->iotype;
+        p->flags        = port->flags;
+        p->mapbase      = port->mapbase;
+        p->private_data = port->private_data;
+        p->type         = port->type;
+        p->line         = port->line;
+
+        set_io_from_upio(p);
+        if (port->serial_in)
+                p->serial_in = port->serial_in;
+        if (port->serial_out)
+                p->serial_out = port->serial_out;
+
+        return 0;
+}
+
+/**
+ *      serial8250_suspend_port - suspend one serial port
+ *      @line:  serial line number
+ *
+ *      Suspend one serial port.
+ */
+void serial8250_suspend_port(int line)
+{
+        uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
+}
+
+/**
+ *      serial8250_resume_port - resume one serial port
+ *      @line:  serial line number
+ *
+ *      Resume one serial port.
+ */
+void serial8250_resume_port(int line)
+{
+        struct uart_8250_port *up = &serial8250_ports[line];
+
+        if (up->capabilities & UART_NATSEMI) {
+                /* Ensure it's still in high speed mode */
+                serial_outp(up, UART_LCR, 0xE0);
+
+                ns16550a_goto_highspeed(up);
+
+                serial_outp(up, UART_LCR, 0);
+                up->port.uartclk = 921600*16;
+        }
+        uart_resume_port(&serial8250_reg, &up->port);
+}
+
+/*
+ * Register a set of serial devices attached to a platform device.  The
+ * list is terminated with a zero flags entry, which means we expect
+ * all entries to have at least UPF_BOOT_AUTOCONF set.
+ */
+static int __devinit serial8250_probe(struct platform_device *dev)
+{
+        struct plat_serial8250_port *p = dev->dev.platform_data;
+        struct uart_port port;
+        int ret, i, irqflag = 0;
+
+        memset(&port, 0, sizeof(struct uart_port));
+
+        if (share_irqs)
+                irqflag = IRQF_SHARED;
+
+        for (i = 0; p && p->flags != 0; p++, i++) {
+                port.iobase             = p->iobase;
+                port.membase            = p->membase;
+                port.irq                = p->irq;
+                port.irqflags           = p->irqflags;
+                port.uartclk            = p->uartclk;
+                port.regshift           = p->regshift;
+                port.iotype             = p->iotype;
+                port.flags              = p->flags;
+                port.mapbase            = p->mapbase;
+                port.hub6               = p->hub6;
+                port.private_data       = p->private_data;
+                port.type               = p->type;
+                port.serial_in          = p->serial_in;
+                port.serial_out         = p->serial_out;
+                port.set_termios        = p->set_termios;
+                port.pm                 = p->pm;
+                port.dev                = &dev->dev;
+                port.irqflags           |= irqflag;
+                ret = serial8250_register_port(&port);
+                if (ret < 0) {
+                        dev_err(&dev->dev, "unable to register port at index %d "
+                                "(IO%lx MEM%llx IRQ%d): %d\n", i,
+                                p->iobase, (unsigned long long)p->mapbase,
+                                p->irq, ret);
+                }
+        }
+        return 0;
+}
+
+/*
+ * Remove serial ports registered against a platform device.
+ */
+static int __devexit serial8250_remove(struct platform_device *dev)
+{
+        int i;
+
+        for (i = 0; i < nr_uarts; i++) {
+                struct uart_8250_port *up = &serial8250_ports[i];
+
+                if (up->port.dev == &dev->dev)
+                        serial8250_unregister_port(i);
+        }
+        return 0;
+}
+
+static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
+{
+        int i;
+
+        for (i = 0; i < UART_NR; i++) {
+                struct uart_8250_port *up = &serial8250_ports[i];
+
+                if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
+                        uart_suspend_port(&serial8250_reg, &up->port);
+        }
+
+        return 0;
+}
+
+static int serial8250_resume(struct platform_device *dev)
+{
+        int i;
+
+        for (i = 0; i < UART_NR; i++) {
+                struct uart_8250_port *up = &serial8250_ports[i];
+
+                if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
+                        serial8250_resume_port(i);
+        }
+
+        return 0;
+}
+
+static struct platform_driver serial8250_isa_driver = {
+        .probe          = serial8250_probe,
+        .remove         = __devexit_p(serial8250_remove),
+        .suspend        = serial8250_suspend,
+        .resume         = serial8250_resume,
+        .driver         = {
+                .name   = "serial8250",
+                .owner  = THIS_MODULE,
+        },
+};
+
+/*
+ * This "device" covers _all_ ISA 8250-compatible serial devices listed
+ * in the table in include/asm/serial.h
+ */
+static struct platform_device *serial8250_isa_devs;
+
+/*
+ * serial8250_register_port and serial8250_unregister_port allows for
+ * 16x50 serial ports to be configured at run-time, to support PCMCIA
+ * modems and PCI multiport cards.
+ */
+static DEFINE_MUTEX(serial_mutex);
+
+static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
+{
+        int i;
+
+        /*
+         * First, find a port entry which matches.
+         */
+        for (i = 0; i < nr_uarts; i++)
+                if (uart_match_port(&serial8250_ports[i].port, port))
+                        return &serial8250_ports[i];
+
+        /*
+         * We didn't find a matching entry, so look for the first
+         * free entry.  We look for one which hasn't been previously
+         * used (indicated by zero iobase).
+         */
+        for (i = 0; i < nr_uarts; i++)
+                if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
+                    serial8250_ports[i].port.iobase == 0)
+                        return &serial8250_ports[i];
+
+        /*
+         * That also failed.  Last resort is to find any entry which
+         * doesn't have a real port associated with it.
+         */
+        for (i = 0; i < nr_uarts; i++)
+                if (serial8250_ports[i].port.type == PORT_UNKNOWN)
+                        return &serial8250_ports[i];
+
+        return NULL;
+}
+
+/**
+ *      serial8250_register_port - register a serial port
+ *      @port: serial port template
+ *
+ *      Configure the serial port specified by the request. If the
+ *      port exists and is in use, it is hung up and unregistered
+ *      first.
+ *
+ *      The port is then probed and if necessary the IRQ is autodetected
+ *      If this fails an error is returned.
+ *
+ *      On success the port is ready to use and the line number is returned.
+ */
+int serial8250_register_port(struct uart_port *port)
+{
+        struct uart_8250_port *uart;
+        int ret = -ENOSPC;
+
+        if (port->uartclk == 0)
+                return -EINVAL;
+
+        mutex_lock(&serial_mutex);
+
+        uart = serial8250_find_match_or_unused(port);
+        if (uart) {
+                uart_remove_one_port(&serial8250_reg, &uart->port);
+
+                uart->port.iobase       = port->iobase;
+                uart->port.membase      = port->membase;
+                uart->port.irq          = port->irq;
+                uart->port.irqflags     = port->irqflags;
+                uart->port.uartclk      = port->uartclk;
+                uart->port.fifosize     = port->fifosize;
+                uart->port.regshift     = port->regshift;
+                uart->port.iotype       = port->iotype;
+                uart->port.flags        = port->flags | UPF_BOOT_AUTOCONF;
+                uart->port.mapbase      = port->mapbase;
+                uart->port.private_data = port->private_data;
+                if (port->dev)
+                        uart->port.dev = port->dev;
+
+                if (port->flags & UPF_FIXED_TYPE)
+                        serial8250_init_fixed_type_port(uart, port->type);
+
+                set_io_from_upio(&uart->port);
+                /* Possibly override default I/O functions.  */
+                if (port->serial_in)
+                        uart->port.serial_in = port->serial_in;
+                if (port->serial_out)
+                        uart->port.serial_out = port->serial_out;
+                /*  Possibly override set_termios call */
+                if (port->set_termios)
+                        uart->port.set_termios = port->set_termios;
+                if (port->pm)
+                        uart->port.pm = port->pm;
+
+                if (serial8250_isa_config != NULL)
+                        serial8250_isa_config(0, &uart->port,
+                                        &uart->capabilities);
+
+                ret = uart_add_one_port(&serial8250_reg, &uart->port);
+                if (ret == 0)
+                        ret = uart->port.line;
+        }
+        mutex_unlock(&serial_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL(serial8250_register_port);
+
+/**
+ *      serial8250_unregister_port - remove a 16x50 serial port at runtime
+ *      @line: serial line number
+ *
+ *      Remove one serial port.  This may not be called from interrupt
+ *      context.  We hand the port back to the our control.
+ */
+void serial8250_unregister_port(int line)
+{
+        struct uart_8250_port *uart = &serial8250_ports[line];
+
+        mutex_lock(&serial_mutex);
+        uart_remove_one_port(&serial8250_reg, &uart->port);
+        if (serial8250_isa_devs) {
+                uart->port.flags &= ~UPF_BOOT_AUTOCONF;
+                uart->port.type = PORT_UNKNOWN;
+                uart->port.dev = &serial8250_isa_devs->dev;
+                uart->capabilities = uart_config[uart->port.type].flags;
+                uart_add_one_port(&serial8250_reg, &uart->port);
+        } else {
+                uart->port.dev = NULL;
+        }
+        mutex_unlock(&serial_mutex);
+}
+EXPORT_SYMBOL(serial8250_unregister_port);
+
+static int __init serial8250_init(void)
+{
+        int ret;
+
+        if (nr_uarts > UART_NR)
+                nr_uarts = UART_NR;
+
+        printk(KERN_INFO "Serial: 8250/16550 driver, "
+                "%d ports, IRQ sharing %sabled\n", nr_uarts,
+                share_irqs ? "en" : "dis");
+
+#ifdef CONFIG_SPARC
+        ret = sunserial_register_minors(&serial8250_reg, UART_NR);
+#else
+        serial8250_reg.nr = UART_NR;
+        ret = uart_register_driver(&serial8250_reg);
+#endif
+        if (ret)
+                goto out;
+
+        serial8250_isa_devs = platform_device_alloc("serial8250",
+                                                    PLAT8250_DEV_LEGACY);
+        if (!serial8250_isa_devs) {
+                ret = -ENOMEM;
+                goto unreg_uart_drv;
+        }
+
+        ret = platform_device_add(serial8250_isa_devs);
+        if (ret)
+                goto put_dev;
+
+        serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
+
+        ret = platform_driver_register(&serial8250_isa_driver);
+        if (ret == 0)
+                goto out;
+
+        platform_device_del(serial8250_isa_devs);
+put_dev:
+        platform_device_put(serial8250_isa_devs);
+unreg_uart_drv:
+#ifdef CONFIG_SPARC
+        sunserial_unregister_minors(&serial8250_reg, UART_NR);
+#else
+        uart_unregister_driver(&serial8250_reg);
+#endif
+out:
+        return ret;
+}
+
+#ifdef MODULE
+static void __exit serial8250_exit(void)
+{
+        struct platform_device *isa_dev = serial8250_isa_devs;
+
+        /*
+         * This tells serial8250_unregister_port() not to re-register
+         * the ports (thereby making serial8250_isa_driver permanently
+         * in use.)
+         */
+        serial8250_isa_devs = NULL;
+
+        platform_driver_unregister(&serial8250_isa_driver);
+        platform_device_unregister(isa_dev);
+
+#ifdef CONFIG_SPARC
+        sunserial_unregister_minors(&serial8250_reg, UART_NR);
+#else
+        uart_unregister_driver(&serial8250_reg);
+#endif
+}
+
+module_init(serial8250_init);
+module_exit(serial8250_exit);
+#else
+postcore_initcall(serial8250_init);
+#endif
+
+EXPORT_SYMBOL(serial8250_suspend_port);
+EXPORT_SYMBOL(serial8250_resume_port);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
+
+module_param(share_irqs, uint, 0644);
+MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
+        " (unsafe)");
+
+module_param(nr_uarts, uint, 0644);
+MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
+
+module_param(skip_txen_test, uint, 0644);
+MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
+
+#ifdef CONFIG_SERIAL_8250_RSA
+module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
+MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
+#endif
+MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
diff --git a/drivers/tty/serial/8250.h b/drivers/tty/serial/8250.h
new file mode 100644
index 00000000000..66a0c936b93
--- /dev/null
+++ b/drivers/tty/serial/8250.h
@@ -0,0 +1,80 @@
+/*
+ *  Driver for 8250/16550-type serial ports
+ *
+ *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
+ *  Copyright (C) 2001 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/serial_8250.h>
+
+struct old_serial_port {
+        unsigned int uart;
+        unsigned int baud_base;
+        unsigned int port;
+        unsigned int irq;
+        unsigned int flags;
+        unsigned char hub6;
+        unsigned char io_type;
+        unsigned char *iomem_base;
+        unsigned short iomem_reg_shift;
+        unsigned long irqflags;
+};
+
+/*
+ * This replaces serial_uart_config in include/linux/serial.h
+ */
+struct serial8250_config {
+        const char      *name;
+        unsigned short  fifo_size;
+        unsigned short  tx_loadsz;
+        unsigned char   fcr;
+        unsigned int    flags;
+};
+
+#define UART_CAP_FIFO   (1 << 8)        /* UART has FIFO */
+#define UART_CAP_EFR    (1 << 9)        /* UART has EFR */
+#define UART_CAP_SLEEP  (1 << 10)       /* UART has IER sleep */
+#define UART_CAP_AFE    (1 << 11)       /* MCR-based hw flow control */
+#define UART_CAP_UUE    (1 << 12)       /* UART needs IER bit 6 set (Xscale) */
+#define UART_CAP_RTOIE  (1 << 13)       /* UART needs IER bit 4 set (Xscale, Tegra) */
+#define UART_CAP_HW_CTSRTS      (1 << 14)       /* UART core support hw control of RTS and CTS */
+
+#define UART_BUG_QUOT   (1 << 0)        /* UART has buggy quot LSB */
+#define UART_BUG_TXEN   (1 << 1)        /* UART has buggy TX IIR status */
+#define UART_BUG_NOMSR  (1 << 2)        /* UART has buggy MSR status bits (Au1x00) */
+#define UART_BUG_THRE   (1 << 3)        /* UART has buggy THRE reassertion */
+
+#define PROBE_RSA       (1 << 0)
+#define PROBE_ANY       (~0)
+
+#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
+
+#ifdef CONFIG_SERIAL_8250_SHARE_IRQ
+#define SERIAL8250_SHARE_IRQS 1
+#else
+#define SERIAL8250_SHARE_IRQS 0
+#endif
+
+#if defined(__alpha__) && !defined(CONFIG_PCI)
+/*
+ * Digital did something really horribly wrong with the OUT1 and OUT2
+ * lines on at least some ALPHA's.  The failure mode is that if either
+ * is cleared, the machine locks up with endless interrupts.
+ */
+#define ALPHA_KLUDGE_MCR  (UART_MCR_OUT2 | UART_MCR_OUT1)
+#elif defined(CONFIG_SBC8560)
+/*
+ * WindRiver did something similarly broken on their SBC8560 board. The
+ * UART tristates its IRQ output while OUT2 is clear, but they pulled
+ * the interrupt line _up_ instead of down, so if we register the IRQ
+ * while the UART is in that state, we die in an IRQ storm. */
+#define ALPHA_KLUDGE_MCR (UART_MCR_OUT2)
+#else
+#define ALPHA_KLUDGE_MCR 0
+#endif
diff --git a/drivers/tty/serial/8250_accent.c b/drivers/tty/serial/8250_accent.c
new file mode 100644
index 00000000000..34b51c65119
--- /dev/null
+++ b/drivers/tty/serial/8250_accent.c
@@ -0,0 +1,45 @@
+/*
+ *  Copyright (C) 2005 Russell King.
+ *  Data taken from include/asm-i386/serial.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/serial_8250.h>
+
+#define PORT(_base,_irq)                                \
+        {                                               \
+                .iobase         = _base,                \
+                .irq            = _irq,                 \
+                .uartclk        = 1843200,              \
+                .iotype         = UPIO_PORT,            \
+                .flags          = UPF_BOOT_AUTOCONF,    \
+        }
+
+static struct plat_serial8250_port accent_data[] = {
+        PORT(0x330, 4),
+        PORT(0x338, 4),
+        { },
+};
+
+static struct platform_device accent_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_ACCENT,
+        .dev                    = {
+                .platform_data  = accent_data,
+        },
+};
+
+static int __init accent_init(void)
+{
+        return platform_device_register(&accent_device);
+}
+
+module_init(accent_init);
+
+MODULE_AUTHOR("Russell King");
+MODULE_DESCRIPTION("8250 serial probe module for Accent Async cards");
+MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_acorn.c b/drivers/tty/serial/8250_acorn.c
new file mode 100644
index 00000000000..b0ce8c56f1a
--- /dev/null
+++ b/drivers/tty/serial/8250_acorn.c
@@ -0,0 +1,141 @@
+/*
+ *  linux/drivers/serial/acorn.c
+ *
+ *  Copyright (C) 1996-2003 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/tty.h>
+#include <linux/serial_core.h>
+#include <linux/errno.h>
+#include <linux/ioport.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/init.h>
+
+#include <asm/io.h>
+#include <asm/ecard.h>
+#include <asm/string.h>
+
+#include "8250.h"
+
+#define MAX_PORTS       3
+
+struct serial_card_type {
+        unsigned int    num_ports;
+        unsigned int    uartclk;
+        unsigned int    type;
+        unsigned int    offset[MAX_PORTS];
+};
+
+struct serial_card_info {
+        unsigned int    num_ports;
+        int             ports[MAX_PORTS];
+        void __iomem *vaddr;
+};
+
+static int __devinit
+serial_card_probe(struct expansion_card *ec, const struct ecard_id *id)
+{
+        struct serial_card_info *info;
+        struct serial_card_type *type = id->data;
+        struct uart_port port;
+        unsigned long bus_addr;
+        unsigned int i;
+
+        info = kzalloc(sizeof(struct serial_card_info), GFP_KERNEL);
+        if (!info)
+                return -ENOMEM;
+
+        info->num_ports = type->num_ports;
+
+        bus_addr = ecard_resource_start(ec, type->type);
+        info->vaddr = ecardm_iomap(ec, type->type, 0, 0);
+        if (!info->vaddr) {
+                kfree(info);
+                return -ENOMEM;
+        }
+
+        ecard_set_drvdata(ec, info);
+
+        memset(&port, 0, sizeof(struct uart_port));
+        port.irq        = ec->irq;
+        port.flags      = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+        port.uartclk    = type->uartclk;
+        port.iotype     = UPIO_MEM;
+        port.regshift   = 2;
+        port.dev        = &ec->dev;
+
+        for (i = 0; i < info->num_ports; i ++) {
+                port.membase = info->vaddr + type->offset[i];
+                port.mapbase = bus_addr + type->offset[i];
+
+                info->ports[i] = serial8250_register_port(&port);
+        }
+
+        return 0;
+}
+
+static void __devexit serial_card_remove(struct expansion_card *ec)
+{
+        struct serial_card_info *info = ecard_get_drvdata(ec);
+        int i;
+
+        ecard_set_drvdata(ec, NULL);
+
+        for (i = 0; i < info->num_ports; i++)
+                if (info->ports[i] > 0)
+                        serial8250_unregister_port(info->ports[i]);
+
+        kfree(info);
+}
+
+static struct serial_card_type atomwide_type = {
+        .num_ports      = 3,
+        .uartclk        = 7372800,
+        .type           = ECARD_RES_IOCSLOW,
+        .offset         = { 0x2800, 0x2400, 0x2000 },
+};
+
+static struct serial_card_type serport_type = {
+        .num_ports      = 2,
+        .uartclk        = 3686400,
+        .type           = ECARD_RES_IOCSLOW,
+        .offset         = { 0x2000, 0x2020 },
+};
+
+static const struct ecard_id serial_cids[] = {
+        { MANU_ATOMWIDE,        PROD_ATOMWIDE_3PSERIAL, &atomwide_type  },
+        { MANU_SERPORT,         PROD_SERPORT_DSPORT,    &serport_type   },
+        { 0xffff, 0xffff }
+};
+
+static struct ecard_driver serial_card_driver = {
+        .probe          = serial_card_probe,
+        .remove         = __devexit_p(serial_card_remove),
+        .id_table       = serial_cids,
+        .drv = {
+                .name   = "8250_acorn",
+        },
+};
+
+static int __init serial_card_init(void)
+{
+        return ecard_register_driver(&serial_card_driver);
+}
+
+static void __exit serial_card_exit(void)
+{
+        ecard_remove_driver(&serial_card_driver);
+}
+
+MODULE_AUTHOR("Russell King");
+MODULE_DESCRIPTION("Acorn 8250-compatible serial port expansion card driver");
+MODULE_LICENSE("GPL");
+
+module_init(serial_card_init);
+module_exit(serial_card_exit);
diff --git a/drivers/tty/serial/8250_boca.c b/drivers/tty/serial/8250_boca.c
new file mode 100644
index 00000000000..d125dc10798
--- /dev/null
+++ b/drivers/tty/serial/8250_boca.c
@@ -0,0 +1,59 @@
+/*
+ *  Copyright (C) 2005 Russell King.
+ *  Data taken from include/asm-i386/serial.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/serial_8250.h>
+
+#define PORT(_base,_irq)                                \
+        {                                               \
+                .iobase         = _base,                \
+                .irq            = _irq,                 \
+                .uartclk        = 1843200,              \
+                .iotype         = UPIO_PORT,            \
+                .flags          = UPF_BOOT_AUTOCONF,    \
+        }
+
+static struct plat_serial8250_port boca_data[] = {
+        PORT(0x100, 12),
+        PORT(0x108, 12),
+        PORT(0x110, 12),
+        PORT(0x118, 12),
+        PORT(0x120, 12),
+        PORT(0x128, 12),
+        PORT(0x130, 12),
+        PORT(0x138, 12),
+        PORT(0x140, 12),
+        PORT(0x148, 12),
+        PORT(0x150, 12),
+        PORT(0x158, 12),
+        PORT(0x160, 12),
+        PORT(0x168, 12),
+        PORT(0x170, 12),
+        PORT(0x178, 12),
+        { },
+};
+
+static struct platform_device boca_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_BOCA,
+        .dev                    = {
+                .platform_data  = boca_data,
+        },
+};
+
+static int __init boca_init(void)
+{
+        return platform_device_register(&boca_device);
+}
+
+module_init(boca_init);
+
+MODULE_AUTHOR("Russell King");
+MODULE_DESCRIPTION("8250 serial probe module for Boca cards");
+MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_early.c b/drivers/tty/serial/8250_early.c
new file mode 100644
index 00000000000..eaafb98debe
--- /dev/null
+++ b/drivers/tty/serial/8250_early.c
@@ -0,0 +1,287 @@
+/*
+ * Early serial console for 8250/16550 devices
+ *
+ * (c) Copyright 2004 Hewlett-Packard Development Company, L.P.
+ *      Bjorn Helgaas <bjorn.helgaas@hp.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Based on the 8250.c serial driver, Copyright (C) 2001 Russell King,
+ * and on early_printk.c by Andi Kleen.
+ *
+ * This is for use before the serial driver has initialized, in
+ * particular, before the UARTs have been discovered and named.
+ * Instead of specifying the console device as, e.g., "ttyS0",
+ * we locate the device directly by its MMIO or I/O port address.
+ *
+ * The user can specify the device directly, e.g.,
+ *      earlycon=uart8250,io,0x3f8,9600n8
+ *      earlycon=uart8250,mmio,0xff5e0000,115200n8
+ *      earlycon=uart8250,mmio32,0xff5e0000,115200n8
+ * or
+ *      console=uart8250,io,0x3f8,9600n8
+ *      console=uart8250,mmio,0xff5e0000,115200n8
+ *      console=uart8250,mmio32,0xff5e0000,115200n8
+ */
+
+#include <linux/tty.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/serial_core.h>
+#include <linux/serial_reg.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <asm/io.h>
+#include <asm/serial.h>
+#ifdef CONFIG_FIX_EARLYCON_MEM
+#include <asm/pgtable.h>
+#include <asm/fixmap.h>
+#endif
+
+struct early_serial8250_device {
+        struct uart_port port;
+        char options[16];               /* e.g., 115200n8 */
+        unsigned int baud;
+};
+
+static struct early_serial8250_device early_device;
+
+static unsigned int __init serial_in(struct uart_port *port, int offset)
+{
+        switch (port->iotype) {
+        case UPIO_MEM:
+                return readb(port->membase + offset);
+        case UPIO_MEM32:
+                return readl(port->membase + (offset << 2));
+        case UPIO_PORT:
+                return inb(port->iobase + offset);
+        default:
+                return 0;
+        }
+}
+
+static void __init serial_out(struct uart_port *port, int offset, int value)
+{
+        switch (port->iotype) {
+        case UPIO_MEM:
+                writeb(value, port->membase + offset);
+                break;
+        case UPIO_MEM32:
+                writel(value, port->membase + (offset << 2));
+                break;
+        case UPIO_PORT:
+                outb(value, port->iobase + offset);
+                break;
+        }
+}
+
+#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
+
+static void __init wait_for_xmitr(struct uart_port *port)
+{
+        unsigned int status;
+
+        for (;;) {
+                status = serial_in(port, UART_LSR);
+                if ((status & BOTH_EMPTY) == BOTH_EMPTY)
+                        return;
+                cpu_relax();
+        }
+}
+
+static void __init serial_putc(struct uart_port *port, int c)
+{
+        wait_for_xmitr(port);
+        serial_out(port, UART_TX, c);
+}
+
+static void __init early_serial8250_write(struct console *console,
+                                        const char *s, unsigned int count)
+{
+        struct uart_port *port = &early_device.port;
+        unsigned int ier;
+
+        /* Save the IER and disable interrupts */
+        ier = serial_in(port, UART_IER);
+        serial_out(port, UART_IER, 0);
+
+        uart_console_write(port, s, count, serial_putc);
+
+        /* Wait for transmitter to become empty and restore the IER */
+        wait_for_xmitr(port);
+        serial_out(port, UART_IER, ier);
+}
+
+static unsigned int __init probe_baud(struct uart_port *port)
+{
+        unsigned char lcr, dll, dlm;
+        unsigned int quot;
+
+        lcr = serial_in(port, UART_LCR);
+        serial_out(port, UART_LCR, lcr | UART_LCR_DLAB);
+        dll = serial_in(port, UART_DLL);
+        dlm = serial_in(port, UART_DLM);
+        serial_out(port, UART_LCR, lcr);
+
+        quot = (dlm << 8) | dll;
+        return (port->uartclk / 16) / quot;
+}
+
+static void __init init_port(struct early_serial8250_device *device)
+{
+        struct uart_port *port = &device->port;
+        unsigned int divisor;
+        unsigned char c;
+
+        serial_out(port, UART_LCR, 0x3);        /* 8n1 */
+        serial_out(port, UART_IER, 0);          /* no interrupt */
+        serial_out(port, UART_FCR, 0);          /* no fifo */
+        serial_out(port, UART_MCR, 0x3);        /* DTR + RTS */
+
+        divisor = port->uartclk / (16 * device->baud);
+        c = serial_in(port, UART_LCR);
+        serial_out(port, UART_LCR, c | UART_LCR_DLAB);
+        serial_out(port, UART_DLL, divisor & 0xff);
+        serial_out(port, UART_DLM, (divisor >> 8) & 0xff);
+        serial_out(port, UART_LCR, c & ~UART_LCR_DLAB);
+}
+
+static int __init parse_options(struct early_serial8250_device *device,
+                                                                char *options)
+{
+        struct uart_port *port = &device->port;
+        int mmio, mmio32, length;
+
+        if (!options)
+                return -ENODEV;
+
+        port->uartclk = BASE_BAUD * 16;
+
+        mmio = !strncmp(options, "mmio,", 5);
+        mmio32 = !strncmp(options, "mmio32,", 7);
+        if (mmio || mmio32) {
+                port->iotype = (mmio ? UPIO_MEM : UPIO_MEM32);
+                port->mapbase = simple_strtoul(options + (mmio ? 5 : 7),
+                                               &options, 0);
+                if (mmio32)
+                        port->regshift = 2;
+#ifdef CONFIG_FIX_EARLYCON_MEM
+                set_fixmap_nocache(FIX_EARLYCON_MEM_BASE,
+                                        port->mapbase & PAGE_MASK);
+                port->membase =
+                        (void __iomem *)__fix_to_virt(FIX_EARLYCON_MEM_BASE);
+                port->membase += port->mapbase & ~PAGE_MASK;
+#else
+                port->membase = ioremap_nocache(port->mapbase, 64);
+                if (!port->membase) {
+                        printk(KERN_ERR "%s: Couldn't ioremap 0x%llx\n",
+                                __func__,
+                               (unsigned long long) port->mapbase);
+                        return -ENOMEM;
+                }
+#endif
+        } else if (!strncmp(options, "io,", 3)) {
+                port->iotype = UPIO_PORT;
+                port->iobase = simple_strtoul(options + 3, &options, 0);
+                mmio = 0;
+        } else
+                return -EINVAL;
+
+        options = strchr(options, ',');
+        if (options) {
+                options++;
+                device->baud = simple_strtoul(options, NULL, 0);
+                length = min(strcspn(options, " "), sizeof(device->options));
+                strncpy(device->options, options, length);
+        } else {
+                device->baud = probe_baud(port);
+                snprintf(device->options, sizeof(device->options), "%u",
+                        device->baud);
+        }
+
+        if (mmio || mmio32)
+                printk(KERN_INFO
+                       "Early serial console at MMIO%s 0x%llx (options '%s')\n",
+                        mmio32 ? "32" : "",
+                        (unsigned long long)port->mapbase,
+                        device->options);
+        else
+                printk(KERN_INFO
+                      "Early serial console at I/O port 0x%lx (options '%s')\n",
+                        port->iobase,
+                        device->options);
+
+        return 0;
+}
+
+static struct console early_serial8250_console __initdata = {
+        .name   = "uart",
+        .write  = early_serial8250_write,
+        .flags  = CON_PRINTBUFFER | CON_BOOT,
+        .index  = -1,
+};
+
+static int __init early_serial8250_setup(char *options)
+{
+        struct early_serial8250_device *device = &early_device;
+        int err;
+
+        if (device->port.membase || device->port.iobase)
+                return 0;
+
+        err = parse_options(device, options);
+        if (err < 0)
+                return err;
+
+        init_port(device);
+        return 0;
+}
+
+int __init setup_early_serial8250_console(char *cmdline)
+{
+        char *options;
+        int err;
+
+        options = strstr(cmdline, "uart8250,");
+        if (!options) {
+                options = strstr(cmdline, "uart,");
+                if (!options)
+                        return 0;
+        }
+
+        options = strchr(cmdline, ',') + 1;
+        err = early_serial8250_setup(options);
+        if (err < 0)
+                return err;
+
+        register_console(&early_serial8250_console);
+
+        return 0;
+}
+
+int serial8250_find_port_for_earlycon(void)
+{
+        struct early_serial8250_device *device = &early_device;
+        struct uart_port *port = &device->port;
+        int line;
+        int ret;
+
+        if (!device->port.membase && !device->port.iobase)
+                return -ENODEV;
+
+        line = serial8250_find_port(port);
+        if (line < 0)
+                return -ENODEV;
+
+        ret = update_console_cmdline("uart", 8250,
+                             "ttyS", line, device->options);
+        if (ret < 0)
+                ret = update_console_cmdline("uart", 0,
+                                     "ttyS", line, device->options);
+
+        return ret;
+}
+
+early_param("earlycon", setup_early_serial8250_console);
diff --git a/drivers/tty/serial/8250_exar_st16c554.c b/drivers/tty/serial/8250_exar_st16c554.c
new file mode 100644
index 00000000000..bf53aabf9b5
--- /dev/null
+++ b/drivers/tty/serial/8250_exar_st16c554.c
@@ -0,0 +1,50 @@
+/*
+ *  Written by Paul B Schroeder < pschroeder "at" uplogix "dot" com >
+ *  Based on 8250_boca.
+ *
+ *  Copyright (C) 2005 Russell King.
+ *  Data taken from include/asm-i386/serial.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/serial_8250.h>
+
+#define PORT(_base,_irq)                                \
+        {                                               \
+                .iobase         = _base,                \
+                .irq            = _irq,                 \
+                .uartclk        = 1843200,              \
+                .iotype         = UPIO_PORT,            \
+                .flags          = UPF_BOOT_AUTOCONF,    \
+        }
+
+static struct plat_serial8250_port exar_data[] = {
+        PORT(0x100, 5),
+        PORT(0x108, 5),
+        PORT(0x110, 5),
+        PORT(0x118, 5),
+        { },
+};
+
+static struct platform_device exar_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_EXAR_ST16C554,
+        .dev                    = {
+                .platform_data  = exar_data,
+        },
+};
+
+static int __init exar_init(void)
+{
+        return platform_device_register(&exar_device);
+}
+
+module_init(exar_init);
+
+MODULE_AUTHOR("Paul B Schroeder");
+MODULE_DESCRIPTION("8250 serial probe module for Exar cards");
+MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_fourport.c b/drivers/tty/serial/8250_fourport.c
new file mode 100644
index 00000000000..be158260962
--- /dev/null
+++ b/drivers/tty/serial/8250_fourport.c
@@ -0,0 +1,51 @@
+/*
+ *  Copyright (C) 2005 Russell King.
+ *  Data taken from include/asm-i386/serial.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/serial_8250.h>
+
+#define PORT(_base,_irq)                                                \
+        {                                                               \
+                .iobase         = _base,                                \
+                .irq            = _irq,                                 \
+                .uartclk        = 1843200,                              \
+                .iotype         = UPIO_PORT,                            \
+                .flags          = UPF_BOOT_AUTOCONF | UPF_FOURPORT,     \
+        }
+
+static struct plat_serial8250_port fourport_data[] = {
+        PORT(0x1a0, 9),
+        PORT(0x1a8, 9),
+        PORT(0x1b0, 9),
+        PORT(0x1b8, 9),
+        PORT(0x2a0, 5),
+        PORT(0x2a8, 5),
+        PORT(0x2b0, 5),
+        PORT(0x2b8, 5),
+        { },
+};
+
+static struct platform_device fourport_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_FOURPORT,
+        .dev                    = {
+                .platform_data  = fourport_data,
+        },
+};
+
+static int __init fourport_init(void)
+{
+        return platform_device_register(&fourport_device);
+}
+
+module_init(fourport_init);
+
+MODULE_AUTHOR("Russell King");
+MODULE_DESCRIPTION("8250 serial probe module for AST Fourport cards");
+MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_gsc.c b/drivers/tty/serial/8250_gsc.c
new file mode 100644
index 00000000000..d8c0ffbfa6e
--- /dev/null
+++ b/drivers/tty/serial/8250_gsc.c
@@ -0,0 +1,122 @@
+/*
+ *      Serial Device Initialisation for Lasi/Asp/Wax/Dino
+ *
+ *      (c) Copyright Matthew Wilcox <willy@debian.org> 2001-2002
+ *
+ *      This program is free software; you can redistribute it and/or modify
+ *      it under the terms of the GNU General Public License as published by
+ *      the Free Software Foundation; either version 2 of the License, or
+ *      (at your option) any later version.
+ */
+
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/serial_core.h>
+#include <linux/signal.h>
+#include <linux/types.h>
+
+#include <asm/hardware.h>
+#include <asm/parisc-device.h>
+#include <asm/io.h>
+
+#include "8250.h"
+
+static int __init serial_init_chip(struct parisc_device *dev)
+{
+        struct uart_port port;
+        unsigned long address;
+        int err;
+
+        if (!dev->irq) {
+                /* We find some unattached serial ports by walking native
+                 * busses.  These should be silently ignored.  Otherwise,
+                 * what we have here is a missing parent device, so tell
+                 * the user what they're missing.
+                 */
+                if (parisc_parent(dev)->id.hw_type != HPHW_IOA)
+                        printk(KERN_INFO
+                                "Serial: device 0x%llx not configured.\n"
+                                "Enable support for Wax, Lasi, Asp or Dino.\n",
+                                (unsigned long long)dev->hpa.start);
+                return -ENODEV;
+        }
+
+        address = dev->hpa.start;
+        if (dev->id.sversion != 0x8d)
+                address += 0x800;
+
+        memset(&port, 0, sizeof(port));
+        port.iotype     = UPIO_MEM;
+        /* 7.272727MHz on Lasi.  Assumed the same for Dino, Wax and Timi. */
+        port.uartclk    = 7272727;
+        port.mapbase    = address;
+        port.membase    = ioremap_nocache(address, 16);
+        port.irq        = dev->irq;
+        port.flags      = UPF_BOOT_AUTOCONF;
+        port.dev        = &dev->dev;
+
+        err = serial8250_register_port(&port);
+        if (err < 0) {
+                printk(KERN_WARNING
+                        "serial8250_register_port returned error %d\n", err);
+                iounmap(port.membase);
+                return err;
+        }
+
+        return 0;
+}
+
+static struct parisc_device_id serial_tbl[] = {
+        { HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x00075 },
+        { HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008c },
+        { HPHW_FIO, HVERSION_REV_ANY_ID, HVERSION_ANY_ID, 0x0008d },
+        { 0 }
+};
+
+/* Hack.  Some machines have SERIAL_0 attached to Lasi and SERIAL_1
+ * attached to Dino.  Unfortunately, Dino appears before Lasi in the device
+ * tree.  To ensure that ttyS0 == SERIAL_0, we register two drivers; one
+ * which only knows about Lasi and then a second which will find all the
+ * other serial ports.  HPUX ignores this problem.
+ */
+static struct parisc_device_id lasi_tbl[] = {
+        { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03B, 0x0008C }, /* C1xx/C1xxL */
+        { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03C, 0x0008C }, /* B132L */
+        { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03D, 0x0008C }, /* B160L */
+        { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03E, 0x0008C }, /* B132L+ */
+        { HPHW_FIO, HVERSION_REV_ANY_ID, 0x03F, 0x0008C }, /* B180L+ */
+        { HPHW_FIO, HVERSION_REV_ANY_ID, 0x046, 0x0008C }, /* Rocky2 120 */
+        { HPHW_FIO, HVERSION_REV_ANY_ID, 0x047, 0x0008C }, /* Rocky2 150 */
+        { HPHW_FIO, HVERSION_REV_ANY_ID, 0x04E, 0x0008C }, /* Kiji L2 132 */
+        { HPHW_FIO, HVERSION_REV_ANY_ID, 0x056, 0x0008C }, /* Raven+ */
+        { 0 }
+};
+
+
+MODULE_DEVICE_TABLE(parisc, serial_tbl);
+
+static struct parisc_driver lasi_driver = {
+        .name           = "serial_1",
+        .id_table       = lasi_tbl,
+        .probe          = serial_init_chip,
+};
+
+static struct parisc_driver serial_driver = {
+        .name           = "serial",
+        .id_table       = serial_tbl,
+        .probe          = serial_init_chip,
+};
+
+static int __init probe_serial_gsc(void)
+{
+        register_parisc_driver(&lasi_driver);
+        register_parisc_driver(&serial_driver);
+        return 0;
+}
+
+module_init(probe_serial_gsc);
+
+MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_hp300.c b/drivers/tty/serial/8250_hp300.c
new file mode 100644
index 00000000000..c13438c9301
--- /dev/null
+++ b/drivers/tty/serial/8250_hp300.c
@@ -0,0 +1,327 @@
+/*
+ * Driver for the 98626/98644/internal serial interface on hp300/hp400
+ * (based on the National Semiconductor INS8250/NS16550AF/WD16C552 UARTs)
+ *
+ * Ported from 2.2 and modified to use the normal 8250 driver
+ * by Kars de Jong <jongk@linux-m68k.org>, May 2004.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+#include <linux/delay.h>
+#include <linux/dio.h>
+#include <linux/console.h>
+#include <linux/slab.h>
+#include <asm/io.h>
+
+#include "8250.h"
+
+#if !defined(CONFIG_HPDCA) && !defined(CONFIG_HPAPCI)
+#warning CONFIG_8250 defined but neither CONFIG_HPDCA nor CONFIG_HPAPCI defined, are you sure?
+#endif
+
+#ifdef CONFIG_HPAPCI
+struct hp300_port
+{
+        struct hp300_port *next;        /* next port */
+        int line;                       /* line (tty) number */
+};
+
+static struct hp300_port *hp300_ports;
+#endif
+
+#ifdef CONFIG_HPDCA
+
+static int __devinit hpdca_init_one(struct dio_dev *d,
+                                        const struct dio_device_id *ent);
+static void __devexit hpdca_remove_one(struct dio_dev *d);
+
+static struct dio_device_id hpdca_dio_tbl[] = {
+        { DIO_ID_DCA0 },
+        { DIO_ID_DCA0REM },
+        { DIO_ID_DCA1 },
+        { DIO_ID_DCA1REM },
+        { 0 }
+};
+
+static struct dio_driver hpdca_driver = {
+        .name      = "hpdca",
+        .id_table  = hpdca_dio_tbl,
+        .probe     = hpdca_init_one,
+        .remove    = __devexit_p(hpdca_remove_one),
+};
+
+#endif
+
+static unsigned int num_ports;
+
+extern int hp300_uart_scode;
+
+/* Offset to UART registers from base of DCA */
+#define UART_OFFSET     17
+
+#define DCA_ID          0x01    /* ID (read), reset (write) */
+#define DCA_IC          0x03    /* Interrupt control        */
+
+/* Interrupt control */
+#define DCA_IC_IE       0x80    /* Master interrupt enable  */
+
+#define HPDCA_BAUD_BASE 153600
+
+/* Base address of the Frodo part */
+#define FRODO_BASE      (0x41c000)
+
+/*
+ * Where we find the 8250-like APCI ports, and how far apart they are.
+ */
+#define FRODO_APCIBASE          0x0
+#define FRODO_APCISPACE         0x20
+#define FRODO_APCI_OFFSET(x)    (FRODO_APCIBASE + ((x) * FRODO_APCISPACE))
+
+#define HPAPCI_BAUD_BASE 500400
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+/*
+ * Parse the bootinfo to find descriptions for headless console and
+ * debug serial ports and register them with the 8250 driver.
+ * This function should be called before serial_console_init() is called
+ * to make sure the serial console will be available for use. IA-64 kernel
+ * calls this function from setup_arch() after the EFI and ACPI tables have
+ * been parsed.
+ */
+int __init hp300_setup_serial_console(void)
+{
+        int scode;
+        struct uart_port port;
+
+        memset(&port, 0, sizeof(port));
+
+        if (hp300_uart_scode < 0 || hp300_uart_scode > DIO_SCMAX)
+                return 0;
+
+        if (DIO_SCINHOLE(hp300_uart_scode))
+                return 0;
+
+        scode = hp300_uart_scode;
+
+        /* Memory mapped I/O */
+        port.iotype = UPIO_MEM;
+        port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF;
+        port.type = PORT_UNKNOWN;
+
+        /* Check for APCI console */
+        if (scode == 256) {
+#ifdef CONFIG_HPAPCI
+                printk(KERN_INFO "Serial console is HP APCI 1\n");
+
+                port.uartclk = HPAPCI_BAUD_BASE * 16;
+                port.mapbase = (FRODO_BASE + FRODO_APCI_OFFSET(1));
+                port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
+                port.regshift = 2;
+                add_preferred_console("ttyS", port.line, "9600n8");
+#else
+                printk(KERN_WARNING "Serial console is APCI but support is disabled (CONFIG_HPAPCI)!\n");
+                return 0;
+#endif
+        } else {
+#ifdef CONFIG_HPDCA
+                unsigned long pa = dio_scodetophysaddr(scode);
+                if (!pa)
+                        return 0;
+
+                printk(KERN_INFO "Serial console is HP DCA at select code %d\n", scode);
+
+                port.uartclk = HPDCA_BAUD_BASE * 16;
+                port.mapbase = (pa + UART_OFFSET);
+                port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
+                port.regshift = 1;
+                port.irq = DIO_IPL(pa + DIO_VIRADDRBASE);
+
+                /* Enable board-interrupts */
+                out_8(pa + DIO_VIRADDRBASE + DCA_IC, DCA_IC_IE);
+
+                if (DIO_ID(pa + DIO_VIRADDRBASE) & 0x80)
+                        add_preferred_console("ttyS", port.line, "9600n8");
+#else
+                printk(KERN_WARNING "Serial console is DCA but support is disabled (CONFIG_HPDCA)!\n");
+                return 0;
+#endif
+        }
+
+        if (early_serial_setup(&port) < 0)
+                printk(KERN_WARNING "hp300_setup_serial_console(): early_serial_setup() failed.\n");
+        return 0;
+}
+#endif /* CONFIG_SERIAL_8250_CONSOLE */
+
+#ifdef CONFIG_HPDCA
+static int __devinit hpdca_init_one(struct dio_dev *d,
+                                const struct dio_device_id *ent)
+{
+        struct uart_port port;
+        int line;
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+        if (hp300_uart_scode == d->scode) {
+                /* Already got it. */
+                return 0;
+        }
+#endif
+        memset(&port, 0, sizeof(struct uart_port));
+
+        /* Memory mapped I/O */
+        port.iotype = UPIO_MEM;
+        port.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF;
+        port.irq = d->ipl;
+        port.uartclk = HPDCA_BAUD_BASE * 16;
+        port.mapbase = (d->resource.start + UART_OFFSET);
+        port.membase = (char *)(port.mapbase + DIO_VIRADDRBASE);
+        port.regshift = 1;
+        port.dev = &d->dev;
+        line = serial8250_register_port(&port);
+
+        if (line < 0) {
+                printk(KERN_NOTICE "8250_hp300: register_serial() DCA scode %d"
+                       " irq %d failed\n", d->scode, port.irq);
+                return -ENOMEM;
+        }
+
+        /* Enable board-interrupts */
+        out_8(d->resource.start + DIO_VIRADDRBASE + DCA_IC, DCA_IC_IE);
+        dio_set_drvdata(d, (void *)line);
+
+        /* Reset the DCA */
+        out_8(d->resource.start + DIO_VIRADDRBASE + DCA_ID, 0xff);
+        udelay(100);
+
+        num_ports++;
+
+        return 0;
+}
+#endif
+
+static int __init hp300_8250_init(void)
+{
+        static int called;
+#ifdef CONFIG_HPAPCI
+        int line;
+        unsigned long base;
+        struct uart_port uport;
+        struct hp300_port *port;
+        int i;
+#endif
+        if (called)
+                return -ENODEV;
+        called = 1;
+
+        if (!MACH_IS_HP300)
+                return -ENODEV;
+
+#ifdef CONFIG_HPDCA
+        dio_register_driver(&hpdca_driver);
+#endif
+#ifdef CONFIG_HPAPCI
+        if (hp300_model < HP_400) {
+                if (!num_ports)
+                        return -ENODEV;
+                return 0;
+        }
+        /* These models have the Frodo chip.
+         * Port 0 is reserved for the Apollo Domain keyboard.
+         * Port 1 is either the console or the DCA.
+         */
+        for (i = 1; i < 4; i++) {
+                /* Port 1 is the console on a 425e, on other machines it's
+                 * mapped to DCA.
+                 */
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+                if (i == 1)
+                        continue;
+#endif
+
+                /* Create new serial device */
+                port = kmalloc(sizeof(struct hp300_port), GFP_KERNEL);
+                if (!port)
+                        return -ENOMEM;
+
+                memset(&uport, 0, sizeof(struct uart_port));
+
+                base = (FRODO_BASE + FRODO_APCI_OFFSET(i));
+
+                /* Memory mapped I/O */
+                uport.iotype = UPIO_MEM;
+                uport.flags = UPF_SKIP_TEST | UPF_SHARE_IRQ \
+                              | UPF_BOOT_AUTOCONF;
+                /* XXX - no interrupt support yet */
+                uport.irq = 0;
+                uport.uartclk = HPAPCI_BAUD_BASE * 16;
+                uport.mapbase = base;
+                uport.membase = (char *)(base + DIO_VIRADDRBASE);
+                uport.regshift = 2;
+
+                line = serial8250_register_port(&uport);
+
+                if (line < 0) {
+                        printk(KERN_NOTICE "8250_hp300: register_serial() APCI"
+                               " %d irq %d failed\n", i, uport.irq);
+                        kfree(port);
+                        continue;
+                }
+
+                port->line = line;
+                port->next = hp300_ports;
+                hp300_ports = port;
+
+                num_ports++;
+        }
+#endif
+
+        /* Any boards found? */
+        if (!num_ports)
+                return -ENODEV;
+
+        return 0;
+}
+
+#ifdef CONFIG_HPDCA
+static void __devexit hpdca_remove_one(struct dio_dev *d)
+{
+        int line;
+
+        line = (int) dio_get_drvdata(d);
+        if (d->resource.start) {
+                /* Disable board-interrupts */
+                out_8(d->resource.start + DIO_VIRADDRBASE + DCA_IC, 0);
+        }
+        serial8250_unregister_port(line);
+}
+#endif
+
+static void __exit hp300_8250_exit(void)
+{
+#ifdef CONFIG_HPAPCI
+        struct hp300_port *port, *to_free;
+
+        for (port = hp300_ports; port; ) {
+                serial8250_unregister_port(port->line);
+                to_free = port;
+                port = port->next;
+                kfree(to_free);
+        }
+
+        hp300_ports = NULL;
+#endif
+#ifdef CONFIG_HPDCA
+        dio_unregister_driver(&hpdca_driver);
+#endif
+}
+
+module_init(hp300_8250_init);
+module_exit(hp300_8250_exit);
+MODULE_DESCRIPTION("HP DCA/APCI serial driver");
+MODULE_AUTHOR("Kars de Jong <jongk@linux-m68k.org>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_hub6.c b/drivers/tty/serial/8250_hub6.c
new file mode 100644
index 00000000000..a5c778e83de
--- /dev/null
+++ b/drivers/tty/serial/8250_hub6.c
@@ -0,0 +1,56 @@
+/*
+ *  Copyright (C) 2005 Russell King.
+ *  Data taken from include/asm-i386/serial.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/serial_8250.h>
+
+#define HUB6(card,port)                                                 \
+        {                                                               \
+                .iobase         = 0x302,                                \
+                .irq            = 3,                                    \
+                .uartclk        = 1843200,                              \
+                .iotype         = UPIO_HUB6,                            \
+                .flags          = UPF_BOOT_AUTOCONF,                    \
+                .hub6           = (card) << 6 | (port) << 3 | 1,        \
+        }
+
+static struct plat_serial8250_port hub6_data[] = {
+        HUB6(0, 0),
+        HUB6(0, 1),
+        HUB6(0, 2),
+        HUB6(0, 3),
+        HUB6(0, 4),
+        HUB6(0, 5),
+        HUB6(1, 0),
+        HUB6(1, 1),
+        HUB6(1, 2),
+        HUB6(1, 3),
+        HUB6(1, 4),
+        HUB6(1, 5),
+        { },
+};
+
+static struct platform_device hub6_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_HUB6,
+        .dev                    = {
+                .platform_data  = hub6_data,
+        },
+};
+
+static int __init hub6_init(void)
+{
+        return platform_device_register(&hub6_device);
+}
+
+module_init(hub6_init);
+
+MODULE_AUTHOR("Russell King");
+MODULE_DESCRIPTION("8250 serial probe module for Hub6 cards");
+MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_mca.c b/drivers/tty/serial/8250_mca.c
new file mode 100644
index 00000000000..d20abf04541
--- /dev/null
+++ b/drivers/tty/serial/8250_mca.c
@@ -0,0 +1,61 @@
+/*
+ *  Copyright (C) 2005 Russell King.
+ *  Data taken from include/asm-i386/serial.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/mca.h>
+#include <linux/serial_8250.h>
+
+/*
+ * FIXME: Should we be doing AUTO_IRQ here?
+ */
+#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
+#define MCA_FLAGS       UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ
+#else
+#define MCA_FLAGS       UPF_BOOT_AUTOCONF | UPF_SKIP_TEST
+#endif
+
+#define PORT(_base,_irq)                        \
+        {                                       \
+                .iobase         = _base,        \
+                .irq            = _irq,         \
+                .uartclk        = 1843200,      \
+                .iotype         = UPIO_PORT,    \
+                .flags          = MCA_FLAGS,    \
+        }
+
+static struct plat_serial8250_port mca_data[] = {
+        PORT(0x3220, 3),
+        PORT(0x3228, 3),
+        PORT(0x4220, 3),
+        PORT(0x4228, 3),
+        PORT(0x5220, 3),
+        PORT(0x5228, 3),
+        { },
+};
+
+static struct platform_device mca_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_MCA,
+        .dev                    = {
+                .platform_data  = mca_data,
+        },
+};
+
+static int __init mca_init(void)
+{
+        if (!MCA_bus)
+                return -ENODEV;
+        return platform_device_register(&mca_device);
+}
+
+module_init(mca_init);
+
+MODULE_AUTHOR("Russell King");
+MODULE_DESCRIPTION("8250 serial probe module for MCA ports");
+MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/8250_pci.c b/drivers/tty/serial/8250_pci.c
new file mode 100644
index 00000000000..3abeca2a2a1
--- /dev/null
+++ b/drivers/tty/serial/8250_pci.c
@@ -0,0 +1,4136 @@
+/*
+ *  Probe module for 8250/16550-type PCI serial ports.
+ *
+ *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
+ *  Copyright (C) 2001 Russell King, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/tty.h>
+#include <linux/serial_core.h>
+#include <linux/8250_pci.h>
+#include <linux/bitops.h>
+
+#include <asm/byteorder.h>
+#include <asm/io.h>
+
+#include "8250.h"
+
+#undef SERIAL_DEBUG_PCI
+
+/*
+ * init function returns:
+ *  > 0 - number of ports
+ *  = 0 - use board->num_ports
+ *  < 0 - error
+ */
+struct pci_serial_quirk {
+        u32     vendor;
+        u32     device;
+        u32     subvendor;
+        u32     subdevice;
+        int     (*probe)(struct pci_dev *dev);
+        int     (*init)(struct pci_dev *dev);
+        int     (*setup)(struct serial_private *,
+                         const struct pciserial_board *,
+                         struct uart_port *, int);
+        void    (*exit)(struct pci_dev *dev);
+};
+
+#define PCI_NUM_BAR_RESOURCES   6
+
+struct serial_private {
+        struct pci_dev          *dev;
+        unsigned int            nr;
+        void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
+        struct pci_serial_quirk *quirk;
+        int                     line[0];
+};
+
+static int pci_default_setup(struct serial_private*,
+          const struct pciserial_board*, struct uart_port*, int);
+
+static void moan_device(const char *str, struct pci_dev *dev)
+{
+        printk(KERN_WARNING
+               "%s: %s\n"
+               "Please send the output of lspci -vv, this\n"
+               "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
+               "manufacturer and name of serial board or\n"
+               "modem board to rmk+serial@arm.linux.org.uk.\n",
+               pci_name(dev), str, dev->vendor, dev->device,
+               dev->subsystem_vendor, dev->subsystem_device);
+}
+
+static int
+setup_port(struct serial_private *priv, struct uart_port *port,
+           int bar, int offset, int regshift)
+{
+        struct pci_dev *dev = priv->dev;
+        unsigned long base, len;
+
+        if (bar >= PCI_NUM_BAR_RESOURCES)
+                return -EINVAL;
+
+        base = pci_resource_start(dev, bar);
+
+        if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
+                len =  pci_resource_len(dev, bar);
+
+                if (!priv->remapped_bar[bar])
+                        priv->remapped_bar[bar] = ioremap_nocache(base, len);
+                if (!priv->remapped_bar[bar])
+                        return -ENOMEM;
+
+                port->iotype = UPIO_MEM;
+                port->iobase = 0;
+                port->mapbase = base + offset;
+                port->membase = priv->remapped_bar[bar] + offset;
+                port->regshift = regshift;
+        } else {
+                port->iotype = UPIO_PORT;
+                port->iobase = base + offset;
+                port->mapbase = 0;
+                port->membase = NULL;
+                port->regshift = 0;
+        }
+        return 0;
+}
+
+/*
+ * ADDI-DATA GmbH communication cards <info@addi-data.com>
+ */
+static int addidata_apci7800_setup(struct serial_private *priv,
+                                const struct pciserial_board *board,
+                                struct uart_port *port, int idx)
+{
+        unsigned int bar = 0, offset = board->first_offset;
+        bar = FL_GET_BASE(board->flags);
+
+        if (idx < 2) {
+                offset += idx * board->uart_offset;
+        } else if ((idx >= 2) && (idx < 4)) {
+                bar += 1;
+                offset += ((idx - 2) * board->uart_offset);
+        } else if ((idx >= 4) && (idx < 6)) {
+                bar += 2;
+                offset += ((idx - 4) * board->uart_offset);
+        } else if (idx >= 6) {
+                bar += 3;
+                offset += ((idx - 6) * board->uart_offset);
+        }
+
+        return setup_port(priv, port, bar, offset, board->reg_shift);
+}
+
+/*
+ * AFAVLAB uses a different mixture of BARs and offsets
+ * Not that ugly ;) -- HW
+ */
+static int
+afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
+              struct uart_port *port, int idx)
+{
+        unsigned int bar, offset = board->first_offset;
+
+        bar = FL_GET_BASE(board->flags);
+        if (idx < 4)
+                bar += idx;
+        else {
+                bar = 4;
+                offset += (idx - 4) * board->uart_offset;
+        }
+
+        return setup_port(priv, port, bar, offset, board->reg_shift);
+}
+
+/*
+ * HP's Remote Management Console.  The Diva chip came in several
+ * different versions.  N-class, L2000 and A500 have two Diva chips, each
+ * with 3 UARTs (the third UART on the second chip is unused).  Superdome
+ * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
+ * one Diva chip, but it has been expanded to 5 UARTs.
+ */
+static int pci_hp_diva_init(struct pci_dev *dev)
+{
+        int rc = 0;
+
+        switch (dev->subsystem_device) {
+        case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
+        case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
+        case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
+        case PCI_DEVICE_ID_HP_DIVA_EVEREST:
+                rc = 3;
+                break;
+        case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
+                rc = 2;
+                break;
+        case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
+                rc = 4;
+                break;
+        case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
+        case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
+                rc = 1;
+                break;
+        }
+
+        return rc;
+}
+
+/*
+ * HP's Diva chip puts the 4th/5th serial port further out, and
+ * some serial ports are supposed to be hidden on certain models.
+ */
+static int
+pci_hp_diva_setup(struct serial_private *priv,
+                const struct pciserial_board *board,
+                struct uart_port *port, int idx)
+{
+        unsigned int offset = board->first_offset;
+        unsigned int bar = FL_GET_BASE(board->flags);
+
+        switch (priv->dev->subsystem_device) {
+        case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
+                if (idx == 3)
+                        idx++;
+                break;
+        case PCI_DEVICE_ID_HP_DIVA_EVEREST:
+                if (idx > 0)
+                        idx++;
+                if (idx > 2)
+                        idx++;
+                break;
+        }
+        if (idx > 2)
+                offset = 0x18;
+
+        offset += idx * board->uart_offset;
+
+        return setup_port(priv, port, bar, offset, board->reg_shift);
+}
+
+/*
+ * Added for EKF Intel i960 serial boards
+ */
+static int pci_inteli960ni_init(struct pci_dev *dev)
+{
+        unsigned long oldval;
+
+        if (!(dev->subsystem_device & 0x1000))
+                return -ENODEV;
+
+        /* is firmware started? */
+        pci_read_config_dword(dev, 0x44, (void *)&oldval);
+        if (oldval == 0x00001000L) { /* RESET value */
+                printk(KERN_DEBUG "Local i960 firmware missing");
+                return -ENODEV;
+        }
+        return 0;
+}
+
+/*
+ * Some PCI serial cards using the PLX 9050 PCI interface chip require
+ * that the card interrupt be explicitly enabled or disabled.  This
+ * seems to be mainly needed on card using the PLX which also use I/O
+ * mapped memory.
+ */
+static int pci_plx9050_init(struct pci_dev *dev)
+{
+        u8 irq_config;
+        void __iomem *p;
+
+        if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
+                moan_device("no memory in bar 0", dev);
+                return 0;
+        }
+
+        irq_config = 0x41;
+        if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
+            dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
+                irq_config = 0x43;
+
+        if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
+            (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
+                /*
+                 * As the megawolf cards have the int pins active
+                 * high, and have 2 UART chips, both ints must be
+                 * enabled on the 9050. Also, the UARTS are set in
+                 * 16450 mode by default, so we have to enable the
+                 * 16C950 'enhanced' mode so that we can use the
+                 * deep FIFOs
+                 */
+                irq_config = 0x5b;
+        /*
+         * enable/disable interrupts
+         */
+        p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
+        if (p == NULL)
+                return -ENOMEM;
+        writel(irq_config, p + 0x4c);
+
+        /*
+         * Read the register back to ensure that it took effect.
+         */
+        readl(p + 0x4c);
+        iounmap(p);
+
+        return 0;
+}
+
+static void __devexit pci_plx9050_exit(struct pci_dev *dev)
+{
+        u8 __iomem *p;
+
+        if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
+                return;
+
+        /*
+         * disable interrupts
+         */
+        p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
+        if (p != NULL) {
+                writel(0, p + 0x4c);
+
+                /*
+                 * Read the register back to ensure that it took effect.
+                 */
+                readl(p + 0x4c);
+                iounmap(p);
+        }
+}
+
+#define NI8420_INT_ENABLE_REG   0x38
+#define NI8420_INT_ENABLE_BIT   0x2000
+
+static void __devexit pci_ni8420_exit(struct pci_dev *dev)
+{
+        void __iomem *p;
+        unsigned long base, len;
+        unsigned int bar = 0;
+
+        if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
+                moan_device("no memory in bar", dev);
+                return;
+        }
+
+        base = pci_resource_start(dev, bar);
+        len =  pci_resource_len(dev, bar);
+        p = ioremap_nocache(base, len);
+        if (p == NULL)
+                return;
+
+        /* Disable the CPU Interrupt */
+        writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
+               p + NI8420_INT_ENABLE_REG);
+        iounmap(p);
+}
+
+
+/* MITE registers */
+#define MITE_IOWBSR1    0xc4
+#define MITE_IOWCR1     0xf4
+#define MITE_LCIMR1     0x08
+#define MITE_LCIMR2     0x10
+
+#define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
+
+static void __devexit pci_ni8430_exit(struct pci_dev *dev)
+{
+        void __iomem *p;
+        unsigned long base, len;
+        unsigned int bar = 0;
+
+        if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
+                moan_device("no memory in bar", dev);
+                return;
+        }
+
+        base = pci_resource_start(dev, bar);
+        len =  pci_resource_len(dev, bar);
+        p = ioremap_nocache(base, len);
+        if (p == NULL)
+                return;
+
+        /* Disable the CPU Interrupt */
+        writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
+        iounmap(p);
+}
+
+/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
+static int
+sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
+                struct uart_port *port, int idx)
+{
+        unsigned int bar, offset = board->first_offset;
+
+        bar = 0;
+
+        if (idx < 4) {
+                /* first four channels map to 0, 0x100, 0x200, 0x300 */
+                offset += idx * board->uart_offset;
+        } else if (idx < 8) {
+                /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
+                offset += idx * board->uart_offset + 0xC00;
+        } else /* we have only 8 ports on PMC-OCTALPRO */
+                return 1;
+
+        return setup_port(priv, port, bar, offset, board->reg_shift);
+}
+
+/*
+* This does initialization for PMC OCTALPRO cards:
+* maps the device memory, resets the UARTs (needed, bc
+* if the module is removed and inserted again, the card
+* is in the sleep mode) and enables global interrupt.
+*/
+
+/* global control register offset for SBS PMC-OctalPro */
+#define OCT_REG_CR_OFF          0x500
+
+static int sbs_init(struct pci_dev *dev)
+{
+        u8 __iomem *p;
+
+        p = pci_ioremap_bar(dev, 0);
+
+        if (p == NULL)
+                return -ENOMEM;
+        /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
+        writeb(0x10, p + OCT_REG_CR_OFF);
+        udelay(50);
+        writeb(0x0, p + OCT_REG_CR_OFF);
+
+        /* Set bit-2 (INTENABLE) of Control Register */
+        writeb(0x4, p + OCT_REG_CR_OFF);
+        iounmap(p);
+
+        return 0;
+}
+
+/*
+ * Disables the global interrupt of PMC-OctalPro
+ */
+
+static void __devexit sbs_exit(struct pci_dev *dev)
+{
+        u8 __iomem *p;
+
+        p = pci_ioremap_bar(dev, 0);
+        /* FIXME: What if resource_len < OCT_REG_CR_OFF */
+        if (p != NULL)
+                writeb(0, p + OCT_REG_CR_OFF);
+        iounmap(p);
+}
+
+/*
+ * SIIG serial cards have an PCI interface chip which also controls
+ * the UART clocking frequency. Each UART can be clocked independently
+ * (except cards equipped with 4 UARTs) and initial clocking settings
+ * are stored in the EEPROM chip. It can cause problems because this
+ * version of serial driver doesn't support differently clocked UART's
+ * on single PCI card. To prevent this, initialization functions set
+ * high frequency clocking for all UART's on given card. It is safe (I
+ * hope) because it doesn't touch EEPROM settings to prevent conflicts
+ * with other OSes (like M$ DOS).
+ *
+ *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
+ *
+ * There is two family of SIIG serial cards with different PCI
+ * interface chip and different configuration methods:
+ *     - 10x cards have control registers in IO and/or memory space;
+ *     - 20x cards have control registers in standard PCI configuration space.
+ *
+ * Note: all 10x cards have PCI device ids 0x10..
+ *       all 20x cards have PCI device ids 0x20..
+ *
+ * There are also Quartet Serial cards which use Oxford Semiconductor
+ * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
+ *
+ * Note: some SIIG cards are probed by the parport_serial object.
+ */
+
+#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
+#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
+
+static int pci_siig10x_init(struct pci_dev *dev)
+{
+        u16 data;
+        void __iomem *p;
+
+        switch (dev->device & 0xfff8) {
+        case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
+                data = 0xffdf;
+                break;
+        case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
+                data = 0xf7ff;
+                break;
+        default:                        /* 1S1P, 4S */
+                data = 0xfffb;
+                break;
+        }
+
+        p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
+        if (p == NULL)
+                return -ENOMEM;
+
+        writew(readw(p + 0x28) & data, p + 0x28);
+        readw(p + 0x28);
+        iounmap(p);
+        return 0;
+}
+
+#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
+#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
+
+static int pci_siig20x_init(struct pci_dev *dev)
+{
+        u8 data;
+
+        /* Change clock frequency for the first UART. */
+        pci_read_config_byte(dev, 0x6f, &data);
+        pci_write_config_byte(dev, 0x6f, data & 0xef);
+
+        /* If this card has 2 UART, we have to do the same with second UART. */
+        if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
+            ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
+                pci_read_config_byte(dev, 0x73, &data);
+                pci_write_config_byte(dev, 0x73, data & 0xef);
+        }
+        return 0;
+}
+
+static int pci_siig_init(struct pci_dev *dev)
+{
+        unsigned int type = dev->device & 0xff00;
+
+        if (type == 0x1000)
+                return pci_siig10x_init(dev);
+        else if (type == 0x2000)
+                return pci_siig20x_init(dev);
+
+        moan_device("Unknown SIIG card", dev);
+        return -ENODEV;
+}
+
+static int pci_siig_setup(struct serial_private *priv,
+                          const struct pciserial_board *board,
+                          struct uart_port *port, int idx)
+{
+        unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
+
+        if (idx > 3) {
+                bar = 4;
+                offset = (idx - 4) * 8;
+        }
+
+        return setup_port(priv, port, bar, offset, 0);
+}
+
+/*
+ * Timedia has an explosion of boards, and to avoid the PCI table from
+ * growing *huge*, we use this function to collapse some 70 entries
+ * in the PCI table into one, for sanity's and compactness's sake.
+ */
+static const unsigned short timedia_single_port[] = {
+        0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
+};
+
+static const unsigned short timedia_dual_port[] = {
+        0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
+        0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
+        0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
+        0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
+        0xD079, 0
+};
+
+static const unsigned short timedia_quad_port[] = {
+        0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
+        0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
+        0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
+        0xB157, 0
+};
+
+static const unsigned short timedia_eight_port[] = {
+        0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
+        0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
+};
+
+static const struct timedia_struct {
+        int num;
+        const unsigned short *ids;
+} timedia_data[] = {
+        { 1, timedia_single_port },
+        { 2, timedia_dual_port },
+        { 4, timedia_quad_port },
+        { 8, timedia_eight_port }
+};
+
+/*
+ * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
+ * listing them individually, this driver merely grabs them all with
+ * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
+ * and should be left free to be claimed by parport_serial instead.
+ */
+static int pci_timedia_probe(struct pci_dev *dev)
+{
+        /*
+         * Check the third digit of the subdevice ID
+         * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
+         */
+        if ((dev->subsystem_device & 0x00f0) >= 0x70) {
+                dev_info(&dev->dev,
+                        "ignoring Timedia subdevice %04x for parport_serial\n",
+                        dev->subsystem_device);
+                return -ENODEV;
+        }
+
+        return 0;
+}
+
+static int pci_timedia_init(struct pci_dev *dev)
+{
+        const unsigned short *ids;
+        int i, j;
+
+        for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
+                ids = timedia_data[i].ids;
+                for (j = 0; ids[j]; j++)
+                        if (dev->subsystem_device == ids[j])
+                                return timedia_data[i].num;
+        }
+        return 0;
+}
+
+/*
+ * Timedia/SUNIX uses a mixture of BARs and offsets
+ * Ugh, this is ugly as all hell --- TYT
+ */
+static int
+pci_timedia_setup(struct serial_private *priv,
+                  const struct pciserial_board *board,
+                  struct uart_port *port, int idx)
+{
+        unsigned int bar = 0, offset = board->first_offset;
+
+        switch (idx) {
+        case 0:
+                bar = 0;
+                break;
+        case 1:
+                offset = board->uart_offset;
+                bar = 0;
+                break;
+        case 2:
+                bar = 1;
+                break;
+        case 3:
+                offset = board->uart_offset;
+                /* FALLTHROUGH */
+        case 4: /* BAR 2 */
+        case 5: /* BAR 3 */
+        case 6: /* BAR 4 */
+        case 7: /* BAR 5 */
+                bar = idx - 2;
+        }
+
+        return setup_port(priv, port, bar, offset, board->reg_shift);
+}
+
+/*
+ * Some Titan cards are also a little weird
+ */
+static int
+titan_400l_800l_setup(struct serial_private *priv,
+                      const struct pciserial_board *board,
+                      struct uart_port *port, int idx)
+{
+        unsigned int bar, offset = board->first_offset;
+
+        switch (idx) {
+        case 0:
+                bar = 1;
+                break;
+        case 1:
+                bar = 2;
+                break;
+        default:
+                bar = 4;
+                offset = (idx - 2) * board->uart_offset;
+        }
+
+        return setup_port(priv, port, bar, offset, board->reg_shift);
+}
+
+static int pci_xircom_init(struct pci_dev *dev)
+{
+        msleep(100);
+        return 0;
+}
+
+static int pci_ni8420_init(struct pci_dev *dev)
+{
+        void __iomem *p;
+        unsigned long base, len;
+        unsigned int bar = 0;
+
+        if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
+                moan_device("no memory in bar", dev);
+                return 0;
+        }
+
+        base = pci_resource_start(dev, bar);
+        len =  pci_resource_len(dev, bar);
+        p = ioremap_nocache(base, len);
+        if (p == NULL)
+                return -ENOMEM;
+
+        /* Enable CPU Interrupt */
+        writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
+               p + NI8420_INT_ENABLE_REG);
+
+        iounmap(p);
+        return 0;
+}
+
+#define MITE_IOWBSR1_WSIZE      0xa
+#define MITE_IOWBSR1_WIN_OFFSET 0x800
+#define MITE_IOWBSR1_WENAB      (1 << 7)
+#define MITE_LCIMR1_IO_IE_0     (1 << 24)
+#define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
+#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
+
+static int pci_ni8430_init(struct pci_dev *dev)
+{
+        void __iomem *p;
+        unsigned long base, len;
+        u32 device_window;
+        unsigned int bar = 0;
+
+        if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
+                moan_device("no memory in bar", dev);
+                return 0;
+        }
+
+        base = pci_resource_start(dev, bar);
+        len =  pci_resource_len(dev, bar);
+        p = ioremap_nocache(base, len);
+        if (p == NULL)
+                return -ENOMEM;
+
+        /* Set device window address and size in BAR0 */
+        device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
+                        | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
+        writel(device_window, p + MITE_IOWBSR1);
+
+        /* Set window access to go to RAMSEL IO address space */
+        writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
+               p + MITE_IOWCR1);
+
+        /* Enable IO Bus Interrupt 0 */
+        writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
+
+        /* Enable CPU Interrupt */
+        writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
+
+        iounmap(p);
+        return 0;
+}
+
+/* UART Port Control Register */
+#define NI8430_PORTCON  0x0f
+#define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
+
+static int
+pci_ni8430_setup(struct serial_private *priv,
+                 const struct pciserial_board *board,
+                 struct uart_port *port, int idx)
+{
+        void __iomem *p;
+        unsigned long base, len;
+        unsigned int bar, offset = board->first_offset;
+
+        if (idx >= board->num_ports)
+                return 1;
+
+        bar = FL_GET_BASE(board->flags);
+        offset += idx * board->uart_offset;
+
+        base = pci_resource_start(priv->dev, bar);
+        len =  pci_resource_len(priv->dev, bar);
+        p = ioremap_nocache(base, len);
+
+        /* enable the transceiver */
+        writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
+               p + offset + NI8430_PORTCON);
+
+        iounmap(p);
+
+        return setup_port(priv, port, bar, offset, board->reg_shift);
+}
+
+static int pci_netmos_9900_setup(struct serial_private *priv,
+                                const struct pciserial_board *board,
+                                struct uart_port *port, int idx)
+{
+        unsigned int bar;
+
+        if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
+                /* netmos apparently orders BARs by datasheet layout, so serial
+                 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
+                 */
+                bar = 3 * idx;
+
+                return setup_port(priv, port, bar, 0, board->reg_shift);
+        } else {
+                return pci_default_setup(priv, board, port, idx);
+        }
+}
+
+/* the 99xx series comes with a range of device IDs and a variety
+ * of capabilities:
+ *
+ * 9900 has varying capabilities and can cascade to sub-controllers
+ *   (cascading should be purely internal)
+ * 9904 is hardwired with 4 serial ports
+ * 9912 and 9922 are hardwired with 2 serial ports
+ */
+static int pci_netmos_9900_numports(struct pci_dev *dev)
+{
+        unsigned int c = dev->class;
+        unsigned int pi;
+        unsigned short sub_serports;
+
+        pi = (c & 0xff);
+
+        if (pi == 2) {
+                return 1;
+        } else if ((pi == 0) &&
+                           (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
+                /* two possibilities: 0x30ps encodes number of parallel and
+                 * serial ports, or 0x1000 indicates *something*. This is not
+                 * immediately obvious, since the 2s1p+4s configuration seems
+                 * to offer all functionality on functions 0..2, while still
+                 * advertising the same function 3 as the 4s+2s1p config.
+                 */
+                sub_serports = dev->subsystem_device & 0xf;
+                if (sub_serports > 0) {
+                        return sub_serports;
+                } else {
+                        printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
+                        return 0;
+                }
+        }
+
+        moan_device("unknown NetMos/Mostech program interface", dev);
+        return 0;
+}
+
+static int pci_netmos_init(struct pci_dev *dev)
+{
+        /* subdevice 0x00PS means <P> parallel, <S> serial */
+        unsigned int num_serial = dev->subsystem_device & 0xf;
+
+        if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
+                (dev->device == PCI_DEVICE_ID_NETMOS_9865))
+                return 0;
+
+        if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
+                        dev->subsystem_device == 0x0299)
+                return 0;
+
+        switch (dev->device) { /* FALLTHROUGH on all */
+                case PCI_DEVICE_ID_NETMOS_9904:
+                case PCI_DEVICE_ID_NETMOS_9912:
+                case PCI_DEVICE_ID_NETMOS_9922:
+                case PCI_DEVICE_ID_NETMOS_9900:
+                        num_serial = pci_netmos_9900_numports(dev);
+                        break;
+
+                default:
+                        if (num_serial == 0 ) {
+                                moan_device("unknown NetMos/Mostech device", dev);
+                        }
+        }
+
+        if (num_serial == 0)
+                return -ENODEV;
+
+        return num_serial;
+}
+
+/*
+ * These chips are available with optionally one parallel port and up to
+ * two serial ports. Unfortunately they all have the same product id.
+ *
+ * Basic configuration is done over a region of 32 I/O ports. The base
+ * ioport is called INTA or INTC, depending on docs/other drivers.
+ *
+ * The region of the 32 I/O ports is configured in POSIO0R...
+ */
+
+/* registers */
+#define ITE_887x_MISCR          0x9c
+#define ITE_887x_INTCBAR        0x78
+#define ITE_887x_UARTBAR        0x7c
+#define ITE_887x_PS0BAR         0x10
+#define ITE_887x_POSIO0         0x60
+
+/* I/O space size */
+#define ITE_887x_IOSIZE         32
+/* I/O space size (bits 26-24; 8 bytes = 011b) */
+#define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
+/* I/O space size (bits 26-24; 32 bytes = 101b) */
+#define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
+/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
+#define ITE_887x_POSIO_SPEED            (3 << 29)
+/* enable IO_Space bit */
+#define ITE_887x_POSIO_ENABLE           (1 << 31)
+
+static int pci_ite887x_init(struct pci_dev *dev)
+{
+        /* inta_addr are the configuration addresses of the ITE */
+        static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
+                                                        0x200, 0x280, 0 };
+        int ret, i, type;
+        struct resource *iobase = NULL;
+        u32 miscr, uartbar, ioport;
+
+        /* search for the base-ioport */
+        i = 0;
+        while (inta_addr[i] && iobase == NULL) {
+                iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
+                                                                "ite887x");
+                if (iobase != NULL) {
+                        /* write POSIO0R - speed | size | ioport */
+                        pci_write_config_dword(dev, ITE_887x_POSIO0,
+                                ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
+                                ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
+                        /* write INTCBAR - ioport */
+                        pci_write_config_dword(dev, ITE_887x_INTCBAR,
+                                                                inta_addr[i]);
+                        ret = inb(inta_addr[i]);
+                        if (ret != 0xff) {
+                                /* ioport connected */
+                                break;
+                        }
+                        release_region(iobase->start, ITE_887x_IOSIZE);
+                        iobase = NULL;
+                }
+                i++;
+        }
+
+        if (!inta_addr[i]) {
+                printk(KERN_ERR "ite887x: could not find iobase\n");
+                return -ENODEV;
+        }
+
+        /* start of undocumented type checking (see parport_pc.c) */
+        type = inb(iobase->start + 0x18) & 0x0f;
+
+        switch (type) {
+        case 0x2:       /* ITE8871 (1P) */
+        case 0xa:       /* ITE8875 (1P) */
+                ret = 0;
+                break;
+        case 0xe:       /* ITE8872 (2S1P) */
+                ret = 2;
+                break;
+        case 0x6:       /* ITE8873 (1S) */
+                ret = 1;
+                break;
+        case 0x8:       /* ITE8874 (2S) */
+                ret = 2;
+                break;
+        default:
+                moan_device("Unknown ITE887x", dev);
+                ret = -ENODEV;
+        }
+
+        /* configure all serial ports */
+        for (i = 0; i < ret; i++) {
+                /* read the I/O port from the device */
+                pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
+                                                                &ioport);
+                ioport &= 0x0000FF00;   /* the actual base address */
+                pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
+                        ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
+                        ITE_887x_POSIO_IOSIZE_8 | ioport);
+
+                /* write the ioport to the UARTBAR */
+                pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
+                uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
+                uartbar |= (ioport << (16 * i));        /* set the ioport */
+                pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
+
+                /* get current config */
+                pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
+                /* disable interrupts (UARTx_Routing[3:0]) */
+                miscr &= ~(0xf << (12 - 4 * i));
+                /* activate the UART (UARTx_En) */
+                miscr |= 1 << (23 - i);
+                /* write new config with activated UART */
+                pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
+        }
+
+        if (ret <= 0) {
+                /* the device has no UARTs if we get here */
+                release_region(iobase->start, ITE_887x_IOSIZE);
+        }
+
+        return ret;
+}
+
+static void __devexit pci_ite887x_exit(struct pci_dev *dev)
+{
+        u32 ioport;
+        /* the ioport is bit 0-15 in POSIO0R */
+        pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
+        ioport &= 0xffff;
+        release_region(ioport, ITE_887x_IOSIZE);
+}
+
+/*
+ * Oxford Semiconductor Inc.
+ * Check that device is part of the Tornado range of devices, then determine
+ * the number of ports available on the device.
+ */
+static int pci_oxsemi_tornado_init(struct pci_dev *dev)
+{
+        u8 __iomem *p;
+        unsigned long deviceID;
+        unsigned int  number_uarts = 0;
+
+        /* OxSemi Tornado devices are all 0xCxxx */
+        if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
+            (dev->device & 0xF000) != 0xC000)
+                return 0;
+
+        p = pci_iomap(dev, 0, 5);
+        if (p == NULL)
+                return -ENOMEM;
+
+        deviceID = ioread32(p);
+        /* Tornado device */
+        if (deviceID == 0x07000200) {
+                number_uarts = ioread8(p + 4);
+                printk(KERN_DEBUG
+                        "%d ports detected on Oxford PCI Express device\n",
+                                                                number_uarts);
+        }
+        pci_iounmap(dev, p);
+        return number_uarts;
+}
+
+static int
+pci_default_setup(struct serial_private *priv,
+                  const struct pciserial_board *board,
+                  struct uart_port *port, int idx)
+{
+        unsigned int bar, offset = board->first_offset, maxnr;
+
+        bar = FL_GET_BASE(board->flags);
+        if (board->flags & FL_BASE_BARS)
+                bar += idx;
+        else
+                offset += idx * board->uart_offset;
+
+        maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
+                (board->reg_shift + 3);
+
+        if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
+                return 1;
+
+        return setup_port(priv, port, bar, offset, board->reg_shift);
+}
+
+static int
+ce4100_serial_setup(struct serial_private *priv,
+                  const struct pciserial_board *board,
+                  struct uart_port *port, int idx)
+{
+        int ret;
+
+        ret = setup_port(priv, port, 0, 0, board->reg_shift);
+        port->iotype = UPIO_MEM32;
+        port->type = PORT_XSCALE;
+        port->flags = (port->flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
+        port->regshift = 2;
+
+        return ret;
+}
+
+static int
+pci_omegapci_setup(struct serial_private *priv,
+                      const struct pciserial_board *board,
+                      struct uart_port *port, int idx)
+{
+        return setup_port(priv, port, 2, idx * 8, 0);
+}
+
+static int skip_tx_en_setup(struct serial_private *priv,
+                        const struct pciserial_board *board,
+                        struct uart_port *port, int idx)
+{
+        port->flags |= UPF_NO_TXEN_TEST;
+        printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
+                          "[%04x:%04x] subsystem [%04x:%04x]\n",
+                          priv->dev->vendor,
+                          priv->dev->device,
+                          priv->dev->subsystem_vendor,
+                          priv->dev->subsystem_device);
+
+        return pci_default_setup(priv, board, port, idx);
+}
+
+static int pci_eg20t_init(struct pci_dev *dev)
+{
+#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
+        return -ENODEV;
+#else
+        return 0;
+#endif
+}
+
+/* This should be in linux/pci_ids.h */
+#define PCI_VENDOR_ID_SBSMODULARIO      0x124B
+#define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
+#define PCI_DEVICE_ID_OCTPRO            0x0001
+#define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
+#define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
+#define PCI_SUBDEVICE_ID_POCTAL232      0x0308
+#define PCI_SUBDEVICE_ID_POCTAL422      0x0408
+#define PCI_VENDOR_ID_ADVANTECH         0x13fe
+#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
+#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
+#define PCI_DEVICE_ID_TITAN_200I        0x8028
+#define PCI_DEVICE_ID_TITAN_400I        0x8048
+#define PCI_DEVICE_ID_TITAN_800I        0x8088
+#define PCI_DEVICE_ID_TITAN_800EH       0xA007
+#define PCI_DEVICE_ID_TITAN_800EHB      0xA008
+#define PCI_DEVICE_ID_TITAN_400EH       0xA009
+#define PCI_DEVICE_ID_TITAN_100E        0xA010
+#define PCI_DEVICE_ID_TITAN_200E        0xA012
+#define PCI_DEVICE_ID_TITAN_400E        0xA013
+#define PCI_DEVICE_ID_TITAN_800E        0xA014
+#define PCI_DEVICE_ID_TITAN_200EI       0xA016
+#define PCI_DEVICE_ID_TITAN_200EISI     0xA017
+#define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
+#define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
+#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
+
+/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
+#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
+
+/*
+ * Master list of serial port init/setup/exit quirks.
+ * This does not describe the general nature of the port.
+ * (ie, baud base, number and location of ports, etc)
+ *
+ * This list is ordered alphabetically by vendor then device.
+ * Specific entries must come before more generic entries.
+ */
+static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
+        /*
+        * ADDI-DATA GmbH communication cards <info@addi-data.com>
+        */
+        {
+                .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
+                .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .setup          = addidata_apci7800_setup,
+        },
+        /*
+         * AFAVLAB cards - these may be called via parport_serial
+         *  It is not clear whether this applies to all products.
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_AFAVLAB,
+                .device         = PCI_ANY_ID,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .setup          = afavlab_setup,
+        },
+        /*
+         * HP Diva
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_HP,
+                .device         = PCI_DEVICE_ID_HP_DIVA,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_hp_diva_init,
+                .setup          = pci_hp_diva_setup,
+        },
+        /*
+         * Intel
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_INTEL,
+                .device         = PCI_DEVICE_ID_INTEL_80960_RP,
+                .subvendor      = 0xe4bf,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_inteli960ni_init,
+                .setup          = pci_default_setup,
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_INTEL,
+                .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .setup          = skip_tx_en_setup,
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_INTEL,
+                .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .setup          = skip_tx_en_setup,
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_INTEL,
+                .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .setup          = skip_tx_en_setup,
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_INTEL,
+                .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .setup          = ce4100_serial_setup,
+        },
+        /*
+         * ITE
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_ITE,
+                .device         = PCI_DEVICE_ID_ITE_8872,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_ite887x_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_ite887x_exit),
+        },
+        /*
+         * National Instruments
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_NI,
+                .device         = PCI_DEVICE_ID_NI_PCI23216,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_ni8420_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_ni8420_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_NI,
+                .device         = PCI_DEVICE_ID_NI_PCI2328,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_ni8420_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_ni8420_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_NI,
+                .device         = PCI_DEVICE_ID_NI_PCI2324,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_ni8420_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_ni8420_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_NI,
+                .device         = PCI_DEVICE_ID_NI_PCI2322,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_ni8420_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_ni8420_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_NI,
+                .device         = PCI_DEVICE_ID_NI_PCI2324I,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_ni8420_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_ni8420_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_NI,
+                .device         = PCI_DEVICE_ID_NI_PCI2322I,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_ni8420_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_ni8420_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_NI,
+                .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_ni8420_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_ni8420_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_NI,
+                .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_ni8420_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_ni8420_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_NI,
+                .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_ni8420_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_ni8420_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_NI,
+                .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_ni8420_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_ni8420_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_NI,
+                .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_ni8420_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_ni8420_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_NI,
+                .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_ni8420_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_ni8420_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_NI,
+                .device         = PCI_ANY_ID,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_ni8430_init,
+                .setup          = pci_ni8430_setup,
+                .exit           = __devexit_p(pci_ni8430_exit),
+        },
+        /*
+         * Panacom
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_PANACOM,
+                .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_plx9050_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_plx9050_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_PANACOM,
+                .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_plx9050_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_plx9050_exit),
+        },
+        /*
+         * PLX
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_PLX,
+                .device         = PCI_DEVICE_ID_PLX_9030,
+                .subvendor      = PCI_SUBVENDOR_ID_PERLE,
+                .subdevice      = PCI_ANY_ID,
+                .setup          = pci_default_setup,
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_PLX,
+                .device         = PCI_DEVICE_ID_PLX_9050,
+                .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
+                .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
+                .init           = pci_plx9050_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_plx9050_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_PLX,
+                .device         = PCI_DEVICE_ID_PLX_9050,
+                .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
+                .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
+                .init           = pci_plx9050_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_plx9050_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_PLX,
+                .device         = PCI_DEVICE_ID_PLX_9050,
+                .subvendor      = PCI_VENDOR_ID_PLX,
+                .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
+                .init           = pci_plx9050_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_plx9050_exit),
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_PLX,
+                .device         = PCI_DEVICE_ID_PLX_ROMULUS,
+                .subvendor      = PCI_VENDOR_ID_PLX,
+                .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
+                .init           = pci_plx9050_init,
+                .setup          = pci_default_setup,
+                .exit           = __devexit_p(pci_plx9050_exit),
+        },
+        /*
+         * SBS Technologies, Inc., PMC-OCTALPRO 232
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
+                .device         = PCI_DEVICE_ID_OCTPRO,
+                .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
+                .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
+                .init           = sbs_init,
+                .setup          = sbs_setup,
+                .exit           = __devexit_p(sbs_exit),
+        },
+        /*
+         * SBS Technologies, Inc., PMC-OCTALPRO 422
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
+                .device         = PCI_DEVICE_ID_OCTPRO,
+                .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
+                .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
+                .init           = sbs_init,
+                .setup          = sbs_setup,
+                .exit           = __devexit_p(sbs_exit),
+        },
+        /*
+         * SBS Technologies, Inc., P-Octal 232
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
+                .device         = PCI_DEVICE_ID_OCTPRO,
+                .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
+                .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
+                .init           = sbs_init,
+                .setup          = sbs_setup,
+                .exit           = __devexit_p(sbs_exit),
+        },
+        /*
+         * SBS Technologies, Inc., P-Octal 422
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
+                .device         = PCI_DEVICE_ID_OCTPRO,
+                .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
+                .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
+                .init           = sbs_init,
+                .setup          = sbs_setup,
+                .exit           = __devexit_p(sbs_exit),
+        },
+        /*
+         * SIIG cards - these may be called via parport_serial
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_SIIG,
+                .device         = PCI_ANY_ID,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_siig_init,
+                .setup          = pci_siig_setup,
+        },
+        /*
+         * Titan cards
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_TITAN,
+                .device         = PCI_DEVICE_ID_TITAN_400L,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .setup          = titan_400l_800l_setup,
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_TITAN,
+                .device         = PCI_DEVICE_ID_TITAN_800L,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .setup          = titan_400l_800l_setup,
+        },
+        /*
+         * Timedia cards
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_TIMEDIA,
+                .device         = PCI_DEVICE_ID_TIMEDIA_1889,
+                .subvendor      = PCI_VENDOR_ID_TIMEDIA,
+                .subdevice      = PCI_ANY_ID,
+                .probe          = pci_timedia_probe,
+                .init           = pci_timedia_init,
+                .setup          = pci_timedia_setup,
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_TIMEDIA,
+                .device         = PCI_ANY_ID,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .setup          = pci_timedia_setup,
+        },
+        /*
+         * Xircom cards
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_XIRCOM,
+                .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_xircom_init,
+                .setup          = pci_default_setup,
+        },
+        /*
+         * Netmos cards - these may be called via parport_serial
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_NETMOS,
+                .device         = PCI_ANY_ID,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_netmos_init,
+                .setup          = pci_netmos_9900_setup,
+        },
+        /*
+         * For Oxford Semiconductor Tornado based devices
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_OXSEMI,
+                .device         = PCI_ANY_ID,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_oxsemi_tornado_init,
+                .setup          = pci_default_setup,
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_MAINPINE,
+                .device         = PCI_ANY_ID,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .init           = pci_oxsemi_tornado_init,
+                .setup          = pci_default_setup,
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_DIGI,
+                .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
+                .subvendor              = PCI_SUBVENDOR_ID_IBM,
+                .subdevice              = PCI_ANY_ID,
+                .init                   = pci_oxsemi_tornado_init,
+                .setup          = pci_default_setup,
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_INTEL,
+                .device         = 0x8811,
+                .init           = pci_eg20t_init,
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_INTEL,
+                .device         = 0x8812,
+                .init           = pci_eg20t_init,
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_INTEL,
+                .device         = 0x8813,
+                .init           = pci_eg20t_init,
+        },
+        {
+                .vendor         = PCI_VENDOR_ID_INTEL,
+                .device         = 0x8814,
+                .init           = pci_eg20t_init,
+        },
+        {
+                .vendor         = 0x10DB,
+                .device         = 0x8027,
+                .init           = pci_eg20t_init,
+        },
+        {
+                .vendor         = 0x10DB,
+                .device         = 0x8028,
+                .init           = pci_eg20t_init,
+        },
+        {
+                .vendor         = 0x10DB,
+                .device         = 0x8029,
+                .init           = pci_eg20t_init,
+        },
+        {
+                .vendor         = 0x10DB,
+                .device         = 0x800C,
+                .init           = pci_eg20t_init,
+        },
+        {
+                .vendor         = 0x10DB,
+                .device         = 0x800D,
+                .init           = pci_eg20t_init,
+        },
+        /*
+         * Cronyx Omega PCI (PLX-chip based)
+         */
+        {
+                .vendor         = PCI_VENDOR_ID_PLX,
+                .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .setup          = pci_omegapci_setup,
+         },
+        /*
+         * Default "match everything" terminator entry
+         */
+        {
+                .vendor         = PCI_ANY_ID,
+                .device         = PCI_ANY_ID,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .setup          = pci_default_setup,
+        }
+};
+
+static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
+{
+        return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
+}
+
+static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
+{
+        struct pci_serial_quirk *quirk;
+
+        for (quirk = pci_serial_quirks; ; quirk++)
+                if (quirk_id_matches(quirk->vendor, dev->vendor) &&
+                    quirk_id_matches(quirk->device, dev->device) &&
+                    quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
+                    quirk_id_matches(quirk->subdevice, dev->subsystem_device))
+                        break;
+        return quirk;
+}
+
+static inline int get_pci_irq(struct pci_dev *dev,
+                                const struct pciserial_board *board)
+{
+        if (board->flags & FL_NOIRQ)
+                return 0;
+        else
+                return dev->irq;
+}
+
+/*
+ * This is the configuration table for all of the PCI serial boards
+ * which we support.  It is directly indexed by the pci_board_num_t enum
+ * value, which is encoded in the pci_device_id PCI probe table's
+ * driver_data member.
+ *
+ * The makeup of these names are:
+ *  pbn_bn{_bt}_n_baud{_offsetinhex}
+ *
+ *  bn          = PCI BAR number
+ *  bt          = Index using PCI BARs
+ *  n           = number of serial ports
+ *  baud        = baud rate
+ *  offsetinhex = offset for each sequential port (in hex)
+ *
+ * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
+ *
+ * Please note: in theory if n = 1, _bt infix should make no difference.
+ * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
+ */
+enum pci_board_num_t {
+        pbn_default = 0,
+
+        pbn_b0_1_115200,
+        pbn_b0_2_115200,
+        pbn_b0_4_115200,
+        pbn_b0_5_115200,
+        pbn_b0_8_115200,
+
+        pbn_b0_1_921600,
+        pbn_b0_2_921600,
+        pbn_b0_4_921600,
+
+        pbn_b0_2_1130000,
+
+        pbn_b0_4_1152000,
+
+        pbn_b0_2_1843200,
+        pbn_b0_4_1843200,
+
+        pbn_b0_2_1843200_200,
+        pbn_b0_4_1843200_200,
+        pbn_b0_8_1843200_200,
+
+        pbn_b0_1_4000000,
+
+        pbn_b0_bt_1_115200,
+        pbn_b0_bt_2_115200,
+        pbn_b0_bt_4_115200,
+        pbn_b0_bt_8_115200,
+
+        pbn_b0_bt_1_460800,
+        pbn_b0_bt_2_460800,
+        pbn_b0_bt_4_460800,
+
+        pbn_b0_bt_1_921600,
+        pbn_b0_bt_2_921600,
+        pbn_b0_bt_4_921600,
+        pbn_b0_bt_8_921600,
+
+        pbn_b1_1_115200,
+        pbn_b1_2_115200,
+        pbn_b1_4_115200,
+        pbn_b1_8_115200,
+        pbn_b1_16_115200,
+
+        pbn_b1_1_921600,
+        pbn_b1_2_921600,
+        pbn_b1_4_921600,
+        pbn_b1_8_921600,
+
+        pbn_b1_2_1250000,
+
+        pbn_b1_bt_1_115200,
+        pbn_b1_bt_2_115200,
+        pbn_b1_bt_4_115200,
+
+        pbn_b1_bt_2_921600,
+
+        pbn_b1_1_1382400,
+        pbn_b1_2_1382400,
+        pbn_b1_4_1382400,
+        pbn_b1_8_1382400,
+
+        pbn_b2_1_115200,
+        pbn_b2_2_115200,
+        pbn_b2_4_115200,
+        pbn_b2_8_115200,
+
+        pbn_b2_1_460800,
+        pbn_b2_4_460800,
+        pbn_b2_8_460800,
+        pbn_b2_16_460800,
+
+        pbn_b2_1_921600,
+        pbn_b2_4_921600,
+        pbn_b2_8_921600,
+
+        pbn_b2_8_1152000,
+
+        pbn_b2_bt_1_115200,
+        pbn_b2_bt_2_115200,
+        pbn_b2_bt_4_115200,
+
+        pbn_b2_bt_2_921600,
+        pbn_b2_bt_4_921600,
+
+        pbn_b3_2_115200,
+        pbn_b3_4_115200,
+        pbn_b3_8_115200,
+
+        pbn_b4_bt_2_921600,
+        pbn_b4_bt_4_921600,
+        pbn_b4_bt_8_921600,
+
+        /*
+         * Board-specific versions.
+         */
+        pbn_panacom,
+        pbn_panacom2,
+        pbn_panacom4,
+        pbn_exsys_4055,
+        pbn_plx_romulus,
+        pbn_oxsemi,
+        pbn_oxsemi_1_4000000,
+        pbn_oxsemi_2_4000000,
+        pbn_oxsemi_4_4000000,
+        pbn_oxsemi_8_4000000,
+        pbn_intel_i960,
+        pbn_sgi_ioc3,
+        pbn_computone_4,
+        pbn_computone_6,
+        pbn_computone_8,
+        pbn_sbsxrsio,
+        pbn_exar_XR17C152,
+        pbn_exar_XR17C154,
+        pbn_exar_XR17C158,
+        pbn_exar_ibm_saturn,
+        pbn_pasemi_1682M,
+        pbn_ni8430_2,
+        pbn_ni8430_4,
+        pbn_ni8430_8,
+        pbn_ni8430_16,
+        pbn_ADDIDATA_PCIe_1_3906250,
+        pbn_ADDIDATA_PCIe_2_3906250,
+        pbn_ADDIDATA_PCIe_4_3906250,
+        pbn_ADDIDATA_PCIe_8_3906250,
+        pbn_ce4100_1_115200,
+        pbn_omegapci,
+        pbn_NETMOS9900_2s_115200,
+};
+
+/*
+ * uart_offset - the space between channels
+ * reg_shift   - describes how the UART registers are mapped
+ *               to PCI memory by the card.
+ * For example IER register on SBS, Inc. PMC-OctPro is located at
+ * offset 0x10 from the UART base, while UART_IER is defined as 1
+ * in include/linux/serial_reg.h,
+ * see first lines of serial_in() and serial_out() in 8250.c
+*/
+
+static struct pciserial_board pci_boards[] __devinitdata = {
+        [pbn_default] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 1,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_1_115200] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 1,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_2_115200] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 2,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_4_115200] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 4,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_5_115200] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 5,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_8_115200] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 8,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_1_921600] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 1,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_2_921600] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 2,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_4_921600] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 4,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b0_2_1130000] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 2,
+                .base_baud      = 1130000,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b0_4_1152000] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 4,
+                .base_baud      = 1152000,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b0_2_1843200] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 2,
+                .base_baud      = 1843200,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_4_1843200] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 4,
+                .base_baud      = 1843200,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b0_2_1843200_200] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 2,
+                .base_baud      = 1843200,
+                .uart_offset    = 0x200,
+        },
+        [pbn_b0_4_1843200_200] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 4,
+                .base_baud      = 1843200,
+                .uart_offset    = 0x200,
+        },
+        [pbn_b0_8_1843200_200] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 8,
+                .base_baud      = 1843200,
+                .uart_offset    = 0x200,
+        },
+        [pbn_b0_1_4000000] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 1,
+                .base_baud      = 4000000,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b0_bt_1_115200] = {
+                .flags          = FL_BASE0|FL_BASE_BARS,
+                .num_ports      = 1,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_bt_2_115200] = {
+                .flags          = FL_BASE0|FL_BASE_BARS,
+                .num_ports      = 2,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_bt_4_115200] = {
+                .flags          = FL_BASE0|FL_BASE_BARS,
+                .num_ports      = 4,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_bt_8_115200] = {
+                .flags          = FL_BASE0|FL_BASE_BARS,
+                .num_ports      = 8,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b0_bt_1_460800] = {
+                .flags          = FL_BASE0|FL_BASE_BARS,
+                .num_ports      = 1,
+                .base_baud      = 460800,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_bt_2_460800] = {
+                .flags          = FL_BASE0|FL_BASE_BARS,
+                .num_ports      = 2,
+                .base_baud      = 460800,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_bt_4_460800] = {
+                .flags          = FL_BASE0|FL_BASE_BARS,
+                .num_ports      = 4,
+                .base_baud      = 460800,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b0_bt_1_921600] = {
+                .flags          = FL_BASE0|FL_BASE_BARS,
+                .num_ports      = 1,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_bt_2_921600] = {
+                .flags          = FL_BASE0|FL_BASE_BARS,
+                .num_ports      = 2,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_bt_4_921600] = {
+                .flags          = FL_BASE0|FL_BASE_BARS,
+                .num_ports      = 4,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+        [pbn_b0_bt_8_921600] = {
+                .flags          = FL_BASE0|FL_BASE_BARS,
+                .num_ports      = 8,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b1_1_115200] = {
+                .flags          = FL_BASE1,
+                .num_ports      = 1,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b1_2_115200] = {
+                .flags          = FL_BASE1,
+                .num_ports      = 2,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b1_4_115200] = {
+                .flags          = FL_BASE1,
+                .num_ports      = 4,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b1_8_115200] = {
+                .flags          = FL_BASE1,
+                .num_ports      = 8,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b1_16_115200] = {
+                .flags          = FL_BASE1,
+                .num_ports      = 16,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b1_1_921600] = {
+                .flags          = FL_BASE1,
+                .num_ports      = 1,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+        [pbn_b1_2_921600] = {
+                .flags          = FL_BASE1,
+                .num_ports      = 2,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+        [pbn_b1_4_921600] = {
+                .flags          = FL_BASE1,
+                .num_ports      = 4,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+        [pbn_b1_8_921600] = {
+                .flags          = FL_BASE1,
+                .num_ports      = 8,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+        [pbn_b1_2_1250000] = {
+                .flags          = FL_BASE1,
+                .num_ports      = 2,
+                .base_baud      = 1250000,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b1_bt_1_115200] = {
+                .flags          = FL_BASE1|FL_BASE_BARS,
+                .num_ports      = 1,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b1_bt_2_115200] = {
+                .flags          = FL_BASE1|FL_BASE_BARS,
+                .num_ports      = 2,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b1_bt_4_115200] = {
+                .flags          = FL_BASE1|FL_BASE_BARS,
+                .num_ports      = 4,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b1_bt_2_921600] = {
+                .flags          = FL_BASE1|FL_BASE_BARS,
+                .num_ports      = 2,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b1_1_1382400] = {
+                .flags          = FL_BASE1,
+                .num_ports      = 1,
+                .base_baud      = 1382400,
+                .uart_offset    = 8,
+        },
+        [pbn_b1_2_1382400] = {
+                .flags          = FL_BASE1,
+                .num_ports      = 2,
+                .base_baud      = 1382400,
+                .uart_offset    = 8,
+        },
+        [pbn_b1_4_1382400] = {
+                .flags          = FL_BASE1,
+                .num_ports      = 4,
+                .base_baud      = 1382400,
+                .uart_offset    = 8,
+        },
+        [pbn_b1_8_1382400] = {
+                .flags          = FL_BASE1,
+                .num_ports      = 8,
+                .base_baud      = 1382400,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b2_1_115200] = {
+                .flags          = FL_BASE2,
+                .num_ports      = 1,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b2_2_115200] = {
+                .flags          = FL_BASE2,
+                .num_ports      = 2,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b2_4_115200] = {
+                .flags          = FL_BASE2,
+                .num_ports      = 4,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b2_8_115200] = {
+                .flags          = FL_BASE2,
+                .num_ports      = 8,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b2_1_460800] = {
+                .flags          = FL_BASE2,
+                .num_ports      = 1,
+                .base_baud      = 460800,
+                .uart_offset    = 8,
+        },
+        [pbn_b2_4_460800] = {
+                .flags          = FL_BASE2,
+                .num_ports      = 4,
+                .base_baud      = 460800,
+                .uart_offset    = 8,
+        },
+        [pbn_b2_8_460800] = {
+                .flags          = FL_BASE2,
+                .num_ports      = 8,
+                .base_baud      = 460800,
+                .uart_offset    = 8,
+        },
+        [pbn_b2_16_460800] = {
+                .flags          = FL_BASE2,
+                .num_ports      = 16,
+                .base_baud      = 460800,
+                .uart_offset    = 8,
+         },
+
+        [pbn_b2_1_921600] = {
+                .flags          = FL_BASE2,
+                .num_ports      = 1,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+        [pbn_b2_4_921600] = {
+                .flags          = FL_BASE2,
+                .num_ports      = 4,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+        [pbn_b2_8_921600] = {
+                .flags          = FL_BASE2,
+                .num_ports      = 8,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b2_8_1152000] = {
+                .flags          = FL_BASE2,
+                .num_ports      = 8,
+                .base_baud      = 1152000,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b2_bt_1_115200] = {
+                .flags          = FL_BASE2|FL_BASE_BARS,
+                .num_ports      = 1,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b2_bt_2_115200] = {
+                .flags          = FL_BASE2|FL_BASE_BARS,
+                .num_ports      = 2,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b2_bt_4_115200] = {
+                .flags          = FL_BASE2|FL_BASE_BARS,
+                .num_ports      = 4,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b2_bt_2_921600] = {
+                .flags          = FL_BASE2|FL_BASE_BARS,
+                .num_ports      = 2,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+        [pbn_b2_bt_4_921600] = {
+                .flags          = FL_BASE2|FL_BASE_BARS,
+                .num_ports      = 4,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b3_2_115200] = {
+                .flags          = FL_BASE3,
+                .num_ports      = 2,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b3_4_115200] = {
+                .flags          = FL_BASE3,
+                .num_ports      = 4,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_b3_8_115200] = {
+                .flags          = FL_BASE3,
+                .num_ports      = 8,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+
+        [pbn_b4_bt_2_921600] = {
+                .flags          = FL_BASE4,
+                .num_ports      = 2,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+        [pbn_b4_bt_4_921600] = {
+                .flags          = FL_BASE4,
+                .num_ports      = 4,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+        [pbn_b4_bt_8_921600] = {
+                .flags          = FL_BASE4,
+                .num_ports      = 8,
+                .base_baud      = 921600,
+                .uart_offset    = 8,
+        },
+
+        /*
+         * Entries following this are board-specific.
+         */
+
+        /*
+         * Panacom - IOMEM
+         */
+        [pbn_panacom] = {
+                .flags          = FL_BASE2,
+                .num_ports      = 2,
+                .base_baud      = 921600,
+                .uart_offset    = 0x400,
+                .reg_shift      = 7,
+        },
+        [pbn_panacom2] = {
+                .flags          = FL_BASE2|FL_BASE_BARS,
+                .num_ports      = 2,
+                .base_baud      = 921600,
+                .uart_offset    = 0x400,
+                .reg_shift      = 7,
+        },
+        [pbn_panacom4] = {
+                .flags          = FL_BASE2|FL_BASE_BARS,
+                .num_ports      = 4,
+                .base_baud      = 921600,
+                .uart_offset    = 0x400,
+                .reg_shift      = 7,
+        },
+
+        [pbn_exsys_4055] = {
+                .flags          = FL_BASE2,
+                .num_ports      = 4,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+
+        /* I think this entry is broken - the first_offset looks wrong --rmk */
+        [pbn_plx_romulus] = {
+                .flags          = FL_BASE2,
+                .num_ports      = 4,
+                .base_baud      = 921600,
+                .uart_offset    = 8 << 2,
+                .reg_shift      = 2,
+                .first_offset   = 0x03,
+        },
+
+        /*
+         * This board uses the size of PCI Base region 0 to
+         * signal now many ports are available
+         */
+        [pbn_oxsemi] = {
+                .flags          = FL_BASE0|FL_REGION_SZ_CAP,
+                .num_ports      = 32,
+                .base_baud      = 115200,
+                .uart_offset    = 8,
+        },
+        [pbn_oxsemi_1_4000000] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 1,
+                .base_baud      = 4000000,
+                .uart_offset    = 0x200,
+                .first_offset   = 0x1000,
+        },
+        [pbn_oxsemi_2_4000000] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 2,
+                .base_baud      = 4000000,
+                .uart_offset    = 0x200,
+                .first_offset   = 0x1000,
+        },
+        [pbn_oxsemi_4_4000000] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 4,
+                .base_baud      = 4000000,
+                .uart_offset    = 0x200,
+                .first_offset   = 0x1000,
+        },
+        [pbn_oxsemi_8_4000000] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 8,
+                .base_baud      = 4000000,
+                .uart_offset    = 0x200,
+                .first_offset   = 0x1000,
+        },
+
+
+        /*
+         * EKF addition for i960 Boards form EKF with serial port.
+         * Max 256 ports.
+         */
+        [pbn_intel_i960] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 32,
+                .base_baud      = 921600,
+                .uart_offset    = 8 << 2,
+                .reg_shift      = 2,
+                .first_offset   = 0x10000,
+        },
+        [pbn_sgi_ioc3] = {
+                .flags          = FL_BASE0|FL_NOIRQ,
+                .num_ports      = 1,
+                .base_baud      = 458333,
+                .uart_offset    = 8,
+                .reg_shift      = 0,
+                .first_offset   = 0x20178,
+        },
+
+        /*
+         * Computone - uses IOMEM.
+         */
+        [pbn_computone_4] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 4,
+                .base_baud      = 921600,
+                .uart_offset    = 0x40,
+                .reg_shift      = 2,
+                .first_offset   = 0x200,
+        },
+        [pbn_computone_6] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 6,
+                .base_baud      = 921600,
+                .uart_offset    = 0x40,
+                .reg_shift      = 2,
+                .first_offset   = 0x200,
+        },
+        [pbn_computone_8] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 8,
+                .base_baud      = 921600,
+                .uart_offset    = 0x40,
+                .reg_shift      = 2,
+                .first_offset   = 0x200,
+        },
+        [pbn_sbsxrsio] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 8,
+                .base_baud      = 460800,
+                .uart_offset    = 256,
+                .reg_shift      = 4,
+        },
+        /*
+         * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
+         *  Only basic 16550A support.
+         *  XR17C15[24] are not tested, but they should work.
+         */
+        [pbn_exar_XR17C152] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 2,
+                .base_baud      = 921600,
+                .uart_offset    = 0x200,
+        },
+        [pbn_exar_XR17C154] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 4,
+                .base_baud      = 921600,
+                .uart_offset    = 0x200,
+        },
+        [pbn_exar_XR17C158] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 8,
+                .base_baud      = 921600,
+                .uart_offset    = 0x200,
+        },
+        [pbn_exar_ibm_saturn] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 1,
+                .base_baud      = 921600,
+                .uart_offset    = 0x200,
+        },
+
+        /*
+         * PA Semi PWRficient PA6T-1682M on-chip UART
+         */
+        [pbn_pasemi_1682M] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 1,
+                .base_baud      = 8333333,
+        },
+        /*
+         * National Instruments 843x
+         */
+        [pbn_ni8430_16] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 16,
+                .base_baud      = 3686400,
+                .uart_offset    = 0x10,
+                .first_offset   = 0x800,
+        },
+        [pbn_ni8430_8] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 8,
+                .base_baud      = 3686400,
+                .uart_offset    = 0x10,
+                .first_offset   = 0x800,
+        },
+        [pbn_ni8430_4] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 4,
+                .base_baud      = 3686400,
+                .uart_offset    = 0x10,
+                .first_offset   = 0x800,
+        },
+        [pbn_ni8430_2] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 2,
+                .base_baud      = 3686400,
+                .uart_offset    = 0x10,
+                .first_offset   = 0x800,
+        },
+        /*
+         * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
+         */
+        [pbn_ADDIDATA_PCIe_1_3906250] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 1,
+                .base_baud      = 3906250,
+                .uart_offset    = 0x200,
+                .first_offset   = 0x1000,
+        },
+        [pbn_ADDIDATA_PCIe_2_3906250] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 2,
+                .base_baud      = 3906250,
+                .uart_offset    = 0x200,
+                .first_offset   = 0x1000,
+        },
+        [pbn_ADDIDATA_PCIe_4_3906250] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 4,
+                .base_baud      = 3906250,
+                .uart_offset    = 0x200,
+                .first_offset   = 0x1000,
+        },
+        [pbn_ADDIDATA_PCIe_8_3906250] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 8,
+                .base_baud      = 3906250,
+                .uart_offset    = 0x200,
+                .first_offset   = 0x1000,
+        },
+        [pbn_ce4100_1_115200] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 1,
+                .base_baud      = 921600,
+                .reg_shift      = 2,
+        },
+        [pbn_omegapci] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 8,
+                .base_baud      = 115200,
+                .uart_offset    = 0x200,
+        },
+        [pbn_NETMOS9900_2s_115200] = {
+                .flags          = FL_BASE0,
+                .num_ports      = 2,
+                .base_baud      = 115200,
+        },
+};
+
+static const struct pci_device_id softmodem_blacklist[] = {
+        { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
+        { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
+        { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
+};
+
+/*
+ * Given a complete unknown PCI device, try to use some heuristics to
+ * guess what the configuration might be, based on the pitiful PCI
+ * serial specs.  Returns 0 on success, 1 on failure.
+ */
+static int __devinit
+serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
+{
+        const struct pci_device_id *blacklist;
+        int num_iomem, num_port, first_port = -1, i;
+
+        /*
+         * If it is not a communications device or the programming
+         * interface is greater than 6, give up.
+         *
+         * (Should we try to make guesses for multiport serial devices
+         * later?)
+         */
+        if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
+             ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
+            (dev->class & 0xff) > 6)
+                return -ENODEV;
+
+        /*
+         * Do not access blacklisted devices that are known not to
+         * feature serial ports.
+         */
+        for (blacklist = softmodem_blacklist;
+             blacklist < softmodem_blacklist + ARRAY_SIZE(softmodem_blacklist);
+             blacklist++) {
+                if (dev->vendor == blacklist->vendor &&
+                    dev->device == blacklist->device)
+                        return -ENODEV;
+        }
+
+        num_iomem = num_port = 0;
+        for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
+                if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
+                        num_port++;
+                        if (first_port == -1)
+                                first_port = i;
+                }
+                if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
+                        num_iomem++;
+        }
+
+        /*
+         * If there is 1 or 0 iomem regions, and exactly one port,
+         * use it.  We guess the number of ports based on the IO
+         * region size.
+         */
+        if (num_iomem <= 1 && num_port == 1) {
+                board->flags = first_port;
+                board->num_ports = pci_resource_len(dev, first_port) / 8;
+                return 0;
+        }
+
+        /*
+         * Now guess if we've got a board which indexes by BARs.
+         * Each IO BAR should be 8 bytes, and they should follow
+         * consecutively.
+         */
+        first_port = -1;
+        num_port = 0;
+        for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
+                if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
+                    pci_resource_len(dev, i) == 8 &&
+                    (first_port == -1 || (first_port + num_port) == i)) {
+                        num_port++;
+                        if (first_port == -1)
+                                first_port = i;
+                }
+        }
+
+        if (num_port > 1) {
+                board->flags = first_port | FL_BASE_BARS;
+                board->num_ports = num_port;
+                return 0;
+        }
+
+        return -ENODEV;
+}
+
+static inline int
+serial_pci_matches(const struct pciserial_board *board,
+                   const struct pciserial_board *guessed)
+{
+        return
+            board->num_ports == guessed->num_ports &&
+            board->base_baud == guessed->base_baud &&
+            board->uart_offset == guessed->uart_offset &&
+            board->reg_shift == guessed->reg_shift &&
+            board->first_offset == guessed->first_offset;
+}
+
+struct serial_private *
+pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
+{
+        struct uart_port serial_port;
+        struct serial_private *priv;
+        struct pci_serial_quirk *quirk;
+        int rc, nr_ports, i;
+
+        nr_ports = board->num_ports;
+
+        /*
+         * Find an init and setup quirks.
+         */
+        quirk = find_quirk(dev);
+
+        /*
+         * Run the new-style initialization function.
+         * The initialization function returns:
+         *  <0  - error
+         *   0  - use board->num_ports
+         *  >0  - number of ports
+         */
+        if (quirk->init) {
+                rc = quirk->init(dev);
+                if (rc < 0) {
+                        priv = ERR_PTR(rc);
+                        goto err_out;
+                }
+                if (rc)
+                        nr_ports = rc;
+        }
+
+        priv = kzalloc(sizeof(struct serial_private) +
+                       sizeof(unsigned int) * nr_ports,
+                       GFP_KERNEL);
+        if (!priv) {
+                priv = ERR_PTR(-ENOMEM);
+                goto err_deinit;
+        }
+
+        priv->dev = dev;
+        priv->quirk = quirk;
+
+        memset(&serial_port, 0, sizeof(struct uart_port));
+        serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
+        serial_port.uartclk = board->base_baud * 16;
+        serial_port.irq = get_pci_irq(dev, board);
+        serial_port.dev = &dev->dev;
+
+        for (i = 0; i < nr_ports; i++) {
+                if (quirk->setup(priv, board, &serial_port, i))
+                        break;
+
+#ifdef SERIAL_DEBUG_PCI
+                printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
+                       serial_port.iobase, serial_port.irq, serial_port.iotype);
+#endif
+
+                priv->line[i] = serial8250_register_port(&serial_port);
+                if (priv->line[i] < 0) {
+                        printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
+                        break;
+                }
+        }
+        priv->nr = i;
+        return priv;
+
+err_deinit:
+        if (quirk->exit)
+                quirk->exit(dev);
+err_out:
+        return priv;
+}
+EXPORT_SYMBOL_GPL(pciserial_init_ports);
+
+void pciserial_remove_ports(struct serial_private *priv)
+{
+        struct pci_serial_quirk *quirk;
+        int i;
+
+        for (i = 0; i < priv->nr; i++)
+                serial8250_unregister_port(priv->line[i]);
+
+        for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
+                if (priv->remapped_bar[i])
+                        iounmap(priv->remapped_bar[i]);
+                priv->remapped_bar[i] = NULL;
+        }
+
+        /*
+         * Find the exit quirks.
+         */
+        quirk = find_quirk(priv->dev);
+        if (quirk->exit)
+                quirk->exit(priv->dev);
+
+        kfree(priv);
+}
+EXPORT_SYMBOL_GPL(pciserial_remove_ports);
+
+void pciserial_suspend_ports(struct serial_private *priv)
+{
+        int i;
+
+        for (i = 0; i < priv->nr; i++)
+                if (priv->line[i] >= 0)
+                        serial8250_suspend_port(priv->line[i]);
+}
+EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
+
+void pciserial_resume_ports(struct serial_private *priv)
+{
+        int i;
+
+        /*
+         * Ensure that the board is correctly configured.
+         */
+        if (priv->quirk->init)
+                priv->quirk->init(priv->dev);
+
+        for (i = 0; i < priv->nr; i++)
+                if (priv->line[i] >= 0)
+                        serial8250_resume_port(priv->line[i]);
+}
+EXPORT_SYMBOL_GPL(pciserial_resume_ports);
+
+/*
+ * Probe one serial board.  Unfortunately, there is no rhyme nor reason
+ * to the arrangement of serial ports on a PCI card.
+ */
+static int __devinit
+pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
+{
+        struct pci_serial_quirk *quirk;
+        struct serial_private *priv;
+        const struct pciserial_board *board;
+        struct pciserial_board tmp;
+        int rc;
+
+        quirk = find_quirk(dev);
+        if (quirk->probe) {
+                rc = quirk->probe(dev);
+                if (rc)
+                        return rc;
+        }
+
+        if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
+                printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
+                        ent->driver_data);
+                return -EINVAL;
+        }
+
+        board = &pci_boards[ent->driver_data];
+
+        rc = pci_enable_device(dev);
+        pci_save_state(dev);
+        if (rc)
+                return rc;
+
+        if (ent->driver_data == pbn_default) {
+                /*
+                 * Use a copy of the pci_board entry for this;
+                 * avoid changing entries in the table.
+                 */
+                memcpy(&tmp, board, sizeof(struct pciserial_board));
+                board = &tmp;
+
+                /*
+                 * We matched one of our class entries.  Try to
+                 * determine the parameters of this board.
+                 */
+                rc = serial_pci_guess_board(dev, &tmp);
+                if (rc)
+                        goto disable;
+        } else {
+                /*
+                 * We matched an explicit entry.  If we are able to
+                 * detect this boards settings with our heuristic,
+                 * then we no longer need this entry.
+                 */
+                memcpy(&tmp, &pci_boards[pbn_default],
+                       sizeof(struct pciserial_board));
+                rc = serial_pci_guess_board(dev, &tmp);
+                if (rc == 0 && serial_pci_matches(board, &tmp))
+                        moan_device("Redundant entry in serial pci_table.",
+                                    dev);
+        }
+
+        priv = pciserial_init_ports(dev, board);
+        if (!IS_ERR(priv)) {
+                pci_set_drvdata(dev, priv);
+                return 0;
+        }
+
+        rc = PTR_ERR(priv);
+
+ disable:
+        pci_disable_device(dev);
+        return rc;
+}
+
+static void __devexit pciserial_remove_one(struct pci_dev *dev)
+{
+        struct serial_private *priv = pci_get_drvdata(dev);
+
+        pci_set_drvdata(dev, NULL);
+
+        pciserial_remove_ports(priv);
+
+        pci_disable_device(dev);
+}
+
+#ifdef CONFIG_PM
+static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
+{
+        struct serial_private *priv = pci_get_drvdata(dev);
+
+        if (priv)
+                pciserial_suspend_ports(priv);
+
+        pci_save_state(dev);
+        pci_set_power_state(dev, pci_choose_state(dev, state));
+        return 0;
+}
+
+static int pciserial_resume_one(struct pci_dev *dev)
+{
+        int err;
+        struct serial_private *priv = pci_get_drvdata(dev);
+
+        pci_set_power_state(dev, PCI_D0);
+        pci_restore_state(dev);
+
+        if (priv) {
+                /*
+                 * The device may have been disabled.  Re-enable it.
+                 */
+                err = pci_enable_device(dev);
+                /* FIXME: We cannot simply error out here */
+                if (err)
+                        printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
+                pciserial_resume_ports(priv);
+        }
+        return 0;
+}
+#endif
+
+static struct pci_device_id serial_pci_tbl[] = {
+        /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
+        {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
+                PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
+                pbn_b2_8_921600 },
+        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
+                pbn_b1_8_1382400 },
+        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
+                pbn_b1_4_1382400 },
+        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
+                pbn_b1_2_1382400 },
+        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
+                pbn_b1_8_1382400 },
+        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
+                pbn_b1_4_1382400 },
+        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
+                pbn_b1_2_1382400 },
+        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
+                pbn_b1_8_921600 },
+        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
+                pbn_b1_8_921600 },
+        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
+                pbn_b1_4_921600 },
+        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
+                pbn_b1_4_921600 },
+        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
+                pbn_b1_2_921600 },
+        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
+                pbn_b1_8_921600 },
+        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
+                pbn_b1_8_921600 },
+        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
+                pbn_b1_4_921600 },
+        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
+                pbn_b1_2_1250000 },
+        {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
+                pbn_b0_2_1843200 },
+        {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
+                pbn_b0_4_1843200 },
+        {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
+                PCI_VENDOR_ID_AFAVLAB,
+                PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
+                pbn_b0_4_1152000 },
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
+                pbn_b0_2_1843200_200 },
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
+                pbn_b0_4_1843200_200 },
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
+                pbn_b0_8_1843200_200 },
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
+                pbn_b0_2_1843200_200 },
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
+                pbn_b0_4_1843200_200 },
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
+                pbn_b0_8_1843200_200 },
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
+                pbn_b0_2_1843200_200 },
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
+                pbn_b0_4_1843200_200 },
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
+                pbn_b0_8_1843200_200 },
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
+                pbn_b0_2_1843200_200 },
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
+                pbn_b0_4_1843200_200 },
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
+                PCI_SUBVENDOR_ID_CONNECT_TECH,
+                PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
+                pbn_b0_8_1843200_200 },
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
+                PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
+                0, 0, pbn_exar_ibm_saturn },
+
+        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_bt_1_115200 },
+        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_bt_2_115200 },
+        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_bt_4_115200 },
+        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_bt_2_115200 },
+        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_bt_4_115200 },
+        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_8_115200 },
+        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_8_460800 },
+        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_8_115200 },
+
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_bt_2_115200 },
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_bt_2_921600 },
+        /*
+         * VScom SPCOM800, from sl@s.pl
+         */
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_8_921600 },
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_4_921600 },
+        /* Unknown card - subdevice 0x1584 */
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
+                PCI_VENDOR_ID_PLX,
+                PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
+                pbn_b0_4_115200 },
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
+                PCI_SUBVENDOR_ID_KEYSPAN,
+                PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
+                pbn_panacom },
+        {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_panacom4 },
+        {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_panacom2 },
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
+                PCI_VENDOR_ID_ESDGMBH,
+                PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
+                pbn_b2_4_115200 },
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
+                PCI_SUBVENDOR_ID_CHASE_PCIFAST,
+                PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
+                pbn_b2_4_460800 },
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
+                PCI_SUBVENDOR_ID_CHASE_PCIFAST,
+                PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
+                pbn_b2_8_460800 },
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
+                PCI_SUBVENDOR_ID_CHASE_PCIFAST,
+                PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
+                pbn_b2_16_460800 },
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
+                PCI_SUBVENDOR_ID_CHASE_PCIFAST,
+                PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
+                pbn_b2_16_460800 },
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
+                PCI_SUBVENDOR_ID_CHASE_PCIRAS,
+                PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
+                pbn_b2_4_460800 },
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
+                PCI_SUBVENDOR_ID_CHASE_PCIRAS,
+                PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
+                pbn_b2_8_460800 },
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
+                PCI_SUBVENDOR_ID_EXSYS,
+                PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
+                pbn_exsys_4055 },
+        /*
+         * Megawolf Romulus PCI Serial Card, from Mike Hudson
+         * (Exoray@isys.ca)
+         */
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
+                0x10b5, 0x106a, 0, 0,
+                pbn_plx_romulus },
+        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_4_115200 },
+        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_2_115200 },
+        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_8_115200 },
+        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_8_115200 },
+        {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
+                PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
+                0, 0,
+                pbn_b0_4_921600 },
+        {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
+                PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
+                0, 0,
+                pbn_b0_4_1152000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0x9505,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_2_921600 },
+
+                /*
+                 * The below card is a little controversial since it is the
+                 * subject of a PCI vendor/device ID clash.  (See
+                 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
+                 * For now just used the hex ID 0x950a.
+                 */
+        {       PCI_VENDOR_ID_OXSEMI, 0x950a,
+                PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
+                pbn_b0_2_115200 },
+        {       PCI_VENDOR_ID_OXSEMI, 0x950a,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_2_1130000 },
+        {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
+                PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
+                pbn_b0_1_921600 },
+        {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_4_115200 },
+        {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_2_921600 },
+        {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
+                PCI_ANY_ID , PCI_ANY_ID, 0, 0,
+                pbn_b2_8_1152000 },
+
+        /*
+         * Oxford Semiconductor Inc. Tornado PCI express device range.
+         */
+        {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_2_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_2_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_4_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_4_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_8_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_8_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        /*
+         * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
+         */
+        {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
+                PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
+                PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
+                pbn_oxsemi_2_4000000 },
+        {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
+                PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
+                pbn_oxsemi_4_4000000 },
+        {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
+                PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
+                pbn_oxsemi_8_4000000 },
+
+        /*
+         * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
+         */
+        {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
+                PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_2_4000000 },
+
+        /*
+         * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
+         * from skokodyn@yahoo.com
+         */
+        {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
+                PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
+                pbn_sbsxrsio },
+        {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
+                PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
+                pbn_sbsxrsio },
+        {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
+                PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
+                pbn_sbsxrsio },
+        {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
+                PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
+                pbn_sbsxrsio },
+
+        /*
+         * Digitan DS560-558, from jimd@esoft.com
+         */
+        {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_1_115200 },
+
+        /*
+         * Titan Electronic cards
+         *  The 400L and 800L have a custom setup quirk.
+         */
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_1_921600 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_2_921600 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_4_921600 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_4_921600 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_1_921600 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_bt_2_921600 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_4_921600 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_8_921600 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b4_bt_2_921600 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b4_bt_4_921600 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b4_bt_8_921600 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_4_921600 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_4_921600 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_4_921600 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_1_4000000 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_2_4000000 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_4_4000000 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_8_4000000 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_2_4000000 },
+        {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi_2_4000000 },
+
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_1_460800 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_1_460800 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_1_460800 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_bt_2_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_bt_2_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_bt_2_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_bt_4_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_bt_4_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_bt_4_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_1_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_1_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_1_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_2_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_2_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_2_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_4_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_4_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_4_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_8_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_8_921600 },
+        {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_8_921600 },
+
+        /*
+         * Computone devices submitted by Doug McNash dmcnash@computone.com
+         */
+        {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
+                PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
+                0, 0, pbn_computone_4 },
+        {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
+                PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
+                0, 0, pbn_computone_8 },
+        {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
+                PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
+                0, 0, pbn_computone_6 },
+
+        {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_oxsemi },
+        {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
+                PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_1_921600 },
+
+        /*
+         * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
+         */
+        {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_8_115200 },
+        {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_8_115200 },
+
+        {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_2_115200 },
+        {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_2_115200 },
+        {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_2_115200 },
+        {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_2_115200 },
+        {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_2_115200 },
+        {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_4_460800 },
+        {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_4_460800 },
+        {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_2_460800 },
+        {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_2_460800 },
+        {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_2_460800 },
+        {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_1_115200 },
+        {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_bt_1_460800 },
+
+        /*
+         * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
+         * Cards are identified by their subsystem vendor IDs, which
+         * (in hex) match the model number.
+         *
+         * Note that JC140x are RS422/485 cards which require ox950
+         * ACR = 0x10, and as such are not currently fully supported.
+         */
+        {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
+                0x1204, 0x0004, 0, 0,
+                pbn_b0_4_921600 },
+        {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
+                0x1208, 0x0004, 0, 0,
+                pbn_b0_4_921600 },
+/*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
+                0x1402, 0x0002, 0, 0,
+                pbn_b0_2_921600 }, */
+/*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
+                0x1404, 0x0004, 0, 0,
+                pbn_b0_4_921600 }, */
+        {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
+                0x1208, 0x0004, 0, 0,
+                pbn_b0_4_921600 },
+
+        {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
+                0x1204, 0x0004, 0, 0,
+                pbn_b0_4_921600 },
+        {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
+                0x1208, 0x0004, 0, 0,
+                pbn_b0_4_921600 },
+        {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
+                0x1208, 0x0004, 0, 0,
+                pbn_b0_4_921600 },
+        /*
+         * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
+         */
+        {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_1_1382400 },
+
+        /*
+         * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
+         */
+        {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_1_1382400 },
+
+        /*
+         * RAStel 2 port modem, gerg@moreton.com.au
+         */
+        {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_bt_2_115200 },
+
+        /*
+         * EKF addition for i960 Boards form EKF with serial port
+         */
+        {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
+                0xE4BF, PCI_ANY_ID, 0, 0,
+                pbn_intel_i960 },
+
+        /*
+         * Xircom Cardbus/Ethernet combos
+         */
+        {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_1_115200 },
+        /*
+         * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
+         */
+        {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_1_115200 },
+
+        /*
+         * Untested PCI modems, sent in from various folks...
+         */
+
+        /*
+         * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
+         */
+        {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
+                0x1048, 0x1500, 0, 0,
+                pbn_b1_1_115200 },
+
+        {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
+                0xFF00, 0, 0, 0,
+                pbn_sgi_ioc3 },
+
+        /*
+         * HP Diva card
+         */
+        {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
+                PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
+                pbn_b1_1_115200 },
+        {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_5_115200 },
+        {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b2_1_115200 },
+
+        {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b3_2_115200 },
+        {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b3_4_115200 },
+        {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b3_8_115200 },
+
+        /*
+         * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
+         */
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
+                PCI_ANY_ID, PCI_ANY_ID,
+                0,
+                0, pbn_exar_XR17C152 },
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
+                PCI_ANY_ID, PCI_ANY_ID,
+                0,
+                0, pbn_exar_XR17C154 },
+        {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
+                PCI_ANY_ID, PCI_ANY_ID,
+                0,
+                0, pbn_exar_XR17C158 },
+
+        /*
+         * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
+         */
+        {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b0_1_115200 },
+        /*
+         * ITE
+         */
+        {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
+                PCI_ANY_ID, PCI_ANY_ID,
+                0, 0,
+                pbn_b1_bt_1_115200 },
+
+        /*
+         * IntaShield IS-200
+         */
+        {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
+                pbn_b2_2_115200 },
+        /*
+         * IntaShield IS-400
+         */
+        {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
+                pbn_b2_4_115200 },
+        /*
+         * Perle PCI-RAS cards
+         */
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
+                PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
+                0, 0, pbn_b2_4_921600 },
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
+                PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
+                0, 0, pbn_b2_8_921600 },
+
+        /*
+         * Mainpine series cards: Fairly standard layout but fools
+         * parts of the autodetect in some cases and uses otherwise
+         * unmatched communications subclasses in the PCI Express case
+         */
+
+        {       /* RockForceDUO */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x0200,
+                0, 0, pbn_b0_2_115200 },
+        {       /* RockForceQUATRO */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x0300,
+                0, 0, pbn_b0_4_115200 },
+        {       /* RockForceDUO+ */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x0400,
+                0, 0, pbn_b0_2_115200 },
+        {       /* RockForceQUATRO+ */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x0500,
+                0, 0, pbn_b0_4_115200 },
+        {       /* RockForce+ */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x0600,
+                0, 0, pbn_b0_2_115200 },
+        {       /* RockForce+ */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x0700,
+                0, 0, pbn_b0_4_115200 },
+        {       /* RockForceOCTO+ */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x0800,
+                0, 0, pbn_b0_8_115200 },
+        {       /* RockForceDUO+ */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x0C00,
+                0, 0, pbn_b0_2_115200 },
+        {       /* RockForceQUARTRO+ */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x0D00,
+                0, 0, pbn_b0_4_115200 },
+        {       /* RockForceOCTO+ */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x1D00,
+                0, 0, pbn_b0_8_115200 },
+        {       /* RockForceD1 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x2000,
+                0, 0, pbn_b0_1_115200 },
+        {       /* RockForceF1 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x2100,
+                0, 0, pbn_b0_1_115200 },
+        {       /* RockForceD2 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x2200,
+                0, 0, pbn_b0_2_115200 },
+        {       /* RockForceF2 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x2300,
+                0, 0, pbn_b0_2_115200 },
+        {       /* RockForceD4 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x2400,
+                0, 0, pbn_b0_4_115200 },
+        {       /* RockForceF4 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x2500,
+                0, 0, pbn_b0_4_115200 },
+        {       /* RockForceD8 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x2600,
+                0, 0, pbn_b0_8_115200 },
+        {       /* RockForceF8 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x2700,
+                0, 0, pbn_b0_8_115200 },
+        {       /* IQ Express D1 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x3000,
+                0, 0, pbn_b0_1_115200 },
+        {       /* IQ Express F1 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x3100,
+                0, 0, pbn_b0_1_115200 },
+        {       /* IQ Express D2 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x3200,
+                0, 0, pbn_b0_2_115200 },
+        {       /* IQ Express F2 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x3300,
+                0, 0, pbn_b0_2_115200 },
+        {       /* IQ Express D4 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x3400,
+                0, 0, pbn_b0_4_115200 },
+        {       /* IQ Express F4 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x3500,
+                0, 0, pbn_b0_4_115200 },
+        {       /* IQ Express D8 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x3C00,
+                0, 0, pbn_b0_8_115200 },
+        {       /* IQ Express F8 */
+                PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
+                PCI_VENDOR_ID_MAINPINE, 0x3D00,
+                0, 0, pbn_b0_8_115200 },
+
+
+        /*
+         * PA Semi PA6T-1682M on-chip UART
+         */
+        {       PCI_VENDOR_ID_PASEMI, 0xa004,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_pasemi_1682M },
+
+        /*
+         * National Instruments
+         */
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_16_115200 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_8_115200 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_bt_4_115200 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_bt_2_115200 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_bt_4_115200 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_bt_2_115200 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_16_115200 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_8_115200 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_bt_4_115200 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_bt_2_115200 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_bt_4_115200 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_b1_bt_2_115200 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_ni8430_2 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_ni8430_2 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_ni8430_4 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_ni8430_4 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_ni8430_8 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_ni8430_8 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_ni8430_16 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_ni8430_16 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_ni8430_2 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_ni8430_2 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_ni8430_4 },
+        {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_ni8430_4 },
+
+        /*
+        * ADDI-DATA GmbH communication cards <info@addi-data.com>
+        */
+        {       PCI_VENDOR_ID_ADDIDATA,
+                PCI_DEVICE_ID_ADDIDATA_APCI7500,
+                PCI_ANY_ID,
+                PCI_ANY_ID,
+                0,
+                0,
+                pbn_b0_4_115200 },
+
+        {       PCI_VENDOR_ID_ADDIDATA,
+                PCI_DEVICE_ID_ADDIDATA_APCI7420,
+                PCI_ANY_ID,
+                PCI_ANY_ID,
+                0,
+                0,
+                pbn_b0_2_115200 },
+
+        {       PCI_VENDOR_ID_ADDIDATA,
+                PCI_DEVICE_ID_ADDIDATA_APCI7300,
+                PCI_ANY_ID,
+                PCI_ANY_ID,
+                0,
+                0,
+                pbn_b0_1_115200 },
+
+        {       PCI_VENDOR_ID_ADDIDATA_OLD,
+                PCI_DEVICE_ID_ADDIDATA_APCI7800,
+                PCI_ANY_ID,
+                PCI_ANY_ID,
+                0,
+                0,
+                pbn_b1_8_115200 },
+
+        {       PCI_VENDOR_ID_ADDIDATA,
+                PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
+                PCI_ANY_ID,
+                PCI_ANY_ID,
+                0,
+                0,
+                pbn_b0_4_115200 },
+
+        {       PCI_VENDOR_ID_ADDIDATA,
+                PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
+                PCI_ANY_ID,
+                PCI_ANY_ID,
+                0,
+                0,
+                pbn_b0_2_115200 },
+
+        {       PCI_VENDOR_ID_ADDIDATA,
+                PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
+                PCI_ANY_ID,
+                PCI_ANY_ID,
+                0,
+                0,
+                pbn_b0_1_115200 },
+
+        {       PCI_VENDOR_ID_ADDIDATA,
+                PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
+                PCI_ANY_ID,
+                PCI_ANY_ID,
+                0,
+                0,
+                pbn_b0_4_115200 },
+
+        {       PCI_VENDOR_ID_ADDIDATA,
+                PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
+                PCI_ANY_ID,
+                PCI_ANY_ID,
+                0,
+                0,
+                pbn_b0_2_115200 },
+
+        {       PCI_VENDOR_ID_ADDIDATA,
+                PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
+                PCI_ANY_ID,
+                PCI_ANY_ID,
+                0,
+                0,
+                pbn_b0_1_115200 },
+
+        {       PCI_VENDOR_ID_ADDIDATA,
+                PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
+                PCI_ANY_ID,
+                PCI_ANY_ID,
+                0,
+                0,
+                pbn_b0_8_115200 },
+
+        {       PCI_VENDOR_ID_ADDIDATA,
+                PCI_DEVICE_ID_ADDIDATA_APCIe7500,
+                PCI_ANY_ID,
+                PCI_ANY_ID,
+                0,
+                0,
+                pbn_ADDIDATA_PCIe_4_3906250 },
+
+        {       PCI_VENDOR_ID_ADDIDATA,
+                PCI_DEVICE_ID_ADDIDATA_APCIe7420,
+                PCI_ANY_ID,
+                PCI_ANY_ID,
+                0,
+                0,
+                pbn_ADDIDATA_PCIe_2_3906250 },
+
+        {       PCI_VENDOR_ID_ADDIDATA,
+                PCI_DEVICE_ID_ADDIDATA_APCIe7300,
+                PCI_ANY_ID,
+                PCI_ANY_ID,
+                0,
+                0,
+                pbn_ADDIDATA_PCIe_1_3906250 },
+
+        {       PCI_VENDOR_ID_ADDIDATA,
+                PCI_DEVICE_ID_ADDIDATA_APCIe7800,
+                PCI_ANY_ID,
+                PCI_ANY_ID,
+                0,
+                0,
+                pbn_ADDIDATA_PCIe_8_3906250 },
+
+        {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
+                PCI_VENDOR_ID_IBM, 0x0299,
+                0, 0, pbn_b0_bt_2_115200 },
+
+        {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
+                0xA000, 0x1000,
+                0, 0, pbn_b0_1_115200 },
+
+        /* the 9901 is a rebranded 9912 */
+        {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
+                0xA000, 0x1000,
+                0, 0, pbn_b0_1_115200 },
+
+        {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
+                0xA000, 0x1000,
+                0, 0, pbn_b0_1_115200 },
+
+        {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
+                0xA000, 0x1000,
+                0, 0, pbn_b0_1_115200 },
+
+        {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
+                0xA000, 0x1000,
+                0, 0, pbn_b0_1_115200 },
+
+        {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
+                0xA000, 0x3002,
+                0, 0, pbn_NETMOS9900_2s_115200 },
+
+        /*
+         * Best Connectivity and Rosewill PCI Multi I/O cards
+         */
+
+        {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
+                0xA000, 0x1000,
+                0, 0, pbn_b0_1_115200 },
+
+        {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
+                0xA000, 0x3002,
+                0, 0, pbn_b0_bt_2_115200 },
+
+        {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
+                0xA000, 0x3004,
+                0, 0, pbn_b0_bt_4_115200 },
+        /* Intel CE4100 */
+        {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
+                PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
+                pbn_ce4100_1_115200 },
+
+        /*
+         * Cronyx Omega PCI
+         */
+        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
+                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+                pbn_omegapci },
+
+        /*
+         * These entries match devices with class COMMUNICATION_SERIAL,
+         * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
+         */
+        {       PCI_ANY_ID, PCI_ANY_ID,
+                PCI_ANY_ID, PCI_ANY_ID,
+                PCI_CLASS_COMMUNICATION_SERIAL << 8,
+                0xffff00, pbn_default },
+        {       PCI_ANY_ID, PCI_ANY_ID,
+                PCI_ANY_ID, PCI_ANY_ID,
+                PCI_CLASS_COMMUNICATION_MODEM << 8,
+                0xffff00, pbn_default },
+        {       PCI_ANY_ID, PCI_ANY_ID,
+                PCI_ANY_ID, PCI_ANY_ID,
+                PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
+                0xffff00, pbn_default },
+        { 0, }
+};
+
+static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
+                                                pci_channel_state_t state)
+{
+        struct serial_private *priv = pci_get_drvdata(dev);
+
+        if (state == pci_channel_io_perm_failure)
+                return PCI_ERS_RESULT_DISCONNECT;
+
+        if (priv)
+                pciserial_suspend_ports(priv);
+
+        pci_disable_device(dev);
+
+        return PCI_ERS_RESULT_NEED_RESET;
+}
+
+static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
+{
+        int rc;
+
+        rc = pci_enable_device(dev);
+
+        if (rc)
+                return PCI_ERS_RESULT_DISCONNECT;
+
+        pci_restore_state(dev);
+        pci_save_state(dev);
+
+        return PCI_ERS_RESULT_RECOVERED;
+}
+
+static void serial8250_io_resume(struct pci_dev *dev)
+{
+        struct serial_private *priv = pci_get_drvdata(dev);
+
+        if (priv)
+                pciserial_resume_ports(priv);
+}
+
+static struct pci_error_handlers serial8250_err_handler = {
+        .error_detected = serial8250_io_error_detected,
+        .slot_reset = serial8250_io_slot_reset,
+        .resume = serial8250_io_resume,
+};
+
+static struct pci_driver serial_pci_driver = {
+        .name           = "serial",
+        .probe          = pciserial_init_one,
+        .remove         = __devexit_p(pciserial_remove_one),
+#ifdef CONFIG_PM
+        .suspend        = pciserial_suspend_one,
+        .resume         = pciserial_resume_one,
+#endif
+        .id_table       = serial_pci_tbl,
+        .err_handler    = &serial8250_err_handler,
+};
+
+static int __init serial8250_pci_init(void)
+{
+        return pci_register_driver(&serial_pci_driver);
+}
+
+static void __exit serial8250_pci_exit(void)
+{
+        pci_unregister_driver(&serial_pci_driver);
+}
+
+module_init(serial8250_pci_init);
+module_exit(serial8250_pci_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
+MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
diff --git a/drivers/tty/serial/8250_pnp.c b/drivers/tty/serial/8250_pnp.c
new file mode 100644
index 00000000000..a2f236510ff
--- /dev/null
+++ b/drivers/tty/serial/8250_pnp.c
@@ -0,0 +1,524 @@
+/*
+ *  Probe module for 8250/16550-type ISAPNP serial ports.
+ *
+ *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
+ *
+ *  Copyright (C) 2001 Russell King, All Rights Reserved.
+ *
+ *  Ported to the Linux PnP Layer - (C) Adam Belay.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/pnp.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/serial_core.h>
+#include <linux/bitops.h>
+
+#include <asm/byteorder.h>
+
+#include "8250.h"
+
+#define UNKNOWN_DEV 0x3000
+
+
+static const struct pnp_device_id pnp_dev_table[] = {
+        /* Archtek America Corp. */
+        /* Archtek SmartLink Modem 3334BT Plug & Play */
+        {       "AAC000F",              0       },
+        /* Anchor Datacomm BV */
+        /* SXPro 144 External Data Fax Modem Plug & Play */
+        {       "ADC0001",              0       },
+        /* SXPro 288 External Data Fax Modem Plug & Play */
+        {       "ADC0002",              0       },
+        /* PROLiNK 1456VH ISA PnP K56flex Fax Modem */
+        {       "AEI0250",              0       },
+        /* Actiontec ISA PNP 56K X2 Fax Modem */
+        {       "AEI1240",              0       },
+        /* Rockwell 56K ACF II Fax+Data+Voice Modem */
+        {       "AKY1021",              0 /*SPCI_FL_NO_SHIRQ*/  },
+        /* AZT3005 PnP SOUND DEVICE */
+        {       "AZT4001",              0       },
+        /* Best Data Products Inc. Smart One 336F PnP Modem */
+        {       "BDP3336",              0       },
+        /*  Boca Research */
+        /* Boca Complete Ofc Communicator 14.4 Data-FAX */
+        {       "BRI0A49",              0       },
+        /* Boca Research 33,600 ACF Modem */
+        {       "BRI1400",              0       },
+        /* Boca 33.6 Kbps Internal FD34FSVD */
+        {       "BRI3400",              0       },
+        /* Boca 33.6 Kbps Internal FD34FSVD */
+        {       "BRI0A49",              0       },
+        /* Best Data Products Inc. Smart One 336F PnP Modem */
+        {       "BDP3336",              0       },
+        /* Computer Peripherals Inc */
+        /* EuroViVa CommCenter-33.6 SP PnP */
+        {       "CPI4050",              0       },
+        /* Creative Labs */
+        /* Creative Labs Phone Blaster 28.8 DSVD PnP Voice */
+        {       "CTL3001",              0       },
+        /* Creative Labs Modem Blaster 28.8 DSVD PnP Voice */
+        {       "CTL3011",              0       },
+        /* Davicom ISA 33.6K Modem */
+        {       "DAV0336",              0       },
+        /* Creative */
+        /* Creative Modem Blaster Flash56 DI5601-1 */
+        {       "DMB1032",              0       },
+        /* Creative Modem Blaster V.90 DI5660 */
+        {       "DMB2001",              0       },
+        /* E-Tech */
+        /* E-Tech CyberBULLET PC56RVP */
+        {       "ETT0002",              0       },
+        /* FUJITSU */
+        /* Fujitsu 33600 PnP-I2 R Plug & Play */
+        {       "FUJ0202",              0       },
+        /* Fujitsu FMV-FX431 Plug & Play */
+        {       "FUJ0205",              0       },
+        /* Fujitsu 33600 PnP-I4 R Plug & Play */
+        {       "FUJ0206",              0       },
+        /* Fujitsu Fax Voice 33600 PNP-I5 R Plug & Play */
+        {       "FUJ0209",              0       },
+        /* Archtek America Corp. */
+        /* Archtek SmartLink Modem 3334BT Plug & Play */
+        {       "GVC000F",              0       },
+        /* Archtek SmartLink Modem 3334BRV 33.6K Data Fax Voice */
+        {       "GVC0303",              0       },
+        /* Hayes */
+        /* Hayes Optima 288 V.34-V.FC + FAX + Voice Plug & Play */
+        {       "HAY0001",              0       },
+        /* Hayes Optima 336 V.34 + FAX + Voice PnP */
+        {       "HAY000C",              0       },
+        /* Hayes Optima 336B V.34 + FAX + Voice PnP */
+        {       "HAY000D",              0       },
+        /* Hayes Accura 56K Ext Fax Modem PnP */
+        {       "HAY5670",              0       },
+        /* Hayes Accura 56K Ext Fax Modem PnP */
+        {       "HAY5674",              0       },
+        /* Hayes Accura 56K Fax Modem PnP */
+        {       "HAY5675",              0       },
+        /* Hayes 288, V.34 + FAX */
+        {       "HAYF000",              0       },
+        /* Hayes Optima 288 V.34 + FAX + Voice, Plug & Play */
+        {       "HAYF001",              0       },
+        /* IBM */
+        /* IBM Thinkpad 701 Internal Modem Voice */
+        {       "IBM0033",              0       },
+        /* Intermec */
+        /* Intermec CV60 touchscreen port */
+        {       "PNP4972",              0       },
+        /* Intertex */
+        /* Intertex 28k8 33k6 Voice EXT PnP */
+        {       "IXDC801",              0       },
+        /* Intertex 33k6 56k Voice EXT PnP */
+        {       "IXDC901",              0       },
+        /* Intertex 28k8 33k6 Voice SP EXT PnP */
+        {       "IXDD801",              0       },
+        /* Intertex 33k6 56k Voice SP EXT PnP */
+        {       "IXDD901",              0       },
+        /* Intertex 28k8 33k6 Voice SP INT PnP */
+        {       "IXDF401",              0       },
+        /* Intertex 28k8 33k6 Voice SP EXT PnP */
+        {       "IXDF801",              0       },
+        /* Intertex 33k6 56k Voice SP EXT PnP */
+        {       "IXDF901",              0       },
+        /* Kortex International */
+        /* KORTEX 28800 Externe PnP */
+        {       "KOR4522",              0       },
+        /* KXPro 33.6 Vocal ASVD PnP */
+        {       "KORF661",              0       },
+        /* Lasat */
+        /* LASAT Internet 33600 PnP */
+        {       "LAS4040",              0       },
+        /* Lasat Safire 560 PnP */
+        {       "LAS4540",              0       },
+        /* Lasat Safire 336  PnP */
+        {       "LAS5440",              0       },
+        /* Microcom, Inc. */
+        /* Microcom TravelPorte FAST V.34 Plug & Play */
+        {       "MNP0281",              0       },
+        /* Microcom DeskPorte V.34 FAST or FAST+ Plug & Play */
+        {       "MNP0336",              0       },
+        /* Microcom DeskPorte FAST EP 28.8 Plug & Play */
+        {       "MNP0339",              0       },
+        /* Microcom DeskPorte 28.8P Plug & Play */
+        {       "MNP0342",              0       },
+        /* Microcom DeskPorte FAST ES 28.8 Plug & Play */
+        {       "MNP0500",              0       },
+        /* Microcom DeskPorte FAST ES 28.8 Plug & Play */
+        {       "MNP0501",              0       },
+        /* Microcom DeskPorte 28.8S Internal Plug & Play */
+        {       "MNP0502",              0       },
+        /* Motorola */
+        /* Motorola BitSURFR Plug & Play */
+        {       "MOT1105",              0       },
+        /* Motorola TA210 Plug & Play */
+        {       "MOT1111",              0       },
+        /* Motorola HMTA 200 (ISDN) Plug & Play */
+        {       "MOT1114",              0       },
+        /* Motorola BitSURFR Plug & Play */
+        {       "MOT1115",              0       },
+        /* Motorola Lifestyle 28.8 Internal */
+        {       "MOT1190",              0       },
+        /* Motorola V.3400 Plug & Play */
+        {       "MOT1501",              0       },
+        /* Motorola Lifestyle 28.8 V.34 Plug & Play */
+        {       "MOT1502",              0       },
+        /* Motorola Power 28.8 V.34 Plug & Play */
+        {       "MOT1505",              0       },
+        /* Motorola ModemSURFR External 28.8 Plug & Play */
+        {       "MOT1509",              0       },
+        /* Motorola Premier 33.6 Desktop Plug & Play */
+        {       "MOT150A",              0       },
+        /* Motorola VoiceSURFR 56K External PnP */
+        {       "MOT150F",              0       },
+        /* Motorola ModemSURFR 56K External PnP */
+        {       "MOT1510",              0       },
+        /* Motorola ModemSURFR 56K Internal PnP */
+        {       "MOT1550",              0       },
+        /* Motorola ModemSURFR Internal 28.8 Plug & Play */
+        {       "MOT1560",              0       },
+        /* Motorola Premier 33.6 Internal Plug & Play */
+        {       "MOT1580",              0       },
+        /* Motorola OnlineSURFR 28.8 Internal Plug & Play */
+        {       "MOT15B0",              0       },
+        /* Motorola VoiceSURFR 56K Internal PnP */
+        {       "MOT15F0",              0       },
+        /* Com 1 */
+        /*  Deskline K56 Phone System PnP */
+        {       "MVX00A1",              0       },
+        /* PC Rider K56 Phone System PnP */
+        {       "MVX00F2",              0       },
+        /* NEC 98NOTE SPEAKER PHONE FAX MODEM(33600bps) */
+        {       "nEC8241",              0       },
+        /* Pace 56 Voice Internal Plug & Play Modem */
+        {       "PMC2430",              0       },
+        /* Generic */
+        /* Generic standard PC COM port  */
+        {       "PNP0500",              0       },
+        /* Generic 16550A-compatible COM port */
+        {       "PNP0501",              0       },
+        /* Compaq 14400 Modem */
+        {       "PNPC000",              0       },
+        /* Compaq 2400/9600 Modem */
+        {       "PNPC001",              0       },
+        /* Dial-Up Networking Serial Cable between 2 PCs */
+        {       "PNPC031",              0       },
+        /* Dial-Up Networking Parallel Cable between 2 PCs */
+        {       "PNPC032",              0       },
+        /* Standard 9600 bps Modem */
+        {       "PNPC100",              0       },
+        /* Standard 14400 bps Modem */
+        {       "PNPC101",              0       },
+        /*  Standard 28800 bps Modem*/
+        {       "PNPC102",              0       },
+        /*  Standard Modem*/
+        {       "PNPC103",              0       },
+        /*  Standard 9600 bps Modem*/
+        {       "PNPC104",              0       },
+        /*  Standard 14400 bps Modem*/
+        {       "PNPC105",              0       },
+        /*  Standard 28800 bps Modem*/
+        {       "PNPC106",              0       },
+        /*  Standard Modem */
+        {       "PNPC107",              0       },
+        /* Standard 9600 bps Modem */
+        {       "PNPC108",              0       },
+        /* Standard 14400 bps Modem */
+        {       "PNPC109",              0       },
+        /* Standard 28800 bps Modem */
+        {       "PNPC10A",              0       },
+        /* Standard Modem */
+        {       "PNPC10B",              0       },
+        /* Standard 9600 bps Modem */
+        {       "PNPC10C",              0       },
+        /* Standard 14400 bps Modem */
+        {       "PNPC10D",              0       },
+        /* Standard 28800 bps Modem */
+        {       "PNPC10E",              0       },
+        /* Standard Modem */
+        {       "PNPC10F",              0       },
+        /* Standard PCMCIA Card Modem */
+        {       "PNP2000",              0       },
+        /* Rockwell */
+        /* Modular Technology */
+        /* Rockwell 33.6 DPF Internal PnP */
+        /* Modular Technology 33.6 Internal PnP */
+        {       "ROK0030",              0       },
+        /* Kortex International */
+        /* KORTEX 14400 Externe PnP */
+        {       "ROK0100",              0       },
+        /* Rockwell 28.8 */
+        {       "ROK4120",              0       },
+        /* Viking Components, Inc */
+        /* Viking 28.8 INTERNAL Fax+Data+Voice PnP */
+        {       "ROK4920",              0       },
+        /* Rockwell */
+        /* British Telecom */
+        /* Modular Technology */
+        /* Rockwell 33.6 DPF External PnP */
+        /* BT Prologue 33.6 External PnP */
+        /* Modular Technology 33.6 External PnP */
+        {       "RSS00A0",              0       },
+        /* Viking 56K FAX INT */
+        {       "RSS0262",              0       },
+        /* K56 par,VV,Voice,Speakphone,AudioSpan,PnP */
+        {       "RSS0250",              0       },
+        /* SupraExpress 28.8 Data/Fax PnP modem */
+        {       "SUP1310",              0       },
+        /* SupraExpress 336i PnP Voice Modem */
+        {       "SUP1381",              0       },
+        /* SupraExpress 33.6 Data/Fax PnP modem */
+        {       "SUP1421",              0       },
+        /* SupraExpress 33.6 Data/Fax PnP modem */
+        {       "SUP1590",              0       },
+        /* SupraExpress 336i Sp ASVD */
+        {       "SUP1620",              0       },
+        /* SupraExpress 33.6 Data/Fax PnP modem */
+        {       "SUP1760",              0       },
+        /* SupraExpress 56i Sp Intl */
+        {       "SUP2171",              0       },
+        /* Phoebe Micro */
+        /* Phoebe Micro 33.6 Data Fax 1433VQH Plug & Play */
+        {       "TEX0011",              0       },
+        /* Archtek America Corp. */
+        /* Archtek SmartLink Modem 3334BT Plug & Play */
+        {       "UAC000F",              0       },
+        /* 3Com Corp. */
+        /* Gateway Telepath IIvi 33.6 */
+        {       "USR0000",              0       },
+        /* U.S. Robotics Sporster 33.6K Fax INT PnP */
+        {       "USR0002",              0       },
+        /*  Sportster Vi 14.4 PnP FAX Voicemail */
+        {       "USR0004",              0       },
+        /* U.S. Robotics 33.6K Voice INT PnP */
+        {       "USR0006",              0       },
+        /* U.S. Robotics 33.6K Voice EXT PnP */
+        {       "USR0007",              0       },
+        /* U.S. Robotics Courier V.Everything INT PnP */
+        {       "USR0009",              0       },
+        /* U.S. Robotics 33.6K Voice INT PnP */
+        {       "USR2002",              0       },
+        /* U.S. Robotics 56K Voice INT PnP */
+        {       "USR2070",              0       },
+        /* U.S. Robotics 56K Voice EXT PnP */
+        {       "USR2080",              0       },
+        /* U.S. Robotics 56K FAX INT */
+        {       "USR3031",              0       },
+        /* U.S. Robotics 56K FAX INT */
+        {       "USR3050",              0       },
+        /* U.S. Robotics 56K Voice INT PnP */
+        {       "USR3070",              0       },
+        /* U.S. Robotics 56K Voice EXT PnP */
+        {       "USR3080",              0       },
+        /* U.S. Robotics 56K Voice INT PnP */
+        {       "USR3090",              0       },
+        /* U.S. Robotics 56K Message  */
+        {       "USR9100",              0       },
+        /* U.S. Robotics 56K FAX EXT PnP*/
+        {       "USR9160",              0       },
+        /* U.S. Robotics 56K FAX INT PnP*/
+        {       "USR9170",              0       },
+        /* U.S. Robotics 56K Voice EXT PnP*/
+        {       "USR9180",              0       },
+        /* U.S. Robotics 56K Voice INT PnP*/
+        {       "USR9190",              0       },
+        /* Wacom tablets */
+        {       "WACFXXX",              0       },
+        /* Compaq touchscreen */
+        {       "FPI2002",              0 },
+        /* Fujitsu Stylistic touchscreens */
+        {       "FUJ02B2",              0 },
+        {       "FUJ02B3",              0 },
+        /* Fujitsu Stylistic LT touchscreens */
+        {       "FUJ02B4",              0 },
+        /* Passive Fujitsu Stylistic touchscreens */
+        {       "FUJ02B6",              0 },
+        {       "FUJ02B7",              0 },
+        {       "FUJ02B8",              0 },
+        {       "FUJ02B9",              0 },
+        {       "FUJ02BC",              0 },
+        /* Fujitsu Wacom Tablet PC device */
+        {       "FUJ02E5",              0       },
+        /* Fujitsu P-series tablet PC device */
+        {       "FUJ02E6",              0       },
+        /* Fujitsu Wacom 2FGT Tablet PC device */
+        {       "FUJ02E7",              0       },
+        /* Fujitsu Wacom 1FGT Tablet PC device */
+        {       "FUJ02E9",              0       },
+        /*
+         * LG C1 EXPRESS DUAL (C1-PB11A3) touch screen (actually a FUJ02E6 in
+         * disguise)
+         */
+        {       "LTS0001",              0       },
+        /* Rockwell's (PORALiNK) 33600 INT PNP */
+        {       "WCI0003",              0       },
+        /* Unknown PnP modems */
+        {       "PNPCXXX",              UNKNOWN_DEV     },
+        /* More unknown PnP modems */
+        {       "PNPDXXX",              UNKNOWN_DEV     },
+        {       "",                     0       }
+};
+
+MODULE_DEVICE_TABLE(pnp, pnp_dev_table);
+
+static char *modem_names[] __devinitdata = {
+        "MODEM", "Modem", "modem", "FAX", "Fax", "fax",
+        "56K", "56k", "K56", "33.6", "28.8", "14.4",
+        "33,600", "28,800", "14,400", "33.600", "28.800", "14.400",
+        "33600", "28800", "14400", "V.90", "V.34", "V.32", NULL
+};
+
+static int __devinit check_name(char *name)
+{
+        char **tmp;
+
+        for (tmp = modem_names; *tmp; tmp++)
+                if (strstr(name, *tmp))
+                        return 1;
+
+        return 0;
+}
+
+static int __devinit check_resources(struct pnp_dev *dev)
+{
+        resource_size_t base[] = {0x2f8, 0x3f8, 0x2e8, 0x3e8};
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(base); i++) {
+                if (pnp_possible_config(dev, IORESOURCE_IO, base[i], 8))
+                        return 1;
+        }
+
+        return 0;
+}
+
+/*
+ * Given a complete unknown PnP device, try to use some heuristics to
+ * detect modems. Currently use such heuristic set:
+ *     - dev->name or dev->bus->name must contain "modem" substring;
+ *     - device must have only one IO region (8 byte long) with base address
+ *       0x2e8, 0x3e8, 0x2f8 or 0x3f8.
+ *
+ * Such detection looks very ugly, but can detect at least some of numerous
+ * PnP modems, alternatively we must hardcode all modems in pnp_devices[]
+ * table.
+ */
+static int __devinit serial_pnp_guess_board(struct pnp_dev *dev, int *flags)
+{
+        if (!(check_name(pnp_dev_name(dev)) ||
+                (dev->card && check_name(dev->card->name))))
+                        return -ENODEV;
+
+        if (check_resources(dev))
+                return 0;
+
+        return -ENODEV;
+}
+
+static int __devinit
+serial_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *dev_id)
+{
+        struct uart_port port;
+        int ret, line, flags = dev_id->driver_data;
+
+        if (flags & UNKNOWN_DEV) {
+                ret = serial_pnp_guess_board(dev, &flags);
+                if (ret < 0)
+                        return ret;
+        }
+
+        memset(&port, 0, sizeof(struct uart_port));
+        if (pnp_irq_valid(dev, 0))
+                port.irq = pnp_irq(dev, 0);
+        if (pnp_port_valid(dev, 0)) {
+                port.iobase = pnp_port_start(dev, 0);
+                port.iotype = UPIO_PORT;
+        } else if (pnp_mem_valid(dev, 0)) {
+                port.mapbase = pnp_mem_start(dev, 0);
+                port.iotype = UPIO_MEM;
+                port.flags = UPF_IOREMAP;
+        } else
+                return -ENODEV;
+
+#ifdef SERIAL_DEBUG_PNP
+        printk(KERN_DEBUG
+                "Setup PNP port: port %x, mem 0x%lx, irq %d, type %d\n",
+                       port.iobase, port.mapbase, port.irq, port.iotype);
+#endif
+
+        port.flags |= UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
+        if (pnp_irq_flags(dev, 0) & IORESOURCE_IRQ_SHAREABLE)
+                port.flags |= UPF_SHARE_IRQ;
+        port.uartclk = 1843200;
+        port.dev = &dev->dev;
+
+        line = serial8250_register_port(&port);
+        if (line < 0)
+                return -ENODEV;
+
+        pnp_set_drvdata(dev, (void *)((long)line + 1));
+        return 0;
+}
+
+static void __devexit serial_pnp_remove(struct pnp_dev *dev)
+{
+        long line = (long)pnp_get_drvdata(dev);
+        if (line)
+                serial8250_unregister_port(line - 1);
+}
+
+#ifdef CONFIG_PM
+static int serial_pnp_suspend(struct pnp_dev *dev, pm_message_t state)
+{
+        long line = (long)pnp_get_drvdata(dev);
+
+        if (!line)
+                return -ENODEV;
+        serial8250_suspend_port(line - 1);
+        return 0;
+}
+
+static int serial_pnp_resume(struct pnp_dev *dev)
+{
+        long line = (long)pnp_get_drvdata(dev);
+
+        if (!line)
+                return -ENODEV;
+        serial8250_resume_port(line - 1);
+        return 0;
+}
+#else
+#define serial_pnp_suspend NULL
+#define serial_pnp_resume NULL
+#endif /* CONFIG_PM */
+
+static struct pnp_driver serial_pnp_driver = {
+        .name           = "serial",
+        .probe          = serial_pnp_probe,
+        .remove         = __devexit_p(serial_pnp_remove),
+        .suspend        = serial_pnp_suspend,
+        .resume         = serial_pnp_resume,
+        .id_table       = pnp_dev_table,
+};
+
+static int __init serial8250_pnp_init(void)
+{
+        return pnp_register_driver(&serial_pnp_driver);
+}
+
+static void __exit serial8250_pnp_exit(void)
+{
+        pnp_unregister_driver(&serial_pnp_driver);
+}
+
+module_init(serial8250_pnp_init);
+module_exit(serial8250_pnp_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Generic 8250/16x50 PnP serial driver");
diff --git a/drivers/tty/serial/bfin_5xx.c b/drivers/tty/serial/bfin_5xx.c
new file mode 100644
index 00000000000..ff6979181ac
--- /dev/null
+++ b/drivers/tty/serial/bfin_5xx.c
@@ -0,0 +1,1596 @@
+/*
+ * Blackfin On-Chip Serial Driver
+ *
+ * Copyright 2006-2010 Analog Devices Inc.
+ *
+ * Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
+#define SUPPORT_SYSRQ
+#endif
+
+#define DRIVER_NAME "bfin-uart"
+#define pr_fmt(fmt) DRIVER_NAME ": " fmt
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/gfp.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/sysrq.h>
+#include <linux/platform_device.h>
+#include <linux/tty.h>
+#include <linux/tty_flip.h>
+#include <linux/serial_core.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/kgdb.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/portmux.h>
+#include <asm/cacheflush.h>
+#include <asm/dma.h>
+
+#define port_membase(uart)     (((struct bfin_serial_port *)(uart))->port.membase)
+#define get_lsr_cache(uart)    (((struct bfin_serial_port *)(uart))->lsr)
+#define put_lsr_cache(uart, v) (((struct bfin_serial_port *)(uart))->lsr = (v))
+#include <asm/bfin_serial.h>
+
+#ifdef CONFIG_SERIAL_BFIN_MODULE
+# undef CONFIG_EARLY_PRINTK
+#endif
+
+#ifdef CONFIG_SERIAL_BFIN_MODULE
+# undef CONFIG_EARLY_PRINTK
+#endif
+
+/* UART name and device definitions */
+#define BFIN_SERIAL_DEV_NAME    "ttyBF"
+#define BFIN_SERIAL_MAJOR       204
+#define BFIN_SERIAL_MINOR       64
+
+static struct bfin_serial_port *bfin_serial_ports[BFIN_UART_NR_PORTS];
+
+#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
+        defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
+
+# ifndef CONFIG_SERIAL_BFIN_PIO
+#  error KGDB only support UART in PIO mode.
+# endif
+
+static int kgdboc_port_line;
+static int kgdboc_break_enabled;
+#endif
+/*
+ * Setup for console. Argument comes from the menuconfig
+ */
+#define DMA_RX_XCOUNT           512
+#define DMA_RX_YCOUNT           (PAGE_SIZE / DMA_RX_XCOUNT)
+
+#define DMA_RX_FLUSH_JIFFIES    (HZ / 50)
+
+#ifdef CONFIG_SERIAL_BFIN_DMA
+static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
+#else
+static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
+#endif
+
+static void bfin_serial_reset_irda(struct uart_port *port);
+
+#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
+        defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
+static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+        if (uart->cts_pin < 0)
+                return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
+
+        /* CTS PIN is negative assertive. */
+        if (UART_GET_CTS(uart))
+                return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
+        else
+                return TIOCM_DSR | TIOCM_CAR;
+}
+
+static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+        if (uart->rts_pin < 0)
+                return;
+
+        /* RTS PIN is negative assertive. */
+        if (mctrl & TIOCM_RTS)
+                UART_ENABLE_RTS(uart);
+        else
+                UART_DISABLE_RTS(uart);
+}
+
+/*
+ * Handle any change of modem status signal.
+ */
+static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id)
+{
+        struct bfin_serial_port *uart = dev_id;
+        unsigned int status;
+
+        status = bfin_serial_get_mctrl(&uart->port);
+        uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+        uart->scts = 1;
+        UART_CLEAR_SCTS(uart);
+        UART_CLEAR_IER(uart, EDSSI);
+#endif
+
+        return IRQ_HANDLED;
+}
+#else
+static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
+{
+        return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
+}
+
+static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+}
+#endif
+
+/*
+ * interrupts are disabled on entry
+ */
+static void bfin_serial_stop_tx(struct uart_port *port)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        struct circ_buf *xmit = &uart->port.state->xmit;
+#endif
+
+        while (!(UART_GET_LSR(uart) & TEMT))
+                cpu_relax();
+
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        disable_dma(uart->tx_dma_channel);
+        xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
+        uart->port.icount.tx += uart->tx_count;
+        uart->tx_count = 0;
+        uart->tx_done = 1;
+#else
+#ifdef CONFIG_BF54x
+        /* Clear TFI bit */
+        UART_PUT_LSR(uart, TFI);
+#endif
+        UART_CLEAR_IER(uart, ETBEI);
+#endif
+}
+
+/*
+ * port is locked and interrupts are disabled
+ */
+static void bfin_serial_start_tx(struct uart_port *port)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+        struct tty_struct *tty = uart->port.state->port.tty;
+
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+        if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
+                uart->scts = 0;
+                uart_handle_cts_change(&uart->port, uart->scts);
+        }
+#endif
+
+        /*
+         * To avoid losting RX interrupt, we reset IR function
+         * before sending data.
+         */
+        if (tty->termios->c_line == N_IRDA)
+                bfin_serial_reset_irda(port);
+
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        if (uart->tx_done)
+                bfin_serial_dma_tx_chars(uart);
+#else
+        UART_SET_IER(uart, ETBEI);
+        bfin_serial_tx_chars(uart);
+#endif
+}
+
+/*
+ * Interrupts are enabled
+ */
+static void bfin_serial_stop_rx(struct uart_port *port)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+
+        UART_CLEAR_IER(uart, ERBFI);
+}
+
+/*
+ * Set the modem control timer to fire immediately.
+ */
+static void bfin_serial_enable_ms(struct uart_port *port)
+{
+}
+
+
+#if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
+# define UART_GET_ANOMALY_THRESHOLD(uart)    ((uart)->anomaly_threshold)
+# define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
+#else
+# define UART_GET_ANOMALY_THRESHOLD(uart)    0
+# define UART_SET_ANOMALY_THRESHOLD(uart, v)
+#endif
+
+#ifdef CONFIG_SERIAL_BFIN_PIO
+static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
+{
+        struct tty_struct *tty = NULL;
+        unsigned int status, ch, flg;
+        static struct timeval anomaly_start = { .tv_sec = 0 };
+
+        status = UART_GET_LSR(uart);
+        UART_CLEAR_LSR(uart);
+
+        ch = UART_GET_CHAR(uart);
+        uart->port.icount.rx++;
+
+#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
+        defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
+        if (kgdb_connected && kgdboc_port_line == uart->port.line
+                && kgdboc_break_enabled)
+                if (ch == 0x3) {/* Ctrl + C */
+                        kgdb_breakpoint();
+                        return;
+                }
+
+        if (!uart->port.state || !uart->port.state->port.tty)
+                return;
+#endif
+        tty = uart->port.state->port.tty;
+
+        if (ANOMALY_05000363) {
+                /* The BF533 (and BF561) family of processors have a nice anomaly
+                 * where they continuously generate characters for a "single" break.
+                 * We have to basically ignore this flood until the "next" valid
+                 * character comes across.  Due to the nature of the flood, it is
+                 * not possible to reliably catch bytes that are sent too quickly
+                 * after this break.  So application code talking to the Blackfin
+                 * which sends a break signal must allow at least 1.5 character
+                 * times after the end of the break for things to stabilize.  This
+                 * timeout was picked as it must absolutely be larger than 1
+                 * character time +/- some percent.  So 1.5 sounds good.  All other
+                 * Blackfin families operate properly.  Woo.
+                 */
+                if (anomaly_start.tv_sec) {
+                        struct timeval curr;
+                        suseconds_t usecs;
+
+                        if ((~ch & (~ch + 1)) & 0xff)
+                                goto known_good_char;
+
+                        do_gettimeofday(&curr);
+                        if (curr.tv_sec - anomaly_start.tv_sec > 1)
+                                goto known_good_char;
+
+                        usecs = 0;
+                        if (curr.tv_sec != anomaly_start.tv_sec)
+                                usecs += USEC_PER_SEC;
+                        usecs += curr.tv_usec - anomaly_start.tv_usec;
+
+                        if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
+                                goto known_good_char;
+
+                        if (ch)
+                                anomaly_start.tv_sec = 0;
+                        else
+                                anomaly_start = curr;
+
+                        return;
+
+ known_good_char:
+                        status &= ~BI;
+                        anomaly_start.tv_sec = 0;
+                }
+        }
+
+        if (status & BI) {
+                if (ANOMALY_05000363)
+                        if (bfin_revid() < 5)
+                                do_gettimeofday(&anomaly_start);
+                uart->port.icount.brk++;
+                if (uart_handle_break(&uart->port))
+                        goto ignore_char;
+                status &= ~(PE | FE);
+        }
+        if (status & PE)
+                uart->port.icount.parity++;
+        if (status & OE)
+                uart->port.icount.overrun++;
+        if (status & FE)
+                uart->port.icount.frame++;
+
+        status &= uart->port.read_status_mask;
+
+        if (status & BI)
+                flg = TTY_BREAK;
+        else if (status & PE)
+                flg = TTY_PARITY;
+        else if (status & FE)
+                flg = TTY_FRAME;
+        else
+                flg = TTY_NORMAL;
+
+        if (uart_handle_sysrq_char(&uart->port, ch))
+                goto ignore_char;
+
+        uart_insert_char(&uart->port, status, OE, ch, flg);
+
+ ignore_char:
+        tty_flip_buffer_push(tty);
+}
+
+static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
+{
+        struct circ_buf *xmit = &uart->port.state->xmit;
+
+        if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
+#ifdef CONFIG_BF54x
+                /* Clear TFI bit */
+                UART_PUT_LSR(uart, TFI);
+#endif
+                /* Anomaly notes:
+                 *  05000215 -  we always clear ETBEI within last UART TX
+                 *              interrupt to end a string. It is always set
+                 *              when start a new tx.
+                 */
+                UART_CLEAR_IER(uart, ETBEI);
+                return;
+        }
+
+        if (uart->port.x_char) {
+                UART_PUT_CHAR(uart, uart->port.x_char);
+                uart->port.icount.tx++;
+                uart->port.x_char = 0;
+        }
+
+        while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
+                UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
+                xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+                uart->port.icount.tx++;
+        }
+
+        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+                uart_write_wakeup(&uart->port);
+}
+
+static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
+{
+        struct bfin_serial_port *uart = dev_id;
+
+        while (UART_GET_LSR(uart) & DR)
+                bfin_serial_rx_chars(uart);
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
+{
+        struct bfin_serial_port *uart = dev_id;
+
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+        if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) {
+                uart->scts = 0;
+                uart_handle_cts_change(&uart->port, uart->scts);
+        }
+#endif
+        spin_lock(&uart->port.lock);
+        if (UART_GET_LSR(uart) & THRE)
+                bfin_serial_tx_chars(uart);
+        spin_unlock(&uart->port.lock);
+
+        return IRQ_HANDLED;
+}
+#endif
+
+#ifdef CONFIG_SERIAL_BFIN_DMA
+static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
+{
+        struct circ_buf *xmit = &uart->port.state->xmit;
+
+        uart->tx_done = 0;
+
+        if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
+                uart->tx_count = 0;
+                uart->tx_done = 1;
+                return;
+        }
+
+        if (uart->port.x_char) {
+                UART_PUT_CHAR(uart, uart->port.x_char);
+                uart->port.icount.tx++;
+                uart->port.x_char = 0;
+        }
+
+        uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
+        if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
+                uart->tx_count = UART_XMIT_SIZE - xmit->tail;
+        blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
+                                        (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
+        set_dma_config(uart->tx_dma_channel,
+                set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
+                        INTR_ON_BUF,
+                        DIMENSION_LINEAR,
+                        DATA_SIZE_8,
+                        DMA_SYNC_RESTART));
+        set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
+        set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
+        set_dma_x_modify(uart->tx_dma_channel, 1);
+        SSYNC();
+        enable_dma(uart->tx_dma_channel);
+
+        UART_SET_IER(uart, ETBEI);
+}
+
+static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
+{
+        struct tty_struct *tty = uart->port.state->port.tty;
+        int i, flg, status;
+
+        status = UART_GET_LSR(uart);
+        UART_CLEAR_LSR(uart);
+
+        uart->port.icount.rx +=
+                CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
+                UART_XMIT_SIZE);
+
+        if (status & BI) {
+                uart->port.icount.brk++;
+                if (uart_handle_break(&uart->port))
+                        goto dma_ignore_char;
+                status &= ~(PE | FE);
+        }
+        if (status & PE)
+                uart->port.icount.parity++;
+        if (status & OE)
+                uart->port.icount.overrun++;
+        if (status & FE)
+                uart->port.icount.frame++;
+
+        status &= uart->port.read_status_mask;
+
+        if (status & BI)
+                flg = TTY_BREAK;
+        else if (status & PE)
+                flg = TTY_PARITY;
+        else if (status & FE)
+                flg = TTY_FRAME;
+        else
+                flg = TTY_NORMAL;
+
+        for (i = uart->rx_dma_buf.tail; ; i++) {
+                if (i >= UART_XMIT_SIZE)
+                        i = 0;
+                if (i == uart->rx_dma_buf.head)
+                        break;
+                if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
+                        uart_insert_char(&uart->port, status, OE,
+                                uart->rx_dma_buf.buf[i], flg);
+        }
+
+ dma_ignore_char:
+        tty_flip_buffer_push(tty);
+}
+
+void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
+{
+        int x_pos, pos;
+
+        dma_disable_irq_nosync(uart->rx_dma_channel);
+        spin_lock_bh(&uart->rx_lock);
+
+        /* 2D DMA RX buffer ring is used. Because curr_y_count and
+         * curr_x_count can't be read as an atomic operation,
+         * curr_y_count should be read before curr_x_count. When
+         * curr_x_count is read, curr_y_count may already indicate
+         * next buffer line. But, the position calculated here is
+         * still indicate the old line. The wrong position data may
+         * be smaller than current buffer tail, which cause garbages
+         * are received if it is not prohibit.
+         */
+        uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
+        x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
+        uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
+        if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
+                uart->rx_dma_nrows = 0;
+        x_pos = DMA_RX_XCOUNT - x_pos;
+        if (x_pos == DMA_RX_XCOUNT)
+                x_pos = 0;
+
+        pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
+        /* Ignore receiving data if new position is in the same line of
+         * current buffer tail and small.
+         */
+        if (pos > uart->rx_dma_buf.tail ||
+                uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
+                uart->rx_dma_buf.head = pos;
+                bfin_serial_dma_rx_chars(uart);
+                uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
+        }
+
+        spin_unlock_bh(&uart->rx_lock);
+        dma_enable_irq(uart->rx_dma_channel);
+
+        mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
+}
+
+static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
+{
+        struct bfin_serial_port *uart = dev_id;
+        struct circ_buf *xmit = &uart->port.state->xmit;
+
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+        if (uart->scts && !(bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) {
+                uart->scts = 0;
+                uart_handle_cts_change(&uart->port, uart->scts);
+        }
+#endif
+
+        spin_lock(&uart->port.lock);
+        if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
+                disable_dma(uart->tx_dma_channel);
+                clear_dma_irqstat(uart->tx_dma_channel);
+                /* Anomaly notes:
+                 *  05000215 -  we always clear ETBEI within last UART TX
+                 *              interrupt to end a string. It is always set
+                 *              when start a new tx.
+                 */
+                UART_CLEAR_IER(uart, ETBEI);
+                xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
+                uart->port.icount.tx += uart->tx_count;
+
+                if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+                        uart_write_wakeup(&uart->port);
+
+                bfin_serial_dma_tx_chars(uart);
+        }
+
+        spin_unlock(&uart->port.lock);
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
+{
+        struct bfin_serial_port *uart = dev_id;
+        unsigned short irqstat;
+        int x_pos, pos;
+
+        spin_lock(&uart->rx_lock);
+        irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
+        clear_dma_irqstat(uart->rx_dma_channel);
+
+        uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
+        x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
+        uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
+        if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0)
+                uart->rx_dma_nrows = 0;
+
+        pos = uart->rx_dma_nrows * DMA_RX_XCOUNT;
+        if (pos > uart->rx_dma_buf.tail ||
+                uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) {
+                uart->rx_dma_buf.head = pos;
+                bfin_serial_dma_rx_chars(uart);
+                uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
+        }
+
+        spin_unlock(&uart->rx_lock);
+
+        return IRQ_HANDLED;
+}
+#endif
+
+/*
+ * Return TIOCSER_TEMT when transmitter is not busy.
+ */
+static unsigned int bfin_serial_tx_empty(struct uart_port *port)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+        unsigned short lsr;
+
+        lsr = UART_GET_LSR(uart);
+        if (lsr & TEMT)
+                return TIOCSER_TEMT;
+        else
+                return 0;
+}
+
+static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+        u16 lcr = UART_GET_LCR(uart);
+        if (break_state)
+                lcr |= SB;
+        else
+                lcr &= ~SB;
+        UART_PUT_LCR(uart, lcr);
+        SSYNC();
+}
+
+static int bfin_serial_startup(struct uart_port *port)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        dma_addr_t dma_handle;
+
+        if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
+                printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
+                return -EBUSY;
+        }
+
+        if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
+                printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
+                free_dma(uart->rx_dma_channel);
+                return -EBUSY;
+        }
+
+        set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
+        set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
+
+        uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
+        uart->rx_dma_buf.head = 0;
+        uart->rx_dma_buf.tail = 0;
+        uart->rx_dma_nrows = 0;
+
+        set_dma_config(uart->rx_dma_channel,
+                set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
+                                INTR_ON_ROW, DIMENSION_2D,
+                                DATA_SIZE_8,
+                                DMA_SYNC_RESTART));
+        set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
+        set_dma_x_modify(uart->rx_dma_channel, 1);
+        set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
+        set_dma_y_modify(uart->rx_dma_channel, 1);
+        set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
+        enable_dma(uart->rx_dma_channel);
+
+        uart->rx_dma_timer.data = (unsigned long)(uart);
+        uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
+        uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
+        add_timer(&(uart->rx_dma_timer));
+#else
+# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
+        defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
+        if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled)
+                kgdboc_break_enabled = 0;
+        else {
+# endif
+        if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
+             "BFIN_UART_RX", uart)) {
+                printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
+                return -EBUSY;
+        }
+
+        if (request_irq
+            (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
+             "BFIN_UART_TX", uart)) {
+                printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
+                free_irq(uart->port.irq, uart);
+                return -EBUSY;
+        }
+
+# ifdef CONFIG_BF54x
+        {
+                /*
+                 * UART2 and UART3 on BF548 share interrupt PINs and DMA
+                 * controllers with SPORT2 and SPORT3. UART rx and tx
+                 * interrupts are generated in PIO mode only when configure
+                 * their peripheral mapping registers properly, which means
+                 * request corresponding DMA channels in PIO mode as well.
+                 */
+                unsigned uart_dma_ch_rx, uart_dma_ch_tx;
+
+                switch (uart->port.irq) {
+                case IRQ_UART3_RX:
+                        uart_dma_ch_rx = CH_UART3_RX;
+                        uart_dma_ch_tx = CH_UART3_TX;
+                        break;
+                case IRQ_UART2_RX:
+                        uart_dma_ch_rx = CH_UART2_RX;
+                        uart_dma_ch_tx = CH_UART2_TX;
+                        break;
+                default:
+                        uart_dma_ch_rx = uart_dma_ch_tx = 0;
+                        break;
+                };
+
+                if (uart_dma_ch_rx &&
+                        request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
+                        printk(KERN_NOTICE"Fail to attach UART interrupt\n");
+                        free_irq(uart->port.irq, uart);
+                        free_irq(uart->port.irq + 1, uart);
+                        return -EBUSY;
+                }
+                if (uart_dma_ch_tx &&
+                        request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
+                        printk(KERN_NOTICE "Fail to attach UART interrupt\n");
+                        free_dma(uart_dma_ch_rx);
+                        free_irq(uart->port.irq, uart);
+                        free_irq(uart->port.irq + 1, uart);
+                        return -EBUSY;
+                }
+        }
+# endif
+# if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
+        defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
+        }
+# endif
+#endif
+
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        if (uart->cts_pin >= 0) {
+                if (request_irq(gpio_to_irq(uart->cts_pin),
+                        bfin_serial_mctrl_cts_int,
+                        IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
+                        IRQF_DISABLED, "BFIN_UART_CTS", uart)) {
+                        uart->cts_pin = -1;
+                        pr_info("Unable to attach BlackFin UART CTS interrupt. So, disable it.\n");
+                }
+        }
+        if (uart->rts_pin >= 0) {
+                gpio_direction_output(uart->rts_pin, 0);
+        }
+#endif
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+        if (uart->cts_pin >= 0 && request_irq(uart->status_irq,
+                bfin_serial_mctrl_cts_int,
+                IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) {
+                uart->cts_pin = -1;
+                pr_info("Unable to attach BlackFin UART Modem Status interrupt.\n");
+        }
+
+        /* CTS RTS PINs are negative assertive. */
+        UART_PUT_MCR(uart, ACTS);
+        UART_SET_IER(uart, EDSSI);
+#endif
+
+        UART_SET_IER(uart, ERBFI);
+        return 0;
+}
+
+static void bfin_serial_shutdown(struct uart_port *port)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        disable_dma(uart->tx_dma_channel);
+        free_dma(uart->tx_dma_channel);
+        disable_dma(uart->rx_dma_channel);
+        free_dma(uart->rx_dma_channel);
+        del_timer(&(uart->rx_dma_timer));
+        dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
+#else
+#ifdef CONFIG_BF54x
+        switch (uart->port.irq) {
+        case IRQ_UART3_RX:
+                free_dma(CH_UART3_RX);
+                free_dma(CH_UART3_TX);
+                break;
+        case IRQ_UART2_RX:
+                free_dma(CH_UART2_RX);
+                free_dma(CH_UART2_TX);
+                break;
+        default:
+                break;
+        };
+#endif
+        free_irq(uart->port.irq, uart);
+        free_irq(uart->port.irq+1, uart);
+#endif
+
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        if (uart->cts_pin >= 0)
+                free_irq(gpio_to_irq(uart->cts_pin), uart);
+#endif
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+        if (uart->cts_pin >= 0)
+                free_irq(uart->status_irq, uart);
+#endif
+}
+
+static void
+bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
+                   struct ktermios *old)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+        unsigned long flags;
+        unsigned int baud, quot;
+        unsigned short val, ier, lcr = 0;
+
+        switch (termios->c_cflag & CSIZE) {
+        case CS8:
+                lcr = WLS(8);
+                break;
+        case CS7:
+                lcr = WLS(7);
+                break;
+        case CS6:
+                lcr = WLS(6);
+                break;
+        case CS5:
+                lcr = WLS(5);
+                break;
+        default:
+                printk(KERN_ERR "%s: word lengh not supported\n",
+                        __func__);
+        }
+
+        /* Anomaly notes:
+         *  05000231 -  STOP bit is always set to 1 whatever the user is set.
+         */
+        if (termios->c_cflag & CSTOPB) {
+                if (ANOMALY_05000231)
+                        printk(KERN_WARNING "STOP bits other than 1 is not "
+                                "supported in case of anomaly 05000231.\n");
+                else
+                        lcr |= STB;
+        }
+        if (termios->c_cflag & PARENB)
+                lcr |= PEN;
+        if (!(termios->c_cflag & PARODD))
+                lcr |= EPS;
+        if (termios->c_cflag & CMSPAR)
+                lcr |= STP;
+
+        spin_lock_irqsave(&uart->port.lock, flags);
+
+        port->read_status_mask = OE;
+        if (termios->c_iflag & INPCK)
+                port->read_status_mask |= (FE | PE);
+        if (termios->c_iflag & (BRKINT | PARMRK))
+                port->read_status_mask |= BI;
+
+        /*
+         * Characters to ignore
+         */
+        port->ignore_status_mask = 0;
+        if (termios->c_iflag & IGNPAR)
+                port->ignore_status_mask |= FE | PE;
+        if (termios->c_iflag & IGNBRK) {
+                port->ignore_status_mask |= BI;
+                /*
+                 * If we're ignoring parity and break indicators,
+                 * ignore overruns too (for real raw support).
+                 */
+                if (termios->c_iflag & IGNPAR)
+                        port->ignore_status_mask |= OE;
+        }
+
+        baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
+        quot = uart_get_divisor(port, baud);
+
+        /* If discipline is not IRDA, apply ANOMALY_05000230 */
+        if (termios->c_line != N_IRDA)
+                quot -= ANOMALY_05000230;
+
+        UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
+
+        /* Disable UART */
+        ier = UART_GET_IER(uart);
+        UART_DISABLE_INTS(uart);
+
+        /* Set DLAB in LCR to Access DLL and DLH */
+        UART_SET_DLAB(uart);
+
+        UART_PUT_DLL(uart, quot & 0xFF);
+        UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
+        SSYNC();
+
+        /* Clear DLAB in LCR to Access THR RBR IER */
+        UART_CLEAR_DLAB(uart);
+
+        UART_PUT_LCR(uart, lcr);
+
+        /* Enable UART */
+        UART_ENABLE_INTS(uart, ier);
+
+        val = UART_GET_GCTL(uart);
+        val |= UCEN;
+        UART_PUT_GCTL(uart, val);
+
+        /* Port speed changed, update the per-port timeout. */
+        uart_update_timeout(port, termios->c_cflag, baud);
+
+        spin_unlock_irqrestore(&uart->port.lock, flags);
+}
+
+static const char *bfin_serial_type(struct uart_port *port)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+
+        return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
+}
+
+/*
+ * Release the memory region(s) being used by 'port'.
+ */
+static void bfin_serial_release_port(struct uart_port *port)
+{
+}
+
+/*
+ * Request the memory region(s) being used by 'port'.
+ */
+static int bfin_serial_request_port(struct uart_port *port)
+{
+        return 0;
+}
+
+/*
+ * Configure/autoconfigure the port.
+ */
+static void bfin_serial_config_port(struct uart_port *port, int flags)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+
+        if (flags & UART_CONFIG_TYPE &&
+            bfin_serial_request_port(&uart->port) == 0)
+                uart->port.type = PORT_BFIN;
+}
+
+/*
+ * Verify the new serial_struct (for TIOCSSERIAL).
+ * The only change we allow are to the flags and type, and
+ * even then only between PORT_BFIN and PORT_UNKNOWN
+ */
+static int
+bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
+{
+        return 0;
+}
+
+/*
+ * Enable the IrDA function if tty->ldisc.num is N_IRDA.
+ * In other cases, disable IrDA function.
+ */
+static void bfin_serial_set_ldisc(struct uart_port *port, int ld)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+        unsigned short val;
+
+        switch (ld) {
+        case N_IRDA:
+                val = UART_GET_GCTL(uart);
+                val |= (IREN | RPOLC);
+                UART_PUT_GCTL(uart, val);
+                break;
+        default:
+                val = UART_GET_GCTL(uart);
+                val &= ~(IREN | RPOLC);
+                UART_PUT_GCTL(uart, val);
+        }
+}
+
+static void bfin_serial_reset_irda(struct uart_port *port)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+        unsigned short val;
+
+        val = UART_GET_GCTL(uart);
+        val &= ~(IREN | RPOLC);
+        UART_PUT_GCTL(uart, val);
+        SSYNC();
+        val |= (IREN | RPOLC);
+        UART_PUT_GCTL(uart, val);
+        SSYNC();
+}
+
+#ifdef CONFIG_CONSOLE_POLL
+/* Anomaly notes:
+ *  05000099 -  Because we only use THRE in poll_put and DR in poll_get,
+ *              losing other bits of UART_LSR is not a problem here.
+ */
+static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+
+        while (!(UART_GET_LSR(uart) & THRE))
+                cpu_relax();
+
+        UART_CLEAR_DLAB(uart);
+        UART_PUT_CHAR(uart, (unsigned char)chr);
+}
+
+static int bfin_serial_poll_get_char(struct uart_port *port)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+        unsigned char chr;
+
+        while (!(UART_GET_LSR(uart) & DR))
+                cpu_relax();
+
+        UART_CLEAR_DLAB(uart);
+        chr = UART_GET_CHAR(uart);
+
+        return chr;
+}
+#endif
+
+#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
+        defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
+static void bfin_kgdboc_port_shutdown(struct uart_port *port)
+{
+        if (kgdboc_break_enabled) {
+                kgdboc_break_enabled = 0;
+                bfin_serial_shutdown(port);
+        }
+}
+
+static int bfin_kgdboc_port_startup(struct uart_port *port)
+{
+        kgdboc_port_line = port->line;
+        kgdboc_break_enabled = !bfin_serial_startup(port);
+        return 0;
+}
+#endif
+
+static struct uart_ops bfin_serial_pops = {
+        .tx_empty       = bfin_serial_tx_empty,
+        .set_mctrl      = bfin_serial_set_mctrl,
+        .get_mctrl      = bfin_serial_get_mctrl,
+        .stop_tx        = bfin_serial_stop_tx,
+        .start_tx       = bfin_serial_start_tx,
+        .stop_rx        = bfin_serial_stop_rx,
+        .enable_ms      = bfin_serial_enable_ms,
+        .break_ctl      = bfin_serial_break_ctl,
+        .startup        = bfin_serial_startup,
+        .shutdown       = bfin_serial_shutdown,
+        .set_termios    = bfin_serial_set_termios,
+        .set_ldisc      = bfin_serial_set_ldisc,
+        .type           = bfin_serial_type,
+        .release_port   = bfin_serial_release_port,
+        .request_port   = bfin_serial_request_port,
+        .config_port    = bfin_serial_config_port,
+        .verify_port    = bfin_serial_verify_port,
+#if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \
+        defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE)
+        .kgdboc_port_startup    = bfin_kgdboc_port_startup,
+        .kgdboc_port_shutdown   = bfin_kgdboc_port_shutdown,
+#endif
+#ifdef CONFIG_CONSOLE_POLL
+        .poll_put_char  = bfin_serial_poll_put_char,
+        .poll_get_char  = bfin_serial_poll_get_char,
+#endif
+};
+
+#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
+/*
+ * If the port was already initialised (eg, by a boot loader),
+ * try to determine the current setup.
+ */
+static void __init
+bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
+                           int *parity, int *bits)
+{
+        unsigned short status;
+
+        status = UART_GET_IER(uart) & (ERBFI | ETBEI);
+        if (status == (ERBFI | ETBEI)) {
+                /* ok, the port was enabled */
+                u16 lcr, dlh, dll;
+
+                lcr = UART_GET_LCR(uart);
+
+                *parity = 'n';
+                if (lcr & PEN) {
+                        if (lcr & EPS)
+                                *parity = 'e';
+                        else
+                                *parity = 'o';
+                }
+                switch (lcr & 0x03) {
+                        case 0: *bits = 5; break;
+                        case 1: *bits = 6; break;
+                        case 2: *bits = 7; break;
+                        case 3: *bits = 8; break;
+                }
+                /* Set DLAB in LCR to Access DLL and DLH */
+                UART_SET_DLAB(uart);
+
+                dll = UART_GET_DLL(uart);
+                dlh = UART_GET_DLH(uart);
+
+                /* Clear DLAB in LCR to Access THR RBR IER */
+                UART_CLEAR_DLAB(uart);
+
+                *baud = get_sclk() / (16*(dll | dlh << 8));
+        }
+        pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
+}
+
+static struct uart_driver bfin_serial_reg;
+
+static void bfin_serial_console_putchar(struct uart_port *port, int ch)
+{
+        struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
+        while (!(UART_GET_LSR(uart) & THRE))
+                barrier();
+        UART_PUT_CHAR(uart, ch);
+}
+
+#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
+                 defined (CONFIG_EARLY_PRINTK) */
+
+#ifdef CONFIG_SERIAL_BFIN_CONSOLE
+#define CLASS_BFIN_CONSOLE      "bfin-console"
+/*
+ * Interrupts are disabled on entering
+ */
+static void
+bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
+{
+        struct bfin_serial_port *uart = bfin_serial_ports[co->index];
+        unsigned long flags;
+
+        spin_lock_irqsave(&uart->port.lock, flags);
+        uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
+        spin_unlock_irqrestore(&uart->port.lock, flags);
+
+}
+
+static int __init
+bfin_serial_console_setup(struct console *co, char *options)
+{
+        struct bfin_serial_port *uart;
+        int baud = 57600;
+        int bits = 8;
+        int parity = 'n';
+# if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
+        defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
+        int flow = 'r';
+# else
+        int flow = 'n';
+# endif
+
+        /*
+         * Check whether an invalid uart number has been specified, and
+         * if so, search for the first available port that does have
+         * console support.
+         */
+        if (co->index < 0 || co->index >= BFIN_UART_NR_PORTS)
+                return -ENODEV;
+
+        uart = bfin_serial_ports[co->index];
+        if (!uart)
+                return -ENODEV;
+
+        if (options)
+                uart_parse_options(options, &baud, &parity, &bits, &flow);
+        else
+                bfin_serial_console_get_options(uart, &baud, &parity, &bits);
+
+        return uart_set_options(&uart->port, co, baud, parity, bits, flow);
+}
+
+static struct console bfin_serial_console = {
+        .name           = BFIN_SERIAL_DEV_NAME,
+        .write          = bfin_serial_console_write,
+        .device         = uart_console_device,
+        .setup          = bfin_serial_console_setup,
+        .flags          = CON_PRINTBUFFER,
+        .index          = -1,
+        .data           = &bfin_serial_reg,
+};
+#define BFIN_SERIAL_CONSOLE     &bfin_serial_console
+#else
+#define BFIN_SERIAL_CONSOLE     NULL
+#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
+
+#ifdef  CONFIG_EARLY_PRINTK
+static struct bfin_serial_port bfin_earlyprintk_port;
+#define CLASS_BFIN_EARLYPRINTK  "bfin-earlyprintk"
+
+/*
+ * Interrupts are disabled on entering
+ */
+static void
+bfin_earlyprintk_console_write(struct console *co, const char *s, unsigned int count)
+{
+        unsigned long flags;
+
+        if (bfin_earlyprintk_port.port.line != co->index)
+                return;
+
+        spin_lock_irqsave(&bfin_earlyprintk_port.port.lock, flags);
+        uart_console_write(&bfin_earlyprintk_port.port, s, count,
+                bfin_serial_console_putchar);
+        spin_unlock_irqrestore(&bfin_earlyprintk_port.port.lock, flags);
+}
+
+/*
+ * This should have a .setup or .early_setup in it, but then things get called
+ * without the command line options, and the baud rate gets messed up - so
+ * don't let the common infrastructure play with things. (see calls to setup
+ * & earlysetup in ./kernel/printk.c:register_console()
+ */
+static struct __initdata console bfin_early_serial_console = {
+        .name = "early_BFuart",
+        .write = bfin_earlyprintk_console_write,
+        .device = uart_console_device,
+        .flags = CON_PRINTBUFFER,
+        .index = -1,
+        .data  = &bfin_serial_reg,
+};
+#endif
+
+static struct uart_driver bfin_serial_reg = {
+        .owner                  = THIS_MODULE,
+        .driver_name            = DRIVER_NAME,
+        .dev_name               = BFIN_SERIAL_DEV_NAME,
+        .major                  = BFIN_SERIAL_MAJOR,
+        .minor                  = BFIN_SERIAL_MINOR,
+        .nr                     = BFIN_UART_NR_PORTS,
+        .cons                   = BFIN_SERIAL_CONSOLE,
+};
+
+static int bfin_serial_suspend(struct platform_device *pdev, pm_message_t state)
+{
+        struct bfin_serial_port *uart = platform_get_drvdata(pdev);
+
+        return uart_suspend_port(&bfin_serial_reg, &uart->port);
+}
+
+static int bfin_serial_resume(struct platform_device *pdev)
+{
+        struct bfin_serial_port *uart = platform_get_drvdata(pdev);
+
+        return uart_resume_port(&bfin_serial_reg, &uart->port);
+}
+
+static int bfin_serial_probe(struct platform_device *pdev)
+{
+        struct resource *res;
+        struct bfin_serial_port *uart = NULL;
+        int ret = 0;
+
+        if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) {
+                dev_err(&pdev->dev, "Wrong bfin uart platform device id.\n");
+                return -ENOENT;
+        }
+
+        if (bfin_serial_ports[pdev->id] == NULL) {
+
+                uart = kzalloc(sizeof(*uart), GFP_KERNEL);
+                if (!uart) {
+                        dev_err(&pdev->dev,
+                                "fail to malloc bfin_serial_port\n");
+                        return -ENOMEM;
+                }
+                bfin_serial_ports[pdev->id] = uart;
+
+#ifdef CONFIG_EARLY_PRINTK
+                if (!(bfin_earlyprintk_port.port.membase
+                        && bfin_earlyprintk_port.port.line == pdev->id)) {
+                        /*
+                         * If the peripheral PINs of current port is allocated
+                         * in earlyprintk probe stage, don't do it again.
+                         */
+#endif
+                ret = peripheral_request_list(
+                        (unsigned short *)pdev->dev.platform_data, DRIVER_NAME);
+                if (ret) {
+                        dev_err(&pdev->dev,
+                                "fail to request bfin serial peripherals\n");
+                        goto out_error_free_mem;
+                }
+#ifdef CONFIG_EARLY_PRINTK
+                }
+#endif
+
+                spin_lock_init(&uart->port.lock);
+                uart->port.uartclk   = get_sclk();
+                uart->port.fifosize  = BFIN_UART_TX_FIFO_SIZE;
+                uart->port.ops       = &bfin_serial_pops;
+                uart->port.line      = pdev->id;
+                uart->port.iotype    = UPIO_MEM;
+                uart->port.flags     = UPF_BOOT_AUTOCONF;
+
+                res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+                if (res == NULL) {
+                        dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
+                        ret = -ENOENT;
+                        goto out_error_free_peripherals;
+                }
+
+                uart->port.membase = ioremap(res->start, resource_size(res));
+                if (!uart->port.membase) {
+                        dev_err(&pdev->dev, "Cannot map uart IO\n");
+                        ret = -ENXIO;
+                        goto out_error_free_peripherals;
+                }
+                uart->port.mapbase = res->start;
+
+                uart->port.irq = platform_get_irq(pdev, 0);
+                if (uart->port.irq < 0) {
+                        dev_err(&pdev->dev, "No uart RX/TX IRQ specified\n");
+                        ret = -ENOENT;
+                        goto out_error_unmap;
+                }
+
+                uart->status_irq = platform_get_irq(pdev, 1);
+                if (uart->status_irq < 0) {
+                        dev_err(&pdev->dev, "No uart status IRQ specified\n");
+                        ret = -ENOENT;
+                        goto out_error_unmap;
+                }
+
+#ifdef CONFIG_SERIAL_BFIN_DMA
+                spin_lock_init(&uart->rx_lock);
+                uart->tx_done       = 1;
+                uart->tx_count      = 0;
+
+                res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+                if (res == NULL) {
+                        dev_err(&pdev->dev, "No uart TX DMA channel specified\n");
+                        ret = -ENOENT;
+                        goto out_error_unmap;
+                }
+                uart->tx_dma_channel = res->start;
+
+                res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
+                if (res == NULL) {
+                        dev_err(&pdev->dev, "No uart RX DMA channel specified\n");
+                        ret = -ENOENT;
+                        goto out_error_unmap;
+                }
+                uart->rx_dma_channel = res->start;
+
+                init_timer(&(uart->rx_dma_timer));
+#endif
+
+#if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \
+        defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS)
+                res = platform_get_resource(pdev, IORESOURCE_IO, 0);
+                if (res == NULL)
+                        uart->cts_pin = -1;
+                else
+                        uart->cts_pin = res->start;
+
+                res = platform_get_resource(pdev, IORESOURCE_IO, 1);
+                if (res == NULL)
+                        uart->rts_pin = -1;
+                else
+                        uart->rts_pin = res->start;
+# if defined(CONFIG_SERIAL_BFIN_CTSRTS)
+                if (uart->rts_pin >= 0)
+                        gpio_request(uart->rts_pin, DRIVER_NAME);
+# endif
+#endif
+        }
+
+#ifdef CONFIG_SERIAL_BFIN_CONSOLE
+        if (!is_early_platform_device(pdev)) {
+#endif
+                uart = bfin_serial_ports[pdev->id];
+                uart->port.dev = &pdev->dev;
+                dev_set_drvdata(&pdev->dev, uart);
+                ret = uart_add_one_port(&bfin_serial_reg, &uart->port);
+#ifdef CONFIG_SERIAL_BFIN_CONSOLE
+        }
+#endif
+
+        if (!ret)
+                return 0;
+
+        if (uart) {
+out_error_unmap:
+                iounmap(uart->port.membase);
+out_error_free_peripherals:
+                peripheral_free_list(
+                        (unsigned short *)pdev->dev.platform_data);
+out_error_free_mem:
+                kfree(uart);
+                bfin_serial_ports[pdev->id] = NULL;
+        }
+
+        return ret;
+}
+
+static int __devexit bfin_serial_remove(struct platform_device *pdev)
+{
+        struct bfin_serial_port *uart = platform_get_drvdata(pdev);
+
+        dev_set_drvdata(&pdev->dev, NULL);
+
+        if (uart) {
+                uart_remove_one_port(&bfin_serial_reg, &uart->port);
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+                if (uart->rts_pin >= 0)
+                        gpio_free(uart->rts_pin);
+#endif
+                iounmap(uart->port.membase);
+                peripheral_free_list(
+                        (unsigned short *)pdev->dev.platform_data);
+                kfree(uart);
+                bfin_serial_ports[pdev->id] = NULL;
+        }
+
+        return 0;
+}
+
+static struct platform_driver bfin_serial_driver = {
+        .probe          = bfin_serial_probe,
+        .remove         = __devexit_p(bfin_serial_remove),
+        .suspend        = bfin_serial_suspend,
+        .resume         = bfin_serial_resume,
+        .driver         = {
+                .name   = DRIVER_NAME,
+                .owner  = THIS_MODULE,
+        },
+};
+
+#if defined(CONFIG_SERIAL_BFIN_CONSOLE)
+static __initdata struct early_platform_driver early_bfin_serial_driver = {
+        .class_str = CLASS_BFIN_CONSOLE,
+        .pdrv = &bfin_serial_driver,
+        .requested_id = EARLY_PLATFORM_ID_UNSET,
+};
+
+static int __init bfin_serial_rs_console_init(void)
+{
+        early_platform_driver_register(&early_bfin_serial_driver, DRIVER_NAME);
+
+        early_platform_driver_probe(CLASS_BFIN_CONSOLE, BFIN_UART_NR_PORTS, 0);
+
+        register_console(&bfin_serial_console);
+
+        return 0;
+}
+console_initcall(bfin_serial_rs_console_init);
+#endif
+
+#ifdef CONFIG_EARLY_PRINTK
+/*
+ * Memory can't be allocated dynamically during earlyprink init stage.
+ * So, do individual probe for earlyprink with a static uart port variable.
+ */
+static int bfin_earlyprintk_probe(struct platform_device *pdev)
+{
+        struct resource *res;
+        int ret;
+
+        if (pdev->id < 0 || pdev->id >= BFIN_UART_NR_PORTS) {
+                dev_err(&pdev->dev, "Wrong earlyprintk platform device id.\n");
+                return -ENOENT;
+        }
+
+        ret = peripheral_request_list(
+                (unsigned short *)pdev->dev.platform_data, DRIVER_NAME);
+        if (ret) {
+                dev_err(&pdev->dev,
+                                "fail to request bfin serial peripherals\n");
+                        return ret;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res == NULL) {
+                dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
+                ret = -ENOENT;
+                goto out_error_free_peripherals;
+        }
+
+        bfin_earlyprintk_port.port.membase = ioremap(res->start,
+                                                     resource_size(res));
+        if (!bfin_earlyprintk_port.port.membase) {
+                dev_err(&pdev->dev, "Cannot map uart IO\n");
+                ret = -ENXIO;
+                goto out_error_free_peripherals;
+        }
+        bfin_earlyprintk_port.port.mapbase = res->start;
+        bfin_earlyprintk_port.port.line = pdev->id;
+        bfin_earlyprintk_port.port.uartclk = get_sclk();
+        bfin_earlyprintk_port.port.fifosize  = BFIN_UART_TX_FIFO_SIZE;
+        spin_lock_init(&bfin_earlyprintk_port.port.lock);
+
+        return 0;
+
+out_error_free_peripherals:
+        peripheral_free_list(
+                (unsigned short *)pdev->dev.platform_data);
+
+        return ret;
+}
+
+static struct platform_driver bfin_earlyprintk_driver = {
+        .probe          = bfin_earlyprintk_probe,
+        .driver         = {
+                .name   = DRIVER_NAME,
+                .owner  = THIS_MODULE,
+        },
+};
+
+static __initdata struct early_platform_driver early_bfin_earlyprintk_driver = {
+        .class_str = CLASS_BFIN_EARLYPRINTK,
+        .pdrv = &bfin_earlyprintk_driver,
+        .requested_id = EARLY_PLATFORM_ID_UNSET,
+};
+
+struct console __init *bfin_earlyserial_init(unsigned int port,
+                                                unsigned int cflag)
+{
+        struct ktermios t;
+        char port_name[20];
+
+        if (port < 0 || port >= BFIN_UART_NR_PORTS)
+                return NULL;
+
+        /*
+         * Only probe resource of the given port in earlyprintk boot arg.
+         * The expected port id should be indicated in port name string.
+         */
+        snprintf(port_name, 20, DRIVER_NAME ".%d", port);
+        early_platform_driver_register(&early_bfin_earlyprintk_driver,
+                port_name);
+        early_platform_driver_probe(CLASS_BFIN_EARLYPRINTK, 1, 0);
+
+        if (!bfin_earlyprintk_port.port.membase)
+                return NULL;
+
+#ifdef CONFIG_SERIAL_BFIN_CONSOLE
+        /*
+         * If we are using early serial, don't let the normal console rewind
+         * log buffer, since that causes things to be printed multiple times
+         */
+        bfin_serial_console.flags &= ~CON_PRINTBUFFER;
+#endif
+
+        bfin_early_serial_console.index = port;
+        t.c_cflag = cflag;
+        t.c_iflag = 0;
+        t.c_oflag = 0;
+        t.c_lflag = ICANON;
+        t.c_line = port;
+        bfin_serial_set_termios(&bfin_earlyprintk_port.port, &t, &t);
+
+        return &bfin_early_serial_console;
+}
+#endif /* CONFIG_EARLY_PRINTK */
+
+static int __init bfin_serial_init(void)
+{
+        int ret;
+
+        pr_info("Blackfin serial driver\n");
+
+        ret = uart_register_driver(&bfin_serial_reg);
+        if (ret) {
+                pr_err("failed to register %s:%d\n",
+                        bfin_serial_reg.driver_name, ret);
+        }
+
+        ret = platform_driver_register(&bfin_serial_driver);
+        if (ret) {
+                pr_err("fail to register bfin uart\n");
+                uart_unregister_driver(&bfin_serial_reg);
+        }
+
+        return ret;
+}
+
+static void __exit bfin_serial_exit(void)
+{
+        platform_driver_unregister(&bfin_serial_driver);
+        uart_unregister_driver(&bfin_serial_reg);
+}
+
+
+module_init(bfin_serial_init);
+module_exit(bfin_serial_exit);
+
+MODULE_AUTHOR("Sonic Zhang, Aubrey Li");
+MODULE_DESCRIPTION("Blackfin generic serial port driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
+MODULE_ALIAS("platform:bfin-uart");
diff --git a/drivers/tty/serial/max3107-aava.c b/drivers/tty/serial/max3107-aava.c
new file mode 100644
index 00000000000..d73aadd7a9a
--- /dev/null
+++ b/drivers/tty/serial/max3107-aava.c
@@ -0,0 +1,344 @@
+/*
+ *  max3107.c - spi uart protocol driver for Maxim 3107
+ *  Based on max3100.c
+ *      by Christian Pellegrin <chripell@evolware.org>
+ *  and max3110.c
+ *      by Feng Tang <feng.tang@intel.com>
+ *
+ *  Copyright (C) Aavamobile 2009
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/spi/spi.h>
+#include <linux/freezer.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/sfi.h>
+#include <asm/mrst.h>
+#include "max3107.h"
+
+/* GPIO direction to input function */
+static int max3107_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
+{
+        struct max3107_port *s = container_of(chip, struct max3107_port, chip);
+        u16 buf[1];             /* Buffer for SPI transfer */
+
+        if (offset >= MAX3107_GPIO_COUNT) {
+                dev_err(&s->spi->dev, "Invalid GPIO\n");
+                return -EINVAL;
+        }
+
+        /* Read current GPIO configuration register */
+        buf[0] = MAX3107_GPIOCFG_REG;
+        /* Perform SPI transfer */
+        if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
+                dev_err(&s->spi->dev, "SPI transfer GPIO read failed\n");
+                return -EIO;
+        }
+        buf[0] &= MAX3107_SPI_RX_DATA_MASK;
+
+        /* Set GPIO to input */
+        buf[0] &= ~(0x0001 << offset);
+
+        /* Write new GPIO configuration register value */
+        buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIOCFG_REG);
+        /* Perform SPI transfer */
+        if (max3107_rw(s, (u8 *)buf, NULL, 2)) {
+                dev_err(&s->spi->dev, "SPI transfer GPIO write failed\n");
+                return -EIO;
+        }
+        return 0;
+}
+
+/* GPIO direction to output function */
+static int max3107_gpio_direction_out(struct gpio_chip *chip, unsigned offset,
+                                        int value)
+{
+        struct max3107_port *s = container_of(chip, struct max3107_port, chip);
+        u16 buf[2];     /* Buffer for SPI transfers */
+
+        if (offset >= MAX3107_GPIO_COUNT) {
+                dev_err(&s->spi->dev, "Invalid GPIO\n");
+                return -EINVAL;
+        }
+
+        /* Read current GPIO configuration and data registers */
+        buf[0] = MAX3107_GPIOCFG_REG;
+        buf[1] = MAX3107_GPIODATA_REG;
+        /* Perform SPI transfer */
+        if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 4)) {
+                dev_err(&s->spi->dev, "SPI transfer gpio failed\n");
+                return -EIO;
+        }
+        buf[0] &= MAX3107_SPI_RX_DATA_MASK;
+        buf[1] &= MAX3107_SPI_RX_DATA_MASK;
+
+        /* Set GPIO to output */
+        buf[0] |= (0x0001 << offset);
+        /* Set value */
+        if (value)
+                buf[1] |= (0x0001 << offset);
+        else
+                buf[1] &= ~(0x0001 << offset);
+
+        /* Write new GPIO configuration and data register values */
+        buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIOCFG_REG);
+        buf[1] |= (MAX3107_WRITE_BIT | MAX3107_GPIODATA_REG);
+        /* Perform SPI transfer */
+        if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
+                dev_err(&s->spi->dev,
+                        "SPI transfer for GPIO conf data w failed\n");
+                return -EIO;
+        }
+        return 0;
+}
+
+/* GPIO value query function */
+static int max3107_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+        struct max3107_port *s = container_of(chip, struct max3107_port, chip);
+        u16 buf[1];     /* Buffer for SPI transfer */
+
+        if (offset >= MAX3107_GPIO_COUNT) {
+                dev_err(&s->spi->dev, "Invalid GPIO\n");
+                return -EINVAL;
+        }
+
+        /* Read current GPIO data register */
+        buf[0] = MAX3107_GPIODATA_REG;
+        /* Perform SPI transfer */
+        if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
+                dev_err(&s->spi->dev, "SPI transfer GPIO data r failed\n");
+                return -EIO;
+        }
+        buf[0] &= MAX3107_SPI_RX_DATA_MASK;
+
+        /* Return value */
+        return buf[0] & (0x0001 << offset);
+}
+
+/* GPIO value set function */
+static void max3107_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        struct max3107_port *s = container_of(chip, struct max3107_port, chip);
+        u16 buf[2];     /* Buffer for SPI transfers */
+
+        if (offset >= MAX3107_GPIO_COUNT) {
+                dev_err(&s->spi->dev, "Invalid GPIO\n");
+                return;
+        }
+
+        /* Read current GPIO configuration registers*/
+        buf[0] = MAX3107_GPIODATA_REG;
+        buf[1] = MAX3107_GPIOCFG_REG;
+        /* Perform SPI transfer */
+        if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 4)) {
+                dev_err(&s->spi->dev,
+                        "SPI transfer for GPIO data and config read failed\n");
+                return;
+        }
+        buf[0] &= MAX3107_SPI_RX_DATA_MASK;
+        buf[1] &= MAX3107_SPI_RX_DATA_MASK;
+
+        if (!(buf[1] & (0x0001 << offset))) {
+                /* Configured as input, can't set value */
+                dev_warn(&s->spi->dev,
+                                "Trying to set value for input GPIO\n");
+                return;
+        }
+
+        /* Set value */
+        if (value)
+                buf[0] |= (0x0001 << offset);
+        else
+                buf[0] &= ~(0x0001 << offset);
+
+        /* Write new GPIO data register value */
+        buf[0] |= (MAX3107_WRITE_BIT | MAX3107_GPIODATA_REG);
+        /* Perform SPI transfer */
+        if (max3107_rw(s, (u8 *)buf, NULL, 2))
+                dev_err(&s->spi->dev, "SPI transfer GPIO data w failed\n");
+}
+
+/* GPIO chip data */
+static struct gpio_chip max3107_gpio_chip = {
+        .owner                  = THIS_MODULE,
+        .direction_input        = max3107_gpio_direction_in,
+        .direction_output       = max3107_gpio_direction_out,
+        .get                    = max3107_gpio_get,
+        .set                    = max3107_gpio_set,
+        .can_sleep              = 1,
+        .base                   = MAX3107_GPIO_BASE,
+        .ngpio                  = MAX3107_GPIO_COUNT,
+};
+
+/**
+ *      max3107_aava_reset      -       reset on AAVA systems
+ *      @spi: The SPI device we are probing
+ *
+ *      Reset the device ready for probing.
+ */
+
+static int max3107_aava_reset(struct spi_device *spi)
+{
+        /* Reset the chip */
+        if (gpio_request(MAX3107_RESET_GPIO, "max3107")) {
+                pr_err("Requesting RESET GPIO failed\n");
+                return -EIO;
+        }
+        if (gpio_direction_output(MAX3107_RESET_GPIO, 0)) {
+                pr_err("Setting RESET GPIO to 0 failed\n");
+                gpio_free(MAX3107_RESET_GPIO);
+                return -EIO;
+        }
+        msleep(MAX3107_RESET_DELAY);
+        if (gpio_direction_output(MAX3107_RESET_GPIO, 1)) {
+                pr_err("Setting RESET GPIO to 1 failed\n");
+                gpio_free(MAX3107_RESET_GPIO);
+                return -EIO;
+        }
+        gpio_free(MAX3107_RESET_GPIO);
+        msleep(MAX3107_WAKEUP_DELAY);
+        return 0;
+}
+
+static int max3107_aava_configure(struct max3107_port *s)
+{
+        int retval;
+
+        /* Initialize GPIO chip data */
+        s->chip = max3107_gpio_chip;
+        s->chip.label = s->spi->modalias;
+        s->chip.dev = &s->spi->dev;
+
+        /* Add GPIO chip */
+        retval = gpiochip_add(&s->chip);
+        if (retval) {
+                dev_err(&s->spi->dev, "Adding GPIO chip failed\n");
+                return retval;
+        }
+
+        /* Temporary fix for EV2 boot problems, set modem reset to 0 */
+        max3107_gpio_direction_out(&s->chip, 3, 0);
+        return 0;
+}
+
+#if 0
+/* This will get enabled once we have the board stuff merged for this
+   specific case */
+
+static const struct baud_table brg13_ext[] = {
+        { 300,    MAX3107_BRG13_B300 },
+        { 600,    MAX3107_BRG13_B600 },
+        { 1200,   MAX3107_BRG13_B1200 },
+        { 2400,   MAX3107_BRG13_B2400 },
+        { 4800,   MAX3107_BRG13_B4800 },
+        { 9600,   MAX3107_BRG13_B9600 },
+        { 19200,  MAX3107_BRG13_B19200 },
+        { 57600,  MAX3107_BRG13_B57600 },
+        { 115200, MAX3107_BRG13_B115200 },
+        { 230400, MAX3107_BRG13_B230400 },
+        { 460800, MAX3107_BRG13_B460800 },
+        { 921600, MAX3107_BRG13_B921600 },
+        { 0, 0 }
+};
+
+static void max3107_aava_init(struct max3107_port *s)
+{
+        /*override for AAVA SC specific*/
+        if (mrst_platform_id() == MRST_PLATFORM_AAVA_SC) {
+                if (get_koski_build_id() <= KOSKI_EV2)
+                        if (s->ext_clk) {
+                                s->brg_cfg = MAX3107_BRG13_B9600;
+                                s->baud_tbl = (struct baud_table *)brg13_ext;
+                        }
+        }
+}
+#endif
+
+static int __devexit max3107_aava_remove(struct spi_device *spi)
+{
+        struct max3107_port *s = dev_get_drvdata(&spi->dev);
+
+        /* Remove GPIO chip */
+        if (gpiochip_remove(&s->chip))
+                dev_warn(&spi->dev, "Removing GPIO chip failed\n");
+
+        /* Then do the default remove */
+        return max3107_remove(spi);
+}
+
+/* Platform data */
+static struct max3107_plat aava_plat_data = {
+        .loopback               = 0,
+        .ext_clk                = 1,
+/*      .init                   = max3107_aava_init, */
+        .configure              = max3107_aava_configure,
+        .hw_suspend             = max3107_hw_susp,
+        .polled_mode            = 0,
+        .poll_time              = 0,
+};
+
+
+static int __devinit max3107_probe_aava(struct spi_device *spi)
+{
+        int err = max3107_aava_reset(spi);
+        if (err < 0)
+                return err;
+        return max3107_probe(spi, &aava_plat_data);
+}
+
+/* Spi driver data */
+static struct spi_driver max3107_driver = {
+        .driver = {
+                .name           = "aava-max3107",
+                .bus            = &spi_bus_type,
+                .owner          = THIS_MODULE,
+        },
+        .probe          = max3107_probe_aava,
+        .remove         = __devexit_p(max3107_aava_remove),
+        .suspend        = max3107_suspend,
+        .resume         = max3107_resume,
+};
+
+/* Driver init function */
+static int __init max3107_init(void)
+{
+        return spi_register_driver(&max3107_driver);
+}
+
+/* Driver exit function */
+static void __exit max3107_exit(void)
+{
+        spi_unregister_driver(&max3107_driver);
+}
+
+module_init(max3107_init);
+module_exit(max3107_exit);
+
+MODULE_DESCRIPTION("MAX3107 driver");
+MODULE_AUTHOR("Aavamobile");
+MODULE_ALIAS("spi:aava-max3107");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/tty/serial/max3107.c b/drivers/tty/serial/max3107.c
new file mode 100644
index 00000000000..a8164601c0e
--- /dev/null
+++ b/drivers/tty/serial/max3107.c
@@ -0,0 +1,1213 @@
+/*
+ *  max3107.c - spi uart protocol driver for Maxim 3107
+ *  Based on max3100.c
+ *      by Christian Pellegrin <chripell@evolware.org>
+ *  and max3110.c
+ *      by Feng Tang <feng.tang@intel.com>
+ *
+ *  Copyright (C) Aavamobile 2009
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/gpio.h>
+#include <linux/spi/spi.h>
+#include <linux/freezer.h>
+#include "max3107.h"
+
+static const struct baud_table brg26_ext[] = {
+        { 300,    MAX3107_BRG26_B300 },
+        { 600,    MAX3107_BRG26_B600 },
+        { 1200,   MAX3107_BRG26_B1200 },
+        { 2400,   MAX3107_BRG26_B2400 },
+        { 4800,   MAX3107_BRG26_B4800 },
+        { 9600,   MAX3107_BRG26_B9600 },
+        { 19200,  MAX3107_BRG26_B19200 },
+        { 57600,  MAX3107_BRG26_B57600 },
+        { 115200, MAX3107_BRG26_B115200 },
+        { 230400, MAX3107_BRG26_B230400 },
+        { 460800, MAX3107_BRG26_B460800 },
+        { 921600, MAX3107_BRG26_B921600 },
+        { 0, 0 }
+};
+
+static const struct baud_table brg13_int[] = {
+        { 300,    MAX3107_BRG13_IB300 },
+        { 600,    MAX3107_BRG13_IB600 },
+        { 1200,   MAX3107_BRG13_IB1200 },
+        { 2400,   MAX3107_BRG13_IB2400 },
+        { 4800,   MAX3107_BRG13_IB4800 },
+        { 9600,   MAX3107_BRG13_IB9600 },
+        { 19200,  MAX3107_BRG13_IB19200 },
+        { 57600,  MAX3107_BRG13_IB57600 },
+        { 115200, MAX3107_BRG13_IB115200 },
+        { 230400, MAX3107_BRG13_IB230400 },
+        { 460800, MAX3107_BRG13_IB460800 },
+        { 921600, MAX3107_BRG13_IB921600 },
+        { 0, 0 }
+};
+
+static u32 get_new_brg(int baud, struct max3107_port *s)
+{
+        int i;
+        const struct baud_table *baud_tbl = s->baud_tbl;
+
+        for (i = 0; i < 13; i++) {
+                if (baud == baud_tbl[i].baud)
+                        return baud_tbl[i].new_brg;
+        }
+
+        return 0;
+}
+
+/* Perform SPI transfer for write/read of device register(s) */
+int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len)
+{
+        struct spi_message spi_msg;
+        struct spi_transfer spi_xfer;
+
+        /* Initialize SPI ,message */
+        spi_message_init(&spi_msg);
+
+        /* Initialize SPI transfer */
+        memset(&spi_xfer, 0, sizeof spi_xfer);
+        spi_xfer.len = len;
+        spi_xfer.tx_buf = tx;
+        spi_xfer.rx_buf = rx;
+        spi_xfer.speed_hz = MAX3107_SPI_SPEED;
+
+        /* Add SPI transfer to SPI message */
+        spi_message_add_tail(&spi_xfer, &spi_msg);
+
+#ifdef DBG_TRACE_SPI_DATA
+        {
+                int i;
+                pr_info("tx len %d:\n", spi_xfer.len);
+                for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
+                        pr_info(" %x", ((u8 *)spi_xfer.tx_buf)[i]);
+                pr_info("\n");
+        }
+#endif
+
+        /* Perform synchronous SPI transfer */
+        if (spi_sync(s->spi, &spi_msg)) {
+                dev_err(&s->spi->dev, "spi_sync failure\n");
+                return -EIO;
+        }
+
+#ifdef DBG_TRACE_SPI_DATA
+        if (spi_xfer.rx_buf) {
+                int i;
+                pr_info("rx len %d:\n", spi_xfer.len);
+                for (i = 0 ; i < spi_xfer.len && i < 32 ; i++)
+                        pr_info(" %x", ((u8 *)spi_xfer.rx_buf)[i]);
+                pr_info("\n");
+        }
+#endif
+        return 0;
+}
+EXPORT_SYMBOL_GPL(max3107_rw);
+
+/* Puts received data to circular buffer */
+static void put_data_to_circ_buf(struct max3107_port *s, unsigned char *data,
+                                        int len)
+{
+        struct uart_port *port = &s->port;
+        struct tty_struct *tty;
+
+        if (!port->state)
+                return;
+
+        tty = port->state->port.tty;
+        if (!tty)
+                return;
+
+        /* Insert received data */
+        tty_insert_flip_string(tty, data, len);
+        /* Update RX counter */
+        port->icount.rx += len;
+}
+
+/* Handle data receiving */
+static void max3107_handlerx(struct max3107_port *s, u16 rxlvl)
+{
+        int i;
+        int j;
+        int len;                                /* SPI transfer buffer length */
+        u16 *buf;
+        u8 *valid_str;
+
+        if (!s->rx_enabled)
+                /* RX is disabled */
+                return;
+
+        if (rxlvl == 0) {
+                /* RX fifo is empty */
+                return;
+        } else if (rxlvl >= MAX3107_RX_FIFO_SIZE) {
+                dev_warn(&s->spi->dev, "Possible RX FIFO overrun %d\n", rxlvl);
+                /* Ensure sanity of RX level */
+                rxlvl = MAX3107_RX_FIFO_SIZE;
+        }
+        if ((s->rxbuf == 0) || (s->rxstr == 0)) {
+                dev_warn(&s->spi->dev, "Rx buffer/str isn't ready\n");
+                return;
+        }
+        buf = s->rxbuf;
+        valid_str = s->rxstr;
+        while (rxlvl) {
+                pr_debug("rxlvl %d\n", rxlvl);
+                /* Clear buffer */
+                memset(buf, 0, sizeof(u16) * (MAX3107_RX_FIFO_SIZE + 2));
+                len = 0;
+                if (s->irqen_reg & MAX3107_IRQ_RXFIFO_BIT) {
+                        /* First disable RX FIFO interrupt */
+                        pr_debug("Disabling RX INT\n");
+                        buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
+                        s->irqen_reg &= ~MAX3107_IRQ_RXFIFO_BIT;
+                        buf[0] |= s->irqen_reg;
+                        len++;
+                }
+                /* Just increase the length by amount of words in FIFO since
+                 * buffer was zeroed and SPI transfer of 0x0000 means reading
+                 * from RX FIFO
+                 */
+                len += rxlvl;
+                /* Append RX level query */
+                buf[len] = MAX3107_RXFIFOLVL_REG;
+                len++;
+
+                /* Perform the SPI transfer */
+                if (max3107_rw(s, (u8 *)buf, (u8 *)buf, len * 2)) {
+                        dev_err(&s->spi->dev, "SPI transfer for RX h failed\n");
+                        return;
+                }
+
+                /* Skip RX FIFO interrupt disabling word if it was added */
+                j = ((len - 1) - rxlvl);
+                /* Read received words */
+                for (i = 0; i < rxlvl; i++, j++)
+                        valid_str[i] = (u8)buf[j];
+                put_data_to_circ_buf(s, valid_str, rxlvl);
+                /* Get new RX level */
+                rxlvl = (buf[len - 1] & MAX3107_SPI_RX_DATA_MASK);
+        }
+
+        if (s->rx_enabled) {
+                /* RX still enabled, re-enable RX FIFO interrupt */
+                pr_debug("Enabling RX INT\n");
+                buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
+                s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
+                buf[0] |= s->irqen_reg;
+                if (max3107_rw(s, (u8 *)buf, NULL, 2))
+                        dev_err(&s->spi->dev, "RX FIFO INT enabling failed\n");
+        }
+
+        /* Push the received data to receivers */
+        if (s->port.state->port.tty)
+                tty_flip_buffer_push(s->port.state->port.tty);
+}
+
+
+/* Handle data sending */
+static void max3107_handletx(struct max3107_port *s)
+{
+        struct circ_buf *xmit = &s->port.state->xmit;
+        int i;
+        unsigned long flags;
+        int len;                                /* SPI transfer buffer length */
+        u16 *buf;
+
+        if (!s->tx_fifo_empty)
+                /* Don't send more data before previous data is sent */
+                return;
+
+        if (uart_circ_empty(xmit) || uart_tx_stopped(&s->port))
+                /* No data to send or TX is stopped */
+                return;
+
+        if (!s->txbuf) {
+                dev_warn(&s->spi->dev, "Txbuf isn't ready\n");
+                return;
+        }
+        buf = s->txbuf;
+        /* Get length of data pending in circular buffer */
+        len = uart_circ_chars_pending(xmit);
+        if (len) {
+                /* Limit to size of TX FIFO */
+                if (len > MAX3107_TX_FIFO_SIZE)
+                        len = MAX3107_TX_FIFO_SIZE;
+
+                pr_debug("txlen %d\n", len);
+
+                /* Update TX counter */
+                s->port.icount.tx += len;
+
+                /* TX FIFO will no longer be empty */
+                s->tx_fifo_empty = 0;
+
+                i = 0;
+                if (s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT) {
+                        /* First disable TX empty interrupt */
+                        pr_debug("Disabling TE INT\n");
+                        buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
+                        s->irqen_reg &= ~MAX3107_IRQ_TXEMPTY_BIT;
+                        buf[i] |= s->irqen_reg;
+                        i++;
+                        len++;
+                }
+                /* Add data to send */
+                spin_lock_irqsave(&s->port.lock, flags);
+                for ( ; i < len ; i++) {
+                        buf[i] = (MAX3107_WRITE_BIT | MAX3107_THR_REG);
+                        buf[i] |= ((u16)xmit->buf[xmit->tail] &
+                                                MAX3107_SPI_TX_DATA_MASK);
+                        xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+                }
+                spin_unlock_irqrestore(&s->port.lock, flags);
+                if (!(s->irqen_reg & MAX3107_IRQ_TXEMPTY_BIT)) {
+                        /* Enable TX empty interrupt */
+                        pr_debug("Enabling TE INT\n");
+                        buf[i] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG);
+                        s->irqen_reg |= MAX3107_IRQ_TXEMPTY_BIT;
+                        buf[i] |= s->irqen_reg;
+                        i++;
+                        len++;
+                }
+                if (!s->tx_enabled) {
+                        /* Enable TX */
+                        pr_debug("Enable TX\n");
+                        buf[i] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
+                        spin_lock_irqsave(&s->data_lock, flags);
+                        s->mode1_reg &= ~MAX3107_MODE1_TXDIS_BIT;
+                        buf[i] |= s->mode1_reg;
+                        spin_unlock_irqrestore(&s->data_lock, flags);
+                        s->tx_enabled = 1;
+                        i++;
+                        len++;
+                }
+
+                /* Perform the SPI transfer */
+                if (max3107_rw(s, (u8 *)buf, NULL, len*2)) {
+                        dev_err(&s->spi->dev,
+                                "SPI transfer TX handling failed\n");
+                        return;
+                }
+        }
+
+        /* Indicate wake up if circular buffer is getting low on data */
+        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+                uart_write_wakeup(&s->port);
+
+}
+
+/* Handle interrupts
+ * Also reads and returns current RX FIFO level
+ */
+static u16 handle_interrupt(struct max3107_port *s)
+{
+        u16 buf[4];     /* Buffer for SPI transfers */
+        u8 irq_status;
+        u16 rx_level;
+        unsigned long flags;
+
+        /* Read IRQ status register */
+        buf[0] = MAX3107_IRQSTS_REG;
+        /* Read status IRQ status register */
+        buf[1] = MAX3107_STS_IRQSTS_REG;
+        /* Read LSR IRQ status register */
+        buf[2] = MAX3107_LSR_IRQSTS_REG;
+        /* Query RX level */
+        buf[3] = MAX3107_RXFIFOLVL_REG;
+
+        if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 8)) {
+                dev_err(&s->spi->dev,
+                        "SPI transfer for INTR handling failed\n");
+                return 0;
+        }
+
+        irq_status = (u8)buf[0];
+        pr_debug("IRQSTS %x\n", irq_status);
+        rx_level = (buf[3] & MAX3107_SPI_RX_DATA_MASK);
+
+        if (irq_status & MAX3107_IRQ_LSR_BIT) {
+                /* LSR interrupt */
+                if (buf[2] & MAX3107_LSR_RXTO_BIT)
+                        /* RX timeout interrupt,
+                         * handled by normal RX handling
+                         */
+                        pr_debug("RX TO INT\n");
+        }
+
+        if (irq_status & MAX3107_IRQ_TXEMPTY_BIT) {
+                /* Tx empty interrupt,
+                 * disable TX and set tx_fifo_empty flag
+                 */
+                pr_debug("TE INT, disabling TX\n");
+                buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
+                spin_lock_irqsave(&s->data_lock, flags);
+                s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
+                buf[0] |= s->mode1_reg;
+                spin_unlock_irqrestore(&s->data_lock, flags);
+                if (max3107_rw(s, (u8 *)buf, NULL, 2))
+                        dev_err(&s->spi->dev, "SPI transfer TX dis failed\n");
+                s->tx_enabled = 0;
+                s->tx_fifo_empty = 1;
+        }
+
+        if (irq_status & MAX3107_IRQ_RXFIFO_BIT)
+                /* RX FIFO interrupt,
+                 * handled by normal RX handling
+                 */
+                pr_debug("RFIFO INT\n");
+
+        /* Return RX level */
+        return rx_level;
+}
+
+/* Trigger work thread*/
+static void max3107_dowork(struct max3107_port *s)
+{
+        if (!work_pending(&s->work) && !freezing(current) && !s->suspended)
+                queue_work(s->workqueue, &s->work);
+        else
+                dev_warn(&s->spi->dev, "interrup isn't serviced normally!\n");
+}
+
+/* Work thread */
+static void max3107_work(struct work_struct *w)
+{
+        struct max3107_port *s = container_of(w, struct max3107_port, work);
+        u16 rxlvl = 0;
+        int len;        /* SPI transfer buffer length */
+        u16 buf[5];     /* Buffer for SPI transfers */
+        unsigned long flags;
+
+        /* Start by reading current RX FIFO level */
+        buf[0] = MAX3107_RXFIFOLVL_REG;
+        if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
+                dev_err(&s->spi->dev, "SPI transfer RX lev failed\n");
+                rxlvl = 0;
+        } else {
+                rxlvl = (buf[0] & MAX3107_SPI_RX_DATA_MASK);
+        }
+
+        do {
+                pr_debug("rxlvl %d\n", rxlvl);
+
+                /* Handle RX */
+                max3107_handlerx(s, rxlvl);
+                rxlvl = 0;
+
+                if (s->handle_irq) {
+                        /* Handle pending interrupts
+                         * We also get new RX FIFO level since new data may
+                         * have been received while pushing received data to
+                         * receivers
+                         */
+                        s->handle_irq = 0;
+                        rxlvl = handle_interrupt(s);
+                }
+
+                /* Handle TX */
+                max3107_handletx(s);
+
+                /* Handle configuration changes */
+                len = 0;
+                spin_lock_irqsave(&s->data_lock, flags);
+                if (s->mode1_commit) {
+                        pr_debug("mode1_commit\n");
+                        buf[len] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
+                        buf[len++] |= s->mode1_reg;
+                        s->mode1_commit = 0;
+                }
+                if (s->lcr_commit) {
+                        pr_debug("lcr_commit\n");
+                        buf[len] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG);
+                        buf[len++] |= s->lcr_reg;
+                        s->lcr_commit = 0;
+                }
+                if (s->brg_commit) {
+                        pr_debug("brg_commit\n");
+                        buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG);
+                        buf[len++] |= ((s->brg_cfg >> 16) &
+                                                MAX3107_SPI_TX_DATA_MASK);
+                        buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG);
+                        buf[len++] |= ((s->brg_cfg >> 8) &
+                                                MAX3107_SPI_TX_DATA_MASK);
+                        buf[len] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG);
+                        buf[len++] |= ((s->brg_cfg) & 0xff);
+                        s->brg_commit = 0;
+                }
+                spin_unlock_irqrestore(&s->data_lock, flags);
+
+                if (len > 0) {
+                        if (max3107_rw(s, (u8 *)buf, NULL, len * 2))
+                                dev_err(&s->spi->dev,
+                                        "SPI transfer config failed\n");
+                }
+
+                /* Reloop if interrupt handling indicated data in RX FIFO */
+        } while (rxlvl);
+
+}
+
+/* Set sleep mode */
+static void max3107_set_sleep(struct max3107_port *s, int mode)
+{
+        u16 buf[1];     /* Buffer for SPI transfer */
+        unsigned long flags;
+        pr_debug("enter, mode %d\n", mode);
+
+        buf[0] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG);
+        spin_lock_irqsave(&s->data_lock, flags);
+        switch (mode) {
+        case MAX3107_DISABLE_FORCED_SLEEP:
+                        s->mode1_reg &= ~MAX3107_MODE1_FORCESLEEP_BIT;
+                        break;
+        case MAX3107_ENABLE_FORCED_SLEEP:
+                        s->mode1_reg |= MAX3107_MODE1_FORCESLEEP_BIT;
+                        break;
+        case MAX3107_DISABLE_AUTOSLEEP:
+                        s->mode1_reg &= ~MAX3107_MODE1_AUTOSLEEP_BIT;
+                        break;
+        case MAX3107_ENABLE_AUTOSLEEP:
+                        s->mode1_reg |= MAX3107_MODE1_AUTOSLEEP_BIT;
+                        break;
+        default:
+                spin_unlock_irqrestore(&s->data_lock, flags);
+                dev_warn(&s->spi->dev, "invalid sleep mode\n");
+                return;
+        }
+        buf[0] |= s->mode1_reg;
+        spin_unlock_irqrestore(&s->data_lock, flags);
+
+        if (max3107_rw(s, (u8 *)buf, NULL, 2))
+                dev_err(&s->spi->dev, "SPI transfer sleep mode failed\n");
+
+        if (mode == MAX3107_DISABLE_AUTOSLEEP ||
+                        mode == MAX3107_DISABLE_FORCED_SLEEP)
+                msleep(MAX3107_WAKEUP_DELAY);
+}
+
+/* Perform full register initialization */
+static void max3107_register_init(struct max3107_port *s)
+{
+        u16 buf[11];    /* Buffer for SPI transfers */
+
+        /* 1. Configure baud rate, 9600 as default */
+        s->baud = 9600;
+        /* the below is default*/
+        if (s->ext_clk) {
+                s->brg_cfg = MAX3107_BRG26_B9600;
+                s->baud_tbl = (struct baud_table *)brg26_ext;
+        } else {
+                s->brg_cfg = MAX3107_BRG13_IB9600;
+                s->baud_tbl = (struct baud_table *)brg13_int;
+        }
+
+        if (s->pdata->init)
+                s->pdata->init(s);
+
+        buf[0] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVMSB_REG)
+                | ((s->brg_cfg >> 16) & MAX3107_SPI_TX_DATA_MASK);
+        buf[1] = (MAX3107_WRITE_BIT | MAX3107_BRGDIVLSB_REG)
+                | ((s->brg_cfg >> 8) & MAX3107_SPI_TX_DATA_MASK);
+        buf[2] = (MAX3107_WRITE_BIT | MAX3107_BRGCFG_REG)
+                | ((s->brg_cfg) & 0xff);
+
+        /* 2. Configure LCR register, 8N1 mode by default */
+        s->lcr_reg = MAX3107_LCR_WORD_LEN_8;
+        buf[3] = (MAX3107_WRITE_BIT | MAX3107_LCR_REG)
+                | s->lcr_reg;
+
+        /* 3. Configure MODE 1 register */
+        s->mode1_reg = 0;
+        /* Enable IRQ pin */
+        s->mode1_reg |= MAX3107_MODE1_IRQSEL_BIT;
+        /* Disable TX */
+        s->mode1_reg |= MAX3107_MODE1_TXDIS_BIT;
+        s->tx_enabled = 0;
+        /* RX is enabled */
+        s->rx_enabled = 1;
+        buf[4] = (MAX3107_WRITE_BIT | MAX3107_MODE1_REG)
+                | s->mode1_reg;
+
+        /* 4. Configure MODE 2 register */
+        buf[5] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
+        if (s->loopback) {
+                /* Enable loopback */
+                buf[5] |= MAX3107_MODE2_LOOPBACK_BIT;
+        }
+        /* Reset FIFOs */
+        buf[5] |= MAX3107_MODE2_FIFORST_BIT;
+        s->tx_fifo_empty = 1;
+
+        /* 5. Configure FIFO trigger level register */
+        buf[6] = (MAX3107_WRITE_BIT | MAX3107_FIFOTRIGLVL_REG);
+        /* RX FIFO trigger for 16 words, TX FIFO trigger not used */
+        buf[6] |= (MAX3107_FIFOTRIGLVL_RX(16) | MAX3107_FIFOTRIGLVL_TX(0));
+
+        /* 6. Configure flow control levels */
+        buf[7] = (MAX3107_WRITE_BIT | MAX3107_FLOWLVL_REG);
+        /* Flow control halt level 96, resume level 48 */
+        buf[7] |= (MAX3107_FLOWLVL_RES(48) | MAX3107_FLOWLVL_HALT(96));
+
+        /* 7. Configure flow control */
+        buf[8] = (MAX3107_WRITE_BIT | MAX3107_FLOWCTRL_REG);
+        /* Enable auto CTS and auto RTS flow control */
+        buf[8] |= (MAX3107_FLOWCTRL_AUTOCTS_BIT | MAX3107_FLOWCTRL_AUTORTS_BIT);
+
+        /* 8. Configure RX timeout register */
+        buf[9] = (MAX3107_WRITE_BIT | MAX3107_RXTO_REG);
+        /* Timeout after 48 character intervals */
+        buf[9] |= 0x0030;
+
+        /* 9. Configure LSR interrupt enable register */
+        buf[10] = (MAX3107_WRITE_BIT | MAX3107_LSR_IRQEN_REG);
+        /* Enable RX timeout interrupt */
+        buf[10] |= MAX3107_LSR_RXTO_BIT;
+
+        /* Perform SPI transfer */
+        if (max3107_rw(s, (u8 *)buf, NULL, 22))
+                dev_err(&s->spi->dev, "SPI transfer for init failed\n");
+
+        /* 10. Clear IRQ status register by reading it */
+        buf[0] = MAX3107_IRQSTS_REG;
+
+        /* 11. Configure interrupt enable register */
+        /* Enable LSR interrupt */
+        s->irqen_reg = MAX3107_IRQ_LSR_BIT;
+        /* Enable RX FIFO interrupt */
+        s->irqen_reg |= MAX3107_IRQ_RXFIFO_BIT;
+        buf[1] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG)
+                | s->irqen_reg;
+
+        /* 12. Clear FIFO reset that was set in step 6 */
+        buf[2] = (MAX3107_WRITE_BIT | MAX3107_MODE2_REG);
+        if (s->loopback) {
+                /* Keep loopback enabled */
+                buf[2] |= MAX3107_MODE2_LOOPBACK_BIT;
+        }
+
+        /* Perform SPI transfer */
+        if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 6))
+                dev_err(&s->spi->dev, "SPI transfer for init failed\n");
+
+}
+
+/* IRQ handler */
+static irqreturn_t max3107_irq(int irqno, void *dev_id)
+{
+        struct max3107_port *s = dev_id;
+
+        if (irqno != s->spi->irq) {
+                /* Unexpected IRQ */
+                return IRQ_NONE;
+        }
+
+        /* Indicate irq */
+        s->handle_irq = 1;
+
+        /* Trigger work thread */
+        max3107_dowork(s);
+
+        return IRQ_HANDLED;
+}
+
+/* HW suspension function
+ *
+ * Currently autosleep is used to decrease current consumption, alternative
+ * approach would be to set the chip to reset mode if UART is not being
+ * used but that would mess the GPIOs
+ *
+ */
+void max3107_hw_susp(struct max3107_port *s, int suspend)
+{
+        pr_debug("enter, suspend %d\n", suspend);
+
+        if (suspend) {
+                /* Suspend requested,
+                 * enable autosleep to decrease current consumption
+                 */
+                s->suspended = 1;
+                max3107_set_sleep(s, MAX3107_ENABLE_AUTOSLEEP);
+        } else {
+                /* Resume requested,
+                 * disable autosleep
+                 */
+                s->suspended = 0;
+                max3107_set_sleep(s, MAX3107_DISABLE_AUTOSLEEP);
+        }
+}
+EXPORT_SYMBOL_GPL(max3107_hw_susp);
+
+/* Modem status IRQ enabling */
+static void max3107_enable_ms(struct uart_port *port)
+{
+        /* Modem status not supported */
+}
+
+/* Data send function */
+static void max3107_start_tx(struct uart_port *port)
+{
+        struct max3107_port *s = container_of(port, struct max3107_port, port);
+
+        /* Trigger work thread for sending data */
+        max3107_dowork(s);
+}
+
+/* Function for checking that there is no pending transfers */
+static unsigned int max3107_tx_empty(struct uart_port *port)
+{
+        struct max3107_port *s = container_of(port, struct max3107_port, port);
+
+        pr_debug("returning %d\n",
+                  (s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit)));
+        return s->tx_fifo_empty && uart_circ_empty(&s->port.state->xmit);
+}
+
+/* Function for stopping RX */
+static void max3107_stop_rx(struct uart_port *port)
+{
+        struct max3107_port *s = container_of(port, struct max3107_port, port);
+        unsigned long flags;
+
+        /* Set RX disabled in MODE 1 register */
+        spin_lock_irqsave(&s->data_lock, flags);
+        s->mode1_reg |= MAX3107_MODE1_RXDIS_BIT;
+        s->mode1_commit = 1;
+        spin_unlock_irqrestore(&s->data_lock, flags);
+        /* Set RX disabled */
+        s->rx_enabled = 0;
+        /* Trigger work thread for doing the actual configuration change */
+        max3107_dowork(s);
+}
+
+/* Function for returning control pin states */
+static unsigned int max3107_get_mctrl(struct uart_port *port)
+{
+        /* DCD and DSR are not wired and CTS/RTS is handled automatically
+         * so just indicate DSR and CAR asserted
+         */
+        return TIOCM_DSR | TIOCM_CAR;
+}
+
+/* Function for setting control pin states */
+static void max3107_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+        /* DCD and DSR are not wired and CTS/RTS is hadnled automatically
+         * so do nothing
+         */
+}
+
+/* Function for configuring UART parameters */
+static void max3107_set_termios(struct uart_port *port,
+                                struct ktermios *termios,
+                                struct ktermios *old)
+{
+        struct max3107_port *s = container_of(port, struct max3107_port, port);
+        struct tty_struct *tty;
+        int baud;
+        u16 new_lcr = 0;
+        u32 new_brg = 0;
+        unsigned long flags;
+
+        if (!port->state)
+                return;
+
+        tty = port->state->port.tty;
+        if (!tty)
+                return;
+
+        /* Get new LCR register values */
+        /* Word size */
+        if ((termios->c_cflag & CSIZE) == CS7)
+                new_lcr |= MAX3107_LCR_WORD_LEN_7;
+        else
+                new_lcr |= MAX3107_LCR_WORD_LEN_8;
+
+        /* Parity */
+        if (termios->c_cflag & PARENB) {
+                new_lcr |= MAX3107_LCR_PARITY_BIT;
+                if (!(termios->c_cflag & PARODD))
+                        new_lcr |= MAX3107_LCR_EVENPARITY_BIT;
+        }
+
+        /* Stop bits */
+        if (termios->c_cflag & CSTOPB) {
+                /* 2 stop bits */
+                new_lcr |= MAX3107_LCR_STOPLEN_BIT;
+        }
+
+        /* Mask termios capabilities we don't support */
+        termios->c_cflag &= ~CMSPAR;
+
+        /* Set status ignore mask */
+        s->port.ignore_status_mask = 0;
+        if (termios->c_iflag & IGNPAR)
+                s->port.ignore_status_mask |= MAX3107_ALL_ERRORS;
+
+        /* Set low latency to immediately handle pushed data */
+        s->port.state->port.tty->low_latency = 1;
+
+        /* Get new baud rate generator configuration */
+        baud = tty_get_baud_rate(tty);
+
+        spin_lock_irqsave(&s->data_lock, flags);
+        new_brg = get_new_brg(baud, s);
+        /* if can't find the corrent config, use previous */
+        if (!new_brg) {
+                baud = s->baud;
+                new_brg = s->brg_cfg;
+        }
+        spin_unlock_irqrestore(&s->data_lock, flags);
+        tty_termios_encode_baud_rate(termios, baud, baud);
+        s->baud = baud;
+
+        /* Update timeout according to new baud rate */
+        uart_update_timeout(port, termios->c_cflag, baud);
+
+        spin_lock_irqsave(&s->data_lock, flags);
+        if (s->lcr_reg != new_lcr) {
+                s->lcr_reg = new_lcr;
+                s->lcr_commit = 1;
+        }
+        if (s->brg_cfg != new_brg) {
+                s->brg_cfg = new_brg;
+                s->brg_commit = 1;
+        }
+        spin_unlock_irqrestore(&s->data_lock, flags);
+
+        /* Trigger work thread for doing the actual configuration change */
+        max3107_dowork(s);
+}
+
+/* Port shutdown function */
+static void max3107_shutdown(struct uart_port *port)
+{
+        struct max3107_port *s = container_of(port, struct max3107_port, port);
+
+        if (s->suspended && s->pdata->hw_suspend)
+                s->pdata->hw_suspend(s, 0);
+
+        /* Free the interrupt */
+        free_irq(s->spi->irq, s);
+
+        if (s->workqueue) {
+                /* Flush and destroy work queue */
+                flush_workqueue(s->workqueue);
+                destroy_workqueue(s->workqueue);
+                s->workqueue = NULL;
+        }
+
+        /* Suspend HW */
+        if (s->pdata->hw_suspend)
+                s->pdata->hw_suspend(s, 1);
+}
+
+/* Port startup function */
+static int max3107_startup(struct uart_port *port)
+{
+        struct max3107_port *s = container_of(port, struct max3107_port, port);
+
+        /* Initialize work queue */
+        s->workqueue = create_freezable_workqueue("max3107");
+        if (!s->workqueue) {
+                dev_err(&s->spi->dev, "Workqueue creation failed\n");
+                return -EBUSY;
+        }
+        INIT_WORK(&s->work, max3107_work);
+
+        /* Setup IRQ */
+        if (request_irq(s->spi->irq, max3107_irq, IRQF_TRIGGER_FALLING,
+                        "max3107", s)) {
+                dev_err(&s->spi->dev, "IRQ reguest failed\n");
+                destroy_workqueue(s->workqueue);
+                s->workqueue = NULL;
+                return -EBUSY;
+        }
+
+        /* Resume HW */
+        if (s->pdata->hw_suspend)
+                s->pdata->hw_suspend(s, 0);
+
+        /* Init registers */
+        max3107_register_init(s);
+
+        return 0;
+}
+
+/* Port type function */
+static const char *max3107_type(struct uart_port *port)
+{
+        struct max3107_port *s = container_of(port, struct max3107_port, port);
+        return s->spi->modalias;
+}
+
+/* Port release function */
+static void max3107_release_port(struct uart_port *port)
+{
+        /* Do nothing */
+}
+
+/* Port request function */
+static int max3107_request_port(struct uart_port *port)
+{
+        /* Do nothing */
+        return 0;
+}
+
+/* Port config function */
+static void max3107_config_port(struct uart_port *port, int flags)
+{
+        struct max3107_port *s = container_of(port, struct max3107_port, port);
+        s->port.type = PORT_MAX3107;
+}
+
+/* Port verify function */
+static int max3107_verify_port(struct uart_port *port,
+                                struct serial_struct *ser)
+{
+        if (ser->type == PORT_UNKNOWN || ser->type == PORT_MAX3107)
+                return 0;
+
+        return -EINVAL;
+}
+
+/* Port stop TX function */
+static void max3107_stop_tx(struct uart_port *port)
+{
+        /* Do nothing */
+}
+
+/* Port break control function */
+static void max3107_break_ctl(struct uart_port *port, int break_state)
+{
+        /* We don't support break control, do nothing */
+}
+
+
+/* Port functions */
+static struct uart_ops max3107_ops = {
+        .tx_empty       = max3107_tx_empty,
+        .set_mctrl      = max3107_set_mctrl,
+        .get_mctrl      = max3107_get_mctrl,
+        .stop_tx        = max3107_stop_tx,
+        .start_tx       = max3107_start_tx,
+        .stop_rx        = max3107_stop_rx,
+        .enable_ms      = max3107_enable_ms,
+        .break_ctl      = max3107_break_ctl,
+        .startup        = max3107_startup,
+        .shutdown       = max3107_shutdown,
+        .set_termios    = max3107_set_termios,
+        .type           = max3107_type,
+        .release_port   = max3107_release_port,
+        .request_port   = max3107_request_port,
+        .config_port    = max3107_config_port,
+        .verify_port    = max3107_verify_port,
+};
+
+/* UART driver data */
+static struct uart_driver max3107_uart_driver = {
+        .owner          = THIS_MODULE,
+        .driver_name    = "ttyMAX",
+        .dev_name       = "ttyMAX",
+        .nr             = 1,
+};
+
+static int driver_registered = 0;
+
+
+
+/* 'Generic' platform data */
+static struct max3107_plat generic_plat_data = {
+        .loopback               = 0,
+        .ext_clk                = 1,
+        .hw_suspend             = max3107_hw_susp,
+        .polled_mode            = 0,
+        .poll_time              = 0,
+};
+
+
+/*******************************************************************/
+
+/**
+ *      max3107_probe           -       SPI bus probe entry point
+ *      @spi: the spi device
+ *
+ *      SPI wants us to probe this device and if appropriate claim it.
+ *      Perform any platform specific requirements and then initialise
+ *      the device.
+ */
+
+int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata)
+{
+        struct max3107_port *s;
+        u16 buf[2];     /* Buffer for SPI transfers */
+        int retval;
+
+        pr_info("enter max3107 probe\n");
+
+        /* Allocate port structure */
+        s = kzalloc(sizeof(*s), GFP_KERNEL);
+        if (!s) {
+                pr_err("Allocating port structure failed\n");
+                return -ENOMEM;
+        }
+
+        s->pdata = pdata;
+
+        /* SPI Rx buffer
+         * +2 for RX FIFO interrupt
+         * disabling and RX level query
+         */
+        s->rxbuf = kzalloc(sizeof(u16) * (MAX3107_RX_FIFO_SIZE+2), GFP_KERNEL);
+        if (!s->rxbuf) {
+                pr_err("Allocating RX buffer failed\n");
+                retval = -ENOMEM;
+                goto err_free4;
+        }
+        s->rxstr = kzalloc(sizeof(u8) * MAX3107_RX_FIFO_SIZE, GFP_KERNEL);
+        if (!s->rxstr) {
+                pr_err("Allocating RX buffer failed\n");
+                retval = -ENOMEM;
+                goto err_free3;
+        }
+        /* SPI Tx buffer
+         * SPI transfer buffer
+         * +3 for TX FIFO empty
+         * interrupt disabling and
+         * enabling and TX enabling
+         */
+        s->txbuf = kzalloc(sizeof(u16) * MAX3107_TX_FIFO_SIZE + 3, GFP_KERNEL);
+        if (!s->txbuf) {
+                pr_err("Allocating TX buffer failed\n");
+                retval = -ENOMEM;
+                goto err_free2;
+        }
+        /* Initialize shared data lock */
+        spin_lock_init(&s->data_lock);
+
+        /* SPI intializations */
+        dev_set_drvdata(&spi->dev, s);
+        spi->mode = SPI_MODE_0;
+        spi->dev.platform_data = pdata;
+        spi->bits_per_word = 16;
+        s->ext_clk = pdata->ext_clk;
+        s->loopback = pdata->loopback;
+        spi_setup(spi);
+        s->spi = spi;
+
+        /* Check REV ID to ensure we are talking to what we expect */
+        buf[0] = MAX3107_REVID_REG;
+        if (max3107_rw(s, (u8 *)buf, (u8 *)buf, 2)) {
+                dev_err(&s->spi->dev, "SPI transfer for REVID read failed\n");
+                retval = -EIO;
+                goto err_free1;
+        }
+        if ((buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID1 &&
+                (buf[0] & MAX3107_SPI_RX_DATA_MASK) != MAX3107_REVID2) {
+                dev_err(&s->spi->dev, "REVID %x does not match\n",
+                                (buf[0] & MAX3107_SPI_RX_DATA_MASK));
+                retval = -ENODEV;
+                goto err_free1;
+        }
+
+        /* Disable all interrupts */
+        buf[0] = (MAX3107_WRITE_BIT | MAX3107_IRQEN_REG | 0x0000);
+        buf[0] |= 0x0000;
+
+        /* Configure clock source */
+        buf[1] = (MAX3107_WRITE_BIT | MAX3107_CLKSRC_REG);
+        if (s->ext_clk) {
+                /* External clock */
+                buf[1] |= MAX3107_CLKSRC_EXTCLK_BIT;
+        }
+
+        /* PLL bypass ON */
+        buf[1] |= MAX3107_CLKSRC_PLLBYP_BIT;
+
+        /* Perform SPI transfer */
+        if (max3107_rw(s, (u8 *)buf, NULL, 4)) {
+                dev_err(&s->spi->dev, "SPI transfer for init failed\n");
+                retval = -EIO;
+                goto err_free1;
+        }
+
+        /* Register UART driver */
+        if (!driver_registered) {
+                retval = uart_register_driver(&max3107_uart_driver);
+                if (retval) {
+                        dev_err(&s->spi->dev, "Registering UART driver failed\n");
+                        goto err_free1;
+                }
+                driver_registered = 1;
+        }
+
+        /* Initialize UART port data */
+        s->port.fifosize = 128;
+        s->port.ops = &max3107_ops;
+        s->port.line = 0;
+        s->port.dev = &spi->dev;
+        s->port.uartclk = 9600;
+        s->port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF;
+        s->port.irq = s->spi->irq;
+        s->port.type = PORT_MAX3107;
+
+        /* Add UART port */
+        retval = uart_add_one_port(&max3107_uart_driver, &s->port);
+        if (retval < 0) {
+                dev_err(&s->spi->dev, "Adding UART port failed\n");
+                goto err_free1;
+        }
+
+        if (pdata->configure) {
+                retval = pdata->configure(s);
+                if (retval < 0)
+                        goto err_free1;
+        }
+
+        /* Go to suspend mode */
+        if (pdata->hw_suspend)
+                pdata->hw_suspend(s, 1);
+
+        return 0;
+
+err_free1:
+        kfree(s->txbuf);
+err_free2:
+        kfree(s->rxstr);
+err_free3:
+        kfree(s->rxbuf);
+err_free4:
+        kfree(s);
+        return retval;
+}
+EXPORT_SYMBOL_GPL(max3107_probe);
+
+/* Driver remove function */
+int max3107_remove(struct spi_device *spi)
+{
+        struct max3107_port *s = dev_get_drvdata(&spi->dev);
+
+        pr_info("enter max3107 remove\n");
+
+        /* Remove port */
+        if (uart_remove_one_port(&max3107_uart_driver, &s->port))
+                dev_warn(&s->spi->dev, "Removing UART port failed\n");
+
+
+        /* Free TxRx buffer */
+        kfree(s->rxbuf);
+        kfree(s->rxstr);
+        kfree(s->txbuf);
+
+        /* Free port structure */
+        kfree(s);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(max3107_remove);
+
+/* Driver suspend function */
+int max3107_suspend(struct spi_device *spi, pm_message_t state)
+{
+#ifdef CONFIG_PM
+        struct max3107_port *s = dev_get_drvdata(&spi->dev);
+
+        pr_debug("enter suspend\n");
+
+        /* Suspend UART port */
+        uart_suspend_port(&max3107_uart_driver, &s->port);
+
+        /* Go to suspend mode */
+        if (s->pdata->hw_suspend)
+                s->pdata->hw_suspend(s, 1);
+#endif  /* CONFIG_PM */
+        return 0;
+}
+EXPORT_SYMBOL_GPL(max3107_suspend);
+
+/* Driver resume function */
+int max3107_resume(struct spi_device *spi)
+{
+#ifdef CONFIG_PM
+        struct max3107_port *s = dev_get_drvdata(&spi->dev);
+
+        pr_debug("enter resume\n");
+
+        /* Resume from suspend */
+        if (s->pdata->hw_suspend)
+                s->pdata->hw_suspend(s, 0);
+
+        /* Resume UART port */
+        uart_resume_port(&max3107_uart_driver, &s->port);
+#endif  /* CONFIG_PM */
+        return 0;
+}
+EXPORT_SYMBOL_GPL(max3107_resume);
+
+static int max3107_probe_generic(struct spi_device *spi)
+{
+        return max3107_probe(spi, &generic_plat_data);
+}
+
+/* Spi driver data */
+static struct spi_driver max3107_driver = {
+        .driver = {
+                .name           = "max3107",
+                .bus            = &spi_bus_type,
+                .owner          = THIS_MODULE,
+        },
+        .probe          = max3107_probe_generic,
+        .remove         = __devexit_p(max3107_remove),
+        .suspend        = max3107_suspend,
+        .resume         = max3107_resume,
+};
+
+/* Driver init function */
+static int __init max3107_init(void)
+{
+        pr_info("enter max3107 init\n");
+        return spi_register_driver(&max3107_driver);
+}
+
+/* Driver exit function */
+static void __exit max3107_exit(void)
+{
+        pr_info("enter max3107 exit\n");
+        /* Unregister UART driver */
+        if (driver_registered)
+                uart_unregister_driver(&max3107_uart_driver);
+        spi_unregister_driver(&max3107_driver);
+}
+
+module_init(max3107_init);
+module_exit(max3107_exit);
+
+MODULE_DESCRIPTION("MAX3107 driver");
+MODULE_AUTHOR("Aavamobile");
+MODULE_ALIAS("spi:max3107");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/tty/serial/max3107.h b/drivers/tty/serial/max3107.h
new file mode 100644
index 00000000000..8415fc723b9
--- /dev/null
+++ b/drivers/tty/serial/max3107.h
@@ -0,0 +1,441 @@
+/*
+ * max3107.h - spi uart protocol driver header for Maxim 3107
+ *
+ * Copyright (C) Aavamobile 2009
+ * Based on serial_max3100.h by Christian Pellegrin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _MAX3107_H
+#define _MAX3107_H
+
+/* Serial error status definitions */
+#define MAX3107_PARITY_ERROR    1
+#define MAX3107_FRAME_ERROR     2
+#define MAX3107_OVERRUN_ERROR   4
+#define MAX3107_ALL_ERRORS      (MAX3107_PARITY_ERROR | \
+                                 MAX3107_FRAME_ERROR | \
+                                 MAX3107_OVERRUN_ERROR)
+
+/* GPIO definitions */
+#define MAX3107_GPIO_BASE       88
+#define MAX3107_GPIO_COUNT      4
+
+
+/* GPIO connected to chip's reset pin */
+#define MAX3107_RESET_GPIO      87
+
+
+/* Chip reset delay */
+#define MAX3107_RESET_DELAY     10
+
+/* Chip wakeup delay */
+#define MAX3107_WAKEUP_DELAY    50
+
+
+/* Sleep mode definitions */
+#define MAX3107_DISABLE_FORCED_SLEEP    0
+#define MAX3107_ENABLE_FORCED_SLEEP     1
+#define MAX3107_DISABLE_AUTOSLEEP       2
+#define MAX3107_ENABLE_AUTOSLEEP        3
+
+
+/* Definitions for register access with SPI transfers
+ *
+ * SPI transfer format:
+ *
+ * Master to slave bits xzzzzzzzyyyyyyyy
+ * Slave to master bits aaaaaaaabbbbbbbb
+ *
+ * where:
+ * x = 0 for reads, 1 for writes
+ * z = register address
+ * y = new register value if write, 0 if read
+ * a = unspecified
+ * b = register value if read, unspecified if write
+ */
+
+/* SPI speed */
+#define MAX3107_SPI_SPEED       (3125000 * 2)
+
+/* Write bit */
+#define MAX3107_WRITE_BIT       (1 << 15)
+
+/* SPI TX data mask */
+#define MAX3107_SPI_RX_DATA_MASK        (0x00ff)
+
+/* SPI RX data mask */
+#define MAX3107_SPI_TX_DATA_MASK        (0x00ff)
+
+/* Register access masks */
+#define MAX3107_RHR_REG                 (0x0000) /* RX FIFO */
+#define MAX3107_THR_REG                 (0x0000) /* TX FIFO */
+#define MAX3107_IRQEN_REG               (0x0100) /* IRQ enable */
+#define MAX3107_IRQSTS_REG              (0x0200) /* IRQ status */
+#define MAX3107_LSR_IRQEN_REG           (0x0300) /* LSR IRQ enable */
+#define MAX3107_LSR_IRQSTS_REG          (0x0400) /* LSR IRQ status */
+#define MAX3107_SPCHR_IRQEN_REG         (0x0500) /* Special char IRQ enable */
+#define MAX3107_SPCHR_IRQSTS_REG        (0x0600) /* Special char IRQ status */
+#define MAX3107_STS_IRQEN_REG           (0x0700) /* Status IRQ enable */
+#define MAX3107_STS_IRQSTS_REG          (0x0800) /* Status IRQ status */
+#define MAX3107_MODE1_REG               (0x0900) /* MODE1 */
+#define MAX3107_MODE2_REG               (0x0a00) /* MODE2 */
+#define MAX3107_LCR_REG                 (0x0b00) /* LCR */
+#define MAX3107_RXTO_REG                (0x0c00) /* RX timeout */
+#define MAX3107_HDPIXDELAY_REG          (0x0d00) /* Auto transceiver delays */
+#define MAX3107_IRDA_REG                (0x0e00) /* IRDA settings */
+#define MAX3107_FLOWLVL_REG             (0x0f00) /* Flow control levels */
+#define MAX3107_FIFOTRIGLVL_REG         (0x1000) /* FIFO IRQ trigger levels */
+#define MAX3107_TXFIFOLVL_REG           (0x1100) /* TX FIFO level */
+#define MAX3107_RXFIFOLVL_REG           (0x1200) /* RX FIFO level */
+#define MAX3107_FLOWCTRL_REG            (0x1300) /* Flow control */
+#define MAX3107_XON1_REG                (0x1400) /* XON1 character */
+#define MAX3107_XON2_REG                (0x1500) /* XON2 character */
+#define MAX3107_XOFF1_REG               (0x1600) /* XOFF1 character */
+#define MAX3107_XOFF2_REG               (0x1700) /* XOFF2 character */
+#define MAX3107_GPIOCFG_REG             (0x1800) /* GPIO config */
+#define MAX3107_GPIODATA_REG            (0x1900) /* GPIO data */
+#define MAX3107_PLLCFG_REG              (0x1a00) /* PLL config */
+#define MAX3107_BRGCFG_REG              (0x1b00) /* Baud rate generator conf */
+#define MAX3107_BRGDIVLSB_REG           (0x1c00) /* Baud rate divisor LSB */
+#define MAX3107_BRGDIVMSB_REG           (0x1d00) /* Baud rate divisor MSB */
+#define MAX3107_CLKSRC_REG              (0x1e00) /* Clock source */
+#define MAX3107_REVID_REG               (0x1f00) /* Revision identification */
+
+/* IRQ register bits */
+#define MAX3107_IRQ_LSR_BIT     (1 << 0) /* LSR interrupt */
+#define MAX3107_IRQ_SPCHR_BIT   (1 << 1) /* Special char interrupt */
+#define MAX3107_IRQ_STS_BIT     (1 << 2) /* Status interrupt */
+#define MAX3107_IRQ_RXFIFO_BIT  (1 << 3) /* RX FIFO interrupt */
+#define MAX3107_IRQ_TXFIFO_BIT  (1 << 4) /* TX FIFO interrupt */
+#define MAX3107_IRQ_TXEMPTY_BIT (1 << 5) /* TX FIFO empty interrupt */
+#define MAX3107_IRQ_RXEMPTY_BIT (1 << 6) /* RX FIFO empty interrupt */
+#define MAX3107_IRQ_CTS_BIT     (1 << 7) /* CTS interrupt */
+
+/* LSR register bits */
+#define MAX3107_LSR_RXTO_BIT    (1 << 0) /* RX timeout */
+#define MAX3107_LSR_RXOVR_BIT   (1 << 1) /* RX overrun */
+#define MAX3107_LSR_RXPAR_BIT   (1 << 2) /* RX parity error */
+#define MAX3107_LSR_FRERR_BIT   (1 << 3) /* Frame error */
+#define MAX3107_LSR_RXBRK_BIT   (1 << 4) /* RX break */
+#define MAX3107_LSR_RXNOISE_BIT (1 << 5) /* RX noise */
+#define MAX3107_LSR_UNDEF6_BIT  (1 << 6) /* Undefined/not used */
+#define MAX3107_LSR_CTS_BIT     (1 << 7) /* CTS pin state */
+
+/* Special character register bits */
+#define MAX3107_SPCHR_XON1_BIT          (1 << 0) /* XON1 character */
+#define MAX3107_SPCHR_XON2_BIT          (1 << 1) /* XON2 character */
+#define MAX3107_SPCHR_XOFF1_BIT         (1 << 2) /* XOFF1 character */
+#define MAX3107_SPCHR_XOFF2_BIT         (1 << 3) /* XOFF2 character */
+#define MAX3107_SPCHR_BREAK_BIT         (1 << 4) /* RX break */
+#define MAX3107_SPCHR_MULTIDROP_BIT     (1 << 5) /* 9-bit multidrop addr char */
+#define MAX3107_SPCHR_UNDEF6_BIT        (1 << 6) /* Undefined/not used */
+#define MAX3107_SPCHR_UNDEF7_BIT        (1 << 7) /* Undefined/not used */
+
+/* Status register bits */
+#define MAX3107_STS_GPIO0_BIT           (1 << 0) /* GPIO 0 interrupt */
+#define MAX3107_STS_GPIO1_BIT           (1 << 1) /* GPIO 1 interrupt */
+#define MAX3107_STS_GPIO2_BIT           (1 << 2) /* GPIO 2 interrupt */
+#define MAX3107_STS_GPIO3_BIT           (1 << 3) /* GPIO 3 interrupt */
+#define MAX3107_STS_UNDEF4_BIT          (1 << 4) /* Undefined/not used */
+#define MAX3107_STS_CLKREADY_BIT        (1 << 5) /* Clock ready */
+#define MAX3107_STS_SLEEP_BIT           (1 << 6) /* Sleep interrupt */
+#define MAX3107_STS_UNDEF7_BIT          (1 << 7) /* Undefined/not used */
+
+/* MODE1 register bits */
+#define MAX3107_MODE1_RXDIS_BIT         (1 << 0) /* RX disable */
+#define MAX3107_MODE1_TXDIS_BIT         (1 << 1) /* TX disable */
+#define MAX3107_MODE1_TXHIZ_BIT         (1 << 2) /* TX pin three-state */
+#define MAX3107_MODE1_RTSHIZ_BIT        (1 << 3) /* RTS pin three-state */
+#define MAX3107_MODE1_TRNSCVCTRL_BIT    (1 << 4) /* Transceiver ctrl enable */
+#define MAX3107_MODE1_FORCESLEEP_BIT    (1 << 5) /* Force sleep mode */
+#define MAX3107_MODE1_AUTOSLEEP_BIT     (1 << 6) /* Auto sleep enable */
+#define MAX3107_MODE1_IRQSEL_BIT        (1 << 7) /* IRQ pin enable */
+
+/* MODE2 register bits */
+#define MAX3107_MODE2_RST_BIT           (1 << 0) /* Chip reset */
+#define MAX3107_MODE2_FIFORST_BIT       (1 << 1) /* FIFO reset */
+#define MAX3107_MODE2_RXTRIGINV_BIT     (1 << 2) /* RX FIFO INT invert */
+#define MAX3107_MODE2_RXEMPTINV_BIT     (1 << 3) /* RX FIFO empty INT invert */
+#define MAX3107_MODE2_SPCHR_BIT         (1 << 4) /* Special chr detect enable */
+#define MAX3107_MODE2_LOOPBACK_BIT      (1 << 5) /* Internal loopback enable */
+#define MAX3107_MODE2_MULTIDROP_BIT     (1 << 6) /* 9-bit multidrop enable */
+#define MAX3107_MODE2_ECHOSUPR_BIT      (1 << 7) /* ECHO suppression enable */
+
+/* LCR register bits */
+#define MAX3107_LCR_LENGTH0_BIT         (1 << 0) /* Word length bit 0 */
+#define MAX3107_LCR_LENGTH1_BIT         (1 << 1) /* Word length bit 1
+                                                  *
+                                                  * Word length bits table:
+                                                  * 00 -> 5 bit words
+                                                  * 01 -> 6 bit words
+                                                  * 10 -> 7 bit words
+                                                  * 11 -> 8 bit words
+                                                  */
+#define MAX3107_LCR_STOPLEN_BIT         (1 << 2) /* STOP length bit
+                                                  *
+                                                  * STOP length bit table:
+                                                  * 0 -> 1 stop bit
+                                                  * 1 -> 1-1.5 stop bits if
+                                                  *      word length is 5,
+                                                  *      2 stop bits otherwise
+                                                  */
+#define MAX3107_LCR_PARITY_BIT          (1 << 3) /* Parity bit enable */
+#define MAX3107_LCR_EVENPARITY_BIT      (1 << 4) /* Even parity bit enable */
+#define MAX3107_LCR_FORCEPARITY_BIT     (1 << 5) /* 9-bit multidrop parity */
+#define MAX3107_LCR_TXBREAK_BIT         (1 << 6) /* TX break enable */
+#define MAX3107_LCR_RTS_BIT             (1 << 7) /* RTS pin control */
+#define MAX3107_LCR_WORD_LEN_5          (0x0000)
+#define MAX3107_LCR_WORD_LEN_6          (0x0001)
+#define MAX3107_LCR_WORD_LEN_7          (0x0002)
+#define MAX3107_LCR_WORD_LEN_8          (0x0003)
+
+
+/* IRDA register bits */
+#define MAX3107_IRDA_IRDAEN_BIT         (1 << 0) /* IRDA mode enable */
+#define MAX3107_IRDA_SIR_BIT            (1 << 1) /* SIR mode enable */
+#define MAX3107_IRDA_SHORTIR_BIT        (1 << 2) /* Short SIR mode enable */
+#define MAX3107_IRDA_MIR_BIT            (1 << 3) /* MIR mode enable */
+#define MAX3107_IRDA_RXINV_BIT          (1 << 4) /* RX logic inversion enable */
+#define MAX3107_IRDA_TXINV_BIT          (1 << 5) /* TX logic inversion enable */
+#define MAX3107_IRDA_UNDEF6_BIT         (1 << 6) /* Undefined/not used */
+#define MAX3107_IRDA_UNDEF7_BIT         (1 << 7) /* Undefined/not used */
+
+/* Flow control trigger level register masks */
+#define MAX3107_FLOWLVL_HALT_MASK       (0x000f) /* Flow control halt level */
+#define MAX3107_FLOWLVL_RES_MASK        (0x00f0) /* Flow control resume level */
+#define MAX3107_FLOWLVL_HALT(words)     ((words/8) & 0x000f)
+#define MAX3107_FLOWLVL_RES(words)      (((words/8) & 0x000f) << 4)
+
+/* FIFO interrupt trigger level register masks */
+#define MAX3107_FIFOTRIGLVL_TX_MASK     (0x000f) /* TX FIFO trigger level */
+#define MAX3107_FIFOTRIGLVL_RX_MASK     (0x00f0) /* RX FIFO trigger level */
+#define MAX3107_FIFOTRIGLVL_TX(words)   ((words/8) & 0x000f)
+#define MAX3107_FIFOTRIGLVL_RX(words)   (((words/8) & 0x000f) << 4)
+
+/* Flow control register bits */
+#define MAX3107_FLOWCTRL_AUTORTS_BIT    (1 << 0) /* Auto RTS flow ctrl enable */
+#define MAX3107_FLOWCTRL_AUTOCTS_BIT    (1 << 1) /* Auto CTS flow ctrl enable */
+#define MAX3107_FLOWCTRL_GPIADDR_BIT    (1 << 2) /* Enables that GPIO inputs
+                                                  * are used in conjunction with
+                                                  * XOFF2 for definition of
+                                                  * special character */
+#define MAX3107_FLOWCTRL_SWFLOWEN_BIT   (1 << 3) /* Auto SW flow ctrl enable */
+#define MAX3107_FLOWCTRL_SWFLOW0_BIT    (1 << 4) /* SWFLOW bit 0 */
+#define MAX3107_FLOWCTRL_SWFLOW1_BIT    (1 << 5) /* SWFLOW bit 1
+                                                  *
+                                                  * SWFLOW bits 1 & 0 table:
+                                                  * 00 -> no transmitter flow
+                                                  *       control
+                                                  * 01 -> receiver compares
+                                                  *       XON2 and XOFF2
+                                                  *       and controls
+                                                  *       transmitter
+                                                  * 10 -> receiver compares
+                                                  *       XON1 and XOFF1
+                                                  *       and controls
+                                                  *       transmitter
+                                                  * 11 -> receiver compares
+                                                  *       XON1, XON2, XOFF1 and
+                                                  *       XOFF2 and controls
+                                                  *       transmitter
+                                                  */
+#define MAX3107_FLOWCTRL_SWFLOW2_BIT    (1 << 6) /* SWFLOW bit 2 */
+#define MAX3107_FLOWCTRL_SWFLOW3_BIT    (1 << 7) /* SWFLOW bit 3
+                                                  *
+                                                  * SWFLOW bits 3 & 2 table:
+                                                  * 00 -> no received flow
+                                                  *       control
+                                                  * 01 -> transmitter generates
+                                                  *       XON2 and XOFF2
+                                                  * 10 -> transmitter generates
+                                                  *       XON1 and XOFF1
+                                                  * 11 -> transmitter generates
+                                                  *       XON1, XON2, XOFF1 and
+                                                  *       XOFF2
+                                                  */
+
+/* GPIO configuration register bits */
+#define MAX3107_GPIOCFG_GP0OUT_BIT      (1 << 0) /* GPIO 0 output enable */
+#define MAX3107_GPIOCFG_GP1OUT_BIT      (1 << 1) /* GPIO 1 output enable */
+#define MAX3107_GPIOCFG_GP2OUT_BIT      (1 << 2) /* GPIO 2 output enable */
+#define MAX3107_GPIOCFG_GP3OUT_BIT      (1 << 3) /* GPIO 3 output enable */
+#define MAX3107_GPIOCFG_GP0OD_BIT       (1 << 4) /* GPIO 0 open-drain enable */
+#define MAX3107_GPIOCFG_GP1OD_BIT       (1 << 5) /* GPIO 1 open-drain enable */
+#define MAX3107_GPIOCFG_GP2OD_BIT       (1 << 6) /* GPIO 2 open-drain enable */
+#define MAX3107_GPIOCFG_GP3OD_BIT       (1 << 7) /* GPIO 3 open-drain enable */
+
+/* GPIO DATA register bits */
+#define MAX3107_GPIODATA_GP0OUT_BIT     (1 << 0) /* GPIO 0 output value */
+#define MAX3107_GPIODATA_GP1OUT_BIT     (1 << 1) /* GPIO 1 output value */
+#define MAX3107_GPIODATA_GP2OUT_BIT     (1 << 2) /* GPIO 2 output value */
+#define MAX3107_GPIODATA_GP3OUT_BIT     (1 << 3) /* GPIO 3 output value */
+#define MAX3107_GPIODATA_GP0IN_BIT      (1 << 4) /* GPIO 0 input value */
+#define MAX3107_GPIODATA_GP1IN_BIT      (1 << 5) /* GPIO 1 input value */
+#define MAX3107_GPIODATA_GP2IN_BIT      (1 << 6) /* GPIO 2 input value */
+#define MAX3107_GPIODATA_GP3IN_BIT      (1 << 7) /* GPIO 3 input value */
+
+/* PLL configuration register masks */
+#define MAX3107_PLLCFG_PREDIV_MASK      (0x003f) /* PLL predivision value */
+#define MAX3107_PLLCFG_PLLFACTOR_MASK   (0x00c0) /* PLL multiplication factor */
+
+/* Baud rate generator configuration register masks and bits */
+#define MAX3107_BRGCFG_FRACT_MASK       (0x000f) /* Fractional portion of
+                                                  * Baud rate generator divisor
+                                                  */
+#define MAX3107_BRGCFG_2XMODE_BIT       (1 << 4) /* Double baud rate */
+#define MAX3107_BRGCFG_4XMODE_BIT       (1 << 5) /* Quadruple baud rate */
+#define MAX3107_BRGCFG_UNDEF6_BIT       (1 << 6) /* Undefined/not used */
+#define MAX3107_BRGCFG_UNDEF7_BIT       (1 << 7) /* Undefined/not used */
+
+/* Clock source register bits */
+#define MAX3107_CLKSRC_INTOSC_BIT       (1 << 0) /* Internal osc enable */
+#define MAX3107_CLKSRC_CRYST_BIT        (1 << 1) /* Crystal osc enable */
+#define MAX3107_CLKSRC_PLL_BIT          (1 << 2) /* PLL enable */
+#define MAX3107_CLKSRC_PLLBYP_BIT       (1 << 3) /* PLL bypass */
+#define MAX3107_CLKSRC_EXTCLK_BIT       (1 << 4) /* External clock enable */
+#define MAX3107_CLKSRC_UNDEF5_BIT       (1 << 5) /* Undefined/not used */
+#define MAX3107_CLKSRC_UNDEF6_BIT       (1 << 6) /* Undefined/not used */
+#define MAX3107_CLKSRC_CLK2RTS_BIT      (1 << 7) /* Baud clk to RTS pin */
+
+
+/* HW definitions */
+#define MAX3107_RX_FIFO_SIZE    128
+#define MAX3107_TX_FIFO_SIZE    128
+#define MAX3107_REVID1          0x00a0
+#define MAX3107_REVID2          0x00a1
+
+
+/* Baud rate generator configuration values for external clock 13MHz */
+#define MAX3107_BRG13_B300      (0x0A9400 | 0x05)
+#define MAX3107_BRG13_B600      (0x054A00 | 0x03)
+#define MAX3107_BRG13_B1200     (0x02A500 | 0x01)
+#define MAX3107_BRG13_B2400     (0x015200 | 0x09)
+#define MAX3107_BRG13_B4800     (0x00A900 | 0x04)
+#define MAX3107_BRG13_B9600     (0x005400 | 0x0A)
+#define MAX3107_BRG13_B19200    (0x002A00 | 0x05)
+#define MAX3107_BRG13_B38400    (0x001500 | 0x03)
+#define MAX3107_BRG13_B57600    (0x000E00 | 0x02)
+#define MAX3107_BRG13_B115200   (0x000700 | 0x01)
+#define MAX3107_BRG13_B230400   (0x000300 | 0x08)
+#define MAX3107_BRG13_B460800   (0x000100 | 0x0c)
+#define MAX3107_BRG13_B921600   (0x000100 | 0x1c)
+
+/* Baud rate generator configuration values for external clock 26MHz */
+#define MAX3107_BRG26_B300      (0x152800 | 0x0A)
+#define MAX3107_BRG26_B600      (0x0A9400 | 0x05)
+#define MAX3107_BRG26_B1200     (0x054A00 | 0x03)
+#define MAX3107_BRG26_B2400     (0x02A500 | 0x01)
+#define MAX3107_BRG26_B4800     (0x015200 | 0x09)
+#define MAX3107_BRG26_B9600     (0x00A900 | 0x04)
+#define MAX3107_BRG26_B19200    (0x005400 | 0x0A)
+#define MAX3107_BRG26_B38400    (0x002A00 | 0x05)
+#define MAX3107_BRG26_B57600    (0x001C00 | 0x03)
+#define MAX3107_BRG26_B115200   (0x000E00 | 0x02)
+#define MAX3107_BRG26_B230400   (0x000700 | 0x01)
+#define MAX3107_BRG26_B460800   (0x000300 | 0x08)
+#define MAX3107_BRG26_B921600   (0x000100 | 0x0C)
+
+/* Baud rate generator configuration values for internal clock */
+#define MAX3107_BRG13_IB300     (0x008000 | 0x00)
+#define MAX3107_BRG13_IB600     (0x004000 | 0x00)
+#define MAX3107_BRG13_IB1200    (0x002000 | 0x00)
+#define MAX3107_BRG13_IB2400    (0x001000 | 0x00)
+#define MAX3107_BRG13_IB4800    (0x000800 | 0x00)
+#define MAX3107_BRG13_IB9600    (0x000400 | 0x00)
+#define MAX3107_BRG13_IB19200   (0x000200 | 0x00)
+#define MAX3107_BRG13_IB38400   (0x000100 | 0x00)
+#define MAX3107_BRG13_IB57600   (0x000000 | 0x0B)
+#define MAX3107_BRG13_IB115200  (0x000000 | 0x05)
+#define MAX3107_BRG13_IB230400  (0x000000 | 0x03)
+#define MAX3107_BRG13_IB460800  (0x000000 | 0x00)
+#define MAX3107_BRG13_IB921600  (0x000000 | 0x00)
+
+
+struct baud_table {
+        int baud;
+        u32 new_brg;
+};
+
+struct max3107_port {
+        /* UART port structure */
+        struct uart_port port;
+
+        /* SPI device structure */
+        struct spi_device *spi;
+
+#if defined(CONFIG_GPIOLIB)
+        /* GPIO chip structure */
+        struct gpio_chip chip;
+#endif
+
+        /* Workqueue that does all the magic */
+        struct workqueue_struct *workqueue;
+        struct work_struct work;
+
+        /* Lock for shared data */
+        spinlock_t data_lock;
+
+        /* Device configuration */
+        int ext_clk;            /* 1 if external clock used */
+        int loopback;           /* Current loopback mode state */
+        int baud;                       /* Current baud rate */
+
+        /* State flags */
+        int suspended;          /* Indicates suspend mode */
+        int tx_fifo_empty;      /* Flag for TX FIFO state */
+        int rx_enabled;         /* Flag for receiver state */
+        int tx_enabled;         /* Flag for transmitter state */
+
+        u16 irqen_reg;          /* Current IRQ enable register value */
+        /* Shared data */
+        u16 mode1_reg;          /* Current mode1 register value*/
+        int mode1_commit;       /* Flag for setting new mode1 register value */
+        u16 lcr_reg;            /* Current LCR register value */
+        int lcr_commit;         /* Flag for setting new LCR register value */
+        u32 brg_cfg;            /* Current Baud rate generator config  */
+        int brg_commit;         /* Flag for setting new baud rate generator
+                                 * config
+                                 */
+        struct baud_table *baud_tbl;
+        int handle_irq;         /* Indicates that IRQ should be handled */
+
+        /* Rx buffer and str*/
+        u16 *rxbuf;
+        u8  *rxstr;
+        /* Tx buffer*/
+        u16 *txbuf;
+
+        struct max3107_plat *pdata;     /* Platform data */
+};
+
+/* Platform data structure */
+struct max3107_plat {
+        /* Loopback mode enable */
+        int loopback;
+        /* External clock enable */
+        int ext_clk;
+        /* Called during the register initialisation */
+        void (*init)(struct max3107_port *s);
+        /* Called when the port is found and configured */
+        int (*configure)(struct max3107_port *s);
+        /* HW suspend function */
+        void (*hw_suspend) (struct max3107_port *s, int suspend);
+        /* Polling mode enable */
+        int polled_mode;
+        /* Polling period if polling mode enabled */
+        int poll_time;
+};
+
+extern int max3107_rw(struct max3107_port *s, u8 *tx, u8 *rx, int len);
+extern void max3107_hw_susp(struct max3107_port *s, int suspend);
+extern int max3107_probe(struct spi_device *spi, struct max3107_plat *pdata);
+extern int max3107_remove(struct spi_device *spi);
+extern int max3107_suspend(struct spi_device *spi, pm_message_t state);
+extern int max3107_resume(struct spi_device *spi);
+
+#endif /* _LINUX_SERIAL_MAX3107_H */
diff --git a/drivers/tty/serial/s3c2410.c b/drivers/tty/serial/s3c2410.c
new file mode 100644
index 00000000000..b1d7e7c1849
--- /dev/null
+++ b/drivers/tty/serial/s3c2410.c
@@ -0,0 +1,115 @@
+/*
+ * Driver for Samsung S3C2410 SoC onboard UARTs.
+ *
+ * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+
+#include <asm/irq.h>
+#include <mach/hardware.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-gpio.h>
+
+#include "samsung.h"
+
+static int s3c2410_serial_setsource(struct uart_port *port,
+                                    struct s3c24xx_uart_clksrc *clk)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        if (strcmp(clk->name, "uclk") == 0)
+                ucon |= S3C2410_UCON_UCLK;
+        else
+                ucon &= ~S3C2410_UCON_UCLK;
+
+        wr_regl(port, S3C2410_UCON, ucon);
+        return 0;
+}
+
+static int s3c2410_serial_getsource(struct uart_port *port,
+                                    struct s3c24xx_uart_clksrc *clk)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        clk->divisor = 1;
+        clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
+
+        return 0;
+}
+
+static int s3c2410_serial_resetport(struct uart_port *port,
+                                    struct s3c2410_uartcfg *cfg)
+{
+        dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",
+            port, port->mapbase, cfg);
+
+        wr_regl(port, S3C2410_UCON,  cfg->ucon);
+        wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+        /* reset both fifos */
+
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+        return 0;
+}
+
+static struct s3c24xx_uart_info s3c2410_uart_inf = {
+        .name           = "Samsung S3C2410 UART",
+        .type           = PORT_S3C2410,
+        .fifosize       = 16,
+        .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
+        .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
+        .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
+        .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
+        .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
+        .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
+        .get_clksrc     = s3c2410_serial_getsource,
+        .set_clksrc     = s3c2410_serial_setsource,
+        .reset_port     = s3c2410_serial_resetport,
+};
+
+static int s3c2410_serial_probe(struct platform_device *dev)
+{
+        return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
+}
+
+static struct platform_driver s3c2410_serial_driver = {
+        .probe          = s3c2410_serial_probe,
+        .remove         = __devexit_p(s3c24xx_serial_remove),
+        .driver         = {
+                .name   = "s3c2410-uart",
+                .owner  = THIS_MODULE,
+        },
+};
+
+static int __init s3c2410_serial_init(void)
+{
+        return s3c24xx_serial_init(&s3c2410_serial_driver, &s3c2410_uart_inf);
+}
+
+static void __exit s3c2410_serial_exit(void)
+{
+        platform_driver_unregister(&s3c2410_serial_driver);
+}
+
+module_init(s3c2410_serial_init);
+module_exit(s3c2410_serial_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_DESCRIPTION("Samsung S3C2410 SoC Serial port driver");
+MODULE_ALIAS("platform:s3c2410-uart");
diff --git a/drivers/tty/serial/s3c2412.c b/drivers/tty/serial/s3c2412.c
new file mode 100644
index 00000000000..2234bf9ced4
--- /dev/null
+++ b/drivers/tty/serial/s3c2412.c
@@ -0,0 +1,149 @@
+/*
+ * Driver for Samsung S3C2412 and S3C2413 SoC onboard UARTs.
+ *
+ * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+
+#include <asm/irq.h>
+#include <mach/hardware.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-gpio.h>
+
+#include "samsung.h"
+
+static int s3c2412_serial_setsource(struct uart_port *port,
+                                     struct s3c24xx_uart_clksrc *clk)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        ucon &= ~S3C2412_UCON_CLKMASK;
+
+        if (strcmp(clk->name, "uclk") == 0)
+                ucon |= S3C2440_UCON_UCLK;
+        else if (strcmp(clk->name, "pclk") == 0)
+                ucon |= S3C2440_UCON_PCLK;
+        else if (strcmp(clk->name, "usysclk") == 0)
+                ucon |= S3C2412_UCON_USYSCLK;
+        else {
+                printk(KERN_ERR "unknown clock source %s\n", clk->name);
+                return -EINVAL;
+        }
+
+        wr_regl(port, S3C2410_UCON, ucon);
+        return 0;
+}
+
+
+static int s3c2412_serial_getsource(struct uart_port *port,
+                                    struct s3c24xx_uart_clksrc *clk)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        switch (ucon & S3C2412_UCON_CLKMASK) {
+        case S3C2412_UCON_UCLK:
+                clk->divisor = 1;
+                clk->name = "uclk";
+                break;
+
+        case S3C2412_UCON_PCLK:
+        case S3C2412_UCON_PCLK2:
+                clk->divisor = 1;
+                clk->name = "pclk";
+                break;
+
+        case S3C2412_UCON_USYSCLK:
+                clk->divisor = 1;
+                clk->name = "usysclk";
+                break;
+        }
+
+        return 0;
+}
+
+static int s3c2412_serial_resetport(struct uart_port *port,
+                                    struct s3c2410_uartcfg *cfg)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        dbg("%s: port=%p (%08lx), cfg=%p\n",
+            __func__, port, port->mapbase, cfg);
+
+        /* ensure we don't change the clock settings... */
+
+        ucon &= S3C2412_UCON_CLKMASK;
+
+        wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
+        wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+        /* reset both fifos */
+
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+        return 0;
+}
+
+static struct s3c24xx_uart_info s3c2412_uart_inf = {
+        .name           = "Samsung S3C2412 UART",
+        .type           = PORT_S3C2412,
+        .fifosize       = 64,
+        .has_divslot    = 1,
+        .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
+        .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
+        .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
+        .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
+        .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
+        .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
+        .get_clksrc     = s3c2412_serial_getsource,
+        .set_clksrc     = s3c2412_serial_setsource,
+        .reset_port     = s3c2412_serial_resetport,
+};
+
+/* device management */
+
+static int s3c2412_serial_probe(struct platform_device *dev)
+{
+        dbg("s3c2440_serial_probe: dev=%p\n", dev);
+        return s3c24xx_serial_probe(dev, &s3c2412_uart_inf);
+}
+
+static struct platform_driver s3c2412_serial_driver = {
+        .probe          = s3c2412_serial_probe,
+        .remove         = __devexit_p(s3c24xx_serial_remove),
+        .driver         = {
+                .name   = "s3c2412-uart",
+                .owner  = THIS_MODULE,
+        },
+};
+
+static inline int s3c2412_serial_init(void)
+{
+        return s3c24xx_serial_init(&s3c2412_serial_driver, &s3c2412_uart_inf);
+}
+
+static inline void s3c2412_serial_exit(void)
+{
+        platform_driver_unregister(&s3c2412_serial_driver);
+}
+
+module_init(s3c2412_serial_init);
+module_exit(s3c2412_serial_exit);
+
+MODULE_DESCRIPTION("Samsung S3C2412,S3C2413 SoC Serial port driver");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:s3c2412-uart");
diff --git a/drivers/tty/serial/s3c2440.c b/drivers/tty/serial/s3c2440.c
new file mode 100644
index 00000000000..1d0c324b813
--- /dev/null
+++ b/drivers/tty/serial/s3c2440.c
@@ -0,0 +1,178 @@
+/*
+ * Driver for Samsung S3C2440 and S3C2442 SoC onboard UARTs.
+ *
+ * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+
+#include <asm/irq.h>
+#include <mach/hardware.h>
+
+#include <plat/regs-serial.h>
+#include <mach/regs-gpio.h>
+
+#include "samsung.h"
+
+
+static int s3c2440_serial_setsource(struct uart_port *port,
+                                     struct s3c24xx_uart_clksrc *clk)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        /* todo - proper fclk<>nonfclk switch. */
+
+        ucon &= ~S3C2440_UCON_CLKMASK;
+
+        if (strcmp(clk->name, "uclk") == 0)
+                ucon |= S3C2440_UCON_UCLK;
+        else if (strcmp(clk->name, "pclk") == 0)
+                ucon |= S3C2440_UCON_PCLK;
+        else if (strcmp(clk->name, "fclk") == 0)
+                ucon |= S3C2440_UCON_FCLK;
+        else {
+                printk(KERN_ERR "unknown clock source %s\n", clk->name);
+                return -EINVAL;
+        }
+
+        wr_regl(port, S3C2410_UCON, ucon);
+        return 0;
+}
+
+
+static int s3c2440_serial_getsource(struct uart_port *port,
+                                    struct s3c24xx_uart_clksrc *clk)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+        unsigned long ucon0, ucon1, ucon2;
+
+        switch (ucon & S3C2440_UCON_CLKMASK) {
+        case S3C2440_UCON_UCLK:
+                clk->divisor = 1;
+                clk->name = "uclk";
+                break;
+
+        case S3C2440_UCON_PCLK:
+        case S3C2440_UCON_PCLK2:
+                clk->divisor = 1;
+                clk->name = "pclk";
+                break;
+
+        case S3C2440_UCON_FCLK:
+                /* the fun of calculating the uart divisors on
+                 * the s3c2440 */
+
+                ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
+                ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
+                ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
+
+                printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
+
+                ucon0 &= S3C2440_UCON0_DIVMASK;
+                ucon1 &= S3C2440_UCON1_DIVMASK;
+                ucon2 &= S3C2440_UCON2_DIVMASK;
+
+                if (ucon0 != 0) {
+                        clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
+                        clk->divisor += 6;
+                } else if (ucon1 != 0) {
+                        clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
+                        clk->divisor += 21;
+                } else if (ucon2 != 0) {
+                        clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
+                        clk->divisor += 36;
+                } else {
+                        /* manual calims 44, seems to be 9 */
+                        clk->divisor = 9;
+                }
+
+                clk->name = "fclk";
+                break;
+        }
+
+        return 0;
+}
+
+static int s3c2440_serial_resetport(struct uart_port *port,
+                                    struct s3c2410_uartcfg *cfg)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
+            port, port->mapbase, cfg);
+
+        /* ensure we don't change the clock settings... */
+
+        ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
+
+        wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
+        wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+        /* reset both fifos */
+
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+        return 0;
+}
+
+static struct s3c24xx_uart_info s3c2440_uart_inf = {
+        .name           = "Samsung S3C2440 UART",
+        .type           = PORT_S3C2440,
+        .fifosize       = 64,
+        .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
+        .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
+        .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
+        .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
+        .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
+        .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
+        .get_clksrc     = s3c2440_serial_getsource,
+        .set_clksrc     = s3c2440_serial_setsource,
+        .reset_port     = s3c2440_serial_resetport,
+};
+
+/* device management */
+
+static int s3c2440_serial_probe(struct platform_device *dev)
+{
+        dbg("s3c2440_serial_probe: dev=%p\n", dev);
+        return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
+}
+
+static struct platform_driver s3c2440_serial_driver = {
+        .probe          = s3c2440_serial_probe,
+        .remove         = __devexit_p(s3c24xx_serial_remove),
+        .driver         = {
+                .name   = "s3c2440-uart",
+                .owner  = THIS_MODULE,
+        },
+};
+
+static int __init s3c2440_serial_init(void)
+{
+        return s3c24xx_serial_init(&s3c2440_serial_driver, &s3c2440_uart_inf);
+}
+
+static void __exit s3c2440_serial_exit(void)
+{
+        platform_driver_unregister(&s3c2440_serial_driver);
+}
+
+module_init(s3c2440_serial_init);
+module_exit(s3c2440_serial_exit);
+
+MODULE_DESCRIPTION("Samsung S3C2440,S3C2442 SoC Serial port driver");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:s3c2440-uart");
diff --git a/drivers/tty/serial/s3c6400.c b/drivers/tty/serial/s3c6400.c
new file mode 100644
index 00000000000..e2f6913d84d
--- /dev/null
+++ b/drivers/tty/serial/s3c6400.c
@@ -0,0 +1,149 @@
+/*
+ * Driver for Samsung S3C6400 and S3C6410 SoC onboard UARTs.
+ *
+ * Copyright 2008 Openmoko,  Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+
+#include <asm/irq.h>
+#include <mach/hardware.h>
+
+#include <plat/regs-serial.h>
+
+#include "samsung.h"
+
+static int s3c6400_serial_setsource(struct uart_port *port,
+                                    struct s3c24xx_uart_clksrc *clk)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        if (strcmp(clk->name, "uclk0") == 0) {
+                ucon &= ~S3C6400_UCON_CLKMASK;
+                ucon |= S3C6400_UCON_UCLK0;
+        } else if (strcmp(clk->name, "uclk1") == 0)
+                ucon |= S3C6400_UCON_UCLK1;
+        else if (strcmp(clk->name, "pclk") == 0) {
+                /* See notes about transitioning from UCLK to PCLK */
+                ucon &= ~S3C6400_UCON_UCLK0;
+        } else {
+                printk(KERN_ERR "unknown clock source %s\n", clk->name);
+                return -EINVAL;
+        }
+
+        wr_regl(port, S3C2410_UCON, ucon);
+        return 0;
+}
+
+
+static int s3c6400_serial_getsource(struct uart_port *port,
+                                    struct s3c24xx_uart_clksrc *clk)
+{
+        u32 ucon = rd_regl(port, S3C2410_UCON);
+
+        clk->divisor = 1;
+
+        switch (ucon & S3C6400_UCON_CLKMASK) {
+        case S3C6400_UCON_UCLK0:
+                clk->name = "uclk0";
+                break;
+
+        case S3C6400_UCON_UCLK1:
+                clk->name = "uclk1";
+                break;
+
+        case S3C6400_UCON_PCLK:
+        case S3C6400_UCON_PCLK2:
+                clk->name = "pclk";
+                break;
+        }
+
+        return 0;
+}
+
+static int s3c6400_serial_resetport(struct uart_port *port,
+                                    struct s3c2410_uartcfg *cfg)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        dbg("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n",
+            port, port->mapbase, cfg);
+
+        /* ensure we don't change the clock settings... */
+
+        ucon &= S3C6400_UCON_CLKMASK;
+
+        wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
+        wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+        /* reset both fifos */
+
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+        return 0;
+}
+
+static struct s3c24xx_uart_info s3c6400_uart_inf = {
+        .name           = "Samsung S3C6400 UART",
+        .type           = PORT_S3C6400,
+        .fifosize       = 64,
+        .has_divslot    = 1,
+        .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
+        .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
+        .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
+        .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
+        .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
+        .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
+        .get_clksrc     = s3c6400_serial_getsource,
+        .set_clksrc     = s3c6400_serial_setsource,
+        .reset_port     = s3c6400_serial_resetport,
+};
+
+/* device management */
+
+static int s3c6400_serial_probe(struct platform_device *dev)
+{
+        dbg("s3c6400_serial_probe: dev=%p\n", dev);
+        return s3c24xx_serial_probe(dev, &s3c6400_uart_inf);
+}
+
+static struct platform_driver s3c6400_serial_driver = {
+        .probe          = s3c6400_serial_probe,
+        .remove         = __devexit_p(s3c24xx_serial_remove),
+        .driver         = {
+                .name   = "s3c6400-uart",
+                .owner  = THIS_MODULE,
+        },
+};
+
+static int __init s3c6400_serial_init(void)
+{
+        return s3c24xx_serial_init(&s3c6400_serial_driver, &s3c6400_uart_inf);
+}
+
+static void __exit s3c6400_serial_exit(void)
+{
+        platform_driver_unregister(&s3c6400_serial_driver);
+}
+
+module_init(s3c6400_serial_init);
+module_exit(s3c6400_serial_exit);
+
+MODULE_DESCRIPTION("Samsung S3C6400,S3C6410 SoC Serial port driver");
+MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:s3c6400-uart");
diff --git a/drivers/tty/serial/s5pv210.c b/drivers/tty/serial/s5pv210.c
new file mode 100644
index 00000000000..8b0b888a1b7
--- /dev/null
+++ b/drivers/tty/serial/s5pv210.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
+ * Based on drivers/serial/s3c6400.c
+ *
+ * Driver for Samsung S5PV210 SoC UARTs.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/serial.h>
+#include <linux/delay.h>
+
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <plat/regs-serial.h>
+#include "samsung.h"
+
+static int s5pv210_serial_setsource(struct uart_port *port,
+                                        struct s3c24xx_uart_clksrc *clk)
+{
+        struct s3c2410_uartcfg *cfg = port->dev->platform_data;
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        if (cfg->flags & NO_NEED_CHECK_CLKSRC)
+                return 0;
+
+        if (strcmp(clk->name, "pclk") == 0)
+                ucon &= ~S5PV210_UCON_CLKMASK;
+        else if (strcmp(clk->name, "uclk1") == 0)
+                ucon |= S5PV210_UCON_CLKMASK;
+        else {
+                printk(KERN_ERR "unknown clock source %s\n", clk->name);
+                return -EINVAL;
+        }
+
+        wr_regl(port, S3C2410_UCON, ucon);
+        return 0;
+}
+
+
+static int s5pv210_serial_getsource(struct uart_port *port,
+                                        struct s3c24xx_uart_clksrc *clk)
+{
+        struct s3c2410_uartcfg *cfg = port->dev->platform_data;
+        u32 ucon = rd_regl(port, S3C2410_UCON);
+
+        clk->divisor = 1;
+
+        if (cfg->flags & NO_NEED_CHECK_CLKSRC)
+                return 0;
+
+        switch (ucon & S5PV210_UCON_CLKMASK) {
+        case S5PV210_UCON_PCLK:
+                clk->name = "pclk";
+                break;
+        case S5PV210_UCON_UCLK:
+                clk->name = "uclk1";
+                break;
+        }
+
+        return 0;
+}
+
+static int s5pv210_serial_resetport(struct uart_port *port,
+                                        struct s3c2410_uartcfg *cfg)
+{
+        unsigned long ucon = rd_regl(port, S3C2410_UCON);
+
+        ucon &= S5PV210_UCON_CLKMASK;
+        wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
+        wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+        /* reset both fifos */
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+        wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+        /* It is need to delay When reset FIFO register */
+        udelay(1);
+
+        return 0;
+}
+
+#define S5PV210_UART_DEFAULT_INFO(fifo_size)                    \
+                .name           = "Samsung S5PV210 UART0",      \
+                .type           = PORT_S3C6400,                 \
+                .fifosize       = fifo_size,                    \
+                .has_divslot    = 1,                            \
+                .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
+                .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
+                .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
+                .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
+                .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
+                .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
+                .get_clksrc     = s5pv210_serial_getsource,     \
+                .set_clksrc     = s5pv210_serial_setsource,     \
+                .reset_port     = s5pv210_serial_resetport
+
+static struct s3c24xx_uart_info s5p_port_fifo256 = {
+        S5PV210_UART_DEFAULT_INFO(256),
+};
+
+static struct s3c24xx_uart_info s5p_port_fifo64 = {
+        S5PV210_UART_DEFAULT_INFO(64),
+};
+
+static struct s3c24xx_uart_info s5p_port_fifo16 = {
+        S5PV210_UART_DEFAULT_INFO(16),
+};
+
+static struct s3c24xx_uart_info *s5p_uart_inf[] = {
+        [0] = &s5p_port_fifo256,
+        [1] = &s5p_port_fifo64,
+        [2] = &s5p_port_fifo16,
+        [3] = &s5p_port_fifo16,
+};
+
+/* device management */
+static int s5p_serial_probe(struct platform_device *pdev)
+{
+        return s3c24xx_serial_probe(pdev, s5p_uart_inf[pdev->id]);
+}
+
+static struct platform_driver s5p_serial_driver = {
+        .probe          = s5p_serial_probe,
+        .remove         = __devexit_p(s3c24xx_serial_remove),
+        .driver         = {
+                .name   = "s5pv210-uart",
+                .owner  = THIS_MODULE,
+        },
+};
+
+static int __init s5p_serial_init(void)
+{
+        return s3c24xx_serial_init(&s5p_serial_driver, *s5p_uart_inf);
+}
+
+static void __exit s5p_serial_exit(void)
+{
+        platform_driver_unregister(&s5p_serial_driver);
+}
+
+module_init(s5p_serial_init);
+module_exit(s5p_serial_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:s5pv210-uart");
+MODULE_DESCRIPTION("Samsung S5PV210 UART Driver support");
+MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
diff --git a/drivers/tty/serial/serial_cs.c b/drivers/tty/serial/serial_cs.c
new file mode 100644
index 00000000000..eef736ff810
--- /dev/null
+++ b/drivers/tty/serial/serial_cs.c
@@ -0,0 +1,870 @@
+/*======================================================================
+
+    A driver for PCMCIA serial devices
+
+    serial_cs.c 1.134 2002/05/04 05:48:53
+
+    The contents of this file are subject to the Mozilla Public
+    License Version 1.1 (the "License"); you may not use this file
+    except in compliance with the License. You may obtain a copy of
+    the License at http://www.mozilla.org/MPL/
+
+    Software distributed under the License is distributed on an "AS
+    IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
+    implied. See the License for the specific language governing
+    rights and limitations under the License.
+
+    The initial developer of the original code is David A. Hinds
+    <dahinds@users.sourceforge.net>.  Portions created by David A. Hinds
+    are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
+
+    Alternatively, the contents of this file may be used under the
+    terms of the GNU General Public License version 2 (the "GPL"), in which
+    case the provisions of the GPL are applicable instead of the
+    above.  If you wish to allow the use of your version of this file
+    only under the terms of the GPL and not to allow others to use
+    your version of this file under the MPL, indicate your decision
+    by deleting the provisions above and replace them with the notice
+    and other provisions required by the GPL.  If you do not delete
+    the provisions above, a recipient may use your version of this
+    file under either the MPL or the GPL.
+    
+======================================================================*/
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/ptrace.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/timer.h>
+#include <linux/serial_core.h>
+#include <linux/delay.h>
+#include <linux/major.h>
+#include <asm/io.h>
+#include <asm/system.h>
+
+#include <pcmcia/cistpl.h>
+#include <pcmcia/ciscode.h>
+#include <pcmcia/ds.h>
+#include <pcmcia/cisreg.h>
+
+#include "8250.h"
+
+
+/*====================================================================*/
+
+/* Parameters that can be set with 'insmod' */
+
+/* Enable the speaker? */
+static int do_sound = 1;
+/* Skip strict UART tests? */
+static int buggy_uart;
+
+module_param(do_sound, int, 0444);
+module_param(buggy_uart, int, 0444);
+
+/*====================================================================*/
+
+/* Table of multi-port card ID's */
+
+struct serial_quirk {
+        unsigned int manfid;
+        unsigned int prodid;
+        int multi;              /* 1 = multifunction, > 1 = # ports */
+        void (*config)(struct pcmcia_device *);
+        void (*setup)(struct pcmcia_device *, struct uart_port *);
+        void (*wakeup)(struct pcmcia_device *);
+        int (*post)(struct pcmcia_device *);
+};
+
+struct serial_info {
+        struct pcmcia_device    *p_dev;
+        int                     ndev;
+        int                     multi;
+        int                     slave;
+        int                     manfid;
+        int                     prodid;
+        int                     c950ctrl;
+        int                     line[4];
+        const struct serial_quirk *quirk;
+};
+
+struct serial_cfg_mem {
+        tuple_t tuple;
+        cisparse_t parse;
+        u_char buf[256];
+};
+
+/*
+ * vers_1 5.0, "Brain Boxes", "2-Port RS232 card", "r6"
+ * manfid 0x0160, 0x0104
+ * This card appears to have a 14.7456MHz clock.
+ */
+/* Generic Modem: MD55x (GPRS/EDGE) have
+ * Elan VPU16551 UART with 14.7456MHz oscillator
+ * manfid 0x015D, 0x4C45
+ */
+static void quirk_setup_brainboxes_0104(struct pcmcia_device *link, struct uart_port *port)
+{
+        port->uartclk = 14745600;
+}
+
+static int quirk_post_ibm(struct pcmcia_device *link)
+{
+        u8 val;
+        int ret;
+
+        ret = pcmcia_read_config_byte(link, 0x800, &val);
+        if (ret)
+                goto failed;
+
+        ret = pcmcia_write_config_byte(link, 0x800, val | 1);
+        if (ret)
+                goto failed;
+        return 0;
+
+ failed:
+        return -ENODEV;
+}
+
+/*
+ * Nokia cards are not really multiport cards.  Shouldn't this
+ * be handled by setting the quirk entry .multi = 0 | 1 ?
+ */
+static void quirk_config_nokia(struct pcmcia_device *link)
+{
+        struct serial_info *info = link->priv;
+
+        if (info->multi > 1)
+                info->multi = 1;
+}
+
+static void quirk_wakeup_oxsemi(struct pcmcia_device *link)
+{
+        struct serial_info *info = link->priv;
+
+        if (info->c950ctrl)
+                outb(12, info->c950ctrl + 1);
+}
+
+/* request_region? oxsemi branch does no request_region too... */
+/*
+ * This sequence is needed to properly initialize MC45 attached to OXCF950.
+ * I tried decreasing these msleep()s, but it worked properly (survived
+ * 1000 stop/start operations) with these timeouts (or bigger).
+ */
+static void quirk_wakeup_possio_gcc(struct pcmcia_device *link)
+{
+        struct serial_info *info = link->priv;
+        unsigned int ctrl = info->c950ctrl;
+
+        outb(0xA, ctrl + 1);
+        msleep(100);
+        outb(0xE, ctrl + 1);
+        msleep(300);
+        outb(0xC, ctrl + 1);
+        msleep(100);
+        outb(0xE, ctrl + 1);
+        msleep(200);
+        outb(0xF, ctrl + 1);
+        msleep(100);
+        outb(0xE, ctrl + 1);
+        msleep(100);
+        outb(0xC, ctrl + 1);
+}
+
+/*
+ * Socket Dual IO: this enables irq's for second port
+ */
+static void quirk_config_socket(struct pcmcia_device *link)
+{
+        struct serial_info *info = link->priv;
+
+        if (info->multi)
+                link->config_flags |= CONF_ENABLE_ESR;
+}
+
+static const struct serial_quirk quirks[] = {
+        {
+                .manfid = 0x0160,
+                .prodid = 0x0104,
+                .multi  = -1,
+                .setup  = quirk_setup_brainboxes_0104,
+        }, {
+                .manfid = 0x015D,
+                .prodid = 0x4C45,
+                .multi  = -1,
+                .setup  = quirk_setup_brainboxes_0104,
+        }, {
+                .manfid = MANFID_IBM,
+                .prodid = ~0,
+                .multi  = -1,
+                .post   = quirk_post_ibm,
+        }, {
+                .manfid = MANFID_INTEL,
+                .prodid = PRODID_INTEL_DUAL_RS232,
+                .multi  = 2,
+        }, {
+                .manfid = MANFID_NATINST,
+                .prodid = PRODID_NATINST_QUAD_RS232,
+                .multi  = 4,
+        }, {
+                .manfid = MANFID_NOKIA,
+                .prodid = ~0,
+                .multi  = -1,
+                .config = quirk_config_nokia,
+        }, {
+                .manfid = MANFID_OMEGA,
+                .prodid = PRODID_OMEGA_QSP_100,
+                .multi  = 4,
+        }, {
+                .manfid = MANFID_OXSEMI,
+                .prodid = ~0,
+                .multi  = -1,
+                .wakeup = quirk_wakeup_oxsemi,
+        }, {
+                .manfid = MANFID_POSSIO,
+                .prodid = PRODID_POSSIO_GCC,
+                .multi  = -1,
+                .wakeup = quirk_wakeup_possio_gcc,
+        }, {
+                .manfid = MANFID_QUATECH,
+                .prodid = PRODID_QUATECH_DUAL_RS232,
+                .multi  = 2,
+        }, {
+                .manfid = MANFID_QUATECH,
+                .prodid = PRODID_QUATECH_DUAL_RS232_D1,
+                .multi  = 2,
+        }, {
+                .manfid = MANFID_QUATECH,
+                .prodid = PRODID_QUATECH_DUAL_RS232_G,
+                .multi  = 2,
+        }, {
+                .manfid = MANFID_QUATECH,
+                .prodid = PRODID_QUATECH_QUAD_RS232,
+                .multi  = 4,
+        }, {
+                .manfid = MANFID_SOCKET,
+                .prodid = PRODID_SOCKET_DUAL_RS232,
+                .multi  = 2,
+                .config = quirk_config_socket,
+        }, {
+                .manfid = MANFID_SOCKET,
+                .prodid = ~0,
+                .multi  = -1,
+                .config = quirk_config_socket,
+        }
+};
+
+
+static int serial_config(struct pcmcia_device * link);
+
+
+static void serial_remove(struct pcmcia_device *link)
+{
+        struct serial_info *info = link->priv;
+        int i;
+
+        dev_dbg(&link->dev, "serial_release\n");
+
+        /*
+         * Recheck to see if the device is still configured.
+         */
+        for (i = 0; i < info->ndev; i++)
+                serial8250_unregister_port(info->line[i]);
+
+        if (!info->slave)
+                pcmcia_disable_device(link);
+}
+
+static int serial_suspend(struct pcmcia_device *link)
+{
+        struct serial_info *info = link->priv;
+        int i;
+
+        for (i = 0; i < info->ndev; i++)
+                serial8250_suspend_port(info->line[i]);
+
+        return 0;
+}
+
+static int serial_resume(struct pcmcia_device *link)
+{
+        struct serial_info *info = link->priv;
+        int i;
+
+        for (i = 0; i < info->ndev; i++)
+                serial8250_resume_port(info->line[i]);
+
+        if (info->quirk && info->quirk->wakeup)
+                info->quirk->wakeup(link);
+
+        return 0;
+}
+
+static int serial_probe(struct pcmcia_device *link)
+{
+        struct serial_info *info;
+
+        dev_dbg(&link->dev, "serial_attach()\n");
+
+        /* Create new serial device */
+        info = kzalloc(sizeof (*info), GFP_KERNEL);
+        if (!info)
+                return -ENOMEM;
+        info->p_dev = link;
+        link->priv = info;
+
+        link->config_flags |= CONF_ENABLE_IRQ;
+        if (do_sound)
+                link->config_flags |= CONF_ENABLE_SPKR;
+
+        return serial_config(link);
+}
+
+static void serial_detach(struct pcmcia_device *link)
+{
+        struct serial_info *info = link->priv;
+
+        dev_dbg(&link->dev, "serial_detach\n");
+
+        /*
+         * Ensure that the ports have been released.
+         */
+        serial_remove(link);
+
+        /* free bits */
+        kfree(info);
+}
+
+/*====================================================================*/
+
+static int setup_serial(struct pcmcia_device *handle, struct serial_info * info,
+                        unsigned int iobase, int irq)
+{
+        struct uart_port port;
+        int line;
+
+        memset(&port, 0, sizeof (struct uart_port));
+        port.iobase = iobase;
+        port.irq = irq;
+        port.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
+        port.uartclk = 1843200;
+        port.dev = &handle->dev;
+        if (buggy_uart)
+                port.flags |= UPF_BUGGY_UART;
+
+        if (info->quirk && info->quirk->setup)
+                info->quirk->setup(handle, &port);
+
+        line = serial8250_register_port(&port);
+        if (line < 0) {
+                printk(KERN_NOTICE "serial_cs: serial8250_register_port() at "
+                       "0x%04lx, irq %d failed\n", (u_long)iobase, irq);
+                return -EINVAL;
+        }
+
+        info->line[info->ndev] = line;
+        info->ndev++;
+
+        return 0;
+}
+
+/*====================================================================*/
+
+static int pfc_config(struct pcmcia_device *p_dev)
+{
+        unsigned int port = 0;
+        struct serial_info *info = p_dev->priv;
+
+        if ((p_dev->resource[1]->end != 0) &&
+                (resource_size(p_dev->resource[1]) == 8)) {
+                port = p_dev->resource[1]->start;
+                info->slave = 1;
+        } else if ((info->manfid == MANFID_OSITECH) &&
+                (resource_size(p_dev->resource[0]) == 0x40)) {
+                port = p_dev->resource[0]->start + 0x28;
+                info->slave = 1;
+        }
+        if (info->slave)
+                return setup_serial(p_dev, info, port, p_dev->irq);
+
+        dev_warn(&p_dev->dev, "no usable port range found, giving up\n");
+        return -ENODEV;
+}
+
+static int simple_config_check(struct pcmcia_device *p_dev, void *priv_data)
+{
+        static const int size_table[2] = { 8, 16 };
+        int *try = priv_data;
+
+        if (p_dev->resource[0]->start == 0)
+                return -ENODEV;
+
+        if ((*try & 0x1) == 0)
+                p_dev->io_lines = 16;
+
+        if (p_dev->resource[0]->end != size_table[(*try >> 1)])
+                return -ENODEV;
+
+        p_dev->resource[0]->end = 8;
+        p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
+        p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
+
+        return pcmcia_request_io(p_dev);
+}
+
+static int simple_config_check_notpicky(struct pcmcia_device *p_dev,
+                                        void *priv_data)
+{
+        static const unsigned int base[5] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8, 0x0 };
+        int j;
+
+        if (p_dev->io_lines > 3)
+                return -ENODEV;
+
+        p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
+        p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
+        p_dev->resource[0]->end = 8;
+
+        for (j = 0; j < 5; j++) {
+                p_dev->resource[0]->start = base[j];
+                p_dev->io_lines = base[j] ? 16 : 3;
+                if (!pcmcia_request_io(p_dev))
+                        return 0;
+        }
+        return -ENODEV;
+}
+
+static int simple_config(struct pcmcia_device *link)
+{
+        struct serial_info *info = link->priv;
+        int i = -ENODEV, try;
+
+        /* First pass: look for a config entry that looks normal.
+         * Two tries: without IO aliases, then with aliases */
+        link->config_flags |= CONF_AUTO_SET_VPP | CONF_AUTO_SET_IO;
+        for (try = 0; try < 4; try++)
+                if (!pcmcia_loop_config(link, simple_config_check, &try))
+                        goto found_port;
+
+        /* Second pass: try to find an entry that isn't picky about
+           its base address, then try to grab any standard serial port
+           address, and finally try to get any free port. */
+        if (!pcmcia_loop_config(link, simple_config_check_notpicky, NULL))
+                goto found_port;
+
+        dev_warn(&link->dev, "no usable port range found, giving up\n");
+        return -1;
+
+found_port:
+        if (info->multi && (info->manfid == MANFID_3COM))
+                link->config_index &= ~(0x08);
+
+        /*
+         * Apply any configuration quirks.
+         */
+        if (info->quirk && info->quirk->config)
+                info->quirk->config(link);
+
+        i = pcmcia_enable_device(link);
+        if (i != 0)
+                return -1;
+        return setup_serial(link, info, link->resource[0]->start, link->irq);
+}
+
+static int multi_config_check(struct pcmcia_device *p_dev, void *priv_data)
+{
+        int *multi = priv_data;
+
+        if (p_dev->resource[1]->end)
+                return -EINVAL;
+
+        /* The quad port cards have bad CIS's, so just look for a
+           window larger than 8 ports and assume it will be right */
+        if (p_dev->resource[0]->end <= 8)
+                return -EINVAL;
+
+        p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
+        p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
+        p_dev->resource[0]->end = *multi * 8;
+
+        if (pcmcia_request_io(p_dev))
+                return -ENODEV;
+        return 0;
+}
+
+static int multi_config_check_notpicky(struct pcmcia_device *p_dev,
+                                       void *priv_data)
+{
+        int *base2 = priv_data;
+
+        if (!p_dev->resource[0]->end || !p_dev->resource[1]->end)
+                return -ENODEV;
+
+        p_dev->resource[0]->end = p_dev->resource[1]->end = 8;
+        p_dev->resource[0]->flags &= ~IO_DATA_PATH_WIDTH;
+        p_dev->resource[0]->flags |= IO_DATA_PATH_WIDTH_8;
+
+        if (pcmcia_request_io(p_dev))
+                return -ENODEV;
+
+        *base2 = p_dev->resource[0]->start + 8;
+        return 0;
+}
+
+static int multi_config(struct pcmcia_device *link)
+{
+        struct serial_info *info = link->priv;
+        int i, base2 = 0;
+
+        link->config_flags |= CONF_AUTO_SET_IO;
+        /* First, look for a generic full-sized window */
+        if (!pcmcia_loop_config(link, multi_config_check, &info->multi))
+                base2 = link->resource[0]->start + 8;
+        else {
+                /* If that didn't work, look for two windows */
+                info->multi = 2;
+                if (pcmcia_loop_config(link, multi_config_check_notpicky,
+                                       &base2)) {
+                        dev_warn(&link->dev, "no usable port range "
+                               "found, giving up\n");
+                        return -ENODEV;
+                }
+        }
+
+        if (!link->irq)
+                dev_warn(&link->dev, "no usable IRQ found, continuing...\n");
+
+        /*
+         * Apply any configuration quirks.
+         */
+        if (info->quirk && info->quirk->config)
+                info->quirk->config(link);
+
+        i = pcmcia_enable_device(link);
+        if (i != 0)
+                return -ENODEV;
+
+        /* The Oxford Semiconductor OXCF950 cards are in fact single-port:
+         * 8 registers are for the UART, the others are extra registers.
+         * Siemen's MC45 PCMCIA (Possio's GCC) is OXCF950 based too.
+         */
+        if (info->manfid == MANFID_OXSEMI || (info->manfid == MANFID_POSSIO &&
+                                info->prodid == PRODID_POSSIO_GCC)) {
+                int err;
+
+                if (link->config_index == 1 ||
+                    link->config_index == 3) {
+                        err = setup_serial(link, info, base2,
+                                        link->irq);
+                        base2 = link->resource[0]->start;
+                } else {
+                        err = setup_serial(link, info, link->resource[0]->start,
+                                        link->irq);
+                }
+                info->c950ctrl = base2;
+
+                /*
+                 * FIXME: We really should wake up the port prior to
+                 * handing it over to the serial layer.
+                 */
+                if (info->quirk && info->quirk->wakeup)
+                        info->quirk->wakeup(link);
+
+                return 0;
+        }
+
+        setup_serial(link, info, link->resource[0]->start, link->irq);
+        for (i = 0; i < info->multi - 1; i++)
+                setup_serial(link, info, base2 + (8 * i),
+                                link->irq);
+        return 0;
+}
+
+static int serial_check_for_multi(struct pcmcia_device *p_dev,  void *priv_data)
+{
+        struct serial_info *info = p_dev->priv;
+
+        if (!p_dev->resource[0]->end)
+                return -EINVAL;
+
+        if ((!p_dev->resource[1]->end) && (p_dev->resource[0]->end % 8 == 0))
+                info->multi = p_dev->resource[0]->end >> 3;
+
+        if ((p_dev->resource[1]->end) && (p_dev->resource[0]->end == 8)
+                && (p_dev->resource[1]->end == 8))
+                info->multi = 2;
+
+        return 0; /* break */
+}
+
+
+static int serial_config(struct pcmcia_device * link)
+{
+        struct serial_info *info = link->priv;
+        int i;
+
+        dev_dbg(&link->dev, "serial_config\n");
+
+        /* Is this a compliant multifunction card? */
+        info->multi = (link->socket->functions > 1);
+
+        /* Is this a multiport card? */
+        info->manfid = link->manf_id;
+        info->prodid = link->card_id;
+
+        for (i = 0; i < ARRAY_SIZE(quirks); i++)
+                if ((quirks[i].manfid == ~0 ||
+                     quirks[i].manfid == info->manfid) &&
+                    (quirks[i].prodid == ~0 ||
+                     quirks[i].prodid == info->prodid)) {
+                        info->quirk = &quirks[i];
+                        break;
+                }
+
+        /* Another check for dual-serial cards: look for either serial or
+           multifunction cards that ask for appropriate IO port ranges */
+        if ((info->multi == 0) &&
+            (link->has_func_id) &&
+            (link->socket->pcmcia_pfc == 0) &&
+            ((link->func_id == CISTPL_FUNCID_MULTI) ||
+             (link->func_id == CISTPL_FUNCID_SERIAL)))
+                pcmcia_loop_config(link, serial_check_for_multi, info);
+
+        /*
+         * Apply any multi-port quirk.
+         */
+        if (info->quirk && info->quirk->multi != -1)
+                info->multi = info->quirk->multi;
+
+        dev_info(&link->dev,
+                "trying to set up [0x%04x:0x%04x] (pfc: %d, multi: %d, quirk: %p)\n",
+                link->manf_id, link->card_id,
+                link->socket->pcmcia_pfc, info->multi, info->quirk);
+        if (link->socket->pcmcia_pfc)
+                i = pfc_config(link);
+        else if (info->multi > 1)
+                i = multi_config(link);
+        else
+                i = simple_config(link);
+
+        if (i || info->ndev == 0)
+                goto failed;
+
+        /*
+         * Apply any post-init quirk.  FIXME: This should really happen
+         * before we register the port, since it might already be in use.
+         */
+        if (info->quirk && info->quirk->post)
+                if (info->quirk->post(link))
+                        goto failed;
+
+        return 0;
+
+failed:
+        dev_warn(&link->dev, "failed to initialize\n");
+        serial_remove(link);
+        return -ENODEV;
+}
+
+static const struct pcmcia_device_id serial_ids[] = {
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0057, 0x0021),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0089, 0x110a),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0104, 0x000a),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0105, 0x0d0a),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0105, 0x0e0a),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0105, 0xea15),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0109, 0x0501),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0138, 0x110a),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0140, 0x000a),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0143, 0x3341),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0143, 0xc0ab),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x016c, 0x0081),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x021b, 0x0101),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x08a1, 0xc0ab),
+        PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "CC/XJEM3288", "DATA/FAX/CELL ETHERNET MODEM", 0xf510db04, 0x04cd2988, 0x46a52d63),
+        PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "CC/XJEM3336", "DATA/FAX/CELL ETHERNET MODEM", 0xf510db04, 0x0143b773, 0x46a52d63),
+        PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "EM1144T", "PCMCIA MODEM", 0xf510db04, 0x856d66c8, 0xbd6c43ef),
+        PCMCIA_PFC_DEVICE_PROD_ID123(1, "MEGAHERTZ", "XJEM1144/CCEM1144", "PCMCIA MODEM", 0xf510db04, 0x52d21e1e, 0xbd6c43ef),
+        PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM28", 0x2e3ee845, 0x0ea978ea),
+        PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM33", 0x2e3ee845, 0x80609023),
+        PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "CEM56", 0x2e3ee845, 0xa650c32a),
+        PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "REM10", 0x2e3ee845, 0x76df1d29),
+        PCMCIA_PFC_DEVICE_PROD_ID13(1, "Xircom", "XEM5600", 0x2e3ee845, 0xf1403719),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "AnyCom", "Fast Ethernet + 56K COMBO", 0x578ba6e7, 0xb0ac62c4),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "ATKK", "LM33-PCM-T", 0xba9eb7e2, 0x077c174e),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "D-Link", "DME336T", 0x1a424a1c, 0xb23897ff),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "Gateway 2000", "XJEM3336", 0xdd9989be, 0x662c394c),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "Grey Cell", "GCS3000", 0x2a151fac, 0x48b932ae),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "Linksys", "EtherFast 10&100 + 56K PC Card (PCMLM56)", 0x0733cc81, 0xb3765033),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "LINKSYS", "PCMLM336", 0xf7cb0b07, 0x7a821b58),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "MEGAHERTZ", "XJEM1144/CCEM1144", 0xf510db04, 0x52d21e1e),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "MICRO RESEARCH", "COMBO-L/M-336", 0xb2ced065, 0x3ced0555),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "NEC", "PK-UG-J001" ,0x18df0ba0 ,0x831b1064),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "Ositech", "Trumpcard:Jack of Diamonds Modem+Ethernet", 0xc2f80cd, 0x656947b9),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "Ositech", "Trumpcard:Jack of Hearts Modem+Ethernet", 0xc2f80cd, 0xdc9ba5ed),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "PCMCIAs", "ComboCard", 0xdcfe12d3, 0xcd8906cc),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "PCMCIAs", "LanModem", 0xdcfe12d3, 0xc67c648f),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "TDK", "GlobalNetworker 3410/3412", 0x1eae9475, 0xd9a93bed),
+        PCMCIA_PFC_DEVICE_PROD_ID12(1, "Xircom", "CreditCard Ethernet+Modem II", 0x2e3ee845, 0xeca401bf),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0e01),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0a05),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x0b05),
+        PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0032, 0x1101),
+        PCMCIA_MFC_DEVICE_MANF_CARD(0, 0x0104, 0x0070),
+        PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0101, 0x0562),
+        PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0104, 0x0070),
+        PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x016c, 0x0020),
+        PCMCIA_MFC_DEVICE_PROD_ID123(1, "APEX DATA", "MULTICARD", "ETHERNET-MODEM", 0x11c2da09, 0x7289dc5d, 0xaad95e1f),
+        PCMCIA_MFC_DEVICE_PROD_ID12(1, "IBM", "Home and Away 28.8 PC Card       ", 0xb569a6e5, 0x5bd4ff2c),
+        PCMCIA_MFC_DEVICE_PROD_ID12(1, "IBM", "Home and Away Credit Card Adapter", 0xb569a6e5, 0x4bdf15c3),
+        PCMCIA_MFC_DEVICE_PROD_ID12(1, "IBM", "w95 Home and Away Credit Card ", 0xb569a6e5, 0xae911c15),
+        PCMCIA_MFC_DEVICE_PROD_ID1(1, "Motorola MARQUIS", 0xf03e4e77),
+        PCMCIA_MFC_DEVICE_PROD_ID2(1, "FAX/Modem/Ethernet Combo Card ", 0x1ed59302),
+        PCMCIA_DEVICE_MANF_CARD(0x0089, 0x0301),
+        PCMCIA_DEVICE_MANF_CARD(0x00a4, 0x0276),
+        PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0039),
+        PCMCIA_DEVICE_MANF_CARD(0x0104, 0x0006),
+        PCMCIA_DEVICE_MANF_CARD(0x0105, 0x0101), /* TDK DF2814 */
+        PCMCIA_DEVICE_MANF_CARD(0x0105, 0x100a), /* Xircom CM-56G */
+        PCMCIA_DEVICE_MANF_CARD(0x0105, 0x3e0a), /* TDK DF5660 */
+        PCMCIA_DEVICE_MANF_CARD(0x0105, 0x410a),
+        PCMCIA_DEVICE_MANF_CARD(0x0107, 0x0002), /* USRobotics 14,400 */
+        PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d50),
+        PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d51),
+        PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d52),
+        PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0d53),
+        PCMCIA_DEVICE_MANF_CARD(0x010b, 0xd180),
+        PCMCIA_DEVICE_MANF_CARD(0x0115, 0x3330), /* USRobotics/SUN 14,400 */
+        PCMCIA_DEVICE_MANF_CARD(0x0124, 0x0100), /* Nokia DTP-2 ver II */
+        PCMCIA_DEVICE_MANF_CARD(0x0134, 0x5600), /* LASAT COMMUNICATIONS A/S */
+        PCMCIA_DEVICE_MANF_CARD(0x0137, 0x000e),
+        PCMCIA_DEVICE_MANF_CARD(0x0137, 0x001b),
+        PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0025),
+        PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0045),
+        PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0052),
+        PCMCIA_DEVICE_MANF_CARD(0x016c, 0x0006), /* Psion 56K+Fax */
+        PCMCIA_DEVICE_MANF_CARD(0x0200, 0x0001), /* MultiMobile */
+        PCMCIA_DEVICE_PROD_ID134("ADV", "TECH", "COMpad-32/85", 0x67459937, 0x916d02ba, 0x8fbe92ae),
+        PCMCIA_DEVICE_PROD_ID124("GATEWAY2000", "CC3144", "PCMCIA MODEM", 0x506bccae, 0xcb3685f1, 0xbd6c43ef),
+        PCMCIA_DEVICE_PROD_ID14("MEGAHERTZ", "PCMCIA MODEM", 0xf510db04, 0xbd6c43ef),
+        PCMCIA_DEVICE_PROD_ID124("TOSHIBA", "T144PF", "PCMCIA MODEM", 0xb4585a1a, 0x7271409c, 0xbd6c43ef),
+        PCMCIA_DEVICE_PROD_ID123("FUJITSU", "FC14F ", "MBH10213", 0x6ee5a3d8, 0x30ead12b, 0xb00f05a0),
+        PCMCIA_DEVICE_PROD_ID123("Novatel Wireless", "Merlin UMTS Modem", "U630", 0x32607776, 0xd9e73b13, 0xe87332e),
+        PCMCIA_DEVICE_PROD_ID13("MEGAHERTZ", "V.34 PCMCIA MODEM", 0xf510db04, 0xbb2cce4a),
+        PCMCIA_DEVICE_PROD_ID12("Brain Boxes", "Bluetooth PC Card", 0xee138382, 0xd4ce9b02),
+        PCMCIA_DEVICE_PROD_ID12("CIRRUS LOGIC", "FAX MODEM", 0xe625f451, 0xcecd6dfa),
+        PCMCIA_DEVICE_PROD_ID12("COMPAQ", "PCMCIA 28800 FAX/DATA MODEM", 0xa3a3062c, 0x8cbd7c76),
+        PCMCIA_DEVICE_PROD_ID12("COMPAQ", "PCMCIA 33600 FAX/DATA MODEM", 0xa3a3062c, 0x5a00ce95),
+        PCMCIA_DEVICE_PROD_ID12("Computerboards, Inc.", "PCM-COM422", 0xd0b78f51, 0x7e2d49ed),
+        PCMCIA_DEVICE_PROD_ID12("Dr. Neuhaus", "FURY CARD 14K4", 0x76942813, 0x8b96ce65),
+        PCMCIA_DEVICE_PROD_ID12("IBM", "ISDN/56K/GSM", 0xb569a6e5, 0xfee5297b),
+        PCMCIA_DEVICE_PROD_ID12("Intelligent", "ANGIA FAX/MODEM", 0xb496e65e, 0xf31602a6),
+        PCMCIA_DEVICE_PROD_ID12("Intel", "MODEM 2400+", 0x816cc815, 0x412729fb),
+        PCMCIA_DEVICE_PROD_ID12("Intertex", "IX34-PCMCIA", 0xf8a097e3, 0x97880447),
+        PCMCIA_DEVICE_PROD_ID12("IOTech Inc ", "PCMCIA Dual RS-232 Serial Port Card", 0x3bd2d898, 0x92abc92f),
+        PCMCIA_DEVICE_PROD_ID12("MACRONIX", "FAX/MODEM", 0x668388b3, 0x3f9bdf2f),
+        PCMCIA_DEVICE_PROD_ID12("Multi-Tech", "MT1432LT", 0x5f73be51, 0x0b3e2383),
+        PCMCIA_DEVICE_PROD_ID12("Multi-Tech", "MT2834LT", 0x5f73be51, 0x4cd7c09e),
+        PCMCIA_DEVICE_PROD_ID12("OEM      ", "C288MX     ", 0xb572d360, 0xd2385b7a),
+        PCMCIA_DEVICE_PROD_ID12("Option International", "V34bis GSM/PSTN Data/Fax Modem", 0x9d7cd6f5, 0x5cb8bf41),
+        PCMCIA_DEVICE_PROD_ID12("PCMCIA   ", "C336MX     ", 0x99bcafe9, 0xaa25bcab),
+        PCMCIA_DEVICE_PROD_ID12("Quatech Inc", "PCMCIA Dual RS-232 Serial Port Card", 0xc4420b35, 0x92abc92f),
+        PCMCIA_DEVICE_PROD_ID12("Quatech Inc", "Dual RS-232 Serial Port PC Card", 0xc4420b35, 0x031a380d),
+        PCMCIA_DEVICE_PROD_ID12("Telia", "SurfinBird 560P/A+", 0xe2cdd5e, 0xc9314b38),
+        PCMCIA_DEVICE_PROD_ID1("Smart Serial Port", 0x2d8ce292),
+        PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "PCMCIA", "EN2218-LAN/MODEM", 0x281f1c5d, 0x570f348e, "cis/PCMLM28.cis"),
+        PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "PCMCIA", "UE2218-LAN/MODEM", 0x281f1c5d, 0x6fdcacee, "cis/PCMLM28.cis"),
+        PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "Psion Dacom", "Gold Card V34 Ethernet", 0xf5f025c2, 0x338e8155, "cis/PCMLM28.cis"),
+        PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "Psion Dacom", "Gold Card V34 Ethernet GSM", 0xf5f025c2, 0x4ae85d35, "cis/PCMLM28.cis"),
+        PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "LINKSYS", "PCMLM28", 0xf7cb0b07, 0x66881874, "cis/PCMLM28.cis"),
+        PCMCIA_PFC_DEVICE_CIS_PROD_ID12(1, "TOSHIBA", "Modem/LAN Card", 0xb4585a1a, 0x53f922f8, "cis/PCMLM28.cis"),
+        PCMCIA_MFC_DEVICE_CIS_PROD_ID12(1, "DAYNA COMMUNICATIONS", "LAN AND MODEM MULTIFUNCTION", 0x8fdf8f89, 0xdd5ed9e8, "cis/DP83903.cis"),
+        PCMCIA_MFC_DEVICE_CIS_PROD_ID4(1, "NSC MF LAN/Modem", 0x58fc6056, "cis/DP83903.cis"),
+        PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x0556, "cis/3CCFEM556.cis"),
+        PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0175, 0x0000, "cis/DP83903.cis"),
+        PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x0035, "cis/3CXEM556.cis"),
+        PCMCIA_MFC_DEVICE_CIS_MANF_CARD(1, 0x0101, 0x003d, "cis/3CXEM556.cis"),
+        PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC850", 0xd85f6206, 0x42a2c018, "cis/SW_8xx_SER.cis"), /* Sierra Wireless AC850 3G Network Adapter R1 */
+        PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC860", 0xd85f6206, 0x698f93db, "cis/SW_8xx_SER.cis"), /* Sierra Wireless AC860 3G Network Adapter R1 */
+        PCMCIA_DEVICE_CIS_PROD_ID12("Sierra Wireless", "AC710/AC750", 0xd85f6206, 0x761b11e0, "cis/SW_7xx_SER.cis"),  /* Sierra Wireless AC710/AC750 GPRS Network Adapter R1 */
+        PCMCIA_DEVICE_CIS_MANF_CARD(0x0192, 0xa555, "cis/SW_555_SER.cis"),  /* Sierra Aircard 555 CDMA 1xrtt Modem -- pre update */
+        PCMCIA_DEVICE_CIS_MANF_CARD(0x013f, 0xa555, "cis/SW_555_SER.cis"),  /* Sierra Aircard 555 CDMA 1xrtt Modem -- post update */
+        PCMCIA_DEVICE_CIS_PROD_ID12("MultiTech", "PCMCIA 56K DataFax", 0x842047ee, 0xc2efcf03, "cis/MT5634ZLX.cis"),
+        PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-2", 0x96913a85, 0x27ab5437, "cis/COMpad2.cis"),
+        PCMCIA_DEVICE_CIS_PROD_ID12("ADVANTECH", "COMpad-32/85B-4", 0x96913a85, 0xcec8f102, "cis/COMpad4.cis"),
+        PCMCIA_DEVICE_CIS_PROD_ID123("ADVANTECH", "COMpad-32/85", "1.0", 0x96913a85, 0x8fbe92ae, 0x0877b627, "cis/COMpad2.cis"),
+        PCMCIA_DEVICE_CIS_PROD_ID2("RS-COM 2P", 0xad20b156, "cis/RS-COM-2P.cis"),
+        PCMCIA_DEVICE_CIS_MANF_CARD(0x0013, 0x0000, "cis/GLOBETROTTER.cis"),
+        PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL100  1.00.",0x19ca78af,0xf964f42b),
+        PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL100",0x19ca78af,0x71d98e83),
+        PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL232  1.00.",0x19ca78af,0x69fb7490),
+        PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c1997.","SERIAL CARD: SL232",0x19ca78af,0xb6bc0235),
+        PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c2000.","SERIAL CARD: CF232",0x63f2e0bd,0xb9e175d3),
+        PCMCIA_DEVICE_PROD_ID12("ELAN DIGITAL SYSTEMS LTD, c2000.","SERIAL CARD: CF232-5",0x63f2e0bd,0xfce33442),
+        PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF232",0x3beb8cf2,0x171e7190),
+        PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF232-5",0x3beb8cf2,0x20da4262),
+        PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF428",0x3beb8cf2,0xea5dd57d),
+        PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: CF500",0x3beb8cf2,0xd77255fa),
+        PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: IC232",0x3beb8cf2,0x6a709903),
+        PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: SL232",0x3beb8cf2,0x18430676),
+        PCMCIA_DEVICE_PROD_ID12("Elan","Serial Port: XL232",0x3beb8cf2,0x6f933767),
+        PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: CF332",0x3beb8cf2,0x16dc1ba7),
+        PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: SL332",0x3beb8cf2,0x19816c41),
+        PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: SL385",0x3beb8cf2,0x64112029),
+        PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
+        PCMCIA_MFC_DEVICE_PROD_ID12(0,"Elan","Serial+Parallel Port: SP230",0x3beb8cf2,0xdb9e58bc),
+        PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: CF332",0x3beb8cf2,0x16dc1ba7),
+        PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: SL332",0x3beb8cf2,0x19816c41),
+        PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: SL385",0x3beb8cf2,0x64112029),
+        PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
+        PCMCIA_MFC_DEVICE_PROD_ID12(2,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
+        PCMCIA_MFC_DEVICE_PROD_ID12(3,"Elan","Serial Port: SL432",0x3beb8cf2,0x1cce7ac4),
+        PCMCIA_DEVICE_MANF_CARD(0x0279, 0x950b),
+        /* too generic */
+        /* PCMCIA_MFC_DEVICE_MANF_CARD(0, 0x0160, 0x0002), */
+        /* PCMCIA_MFC_DEVICE_MANF_CARD(1, 0x0160, 0x0002), */
+        PCMCIA_DEVICE_FUNC_ID(2),
+        PCMCIA_DEVICE_NULL,
+};
+MODULE_DEVICE_TABLE(pcmcia, serial_ids);
+
+MODULE_FIRMWARE("cis/PCMLM28.cis");
+MODULE_FIRMWARE("cis/DP83903.cis");
+MODULE_FIRMWARE("cis/3CCFEM556.cis");
+MODULE_FIRMWARE("cis/3CXEM556.cis");
+MODULE_FIRMWARE("cis/SW_8xx_SER.cis");
+MODULE_FIRMWARE("cis/SW_7xx_SER.cis");
+MODULE_FIRMWARE("cis/SW_555_SER.cis");
+MODULE_FIRMWARE("cis/MT5634ZLX.cis");
+MODULE_FIRMWARE("cis/COMpad2.cis");
+MODULE_FIRMWARE("cis/COMpad4.cis");
+MODULE_FIRMWARE("cis/RS-COM-2P.cis");
+
+static struct pcmcia_driver serial_cs_driver = {
+        .owner          = THIS_MODULE,
+        .name           = "serial_cs",
+        .probe          = serial_probe,
+        .remove         = serial_detach,
+        .id_table       = serial_ids,
+        .suspend        = serial_suspend,
+        .resume         = serial_resume,
+};
+
+static int __init init_serial_cs(void)
+{
+        return pcmcia_register_driver(&serial_cs_driver);
+}
+
+static void __exit exit_serial_cs(void)
+{
+        pcmcia_unregister_driver(&serial_cs_driver);
+}
+
+module_init(init_serial_cs);
+module_exit(exit_serial_cs);
+
+MODULE_LICENSE("GPL");
diff --git a/drivers/tty/serial/suncore.h b/drivers/tty/serial/suncore.h
new file mode 100644
index 00000000000..db2057936c3
--- /dev/null
+++ b/drivers/tty/serial/suncore.h
@@ -0,0 +1,33 @@
+/* suncore.h
+ *
+ * Generic SUN serial/kbd/ms layer.  Based entirely
+ * upon drivers/sbus/char/sunserial.h which is:
+ *
+ * Copyright (C) 1997  Eddie C. Dost  (ecd@skynet.be)
+ *
+ * Port to new UART layer is:
+ *
+ * Copyright (C) 2002 David S. Miller (davem@redhat.com)
+ */
+
+#ifndef _SERIAL_SUN_H
+#define _SERIAL_SUN_H
+
+/* Serial keyboard defines for L1-A processing... */
+#define SUNKBD_RESET            0xff
+#define SUNKBD_L1               0x01
+#define SUNKBD_UP               0x80
+#define SUNKBD_A                0x4d
+
+extern unsigned int suncore_mouse_baud_cflag_next(unsigned int, int *);
+extern int suncore_mouse_baud_detection(unsigned char, int);
+
+extern int sunserial_register_minors(struct uart_driver *, int);
+extern void sunserial_unregister_minors(struct uart_driver *, int);
+
+extern int sunserial_console_match(struct console *, struct device_node *,
+                                   struct uart_driver *, int, bool);
+extern void sunserial_console_termios(struct console *,
+                                      struct device_node *);
+
+#endif /* !(_SERIAL_SUN_H) */
diff --git a/drivers/tty/serial/tegra_hsuart.c b/drivers/tty/serial/tegra_hsuart.c
new file mode 100644
index 00000000000..4169cbcbf29
--- /dev/null
+++ b/drivers/tty/serial/tegra_hsuart.c
@@ -0,0 +1,1682 @@
+/*
+ * drivers/serial/tegra_hsuart.c
+ *
+ * High-speed serial driver for NVIDIA Tegra SoCs
+ *
+ * Copyright (C) 2009-2011 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/termios.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/string.h>
+#include <linux/pagemap.h>
+#include <linux/serial_reg.h>
+#include <linux/serial_8250.h>
+#include <linux/debugfs.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <linux/tegra_uart.h>
+
+#include <mach/dma.h>
+#include <mach/clk.h>
+
+#define TEGRA_UART_TYPE "TEGRA_UART"
+
+#define TX_EMPTY_STATUS (UART_LSR_TEMT | UART_LSR_THRE)
+
+#define BYTES_TO_ALIGN(x) ((unsigned long)(ALIGN((x), sizeof(u32))) - \
+        (unsigned long)(x))
+
+#define UART_RX_DMA_BUFFER_SIZE    (2048*8)
+
+#define UART_LSR_FIFOE          0x80
+#define UART_LSR_TXFIFO_FULL    0x100
+#define UART_IER_EORD           0x20
+#define UART_MCR_RTS_EN         0x40
+#define UART_MCR_CTS_EN         0x20
+#define UART_LSR_ANY            (UART_LSR_OE | UART_LSR_BI | \
+                                UART_LSR_PE | UART_LSR_FE)
+
+#define TX_FORCE_PIO 0
+#define RX_FORCE_PIO 0
+
+const int dma_req_sel[] = {
+        TEGRA_DMA_REQ_SEL_UARTA,
+        TEGRA_DMA_REQ_SEL_UARTB,
+        TEGRA_DMA_REQ_SEL_UARTC,
+        TEGRA_DMA_REQ_SEL_UARTD,
+        TEGRA_DMA_REQ_SEL_UARTE,
+};
+
+#define TEGRA_TX_PIO                    1
+#define TEGRA_TX_DMA                    2
+
+#define TEGRA_UART_MIN_DMA              16
+#define TEGRA_UART_FIFO_SIZE            8
+
+#define TEGRA_UART_CLOSED    0
+#define TEGRA_UART_OPENED    1
+#define TEGRA_UART_CLOCK_OFF 2
+#define TEGRA_UART_SUSPEND   3
+
+/* Tx fifo trigger level setting in tegra uart is in
+ * reverse way then conventional uart */
+#define TEGRA_UART_TX_TRIG_16B 0x00
+#define TEGRA_UART_TX_TRIG_8B  0x10
+#define TEGRA_UART_TX_TRIG_4B  0x20
+#define TEGRA_UART_TX_TRIG_1B  0x30
+
+struct tegra_uart_port {
+        struct uart_port        uport;
+        char                    port_name[32];
+
+        /* Module info */
+        unsigned long           size;
+        struct clk              *clk;
+        unsigned int            baud;
+
+        /* Register shadow */
+        unsigned char           fcr_shadow;
+        unsigned char           mcr_shadow;
+        unsigned char           lcr_shadow;
+        unsigned char           ier_shadow;
+        bool                    use_cts_control;
+        bool                    rts_active;
+
+        int                     tx_in_progress;
+        unsigned int            tx_bytes;
+
+        dma_addr_t              xmit_dma_addr;
+
+        /* TX DMA */
+        struct tegra_dma_req    tx_dma_req;
+        struct tegra_dma_channel *tx_dma;
+
+        /* RX DMA */
+        struct tegra_dma_req    rx_dma_req;
+        struct tegra_dma_channel *rx_dma;
+
+        bool                    use_rx_dma;
+        bool                    use_tx_dma;
+        int                     uart_state;
+        bool                    rx_timeout;
+        int                     rx_in_progress;
+};
+
+static void tegra_set_baudrate(struct tegra_uart_port *t, unsigned int baud);
+static void do_handle_rx_pio(struct tegra_uart_port *t);
+static void do_handle_rx_dma(struct tegra_uart_port *t);
+static void set_rts(struct tegra_uart_port *t, bool active);
+
+static inline u8 uart_readb(struct tegra_uart_port *t, unsigned long reg)
+{
+        u8 val = readb(t->uport.membase + (reg << t->uport.regshift));
+        dev_vdbg(t->uport.dev, "%s: %p %03lx = %02x\n", __func__,
+                t->uport.membase, reg << t->uport.regshift, val);
+        return val;
+}
+
+static inline u32 uart_readl(struct tegra_uart_port *t, unsigned long reg)
+{
+        u32 val = readl(t->uport.membase + (reg << t->uport.regshift));
+        dev_vdbg(t->uport.dev, "%s: %p %03lx = %02x\n", __func__,
+                t->uport.membase, reg << t->uport.regshift, val);
+        return val;
+}
+
+static inline void uart_writeb(struct tegra_uart_port *t, u8 val,
+        unsigned long reg)
+{
+        dev_vdbg(t->uport.dev, "%s: %p %03lx %02x\n",
+                __func__, t->uport.membase, reg << t->uport.regshift, val);
+        writeb(val, t->uport.membase + (reg << t->uport.regshift));
+}
+
+static inline void uart_writel(struct tegra_uart_port *t, u32 val,
+        unsigned long reg)
+{
+        dev_vdbg(t->uport.dev, "%s: %p %03lx %08x\n",
+                __func__, t->uport.membase, reg << t->uport.regshift, val);
+        writel(val, t->uport.membase + (reg << t->uport.regshift));
+}
+
+static void fill_tx_fifo(struct tegra_uart_port *t, int max_bytes)
+{
+        int i;
+        struct circ_buf *xmit = &t->uport.state->xmit;
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+        unsigned long lsr;
+#endif
+
+        for (i = 0; i < max_bytes; i++) {
+                BUG_ON(uart_circ_empty(xmit));
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+                lsr = uart_readl(t, UART_LSR);
+                if ((lsr & UART_LSR_TXFIFO_FULL))
+                        break;
+#endif
+                uart_writeb(t, xmit->buf[xmit->tail], UART_TX);
+                xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+                t->uport.icount.tx++;
+        }
+}
+
+static void tegra_start_pio_tx(struct tegra_uart_port *t, unsigned int bytes)
+{
+        if (bytes > TEGRA_UART_FIFO_SIZE)
+                bytes = TEGRA_UART_FIFO_SIZE;
+
+        t->fcr_shadow &= ~UART_FCR_T_TRIG_11;
+        t->fcr_shadow |= TEGRA_UART_TX_TRIG_8B;
+        uart_writeb(t, t->fcr_shadow, UART_FCR);
+        t->tx_in_progress = TEGRA_TX_PIO;
+        t->tx_bytes = bytes;
+        t->ier_shadow |= UART_IER_THRI;
+        uart_writeb(t, t->ier_shadow, UART_IER);
+}
+
+static void tegra_start_dma_tx(struct tegra_uart_port *t, unsigned long bytes)
+{
+        struct circ_buf *xmit;
+        xmit = &t->uport.state->xmit;
+
+        dma_sync_single_for_device(t->uport.dev, t->xmit_dma_addr,
+                UART_XMIT_SIZE, DMA_TO_DEVICE);
+
+        t->fcr_shadow &= ~UART_FCR_T_TRIG_11;
+        t->fcr_shadow |= TEGRA_UART_TX_TRIG_4B;
+        uart_writeb(t, t->fcr_shadow, UART_FCR);
+
+        t->tx_bytes = bytes & ~(sizeof(u32)-1);
+        t->tx_dma_req.source_addr = t->xmit_dma_addr + xmit->tail;
+        t->tx_dma_req.size = t->tx_bytes;
+
+        t->tx_in_progress = TEGRA_TX_DMA;
+
+        tegra_dma_enqueue_req(t->tx_dma, &t->tx_dma_req);
+}
+
+/* Called with u->lock taken */
+static void tegra_start_next_tx(struct tegra_uart_port *t)
+{
+        unsigned long tail;
+        unsigned long count;
+
+        struct circ_buf *xmit;
+
+        xmit = &t->uport.state->xmit;
+        tail = (unsigned long)&xmit->buf[xmit->tail];
+        count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
+
+
+        dev_vdbg(t->uport.dev, "+%s %lu %d\n", __func__, count,
+                t->tx_in_progress);
+
+        if (count == 0)
+                goto out;
+
+        if (!t->use_tx_dma || count < TEGRA_UART_MIN_DMA)
+                tegra_start_pio_tx(t, count);
+        else if (BYTES_TO_ALIGN(tail) > 0)
+                tegra_start_pio_tx(t, BYTES_TO_ALIGN(tail));
+        else
+                tegra_start_dma_tx(t, count);
+
+out:
+        dev_vdbg(t->uport.dev, "-%s", __func__);
+}
+
+/* Called by serial core driver with u->lock taken. */
+static void tegra_start_tx(struct uart_port *u)
+{
+        struct tegra_uart_port *t;
+        struct circ_buf *xmit;
+
+        t = container_of(u, struct tegra_uart_port, uport);
+        xmit = &u->state->xmit;
+
+        if (!uart_circ_empty(xmit) && !t->tx_in_progress)
+                tegra_start_next_tx(t);
+}
+
+static int tegra_start_dma_rx(struct tegra_uart_port *t)
+{
+        wmb();
+        dma_sync_single_for_device(t->uport.dev, t->rx_dma_req.dest_addr,
+                        t->rx_dma_req.size, DMA_TO_DEVICE);
+        if (tegra_dma_enqueue_req(t->rx_dma, &t->rx_dma_req)) {
+                dev_err(t->uport.dev, "Could not enqueue Rx DMA req\n");
+                return -EINVAL;
+        }
+        return 0;
+}
+
+static void tegra_rx_dma_threshold_callback(struct tegra_dma_req *req)
+{
+        struct tegra_uart_port *t = req->dev;
+        struct uart_port *u = &t->uport;
+        unsigned long flags;
+
+        spin_lock_irqsave(&u->lock, flags);
+
+        do_handle_rx_dma(t);
+
+        spin_unlock_irqrestore(&u->lock, flags);
+}
+
+/*
+ * It is expected that the callers take the UART lock when this API is called.
+ *
+ * There are 2 contexts when this function is called:
+ *
+ * 1. DMA ISR - DMA ISR triggers the threshold complete calback, which calls the
+ * dequue API which in-turn calls this callback. UART lock is taken during
+ * the call to the threshold callback.
+ *
+ * 2. UART ISR - UART calls the dequue API which in-turn will call this API.
+ * In this case, UART ISR takes the UART lock.
+ */
+static void tegra_rx_dma_complete_callback(struct tegra_dma_req *req)
+{
+        struct tegra_uart_port *t = req->dev;
+        struct uart_port *u = &t->uport;
+        struct tty_struct *tty = u->state->port.tty;
+        int copied;
+
+        /* If we are here, DMA is stopped */
+
+        dev_dbg(t->uport.dev, "%s: %d %d\n", __func__, req->bytes_transferred,
+                req->status);
+        if (req->bytes_transferred) {
+                t->uport.icount.rx += req->bytes_transferred;
+                dma_sync_single_for_cpu(t->uport.dev, req->dest_addr,
+                                req->size, DMA_FROM_DEVICE);
+                copied = tty_insert_flip_string(tty,
+                        ((unsigned char *)(req->virt_addr)),
+                        req->bytes_transferred);
+                if (copied != req->bytes_transferred) {
+                        WARN_ON(1);
+                        dev_err(t->uport.dev, "Not able to copy uart data "
+                                "to tty layer Req %d and coped %d\n",
+                                req->bytes_transferred, copied);
+                }
+                dma_sync_single_for_device(t->uport.dev, req->dest_addr,
+                                req->size, DMA_TO_DEVICE);
+        }
+
+        do_handle_rx_pio(t);
+
+        /* Push the read data later in caller place. */
+        if (req->status == -TEGRA_DMA_REQ_ERROR_ABORTED)
+                return;
+
+        spin_unlock(&u->lock);
+        tty_flip_buffer_push(u->state->port.tty);
+        spin_lock(&u->lock);
+}
+
+/* Lock already taken */
+static void do_handle_rx_dma(struct tegra_uart_port *t)
+{
+        struct uart_port *u = &t->uport;
+        if (t->rts_active)
+                set_rts(t, false);
+        tegra_dma_dequeue_req(t->rx_dma, &t->rx_dma_req);
+        tty_flip_buffer_push(u->state->port.tty);
+        /* enqueue the request again */
+        tegra_start_dma_rx(t);
+        if (t->rts_active)
+                set_rts(t, true);
+}
+
+/* Wait for a symbol-time. */
+static void wait_sym_time(struct tegra_uart_port *t, unsigned int syms)
+{
+
+        /* Definitely have a start bit. */
+        unsigned int bits = 1;
+        switch (t->lcr_shadow & 3) {
+        case UART_LCR_WLEN5:
+                bits += 5;
+                break;
+        case UART_LCR_WLEN6:
+                bits += 6;
+                break;
+        case UART_LCR_WLEN7:
+                bits += 7;
+                break;
+        default:
+                bits += 8;
+                break;
+        }
+
+        /* Technically 5 bits gets 1.5 bits of stop... */
+        if (t->lcr_shadow & UART_LCR_STOP)
+                bits += 2;
+        else
+                bits++;
+
+        if (t->lcr_shadow & UART_LCR_PARITY)
+                bits++;
+
+        if (likely(t->baud))
+                udelay(DIV_ROUND_UP(syms * bits * 1000000, t->baud));
+}
+
+/* Flush desired FIFO. */
+static void tegra_fifo_reset(struct tegra_uart_port *t, u8 fcr_bits)
+{
+        unsigned char fcr = t->fcr_shadow;
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+        fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
+        uart_writeb(t, fcr, UART_FCR);
+#else
+        /*Hw issue: Resetting tx fifo with non-fifo
+        mode to avoid any extra character to be sent*/
+        fcr &= ~UART_FCR_ENABLE_FIFO;
+        uart_writeb(t, fcr, UART_FCR);
+        udelay(60);
+        fcr |= fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
+        uart_writeb(t, fcr, UART_FCR);
+        fcr |= UART_FCR_ENABLE_FIFO;
+        uart_writeb(t, fcr, UART_FCR);
+#endif
+        uart_readb(t, UART_SCR); /* Dummy read to ensure the write is posted */
+        wait_sym_time(t, 1); /* Wait for the flush to propagate. */
+}
+
+static char do_decode_rx_error(struct tegra_uart_port *t, u8 lsr)
+{
+        char flag = TTY_NORMAL;
+
+        if (unlikely(lsr & UART_LSR_ANY)) {
+                if (lsr & UART_LSR_OE) {
+                        /* Overrrun error  */
+                        flag |= TTY_OVERRUN;
+                        t->uport.icount.overrun++;
+                        dev_err(t->uport.dev, "Got overrun errors\n");
+                } else if (lsr & UART_LSR_PE) {
+                        /* Parity error */
+                        flag |= TTY_PARITY;
+                        t->uport.icount.parity++;
+                        dev_err(t->uport.dev, "Got Parity errors\n");
+                } else if (lsr & UART_LSR_FE) {
+                        flag |= TTY_FRAME;
+                        t->uport.icount.frame++;
+                        dev_err(t->uport.dev, "Got frame errors\n");
+                } else if (lsr & UART_LSR_BI) {
+                        dev_err(t->uport.dev, "Got Break\n");
+                        t->uport.icount.brk++;
+                        /* If FIFO read error without any data, reset Rx FIFO */
+                        if (!(lsr & UART_LSR_DR) && (lsr & UART_LSR_FIFOE))
+                                tegra_fifo_reset(t, UART_FCR_CLEAR_RCVR);
+                }
+        }
+        return flag;
+}
+
+static void do_handle_rx_pio(struct tegra_uart_port *t)
+{
+        int count = 0;
+        do {
+                char flag = TTY_NORMAL;
+                unsigned char lsr = 0;
+                unsigned char ch;
+
+
+                lsr = uart_readb(t, UART_LSR);
+                if (!(lsr & UART_LSR_DR))
+                        break;
+
+                flag =  do_decode_rx_error(t, lsr);
+                ch = uart_readb(t, UART_RX);
+                t->uport.icount.rx++;
+                count++;
+
+                if (!uart_handle_sysrq_char(&t->uport, c))
+                        uart_insert_char(&t->uport, lsr, UART_LSR_OE, ch, flag);
+        } while (1);
+
+        dev_dbg(t->uport.dev, "PIO received %d bytes\n", count);
+        return;
+}
+
+static void do_handle_modem_signal(struct uart_port *u)
+{
+        unsigned char msr;
+        struct tegra_uart_port *t;
+
+        t = container_of(u, struct tegra_uart_port, uport);
+        msr = uart_readb(t, UART_MSR);
+        if (msr & UART_MSR_CTS)
+                dev_dbg(u->dev, "CTS triggered\n");
+        if (msr & UART_MSR_DSR)
+                dev_dbg(u->dev, "DSR enabled\n");
+        if (msr & UART_MSR_DCD)
+                dev_dbg(u->dev, "CD enabled\n");
+        if (msr & UART_MSR_RI)
+                dev_dbg(u->dev, "RI enabled\n");
+        return;
+}
+
+static void do_handle_tx_pio(struct tegra_uart_port *t)
+{
+        struct circ_buf *xmit = &t->uport.state->xmit;
+
+        fill_tx_fifo(t, t->tx_bytes);
+
+        t->tx_in_progress = 0;
+
+        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+                uart_write_wakeup(&t->uport);
+
+        tegra_start_next_tx(t);
+        return;
+}
+
+static void tegra_tx_dma_complete_callback(struct tegra_dma_req *req)
+{
+        struct tegra_uart_port *t = req->dev;
+        struct circ_buf *xmit = &t->uport.state->xmit;
+        int count = req->bytes_transferred;
+        unsigned long flags;
+
+        dev_vdbg(t->uport.dev, "%s: %d\n", __func__, count);
+
+        /* Update xmit pointers without lock if dma aborted. */
+        if (req->status == -TEGRA_DMA_REQ_ERROR_ABORTED) {
+                xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
+                t->tx_in_progress = 0;
+                return;
+        }
+
+        spin_lock_irqsave(&t->uport.lock, flags);
+        xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
+        t->tx_in_progress = 0;
+
+        if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+                uart_write_wakeup(&t->uport);
+
+        tegra_start_next_tx(t);
+
+        spin_unlock_irqrestore(&t->uport.lock, flags);
+}
+
+static irqreturn_t tegra_uart_isr(int irq, void *data)
+{
+        struct tegra_uart_port *t = data;
+        struct uart_port *u = &t->uport;
+        unsigned char iir;
+        unsigned char ier;
+        bool is_rx_int = false;
+        unsigned long flags;
+
+        spin_lock_irqsave(&u->lock, flags);
+        t  = container_of(u, struct tegra_uart_port, uport);
+        while (1) {
+                iir = uart_readb(t, UART_IIR);
+                if (iir & UART_IIR_NO_INT) {
+                        if (likely(t->use_rx_dma) && is_rx_int) {
+                                do_handle_rx_dma(t);
+
+                                if (t->rx_in_progress) {
+                                        ier = t->ier_shadow;
+                                        ier |= (UART_IER_RLSI | UART_IER_RTOIE |
+                                                                UART_IER_EORD);
+                                        t->ier_shadow = ier;
+                                        uart_writeb(t, ier, UART_IER);
+                                }
+                        }
+                        spin_unlock_irqrestore(&u->lock, flags);
+                        return IRQ_HANDLED;
+                }
+
+                dev_dbg(u->dev, "tegra_uart_isr iir = 0x%x (%d)\n", iir,
+                        (iir >> 1) & 0x7);
+                switch ((iir >> 1) & 0x7) {
+                case 0: /* Modem signal change interrupt */
+                        do_handle_modem_signal(u);
+                        break;
+                case 1: /* Transmit interrupt only triggered when using PIO */
+                        t->ier_shadow &= ~UART_IER_THRI;
+                        uart_writeb(t, t->ier_shadow, UART_IER);
+                        do_handle_tx_pio(t);
+                        break;
+                case 4: /* End of data */
+                case 6: /* Rx timeout */
+                case 2: /* Receive */
+                        if (likely(t->use_rx_dma)) {
+                                if (!is_rx_int) {
+                                        is_rx_int = true;
+                                        /* Disable interrups */
+                                        ier = t->ier_shadow;
+                                        ier |= UART_IER_RDI;
+                                        uart_writeb(t, ier, UART_IER);
+                                        ier &= ~(UART_IER_RDI | UART_IER_RLSI |
+                                                UART_IER_RTOIE | UART_IER_EORD);
+                                        t->ier_shadow = ier;
+                                        uart_writeb(t, ier, UART_IER);
+                                }
+                        } else {
+                                do_handle_rx_pio(t);
+
+                                spin_unlock_irqrestore(&u->lock, flags);
+                                tty_flip_buffer_push(u->state->port.tty);
+                                spin_lock_irqsave(&u->lock, flags);
+                        }
+                        break;
+                case 3: /* Receive error */
+                        /* FIXME how to handle this? Why do we get here */
+                        do_decode_rx_error(t, uart_readb(t, UART_LSR));
+                        break;
+                case 5: /* break nothing to handle */
+                case 7: /* break nothing to handle */
+                        break;
+                }
+        }
+}
+
+static void tegra_stop_rx(struct uart_port *u)
+{
+        struct tegra_uart_port *t;
+        unsigned char ier;
+
+        t = container_of(u, struct tegra_uart_port, uport);
+
+        if (t->rts_active)
+                set_rts(t, false);
+
+        if (t->rx_in_progress) {
+                wait_sym_time(t, 1); /* wait a character interval */
+
+                ier = t->ier_shadow;
+                ier &= ~(UART_IER_RDI | UART_IER_RLSI | UART_IER_RTOIE |
+                                        UART_IER_EORD);
+                t->ier_shadow = ier;
+                uart_writeb(t, ier, UART_IER);
+                t->rx_in_progress = 0;
+
+                if (t->use_rx_dma && t->rx_dma)
+                        tegra_dma_dequeue_req(t->rx_dma, &t->rx_dma_req);
+                else
+                        do_handle_rx_pio(t);
+
+                tty_flip_buffer_push(u->state->port.tty);
+        }
+
+        return;
+}
+
+static void tegra_uart_hw_deinit(struct tegra_uart_port *t)
+{
+        unsigned long flags;
+        unsigned long char_time = DIV_ROUND_UP(10000000, t->baud);
+        unsigned long fifo_empty_time = t->uport.fifosize * char_time;
+        unsigned long wait_time;
+        unsigned char lsr;
+        unsigned char msr;
+        unsigned char mcr;
+
+        /* Disable interrupts */
+        uart_writeb(t, 0, UART_IER);
+
+        lsr = uart_readb(t, UART_LSR);
+        if ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
+                msr = uart_readb(t, UART_MSR);
+                mcr = uart_readb(t, UART_MCR);
+                if ((mcr & UART_MCR_CTS_EN) && (msr & UART_MSR_CTS))
+                        dev_err(t->uport.dev, "%s: Tx fifo not empty and "
+                                "slave disabled CTS, Waiting for slave to"
+                                " be ready\n", __func__);
+
+                /* Wait for Tx fifo to be empty */
+                while ((lsr & UART_LSR_TEMT) != UART_LSR_TEMT) {
+                        wait_time = min(fifo_empty_time, 100lu);
+                        udelay(wait_time);
+                        fifo_empty_time -= wait_time;
+                        if (!fifo_empty_time) {
+                                msr = uart_readb(t, UART_MSR);
+                                mcr = uart_readb(t, UART_MCR);
+                                if ((mcr & UART_MCR_CTS_EN) &&
+                                        (msr & UART_MSR_CTS))
+                                        dev_err(t->uport.dev, "%s: Slave is "
+                                        "still not ready!\n", __func__);
+                                break;
+                        }
+                        lsr = uart_readb(t, UART_LSR);
+                }
+        }
+
+        spin_lock_irqsave(&t->uport.lock, flags);
+
+        /* Reset the Rx and Tx FIFOs */
+        tegra_fifo_reset(t, UART_FCR_CLEAR_XMIT | UART_FCR_CLEAR_RCVR);
+
+        t->baud = 0;
+        t->uart_state = TEGRA_UART_CLOSED;
+
+        spin_unlock_irqrestore(&t->uport.lock, flags);
+
+        clk_disable(t->clk);
+}
+
+static void tegra_uart_free_rx_dma_buffer(struct tegra_uart_port *t)
+{
+        if (likely(t->rx_dma_req.dest_addr))
+                dma_free_coherent(t->uport.dev, t->rx_dma_req.size,
+                        t->rx_dma_req.virt_addr, t->rx_dma_req.dest_addr);
+        t->rx_dma_req.dest_addr = 0;
+        t->rx_dma_req.virt_addr = NULL;
+}
+
+static void tegra_uart_free_rx_dma(struct tegra_uart_port *t)
+{
+        if (!t->use_rx_dma)
+                return;
+
+        tegra_dma_free_channel(t->rx_dma);
+        t->rx_dma = NULL;
+        t->use_rx_dma = false;
+}
+
+static int tegra_uart_hw_init(struct tegra_uart_port *t)
+{
+        unsigned char ier;
+
+        dev_vdbg(t->uport.dev, "+tegra_uart_hw_init\n");
+
+        t->fcr_shadow = 0;
+        t->mcr_shadow = 0;
+        t->lcr_shadow = 0;
+        t->ier_shadow = 0;
+        t->baud = 0;
+
+        clk_enable(t->clk);
+
+        /* Reset the UART controller to clear all previous status.*/
+        tegra_periph_reset_assert(t->clk);
+        udelay(100);
+        tegra_periph_reset_deassert(t->clk);
+        udelay(100);
+
+        t->rx_in_progress = 0;
+
+        /*
+         * Set the trigger level
+         *
+         * For PIO mode:
+         *
+         * For receive, this will interrupt the CPU after that many number of
+         * bytes are received, for the remaining bytes the receive timeout
+         * interrupt is received.
+         *
+         *  Rx high watermark is set to 4.
+         *
+         * For transmit, if the trasnmit interrupt is enabled, this will
+         * interrupt the CPU when the number of entries in the FIFO reaches the
+         * low watermark.
+         *
+         *  Tx low watermark is set to 8.
+         *
+         *  For DMA mode:
+         *
+         *  Set the Tx trigger to 4. This should match the DMA burst size that
+         *  programmed in the DMA registers.
+         */
+        t->fcr_shadow = UART_FCR_ENABLE_FIFO;
+        t->fcr_shadow |= UART_FCR_R_TRIG_01;
+        t->fcr_shadow |= TEGRA_UART_TX_TRIG_8B;
+        uart_writeb(t, t->fcr_shadow, UART_FCR);
+
+        if (t->use_rx_dma) {
+                /*
+                 * Initialize the UART for a simple default configuration
+                 * so that the receive DMA buffer may be enqueued */
+                t->lcr_shadow = 3;  /* no parity, stop, 8 data bits */
+                tegra_set_baudrate(t, 115200);
+                t->fcr_shadow |= UART_FCR_DMA_SELECT;
+                uart_writeb(t, t->fcr_shadow, UART_FCR);
+                if (tegra_start_dma_rx(t)) {
+                        dev_err(t->uport.dev, "Rx DMA enqueue failed\n");
+                        tegra_uart_free_rx_dma(t);
+                        t->fcr_shadow &= ~UART_FCR_DMA_SELECT;
+                        uart_writeb(t, t->fcr_shadow, UART_FCR);
+                }
+        } else {
+                uart_writeb(t, t->fcr_shadow, UART_FCR);
+        }
+
+        t->rx_in_progress = 1;
+
+        /*
+         *  Enable IE_RXS for the receive status interrupts like line errros.
+         *  Enable IE_RX_TIMEOUT to get the bytes which cannot be DMA'd.
+         *
+         *  If using DMA mode, enable EORD instead of receive interrupt which
+         *  will interrupt after the UART is done with the receive instead of
+         *  the interrupt when the FIFO "threshold" is reached.
+         *
+         *  EORD is different interrupt than RX_TIMEOUT - RX_TIMEOUT occurs when
+         *  the DATA is sitting in the FIFO and couldn't be transferred to the
+         *  DMA as the DMA size alignment(4 bytes) is not met. EORD will be
+         *  triggered when there is a pause of the incomming data stream for 4
+         *  characters long.
+         *
+         *  For pauses in the data which is not aligned to 4 bytes, we get
+         *  both the EORD as well as RX_TIMEOUT - SW sees RX_TIMEOUT first
+         *  then the EORD.
+         *
+         *  Don't get confused, believe in the magic of nvidia hw...:-)
+         */
+        ier = 0;
+        ier |= UART_IER_RLSI | UART_IER_RTOIE;
+        if (t->use_rx_dma)
+                ier |= UART_IER_EORD;
+        else
+                ier |= UART_IER_RDI;
+        t->ier_shadow = ier;
+        uart_writeb(t, ier, UART_IER);
+
+        t->uart_state = TEGRA_UART_OPENED;
+        dev_vdbg(t->uport.dev, "-tegra_uart_hw_init\n");
+        return 0;
+}
+
+static int tegra_uart_init_rx_dma_buffer(struct tegra_uart_port *t)
+{
+        dma_addr_t rx_dma_phys;
+        void *rx_dma_virt;
+
+        t->rx_dma_req.size = UART_RX_DMA_BUFFER_SIZE;
+        rx_dma_virt = dma_alloc_coherent(t->uport.dev,
+                t->rx_dma_req.size, &rx_dma_phys, GFP_KERNEL);
+        if (!rx_dma_virt) {
+                dev_err(t->uport.dev, "DMA buffers allocate failed\n");
+                return -ENOMEM;
+        }
+        t->rx_dma_req.dest_addr = rx_dma_phys;
+        t->rx_dma_req.virt_addr = rx_dma_virt;
+
+        t->rx_dma_req.source_addr = (unsigned long)t->uport.mapbase;
+        t->rx_dma_req.source_wrap = 4;
+        t->rx_dma_req.dest_wrap = 0;
+        t->rx_dma_req.to_memory = 1;
+        t->rx_dma_req.source_bus_width = 8;
+        t->rx_dma_req.dest_bus_width = 32;
+        t->rx_dma_req.req_sel = dma_req_sel[t->uport.line];
+        t->rx_dma_req.complete = tegra_rx_dma_complete_callback;
+        t->rx_dma_req.threshold = tegra_rx_dma_threshold_callback;
+        t->rx_dma_req.dev = t;
+
+        return 0;
+}
+
+static int tegra_uart_init_rx_dma(struct tegra_uart_port *t)
+{
+        t->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_CONTINUOUS,
+                                        "uart_rx_%d", t->uport.line);
+        if (!t->rx_dma) {
+                dev_err(t->uport.dev, "%s: failed to allocate RX DMA.\n",
+                                __func__);
+                return -ENODEV;
+        }
+        return 0;
+}
+
+static int tegra_startup(struct uart_port *u)
+{
+        struct tegra_uart_port *t = container_of(u,
+                struct tegra_uart_port, uport);
+        int ret = 0;
+        struct tegra_uart_platform_data *pdata;
+
+        t = container_of(u, struct tegra_uart_port, uport);
+        sprintf(t->port_name, "tegra_uart_%d", u->line);
+
+        t->use_tx_dma = false;
+        if (!TX_FORCE_PIO) {
+                t->tx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT,
+                                        "uart_tx_%d", u->line);
+                if (t->tx_dma)
+                        t->use_tx_dma = true;
+                else
+                        pr_err("%s: failed to allocate TX DMA.\n", __func__);
+        }
+        if (t->use_tx_dma) {
+                t->tx_dma_req.instance = u->line;
+                t->tx_dma_req.complete = tegra_tx_dma_complete_callback;
+                t->tx_dma_req.to_memory = 0;
+
+                t->tx_dma_req.dest_addr = (unsigned long)t->uport.mapbase;
+                t->tx_dma_req.dest_wrap = 4;
+                t->tx_dma_req.source_wrap = 0;
+                t->tx_dma_req.source_bus_width = 32;
+                t->tx_dma_req.dest_bus_width = 8;
+                t->tx_dma_req.req_sel = dma_req_sel[t->uport.line];
+                t->tx_dma_req.dev = t;
+                t->tx_dma_req.size = 0;
+                t->xmit_dma_addr = dma_map_single(t->uport.dev,
+                        t->uport.state->xmit.buf, UART_XMIT_SIZE,
+                        DMA_TO_DEVICE);
+        }
+        t->tx_in_progress = 0;
+
+        t->use_rx_dma = false;
+        if (!RX_FORCE_PIO && t->rx_dma_req.virt_addr) {
+                if (!tegra_uart_init_rx_dma(t))
+                        t->use_rx_dma = true;
+        }
+
+        ret = tegra_uart_hw_init(t);
+        if (ret)
+                goto fail;
+
+        pdata = u->dev->platform_data;
+        if (pdata->is_loopback)
+                t->mcr_shadow |= UART_MCR_LOOP;
+
+        dev_dbg(u->dev, "Requesting IRQ %d\n", u->irq);
+        ret = request_irq(u->irq, tegra_uart_isr, IRQF_DISABLED,
+                                t->port_name, t);
+        if (ret) {
+                dev_err(u->dev, "Failed to register ISR for IRQ %d\n", u->irq);
+                goto fail;
+        }
+
+        dev_dbg(u->dev, "Started UART port %d\n", u->line);
+        return 0;
+fail:
+        dev_err(u->dev, "Tegra UART startup failed\n");
+        return ret;
+}
+
+static void tegra_shutdown(struct uart_port *u)
+{
+        struct tegra_uart_port *t;
+
+        t = container_of(u, struct tegra_uart_port, uport);
+        dev_vdbg(u->dev, "+tegra_shutdown\n");
+
+        tegra_uart_hw_deinit(t);
+
+        t->rx_in_progress = 0;
+        t->tx_in_progress = 0;
+
+        tegra_uart_free_rx_dma(t);
+        if (t->use_tx_dma) {
+                tegra_dma_free_channel(t->tx_dma);
+                t->tx_dma = NULL;
+                t->use_tx_dma = false;
+                dma_unmap_single(t->uport.dev, t->xmit_dma_addr, UART_XMIT_SIZE,
+                                DMA_TO_DEVICE);
+                t->xmit_dma_addr = 0;
+        }
+
+        free_irq(u->irq, t);
+        dev_vdbg(u->dev, "-tegra_shutdown\n");
+}
+
+static void tegra_wake_peer(struct uart_port *u)
+{
+        struct tegra_uart_platform_data *pdata = u->dev->platform_data;
+
+        if (pdata && pdata->wake_peer)
+                pdata->wake_peer(u);
+}
+
+static unsigned int tegra_get_mctrl(struct uart_port *u)
+{
+        /*
+         * RI - Ring detector is active
+         * CD/DCD/CAR - Carrier detect is always active. For some reason
+         *                        linux has different names for carrier detect.
+         * DSR - Data Set ready is active as the hardware doesn't support it.
+         *         Don't know if the linux support this yet?
+         * CTS - Clear to send. Always set to active, as the hardware handles
+         *         CTS automatically.
+         */
+        return TIOCM_RI | TIOCM_CD | TIOCM_DSR | TIOCM_CTS;
+}
+
+static void set_rts(struct tegra_uart_port *t, bool active)
+{
+        unsigned char mcr;
+        mcr = t->mcr_shadow;
+        if (active)
+                mcr |= UART_MCR_RTS_EN;
+        else
+                mcr &= ~UART_MCR_RTS_EN;
+        if (mcr != t->mcr_shadow) {
+                uart_writeb(t, mcr, UART_MCR);
+                t->mcr_shadow = mcr;
+        }
+        return;
+}
+
+static void set_dtr(struct tegra_uart_port *t, bool active)
+{
+        unsigned char mcr;
+        mcr = t->mcr_shadow;
+        if (active)
+                mcr |= UART_MCR_DTR;
+        else
+                mcr &= ~UART_MCR_DTR;
+        if (mcr != t->mcr_shadow) {
+                uart_writeb(t, mcr, UART_MCR);
+                t->mcr_shadow = mcr;
+        }
+        return;
+}
+
+static void tegra_set_mctrl(struct uart_port *u, unsigned int mctrl)
+{
+        unsigned char mcr;
+        struct tegra_uart_port *t;
+
+        dev_dbg(u->dev, "tegra_set_mctrl called with %d\n", mctrl);
+        t = container_of(u, struct tegra_uart_port, uport);
+
+        mcr = t->mcr_shadow;
+        if (mctrl & TIOCM_RTS) {
+                t->rts_active = true;
+                set_rts(t, true);
+        } else {
+                t->rts_active = false;
+                set_rts(t, false);
+        }
+
+        if (mctrl & TIOCM_DTR)
+                set_dtr(t, true);
+        else
+                set_dtr(t, false);
+        return;
+}
+
+static void tegra_break_ctl(struct uart_port *u, int break_ctl)
+{
+        struct tegra_uart_port *t;
+        unsigned char lcr;
+
+        t = container_of(u, struct tegra_uart_port, uport);
+        lcr = t->lcr_shadow;
+        if (break_ctl)
+                lcr |= UART_LCR_SBC;
+        else
+                lcr &= ~UART_LCR_SBC;
+        uart_writeb(t, lcr, UART_LCR);
+        t->lcr_shadow = lcr;
+}
+
+static int tegra_request_port(struct uart_port *u)
+{
+        return 0;
+}
+
+static void tegra_release_port(struct uart_port *u)
+{
+        /* Nothing to do here */
+}
+
+static unsigned int tegra_tx_empty(struct uart_port *u)
+{
+        struct tegra_uart_port *t;
+        unsigned int ret = 0;
+        unsigned long flags;
+        unsigned char lsr;
+
+        t = container_of(u, struct tegra_uart_port, uport);
+        dev_vdbg(u->dev, "+tegra_tx_empty\n");
+
+        spin_lock_irqsave(&u->lock, flags);
+        if (!t->tx_in_progress) {
+                lsr = uart_readb(t, UART_LSR);
+                if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
+                        ret = TIOCSER_TEMT;
+        }
+        spin_unlock_irqrestore(&u->lock, flags);
+
+        dev_vdbg(u->dev, "-tegra_tx_empty\n");
+        return ret;
+}
+
+static void tegra_stop_tx(struct uart_port *u)
+{
+        struct tegra_uart_port *t;
+
+        t = container_of(u, struct tegra_uart_port, uport);
+
+        if (t->use_tx_dma)
+                tegra_dma_dequeue_req(t->tx_dma, &t->tx_dma_req);
+
+        return;
+}
+
+static void tegra_enable_ms(struct uart_port *u)
+{
+}
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+static int clk_div71_get_divider(unsigned long parent_rate,
+                unsigned long rate)
+{
+        s64 divider_u71 = parent_rate;
+        if (!rate)
+                return -EINVAL;
+
+        divider_u71 *= 2;
+        divider_u71 += rate - 1;
+        do_div(divider_u71, rate);
+
+        if ((divider_u71 - 2) < 0)
+                return 0;
+
+        if ((divider_u71 - 2) > 255)
+                return -EINVAL;
+
+        return divider_u71 - 2;
+}
+#endif
+
+static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
+{
+        s64 divider_u16;
+
+        divider_u16 = parent_rate;
+        if (!rate)
+                return -EINVAL;
+        divider_u16 += rate - 1;
+        do_div(divider_u16, rate);
+
+        if (divider_u16 > 0xFFFF)
+                return -EINVAL;
+
+        return divider_u16;
+}
+
+static unsigned long find_best_clock_source(struct tegra_uart_port *t,
+                unsigned long rate)
+{
+        struct uart_port *u = &t->uport;
+        struct tegra_uart_platform_data *pdata;
+        int i;
+        int divider;
+        unsigned long parent_rate;
+        unsigned long new_rate;
+        unsigned long err_rate;
+        unsigned int fin_err = rate;
+        unsigned long fin_rate = rate;
+        int final_index = -1;
+        int count;
+        unsigned long error_2perc;
+
+        pdata = u->dev->platform_data;
+        if (!pdata || !pdata->parent_clk_count)
+                return fin_rate;
+
+        error_2perc = (rate / 50);
+
+        for (count = 0; count < pdata->parent_clk_count; ++count) {
+                parent_rate = pdata->parent_clk_list[count].fixed_clk_rate;
+
+                if (parent_rate < rate)
+                        continue;
+
+#ifndef CONFIG_ARCH_TEGRA_2x_SOC
+                divider = clk_div71_get_divider(parent_rate, rate);
+
+                /* Get the best divider around calculated value */
+                if (divider > 2) {
+                        for (i = divider - 2; i < (divider + 2); ++i) {
+                                new_rate = ((parent_rate << 1) + i + 1) /
+                                                                (i + 2);
+                                err_rate = abs(new_rate - rate);
+                                if (err_rate < fin_err) {
+                                        final_index = count;
+                                        fin_err = err_rate;
+                                        fin_rate = new_rate;
+                                        if (fin_err < error_2perc)
+                                                break;
+                                }
+                        }
+                        if (fin_err < error_2perc)
+                                break;
+                }
+#endif
+                /* Get the divisor by uart controller dll/dlm */
+                divider = clk_div16_get_divider(parent_rate, rate);
+
+                /* Get the best divider around calculated value */
+                if (divider > 2) {
+                        for (i = divider - 2; i < (divider + 2); ++i) {
+                                new_rate = parent_rate/i;
+                                err_rate = abs(new_rate - rate);
+                                if (err_rate < fin_err) {
+                                        final_index = count;
+                                        fin_err = err_rate;
+                                        fin_rate = parent_rate;
+                                        if (fin_err < error_2perc)
+                                                break;
+                                }
+                        }
+                        if (fin_err < error_2perc)
+                                break;
+                }
+        }
+
+        if (final_index >= 0) {
+                dev_info(t->uport.dev, "Setting clk_src %s\n",
+                                pdata->parent_clk_list[final_index].name);
+                clk_set_parent(t->clk,
+                        pdata->parent_clk_list[final_index].parent_clk);
+        }
+        return fin_rate;
+}
+
+#define UART_CLOCK_ACCURACY 5
+static void tegra_set_baudrate(struct tegra_uart_port *t, unsigned int baud)
+{
+        unsigned long rate;
+        unsigned int divisor;
+        unsigned char lcr;
+        unsigned int baud_actual;
+        unsigned int baud_delta;
+        unsigned long best_rate;
+
+        if (t->baud == baud)
+                return;
+
+        rate = baud * 16;
+        best_rate = find_best_clock_source(t, rate);
+        clk_set_rate(t->clk, best_rate);
+
+        rate = clk_get_rate(t->clk);
+
+        divisor = rate;
+        do_div(divisor, 16);
+        divisor += baud/2;
+        do_div(divisor, baud);
+
+        /* The allowable baudrate error from desired baudrate is 5% */
+        baud_actual = divisor ? rate / (16 * divisor) : 0;
+        baud_delta = abs(baud_actual - baud);
+        if (WARN_ON(baud_delta * 20 > baud)) {
+                dev_err(t->uport.dev, "requested baud %u, actual %u\n",
+                                baud, baud_actual);
+        }
+
+        lcr = t->lcr_shadow;
+        lcr |= UART_LCR_DLAB;
+        uart_writeb(t, lcr, UART_LCR);
+
+        uart_writel(t, divisor & 0xFF, UART_TX);
+        uart_writel(t, ((divisor >> 8) & 0xFF), UART_IER);
+
+        lcr &= ~UART_LCR_DLAB;
+        uart_writeb(t, lcr, UART_LCR);
+        uart_readb(t, UART_SCR); /* Dummy read to ensure the write is posted */
+
+        t->baud = baud;
+        wait_sym_time(t, 2); /* wait two character intervals at new rate */
+        dev_dbg(t->uport.dev, "Baud %u clock freq %lu and divisor of %u\n",
+                baud, rate, divisor);
+}
+
+static void tegra_set_termios(struct uart_port *u, struct ktermios *termios,
+                                           struct ktermios *oldtermios)
+{
+        struct tegra_uart_port *t;
+        unsigned int baud;
+        unsigned long flags;
+        unsigned int lcr;
+        unsigned int c_cflag = termios->c_cflag;
+        unsigned char mcr;
+
+        t = container_of(u, struct tegra_uart_port, uport);
+        dev_vdbg(t->uport.dev, "+tegra_set_termios\n");
+
+        spin_lock_irqsave(&u->lock, flags);
+
+        /* Changing configuration, it is safe to stop any rx now */
+        if (t->rts_active)
+                set_rts(t, false);
+
+        /* Parity */
+        lcr = t->lcr_shadow;
+        lcr &= ~UART_LCR_PARITY;
+        if (PARENB == (c_cflag & PARENB)) {
+                if (CMSPAR == (c_cflag & CMSPAR)) {
+                        /* FIXME What is space parity? */
+                        /* data |= SPACE_PARITY; */
+                } else if (c_cflag & PARODD) {
+                        lcr |= UART_LCR_PARITY;
+                        lcr &= ~UART_LCR_EPAR;
+                        lcr &= ~UART_LCR_SPAR;
+                } else {
+                        lcr |= UART_LCR_PARITY;
+                        lcr |= UART_LCR_EPAR;
+                        lcr &= ~UART_LCR_SPAR;
+                }
+        }
+
+        lcr &= ~UART_LCR_WLEN8;
+        switch (c_cflag & CSIZE) {
+        case CS5:
+                lcr |= UART_LCR_WLEN5;
+                break;
+        case CS6:
+                lcr |= UART_LCR_WLEN6;
+                break;
+        case CS7:
+                lcr |= UART_LCR_WLEN7;
+                break;
+        default:
+                lcr |= UART_LCR_WLEN8;
+                break;
+        }
+
+        /* Stop bits */
+        if (termios->c_cflag & CSTOPB)
+                lcr |= UART_LCR_STOP;
+        else
+                lcr &= ~UART_LCR_STOP;
+
+        uart_writeb(t, lcr, UART_LCR);
+        t->lcr_shadow = lcr;
+
+        /* Baud rate. */
+        baud = uart_get_baud_rate(u, termios, oldtermios, 200, 4000000);
+        spin_unlock_irqrestore(&u->lock, flags);
+        tegra_set_baudrate(t, baud);
+        spin_lock_irqsave(&u->lock, flags);
+
+        /* Flow control */
+        if (termios->c_cflag & CRTSCTS) {
+                mcr = t->mcr_shadow;
+                mcr |= UART_MCR_CTS_EN;
+                mcr &= ~UART_MCR_RTS_EN;
+                t->mcr_shadow = mcr;
+                uart_writeb(t, mcr, UART_MCR);
+                t->use_cts_control = true;
+                /* if top layer has asked to set rts active then do so here */
+                if (t->rts_active)
+                        set_rts(t, true);
+        } else {
+                mcr = t->mcr_shadow;
+                mcr &= ~UART_MCR_CTS_EN;
+                mcr &= ~UART_MCR_RTS_EN;
+                t->mcr_shadow = mcr;
+                uart_writeb(t, mcr, UART_MCR);
+                t->use_cts_control = false;
+        }
+
+        /* update the port timeout based on new settings */
+        uart_update_timeout(u, termios->c_cflag, baud);
+
+        spin_unlock_irqrestore(&u->lock, flags);
+        dev_vdbg(t->uport.dev, "-tegra_set_termios\n");
+        return;
+}
+
+/*
+ * Flush any TX data submitted for DMA and PIO. Called when the
+ * TX circular buffer is reset.
+ */
+static void tegra_flush_buffer(struct uart_port *u)
+{
+        struct tegra_uart_port *t;
+
+        dev_vdbg(u->dev, "%s called", __func__);
+
+        t = container_of(u, struct tegra_uart_port, uport);
+
+        t->tx_bytes = 0;
+
+        if (t->use_tx_dma) {
+                tegra_dma_dequeue_req(t->tx_dma, &t->tx_dma_req);
+                t->tx_dma_req.size = 0;
+        }
+        return;
+}
+
+
+static void tegra_pm(struct uart_port *u, unsigned int state,
+        unsigned int oldstate)
+{
+
+}
+
+static const char *tegra_type(struct uart_port *u)
+{
+        return TEGRA_UART_TYPE;
+}
+
+static struct uart_ops tegra_uart_ops = {
+        .tx_empty       = tegra_tx_empty,
+        .set_mctrl      = tegra_set_mctrl,
+        .get_mctrl      = tegra_get_mctrl,
+        .stop_tx        = tegra_stop_tx,
+        .start_tx       = tegra_start_tx,
+        .stop_rx        = tegra_stop_rx,
+        .flush_buffer   = tegra_flush_buffer,
+        .enable_ms      = tegra_enable_ms,
+        .break_ctl      = tegra_break_ctl,
+        .startup        = tegra_startup,
+        .shutdown       = tegra_shutdown,
+        .wake_peer      = tegra_wake_peer,
+        .set_termios    = tegra_set_termios,
+        .pm             = tegra_pm,
+        .type           = tegra_type,
+        .request_port   = tegra_request_port,
+        .release_port   = tegra_release_port,
+};
+
+static struct uart_driver tegra_uart_driver = {
+        .owner          = THIS_MODULE,
+        .driver_name    = "tegra_uart",
+        .dev_name       = "ttyHS",
+        .cons           = 0,
+        .nr             = 5,
+};
+
+static int __init tegra_uart_probe(struct platform_device *pdev)
+{
+        struct tegra_uart_port *t;
+        struct uart_port *u;
+        struct resource *resource;
+        int ret;
+        char name[64];
+        if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr) {
+                pr_err("Invalid Uart instance (%d)\n", pdev->id);
+                return -ENODEV;
+        }
+
+        t = kzalloc(sizeof(struct tegra_uart_port), GFP_KERNEL);
+        if (!t) {
+                pr_err("%s: Failed to allocate memory\n", __func__);
+                return -ENOMEM;
+        }
+        u = &t->uport;
+        u->dev = &pdev->dev;
+        platform_set_drvdata(pdev, u);
+        u->line = pdev->id;
+        u->ops = &tegra_uart_ops;
+        u->type = PORT_TEGRA;
+        u->fifosize = 32;
+
+        resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (unlikely(!resource)) {
+                ret = -ENXIO;
+                goto fail;
+        }
+
+        u->mapbase = resource->start;
+        u->membase = IO_ADDRESS(u->mapbase);
+        if (unlikely(!u->membase)) {
+                ret = -ENOMEM;
+                goto fail;
+        }
+        u->iotype = UPIO_MEM32;
+
+        u->irq = platform_get_irq(pdev, 0);
+        if (unlikely(u->irq < 0)) {
+                ret = -ENXIO;
+                goto fail;
+        }
+
+        u->regshift = 2;
+
+        t->clk = clk_get(&pdev->dev, NULL);
+        if (IS_ERR_OR_NULL(t->clk)) {
+                dev_err(&pdev->dev, "Couldn't get the clock\n");
+                ret = -ENODEV;
+                goto fail;
+        }
+
+        ret = uart_add_one_port(&tegra_uart_driver, u);
+        if (ret) {
+                pr_err("%s: Failed(%d) to add uart port %s%d\n",
+                        __func__, ret, tegra_uart_driver.dev_name, u->line);
+                goto fail;
+        }
+
+        snprintf(name, sizeof(name), "tegra_hsuart_%d", u->line);
+        pr_info("Registered UART port %s%d\n",
+                tegra_uart_driver.dev_name, u->line);
+        t->uart_state = TEGRA_UART_CLOSED;
+
+        if (!RX_FORCE_PIO) {
+                ret = tegra_uart_init_rx_dma_buffer(t);
+                if (ret < 0) {
+                        pr_err("%s: Failed(%d) to allocate rx dma buffer "
+                                "%s%d\n", __func__, ret,
+                                tegra_uart_driver.dev_name, u->line);
+                        goto rx_dma_buff_fail;
+                }
+        }
+        return ret;
+
+rx_dma_buff_fail:
+        uart_remove_one_port(&tegra_uart_driver, u);
+fail:
+        if (t->clk)
+                clk_put(t->clk);
+        platform_set_drvdata(pdev, NULL);
+        kfree(t);
+        return ret;
+}
+
+static int __devexit tegra_uart_remove(struct platform_device *pdev)
+{
+        struct tegra_uart_port *t = platform_get_drvdata(pdev);
+        struct uart_port *u;
+
+        if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr)
+                pr_err("Invalid Uart instance (%d)\n", pdev->id);
+
+        u = &t->uport;
+        uart_remove_one_port(&tegra_uart_driver, u);
+
+        tegra_uart_free_rx_dma_buffer(t);
+
+        platform_set_drvdata(pdev, NULL);
+
+        pr_info("Unregistered UART port %s%d\n",
+                tegra_uart_driver.dev_name, u->line);
+        kfree(t);
+        return 0;
+}
+
+static int tegra_uart_suspend(struct platform_device *pdev, pm_message_t state)
+{
+        struct tegra_uart_port *t = platform_get_drvdata(pdev);
+        struct uart_port *u;
+
+        if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr)
+                pr_err("Invalid Uart instance (%d)\n", pdev->id);
+
+        u = &t->uport;
+        dev_dbg(t->uport.dev, "tegra_uart_suspend called\n");
+
+        /* enable clock before calling suspend so that controller
+           register can be accessible */
+        if (t->uart_state == TEGRA_UART_CLOCK_OFF) {
+                clk_enable(t->clk);
+                t->uart_state = TEGRA_UART_OPENED;
+        }
+
+        uart_suspend_port(&tegra_uart_driver, u);
+        t->uart_state = TEGRA_UART_SUSPEND;
+
+        return 0;
+}
+
+static int tegra_uart_resume(struct platform_device *pdev)
+{
+        struct tegra_uart_port *t = platform_get_drvdata(pdev);
+        struct uart_port *u;
+
+        if (pdev->id < 0 || pdev->id > tegra_uart_driver.nr)
+                pr_err("Invalid Uart instance (%d)\n", pdev->id);
+
+        u = &t->uport;
+        dev_dbg(t->uport.dev, "tegra_uart_resume called\n");
+
+        if (t->uart_state == TEGRA_UART_SUSPEND)
+                uart_resume_port(&tegra_uart_driver, u);
+        return 0;
+}
+
+/* Switch off the clock of the uart controller. */
+void tegra_uart_request_clock_off(struct uart_port *uport)
+{
+        unsigned long flags;
+        struct tegra_uart_port *t;
+        bool is_clk_disable = false;
+
+        if (IS_ERR_OR_NULL(uport))
+                BUG();
+
+        dev_vdbg(uport->dev, "tegra_uart_request_clock_off");
+
+        t = container_of(uport, struct tegra_uart_port, uport);
+        spin_lock_irqsave(&uport->lock, flags);
+        if (t->uart_state == TEGRA_UART_OPENED) {
+                is_clk_disable = true;
+                t->uart_state = TEGRA_UART_CLOCK_OFF;
+        }
+        spin_unlock_irqrestore(&uport->lock, flags);
+
+        if (is_clk_disable)
+                clk_disable(t->clk);
+
+        return;
+}
+
+/* Switch on the clock of the uart controller */
+void tegra_uart_request_clock_on(struct uart_port *uport)
+{
+        unsigned long flags;
+        struct tegra_uart_port *t;
+        bool is_clk_enable = false;
+
+        if (IS_ERR_OR_NULL(uport))
+                BUG();
+
+        t = container_of(uport, struct tegra_uart_port, uport);
+        spin_lock_irqsave(&uport->lock, flags);
+        if (t->uart_state == TEGRA_UART_CLOCK_OFF) {
+                is_clk_enable = true;
+                t->uart_state = TEGRA_UART_OPENED;
+        }
+        spin_unlock_irqrestore(&uport->lock, flags);
+
+        if (is_clk_enable)
+                clk_enable(t->clk);
+
+        return;
+}
+
+/* Set the modem control signals state of uart controller. */
+void tegra_uart_set_mctrl(struct uart_port *uport, unsigned int mctrl)
+{
+        unsigned long flags;
+        struct tegra_uart_port *t;
+
+        t = container_of(uport, struct tegra_uart_port, uport);
+        if (t->uart_state != TEGRA_UART_OPENED) {
+                dev_err(t->uport.dev, "Uart is in invalid state\n");
+                return;
+        }
+
+        spin_lock_irqsave(&uport->lock, flags);
+        if (mctrl & TIOCM_RTS) {
+                t->rts_active = true;
+                set_rts(t, true);
+        } else {
+                t->rts_active = false;
+                set_rts(t, false);
+        }
+
+        if (mctrl & TIOCM_DTR)
+                set_dtr(t, true);
+        else
+                set_dtr(t, false);
+        spin_unlock_irqrestore(&uport->lock, flags);
+        return;
+}
+
+/*
+ * Return the status of the transmit fifo whether empty or not.
+ * Return 0 if tx fifo is not empty.
+ * Return TIOCSER_TEMT if tx fifo is empty.
+ */
+int tegra_uart_is_tx_empty(struct uart_port *uport)
+{
+        return tegra_tx_empty(uport);
+}
+
+static struct platform_driver tegra_uart_platform_driver = {
+        .probe          = tegra_uart_probe,
+        .remove         = __devexit_p(tegra_uart_remove),
+        .suspend        = tegra_uart_suspend,
+        .resume         = tegra_uart_resume,
+        .driver         = {
+                .name   = "tegra_uart"
+        }
+};
+
+static int __init tegra_uart_init(void)
+{
+        int ret;
+
+        ret = uart_register_driver(&tegra_uart_driver);
+        if (unlikely(ret)) {
+                pr_err("Could not register %s driver\n",
+                        tegra_uart_driver.driver_name);
+                return ret;
+        }
+
+        ret = platform_driver_register(&tegra_uart_platform_driver);
+        if (unlikely(ret)) {
+                pr_err("Could not register the UART platfrom driver\n");
+                uart_unregister_driver(&tegra_uart_driver);
+                return ret;
+        }
+
+        pr_info("Initialized tegra uart driver\n");
+        return 0;
+}
+
+static void __exit tegra_uart_exit(void)
+{
+        pr_info("Unloading tegra uart driver\n");
+        platform_driver_unregister(&tegra_uart_platform_driver);
+        uart_unregister_driver(&tegra_uart_driver);
+}
+
+module_init(tegra_uart_init);
+module_exit(tegra_uart_exit);
+MODULE_DESCRIPTION("High speed UART driver for tegra chipset");