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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/mmc/host/at91_mci.c
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'drivers/mmc/host/at91_mci.c')
-rw-r--r--drivers/mmc/host/at91_mci.c1216
1 files changed, 1216 insertions, 0 deletions
diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c
new file mode 100644
index 00000000000..a4aa3af86fe
--- /dev/null
+++ b/drivers/mmc/host/at91_mci.c
@@ -0,0 +1,1216 @@
1/*
2 * linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver
3 *
4 * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
5 *
6 * Copyright (C) 2006 Malcolm Noyes
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/*
14 This is the AT91 MCI driver that has been tested with both MMC cards
15 and SD-cards. Boards that support write protect are now supported.
16 The CCAT91SBC001 board does not support SD cards.
17
18 The three entry points are at91_mci_request, at91_mci_set_ios
19 and at91_mci_get_ro.
20
21 SET IOS
22 This configures the device to put it into the correct mode and clock speed
23 required.
24
25 MCI REQUEST
26 MCI request processes the commands sent in the mmc_request structure. This
27 can consist of a processing command and a stop command in the case of
28 multiple block transfers.
29
30 There are three main types of request, commands, reads and writes.
31
32 Commands are straight forward. The command is submitted to the controller and
33 the request function returns. When the controller generates an interrupt to indicate
34 the command is finished, the response to the command are read and the mmc_request_done
35 function called to end the request.
36
37 Reads and writes work in a similar manner to normal commands but involve the PDC (DMA)
38 controller to manage the transfers.
39
40 A read is done from the controller directly to the scatterlist passed in from the request.
41 Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte
42 swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug.
43
44 The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY
45
46 A write is slightly different in that the bytes to write are read from the scatterlist
47 into a dma memory buffer (this is in case the source buffer should be read only). The
48 entire write buffer is then done from this single dma memory buffer.
49
50 The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY
51
52 GET RO
53 Gets the status of the write protect pin, if available.
54*/
55
56#include <linux/module.h>
57#include <linux/moduleparam.h>
58#include <linux/init.h>
59#include <linux/ioport.h>
60#include <linux/platform_device.h>
61#include <linux/interrupt.h>
62#include <linux/blkdev.h>
63#include <linux/delay.h>
64#include <linux/err.h>
65#include <linux/dma-mapping.h>
66#include <linux/clk.h>
67#include <linux/atmel_pdc.h>
68#include <linux/gfp.h>
69#include <linux/highmem.h>
70
71#include <linux/mmc/host.h>
72#include <linux/mmc/sdio.h>
73
74#include <asm/io.h>
75#include <asm/irq.h>
76#include <asm/gpio.h>
77
78#include <mach/board.h>
79#include <mach/cpu.h>
80
81#include "at91_mci.h"
82
83#define DRIVER_NAME "at91_mci"
84
85static inline int at91mci_is_mci1rev2xx(void)
86{
87 return ( cpu_is_at91sam9260()
88 || cpu_is_at91sam9263()
89 || cpu_is_at91cap9()
90 || cpu_is_at91sam9rl()
91 || cpu_is_at91sam9g10()
92 || cpu_is_at91sam9g20()
93 );
94}
95
96#define FL_SENT_COMMAND (1 << 0)
97#define FL_SENT_STOP (1 << 1)
98
99#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \
100 | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \
101 | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
102
103#define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg))
104#define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg))
105
106#define MCI_BLKSIZE 512
107#define MCI_MAXBLKSIZE 4095
108#define MCI_BLKATONCE 256
109#define MCI_BUFSIZE (MCI_BLKSIZE * MCI_BLKATONCE)
110
111/*
112 * Low level type for this driver
113 */
114struct at91mci_host
115{
116 struct mmc_host *mmc;
117 struct mmc_command *cmd;
118 struct mmc_request *request;
119
120 void __iomem *baseaddr;
121 int irq;
122
123 struct at91_mmc_data *board;
124 int present;
125
126 struct clk *mci_clk;
127
128 /*
129 * Flag indicating when the command has been sent. This is used to
130 * work out whether or not to send the stop
131 */
132 unsigned int flags;
133 /* flag for current bus settings */
134 u32 bus_mode;
135
136 /* DMA buffer used for transmitting */
137 unsigned int* buffer;
138 dma_addr_t physical_address;
139 unsigned int total_length;
140
141 /* Latest in the scatterlist that has been enabled for transfer, but not freed */
142 int in_use_index;
143
144 /* Latest in the scatterlist that has been enabled for transfer */
145 int transfer_index;
146
147 /* Timer for timeouts */
148 struct timer_list timer;
149};
150
151/*
152 * Reset the controller and restore most of the state
153 */
154static void at91_reset_host(struct at91mci_host *host)
155{
156 unsigned long flags;
157 u32 mr;
158 u32 sdcr;
159 u32 dtor;
160 u32 imr;
161
162 local_irq_save(flags);
163 imr = at91_mci_read(host, AT91_MCI_IMR);
164
165 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
166
167 /* save current state */
168 mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff;
169 sdcr = at91_mci_read(host, AT91_MCI_SDCR);
170 dtor = at91_mci_read(host, AT91_MCI_DTOR);
171
172 /* reset the controller */
173 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
174
175 /* restore state */
176 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
177 at91_mci_write(host, AT91_MCI_MR, mr);
178 at91_mci_write(host, AT91_MCI_SDCR, sdcr);
179 at91_mci_write(host, AT91_MCI_DTOR, dtor);
180 at91_mci_write(host, AT91_MCI_IER, imr);
181
182 /* make sure sdio interrupts will fire */
183 at91_mci_read(host, AT91_MCI_SR);
184
185 local_irq_restore(flags);
186}
187
188static void at91_timeout_timer(unsigned long data)
189{
190 struct at91mci_host *host;
191
192 host = (struct at91mci_host *)data;
193
194 if (host->request) {
195 dev_err(host->mmc->parent, "Timeout waiting end of packet\n");
196
197 if (host->cmd && host->cmd->data) {
198 host->cmd->data->error = -ETIMEDOUT;
199 } else {
200 if (host->cmd)
201 host->cmd->error = -ETIMEDOUT;
202 else
203 host->request->cmd->error = -ETIMEDOUT;
204 }
205
206 at91_reset_host(host);
207 mmc_request_done(host->mmc, host->request);
208 }
209}
210
211/*
212 * Copy from sg to a dma block - used for transfers
213 */
214static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data)
215{
216 unsigned int len, i, size;
217 unsigned *dmabuf = host->buffer;
218
219 size = data->blksz * data->blocks;
220 len = data->sg_len;
221
222 /* MCI1 rev2xx Data Write Operation and number of bytes erratum */
223 if (at91mci_is_mci1rev2xx())
224 if (host->total_length == 12)
225 memset(dmabuf, 0, 12);
226
227 /*
228 * Just loop through all entries. Size might not
229 * be the entire list though so make sure that
230 * we do not transfer too much.
231 */
232 for (i = 0; i < len; i++) {
233 struct scatterlist *sg;
234 int amount;
235 unsigned int *sgbuffer;
236
237 sg = &data->sg[i];
238
239 sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
240 amount = min(size, sg->length);
241 size -= amount;
242
243 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */
244 int index;
245
246 for (index = 0; index < (amount / 4); index++)
247 *dmabuf++ = swab32(sgbuffer[index]);
248 } else {
249 char *tmpv = (char *)dmabuf;
250 memcpy(tmpv, sgbuffer, amount);
251 tmpv += amount;
252 dmabuf = (unsigned *)tmpv;
253 }
254
255 kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
256
257 if (size == 0)
258 break;
259 }
260
261 /*
262 * Check that we didn't get a request to transfer
263 * more data than can fit into the SG list.
264 */
265 BUG_ON(size != 0);
266}
267
268/*
269 * Handle after a dma read
270 */
271static void at91_mci_post_dma_read(struct at91mci_host *host)
272{
273 struct mmc_command *cmd;
274 struct mmc_data *data;
275 unsigned int len, i, size;
276 unsigned *dmabuf = host->buffer;
277
278 pr_debug("post dma read\n");
279
280 cmd = host->cmd;
281 if (!cmd) {
282 pr_debug("no command\n");
283 return;
284 }
285
286 data = cmd->data;
287 if (!data) {
288 pr_debug("no data\n");
289 return;
290 }
291
292 size = data->blksz * data->blocks;
293 len = data->sg_len;
294
295 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX);
296 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF);
297
298 for (i = 0; i < len; i++) {
299 struct scatterlist *sg;
300 int amount;
301 unsigned int *sgbuffer;
302
303 sg = &data->sg[i];
304
305 sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
306 amount = min(size, sg->length);
307 size -= amount;
308
309 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */
310 int index;
311 for (index = 0; index < (amount / 4); index++)
312 sgbuffer[index] = swab32(*dmabuf++);
313 } else {
314 char *tmpv = (char *)dmabuf;
315 memcpy(sgbuffer, tmpv, amount);
316 tmpv += amount;
317 dmabuf = (unsigned *)tmpv;
318 }
319
320 flush_kernel_dcache_page(sg_page(sg));
321 kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
322 data->bytes_xfered += amount;
323 if (size == 0)
324 break;
325 }
326
327 pr_debug("post dma read done\n");
328}
329
330/*
331 * Handle transmitted data
332 */
333static void at91_mci_handle_transmitted(struct at91mci_host *host)
334{
335 struct mmc_command *cmd;
336 struct mmc_data *data;
337
338 pr_debug("Handling the transmit\n");
339
340 /* Disable the transfer */
341 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
342
343 /* Now wait for cmd ready */
344 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE);
345
346 cmd = host->cmd;
347 if (!cmd) return;
348
349 data = cmd->data;
350 if (!data) return;
351
352 if (cmd->data->blocks > 1) {
353 pr_debug("multiple write : wait for BLKE...\n");
354 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE);
355 } else
356 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
357}
358
359/*
360 * Update bytes tranfered count during a write operation
361 */
362static void at91_mci_update_bytes_xfered(struct at91mci_host *host)
363{
364 struct mmc_data *data;
365
366 /* always deal with the effective request (and not the current cmd) */
367
368 if (host->request->cmd && host->request->cmd->error != 0)
369 return;
370
371 if (host->request->data) {
372 data = host->request->data;
373 if (data->flags & MMC_DATA_WRITE) {
374 /* card is in IDLE mode now */
375 pr_debug("-> bytes_xfered %d, total_length = %d\n",
376 data->bytes_xfered, host->total_length);
377 data->bytes_xfered = data->blksz * data->blocks;
378 }
379 }
380}
381
382
383/*Handle after command sent ready*/
384static int at91_mci_handle_cmdrdy(struct at91mci_host *host)
385{
386 if (!host->cmd)
387 return 1;
388 else if (!host->cmd->data) {
389 if (host->flags & FL_SENT_STOP) {
390 /*After multi block write, we must wait for NOTBUSY*/
391 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
392 } else return 1;
393 } else if (host->cmd->data->flags & MMC_DATA_WRITE) {
394 /*After sendding multi-block-write command, start DMA transfer*/
395 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE);
396 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
397 }
398
399 /* command not completed, have to wait */
400 return 0;
401}
402
403
404/*
405 * Enable the controller
406 */
407static void at91_mci_enable(struct at91mci_host *host)
408{
409 unsigned int mr;
410
411 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
412 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
413 at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
414 mr = AT91_MCI_PDCMODE | 0x34a;
415
416 if (at91mci_is_mci1rev2xx())
417 mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF;
418
419 at91_mci_write(host, AT91_MCI_MR, mr);
420
421 /* use Slot A or B (only one at same time) */
422 at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b);
423}
424
425/*
426 * Disable the controller
427 */
428static void at91_mci_disable(struct at91mci_host *host)
429{
430 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
431}
432
433/*
434 * Send a command
435 */
436static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd)
437{
438 unsigned int cmdr, mr;
439 unsigned int block_length;
440 struct mmc_data *data = cmd->data;
441
442 unsigned int blocks;
443 unsigned int ier = 0;
444
445 host->cmd = cmd;
446
447 /* Needed for leaving busy state before CMD1 */
448 if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
449 pr_debug("Clearing timeout\n");
450 at91_mci_write(host, AT91_MCI_ARGR, 0);
451 at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD);
452 while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
453 /* spin */
454 pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR));
455 }
456 }
457
458 cmdr = cmd->opcode;
459
460 if (mmc_resp_type(cmd) == MMC_RSP_NONE)
461 cmdr |= AT91_MCI_RSPTYP_NONE;
462 else {
463 /* if a response is expected then allow maximum response latancy */
464 cmdr |= AT91_MCI_MAXLAT;
465 /* set 136 bit response for R2, 48 bit response otherwise */
466 if (mmc_resp_type(cmd) == MMC_RSP_R2)
467 cmdr |= AT91_MCI_RSPTYP_136;
468 else
469 cmdr |= AT91_MCI_RSPTYP_48;
470 }
471
472 if (data) {
473
474 if (cpu_is_at91rm9200() || cpu_is_at91sam9261()) {
475 if (data->blksz & 0x3) {
476 pr_debug("Unsupported block size\n");
477 cmd->error = -EINVAL;
478 mmc_request_done(host->mmc, host->request);
479 return;
480 }
481 if (data->flags & MMC_DATA_STREAM) {
482 pr_debug("Stream commands not supported\n");
483 cmd->error = -EINVAL;
484 mmc_request_done(host->mmc, host->request);
485 return;
486 }
487 }
488
489 block_length = data->blksz;
490 blocks = data->blocks;
491
492 /* always set data start - also set direction flag for read */
493 if (data->flags & MMC_DATA_READ)
494 cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
495 else if (data->flags & MMC_DATA_WRITE)
496 cmdr |= AT91_MCI_TRCMD_START;
497
498 if (cmd->opcode == SD_IO_RW_EXTENDED) {
499 cmdr |= AT91_MCI_TRTYP_SDIO_BLOCK;
500 } else {
501 if (data->flags & MMC_DATA_STREAM)
502 cmdr |= AT91_MCI_TRTYP_STREAM;
503 if (data->blocks > 1)
504 cmdr |= AT91_MCI_TRTYP_MULTIPLE;
505 }
506 }
507 else {
508 block_length = 0;
509 blocks = 0;
510 }
511
512 if (host->flags & FL_SENT_STOP)
513 cmdr |= AT91_MCI_TRCMD_STOP;
514
515 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
516 cmdr |= AT91_MCI_OPDCMD;
517
518 /*
519 * Set the arguments and send the command
520 */
521 pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
522 cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR));
523
524 if (!data) {
525 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS);
526 at91_mci_write(host, ATMEL_PDC_RPR, 0);
527 at91_mci_write(host, ATMEL_PDC_RCR, 0);
528 at91_mci_write(host, ATMEL_PDC_RNPR, 0);
529 at91_mci_write(host, ATMEL_PDC_RNCR, 0);
530 at91_mci_write(host, ATMEL_PDC_TPR, 0);
531 at91_mci_write(host, ATMEL_PDC_TCR, 0);
532 at91_mci_write(host, ATMEL_PDC_TNPR, 0);
533 at91_mci_write(host, ATMEL_PDC_TNCR, 0);
534 ier = AT91_MCI_CMDRDY;
535 } else {
536 /* zero block length and PDC mode */
537 mr = at91_mci_read(host, AT91_MCI_MR) & 0x5fff;
538 mr |= (data->blksz & 0x3) ? AT91_MCI_PDCFBYTE : 0;
539 mr |= (block_length << 16);
540 mr |= AT91_MCI_PDCMODE;
541 at91_mci_write(host, AT91_MCI_MR, mr);
542
543 if (!(cpu_is_at91rm9200() || cpu_is_at91sam9261()))
544 at91_mci_write(host, AT91_MCI_BLKR,
545 AT91_MCI_BLKR_BCNT(blocks) |
546 AT91_MCI_BLKR_BLKLEN(block_length));
547
548 /*
549 * Disable the PDC controller
550 */
551 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
552
553 if (cmdr & AT91_MCI_TRCMD_START) {
554 data->bytes_xfered = 0;
555 host->transfer_index = 0;
556 host->in_use_index = 0;
557 if (cmdr & AT91_MCI_TRDIR) {
558 /*
559 * Handle a read
560 */
561 host->total_length = 0;
562
563 at91_mci_write(host, ATMEL_PDC_RPR, host->physical_address);
564 at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ?
565 (blocks * block_length) : (blocks * block_length) / 4);
566 at91_mci_write(host, ATMEL_PDC_RNPR, 0);
567 at91_mci_write(host, ATMEL_PDC_RNCR, 0);
568
569 ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
570 }
571 else {
572 /*
573 * Handle a write
574 */
575 host->total_length = block_length * blocks;
576 /*
577 * MCI1 rev2xx Data Write Operation and
578 * number of bytes erratum
579 */
580 if (at91mci_is_mci1rev2xx())
581 if (host->total_length < 12)
582 host->total_length = 12;
583
584 at91_mci_sg_to_dma(host, data);
585
586 pr_debug("Transmitting %d bytes\n", host->total_length);
587
588 at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address);
589 at91_mci_write(host, ATMEL_PDC_TCR, (data->blksz & 0x3) ?
590 host->total_length : host->total_length / 4);
591
592 ier = AT91_MCI_CMDRDY;
593 }
594 }
595 }
596
597 /*
598 * Send the command and then enable the PDC - not the other way round as
599 * the data sheet says
600 */
601
602 at91_mci_write(host, AT91_MCI_ARGR, cmd->arg);
603 at91_mci_write(host, AT91_MCI_CMDR, cmdr);
604
605 if (cmdr & AT91_MCI_TRCMD_START) {
606 if (cmdr & AT91_MCI_TRDIR)
607 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
608 }
609
610 /* Enable selected interrupts */
611 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier);
612}
613
614/*
615 * Process the next step in the request
616 */
617static void at91_mci_process_next(struct at91mci_host *host)
618{
619 if (!(host->flags & FL_SENT_COMMAND)) {
620 host->flags |= FL_SENT_COMMAND;
621 at91_mci_send_command(host, host->request->cmd);
622 }
623 else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) {
624 host->flags |= FL_SENT_STOP;
625 at91_mci_send_command(host, host->request->stop);
626 } else {
627 del_timer(&host->timer);
628 /* the at91rm9200 mci controller hangs after some transfers,
629 * and the workaround is to reset it after each transfer.
630 */
631 if (cpu_is_at91rm9200())
632 at91_reset_host(host);
633 mmc_request_done(host->mmc, host->request);
634 }
635}
636
637/*
638 * Handle a command that has been completed
639 */
640static void at91_mci_completed_command(struct at91mci_host *host, unsigned int status)
641{
642 struct mmc_command *cmd = host->cmd;
643 struct mmc_data *data = cmd->data;
644
645 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
646
647 cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0));
648 cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1));
649 cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2));
650 cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3));
651
652 pr_debug("Status = %08X/%08x [%08X %08X %08X %08X]\n",
653 status, at91_mci_read(host, AT91_MCI_SR),
654 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
655
656 if (status & AT91_MCI_ERRORS) {
657 if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) {
658 cmd->error = 0;
659 }
660 else {
661 if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) {
662 if (data) {
663 if (status & AT91_MCI_DTOE)
664 data->error = -ETIMEDOUT;
665 else if (status & AT91_MCI_DCRCE)
666 data->error = -EILSEQ;
667 }
668 } else {
669 if (status & AT91_MCI_RTOE)
670 cmd->error = -ETIMEDOUT;
671 else if (status & AT91_MCI_RCRCE)
672 cmd->error = -EILSEQ;
673 else
674 cmd->error = -EIO;
675 }
676
677 pr_debug("Error detected and set to %d/%d (cmd = %d, retries = %d)\n",
678 cmd->error, data ? data->error : 0,
679 cmd->opcode, cmd->retries);
680 }
681 }
682 else
683 cmd->error = 0;
684
685 at91_mci_process_next(host);
686}
687
688/*
689 * Handle an MMC request
690 */
691static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
692{
693 struct at91mci_host *host = mmc_priv(mmc);
694 host->request = mrq;
695 host->flags = 0;
696
697 /* more than 1s timeout needed with slow SD cards */
698 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
699
700 at91_mci_process_next(host);
701}
702
703/*
704 * Set the IOS
705 */
706static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
707{
708 int clkdiv;
709 struct at91mci_host *host = mmc_priv(mmc);
710 unsigned long at91_master_clock = clk_get_rate(host->mci_clk);
711
712 host->bus_mode = ios->bus_mode;
713
714 if (ios->clock == 0) {
715 /* Disable the MCI controller */
716 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS);
717 clkdiv = 0;
718 }
719 else {
720 /* Enable the MCI controller */
721 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
722
723 if ((at91_master_clock % (ios->clock * 2)) == 0)
724 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
725 else
726 clkdiv = (at91_master_clock / ios->clock) / 2;
727
728 pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv,
729 at91_master_clock / (2 * (clkdiv + 1)));
730 }
731 if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
732 pr_debug("MMC: Setting controller bus width to 4\n");
733 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
734 }
735 else {
736 pr_debug("MMC: Setting controller bus width to 1\n");
737 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
738 }
739
740 /* Set the clock divider */
741 at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
742
743 /* maybe switch power to the card */
744 if (host->board->vcc_pin) {
745 switch (ios->power_mode) {
746 case MMC_POWER_OFF:
747 gpio_set_value(host->board->vcc_pin, 0);
748 break;
749 case MMC_POWER_UP:
750 gpio_set_value(host->board->vcc_pin, 1);
751 break;
752 case MMC_POWER_ON:
753 break;
754 default:
755 WARN_ON(1);
756 }
757 }
758}
759
760/*
761 * Handle an interrupt
762 */
763static irqreturn_t at91_mci_irq(int irq, void *devid)
764{
765 struct at91mci_host *host = devid;
766 int completed = 0;
767 unsigned int int_status, int_mask;
768
769 int_status = at91_mci_read(host, AT91_MCI_SR);
770 int_mask = at91_mci_read(host, AT91_MCI_IMR);
771
772 pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
773 int_status & int_mask);
774
775 int_status = int_status & int_mask;
776
777 if (int_status & AT91_MCI_ERRORS) {
778 completed = 1;
779
780 if (int_status & AT91_MCI_UNRE)
781 pr_debug("MMC: Underrun error\n");
782 if (int_status & AT91_MCI_OVRE)
783 pr_debug("MMC: Overrun error\n");
784 if (int_status & AT91_MCI_DTOE)
785 pr_debug("MMC: Data timeout\n");
786 if (int_status & AT91_MCI_DCRCE)
787 pr_debug("MMC: CRC error in data\n");
788 if (int_status & AT91_MCI_RTOE)
789 pr_debug("MMC: Response timeout\n");
790 if (int_status & AT91_MCI_RENDE)
791 pr_debug("MMC: Response end bit error\n");
792 if (int_status & AT91_MCI_RCRCE)
793 pr_debug("MMC: Response CRC error\n");
794 if (int_status & AT91_MCI_RDIRE)
795 pr_debug("MMC: Response direction error\n");
796 if (int_status & AT91_MCI_RINDE)
797 pr_debug("MMC: Response index error\n");
798 } else {
799 /* Only continue processing if no errors */
800
801 if (int_status & AT91_MCI_TXBUFE) {
802 pr_debug("TX buffer empty\n");
803 at91_mci_handle_transmitted(host);
804 }
805
806 if (int_status & AT91_MCI_ENDRX) {
807 pr_debug("ENDRX\n");
808 at91_mci_post_dma_read(host);
809 }
810
811 if (int_status & AT91_MCI_RXBUFF) {
812 pr_debug("RX buffer full\n");
813 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
814 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX);
815 completed = 1;
816 }
817
818 if (int_status & AT91_MCI_ENDTX)
819 pr_debug("Transmit has ended\n");
820
821 if (int_status & AT91_MCI_NOTBUSY) {
822 pr_debug("Card is ready\n");
823 at91_mci_update_bytes_xfered(host);
824 completed = 1;
825 }
826
827 if (int_status & AT91_MCI_DTIP)
828 pr_debug("Data transfer in progress\n");
829
830 if (int_status & AT91_MCI_BLKE) {
831 pr_debug("Block transfer has ended\n");
832 if (host->request->data && host->request->data->blocks > 1) {
833 /* multi block write : complete multi write
834 * command and send stop */
835 completed = 1;
836 } else {
837 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
838 }
839 }
840
841 if (int_status & AT91_MCI_SDIOIRQA)
842 mmc_signal_sdio_irq(host->mmc);
843
844 if (int_status & AT91_MCI_SDIOIRQB)
845 mmc_signal_sdio_irq(host->mmc);
846
847 if (int_status & AT91_MCI_TXRDY)
848 pr_debug("Ready to transmit\n");
849
850 if (int_status & AT91_MCI_RXRDY)
851 pr_debug("Ready to receive\n");
852
853 if (int_status & AT91_MCI_CMDRDY) {
854 pr_debug("Command ready\n");
855 completed = at91_mci_handle_cmdrdy(host);
856 }
857 }
858
859 if (completed) {
860 pr_debug("Completed command\n");
861 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
862 at91_mci_completed_command(host, int_status);
863 } else
864 at91_mci_write(host, AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
865
866 return IRQ_HANDLED;
867}
868
869static irqreturn_t at91_mmc_det_irq(int irq, void *_host)
870{
871 struct at91mci_host *host = _host;
872 int present = !gpio_get_value(irq_to_gpio(irq));
873
874 /*
875 * we expect this irq on both insert and remove,
876 * and use a short delay to debounce.
877 */
878 if (present != host->present) {
879 host->present = present;
880 pr_debug("%s: card %s\n", mmc_hostname(host->mmc),
881 present ? "insert" : "remove");
882 if (!present) {
883 pr_debug("****** Resetting SD-card bus width ******\n");
884 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
885 }
886 /* 0.5s needed because of early card detect switch firing */
887 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
888 }
889 return IRQ_HANDLED;
890}
891
892static int at91_mci_get_ro(struct mmc_host *mmc)
893{
894 struct at91mci_host *host = mmc_priv(mmc);
895
896 if (host->board->wp_pin)
897 return !!gpio_get_value(host->board->wp_pin);
898 /*
899 * Board doesn't support read only detection; let the mmc core
900 * decide what to do.
901 */
902 return -ENOSYS;
903}
904
905static void at91_mci_enable_sdio_irq(struct mmc_host *mmc, int enable)
906{
907 struct at91mci_host *host = mmc_priv(mmc);
908
909 pr_debug("%s: sdio_irq %c : %s\n", mmc_hostname(host->mmc),
910 host->board->slot_b ? 'B':'A', enable ? "enable" : "disable");
911 at91_mci_write(host, enable ? AT91_MCI_IER : AT91_MCI_IDR,
912 host->board->slot_b ? AT91_MCI_SDIOIRQB : AT91_MCI_SDIOIRQA);
913
914}
915
916static const struct mmc_host_ops at91_mci_ops = {
917 .request = at91_mci_request,
918 .set_ios = at91_mci_set_ios,
919 .get_ro = at91_mci_get_ro,
920 .enable_sdio_irq = at91_mci_enable_sdio_irq,
921};
922
923/*
924 * Probe for the device
925 */
926static int __init at91_mci_probe(struct platform_device *pdev)
927{
928 struct mmc_host *mmc;
929 struct at91mci_host *host;
930 struct resource *res;
931 int ret;
932
933 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
934 if (!res)
935 return -ENXIO;
936
937 if (!request_mem_region(res->start, resource_size(res), DRIVER_NAME))
938 return -EBUSY;
939
940 mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev);
941 if (!mmc) {
942 ret = -ENOMEM;
943 dev_dbg(&pdev->dev, "couldn't allocate mmc host\n");
944 goto fail6;
945 }
946
947 mmc->ops = &at91_mci_ops;
948 mmc->f_min = 375000;
949 mmc->f_max = 25000000;
950 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
951 mmc->caps = 0;
952
953 mmc->max_blk_size = MCI_MAXBLKSIZE;
954 mmc->max_blk_count = MCI_BLKATONCE;
955 mmc->max_req_size = MCI_BUFSIZE;
956 mmc->max_segs = MCI_BLKATONCE;
957 mmc->max_seg_size = MCI_BUFSIZE;
958
959 host = mmc_priv(mmc);
960 host->mmc = mmc;
961 host->bus_mode = 0;
962 host->board = pdev->dev.platform_data;
963 if (host->board->wire4) {
964 if (at91mci_is_mci1rev2xx())
965 mmc->caps |= MMC_CAP_4_BIT_DATA;
966 else
967 dev_warn(&pdev->dev, "4 wire bus mode not supported"
968 " - using 1 wire\n");
969 }
970
971 host->buffer = dma_alloc_coherent(&pdev->dev, MCI_BUFSIZE,
972 &host->physical_address, GFP_KERNEL);
973 if (!host->buffer) {
974 ret = -ENOMEM;
975 dev_err(&pdev->dev, "Can't allocate transmit buffer\n");
976 goto fail5;
977 }
978
979 /* Add SDIO capability when available */
980 if (at91mci_is_mci1rev2xx()) {
981 /* at91mci MCI1 rev2xx sdio interrupt erratum */
982 if (host->board->wire4 || !host->board->slot_b)
983 mmc->caps |= MMC_CAP_SDIO_IRQ;
984 }
985
986 /*
987 * Reserve GPIOs ... board init code makes sure these pins are set
988 * up as GPIOs with the right direction (input, except for vcc)
989 */
990 if (host->board->det_pin) {
991 ret = gpio_request(host->board->det_pin, "mmc_detect");
992 if (ret < 0) {
993 dev_dbg(&pdev->dev, "couldn't claim card detect pin\n");
994 goto fail4b;
995 }
996 }
997 if (host->board->wp_pin) {
998 ret = gpio_request(host->board->wp_pin, "mmc_wp");
999 if (ret < 0) {
1000 dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n");
1001 goto fail4;
1002 }
1003 }
1004 if (host->board->vcc_pin) {
1005 ret = gpio_request(host->board->vcc_pin, "mmc_vcc");
1006 if (ret < 0) {
1007 dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n");
1008 goto fail3;
1009 }
1010 }
1011
1012 /*
1013 * Get Clock
1014 */
1015 host->mci_clk = clk_get(&pdev->dev, "mci_clk");
1016 if (IS_ERR(host->mci_clk)) {
1017 ret = -ENODEV;
1018 dev_dbg(&pdev->dev, "no mci_clk?\n");
1019 goto fail2;
1020 }
1021
1022 /*
1023 * Map I/O region
1024 */
1025 host->baseaddr = ioremap(res->start, resource_size(res));
1026 if (!host->baseaddr) {
1027 ret = -ENOMEM;
1028 goto fail1;
1029 }
1030
1031 /*
1032 * Reset hardware
1033 */
1034 clk_enable(host->mci_clk); /* Enable the peripheral clock */
1035 at91_mci_disable(host);
1036 at91_mci_enable(host);
1037
1038 /*
1039 * Allocate the MCI interrupt
1040 */
1041 host->irq = platform_get_irq(pdev, 0);
1042 ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED,
1043 mmc_hostname(mmc), host);
1044 if (ret) {
1045 dev_dbg(&pdev->dev, "request MCI interrupt failed\n");
1046 goto fail0;
1047 }
1048
1049 setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host);
1050
1051 platform_set_drvdata(pdev, mmc);
1052
1053 /*
1054 * Add host to MMC layer
1055 */
1056 if (host->board->det_pin) {
1057 host->present = !gpio_get_value(host->board->det_pin);
1058 }
1059 else
1060 host->present = -1;
1061
1062 mmc_add_host(mmc);
1063
1064 /*
1065 * monitor card insertion/removal if we can
1066 */
1067 if (host->board->det_pin) {
1068 ret = request_irq(gpio_to_irq(host->board->det_pin),
1069 at91_mmc_det_irq, 0, mmc_hostname(mmc), host);
1070 if (ret)
1071 dev_warn(&pdev->dev, "request MMC detect irq failed\n");
1072 else
1073 device_init_wakeup(&pdev->dev, 1);
1074 }
1075
1076 pr_debug("Added MCI driver\n");
1077
1078 return 0;
1079
1080fail0:
1081 clk_disable(host->mci_clk);
1082 iounmap(host->baseaddr);
1083fail1:
1084 clk_put(host->mci_clk);
1085fail2:
1086 if (host->board->vcc_pin)
1087 gpio_free(host->board->vcc_pin);
1088fail3:
1089 if (host->board->wp_pin)
1090 gpio_free(host->board->wp_pin);
1091fail4:
1092 if (host->board->det_pin)
1093 gpio_free(host->board->det_pin);
1094fail4b:
1095 if (host->buffer)
1096 dma_free_coherent(&pdev->dev, MCI_BUFSIZE,
1097 host->buffer, host->physical_address);
1098fail5:
1099 mmc_free_host(mmc);
1100fail6:
1101 release_mem_region(res->start, resource_size(res));
1102 dev_err(&pdev->dev, "probe failed, err %d\n", ret);
1103 return ret;
1104}
1105
1106/*
1107 * Remove a device
1108 */
1109static int __exit at91_mci_remove(struct platform_device *pdev)
1110{
1111 struct mmc_host *mmc = platform_get_drvdata(pdev);
1112 struct at91mci_host *host;
1113 struct resource *res;
1114
1115 if (!mmc)
1116 return -1;
1117
1118 host = mmc_priv(mmc);
1119
1120 if (host->buffer)
1121 dma_free_coherent(&pdev->dev, MCI_BUFSIZE,
1122 host->buffer, host->physical_address);
1123
1124 if (host->board->det_pin) {
1125 if (device_can_wakeup(&pdev->dev))
1126 free_irq(gpio_to_irq(host->board->det_pin), host);
1127 device_init_wakeup(&pdev->dev, 0);
1128 gpio_free(host->board->det_pin);
1129 }
1130
1131 at91_mci_disable(host);
1132 del_timer_sync(&host->timer);
1133 mmc_remove_host(mmc);
1134 free_irq(host->irq, host);
1135
1136 clk_disable(host->mci_clk); /* Disable the peripheral clock */
1137 clk_put(host->mci_clk);
1138
1139 if (host->board->vcc_pin)
1140 gpio_free(host->board->vcc_pin);
1141 if (host->board->wp_pin)
1142 gpio_free(host->board->wp_pin);
1143
1144 iounmap(host->baseaddr);
1145 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1146 release_mem_region(res->start, resource_size(res));
1147
1148 mmc_free_host(mmc);
1149 platform_set_drvdata(pdev, NULL);
1150 pr_debug("MCI Removed\n");
1151
1152 return 0;
1153}
1154
1155#ifdef CONFIG_PM
1156static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state)
1157{
1158 struct mmc_host *mmc = platform_get_drvdata(pdev);
1159 struct at91mci_host *host = mmc_priv(mmc);
1160 int ret = 0;
1161
1162 if (host->board->det_pin && device_may_wakeup(&pdev->dev))
1163 enable_irq_wake(host->board->det_pin);
1164
1165 if (mmc)
1166 ret = mmc_suspend_host(mmc);
1167
1168 return ret;
1169}
1170
1171static int at91_mci_resume(struct platform_device *pdev)
1172{
1173 struct mmc_host *mmc = platform_get_drvdata(pdev);
1174 struct at91mci_host *host = mmc_priv(mmc);
1175 int ret = 0;
1176
1177 if (host->board->det_pin && device_may_wakeup(&pdev->dev))
1178 disable_irq_wake(host->board->det_pin);
1179
1180 if (mmc)
1181 ret = mmc_resume_host(mmc);
1182
1183 return ret;
1184}
1185#else
1186#define at91_mci_suspend NULL
1187#define at91_mci_resume NULL
1188#endif
1189
1190static struct platform_driver at91_mci_driver = {
1191 .remove = __exit_p(at91_mci_remove),
1192 .suspend = at91_mci_suspend,
1193 .resume = at91_mci_resume,
1194 .driver = {
1195 .name = DRIVER_NAME,
1196 .owner = THIS_MODULE,
1197 },
1198};
1199
1200static int __init at91_mci_init(void)
1201{
1202 return platform_driver_probe(&at91_mci_driver, at91_mci_probe);
1203}
1204
1205static void __exit at91_mci_exit(void)
1206{
1207 platform_driver_unregister(&at91_mci_driver);
1208}
1209
1210module_init(at91_mci_init);
1211module_exit(at91_mci_exit);
1212
1213MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver");
1214MODULE_AUTHOR("Nick Randell");
1215MODULE_LICENSE("GPL");
1216MODULE_ALIAS("platform:at91_mci");
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-14 20:22:46 -0400