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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/mmc/host
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'drivers/mmc/host')
-rw-r--r--drivers/mmc/host/at91_mci.c1216
-rw-r--r--drivers/mmc/host/at91_mci.h115
-rw-r--r--drivers/mmc/host/imxmmc.c1169
-rw-r--r--drivers/mmc/host/imxmmc.h64
4 files changed, 2564 insertions, 0 deletions
diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c
new file mode 100644
index 00000000000..a4aa3af86fe
--- /dev/null
+++ b/drivers/mmc/host/at91_mci.c
@@ -0,0 +1,1216 @@
1/*
2 * linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver
3 *
4 * Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
5 *
6 * Copyright (C) 2006 Malcolm Noyes
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13/*
14 This is the AT91 MCI driver that has been tested with both MMC cards
15 and SD-cards. Boards that support write protect are now supported.
16 The CCAT91SBC001 board does not support SD cards.
17
18 The three entry points are at91_mci_request, at91_mci_set_ios
19 and at91_mci_get_ro.
20
21 SET IOS
22 This configures the device to put it into the correct mode and clock speed
23 required.
24
25 MCI REQUEST
26 MCI request processes the commands sent in the mmc_request structure. This
27 can consist of a processing command and a stop command in the case of
28 multiple block transfers.
29
30 There are three main types of request, commands, reads and writes.
31
32 Commands are straight forward. The command is submitted to the controller and
33 the request function returns. When the controller generates an interrupt to indicate
34 the command is finished, the response to the command are read and the mmc_request_done
35 function called to end the request.
36
37 Reads and writes work in a similar manner to normal commands but involve the PDC (DMA)
38 controller to manage the transfers.
39
40 A read is done from the controller directly to the scatterlist passed in from the request.
41 Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte
42 swapped in the scatterlist buffers. AT91SAM926x are not affected by this bug.
43
44 The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY
45
46 A write is slightly different in that the bytes to write are read from the scatterlist
47 into a dma memory buffer (this is in case the source buffer should be read only). The
48 entire write buffer is then done from this single dma memory buffer.
49
50 The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY
51
52 GET RO
53 Gets the status of the write protect pin, if available.
54*/
55
56#include <linux/module.h>
57#include <linux/moduleparam.h>
58#include <linux/init.h>
59#include <linux/ioport.h>
60#include <linux/platform_device.h>
61#include <linux/interrupt.h>
62#include <linux/blkdev.h>
63#include <linux/delay.h>
64#include <linux/err.h>
65#include <linux/dma-mapping.h>
66#include <linux/clk.h>
67#include <linux/atmel_pdc.h>
68#include <linux/gfp.h>
69#include <linux/highmem.h>
70
71#include <linux/mmc/host.h>
72#include <linux/mmc/sdio.h>
73
74#include <asm/io.h>
75#include <asm/irq.h>
76#include <asm/gpio.h>
77
78#include <mach/board.h>
79#include <mach/cpu.h>
80
81#include "at91_mci.h"
82
83#define DRIVER_NAME "at91_mci"
84
85static inline int at91mci_is_mci1rev2xx(void)
86{
87 return ( cpu_is_at91sam9260()
88 || cpu_is_at91sam9263()
89 || cpu_is_at91cap9()
90 || cpu_is_at91sam9rl()
91 || cpu_is_at91sam9g10()
92 || cpu_is_at91sam9g20()
93 );
94}
95
96#define FL_SENT_COMMAND (1 << 0)
97#define FL_SENT_STOP (1 << 1)
98
99#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE \
100 | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE \
101 | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
102
103#define at91_mci_read(host, reg) __raw_readl((host)->baseaddr + (reg))
104#define at91_mci_write(host, reg, val) __raw_writel((val), (host)->baseaddr + (reg))
105
106#define MCI_BLKSIZE 512
107#define MCI_MAXBLKSIZE 4095
108#define MCI_BLKATONCE 256
109#define MCI_BUFSIZE (MCI_BLKSIZE * MCI_BLKATONCE)
110
111/*
112 * Low level type for this driver
113 */
114struct at91mci_host
115{
116 struct mmc_host *mmc;
117 struct mmc_command *cmd;
118 struct mmc_request *request;
119
120 void __iomem *baseaddr;
121 int irq;
122
123 struct at91_mmc_data *board;
124 int present;
125
126 struct clk *mci_clk;
127
128 /*
129 * Flag indicating when the command has been sent. This is used to
130 * work out whether or not to send the stop
131 */
132 unsigned int flags;
133 /* flag for current bus settings */
134 u32 bus_mode;
135
136 /* DMA buffer used for transmitting */
137 unsigned int* buffer;
138 dma_addr_t physical_address;
139 unsigned int total_length;
140
141 /* Latest in the scatterlist that has been enabled for transfer, but not freed */
142 int in_use_index;
143
144 /* Latest in the scatterlist that has been enabled for transfer */
145 int transfer_index;
146
147 /* Timer for timeouts */
148 struct timer_list timer;
149};
150
151/*
152 * Reset the controller and restore most of the state
153 */
154static void at91_reset_host(struct at91mci_host *host)
155{
156 unsigned long flags;
157 u32 mr;
158 u32 sdcr;
159 u32 dtor;
160 u32 imr;
161
162 local_irq_save(flags);
163 imr = at91_mci_read(host, AT91_MCI_IMR);
164
165 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
166
167 /* save current state */
168 mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff;
169 sdcr = at91_mci_read(host, AT91_MCI_SDCR);
170 dtor = at91_mci_read(host, AT91_MCI_DTOR);
171
172 /* reset the controller */
173 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
174
175 /* restore state */
176 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
177 at91_mci_write(host, AT91_MCI_MR, mr);
178 at91_mci_write(host, AT91_MCI_SDCR, sdcr);
179 at91_mci_write(host, AT91_MCI_DTOR, dtor);
180 at91_mci_write(host, AT91_MCI_IER, imr);
181
182 /* make sure sdio interrupts will fire */
183 at91_mci_read(host, AT91_MCI_SR);
184
185 local_irq_restore(flags);
186}
187
188static void at91_timeout_timer(unsigned long data)
189{
190 struct at91mci_host *host;
191
192 host = (struct at91mci_host *)data;
193
194 if (host->request) {
195 dev_err(host->mmc->parent, "Timeout waiting end of packet\n");
196
197 if (host->cmd && host->cmd->data) {
198 host->cmd->data->error = -ETIMEDOUT;
199 } else {
200 if (host->cmd)
201 host->cmd->error = -ETIMEDOUT;
202 else
203 host->request->cmd->error = -ETIMEDOUT;
204 }
205
206 at91_reset_host(host);
207 mmc_request_done(host->mmc, host->request);
208 }
209}
210
211/*
212 * Copy from sg to a dma block - used for transfers
213 */
214static inline void at91_mci_sg_to_dma(struct at91mci_host *host, struct mmc_data *data)
215{
216 unsigned int len, i, size;
217 unsigned *dmabuf = host->buffer;
218
219 size = data->blksz * data->blocks;
220 len = data->sg_len;
221
222 /* MCI1 rev2xx Data Write Operation and number of bytes erratum */
223 if (at91mci_is_mci1rev2xx())
224 if (host->total_length == 12)
225 memset(dmabuf, 0, 12);
226
227 /*
228 * Just loop through all entries. Size might not
229 * be the entire list though so make sure that
230 * we do not transfer too much.
231 */
232 for (i = 0; i < len; i++) {
233 struct scatterlist *sg;
234 int amount;
235 unsigned int *sgbuffer;
236
237 sg = &data->sg[i];
238
239 sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
240 amount = min(size, sg->length);
241 size -= amount;
242
243 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */
244 int index;
245
246 for (index = 0; index < (amount / 4); index++)
247 *dmabuf++ = swab32(sgbuffer[index]);
248 } else {
249 char *tmpv = (char *)dmabuf;
250 memcpy(tmpv, sgbuffer, amount);
251 tmpv += amount;
252 dmabuf = (unsigned *)tmpv;
253 }
254
255 kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
256
257 if (size == 0)
258 break;
259 }
260
261 /*
262 * Check that we didn't get a request to transfer
263 * more data than can fit into the SG list.
264 */
265 BUG_ON(size != 0);
266}
267
268/*
269 * Handle after a dma read
270 */
271static void at91_mci_post_dma_read(struct at91mci_host *host)
272{
273 struct mmc_command *cmd;
274 struct mmc_data *data;
275 unsigned int len, i, size;
276 unsigned *dmabuf = host->buffer;
277
278 pr_debug("post dma read\n");
279
280 cmd = host->cmd;
281 if (!cmd) {
282 pr_debug("no command\n");
283 return;
284 }
285
286 data = cmd->data;
287 if (!data) {
288 pr_debug("no data\n");
289 return;
290 }
291
292 size = data->blksz * data->blocks;
293 len = data->sg_len;
294
295 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_ENDRX);
296 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_RXBUFF);
297
298 for (i = 0; i < len; i++) {
299 struct scatterlist *sg;
300 int amount;
301 unsigned int *sgbuffer;
302
303 sg = &data->sg[i];
304
305 sgbuffer = kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
306 amount = min(size, sg->length);
307 size -= amount;
308
309 if (cpu_is_at91rm9200()) { /* AT91RM9200 errata */
310 int index;
311 for (index = 0; index < (amount / 4); index++)
312 sgbuffer[index] = swab32(*dmabuf++);
313 } else {
314 char *tmpv = (char *)dmabuf;
315 memcpy(sgbuffer, tmpv, amount);
316 tmpv += amount;
317 dmabuf = (unsigned *)tmpv;
318 }
319
320 flush_kernel_dcache_page(sg_page(sg));
321 kunmap_atomic(sgbuffer, KM_BIO_SRC_IRQ);
322 data->bytes_xfered += amount;
323 if (size == 0)
324 break;
325 }
326
327 pr_debug("post dma read done\n");
328}
329
330/*
331 * Handle transmitted data
332 */
333static void at91_mci_handle_transmitted(struct at91mci_host *host)
334{
335 struct mmc_command *cmd;
336 struct mmc_data *data;
337
338 pr_debug("Handling the transmit\n");
339
340 /* Disable the transfer */
341 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
342
343 /* Now wait for cmd ready */
344 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_TXBUFE);
345
346 cmd = host->cmd;
347 if (!cmd) return;
348
349 data = cmd->data;
350 if (!data) return;
351
352 if (cmd->data->blocks > 1) {
353 pr_debug("multiple write : wait for BLKE...\n");
354 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_BLKE);
355 } else
356 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
357}
358
359/*
360 * Update bytes tranfered count during a write operation
361 */
362static void at91_mci_update_bytes_xfered(struct at91mci_host *host)
363{
364 struct mmc_data *data;
365
366 /* always deal with the effective request (and not the current cmd) */
367
368 if (host->request->cmd && host->request->cmd->error != 0)
369 return;
370
371 if (host->request->data) {
372 data = host->request->data;
373 if (data->flags & MMC_DATA_WRITE) {
374 /* card is in IDLE mode now */
375 pr_debug("-> bytes_xfered %d, total_length = %d\n",
376 data->bytes_xfered, host->total_length);
377 data->bytes_xfered = data->blksz * data->blocks;
378 }
379 }
380}
381
382
383/*Handle after command sent ready*/
384static int at91_mci_handle_cmdrdy(struct at91mci_host *host)
385{
386 if (!host->cmd)
387 return 1;
388 else if (!host->cmd->data) {
389 if (host->flags & FL_SENT_STOP) {
390 /*After multi block write, we must wait for NOTBUSY*/
391 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
392 } else return 1;
393 } else if (host->cmd->data->flags & MMC_DATA_WRITE) {
394 /*After sendding multi-block-write command, start DMA transfer*/
395 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_TXBUFE | AT91_MCI_BLKE);
396 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
397 }
398
399 /* command not completed, have to wait */
400 return 0;
401}
402
403
404/*
405 * Enable the controller
406 */
407static void at91_mci_enable(struct at91mci_host *host)
408{
409 unsigned int mr;
410
411 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
412 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
413 at91_mci_write(host, AT91_MCI_DTOR, AT91_MCI_DTOMUL_1M | AT91_MCI_DTOCYC);
414 mr = AT91_MCI_PDCMODE | 0x34a;
415
416 if (at91mci_is_mci1rev2xx())
417 mr |= AT91_MCI_RDPROOF | AT91_MCI_WRPROOF;
418
419 at91_mci_write(host, AT91_MCI_MR, mr);
420
421 /* use Slot A or B (only one at same time) */
422 at91_mci_write(host, AT91_MCI_SDCR, host->board->slot_b);
423}
424
425/*
426 * Disable the controller
427 */
428static void at91_mci_disable(struct at91mci_host *host)
429{
430 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
431}
432
433/*
434 * Send a command
435 */
436static void at91_mci_send_command(struct at91mci_host *host, struct mmc_command *cmd)
437{
438 unsigned int cmdr, mr;
439 unsigned int block_length;
440 struct mmc_data *data = cmd->data;
441
442 unsigned int blocks;
443 unsigned int ier = 0;
444
445 host->cmd = cmd;
446
447 /* Needed for leaving busy state before CMD1 */
448 if ((at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_RTOE) && (cmd->opcode == 1)) {
449 pr_debug("Clearing timeout\n");
450 at91_mci_write(host, AT91_MCI_ARGR, 0);
451 at91_mci_write(host, AT91_MCI_CMDR, AT91_MCI_OPDCMD);
452 while (!(at91_mci_read(host, AT91_MCI_SR) & AT91_MCI_CMDRDY)) {
453 /* spin */
454 pr_debug("Clearing: SR = %08X\n", at91_mci_read(host, AT91_MCI_SR));
455 }
456 }
457
458 cmdr = cmd->opcode;
459
460 if (mmc_resp_type(cmd) == MMC_RSP_NONE)
461 cmdr |= AT91_MCI_RSPTYP_NONE;
462 else {
463 /* if a response is expected then allow maximum response latancy */
464 cmdr |= AT91_MCI_MAXLAT;
465 /* set 136 bit response for R2, 48 bit response otherwise */
466 if (mmc_resp_type(cmd) == MMC_RSP_R2)
467 cmdr |= AT91_MCI_RSPTYP_136;
468 else
469 cmdr |= AT91_MCI_RSPTYP_48;
470 }
471
472 if (data) {
473
474 if (cpu_is_at91rm9200() || cpu_is_at91sam9261()) {
475 if (data->blksz & 0x3) {
476 pr_debug("Unsupported block size\n");
477 cmd->error = -EINVAL;
478 mmc_request_done(host->mmc, host->request);
479 return;
480 }
481 if (data->flags & MMC_DATA_STREAM) {
482 pr_debug("Stream commands not supported\n");
483 cmd->error = -EINVAL;
484 mmc_request_done(host->mmc, host->request);
485 return;
486 }
487 }
488
489 block_length = data->blksz;
490 blocks = data->blocks;
491
492 /* always set data start - also set direction flag for read */
493 if (data->flags & MMC_DATA_READ)
494 cmdr |= (AT91_MCI_TRDIR | AT91_MCI_TRCMD_START);
495 else if (data->flags & MMC_DATA_WRITE)
496 cmdr |= AT91_MCI_TRCMD_START;
497
498 if (cmd->opcode == SD_IO_RW_EXTENDED) {
499 cmdr |= AT91_MCI_TRTYP_SDIO_BLOCK;
500 } else {
501 if (data->flags & MMC_DATA_STREAM)
502 cmdr |= AT91_MCI_TRTYP_STREAM;
503 if (data->blocks > 1)
504 cmdr |= AT91_MCI_TRTYP_MULTIPLE;
505 }
506 }
507 else {
508 block_length = 0;
509 blocks = 0;
510 }
511
512 if (host->flags & FL_SENT_STOP)
513 cmdr |= AT91_MCI_TRCMD_STOP;
514
515 if (host->bus_mode == MMC_BUSMODE_OPENDRAIN)
516 cmdr |= AT91_MCI_OPDCMD;
517
518 /*
519 * Set the arguments and send the command
520 */
521 pr_debug("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n",
522 cmd->opcode, cmdr, cmd->arg, blocks, block_length, at91_mci_read(host, AT91_MCI_MR));
523
524 if (!data) {
525 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS | ATMEL_PDC_RXTDIS);
526 at91_mci_write(host, ATMEL_PDC_RPR, 0);
527 at91_mci_write(host, ATMEL_PDC_RCR, 0);
528 at91_mci_write(host, ATMEL_PDC_RNPR, 0);
529 at91_mci_write(host, ATMEL_PDC_RNCR, 0);
530 at91_mci_write(host, ATMEL_PDC_TPR, 0);
531 at91_mci_write(host, ATMEL_PDC_TCR, 0);
532 at91_mci_write(host, ATMEL_PDC_TNPR, 0);
533 at91_mci_write(host, ATMEL_PDC_TNCR, 0);
534 ier = AT91_MCI_CMDRDY;
535 } else {
536 /* zero block length and PDC mode */
537 mr = at91_mci_read(host, AT91_MCI_MR) & 0x5fff;
538 mr |= (data->blksz & 0x3) ? AT91_MCI_PDCFBYTE : 0;
539 mr |= (block_length << 16);
540 mr |= AT91_MCI_PDCMODE;
541 at91_mci_write(host, AT91_MCI_MR, mr);
542
543 if (!(cpu_is_at91rm9200() || cpu_is_at91sam9261()))
544 at91_mci_write(host, AT91_MCI_BLKR,
545 AT91_MCI_BLKR_BCNT(blocks) |
546 AT91_MCI_BLKR_BLKLEN(block_length));
547
548 /*
549 * Disable the PDC controller
550 */
551 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
552
553 if (cmdr & AT91_MCI_TRCMD_START) {
554 data->bytes_xfered = 0;
555 host->transfer_index = 0;
556 host->in_use_index = 0;
557 if (cmdr & AT91_MCI_TRDIR) {
558 /*
559 * Handle a read
560 */
561 host->total_length = 0;
562
563 at91_mci_write(host, ATMEL_PDC_RPR, host->physical_address);
564 at91_mci_write(host, ATMEL_PDC_RCR, (data->blksz & 0x3) ?
565 (blocks * block_length) : (blocks * block_length) / 4);
566 at91_mci_write(host, ATMEL_PDC_RNPR, 0);
567 at91_mci_write(host, ATMEL_PDC_RNCR, 0);
568
569 ier = AT91_MCI_ENDRX /* | AT91_MCI_RXBUFF */;
570 }
571 else {
572 /*
573 * Handle a write
574 */
575 host->total_length = block_length * blocks;
576 /*
577 * MCI1 rev2xx Data Write Operation and
578 * number of bytes erratum
579 */
580 if (at91mci_is_mci1rev2xx())
581 if (host->total_length < 12)
582 host->total_length = 12;
583
584 at91_mci_sg_to_dma(host, data);
585
586 pr_debug("Transmitting %d bytes\n", host->total_length);
587
588 at91_mci_write(host, ATMEL_PDC_TPR, host->physical_address);
589 at91_mci_write(host, ATMEL_PDC_TCR, (data->blksz & 0x3) ?
590 host->total_length : host->total_length / 4);
591
592 ier = AT91_MCI_CMDRDY;
593 }
594 }
595 }
596
597 /*
598 * Send the command and then enable the PDC - not the other way round as
599 * the data sheet says
600 */
601
602 at91_mci_write(host, AT91_MCI_ARGR, cmd->arg);
603 at91_mci_write(host, AT91_MCI_CMDR, cmdr);
604
605 if (cmdr & AT91_MCI_TRCMD_START) {
606 if (cmdr & AT91_MCI_TRDIR)
607 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
608 }
609
610 /* Enable selected interrupts */
611 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_ERRORS | ier);
612}
613
614/*
615 * Process the next step in the request
616 */
617static void at91_mci_process_next(struct at91mci_host *host)
618{
619 if (!(host->flags & FL_SENT_COMMAND)) {
620 host->flags |= FL_SENT_COMMAND;
621 at91_mci_send_command(host, host->request->cmd);
622 }
623 else if ((!(host->flags & FL_SENT_STOP)) && host->request->stop) {
624 host->flags |= FL_SENT_STOP;
625 at91_mci_send_command(host, host->request->stop);
626 } else {
627 del_timer(&host->timer);
628 /* the at91rm9200 mci controller hangs after some transfers,
629 * and the workaround is to reset it after each transfer.
630 */
631 if (cpu_is_at91rm9200())
632 at91_reset_host(host);
633 mmc_request_done(host->mmc, host->request);
634 }
635}
636
637/*
638 * Handle a command that has been completed
639 */
640static void at91_mci_completed_command(struct at91mci_host *host, unsigned int status)
641{
642 struct mmc_command *cmd = host->cmd;
643 struct mmc_data *data = cmd->data;
644
645 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
646
647 cmd->resp[0] = at91_mci_read(host, AT91_MCI_RSPR(0));
648 cmd->resp[1] = at91_mci_read(host, AT91_MCI_RSPR(1));
649 cmd->resp[2] = at91_mci_read(host, AT91_MCI_RSPR(2));
650 cmd->resp[3] = at91_mci_read(host, AT91_MCI_RSPR(3));
651
652 pr_debug("Status = %08X/%08x [%08X %08X %08X %08X]\n",
653 status, at91_mci_read(host, AT91_MCI_SR),
654 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
655
656 if (status & AT91_MCI_ERRORS) {
657 if ((status & AT91_MCI_RCRCE) && !(mmc_resp_type(cmd) & MMC_RSP_CRC)) {
658 cmd->error = 0;
659 }
660 else {
661 if (status & (AT91_MCI_DTOE | AT91_MCI_DCRCE)) {
662 if (data) {
663 if (status & AT91_MCI_DTOE)
664 data->error = -ETIMEDOUT;
665 else if (status & AT91_MCI_DCRCE)
666 data->error = -EILSEQ;
667 }
668 } else {
669 if (status & AT91_MCI_RTOE)
670 cmd->error = -ETIMEDOUT;
671 else if (status & AT91_MCI_RCRCE)
672 cmd->error = -EILSEQ;
673 else
674 cmd->error = -EIO;
675 }
676
677 pr_debug("Error detected and set to %d/%d (cmd = %d, retries = %d)\n",
678 cmd->error, data ? data->error : 0,
679 cmd->opcode, cmd->retries);
680 }
681 }
682 else
683 cmd->error = 0;
684
685 at91_mci_process_next(host);
686}
687
688/*
689 * Handle an MMC request
690 */
691static void at91_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
692{
693 struct at91mci_host *host = mmc_priv(mmc);
694 host->request = mrq;
695 host->flags = 0;
696
697 /* more than 1s timeout needed with slow SD cards */
698 mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
699
700 at91_mci_process_next(host);
701}
702
703/*
704 * Set the IOS
705 */
706static void at91_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
707{
708 int clkdiv;
709 struct at91mci_host *host = mmc_priv(mmc);
710 unsigned long at91_master_clock = clk_get_rate(host->mci_clk);
711
712 host->bus_mode = ios->bus_mode;
713
714 if (ios->clock == 0) {
715 /* Disable the MCI controller */
716 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS);
717 clkdiv = 0;
718 }
719 else {
720 /* Enable the MCI controller */
721 at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
722
723 if ((at91_master_clock % (ios->clock * 2)) == 0)
724 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1;
725 else
726 clkdiv = (at91_master_clock / ios->clock) / 2;
727
728 pr_debug("clkdiv = %d. mcck = %ld\n", clkdiv,
729 at91_master_clock / (2 * (clkdiv + 1)));
730 }
731 if (ios->bus_width == MMC_BUS_WIDTH_4 && host->board->wire4) {
732 pr_debug("MMC: Setting controller bus width to 4\n");
733 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) | AT91_MCI_SDCBUS);
734 }
735 else {
736 pr_debug("MMC: Setting controller bus width to 1\n");
737 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
738 }
739
740 /* Set the clock divider */
741 at91_mci_write(host, AT91_MCI_MR, (at91_mci_read(host, AT91_MCI_MR) & ~AT91_MCI_CLKDIV) | clkdiv);
742
743 /* maybe switch power to the card */
744 if (host->board->vcc_pin) {
745 switch (ios->power_mode) {
746 case MMC_POWER_OFF:
747 gpio_set_value(host->board->vcc_pin, 0);
748 break;
749 case MMC_POWER_UP:
750 gpio_set_value(host->board->vcc_pin, 1);
751 break;
752 case MMC_POWER_ON:
753 break;
754 default:
755 WARN_ON(1);
756 }
757 }
758}
759
760/*
761 * Handle an interrupt
762 */
763static irqreturn_t at91_mci_irq(int irq, void *devid)
764{
765 struct at91mci_host *host = devid;
766 int completed = 0;
767 unsigned int int_status, int_mask;
768
769 int_status = at91_mci_read(host, AT91_MCI_SR);
770 int_mask = at91_mci_read(host, AT91_MCI_IMR);
771
772 pr_debug("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask,
773 int_status & int_mask);
774
775 int_status = int_status & int_mask;
776
777 if (int_status & AT91_MCI_ERRORS) {
778 completed = 1;
779
780 if (int_status & AT91_MCI_UNRE)
781 pr_debug("MMC: Underrun error\n");
782 if (int_status & AT91_MCI_OVRE)
783 pr_debug("MMC: Overrun error\n");
784 if (int_status & AT91_MCI_DTOE)
785 pr_debug("MMC: Data timeout\n");
786 if (int_status & AT91_MCI_DCRCE)
787 pr_debug("MMC: CRC error in data\n");
788 if (int_status & AT91_MCI_RTOE)
789 pr_debug("MMC: Response timeout\n");
790 if (int_status & AT91_MCI_RENDE)
791 pr_debug("MMC: Response end bit error\n");
792 if (int_status & AT91_MCI_RCRCE)
793 pr_debug("MMC: Response CRC error\n");
794 if (int_status & AT91_MCI_RDIRE)
795 pr_debug("MMC: Response direction error\n");
796 if (int_status & AT91_MCI_RINDE)
797 pr_debug("MMC: Response index error\n");
798 } else {
799 /* Only continue processing if no errors */
800
801 if (int_status & AT91_MCI_TXBUFE) {
802 pr_debug("TX buffer empty\n");
803 at91_mci_handle_transmitted(host);
804 }
805
806 if (int_status & AT91_MCI_ENDRX) {
807 pr_debug("ENDRX\n");
808 at91_mci_post_dma_read(host);
809 }
810
811 if (int_status & AT91_MCI_RXBUFF) {
812 pr_debug("RX buffer full\n");
813 at91_mci_write(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
814 at91_mci_write(host, AT91_MCI_IDR, AT91_MCI_RXBUFF | AT91_MCI_ENDRX);
815 completed = 1;
816 }
817
818 if (int_status & AT91_MCI_ENDTX)
819 pr_debug("Transmit has ended\n");
820
821 if (int_status & AT91_MCI_NOTBUSY) {
822 pr_debug("Card is ready\n");
823 at91_mci_update_bytes_xfered(host);
824 completed = 1;
825 }
826
827 if (int_status & AT91_MCI_DTIP)
828 pr_debug("Data transfer in progress\n");
829
830 if (int_status & AT91_MCI_BLKE) {
831 pr_debug("Block transfer has ended\n");
832 if (host->request->data && host->request->data->blocks > 1) {
833 /* multi block write : complete multi write
834 * command and send stop */
835 completed = 1;
836 } else {
837 at91_mci_write(host, AT91_MCI_IER, AT91_MCI_NOTBUSY);
838 }
839 }
840
841 if (int_status & AT91_MCI_SDIOIRQA)
842 mmc_signal_sdio_irq(host->mmc);
843
844 if (int_status & AT91_MCI_SDIOIRQB)
845 mmc_signal_sdio_irq(host->mmc);
846
847 if (int_status & AT91_MCI_TXRDY)
848 pr_debug("Ready to transmit\n");
849
850 if (int_status & AT91_MCI_RXRDY)
851 pr_debug("Ready to receive\n");
852
853 if (int_status & AT91_MCI_CMDRDY) {
854 pr_debug("Command ready\n");
855 completed = at91_mci_handle_cmdrdy(host);
856 }
857 }
858
859 if (completed) {
860 pr_debug("Completed command\n");
861 at91_mci_write(host, AT91_MCI_IDR, 0xffffffff & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
862 at91_mci_completed_command(host, int_status);
863 } else
864 at91_mci_write(host, AT91_MCI_IDR, int_status & ~(AT91_MCI_SDIOIRQA | AT91_MCI_SDIOIRQB));
865
866 return IRQ_HANDLED;
867}
868
869static irqreturn_t at91_mmc_det_irq(int irq, void *_host)
870{
871 struct at91mci_host *host = _host;
872 int present = !gpio_get_value(irq_to_gpio(irq));
873
874 /*
875 * we expect this irq on both insert and remove,
876 * and use a short delay to debounce.
877 */
878 if (present != host->present) {
879 host->present = present;
880 pr_debug("%s: card %s\n", mmc_hostname(host->mmc),
881 present ? "insert" : "remove");
882 if (!present) {
883 pr_debug("****** Resetting SD-card bus width ******\n");
884 at91_mci_write(host, AT91_MCI_SDCR, at91_mci_read(host, AT91_MCI_SDCR) & ~AT91_MCI_SDCBUS);
885 }
886 /* 0.5s needed because of early card detect switch firing */
887 mmc_detect_change(host->mmc, msecs_to_jiffies(500));
888 }
889 return IRQ_HANDLED;
890}
891
892static int at91_mci_get_ro(struct mmc_host *mmc)
893{
894 struct at91mci_host *host = mmc_priv(mmc);
895
896 if (host->board->wp_pin)
897 return !!gpio_get_value(host->board->wp_pin);
898 /*
899 * Board doesn't support read only detection; let the mmc core
900 * decide what to do.
901 */
902 return -ENOSYS;
903}
904
905static void at91_mci_enable_sdio_irq(struct mmc_host *mmc, int enable)
906{
907 struct at91mci_host *host = mmc_priv(mmc);
908
909 pr_debug("%s: sdio_irq %c : %s\n", mmc_hostname(host->mmc),
910 host->board->slot_b ? 'B':'A', enable ? "enable" : "disable");
911 at91_mci_write(host, enable ? AT91_MCI_IER : AT91_MCI_IDR,
912 host->board->slot_b ? AT91_MCI_SDIOIRQB : AT91_MCI_SDIOIRQA);
913
914}
915
916static const struct mmc_host_ops at91_mci_ops = {
917 .request = at91_mci_request,
918 .set_ios = at91_mci_set_ios,
919 .get_ro = at91_mci_get_ro,
920 .enable_sdio_irq = at91_mci_enable_sdio_irq,
921};
922
923/*
924 * Probe for the device
925 */
926static int __init at91_mci_probe(struct platform_device *pdev)
927{
928 struct mmc_host *mmc;
929 struct at91mci_host *host;
930 struct resource *res;
931 int ret;
932
933 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
934 if (!res)
935 return -ENXIO;
936
937 if (!request_mem_region(res->start, resource_size(res), DRIVER_NAME))
938 return -EBUSY;
939
940 mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev);
941 if (!mmc) {
942 ret = -ENOMEM;
943 dev_dbg(&pdev->dev, "couldn't allocate mmc host\n");
944 goto fail6;
945 }
946
947 mmc->ops = &at91_mci_ops;
948 mmc->f_min = 375000;
949 mmc->f_max = 25000000;
950 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
951 mmc->caps = 0;
952
953 mmc->max_blk_size = MCI_MAXBLKSIZE;
954 mmc->max_blk_count = MCI_BLKATONCE;
955 mmc->max_req_size = MCI_BUFSIZE;
956 mmc->max_segs = MCI_BLKATONCE;
957 mmc->max_seg_size = MCI_BUFSIZE;
958
959 host = mmc_priv(mmc);
960 host->mmc = mmc;
961 host->bus_mode = 0;
962 host->board = pdev->dev.platform_data;
963 if (host->board->wire4) {
964 if (at91mci_is_mci1rev2xx())
965 mmc->caps |= MMC_CAP_4_BIT_DATA;
966 else
967 dev_warn(&pdev->dev, "4 wire bus mode not supported"
968 " - using 1 wire\n");
969 }
970
971 host->buffer = dma_alloc_coherent(&pdev->dev, MCI_BUFSIZE,
972 &host->physical_address, GFP_KERNEL);
973 if (!host->buffer) {
974 ret = -ENOMEM;
975 dev_err(&pdev->dev, "Can't allocate transmit buffer\n");
976 goto fail5;
977 }
978
979 /* Add SDIO capability when available */
980 if (at91mci_is_mci1rev2xx()) {
981 /* at91mci MCI1 rev2xx sdio interrupt erratum */
982 if (host->board->wire4 || !host->board->slot_b)
983 mmc->caps |= MMC_CAP_SDIO_IRQ;
984 }
985
986 /*
987 * Reserve GPIOs ... board init code makes sure these pins are set
988 * up as GPIOs with the right direction (input, except for vcc)
989 */
990 if (host->board->det_pin) {
991 ret = gpio_request(host->board->det_pin, "mmc_detect");
992 if (ret < 0) {
993 dev_dbg(&pdev->dev, "couldn't claim card detect pin\n");
994 goto fail4b;
995 }
996 }
997 if (host->board->wp_pin) {
998 ret = gpio_request(host->board->wp_pin, "mmc_wp");
999 if (ret < 0) {
1000 dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n");
1001 goto fail4;
1002 }
1003 }
1004 if (host->board->vcc_pin) {
1005 ret = gpio_request(host->board->vcc_pin, "mmc_vcc");
1006 if (ret < 0) {
1007 dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n");
1008 goto fail3;
1009 }
1010 }
1011
1012 /*
1013 * Get Clock
1014 */
1015 host->mci_clk = clk_get(&pdev->dev, "mci_clk");
1016 if (IS_ERR(host->mci_clk)) {
1017 ret = -ENODEV;
1018 dev_dbg(&pdev->dev, "no mci_clk?\n");
1019 goto fail2;
1020 }
1021
1022 /*
1023 * Map I/O region
1024 */
1025 host->baseaddr = ioremap(res->start, resource_size(res));
1026 if (!host->baseaddr) {
1027 ret = -ENOMEM;
1028 goto fail1;
1029 }
1030
1031 /*
1032 * Reset hardware
1033 */
1034 clk_enable(host->mci_clk); /* Enable the peripheral clock */
1035 at91_mci_disable(host);
1036 at91_mci_enable(host);
1037
1038 /*
1039 * Allocate the MCI interrupt
1040 */
1041 host->irq = platform_get_irq(pdev, 0);
1042 ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED,
1043 mmc_hostname(mmc), host);
1044 if (ret) {
1045 dev_dbg(&pdev->dev, "request MCI interrupt failed\n");
1046 goto fail0;
1047 }
1048
1049 setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host);
1050
1051 platform_set_drvdata(pdev, mmc);
1052
1053 /*
1054 * Add host to MMC layer
1055 */
1056 if (host->board->det_pin) {
1057 host->present = !gpio_get_value(host->board->det_pin);
1058 }
1059 else
1060 host->present = -1;
1061
1062 mmc_add_host(mmc);
1063
1064 /*
1065 * monitor card insertion/removal if we can
1066 */
1067 if (host->board->det_pin) {
1068 ret = request_irq(gpio_to_irq(host->board->det_pin),
1069 at91_mmc_det_irq, 0, mmc_hostname(mmc), host);
1070 if (ret)
1071 dev_warn(&pdev->dev, "request MMC detect irq failed\n");
1072 else
1073 device_init_wakeup(&pdev->dev, 1);
1074 }
1075
1076 pr_debug("Added MCI driver\n");
1077
1078 return 0;
1079
1080fail0:
1081 clk_disable(host->mci_clk);
1082 iounmap(host->baseaddr);
1083fail1:
1084 clk_put(host->mci_clk);
1085fail2:
1086 if (host->board->vcc_pin)
1087 gpio_free(host->board->vcc_pin);
1088fail3:
1089 if (host->board->wp_pin)
1090 gpio_free(host->board->wp_pin);
1091fail4:
1092 if (host->board->det_pin)
1093 gpio_free(host->board->det_pin);
1094fail4b:
1095 if (host->buffer)
1096 dma_free_coherent(&pdev->dev, MCI_BUFSIZE,
1097 host->buffer, host->physical_address);
1098fail5:
1099 mmc_free_host(mmc);
1100fail6:
1101 release_mem_region(res->start, resource_size(res));
1102 dev_err(&pdev->dev, "probe failed, err %d\n", ret);
1103 return ret;
1104}
1105
1106/*
1107 * Remove a device
1108 */
1109static int __exit at91_mci_remove(struct platform_device *pdev)
1110{
1111 struct mmc_host *mmc = platform_get_drvdata(pdev);
1112 struct at91mci_host *host;
1113 struct resource *res;
1114
1115 if (!mmc)
1116 return -1;
1117
1118 host = mmc_priv(mmc);
1119
1120 if (host->buffer)
1121 dma_free_coherent(&pdev->dev, MCI_BUFSIZE,
1122 host->buffer, host->physical_address);
1123
1124 if (host->board->det_pin) {
1125 if (device_can_wakeup(&pdev->dev))
1126 free_irq(gpio_to_irq(host->board->det_pin), host);
1127 device_init_wakeup(&pdev->dev, 0);
1128 gpio_free(host->board->det_pin);
1129 }
1130
1131 at91_mci_disable(host);
1132 del_timer_sync(&host->timer);
1133 mmc_remove_host(mmc);
1134 free_irq(host->irq, host);
1135
1136 clk_disable(host->mci_clk); /* Disable the peripheral clock */
1137 clk_put(host->mci_clk);
1138
1139 if (host->board->vcc_pin)
1140 gpio_free(host->board->vcc_pin);
1141 if (host->board->wp_pin)
1142 gpio_free(host->board->wp_pin);
1143
1144 iounmap(host->baseaddr);
1145 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1146 release_mem_region(res->start, resource_size(res));
1147
1148 mmc_free_host(mmc);
1149 platform_set_drvdata(pdev, NULL);
1150 pr_debug("MCI Removed\n");
1151
1152 return 0;
1153}
1154
1155#ifdef CONFIG_PM
1156static int at91_mci_suspend(struct platform_device *pdev, pm_message_t state)
1157{
1158 struct mmc_host *mmc = platform_get_drvdata(pdev);
1159 struct at91mci_host *host = mmc_priv(mmc);
1160 int ret = 0;
1161
1162 if (host->board->det_pin && device_may_wakeup(&pdev->dev))
1163 enable_irq_wake(host->board->det_pin);
1164
1165 if (mmc)
1166 ret = mmc_suspend_host(mmc);
1167
1168 return ret;
1169}
1170
1171static int at91_mci_resume(struct platform_device *pdev)
1172{
1173 struct mmc_host *mmc = platform_get_drvdata(pdev);
1174 struct at91mci_host *host = mmc_priv(mmc);
1175 int ret = 0;
1176
1177 if (host->board->det_pin && device_may_wakeup(&pdev->dev))
1178 disable_irq_wake(host->board->det_pin);
1179
1180 if (mmc)
1181 ret = mmc_resume_host(mmc);
1182
1183 return ret;
1184}
1185#else
1186#define at91_mci_suspend NULL
1187#define at91_mci_resume NULL
1188#endif
1189
1190static struct platform_driver at91_mci_driver = {
1191 .remove = __exit_p(at91_mci_remove),
1192 .suspend = at91_mci_suspend,
1193 .resume = at91_mci_resume,
1194 .driver = {
1195 .name = DRIVER_NAME,
1196 .owner = THIS_MODULE,
1197 },
1198};
1199
1200static int __init at91_mci_init(void)
1201{
1202 return platform_driver_probe(&at91_mci_driver, at91_mci_probe);
1203}
1204
1205static void __exit at91_mci_exit(void)
1206{
1207 platform_driver_unregister(&at91_mci_driver);
1208}
1209
1210module_init(at91_mci_init);
1211module_exit(at91_mci_exit);
1212
1213MODULE_DESCRIPTION("AT91 Multimedia Card Interface driver");
1214MODULE_AUTHOR("Nick Randell");
1215MODULE_LICENSE("GPL");
1216MODULE_ALIAS("platform:at91_mci");
diff --git a/drivers/mmc/host/at91_mci.h b/drivers/mmc/host/at91_mci.h
new file mode 100644
index 00000000000..eec3a6b1c2b
--- /dev/null
+++ b/drivers/mmc/host/at91_mci.h
@@ -0,0 +1,115 @@
1/*
2 * drivers/mmc/host/at91_mci.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * MultiMedia Card Interface (MCI) registers.
8 * Based on AT91RM9200 datasheet revision F.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_MCI_H
17#define AT91_MCI_H
18
19#define AT91_MCI_CR 0x00 /* Control Register */
20#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
21#define AT91_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */
22#define AT91_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */
23#define AT91_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */
24#define AT91_MCI_SWRST (1 << 7) /* Software Reset */
25
26#define AT91_MCI_MR 0x04 /* Mode Register */
27#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
28#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
29#define AT91_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */
30#define AT91_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */
31#define AT91_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */
32#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
33#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
34#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
35
36#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */
37#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
38#define AT91_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */
39#define AT91_MCI_DTOMUL_1 (0 << 4)
40#define AT91_MCI_DTOMUL_16 (1 << 4)
41#define AT91_MCI_DTOMUL_128 (2 << 4)
42#define AT91_MCI_DTOMUL_256 (3 << 4)
43#define AT91_MCI_DTOMUL_1K (4 << 4)
44#define AT91_MCI_DTOMUL_4K (5 << 4)
45#define AT91_MCI_DTOMUL_64K (6 << 4)
46#define AT91_MCI_DTOMUL_1M (7 << 4)
47
48#define AT91_MCI_SDCR 0x0c /* SD Card Register */
49#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */
50#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
51
52#define AT91_MCI_ARGR 0x10 /* Argument Register */
53
54#define AT91_MCI_CMDR 0x14 /* Command Register */
55#define AT91_MCI_CMDNB (0x3f << 0) /* Command Number */
56#define AT91_MCI_RSPTYP (3 << 6) /* Response Type */
57#define AT91_MCI_RSPTYP_NONE (0 << 6)
58#define AT91_MCI_RSPTYP_48 (1 << 6)
59#define AT91_MCI_RSPTYP_136 (2 << 6)
60#define AT91_MCI_SPCMD (7 << 8) /* Special Command */
61#define AT91_MCI_SPCMD_NONE (0 << 8)
62#define AT91_MCI_SPCMD_INIT (1 << 8)
63#define AT91_MCI_SPCMD_SYNC (2 << 8)
64#define AT91_MCI_SPCMD_ICMD (4 << 8)
65#define AT91_MCI_SPCMD_IRESP (5 << 8)
66#define AT91_MCI_OPDCMD (1 << 11) /* Open Drain Command */
67#define AT91_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */
68#define AT91_MCI_TRCMD (3 << 16) /* Transfer Command */
69#define AT91_MCI_TRCMD_NONE (0 << 16)
70#define AT91_MCI_TRCMD_START (1 << 16)
71#define AT91_MCI_TRCMD_STOP (2 << 16)
72#define AT91_MCI_TRDIR (1 << 18) /* Transfer Direction */
73#define AT91_MCI_TRTYP (3 << 19) /* Transfer Type */
74#define AT91_MCI_TRTYP_BLOCK (0 << 19)
75#define AT91_MCI_TRTYP_MULTIPLE (1 << 19)
76#define AT91_MCI_TRTYP_STREAM (2 << 19)
77#define AT91_MCI_TRTYP_SDIO_BYTE (4 << 19)
78#define AT91_MCI_TRTYP_SDIO_BLOCK (5 << 19)
79
80#define AT91_MCI_BLKR 0x18 /* Block Register */
81#define AT91_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */
82#define AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block length */
83
84#define AT91_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */
85#define AT91_MCR_RDR 0x30 /* Receive Data Register */
86#define AT91_MCR_TDR 0x34 /* Transmit Data Register */
87
88#define AT91_MCI_SR 0x40 /* Status Register */
89#define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */
90#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */
91#define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */
92#define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */
93#define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */
94#define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */
95#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */
96#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */
97#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */
98#define AT91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B */
99#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */
100#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */
101#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
102#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */
103#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */
104#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */
105#define AT91_MCI_RTOE (1 << 20) /* Response Time-out Error */
106#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */
107#define AT91_MCI_DTOE (1 << 22) /* Data Time-out Error */
108#define AT91_MCI_OVRE (1 << 30) /* Overrun */
109#define AT91_MCI_UNRE (1 << 31) /* Underrun */
110
111#define AT91_MCI_IER 0x44 /* Interrupt Enable Register */
112#define AT91_MCI_IDR 0x48 /* Interrupt Disable Register */
113#define AT91_MCI_IMR 0x4c /* Interrupt Mask Register */
114
115#endif
diff --git a/drivers/mmc/host/imxmmc.c b/drivers/mmc/host/imxmmc.c
new file mode 100644
index 00000000000..881f7ba545a
--- /dev/null
+++ b/drivers/mmc/host/imxmmc.c
@@ -0,0 +1,1169 @@
1/*
2 * linux/drivers/mmc/host/imxmmc.c - Motorola i.MX MMCI driver
3 *
4 * Copyright (C) 2004 Sascha Hauer, Pengutronix <sascha@saschahauer.de>
5 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
6 *
7 * derived from pxamci.c by Russell King
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/ioport.h>
18#include <linux/platform_device.h>
19#include <linux/interrupt.h>
20#include <linux/blkdev.h>
21#include <linux/dma-mapping.h>
22#include <linux/mmc/host.h>
23#include <linux/mmc/card.h>
24#include <linux/delay.h>
25#include <linux/clk.h>
26#include <linux/io.h>
27
28#include <asm/dma.h>
29#include <asm/irq.h>
30#include <asm/sizes.h>
31#include <mach/mmc.h>
32#include <mach/imx-dma.h>
33
34#include "imxmmc.h"
35
36#define DRIVER_NAME "imx-mmc"
37
38#define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
39 INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
40 INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
41
42struct imxmci_host {
43 struct mmc_host *mmc;
44 spinlock_t lock;
45 struct resource *res;
46 void __iomem *base;
47 int irq;
48 imx_dmach_t dma;
49 volatile unsigned int imask;
50 unsigned int power_mode;
51 unsigned int present;
52 struct imxmmc_platform_data *pdata;
53
54 struct mmc_request *req;
55 struct mmc_command *cmd;
56 struct mmc_data *data;
57
58 struct timer_list timer;
59 struct tasklet_struct tasklet;
60 unsigned int status_reg;
61 unsigned long pending_events;
62 /* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */
63 u16 *data_ptr;
64 unsigned int data_cnt;
65 atomic_t stuck_timeout;
66
67 unsigned int dma_nents;
68 unsigned int dma_size;
69 unsigned int dma_dir;
70 int dma_allocated;
71
72 unsigned char actual_bus_width;
73
74 int prev_cmd_code;
75
76 struct clk *clk;
77};
78
79#define IMXMCI_PEND_IRQ_b 0
80#define IMXMCI_PEND_DMA_END_b 1
81#define IMXMCI_PEND_DMA_ERR_b 2
82#define IMXMCI_PEND_WAIT_RESP_b 3
83#define IMXMCI_PEND_DMA_DATA_b 4
84#define IMXMCI_PEND_CPU_DATA_b 5
85#define IMXMCI_PEND_CARD_XCHG_b 6
86#define IMXMCI_PEND_SET_INIT_b 7
87#define IMXMCI_PEND_STARTED_b 8
88
89#define IMXMCI_PEND_IRQ_m (1 << IMXMCI_PEND_IRQ_b)
90#define IMXMCI_PEND_DMA_END_m (1 << IMXMCI_PEND_DMA_END_b)
91#define IMXMCI_PEND_DMA_ERR_m (1 << IMXMCI_PEND_DMA_ERR_b)
92#define IMXMCI_PEND_WAIT_RESP_m (1 << IMXMCI_PEND_WAIT_RESP_b)
93#define IMXMCI_PEND_DMA_DATA_m (1 << IMXMCI_PEND_DMA_DATA_b)
94#define IMXMCI_PEND_CPU_DATA_m (1 << IMXMCI_PEND_CPU_DATA_b)
95#define IMXMCI_PEND_CARD_XCHG_m (1 << IMXMCI_PEND_CARD_XCHG_b)
96#define IMXMCI_PEND_SET_INIT_m (1 << IMXMCI_PEND_SET_INIT_b)
97#define IMXMCI_PEND_STARTED_m (1 << IMXMCI_PEND_STARTED_b)
98
99static void imxmci_stop_clock(struct imxmci_host *host)
100{
101 int i = 0;
102 u16 reg;
103
104 reg = readw(host->base + MMC_REG_STR_STP_CLK);
105 writew(reg & ~STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
106 while (i < 0x1000) {
107 if (!(i & 0x7f)) {
108 reg = readw(host->base + MMC_REG_STR_STP_CLK);
109 writew(reg | STR_STP_CLK_STOP_CLK,
110 host->base + MMC_REG_STR_STP_CLK);
111 }
112
113 reg = readw(host->base + MMC_REG_STATUS);
114 if (!(reg & STATUS_CARD_BUS_CLK_RUN)) {
115 /* Check twice before cut */
116 reg = readw(host->base + MMC_REG_STATUS);
117 if (!(reg & STATUS_CARD_BUS_CLK_RUN))
118 return;
119 }
120
121 i++;
122 }
123 dev_dbg(mmc_dev(host->mmc), "imxmci_stop_clock blocked, no luck\n");
124}
125
126static int imxmci_start_clock(struct imxmci_host *host)
127{
128 unsigned int trials = 0;
129 unsigned int delay_limit = 128;
130 unsigned long flags;
131 u16 reg;
132
133 reg = readw(host->base + MMC_REG_STR_STP_CLK);
134 writew(reg & ~STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
135
136 clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
137
138 /*
139 * Command start of the clock, this usually succeeds in less
140 * then 6 delay loops, but during card detection (low clockrate)
141 * it takes up to 5000 delay loops and sometimes fails for the first time
142 */
143 reg = readw(host->base + MMC_REG_STR_STP_CLK);
144 writew(reg | STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
145
146 do {
147 unsigned int delay = delay_limit;
148
149 while (delay--) {
150 reg = readw(host->base + MMC_REG_STATUS);
151 if (reg & STATUS_CARD_BUS_CLK_RUN) {
152 /* Check twice before cut */
153 reg = readw(host->base + MMC_REG_STATUS);
154 if (reg & STATUS_CARD_BUS_CLK_RUN)
155 return 0;
156 }
157
158 if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
159 return 0;
160 }
161
162 local_irq_save(flags);
163 /*
164 * Ensure, that request is not doubled under all possible circumstances.
165 * It is possible, that cock running state is missed, because some other
166 * IRQ or schedule delays this function execution and the clocks has
167 * been already stopped by other means (response processing, SDHC HW)
168 */
169 if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) {
170 reg = readw(host->base + MMC_REG_STR_STP_CLK);
171 writew(reg | STR_STP_CLK_START_CLK,
172 host->base + MMC_REG_STR_STP_CLK);
173 }
174 local_irq_restore(flags);
175
176 } while (++trials < 256);
177
178 dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
179
180 return -1;
181}
182
183static void imxmci_softreset(struct imxmci_host *host)
184{
185 int i;
186
187 /* reset sequence */
188 writew(0x08, host->base + MMC_REG_STR_STP_CLK);
189 writew(0x0D, host->base + MMC_REG_STR_STP_CLK);
190
191 for (i = 0; i < 8; i++)
192 writew(0x05, host->base + MMC_REG_STR_STP_CLK);
193
194 writew(0xff, host->base + MMC_REG_RES_TO);
195 writew(512, host->base + MMC_REG_BLK_LEN);
196 writew(1, host->base + MMC_REG_NOB);
197}
198
199static int imxmci_busy_wait_for_status(struct imxmci_host *host,
200 unsigned int *pstat, unsigned int stat_mask,
201 int timeout, const char *where)
202{
203 int loops = 0;
204
205 while (!(*pstat & stat_mask)) {
206 loops += 2;
207 if (loops >= timeout) {
208 dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
209 where, *pstat, stat_mask);
210 return -1;
211 }
212 udelay(2);
213 *pstat |= readw(host->base + MMC_REG_STATUS);
214 }
215 if (!loops)
216 return 0;
217
218 /* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
219 if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000))
220 dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
221 loops, where, *pstat, stat_mask);
222 return loops;
223}
224
225static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
226{
227 unsigned int nob = data->blocks;
228 unsigned int blksz = data->blksz;
229 unsigned int datasz = nob * blksz;
230 int i;
231
232 if (data->flags & MMC_DATA_STREAM)
233 nob = 0xffff;
234
235 host->data = data;
236 data->bytes_xfered = 0;
237
238 writew(nob, host->base + MMC_REG_NOB);
239 writew(blksz, host->base + MMC_REG_BLK_LEN);
240
241 /*
242 * DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
243 * We are in big troubles for non-512 byte transfers according to note in the paragraph
244 * 20.6.7 of User Manual anyway, but we need to be able to transfer SCR at least.
245 * The situation is even more complex in reality. The SDHC in not able to handle wll
246 * partial FIFO fills and reads. The length has to be rounded up to burst size multiple.
247 * This is required for SCR read at least.
248 */
249 if (datasz < 512) {
250 host->dma_size = datasz;
251 if (data->flags & MMC_DATA_READ) {
252 host->dma_dir = DMA_FROM_DEVICE;
253
254 /* Hack to enable read SCR */
255 writew(1, host->base + MMC_REG_NOB);
256 writew(512, host->base + MMC_REG_BLK_LEN);
257 } else {
258 host->dma_dir = DMA_TO_DEVICE;
259 }
260
261 /* Convert back to virtual address */
262 host->data_ptr = (u16 *)sg_virt(data->sg);
263 host->data_cnt = 0;
264
265 clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
266 set_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
267
268 return;
269 }
270
271 if (data->flags & MMC_DATA_READ) {
272 host->dma_dir = DMA_FROM_DEVICE;
273 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
274 data->sg_len, host->dma_dir);
275
276 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
277 host->res->start + MMC_REG_BUFFER_ACCESS,
278 DMA_MODE_READ);
279
280 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
281 CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
282 } else {
283 host->dma_dir = DMA_TO_DEVICE;
284
285 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
286 data->sg_len, host->dma_dir);
287
288 imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
289 host->res->start + MMC_REG_BUFFER_ACCESS,
290 DMA_MODE_WRITE);
291
292 /*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
293 CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
294 }
295
296#if 1 /* This code is there only for consistency checking and can be disabled in future */
297 host->dma_size = 0;
298 for (i = 0; i < host->dma_nents; i++)
299 host->dma_size += data->sg[i].length;
300
301 if (datasz > host->dma_size) {
302 dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
303 datasz, host->dma_size);
304 }
305#endif
306
307 host->dma_size = datasz;
308
309 wmb();
310
311 set_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
312 clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
313
314 /* start DMA engine for read, write is delayed after initial response */
315 if (host->dma_dir == DMA_FROM_DEVICE)
316 imx_dma_enable(host->dma);
317}
318
319static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
320{
321 unsigned long flags;
322 u32 imask;
323
324 WARN_ON(host->cmd != NULL);
325 host->cmd = cmd;
326
327 /* Ensure, that clock are stopped else command programming and start fails */
328 imxmci_stop_clock(host);
329
330 if (cmd->flags & MMC_RSP_BUSY)
331 cmdat |= CMD_DAT_CONT_BUSY;
332
333 switch (mmc_resp_type(cmd)) {
334 case MMC_RSP_R1: /* short CRC, OPCODE */
335 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
336 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R1;
337 break;
338 case MMC_RSP_R2: /* long 136 bit + CRC */
339 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R2;
340 break;
341 case MMC_RSP_R3: /* short */
342 cmdat |= CMD_DAT_CONT_RESPONSE_FORMAT_R3;
343 break;
344 default:
345 break;
346 }
347
348 if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events))
349 cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
350
351 if (host->actual_bus_width == MMC_BUS_WIDTH_4)
352 cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
353
354 writew(cmd->opcode, host->base + MMC_REG_CMD);
355 writew(cmd->arg >> 16, host->base + MMC_REG_ARGH);
356 writew(cmd->arg & 0xffff, host->base + MMC_REG_ARGL);
357 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
358
359 atomic_set(&host->stuck_timeout, 0);
360 set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
361
362
363 imask = IMXMCI_INT_MASK_DEFAULT;
364 imask &= ~INT_MASK_END_CMD_RES;
365 if (cmdat & CMD_DAT_CONT_DATA_ENABLE) {
366 /* imask &= ~INT_MASK_BUF_READY; */
367 imask &= ~INT_MASK_DATA_TRAN;
368 if (cmdat & CMD_DAT_CONT_WRITE)
369 imask &= ~INT_MASK_WRITE_OP_DONE;
370 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
371 imask &= ~INT_MASK_BUF_READY;
372 }
373
374 spin_lock_irqsave(&host->lock, flags);
375 host->imask = imask;
376 writew(host->imask, host->base + MMC_REG_INT_MASK);
377 spin_unlock_irqrestore(&host->lock, flags);
378
379 dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
380 cmd->opcode, cmd->opcode, imask);
381
382 imxmci_start_clock(host);
383}
384
385static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *req)
386{
387 unsigned long flags;
388
389 spin_lock_irqsave(&host->lock, flags);
390
391 host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
392 IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
393
394 host->imask = IMXMCI_INT_MASK_DEFAULT;
395 writew(host->imask, host->base + MMC_REG_INT_MASK);
396
397 spin_unlock_irqrestore(&host->lock, flags);
398
399 if (req && req->cmd)
400 host->prev_cmd_code = req->cmd->opcode;
401
402 host->req = NULL;
403 host->cmd = NULL;
404 host->data = NULL;
405 mmc_request_done(host->mmc, req);
406}
407
408static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
409{
410 struct mmc_data *data = host->data;
411 int data_error;
412
413 if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
414 imx_dma_disable(host->dma);
415 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
416 host->dma_dir);
417 }
418
419 if (stat & STATUS_ERR_MASK) {
420 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat);
421 if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
422 data->error = -EILSEQ;
423 else if (stat & STATUS_TIME_OUT_READ)
424 data->error = -ETIMEDOUT;
425 else
426 data->error = -EIO;
427 } else {
428 data->bytes_xfered = host->dma_size;
429 }
430
431 data_error = data->error;
432
433 host->data = NULL;
434
435 return data_error;
436}
437
438static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
439{
440 struct mmc_command *cmd = host->cmd;
441 int i;
442 u32 a, b, c;
443 struct mmc_data *data = host->data;
444
445 if (!cmd)
446 return 0;
447
448 host->cmd = NULL;
449
450 if (stat & STATUS_TIME_OUT_RESP) {
451 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
452 cmd->error = -ETIMEDOUT;
453 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
454 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
455 cmd->error = -EILSEQ;
456 }
457
458 if (cmd->flags & MMC_RSP_PRESENT) {
459 if (cmd->flags & MMC_RSP_136) {
460 for (i = 0; i < 4; i++) {
461 a = readw(host->base + MMC_REG_RES_FIFO);
462 b = readw(host->base + MMC_REG_RES_FIFO);
463 cmd->resp[i] = a << 16 | b;
464 }
465 } else {
466 a = readw(host->base + MMC_REG_RES_FIFO);
467 b = readw(host->base + MMC_REG_RES_FIFO);
468 c = readw(host->base + MMC_REG_RES_FIFO);
469 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
470 }
471 }
472
473 dev_dbg(mmc_dev(host->mmc), "RESP 0x%08x, 0x%08x, 0x%08x, 0x%08x, error %d\n",
474 cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3], cmd->error);
475
476 if (data && !cmd->error && !(stat & STATUS_ERR_MASK)) {
477 if (host->req->data->flags & MMC_DATA_WRITE) {
478
479 /* Wait for FIFO to be empty before starting DMA write */
480
481 stat = readw(host->base + MMC_REG_STATUS);
482 if (imxmci_busy_wait_for_status(host, &stat,
483 STATUS_APPL_BUFF_FE,
484 40, "imxmci_cmd_done DMA WR") < 0) {
485 cmd->error = -EIO;
486 imxmci_finish_data(host, stat);
487 if (host->req)
488 imxmci_finish_request(host, host->req);
489 dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
490 stat);
491 return 0;
492 }
493
494 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
495 imx_dma_enable(host->dma);
496 }
497 } else {
498 struct mmc_request *req;
499 imxmci_stop_clock(host);
500 req = host->req;
501
502 if (data)
503 imxmci_finish_data(host, stat);
504
505 if (req)
506 imxmci_finish_request(host, req);
507 else
508 dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
509 }
510
511 return 1;
512}
513
514static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
515{
516 struct mmc_data *data = host->data;
517 int data_error;
518
519 if (!data)
520 return 0;
521
522 data_error = imxmci_finish_data(host, stat);
523
524 if (host->req->stop) {
525 imxmci_stop_clock(host);
526 imxmci_start_cmd(host, host->req->stop, 0);
527 } else {
528 struct mmc_request *req;
529 req = host->req;
530 if (req)
531 imxmci_finish_request(host, req);
532 else
533 dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
534 }
535
536 return 1;
537}
538
539static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
540{
541 int i;
542 int burst_len;
543 int trans_done = 0;
544 unsigned int stat = *pstat;
545
546 if (host->actual_bus_width != MMC_BUS_WIDTH_4)
547 burst_len = 16;
548 else
549 burst_len = 64;
550
551 /* This is unfortunately required */
552 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data running STATUS = 0x%x\n",
553 stat);
554
555 udelay(20); /* required for clocks < 8MHz*/
556
557 if (host->dma_dir == DMA_FROM_DEVICE) {
558 imxmci_busy_wait_for_status(host, &stat,
559 STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
560 STATUS_TIME_OUT_READ,
561 50, "imxmci_cpu_driven_data read");
562
563 while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
564 !(stat & STATUS_TIME_OUT_READ) &&
565 (host->data_cnt < 512)) {
566
567 udelay(20); /* required for clocks < 8MHz*/
568
569 for (i = burst_len; i >= 2 ; i -= 2) {
570 u16 data;
571 data = readw(host->base + MMC_REG_BUFFER_ACCESS);
572 udelay(10); /* required for clocks < 8MHz*/
573 if (host->data_cnt+2 <= host->dma_size) {
574 *(host->data_ptr++) = data;
575 } else {
576 if (host->data_cnt < host->dma_size)
577 *(u8 *)(host->data_ptr) = data;
578 }
579 host->data_cnt += 2;
580 }
581
582 stat = readw(host->base + MMC_REG_STATUS);
583
584 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
585 host->data_cnt, burst_len, stat);
586 }
587
588 if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
589 trans_done = 1;
590
591 if (host->dma_size & 0x1ff)
592 stat &= ~STATUS_CRC_READ_ERR;
593
594 if (stat & STATUS_TIME_OUT_READ) {
595 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
596 stat);
597 trans_done = -1;
598 }
599
600 } else {
601 imxmci_busy_wait_for_status(host, &stat,
602 STATUS_APPL_BUFF_FE,
603 20, "imxmci_cpu_driven_data write");
604
605 while ((stat & STATUS_APPL_BUFF_FE) &&
606 (host->data_cnt < host->dma_size)) {
607 if (burst_len >= host->dma_size - host->data_cnt) {
608 burst_len = host->dma_size - host->data_cnt;
609 host->data_cnt = host->dma_size;
610 trans_done = 1;
611 } else {
612 host->data_cnt += burst_len;
613 }
614
615 for (i = burst_len; i > 0 ; i -= 2)
616 writew(*(host->data_ptr++), host->base + MMC_REG_BUFFER_ACCESS);
617
618 stat = readw(host->base + MMC_REG_STATUS);
619
620 dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
621 burst_len, stat);
622 }
623 }
624
625 *pstat = stat;
626
627 return trans_done;
628}
629
630static void imxmci_dma_irq(int dma, void *devid)
631{
632 struct imxmci_host *host = devid;
633 u32 stat = readw(host->base + MMC_REG_STATUS);
634
635 atomic_set(&host->stuck_timeout, 0);
636 host->status_reg = stat;
637 set_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
638 tasklet_schedule(&host->tasklet);
639}
640
641static irqreturn_t imxmci_irq(int irq, void *devid)
642{
643 struct imxmci_host *host = devid;
644 u32 stat = readw(host->base + MMC_REG_STATUS);
645 int handled = 1;
646
647 writew(host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT,
648 host->base + MMC_REG_INT_MASK);
649
650 atomic_set(&host->stuck_timeout, 0);
651 host->status_reg = stat;
652 set_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
653 set_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
654 tasklet_schedule(&host->tasklet);
655
656 return IRQ_RETVAL(handled);
657}
658
659static void imxmci_tasklet_fnc(unsigned long data)
660{
661 struct imxmci_host *host = (struct imxmci_host *)data;
662 u32 stat;
663 unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
664 int timeout = 0;
665
666 if (atomic_read(&host->stuck_timeout) > 4) {
667 char *what;
668 timeout = 1;
669 stat = readw(host->base + MMC_REG_STATUS);
670 host->status_reg = stat;
671 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
672 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
673 what = "RESP+DMA";
674 else
675 what = "RESP";
676 else
677 if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
678 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
679 what = "DATA";
680 else
681 what = "DMA";
682 else
683 what = "???";
684
685 dev_err(mmc_dev(host->mmc),
686 "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
687 what, stat,
688 readw(host->base + MMC_REG_INT_MASK));
689 dev_err(mmc_dev(host->mmc),
690 "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
691 readw(host->base + MMC_REG_CMD_DAT_CONT),
692 readw(host->base + MMC_REG_BLK_LEN),
693 readw(host->base + MMC_REG_NOB),
694 CCR(host->dma));
695 dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
696 host->cmd ? host->cmd->opcode : 0,
697 host->prev_cmd_code,
698 1 << host->actual_bus_width, host->dma_size);
699 }
700
701 if (!host->present || timeout)
702 host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
703 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
704
705 if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
706 clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
707
708 stat = readw(host->base + MMC_REG_STATUS);
709 /*
710 * This is not required in theory, but there is chance to miss some flag
711 * which clears automatically by mask write, FreeScale original code keeps
712 * stat from IRQ time so do I
713 */
714 stat |= host->status_reg;
715
716 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
717 stat &= ~STATUS_CRC_READ_ERR;
718
719 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
720 imxmci_busy_wait_for_status(host, &stat,
721 STATUS_END_CMD_RESP | STATUS_ERR_MASK,
722 20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
723 }
724
725 if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
726 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
727 imxmci_cmd_done(host, stat);
728 if (host->data && (stat & STATUS_ERR_MASK))
729 imxmci_data_done(host, stat);
730 }
731
732 if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
733 stat |= readw(host->base + MMC_REG_STATUS);
734 if (imxmci_cpu_driven_data(host, &stat)) {
735 if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
736 imxmci_cmd_done(host, stat);
737 atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
738 &host->pending_events);
739 imxmci_data_done(host, stat);
740 }
741 }
742 }
743
744 if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
745 !test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
746
747 stat = readw(host->base + MMC_REG_STATUS);
748 /* Same as above */
749 stat |= host->status_reg;
750
751 if (host->dma_dir == DMA_TO_DEVICE)
752 data_dir_mask = STATUS_WRITE_OP_DONE;
753 else
754 data_dir_mask = STATUS_DATA_TRANS_DONE;
755
756 if (stat & data_dir_mask) {
757 clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
758 imxmci_data_done(host, stat);
759 }
760 }
761
762 if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
763
764 if (host->cmd)
765 imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
766
767 if (host->data)
768 imxmci_data_done(host, STATUS_TIME_OUT_READ |
769 STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
770
771 if (host->req)
772 imxmci_finish_request(host, host->req);
773
774 mmc_detect_change(host->mmc, msecs_to_jiffies(100));
775
776 }
777}
778
779static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
780{
781 struct imxmci_host *host = mmc_priv(mmc);
782 unsigned int cmdat;
783
784 WARN_ON(host->req != NULL);
785
786 host->req = req;
787
788 cmdat = 0;
789
790 if (req->data) {
791 imxmci_setup_data(host, req->data);
792
793 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
794
795 if (req->data->flags & MMC_DATA_WRITE)
796 cmdat |= CMD_DAT_CONT_WRITE;
797
798 if (req->data->flags & MMC_DATA_STREAM)
799 cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
800 }
801
802 imxmci_start_cmd(host, req->cmd, cmdat);
803}
804
805#define CLK_RATE 19200000
806
807static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
808{
809 struct imxmci_host *host = mmc_priv(mmc);
810 int prescaler;
811
812 if (ios->bus_width == MMC_BUS_WIDTH_4) {
813 host->actual_bus_width = MMC_BUS_WIDTH_4;
814 imx_gpio_mode(PB11_PF_SD_DAT3);
815 BLR(host->dma) = 0; /* burst 64 byte read/write */
816 } else {
817 host->actual_bus_width = MMC_BUS_WIDTH_1;
818 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
819 BLR(host->dma) = 16; /* burst 16 byte read/write */
820 }
821
822 if (host->power_mode != ios->power_mode) {
823 switch (ios->power_mode) {
824 case MMC_POWER_OFF:
825 break;
826 case MMC_POWER_UP:
827 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
828 break;
829 case MMC_POWER_ON:
830 break;
831 }
832 host->power_mode = ios->power_mode;
833 }
834
835 if (ios->clock) {
836 unsigned int clk;
837 u16 reg;
838
839 /* The prescaler is 5 for PERCLK2 equal to 96MHz
840 * then 96MHz / 5 = 19.2 MHz
841 */
842 clk = clk_get_rate(host->clk);
843 prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE;
844 switch (prescaler) {
845 case 0:
846 case 1: prescaler = 0;
847 break;
848 case 2: prescaler = 1;
849 break;
850 case 3: prescaler = 2;
851 break;
852 case 4: prescaler = 4;
853 break;
854 default:
855 case 5: prescaler = 5;
856 break;
857 }
858
859 dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
860 clk, prescaler);
861
862 for (clk = 0; clk < 8; clk++) {
863 int x;
864 x = CLK_RATE / (1 << clk);
865 if (x <= ios->clock)
866 break;
867 }
868
869 /* enable controller */
870 reg = readw(host->base + MMC_REG_STR_STP_CLK);
871 writew(reg | STR_STP_CLK_ENABLE,
872 host->base + MMC_REG_STR_STP_CLK);
873
874 imxmci_stop_clock(host);
875 writew((prescaler << 3) | clk, host->base + MMC_REG_CLK_RATE);
876 /*
877 * Under my understanding, clock should not be started there, because it would
878 * initiate SDHC sequencer and send last or random command into card
879 */
880 /* imxmci_start_clock(host); */
881
882 dev_dbg(mmc_dev(host->mmc),
883 "MMC_CLK_RATE: 0x%08x\n",
884 readw(host->base + MMC_REG_CLK_RATE));
885 } else {
886 imxmci_stop_clock(host);
887 }
888}
889
890static int imxmci_get_ro(struct mmc_host *mmc)
891{
892 struct imxmci_host *host = mmc_priv(mmc);
893
894 if (host->pdata && host->pdata->get_ro)
895 return !!host->pdata->get_ro(mmc_dev(mmc));
896 /*
897 * Board doesn't support read only detection; let the mmc core
898 * decide what to do.
899 */
900 return -ENOSYS;
901}
902
903
904static const struct mmc_host_ops imxmci_ops = {
905 .request = imxmci_request,
906 .set_ios = imxmci_set_ios,
907 .get_ro = imxmci_get_ro,
908};
909
910static void imxmci_check_status(unsigned long data)
911{
912 struct imxmci_host *host = (struct imxmci_host *)data;
913
914 if (host->pdata && host->pdata->card_present &&
915 host->pdata->card_present(mmc_dev(host->mmc)) != host->present) {
916 host->present ^= 1;
917 dev_info(mmc_dev(host->mmc), "card %s\n",
918 host->present ? "inserted" : "removed");
919
920 set_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events);
921 tasklet_schedule(&host->tasklet);
922 }
923
924 if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
925 test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
926 atomic_inc(&host->stuck_timeout);
927 if (atomic_read(&host->stuck_timeout) > 4)
928 tasklet_schedule(&host->tasklet);
929 } else {
930 atomic_set(&host->stuck_timeout, 0);
931
932 }
933
934 mod_timer(&host->timer, jiffies + (HZ>>1));
935}
936
937static int __init imxmci_probe(struct platform_device *pdev)
938{
939 struct mmc_host *mmc;
940 struct imxmci_host *host = NULL;
941 struct resource *r;
942 int ret = 0, irq;
943 u16 rev_no;
944
945 printk(KERN_INFO "i.MX mmc driver\n");
946
947 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
948 irq = platform_get_irq(pdev, 0);
949 if (!r || irq < 0)
950 return -ENXIO;
951
952 r = request_mem_region(r->start, resource_size(r), pdev->name);
953 if (!r)
954 return -EBUSY;
955
956 mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
957 if (!mmc) {
958 ret = -ENOMEM;
959 goto out;
960 }
961
962 mmc->ops = &imxmci_ops;
963 mmc->f_min = 150000;
964 mmc->f_max = CLK_RATE/2;
965 mmc->ocr_avail = MMC_VDD_32_33;
966 mmc->caps = MMC_CAP_4_BIT_DATA;
967
968 /* MMC core transfer sizes tunable parameters */
969 mmc->max_segs = 64;
970 mmc->max_seg_size = 64*512; /* default PAGE_CACHE_SIZE */
971 mmc->max_req_size = 64*512; /* default PAGE_CACHE_SIZE */
972 mmc->max_blk_size = 2048;
973 mmc->max_blk_count = 65535;
974
975 host = mmc_priv(mmc);
976 host->base = ioremap(r->start, resource_size(r));
977 if (!host->base) {
978 ret = -ENOMEM;
979 goto out;
980 }
981
982 host->mmc = mmc;
983 host->dma_allocated = 0;
984 host->pdata = pdev->dev.platform_data;
985 if (!host->pdata)
986 dev_warn(&pdev->dev, "No platform data provided!\n");
987
988 spin_lock_init(&host->lock);
989 host->res = r;
990 host->irq = irq;
991
992 host->clk = clk_get(&pdev->dev, "perclk2");
993 if (IS_ERR(host->clk)) {
994 ret = PTR_ERR(host->clk);
995 goto out;
996 }
997 clk_enable(host->clk);
998
999 imx_gpio_mode(PB8_PF_SD_DAT0);
1000 imx_gpio_mode(PB9_PF_SD_DAT1);
1001 imx_gpio_mode(PB10_PF_SD_DAT2);
1002 /* Configured as GPIO with pull-up to ensure right MCC card mode */
1003 /* Switched to PB11_PF_SD_DAT3 if 4 bit bus is configured */
1004 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
1005 /* imx_gpio_mode(PB11_PF_SD_DAT3); */
1006 imx_gpio_mode(PB12_PF_SD_CLK);
1007 imx_gpio_mode(PB13_PF_SD_CMD);
1008
1009 imxmci_softreset(host);
1010
1011 rev_no = readw(host->base + MMC_REG_REV_NO);
1012 if (rev_no != 0x390) {
1013 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1014 readw(host->base + MMC_REG_REV_NO));
1015 goto out;
1016 }
1017
1018 /* recommended in data sheet */
1019 writew(0x2db4, host->base + MMC_REG_READ_TO);
1020
1021 host->imask = IMXMCI_INT_MASK_DEFAULT;
1022 writew(host->imask, host->base + MMC_REG_INT_MASK);
1023
1024 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
1025 if(host->dma < 0) {
1026 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n");
1027 ret = -EBUSY;
1028 goto out;
1029 }
1030 host->dma_allocated = 1;
1031 imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
1032 RSSR(host->dma) = DMA_REQ_SDHC;
1033
1034 tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
1035 host->status_reg=0;
1036 host->pending_events=0;
1037
1038 ret = request_irq(host->irq, imxmci_irq, 0, DRIVER_NAME, host);
1039 if (ret)
1040 goto out;
1041
1042 if (host->pdata && host->pdata->card_present)
1043 host->present = host->pdata->card_present(mmc_dev(mmc));
1044 else /* if there is no way to detect assume that card is present */
1045 host->present = 1;
1046
1047 init_timer(&host->timer);
1048 host->timer.data = (unsigned long)host;
1049 host->timer.function = imxmci_check_status;
1050 add_timer(&host->timer);
1051 mod_timer(&host->timer, jiffies + (HZ >> 1));
1052
1053 platform_set_drvdata(pdev, mmc);
1054
1055 mmc_add_host(mmc);
1056
1057 return 0;
1058
1059out:
1060 if (host) {
1061 if (host->dma_allocated) {
1062 imx_dma_free(host->dma);
1063 host->dma_allocated = 0;
1064 }
1065 if (host->clk) {
1066 clk_disable(host->clk);
1067 clk_put(host->clk);
1068 }
1069 if (host->base)
1070 iounmap(host->base);
1071 }
1072 if (mmc)
1073 mmc_free_host(mmc);
1074 release_mem_region(r->start, resource_size(r));
1075 return ret;
1076}
1077
1078static int __exit imxmci_remove(struct platform_device *pdev)
1079{
1080 struct mmc_host *mmc = platform_get_drvdata(pdev);
1081
1082 platform_set_drvdata(pdev, NULL);
1083
1084 if (mmc) {
1085 struct imxmci_host *host = mmc_priv(mmc);
1086
1087 tasklet_disable(&host->tasklet);
1088
1089 del_timer_sync(&host->timer);
1090 mmc_remove_host(mmc);
1091
1092 free_irq(host->irq, host);
1093 iounmap(host->base);
1094 if (host->dma_allocated) {
1095 imx_dma_free(host->dma);
1096 host->dma_allocated = 0;
1097 }
1098
1099 tasklet_kill(&host->tasklet);
1100
1101 clk_disable(host->clk);
1102 clk_put(host->clk);
1103
1104 release_mem_region(host->res->start, resource_size(host->res));
1105
1106 mmc_free_host(mmc);
1107 }
1108 return 0;
1109}
1110
1111#ifdef CONFIG_PM
1112static int imxmci_suspend(struct platform_device *dev, pm_message_t state)
1113{
1114 struct mmc_host *mmc = platform_get_drvdata(dev);
1115 int ret = 0;
1116
1117 if (mmc)
1118 ret = mmc_suspend_host(mmc);
1119
1120 return ret;
1121}
1122
1123static int imxmci_resume(struct platform_device *dev)
1124{
1125 struct mmc_host *mmc = platform_get_drvdata(dev);
1126 struct imxmci_host *host;
1127 int ret = 0;
1128
1129 if (mmc) {
1130 host = mmc_priv(mmc);
1131 if (host)
1132 set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
1133 ret = mmc_resume_host(mmc);
1134 }
1135
1136 return ret;
1137}
1138#else
1139#define imxmci_suspend NULL
1140#define imxmci_resume NULL
1141#endif /* CONFIG_PM */
1142
1143static struct platform_driver imxmci_driver = {
1144 .remove = __exit_p(imxmci_remove),
1145 .suspend = imxmci_suspend,
1146 .resume = imxmci_resume,
1147 .driver = {
1148 .name = DRIVER_NAME,
1149 .owner = THIS_MODULE,
1150 }
1151};
1152
1153static int __init imxmci_init(void)
1154{
1155 return platform_driver_probe(&imxmci_driver, imxmci_probe);
1156}
1157
1158static void __exit imxmci_exit(void)
1159{
1160 platform_driver_unregister(&imxmci_driver);
1161}
1162
1163module_init(imxmci_init);
1164module_exit(imxmci_exit);
1165
1166MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1167MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1168MODULE_LICENSE("GPL");
1169MODULE_ALIAS("platform:imx-mmc");
diff --git a/drivers/mmc/host/imxmmc.h b/drivers/mmc/host/imxmmc.h
new file mode 100644
index 00000000000..09d5d4ee3a7
--- /dev/null
+++ b/drivers/mmc/host/imxmmc.h
@@ -0,0 +1,64 @@
1#define MMC_REG_STR_STP_CLK 0x00
2#define MMC_REG_STATUS 0x04
3#define MMC_REG_CLK_RATE 0x08
4#define MMC_REG_CMD_DAT_CONT 0x0C
5#define MMC_REG_RES_TO 0x10
6#define MMC_REG_READ_TO 0x14
7#define MMC_REG_BLK_LEN 0x18
8#define MMC_REG_NOB 0x1C
9#define MMC_REG_REV_NO 0x20
10#define MMC_REG_INT_MASK 0x24
11#define MMC_REG_CMD 0x28
12#define MMC_REG_ARGH 0x2C
13#define MMC_REG_ARGL 0x30
14#define MMC_REG_RES_FIFO 0x34
15#define MMC_REG_BUFFER_ACCESS 0x38
16
17#define STR_STP_CLK_IPG_CLK_GATE_DIS (1<<15)
18#define STR_STP_CLK_IPG_PERCLK_GATE_DIS (1<<14)
19#define STR_STP_CLK_ENDIAN (1<<5)
20#define STR_STP_CLK_RESET (1<<3)
21#define STR_STP_CLK_ENABLE (1<<2)
22#define STR_STP_CLK_START_CLK (1<<1)
23#define STR_STP_CLK_STOP_CLK (1<<0)
24#define STATUS_CARD_PRESENCE (1<<15)
25#define STATUS_SDIO_INT_ACTIVE (1<<14)
26#define STATUS_END_CMD_RESP (1<<13)
27#define STATUS_WRITE_OP_DONE (1<<12)
28#define STATUS_DATA_TRANS_DONE (1<<11)
29#define STATUS_WR_CRC_ERROR_CODE_MASK (3<<10)
30#define STATUS_CARD_BUS_CLK_RUN (1<<8)
31#define STATUS_APPL_BUFF_FF (1<<7)
32#define STATUS_APPL_BUFF_FE (1<<6)
33#define STATUS_RESP_CRC_ERR (1<<5)
34#define STATUS_CRC_READ_ERR (1<<3)
35#define STATUS_CRC_WRITE_ERR (1<<2)
36#define STATUS_TIME_OUT_RESP (1<<1)
37#define STATUS_TIME_OUT_READ (1<<0)
38#define STATUS_ERR_MASK 0x2f
39#define CLK_RATE_PRESCALER(x) ((x) & 0x7)
40#define CLK_RATE_CLK_RATE(x) (((x) & 0x7) << 3)
41#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1<<12)
42#define CMD_DAT_CONT_STOP_READWAIT (1<<11)
43#define CMD_DAT_CONT_START_READWAIT (1<<10)
44#define CMD_DAT_CONT_BUS_WIDTH_1 (0<<8)
45#define CMD_DAT_CONT_BUS_WIDTH_4 (2<<8)
46#define CMD_DAT_CONT_INIT (1<<7)
47#define CMD_DAT_CONT_BUSY (1<<6)
48#define CMD_DAT_CONT_STREAM_BLOCK (1<<5)
49#define CMD_DAT_CONT_WRITE (1<<4)
50#define CMD_DAT_CONT_DATA_ENABLE (1<<3)
51#define CMD_DAT_CONT_RESPONSE_FORMAT_R1 (1)
52#define CMD_DAT_CONT_RESPONSE_FORMAT_R2 (2)
53#define CMD_DAT_CONT_RESPONSE_FORMAT_R3 (3)
54#define CMD_DAT_CONT_RESPONSE_FORMAT_R4 (4)
55#define CMD_DAT_CONT_RESPONSE_FORMAT_R5 (5)
56#define CMD_DAT_CONT_RESPONSE_FORMAT_R6 (6)
57#define INT_MASK_AUTO_CARD_DETECT (1<<6)
58#define INT_MASK_DAT0_EN (1<<5)
59#define INT_MASK_SDIO (1<<4)
60#define INT_MASK_BUF_READY (1<<3)
61#define INT_MASK_END_CMD_RES (1<<2)
62#define INT_MASK_WRITE_OP_DONE (1<<1)
63#define INT_MASK_DATA_TRAN (1<<0)
64#define INT_ALL (0x7f)
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-14 07:55:15 -0400