Added missing tegra files.HEADmaster

4 files changed, 2564 insertions, 0 deletions

diff --git a/drivers/mmc/host/at91_mci.c b/drivers/mmc/host/at91_mci.c
new file mode 100644
index 00000000000..a4aa3af86fe
--- /dev/null
+++ b/drivers/mmc/host/at91_mci.c
@@ -0,0 +1,1216 @@
+/*
+ *  linux/drivers/mmc/host/at91_mci.c - ATMEL AT91 MCI Driver
+ *
+ *  Copyright (C) 2005 Cougar Creek Computing Devices Ltd, All Rights Reserved
+ *
+ *  Copyright (C) 2006 Malcolm Noyes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+   This is the AT91 MCI driver that has been tested with both MMC cards
+   and SD-cards.  Boards that support write protect are now supported.
+   The CCAT91SBC001 board does not support SD cards.
+
+   The three entry points are at91_mci_request, at91_mci_set_ios
+   and at91_mci_get_ro.
+
+   SET IOS
+     This configures the device to put it into the correct mode and clock speed
+     required.
+
+   MCI REQUEST
+     MCI request processes the commands sent in the mmc_request structure. This
+     can consist of a processing command and a stop command in the case of
+     multiple block transfers.
+
+     There are three main types of request, commands, reads and writes.
+
+     Commands are straight forward. The command is submitted to the controller and
+     the request function returns. When the controller generates an interrupt to indicate
+     the command is finished, the response to the command are read and the mmc_request_done
+     function called to end the request.
+
+     Reads and writes work in a similar manner to normal commands but involve the PDC (DMA)
+     controller to manage the transfers.
+
+     A read is done from the controller directly to the scatterlist passed in from the request.
+     Due to a bug in the AT91RM9200 controller, when a read is completed, all the words are byte
+     swapped in the scatterlist buffers.  AT91SAM926x are not affected by this bug.
+
+     The sequence of read interrupts is: ENDRX, RXBUFF, CMDRDY
+
+     A write is slightly different in that the bytes to write are read from the scatterlist
+     into a dma memory buffer (this is in case the source buffer should be read only). The
+     entire write buffer is then done from this single dma memory buffer.
+
+     The sequence of write interrupts is: ENDTX, TXBUFE, NOTBUSY, CMDRDY
+
+   GET RO
+     Gets the status of the write protect pin, if available.
+*/
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/blkdev.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/dma-mapping.h>
+#include <linux/clk.h>
+#include <linux/atmel_pdc.h>
+#include <linux/gfp.h>
+#include <linux/highmem.h>
+
+#include <linux/mmc/host.h>
+#include <linux/mmc/sdio.h>
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/gpio.h>
+
+#include <mach/board.h>
+#include <mach/cpu.h>
+
+#include "at91_mci.h"
+
+#define DRIVER_NAME "at91_mci"
+
+static inline int at91mci_is_mci1rev2xx(void)
+{
+        return (   cpu_is_at91sam9260()
+                || cpu_is_at91sam9263()
+                || cpu_is_at91cap9()
+                || cpu_is_at91sam9rl()
+                || cpu_is_at91sam9g10()
+                || cpu_is_at91sam9g20()
+                );
+}
+
+#define FL_SENT_COMMAND (1 << 0)
+#define FL_SENT_STOP    (1 << 1)
+
+#define AT91_MCI_ERRORS (AT91_MCI_RINDE | AT91_MCI_RDIRE | AT91_MCI_RCRCE       \
+                | AT91_MCI_RENDE | AT91_MCI_RTOE | AT91_MCI_DCRCE               \
+                | AT91_MCI_DTOE | AT91_MCI_OVRE | AT91_MCI_UNRE)
+
+#define at91_mci_read(host, reg)        __raw_readl((host)->baseaddr + (reg))
+#define at91_mci_write(host, reg, val)  __raw_writel((val), (host)->baseaddr + (reg))
+
+#define MCI_BLKSIZE             512
+#define MCI_MAXBLKSIZE          4095
+#define MCI_BLKATONCE           256
+#define MCI_BUFSIZE             (MCI_BLKSIZE * MCI_BLKATONCE)
+
+/*
+ * Low level type for this driver
+ */
+struct at91mci_host
+{
+        struct mmc_host *mmc;
+        struct mmc_command *cmd;
+        struct mmc_request *request;
+
+        void __iomem *baseaddr;
+        int irq;
+
+        struct at91_mmc_data *board;
+        int present;
+
+        struct clk *mci_clk;
+
+        /*
+         * Flag indicating when the command has been sent. This is used to
+         * work out whether or not to send the stop
+         */
+        unsigned int flags;
+        /* flag for current bus settings */
+        u32 bus_mode;
+
+        /* DMA buffer used for transmitting */
+        unsigned int* buffer;
+        dma_addr_t physical_address;
+        unsigned int total_length;
+
+        /* Latest in the scatterlist that has been enabled for transfer, but not freed */
+        int in_use_index;
+
+        /* Latest in the scatterlist that has been enabled for transfer */
+        int transfer_index;
+
+        /* Timer for timeouts */
+        struct timer_list timer;
+};
+
+/*
+ * Reset the controller and restore most of the state
+ */
+static void at91_reset_host(struct at91mci_host *host)
+{
+        unsigned long flags;
+        u32 mr;
+        u32 sdcr;
+        u32 dtor;
+        u32 imr;
+
+        local_irq_save(flags);
+        imr = at91_mci_read(host, AT91_MCI_IMR);
+
+        at91_mci_write(host, AT91_MCI_IDR, 0xffffffff);
+
+        /* save current state */
+        mr = at91_mci_read(host, AT91_MCI_MR) & 0x7fff;
+        sdcr = at91_mci_read(host, AT91_MCI_SDCR);
+        dtor = at91_mci_read(host, AT91_MCI_DTOR);
+
+        /* reset the controller */
+        at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIDIS | AT91_MCI_SWRST);
+
+        /* restore state */
+        at91_mci_write(host, AT91_MCI_CR, AT91_MCI_MCIEN);
+        at91_mci_write(host, AT91_MCI_MR, mr);
+        at91_mci_write(host, AT91_MCI_SDCR, sdcr);
+        at91_mci_write(host, AT91_MCI_DTOR, dtor);
+        at91_mci_write(host, AT91_MCI_IER, imr);
+
+        /* make sure sdio interrupts will fire */
+        at91_mci_read(host, AT91_MCI_SR);
+
+        local_irq_restore(flags);
+}
+
+static void at91_timeout_timer(unsigned long data)
+{
+        struct at91mci_host *host;
+
+        host = (struct at91mci_host *)data;
+
+        if (host->request) {
+                dev_err(host->mmc->parent, "Timeout waiting end of packet\n");
+
+                if (host->cmd && host->cmd->data) {
+                        host->cmd->data->error = -ETIMEDOUT;
+                } else {
+                        if (host->cmd)
+                                host->cmd->error = -ETIMEDOUT;
+                        else
+                                host->request->cmd->error = -ETIMEDOUT;
+                }
+
+                at91_reset_host(host);
+                mmc_request_done(host->mmc, host->request);
+        }
+}
+
+/*
+ * Copy from sg to a dma block - used for transfers