Added missing tegra files.HEADmaster

15 files changed, 8460 insertions, 0 deletions

diff --git a/drivers/mfd/ab3550-core.c b/drivers/mfd/ab3550-core.c
new file mode 100644
index 00000000000..56ba1943c91
--- /dev/null
+++ b/drivers/mfd/ab3550-core.c
@@ -0,0 +1,1380 @@
+/*
+ * Copyright (C) 2007-2010 ST-Ericsson
+ * License terms: GNU General Public License (GPL) version 2
+ * Low-level core for exclusive access to the AB3550 IC on the I2C bus
+ * and some basic chip-configuration.
+ * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com>
+ * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
+ * Author: Mattias Wallin <mattias.wallin@stericsson.com>
+ * Author: Rickard Andersson <rickard.andersson@stericsson.com>
+ */
+
+#include <linux/i2c.h>
+#include <linux/mutex.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/random.h>
+#include <linux/workqueue.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/uaccess.h>
+#include <linux/mfd/abx500.h>
+#include <linux/list.h>
+#include <linux/bitops.h>
+#include <linux/spinlock.h>
+#include <linux/mfd/core.h>
+
+#define AB3550_NAME_STRING "ab3550"
+#define AB3550_ID_FORMAT_STRING "AB3550 %s"
+#define AB3550_NUM_BANKS 2
+#define AB3550_NUM_EVENT_REG 5
+
+/* These are the only registers inside AB3550 used in this main file */
+
+/* Chip ID register */
+#define AB3550_CID_REG           0x20
+
+/* Interrupt event registers */
+#define AB3550_EVENT_BANK        0
+#define AB3550_EVENT_REG         0x22
+
+/* Read/write operation values. */
+#define AB3550_PERM_RD (0x01)
+#define AB3550_PERM_WR (0x02)
+
+/* Read/write permissions. */
+#define AB3550_PERM_RO (AB3550_PERM_RD)
+#define AB3550_PERM_RW (AB3550_PERM_RD | AB3550_PERM_WR)
+
+/**
+ * struct ab3550
+ * @access_mutex: lock out concurrent accesses to the AB registers
+ * @i2c_client: I2C client for this chip
+ * @chip_name: name of this chip variant
+ * @chip_id: 8 bit chip ID for this chip variant
+ * @mask_work: a worker for writing to mask registers
+ * @event_lock: a lock to protect the event_mask
+ * @event_mask: a local copy of the mask event registers
+ * @startup_events: a copy of the first reading of the event registers
+ * @startup_events_read: whether the first events have been read
+ */
+struct ab3550 {
+        struct mutex access_mutex;
+        struct i2c_client *i2c_client[AB3550_NUM_BANKS];
+        char chip_name[32];
+        u8 chip_id;
+        struct work_struct mask_work;
+        spinlock_t event_lock;
+        u8 event_mask[AB3550_NUM_EVENT_REG];
+        u8 startup_events[AB3550_NUM_EVENT_REG];
+        bool startup_events_read;
+#ifdef CONFIG_DEBUG_FS
+        unsigned int debug_bank;
+        unsigned int debug_address;
+#endif
+};
+
+/**
+ * struct ab3550_reg_range
+ * @first: the first address of the range
+ * @last: the last address of the range
+ * @perm: access permissions for the range
+ */
+struct ab3550_reg_range {
+        u8 first;
+        u8 last;
+        u8 perm;
+};
+
+/**
+ * struct ab3550_reg_ranges
+ * @count: the number of ranges in the list
+ * @range: the list of register ranges
+ */
+struct ab3550_reg_ranges {
+        u8 count;
+        const struct ab3550_reg_range *range;
+};
+
+/*
+ * Permissible register ranges for reading and writing per device and bank.
+ *
+ * The ranges must be listed in increasing address order, and no overlaps are
+ * allowed. It is assumed that write permission implies read permission
+ * (i.e. only RO and RW permissions should be used).  Ranges with write
+ * permission must not be split up.
+ */
+
+#define NO_RANGE {.count = 0, .range = NULL,}
+
+static struct
+ab3550_reg_ranges ab3550_reg_ranges[AB3550_NUM_DEVICES][AB3550_NUM_BANKS] = {
+        [AB3550_DEVID_DAC] = {
+                NO_RANGE,
+                {
+                        .count = 2,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0xb0,
+                                        .last = 0xba,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                                {
+                                        .first = 0xbc,
+                                        .last = 0xc3,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                        },
+                },
+        },
+        [AB3550_DEVID_LEDS] = {
+                NO_RANGE,
+                {
+                        .count = 2,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x5a,
+                                        .last = 0x88,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                                {
+                                        .first = 0x8a,
+                                        .last = 0xad,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                        }
+                },
+        },
+        [AB3550_DEVID_POWER] = {
+                {
+                        .count = 1,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x21,
+                                        .last = 0x21,
+                                        .perm = AB3550_PERM_RO,
+                                },
+                        }
+                },
+                NO_RANGE,
+        },
+        [AB3550_DEVID_REGULATORS] = {
+                {
+                        .count = 1,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x69,
+                                        .last = 0xa3,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                        }
+                },
+                {
+                        .count = 1,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x14,
+                                        .last = 0x16,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                        }
+                },
+        },
+        [AB3550_DEVID_SIM] = {
+                {
+                        .count = 1,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x21,
+                                        .last = 0x21,
+                                        .perm = AB3550_PERM_RO,
+                                },