Added missing tegra files.HEADmaster

15 files changed, 8460 insertions, 0 deletions

diff --git a/drivers/mfd/ab3550-core.c b/drivers/mfd/ab3550-core.c
new file mode 100644
index 00000000000..56ba1943c91
--- /dev/null
+++ b/drivers/mfd/ab3550-core.c
@@ -0,0 +1,1380 @@
+/*
+ * Copyright (C) 2007-2010 ST-Ericsson
+ * License terms: GNU General Public License (GPL) version 2
+ * Low-level core for exclusive access to the AB3550 IC on the I2C bus
+ * and some basic chip-configuration.
+ * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com>
+ * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
+ * Author: Mattias Wallin <mattias.wallin@stericsson.com>
+ * Author: Rickard Andersson <rickard.andersson@stericsson.com>
+ */
+
+#include <linux/i2c.h>
+#include <linux/mutex.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/random.h>
+#include <linux/workqueue.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/uaccess.h>
+#include <linux/mfd/abx500.h>
+#include <linux/list.h>
+#include <linux/bitops.h>
+#include <linux/spinlock.h>
+#include <linux/mfd/core.h>
+
+#define AB3550_NAME_STRING "ab3550"
+#define AB3550_ID_FORMAT_STRING "AB3550 %s"
+#define AB3550_NUM_BANKS 2
+#define AB3550_NUM_EVENT_REG 5
+
+/* These are the only registers inside AB3550 used in this main file */
+
+/* Chip ID register */
+#define AB3550_CID_REG           0x20
+
+/* Interrupt event registers */
+#define AB3550_EVENT_BANK        0
+#define AB3550_EVENT_REG         0x22
+
+/* Read/write operation values. */
+#define AB3550_PERM_RD (0x01)
+#define AB3550_PERM_WR (0x02)
+
+/* Read/write permissions. */
+#define AB3550_PERM_RO (AB3550_PERM_RD)
+#define AB3550_PERM_RW (AB3550_PERM_RD | AB3550_PERM_WR)
+
+/**
+ * struct ab3550
+ * @access_mutex: lock out concurrent accesses to the AB registers
+ * @i2c_client: I2C client for this chip
+ * @chip_name: name of this chip variant
+ * @chip_id: 8 bit chip ID for this chip variant
+ * @mask_work: a worker for writing to mask registers
+ * @event_lock: a lock to protect the event_mask
+ * @event_mask: a local copy of the mask event registers
+ * @startup_events: a copy of the first reading of the event registers
+ * @startup_events_read: whether the first events have been read
+ */
+struct ab3550 {
+        struct mutex access_mutex;
+        struct i2c_client *i2c_client[AB3550_NUM_BANKS];
+        char chip_name[32];
+        u8 chip_id;
+        struct work_struct mask_work;
+        spinlock_t event_lock;
+        u8 event_mask[AB3550_NUM_EVENT_REG];
+        u8 startup_events[AB3550_NUM_EVENT_REG];
+        bool startup_events_read;
+#ifdef CONFIG_DEBUG_FS
+        unsigned int debug_bank;
+        unsigned int debug_address;
+#endif
+};
+
+/**
+ * struct ab3550_reg_range
+ * @first: the first address of the range
+ * @last: the last address of the range
+ * @perm: access permissions for the range
+ */
+struct ab3550_reg_range {
+        u8 first;
+        u8 last;
+        u8 perm;
+};
+
+/**
+ * struct ab3550_reg_ranges
+ * @count: the number of ranges in the list
+ * @range: the list of register ranges
+ */
+struct ab3550_reg_ranges {
+        u8 count;
+        const struct ab3550_reg_range *range;
+};
+
+/*
+ * Permissible register ranges for reading and writing per device and bank.
+ *
+ * The ranges must be listed in increasing address order, and no overlaps are
+ * allowed. It is assumed that write permission implies read permission
+ * (i.e. only RO and RW permissions should be used).  Ranges with write
+ * permission must not be split up.
+ */
+
+#define NO_RANGE {.count = 0, .range = NULL,}
+
+static struct
+ab3550_reg_ranges ab3550_reg_ranges[AB3550_NUM_DEVICES][AB3550_NUM_BANKS] = {
+        [AB3550_DEVID_DAC] = {
+                NO_RANGE,
+                {
+                        .count = 2,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0xb0,
+                                        .last = 0xba,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                                {
+                                        .first = 0xbc,
+                                        .last = 0xc3,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                        },
+                },
+        },
+        [AB3550_DEVID_LEDS] = {
+                NO_RANGE,
+                {
+                        .count = 2,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x5a,
+                                        .last = 0x88,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                                {
+                                        .first = 0x8a,
+                                        .last = 0xad,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                        }
+                },
+        },
+        [AB3550_DEVID_POWER] = {
+                {
+                        .count = 1,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x21,
+                                        .last = 0x21,
+                                        .perm = AB3550_PERM_RO,
+                                },
+                        }
+                },
+                NO_RANGE,
+        },
+        [AB3550_DEVID_REGULATORS] = {
+                {
+                        .count = 1,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x69,
+                                        .last = 0xa3,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                        }
+                },
+                {
+                        .count = 1,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x14,
+                                        .last = 0x16,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                        }
+                },
+        },
+        [AB3550_DEVID_SIM] = {
+                {
+                        .count = 1,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x21,
+                                        .last = 0x21,
+                                        .perm = AB3550_PERM_RO,
+                                },
+                        }
+                },
+                {
+                        .count = 1,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x14,
+                                        .last = 0x17,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                        }
+
+                },
+        },
+        [AB3550_DEVID_UART] = {
+                NO_RANGE,
+                NO_RANGE,
+        },
+        [AB3550_DEVID_RTC] = {
+                {
+                        .count = 1,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x00,
+                                        .last = 0x0c,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                        }
+                },
+                NO_RANGE,
+        },
+        [AB3550_DEVID_CHARGER] = {
+                {
+                        .count = 2,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x10,
+                                        .last = 0x1a,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                                {
+                                        .first = 0x21,
+                                        .last = 0x21,
+                                        .perm = AB3550_PERM_RO,
+                                },
+                        }
+                },
+                NO_RANGE,
+        },
+        [AB3550_DEVID_ADC] = {
+                NO_RANGE,
+                {
+                        .count = 1,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x20,
+                                        .last = 0x56,
+                                        .perm = AB3550_PERM_RW,
+                                },
+
+                        }
+                },
+        },
+        [AB3550_DEVID_FUELGAUGE] = {
+                {
+                        .count = 1,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x21,
+                                        .last = 0x21,
+                                        .perm = AB3550_PERM_RO,
+                                },
+                        }
+                },
+                {
+                        .count = 1,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x00,
+                                        .last = 0x0e,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                        }
+                },
+        },
+        [AB3550_DEVID_VIBRATOR] = {
+                NO_RANGE,
+                {
+                        .count = 1,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x10,
+                                        .last = 0x13,
+                                        .perm = AB3550_PERM_RW,
+                                },
+
+                        }
+                },
+        },
+        [AB3550_DEVID_CODEC] = {
+                {
+                        .count = 2,
+                        .range = (struct ab3550_reg_range[]) {
+                                {
+                                        .first = 0x31,
+                                        .last = 0x63,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                                {
+                                        .first = 0x65,
+                                        .last = 0x68,
+                                        .perm = AB3550_PERM_RW,
+                                },
+                        }
+                },
+                NO_RANGE,
+        },
+};
+
+static struct mfd_cell ab3550_devs[AB3550_NUM_DEVICES] = {
+        [AB3550_DEVID_DAC] = {
+                .name = "ab3550-dac",
+                .id = AB3550_DEVID_DAC,
+                .num_resources = 0,
+        },
+        [AB3550_DEVID_LEDS] = {
+                .name = "ab3550-leds",
+                .id = AB3550_DEVID_LEDS,
+        },
+        [AB3550_DEVID_POWER] = {
+                .name = "ab3550-power",
+                .id = AB3550_DEVID_POWER,
+        },
+        [AB3550_DEVID_REGULATORS] = {
+                .name = "ab3550-regulators",
+                .id = AB3550_DEVID_REGULATORS,
+        },
+        [AB3550_DEVID_SIM] = {
+                .name = "ab3550-sim",
+                .id = AB3550_DEVID_SIM,
+        },
+        [AB3550_DEVID_UART] = {
+                .name = "ab3550-uart",
+                .id = AB3550_DEVID_UART,
+        },
+        [AB3550_DEVID_RTC] = {
+                .name = "ab3550-rtc",
+                .id = AB3550_DEVID_RTC,
+        },
+        [AB3550_DEVID_CHARGER] = {
+                .name = "ab3550-charger",
+                .id = AB3550_DEVID_CHARGER,
+        },
+        [AB3550_DEVID_ADC] = {
+                .name = "ab3550-adc",
+                .id = AB3550_DEVID_ADC,
+                .num_resources = 10,
+                .resources = (struct resource[]) {
+                        {
+                                .name = "TRIGGER-0",
+                                .flags = IORESOURCE_IRQ,
+                                .start = 16,
+                                .end = 16,
+                        },
+                        {
+                                .name = "TRIGGER-1",
+                                .flags = IORESOURCE_IRQ,
+                                .start = 17,
+                                .end = 17,
+                        },
+                        {
+                                .name = "TRIGGER-2",
+                                .flags = IORESOURCE_IRQ,
+                                .start = 18,
+                                .end = 18,
+                        },
+                        {
+                                .name = "TRIGGER-3",
+                                .flags = IORESOURCE_IRQ,
+                                .start = 19,
+                                .end = 19,
+                        },
+                        {
+                                .name = "TRIGGER-4",
+                                .flags = IORESOURCE_IRQ,
+                                .start = 20,
+                                .end = 20,
+                        },
+                        {
+                                .name = "TRIGGER-5",
+                                .flags = IORESOURCE_IRQ,
+                                .start = 21,
+                                .end = 21,
+                        },
+                        {
+                                .name = "TRIGGER-6",
+                                .flags = IORESOURCE_IRQ,
+                                .start = 22,
+                                .end = 22,
+                        },
+                        {
+                                .name = "TRIGGER-7",
+                                .flags = IORESOURCE_IRQ,
+                                .start = 23,
+                                .end = 23,
+                        },
+                        {
+                                .name = "TRIGGER-VBAT-TXON",
+                                .flags = IORESOURCE_IRQ,
+                                .start = 13,
+                                .end = 13,
+                        },
+                        {
+                                .name = "TRIGGER-VBAT",
+                                .flags = IORESOURCE_IRQ,
+                                .start = 12,
+                                .end = 12,
+                        },
+                },
+        },
+        [AB3550_DEVID_FUELGAUGE] = {
+                .name = "ab3550-fuelgauge",
+                .id = AB3550_DEVID_FUELGAUGE,
+        },
+        [AB3550_DEVID_VIBRATOR] = {
+                .name = "ab3550-vibrator",
+                .id = AB3550_DEVID_VIBRATOR,
+        },
+        [AB3550_DEVID_CODEC] = {
+                .name = "ab3550-codec",
+                .id = AB3550_DEVID_CODEC,
+        },
+};
+
+/*
+ * I2C transactions with error messages.
+ */
+static int ab3550_i2c_master_send(struct ab3550 *ab, u8 bank, u8 *data,
+        u8 count)
+{
+        int err;
+
+        err = i2c_master_send(ab->i2c_client[bank], data, count);
+        if (err < 0) {
+                dev_err(&ab->i2c_client[0]->dev, "send error: %d\n", err);
+                return err;
+        }
+        return 0;
+}
+
+static int ab3550_i2c_master_recv(struct ab3550 *ab, u8 bank, u8 *data,
+        u8 count)
+{
+        int err;
+
+        err = i2c_master_recv(ab->i2c_client[bank], data, count);
+        if (err < 0) {
+                dev_err(&ab->i2c_client[0]->dev, "receive error: %d\n", err);
+                return err;
+        }
+        return 0;
+}
+
+/*
+ * Functionality for getting/setting register values.
+ */
+static int get_register_interruptible(struct ab3550 *ab, u8 bank, u8 reg,
+        u8 *value)
+{
+        int err;
+
+        err = mutex_lock_interruptible(&ab->access_mutex);
+        if (err)
+                return err;
+
+        err = ab3550_i2c_master_send(ab, bank, &reg, 1);
+        if (!err)
+                err = ab3550_i2c_master_recv(ab, bank, value, 1);
+
+        mutex_unlock(&ab->access_mutex);
+        return err;
+}
+
+static int get_register_page_interruptible(struct ab3550 *ab, u8 bank,
+        u8 first_reg, u8 *regvals, u8 numregs)
+{
+        int err;
+
+        err = mutex_lock_interruptible(&ab->access_mutex);
+        if (err)
+                return err;
+
+        err = ab3550_i2c_master_send(ab, bank, &first_reg, 1);
+        if (!err)
+                err = ab3550_i2c_master_recv(ab, bank, regvals, numregs);
+
+        mutex_unlock(&ab->access_mutex);
+        return err;
+}
+
+static int mask_and_set_register_interruptible(struct ab3550 *ab, u8 bank,
+        u8 reg, u8 bitmask, u8 bitvalues)
+{
+        int err = 0;
+
+        if (likely(bitmask)) {
+                u8 reg_bits[2] = {reg, 0};
+
+                err = mutex_lock_interruptible(&ab->access_mutex);
+                if (err)
+                        return err;
+
+                if (bitmask == 0xFF) /* No need to read in this case. */
+                        reg_bits[1] = bitvalues;
+                else { /* Read and modify the register value. */
+                        u8 bits;
+
+                        err = ab3550_i2c_master_send(ab, bank, &reg, 1);
+                        if (err)
+                                goto unlock_and_return;
+                        err = ab3550_i2c_master_recv(ab, bank, &bits, 1);
+                        if (err)
+                                goto unlock_and_return;
+                        reg_bits[1] = ((~bitmask & bits) |
+                                (bitmask & bitvalues));
+                }
+                /* Write the new value. */
+                err = ab3550_i2c_master_send(ab, bank, reg_bits, 2);
+unlock_and_return:
+                mutex_unlock(&ab->access_mutex);
+        }
+        return err;
+}
+
+/*
+ * Read/write permission checking functions.
+ */
+static bool page_write_allowed(const struct ab3550_reg_ranges *ranges,
+        u8 first_reg, u8 last_reg)
+{
+        u8 i;
+
+        if (last_reg < first_reg)
+                return false;
+
+        for (i = 0; i < ranges->count; i++) {
+                if (first_reg < ranges->range[i].first)
+                        break;
+                if ((last_reg <= ranges->range[i].last) &&
+                        (ranges->range[i].perm & AB3550_PERM_WR))
+                        return true;
+        }
+        return false;
+}
+
+static bool reg_write_allowed(const struct ab3550_reg_ranges *ranges, u8 reg)
+{
+        return page_write_allowed(ranges, reg, reg);
+}
+
+static bool page_read_allowed(const struct ab3550_reg_ranges *ranges,
+        u8 first_reg, u8 last_reg)
+{
+        u8 i;
+
+        if (last_reg < first_reg)
+                return false;
+        /* Find the range (if it exists in the list) that includes first_reg. */
+        for (i = 0; i < ranges->count; i++) {
+                if (first_reg < ranges->range[i].first)
+                        return false;
+                if (first_reg <= ranges->range[i].last)
+                        break;
+        }
+        /* Make sure that the entire range up to and including last_reg is
+         * readable. This may span several of the ranges in the list.
+         */
+        while ((i < ranges->count) &&
+                (ranges->range[i].perm & AB3550_PERM_RD)) {
+                if (last_reg <= ranges->range[i].last)
+                        return true;
+                if ((++i >= ranges->count) ||
+                        (ranges->range[i].first !=
+                         (ranges->range[i - 1].last + 1))) {
+                        break;
+                }
+        }
+        return false;
+}
+
+static bool reg_read_allowed(const struct ab3550_reg_ranges *ranges, u8 reg)
+{
+        return page_read_allowed(ranges, reg, reg);
+}
+
+/*
+ * The register access functionality.
+ */
+static int ab3550_get_chip_id(struct device *dev)
+{
+        struct ab3550 *ab = dev_get_drvdata(dev->parent);
+        return (int)ab->chip_id;
+}
+
+static int ab3550_mask_and_set_register_interruptible(struct device *dev,
+        u8 bank, u8 reg, u8 bitmask, u8 bitvalues)
+{
+        struct ab3550 *ab;
+        struct platform_device *pdev = to_platform_device(dev);
+
+        if ((AB3550_NUM_BANKS <= bank) ||
+                !reg_write_allowed(&ab3550_reg_ranges[pdev->id][bank], reg))
+                return -EINVAL;
+
+        ab = dev_get_drvdata(dev->parent);
+        return mask_and_set_register_interruptible(ab, bank, reg,
+                bitmask, bitvalues);
+}
+
+static int ab3550_set_register_interruptible(struct device *dev, u8 bank,
+        u8 reg, u8 value)
+{
+        return ab3550_mask_and_set_register_interruptible(dev, bank, reg, 0xFF,
+                value);
+}
+
+static int ab3550_get_register_interruptible(struct device *dev, u8 bank,
+        u8 reg, u8 *value)
+{
+        struct ab3550 *ab;
+        struct platform_device *pdev = to_platform_device(dev);
+
+        if ((AB3550_NUM_BANKS <= bank) ||
+                !reg_read_allowed(&ab3550_reg_ranges[pdev->id][bank], reg))
+                return -EINVAL;
+
+        ab = dev_get_drvdata(dev->parent);
+        return get_register_interruptible(ab, bank, reg, value);
+}
+
+static int ab3550_get_register_page_interruptible(struct device *dev, u8 bank,
+        u8 first_reg, u8 *regvals, u8 numregs)
+{
+        struct ab3550 *ab;
+        struct platform_device *pdev = to_platform_device(dev);
+
+        if ((AB3550_NUM_BANKS <= bank) ||
+                !page_read_allowed(&ab3550_reg_ranges[pdev->id][bank],
+                        first_reg, (first_reg + numregs - 1)))
+                return -EINVAL;
+
+        ab = dev_get_drvdata(dev->parent);
+        return get_register_page_interruptible(ab, bank, first_reg, regvals,
+                numregs);
+}
+
+static int ab3550_event_registers_startup_state_get(struct device *dev,
+        u8 *event)
+{
+        struct ab3550 *ab;
+
+        ab = dev_get_drvdata(dev->parent);
+        if (!ab->startup_events_read)
+                return -EAGAIN; /* Try again later */
+
+        memcpy(event, ab->startup_events, AB3550_NUM_EVENT_REG);
+        return 0;
+}
+
+static int ab3550_startup_irq_enabled(struct device *dev, unsigned int irq)
+{
+        struct ab3550 *ab;
+        struct ab3550_platform_data *plf_data;
+        bool val;
+
+        ab = irq_get_chip_data(irq);
+        plf_data = ab->i2c_client[0]->dev.platform_data;
+        irq -= plf_data->irq.base;
+        val = ((ab->startup_events[irq / 8] & BIT(irq % 8)) != 0);
+
+        return val;
+}
+
+static struct abx500_ops ab3550_ops = {
+        .get_chip_id = ab3550_get_chip_id,
+        .get_register = ab3550_get_register_interruptible,
+        .set_register = ab3550_set_register_interruptible,
+        .get_register_page = ab3550_get_register_page_interruptible,
+        .set_register_page = NULL,
+        .mask_and_set_register = ab3550_mask_and_set_register_interruptible,
+        .event_registers_startup_state_get =
+                ab3550_event_registers_startup_state_get,
+        .startup_irq_enabled = ab3550_startup_irq_enabled,
+};
+
+static irqreturn_t ab3550_irq_handler(int irq, void *data)
+{
+        struct ab3550 *ab = data;
+        int err;
+        unsigned int i;
+        u8 e[AB3550_NUM_EVENT_REG];
+        u8 *events;
+        unsigned long flags;
+
+        events = (ab->startup_events_read ? e : ab->startup_events);
+
+        err = get_register_page_interruptible(ab, AB3550_EVENT_BANK,
+                AB3550_EVENT_REG, events, AB3550_NUM_EVENT_REG);
+        if (err)
+                goto err_event_rd;
+
+        if (!ab->startup_events_read) {
+                dev_info(&ab->i2c_client[0]->dev,
+                        "startup events 0x%x,0x%x,0x%x,0x%x,0x%x\n",
+                        ab->startup_events[0], ab->startup_events[1],
+                        ab->startup_events[2], ab->startup_events[3],
+                        ab->startup_events[4]);
+                ab->startup_events_read = true;
+                goto out;
+        }
+
+        /* The two highest bits in event[4] are not used. */
+        events[4] &= 0x3f;
+
+        spin_lock_irqsave(&ab->event_lock, flags);
+        for (i = 0; i < AB3550_NUM_EVENT_REG; i++)
+                events[i] &= ~ab->event_mask[i];
+        spin_unlock_irqrestore(&ab->event_lock, flags);
+
+        for (i = 0; i < AB3550_NUM_EVENT_REG; i++) {
+                u8 bit;
+                u8 event_reg;
+
+                dev_dbg(&ab->i2c_client[0]->dev, "IRQ Event[%d]: 0x%2x\n",
+                        i, events[i]);
+
+                event_reg = events[i];
+                for (bit = 0; event_reg; bit++, event_reg /= 2) {
+                        if (event_reg % 2) {
+                                unsigned int irq;
+                                struct ab3550_platform_data *plf_data;
+
+                                plf_data = ab->i2c_client[0]->dev.platform_data;
+                                irq = plf_data->irq.base + (i * 8) + bit;
+                                handle_nested_irq(irq);
+                        }
+                }
+        }
+out:
+        return IRQ_HANDLED;
+
+err_event_rd:
+        dev_dbg(&ab->i2c_client[0]->dev, "error reading event registers\n");
+        return IRQ_HANDLED;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static struct ab3550_reg_ranges debug_ranges[AB3550_NUM_BANKS] = {
+        {
+                .count = 6,
+                .range = (struct ab3550_reg_range[]) {
+                        {
+                                .first = 0x00,
+                                .last = 0x0e,
+                        },
+                        {
+                                .first = 0x10,
+                                .last = 0x1a,
+                        },
+                        {
+                                .first = 0x1e,
+                                .last = 0x4f,
+                        },
+                        {
+                                .first = 0x51,
+                                .last = 0x63,
+                        },
+                        {
+                                .first = 0x65,
+                                .last = 0xa3,
+                        },
+                        {
+                                .first = 0xa5,
+                                .last = 0xa8,
+                        },
+                }
+        },
+        {
+                .count = 8,
+                .range = (struct ab3550_reg_range[]) {
+                        {
+                                .first = 0x00,
+                                .last = 0x0e,
+                        },
+                        {
+                                .first = 0x10,
+                                .last = 0x17,
+                        },
+                        {
+                                .first = 0x1a,
+                                .last = 0x1c,
+                        },
+                        {
+                                .first = 0x20,
+                                .last = 0x56,
+                        },
+                        {
+                                .first = 0x5a,
+                                .last = 0x88,
+                        },
+                        {
+                                .first = 0x8a,
+                                .last = 0xad,
+                        },
+                        {
+                                .first = 0xb0,
+                                .last = 0xba,
+                        },
+                        {
+                                .first = 0xbc,
+                                .last = 0xc3,
+                        },
+                }
+        },
+};
+
+static int ab3550_registers_print(struct seq_file *s, void *p)
+{
+        struct ab3550 *ab = s->private;
+        int bank;
+
+        seq_printf(s, AB3550_NAME_STRING " register values:\n");
+
+        for (bank = 0; bank < AB3550_NUM_BANKS; bank++) {
+                unsigned int i;
+
+                seq_printf(s, " bank %d:\n", bank);
+                for (i = 0; i < debug_ranges[bank].count; i++) {
+                        u8 reg;
+
+                        for (reg = debug_ranges[bank].range[i].first;
+                                reg <= debug_ranges[bank].range[i].last;
+                                reg++) {
+                                u8 value;
+
+                                get_register_interruptible(ab, bank, reg,
+                                        &value);
+                                seq_printf(s, "  [%d/0x%02X]: 0x%02X\n", bank,
+                                        reg, value);
+                        }
+                }
+        }
+        return 0;
+}
+
+static int ab3550_registers_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, ab3550_registers_print, inode->i_private);
+}
+
+static const struct file_operations ab3550_registers_fops = {
+        .open = ab3550_registers_open,
+        .read = seq_read,
+        .llseek = seq_lseek,
+        .release = single_release,
+        .owner = THIS_MODULE,
+};
+
+static int ab3550_bank_print(struct seq_file *s, void *p)
+{
+        struct ab3550 *ab = s->private;
+
+        seq_printf(s, "%d\n", ab->debug_bank);
+        return 0;
+}
+
+static int ab3550_bank_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, ab3550_bank_print, inode->i_private);
+}
+
+static ssize_t ab3550_bank_write(struct file *file,
+        const char __user *user_buf,
+        size_t count, loff_t *ppos)
+{
+        struct ab3550 *ab = ((struct seq_file *)(file->private_data))->private;
+        unsigned long user_bank;
+        int err;
+
+        /* Get userspace string and assure termination */
+        err = kstrtoul_from_user(user_buf, count, 0, &user_bank);
+        if (err)
+                return err;
+
+        if (user_bank >= AB3550_NUM_BANKS) {
+                dev_err(&ab->i2c_client[0]->dev,
+                        "debugfs error input > number of banks\n");
+                return -EINVAL;
+        }
+
+        ab->debug_bank = user_bank;
+
+        return count;
+}
+
+static int ab3550_address_print(struct seq_file *s, void *p)
+{
+        struct ab3550 *ab = s->private;
+
+        seq_printf(s, "0x%02X\n", ab->debug_address);
+        return 0;
+}
+
+static int ab3550_address_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, ab3550_address_print, inode->i_private);
+}
+
+static ssize_t ab3550_address_write(struct file *file,
+        const char __user *user_buf,
+        size_t count, loff_t *ppos)
+{
+        struct ab3550 *ab = ((struct seq_file *)(file->private_data))->private;
+        unsigned long user_address;
+        int err;
+
+        /* Get userspace string and assure termination */
+        err = kstrtoul_from_user(user_buf, count, 0, &user_address);
+        if (err)
+                return err;
+
+        if (user_address > 0xff) {
+                dev_err(&ab->i2c_client[0]->dev,
+                        "debugfs error input > 0xff\n");
+                return -EINVAL;
+        }
+        ab->debug_address = user_address;
+        return count;
+}
+
+static int ab3550_val_print(struct seq_file *s, void *p)
+{
+        struct ab3550 *ab = s->private;
+        int err;
+        u8 regvalue;
+
+        err = get_register_interruptible(ab, (u8)ab->debug_bank,
+                (u8)ab->debug_address, &regvalue);
+        if (err)
+                return -EINVAL;
+        seq_printf(s, "0x%02X\n", regvalue);
+
+        return 0;
+}
+
+static int ab3550_val_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, ab3550_val_print, inode->i_private);
+}
+
+static ssize_t ab3550_val_write(struct file *file,
+        const char __user *user_buf,
+        size_t count, loff_t *ppos)
+{
+        struct ab3550 *ab = ((struct seq_file *)(file->private_data))->private;
+        unsigned long user_val;
+        int err;
+        u8 regvalue;
+
+        /* Get userspace string and assure termination */
+        err = kstrtoul_from_user(user_buf, count, 0, &user_val);
+        if (err)
+                return err;
+
+        if (user_val > 0xff) {
+                dev_err(&ab->i2c_client[0]->dev,
+                        "debugfs error input > 0xff\n");
+                return -EINVAL;
+        }
+        err = mask_and_set_register_interruptible(
+                ab, (u8)ab->debug_bank,
+                (u8)ab->debug_address, 0xFF, (u8)user_val);
+        if (err)
+                return -EINVAL;
+
+        get_register_interruptible(ab, (u8)ab->debug_bank,
+                (u8)ab->debug_address, &regvalue);
+        if (err)
+                return -EINVAL;
+
+        return count;
+}
+
+static const struct file_operations ab3550_bank_fops = {
+        .open = ab3550_bank_open,
+        .write = ab3550_bank_write,
+        .read = seq_read,
+        .llseek = seq_lseek,
+        .release = single_release,
+        .owner = THIS_MODULE,
+};
+
+static const struct file_operations ab3550_address_fops = {
+        .open = ab3550_address_open,
+        .write = ab3550_address_write,
+        .read = seq_read,
+        .llseek = seq_lseek,
+        .release = single_release,
+        .owner = THIS_MODULE,
+};
+
+static const struct file_operations ab3550_val_fops = {
+        .open = ab3550_val_open,
+        .write = ab3550_val_write,
+        .read = seq_read,
+        .llseek = seq_lseek,
+        .release = single_release,
+        .owner = THIS_MODULE,
+};
+
+static struct dentry *ab3550_dir;
+static struct dentry *ab3550_reg_file;
+static struct dentry *ab3550_bank_file;
+static struct dentry *ab3550_address_file;
+static struct dentry *ab3550_val_file;
+
+static inline void ab3550_setup_debugfs(struct ab3550 *ab)
+{
+        ab->debug_bank = 0;
+        ab->debug_address = 0x00;
+
+        ab3550_dir = debugfs_create_dir(AB3550_NAME_STRING, NULL);
+        if (!ab3550_dir)
+                goto exit_no_debugfs;
+
+        ab3550_reg_file = debugfs_create_file("all-registers",
+                S_IRUGO, ab3550_dir, ab, &ab3550_registers_fops);
+        if (!ab3550_reg_file)
+                goto exit_destroy_dir;
+
+        ab3550_bank_file = debugfs_create_file("register-bank",
+                (S_IRUGO | S_IWUSR), ab3550_dir, ab, &ab3550_bank_fops);
+        if (!ab3550_bank_file)
+                goto exit_destroy_reg;
+
+        ab3550_address_file = debugfs_create_file("register-address",
+                (S_IRUGO | S_IWUSR), ab3550_dir, ab, &ab3550_address_fops);
+        if (!ab3550_address_file)
+                goto exit_destroy_bank;
+
+        ab3550_val_file = debugfs_create_file("register-value",
+                (S_IRUGO | S_IWUSR), ab3550_dir, ab, &ab3550_val_fops);
+        if (!ab3550_val_file)
+                goto exit_destroy_address;
+
+        return;
+
+exit_destroy_address:
+        debugfs_remove(ab3550_address_file);
+exit_destroy_bank:
+        debugfs_remove(ab3550_bank_file);
+exit_destroy_reg:
+        debugfs_remove(ab3550_reg_file);
+exit_destroy_dir:
+        debugfs_remove(ab3550_dir);
+exit_no_debugfs:
+        dev_err(&ab->i2c_client[0]->dev, "failed to create debugfs entries.\n");
+        return;
+}
+
+static inline void ab3550_remove_debugfs(void)
+{
+        debugfs_remove(ab3550_val_file);
+        debugfs_remove(ab3550_address_file);
+        debugfs_remove(ab3550_bank_file);
+        debugfs_remove(ab3550_reg_file);
+        debugfs_remove(ab3550_dir);
+}
+
+#else /* !CONFIG_DEBUG_FS */
+static inline void ab3550_setup_debugfs(struct ab3550 *ab)
+{
+}
+static inline void ab3550_remove_debugfs(void)
+{
+}
+#endif
+
+/*
+ * Basic set-up, datastructure creation/destruction and I2C interface.
+ * This sets up a default config in the AB3550 chip so that it
+ * will work as expected.
+ */
+static int __init ab3550_setup(struct ab3550 *ab)
+{
+        int err = 0;
+        int i;
+        struct ab3550_platform_data *plf_data;
+        struct abx500_init_settings *settings;
+
+        plf_data = ab->i2c_client[0]->dev.platform_data;
+        settings = plf_data->init_settings;
+
+        for (i = 0; i < plf_data->init_settings_sz; i++) {
+                err = mask_and_set_register_interruptible(ab,
+                        settings[i].bank,
+                        settings[i].reg,
+                        0xFF, settings[i].setting);
+                if (err)
+                        goto exit_no_setup;
+
+                /* If event mask register update the event mask in ab3550 */
+                if ((settings[i].bank == 0) &&
+                        (AB3550_IMR1 <= settings[i].reg) &&
+                        (settings[i].reg <= AB3550_IMR5)) {
+                        ab->event_mask[settings[i].reg - AB3550_IMR1] =
+                                settings[i].setting;
+                }
+        }
+exit_no_setup:
+        return err;
+}
+
+static void ab3550_mask_work(struct work_struct *work)
+{
+        struct ab3550 *ab = container_of(work, struct ab3550, mask_work);
+        int i;
+        unsigned long flags;
+        u8 mask[AB3550_NUM_EVENT_REG];
+
+        spin_lock_irqsave(&ab->event_lock, flags);
+        for (i = 0; i < AB3550_NUM_EVENT_REG; i++)
+                mask[i] = ab->event_mask[i];
+        spin_unlock_irqrestore(&ab->event_lock, flags);
+
+        for (i = 0; i < AB3550_NUM_EVENT_REG; i++) {
+                int err;
+
+                err = mask_and_set_register_interruptible(ab, 0,
+                        (AB3550_IMR1 + i), ~0, mask[i]);
+                if (err)
+                        dev_err(&ab->i2c_client[0]->dev,
+                                "ab3550_mask_work failed 0x%x,0x%x\n",
+                                (AB3550_IMR1 + i), mask[i]);
+        }
+}
+
+static void ab3550_mask(struct irq_data *data)
+{
+        unsigned long flags;
+        struct ab3550 *ab;
+        struct ab3550_platform_data *plf_data;
+        int irq;
+
+        ab = irq_data_get_irq_chip_data(data);
+        plf_data = ab->i2c_client[0]->dev.platform_data;
+        irq = data->irq - plf_data->irq.base;
+
+        spin_lock_irqsave(&ab->event_lock, flags);
+        ab->event_mask[irq / 8] |= BIT(irq % 8);
+        spin_unlock_irqrestore(&ab->event_lock, flags);
+
+        schedule_work(&ab->mask_work);
+}
+
+static void ab3550_unmask(struct irq_data *data)
+{
+        unsigned long flags;
+        struct ab3550 *ab;
+        struct ab3550_platform_data *plf_data;
+        int irq;
+
+        ab = irq_data_get_irq_chip_data(data);
+        plf_data = ab->i2c_client[0]->dev.platform_data;
+        irq = data->irq - plf_data->irq.base;
+
+        spin_lock_irqsave(&ab->event_lock, flags);
+        ab->event_mask[irq / 8] &= ~BIT(irq % 8);
+        spin_unlock_irqrestore(&ab->event_lock, flags);
+
+        schedule_work(&ab->mask_work);
+}
+
+static void noop(struct irq_data *data)
+{
+}
+
+static struct irq_chip ab3550_irq_chip = {
+        .name           = "ab3550-core", /* Keep the same name as the request */
+        .irq_disable    = ab3550_mask, /* No default to mask in chip.c */
+        .irq_ack        = noop,
+        .irq_mask       = ab3550_mask,
+        .irq_unmask     = ab3550_unmask,
+};
+
+struct ab_family_id {
+        u8      id;
+        char    *name;
+};
+
+static const struct ab_family_id ids[] __initdata = {
+        /* AB3550 */
+        {
+                .id = AB3550_P1A,
+                .name = "P1A"
+        },
+        /* Terminator */
+        {
+                .id = 0x00,
+        }
+};
+
+static int __init ab3550_probe(struct i2c_client *client,
+        const struct i2c_device_id *id)
+{
+        struct ab3550 *ab;
+        struct ab3550_platform_data *ab3550_plf_data =
+                client->dev.platform_data;
+        int err;
+        int i;
+        int num_i2c_clients = 0;
+
+        ab = kzalloc(sizeof(struct ab3550), GFP_KERNEL);
+        if (!ab) {
+                dev_err(&client->dev,
+                        "could not allocate " AB3550_NAME_STRING " device\n");
+                return -ENOMEM;
+        }
+
+        /* Initialize data structure */
+        mutex_init(&ab->access_mutex);
+        spin_lock_init(&ab->event_lock);
+        ab->i2c_client[0] = client;
+
+        i2c_set_clientdata(client, ab);
+
+        /* Read chip ID register */
+        err = get_register_interruptible(ab, 0, AB3550_CID_REG, &ab->chip_id);
+        if (err) {
+                dev_err(&client->dev, "could not communicate with the analog "
+                        "baseband chip\n");
+                goto exit_no_detect;
+        }
+
+        for (i = 0; ids[i].id != 0x0; i++) {
+                if (ids[i].id == ab->chip_id) {
+                        snprintf(&ab->chip_name[0], sizeof(ab->chip_name) - 1,
+                                AB3550_ID_FORMAT_STRING, ids[i].name);
+                        break;
+                }
+        }
+
+        if (ids[i].id == 0x0) {
+                dev_err(&client->dev, "unknown analog baseband chip id: 0x%x\n",
+                        ab->chip_id);
+                dev_err(&client->dev, "driver not started!\n");
+                goto exit_no_detect;
+        }
+
+        dev_info(&client->dev, "detected AB chip: %s\n", &ab->chip_name[0]);
+
+        /* Attach other dummy I2C clients. */
+        while (++num_i2c_clients < AB3550_NUM_BANKS) {
+                ab->i2c_client[num_i2c_clients] =
+                        i2c_new_dummy(client->adapter,
+                                (client->addr + num_i2c_clients));
+                if (!ab->i2c_client[num_i2c_clients]) {
+                        err = -ENOMEM;
+                        goto exit_no_dummy_client;
+                }
+                strlcpy(ab->i2c_client[num_i2c_clients]->name, id->name,
+                        sizeof(ab->i2c_client[num_i2c_clients]->name));
+        }
+
+        err = ab3550_setup(ab);
+        if (err)
+                goto exit_no_setup;
+
+        INIT_WORK(&ab->mask_work, ab3550_mask_work);
+
+        for (i = 0; i < ab3550_plf_data->irq.count; i++) {
+                unsigned int irq;
+
+                irq = ab3550_plf_data->irq.base + i;
+                irq_set_chip_data(irq, ab);
+                irq_set_chip_and_handler(irq, &ab3550_irq_chip,
+                                         handle_simple_irq);
+                irq_set_nested_thread(irq, 1);
+#ifdef CONFIG_ARM
+                set_irq_flags(irq, IRQF_VALID);
+#else
+                irq_set_noprobe(irq);
+#endif
+        }
+
+        err = request_threaded_irq(client->irq, NULL, ab3550_irq_handler,
+                IRQF_ONESHOT, "ab3550-core", ab);
+        /* This real unpredictable IRQ is of course sampled for entropy */
+        rand_initialize_irq(client->irq);
+
+        if (err)
+                goto exit_no_irq;
+
+        err = abx500_register_ops(&client->dev, &ab3550_ops);
+        if (err)
+                goto exit_no_ops;
+
+        /* Set up and register the platform devices. */
+        for (i = 0; i < AB3550_NUM_DEVICES; i++) {
+                ab3550_devs[i].platform_data = ab3550_plf_data->dev_data[i];
+                ab3550_devs[i].pdata_size = ab3550_plf_data->dev_data_sz[i];
+        }
+
+        err = mfd_add_devices(&client->dev, 0, ab3550_devs,
+                ARRAY_SIZE(ab3550_devs), NULL,
+                ab3550_plf_data->irq.base);
+
+        ab3550_setup_debugfs(ab);
+
+        return 0;
+
+exit_no_ops:
+exit_no_irq:
+exit_no_setup:
+exit_no_dummy_client:
+        /* Unregister the dummy i2c clients. */
+        while (--num_i2c_clients)
+                i2c_unregister_device(ab->i2c_client[num_i2c_clients]);
+exit_no_detect:
+        kfree(ab);
+        return err;
+}
+
+static int __exit ab3550_remove(struct i2c_client *client)
+{
+        struct ab3550 *ab = i2c_get_clientdata(client);
+        int num_i2c_clients = AB3550_NUM_BANKS;
+
+        mfd_remove_devices(&client->dev);
+        ab3550_remove_debugfs();
+
+        while (--num_i2c_clients)
+                i2c_unregister_device(ab->i2c_client[num_i2c_clients]);
+
+        /*
+         * At this point, all subscribers should have unregistered
+         * their notifiers so deactivate IRQ
+         */
+        free_irq(client->irq, ab);
+        kfree(ab);
+        return 0;
+}
+
+static const struct i2c_device_id ab3550_id[] = {
+        {AB3550_NAME_STRING, 0},
+        {}
+};
+MODULE_DEVICE_TABLE(i2c, ab3550_id);
+
+static struct i2c_driver ab3550_driver = {
+        .driver = {
+                .name   = AB3550_NAME_STRING,
+                .owner  = THIS_MODULE,
+        },
+        .id_table       = ab3550_id,
+        .probe          = ab3550_probe,
+        .remove         = __exit_p(ab3550_remove),
+};
+
+static int __init ab3550_i2c_init(void)
+{
+        return i2c_add_driver(&ab3550_driver);
+}
+
+static void __exit ab3550_i2c_exit(void)
+{
+        i2c_del_driver(&ab3550_driver);
+}
+
+subsys_initcall(ab3550_i2c_init);
+module_exit(ab3550_i2c_exit);
+
+MODULE_AUTHOR("Mattias Wallin <mattias.wallin@stericsson.com>");
+MODULE_DESCRIPTION("AB3550 core driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/ab8500-i2c.c b/drivers/mfd/ab8500-i2c.c
new file mode 100644
index 00000000000..9be541c6b00
--- /dev/null
+++ b/drivers/mfd/ab8500-i2c.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ * Author: Mattias Wallin <mattias.wallin@stericsson.com> for ST-Ericsson.
+ * License Terms: GNU General Public License v2
+ * This file was based on drivers/mfd/ab8500-spi.c
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/ab8500.h>
+#include <linux/mfd/db8500-prcmu.h>
+
+static int ab8500_i2c_write(struct ab8500 *ab8500, u16 addr, u8 data)
+{
+        int ret;
+
+        ret = prcmu_abb_write((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
+        if (ret < 0)
+                dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
+        return ret;
+}
+
+static int ab8500_i2c_read(struct ab8500 *ab8500, u16 addr)
+{
+        int ret;
+        u8 data;
+
+        ret = prcmu_abb_read((u8)(addr >> 8), (u8)(addr & 0xFF), &data, 1);
+        if (ret < 0) {
+                dev_err(ab8500->dev, "prcmu i2c error %d\n", ret);
+                return ret;
+        }
+        return (int)data;
+}
+
+static int __devinit ab8500_i2c_probe(struct platform_device *plf)
+{
+        struct ab8500 *ab8500;
+        struct resource *resource;
+        int ret;
+
+        ab8500 = kzalloc(sizeof *ab8500, GFP_KERNEL);
+        if (!ab8500)
+                return -ENOMEM;
+
+        ab8500->dev = &plf->dev;
+
+        resource = platform_get_resource(plf, IORESOURCE_IRQ, 0);
+        if (!resource) {
+                kfree(ab8500);
+                return -ENODEV;
+        }
+
+        ab8500->irq = resource->start;
+
+        ab8500->read = ab8500_i2c_read;
+        ab8500->write = ab8500_i2c_write;
+
+        platform_set_drvdata(plf, ab8500);
+
+        ret = ab8500_init(ab8500);
+        if (ret)
+                kfree(ab8500);
+
+        return ret;
+}
+
+static int __devexit ab8500_i2c_remove(struct platform_device *plf)
+{
+        struct ab8500 *ab8500 = platform_get_drvdata(plf);
+
+        ab8500_exit(ab8500);
+        kfree(ab8500);
+
+        return 0;
+}
+
+static struct platform_driver ab8500_i2c_driver = {
+        .driver = {
+                .name = "ab8500-i2c",
+                .owner = THIS_MODULE,
+        },
+        .probe  = ab8500_i2c_probe,
+        .remove = __devexit_p(ab8500_i2c_remove)
+};
+
+static int __init ab8500_i2c_init(void)
+{
+        return platform_driver_register(&ab8500_i2c_driver);
+}
+
+static void __exit ab8500_i2c_exit(void)
+{
+        platform_driver_unregister(&ab8500_i2c_driver);
+}
+arch_initcall(ab8500_i2c_init);
+module_exit(ab8500_i2c_exit);
+
+MODULE_AUTHOR("Mattias WALLIN <mattias.wallin@stericsson.com");
+MODULE_DESCRIPTION("AB8500 Core access via PRCMU I2C");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/mfd/db5500-prcmu-regs.h b/drivers/mfd/db5500-prcmu-regs.h
new file mode 100644
index 00000000000..9a8e9e4ddd3
--- /dev/null
+++ b/drivers/mfd/db5500-prcmu-regs.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * PRCM Unit registers
+ */
+
+#ifndef __MACH_PRCMU_REGS_H
+#define __MACH_PRCMU_REGS_H
+
+#include <mach/hardware.h>
+
+#define PRCM_ARM_PLLDIVPS       (_PRCMU_BASE + 0x118)
+#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE          0x3f
+#define PRCM_ARM_PLLDIVPS_MAX_MASK              0xf
+
+#define PRCM_PLLARM_LOCKP       (_PRCMU_BASE + 0x0a8)
+#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3    0x2
+
+#define PRCM_ARM_CHGCLKREQ      (_PRCMU_BASE + 0x114)
+#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ   0x1
+
+#define PRCM_PLLARM_ENABLE      (_PRCMU_BASE + 0x98)
+#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE   0x1
+#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON  0x100
+
+#define PRCM_ARMCLKFIX_MGT      (_PRCMU_BASE + 0x0)
+#define PRCM_A9_RESETN_CLR      (_PRCMU_BASE + 0x1f4)
+#define PRCM_A9_RESETN_SET      (_PRCMU_BASE + 0x1f0)
+#define PRCM_ARM_LS_CLAMP       (_PRCMU_BASE + 0x30c)
+#define PRCM_SRAM_A9            (_PRCMU_BASE + 0x308)
+
+/* ARM WFI Standby signal register */
+#define PRCM_ARM_WFI_STANDBY    (_PRCMU_BASE + 0x130)
+#define PRCM_IOCR               (_PRCMU_BASE + 0x310)
+#define PRCM_IOCR_IOFORCE                       0x1
+
+/* CPU mailbox registers */
+#define PRCM_MBOX_CPU_VAL       (_PRCMU_BASE + 0x0fc)
+#define PRCM_MBOX_CPU_SET       (_PRCMU_BASE + 0x100)
+#define PRCM_MBOX_CPU_CLR       (_PRCMU_BASE + 0x104)
+
+/* Dual A9 core interrupt management unit registers */
+#define PRCM_A9_MASK_REQ        (_PRCMU_BASE + 0x328)
+#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ       0x1
+
+#define PRCM_A9_MASK_ACK        (_PRCMU_BASE + 0x32c)
+#define PRCM_ARMITMSK31TO0      (_PRCMU_BASE + 0x11c)
+#define PRCM_ARMITMSK63TO32     (_PRCMU_BASE + 0x120)
+#define PRCM_ARMITMSK95TO64     (_PRCMU_BASE + 0x124)
+#define PRCM_ARMITMSK127TO96    (_PRCMU_BASE + 0x128)
+#define PRCM_POWER_STATE_VAL    (_PRCMU_BASE + 0x25C)
+#define PRCM_ARMITVAL31TO0      (_PRCMU_BASE + 0x260)
+#define PRCM_ARMITVAL63TO32     (_PRCMU_BASE + 0x264)
+#define PRCM_ARMITVAL95TO64     (_PRCMU_BASE + 0x268)
+#define PRCM_ARMITVAL127TO96    (_PRCMU_BASE + 0x26C)
+
+#define PRCM_HOSTACCESS_REQ     (_PRCMU_BASE + 0x334)
+#define ARM_WAKEUP_MODEM        0x1
+
+#define PRCM_ARM_IT1_CLEAR      (_PRCMU_BASE + 0x48C)
+#define PRCM_ARM_IT1_VAL        (_PRCMU_BASE + 0x494)
+#define PRCM_HOLD_EVT           (_PRCMU_BASE + 0x174)
+
+#define PRCM_ITSTATUS0          (_PRCMU_BASE + 0x148)
+#define PRCM_ITSTATUS1          (_PRCMU_BASE + 0x150)
+#define PRCM_ITSTATUS2          (_PRCMU_BASE + 0x158)
+#define PRCM_ITSTATUS3          (_PRCMU_BASE + 0x160)
+#define PRCM_ITSTATUS4          (_PRCMU_BASE + 0x168)
+#define PRCM_ITSTATUS5          (_PRCMU_BASE + 0x484)
+#define PRCM_ITCLEAR5           (_PRCMU_BASE + 0x488)
+#define PRCM_ARMIT_MASKXP70_IT  (_PRCMU_BASE + 0x1018)
+
+/* System reset register */
+#define PRCM_APE_SOFTRST        (_PRCMU_BASE + 0x228)
+
+/* Level shifter and clamp control registers */
+#define PRCM_MMIP_LS_CLAMP_SET     (_PRCMU_BASE + 0x420)
+#define PRCM_MMIP_LS_CLAMP_CLR     (_PRCMU_BASE + 0x424)
+
+/* PRCMU clock/PLL/reset registers */
+#define PRCM_PLLDSI_FREQ           (_PRCMU_BASE + 0x500)
+#define PRCM_PLLDSI_ENABLE         (_PRCMU_BASE + 0x504)
+#define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)
+#define PRCM_LCDCLK_MGT            (_PRCMU_BASE + 0x044)
+#define PRCM_MCDECLK_MGT           (_PRCMU_BASE + 0x064)
+#define PRCM_HDMICLK_MGT           (_PRCMU_BASE + 0x058)
+#define PRCM_TVCLK_MGT             (_PRCMU_BASE + 0x07c)
+#define PRCM_DSI_PLLOUT_SEL        (_PRCMU_BASE + 0x530)
+#define PRCM_DSITVCLK_DIV          (_PRCMU_BASE + 0x52C)
+#define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)
+#define PRCM_APE_RESETN_SET        (_PRCMU_BASE + 0x1E4)
+#define PRCM_APE_RESETN_CLR        (_PRCMU_BASE + 0x1E8)
+#define PRCM_CLKOCR                (_PRCMU_BASE + 0x1CC)
+
+/* ePOD and memory power signal control registers */
+#define PRCM_EPOD_C_SET            (_PRCMU_BASE + 0x410)
+#define PRCM_SRAM_LS_SLEEP         (_PRCMU_BASE + 0x304)
+
+/* Debug power control unit registers */
+#define PRCM_POWER_STATE_SET       (_PRCMU_BASE + 0x254)
+
+/* Miscellaneous unit registers */
+#define PRCM_DSI_SW_RESET          (_PRCMU_BASE + 0x324)
+#define PRCM_GPIOCR                (_PRCMU_BASE + 0x138)
+#define PRCM_GPIOCR_DBG_STM_MOD_CMD1            0x800
+#define PRCM_GPIOCR_DBG_UARTMOD_CMD0            0x1
+
+
+#endif /* __MACH_PRCMU__REGS_H */
diff --git a/drivers/mfd/db5500-prcmu.c b/drivers/mfd/db5500-prcmu.c
new file mode 100644
index 00000000000..9dbb3cab4a6
--- /dev/null
+++ b/drivers/mfd/db5500-prcmu.c
@@ -0,0 +1,448 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
+ *
+ * U5500 PRCM Unit interface driver
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/mutex.h>
+#include <linux/completion.h>
+#include <linux/irq.h>
+#include <linux/jiffies.h>
+#include <linux/bitops.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/db5500-prcmu.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/db5500-regs.h>
+#include "db5500-prcmu-regs.h"
+
+#define _PRCM_MB_HEADER (tcdm_base + 0xFE8)
+#define PRCM_REQ_MB0_HEADER (_PRCM_MB_HEADER + 0x0)
+#define PRCM_REQ_MB1_HEADER (_PRCM_MB_HEADER + 0x1)
+#define PRCM_REQ_MB2_HEADER (_PRCM_MB_HEADER + 0x2)
+#define PRCM_REQ_MB3_HEADER (_PRCM_MB_HEADER + 0x3)
+#define PRCM_REQ_MB4_HEADER (_PRCM_MB_HEADER + 0x4)
+#define PRCM_REQ_MB5_HEADER (_PRCM_MB_HEADER + 0x5)
+#define PRCM_REQ_MB6_HEADER (_PRCM_MB_HEADER + 0x6)
+#define PRCM_REQ_MB7_HEADER (_PRCM_MB_HEADER + 0x7)
+#define PRCM_ACK_MB0_HEADER (_PRCM_MB_HEADER + 0x8)
+#define PRCM_ACK_MB1_HEADER (_PRCM_MB_HEADER + 0x9)
+#define PRCM_ACK_MB2_HEADER (_PRCM_MB_HEADER + 0xa)
+#define PRCM_ACK_MB3_HEADER (_PRCM_MB_HEADER + 0xb)
+#define PRCM_ACK_MB4_HEADER (_PRCM_MB_HEADER + 0xc)
+#define PRCM_ACK_MB5_HEADER (_PRCM_MB_HEADER + 0xd)
+#define PRCM_ACK_MB6_HEADER (_PRCM_MB_HEADER + 0xe)
+#define PRCM_ACK_MB7_HEADER (_PRCM_MB_HEADER + 0xf)
+
+/* Req Mailboxes */
+#define PRCM_REQ_MB0 (tcdm_base + 0xFD8)
+#define PRCM_REQ_MB1 (tcdm_base + 0xFCC)
+#define PRCM_REQ_MB2 (tcdm_base + 0xFC4)
+#define PRCM_REQ_MB3 (tcdm_base + 0xFC0)
+#define PRCM_REQ_MB4 (tcdm_base + 0xF98)
+#define PRCM_REQ_MB5 (tcdm_base + 0xF90)
+#define PRCM_REQ_MB6 (tcdm_base + 0xF8C)
+#define PRCM_REQ_MB7 (tcdm_base + 0xF84)
+
+/* Ack Mailboxes */
+#define PRCM_ACK_MB0 (tcdm_base + 0xF38)
+#define PRCM_ACK_MB1 (tcdm_base + 0xF30)
+#define PRCM_ACK_MB2 (tcdm_base + 0xF24)
+#define PRCM_ACK_MB3 (tcdm_base + 0xF20)
+#define PRCM_ACK_MB4 (tcdm_base + 0xF1C)
+#define PRCM_ACK_MB5 (tcdm_base + 0xF14)
+#define PRCM_ACK_MB6 (tcdm_base + 0xF0C)
+#define PRCM_ACK_MB7 (tcdm_base + 0xF08)
+
+enum mb_return_code {
+        RC_SUCCESS,
+        RC_FAIL,
+};
+
+/* Mailbox 0 headers. */
+enum mb0_header {
+        /* request */
+        RMB0H_PWR_STATE_TRANS = 1,
+        RMB0H_WAKE_UP_CFG,
+        RMB0H_RD_WAKE_UP_ACK,
+        /* acknowledge */
+        AMB0H_WAKE_UP = 1,
+};
+
+/* Mailbox 5 headers. */
+enum mb5_header {
+        MB5H_I2C_WRITE = 1,
+        MB5H_I2C_READ,
+};
+
+/* Request mailbox 5 fields. */
+#define PRCM_REQ_MB5_I2C_SLAVE (PRCM_REQ_MB5 + 0)
+#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 1)
+#define PRCM_REQ_MB5_I2C_SIZE (PRCM_REQ_MB5 + 2)
+#define PRCM_REQ_MB5_I2C_DATA (PRCM_REQ_MB5 + 4)
+
+/* Acknowledge mailbox 5 fields. */
+#define PRCM_ACK_MB5_RETURN_CODE (PRCM_ACK_MB5 + 0)
+#define PRCM_ACK_MB5_I2C_DATA (PRCM_ACK_MB5 + 4)
+
+#define NUM_MB 8
+#define MBOX_BIT BIT
+#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
+
+/*
+* Used by MCDE to setup all necessary PRCMU registers
+*/
+#define PRCMU_RESET_DSIPLL                      0x00004000
+#define PRCMU_UNCLAMP_DSIPLL                    0x00400800
+
+/* HDMI CLK MGT PLLSW=001 (PLLSOC0), PLLDIV=0x8, = 50 Mhz*/
+#define PRCMU_DSI_CLOCK_SETTING                 0x00000128
+/* TVCLK_MGT PLLSW=001 (PLLSOC0) PLLDIV=0x13, = 19.05 MHZ */
+#define PRCMU_DSI_LP_CLOCK_SETTING              0x00000135
+#define PRCMU_PLLDSI_FREQ_SETTING               0x0004013C
+#define PRCMU_DSI_PLLOUT_SEL_SETTING            0x00000002
+#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV           0x03000101
+#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV          0x00000101
+
+#define PRCMU_ENABLE_PLLDSI                     0x00000001
+#define PRCMU_DISABLE_PLLDSI                    0x00000000
+
+#define PRCMU_DSI_RESET_SW                      0x00000003
+
+#define PRCMU_PLLDSI_LOCKP_LOCKED               0x3
+
+/*
+ * mb0_transfer - state needed for mailbox 0 communication.
+ * @lock:               The transaction lock.
+ */
+static struct {
+        spinlock_t lock;
+} mb0_transfer;
+
+/*
+ * mb5_transfer - state needed for mailbox 5 communication.
+ * @lock:       The transaction lock.
+ * @work:       The transaction completion structure.
+ * @ack:        Reply ("acknowledge") data.
+ */
+static struct {
+        struct mutex lock;
+        struct completion work;
+        struct {
+                u8 header;
+                u8 status;
+                u8 value[4];
+        } ack;
+} mb5_transfer;
+
+/* PRCMU TCDM base IO address. */
+static __iomem void *tcdm_base;
+
+/**
+ * db5500_prcmu_abb_read() - Read register value(s) from the ABB.
+ * @slave:      The I2C slave address.
+ * @reg:        The (start) register address.
+ * @value:      The read out value(s).
+ * @size:       The number of registers to read.
+ *
+ * Reads register value(s) from the ABB.
+ * @size has to be <= 4.
+ */
+int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
+{
+        int r;
+
+        if ((size < 1) || (4 < size))
+                return -EINVAL;
+
+        mutex_lock(&mb5_transfer.lock);
+
+        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
+                cpu_relax();
+        writeb(slave, PRCM_REQ_MB5_I2C_SLAVE);
+        writeb(reg, PRCM_REQ_MB5_I2C_REG);
+        writeb(size, PRCM_REQ_MB5_I2C_SIZE);
+        writeb(MB5H_I2C_READ, PRCM_REQ_MB5_HEADER);
+
+        writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
+        wait_for_completion(&mb5_transfer.work);
+
+        r = 0;
+        if ((mb5_transfer.ack.header == MB5H_I2C_READ) &&
+                (mb5_transfer.ack.status == RC_SUCCESS))
+                memcpy(value, mb5_transfer.ack.value, (size_t)size);
+        else
+                r = -EIO;
+
+        mutex_unlock(&mb5_transfer.lock);
+
+        return r;
+}
+
+/**
+ * db5500_prcmu_abb_write() - Write register value(s) to the ABB.
+ * @slave:      The I2C slave address.
+ * @reg:        The (start) register address.
+ * @value:      The value(s) to write.
+ * @size:       The number of registers to write.
+ *
+ * Writes register value(s) to the ABB.
+ * @size has to be <= 4.
+ */
+int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
+{
+        int r;
+
+        if ((size < 1) || (4 < size))
+                return -EINVAL;
+
+        mutex_lock(&mb5_transfer.lock);
+
+        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
+                cpu_relax();
+        writeb(slave, PRCM_REQ_MB5_I2C_SLAVE);
+        writeb(reg, PRCM_REQ_MB5_I2C_REG);
+        writeb(size, PRCM_REQ_MB5_I2C_SIZE);
+        memcpy_toio(PRCM_REQ_MB5_I2C_DATA, value, size);
+        writeb(MB5H_I2C_WRITE, PRCM_REQ_MB5_HEADER);
+
+        writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
+        wait_for_completion(&mb5_transfer.work);
+
+        if ((mb5_transfer.ack.header == MB5H_I2C_WRITE) &&
+                (mb5_transfer.ack.status == RC_SUCCESS))
+                r = 0;
+        else
+                r = -EIO;
+
+        mutex_unlock(&mb5_transfer.lock);
+
+        return r;
+}
+
+int db5500_prcmu_enable_dsipll(void)
+{
+        int i;
+
+        /* Enable DSIPLL_RESETN resets */
+        writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
+        /* Unclamp DSIPLL in/out */
+        writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
+        /* Set DSI PLL FREQ */
+        writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
+        writel(PRCMU_DSI_PLLOUT_SEL_SETTING,
+                PRCM_DSI_PLLOUT_SEL);
+        /* Enable Escape clocks */
+        writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
+
+        /* Start DSI PLL */
+        writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
+        /* Reset DSI PLL */
+        writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
+        for (i = 0; i < 10; i++) {
+                if ((readl(PRCM_PLLDSI_LOCKP) &
+                        PRCMU_PLLDSI_LOCKP_LOCKED) == PRCMU_PLLDSI_LOCKP_LOCKED)
+                        break;
+                udelay(100);
+        }
+        /* Release DSIPLL_RESETN */
+        writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
+        return 0;
+}
+
+int db5500_prcmu_disable_dsipll(void)
+{
+        /* Disable dsi pll */
+        writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
+        /* Disable  escapeclock */
+        writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
+        return 0;
+}
+
+int db5500_prcmu_set_display_clocks(void)
+{
+        /* HDMI and TVCLK Should be handled somewhere else */
+        /* PLLDIV=8, PLLSW=2, CLKEN=1 */
+        writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
+        /* PLLDIV=14, PLLSW=2, CLKEN=1 */
+        writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
+        return 0;
+}
+
+static void ack_dbb_wakeup(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&mb0_transfer.lock, flags);
+
+        while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
+                cpu_relax();
+
+        writeb(RMB0H_RD_WAKE_UP_ACK, PRCM_REQ_MB0_HEADER);
+        writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
+
+        spin_unlock_irqrestore(&mb0_transfer.lock, flags);
+}
+
+static inline void print_unknown_header_warning(u8 n, u8 header)
+{
+        pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
+                header, n);
+}
+
+static bool read_mailbox_0(void)
+{
+        bool r;
+        u8 header;
+
+        header = readb(PRCM_ACK_MB0_HEADER);
+        switch (header) {
+        case AMB0H_WAKE_UP:
+                r = true;
+                break;
+        default:
+                print_unknown_header_warning(0, header);
+                r = false;
+                break;
+        }
+        writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
+        return r;
+}
+
+static bool read_mailbox_1(void)
+{
+        writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
+        return false;
+}
+
+static bool read_mailbox_2(void)
+{
+        writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR);
+        return false;
+}
+
+static bool read_mailbox_3(void)
+{
+        writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR);
+        return false;
+}
+
+static bool read_mailbox_4(void)
+{
+        writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR);
+        return false;
+}
+
+static bool read_mailbox_5(void)
+{
+        u8 header;
+
+        header = readb(PRCM_ACK_MB5_HEADER);
+        switch (header) {
+        case MB5H_I2C_READ:
+                memcpy_fromio(mb5_transfer.ack.value, PRCM_ACK_MB5_I2C_DATA, 4);
+        case MB5H_I2C_WRITE:
+                mb5_transfer.ack.header = header;
+                mb5_transfer.ack.status = readb(PRCM_ACK_MB5_RETURN_CODE);
+                complete(&mb5_transfer.work);
+                break;
+        default:
+                print_unknown_header_warning(5, header);
+                break;
+        }
+        writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR);
+        return false;
+}
+
+static bool read_mailbox_6(void)
+{
+        writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR);
+        return false;
+}
+
+static bool read_mailbox_7(void)
+{
+        writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR);
+        return false;
+}
+
+static bool (* const read_mailbox[NUM_MB])(void) = {
+        read_mailbox_0,
+        read_mailbox_1,
+        read_mailbox_2,
+        read_mailbox_3,
+        read_mailbox_4,
+        read_mailbox_5,
+        read_mailbox_6,
+        read_mailbox_7
+};
+
+static irqreturn_t prcmu_irq_handler(int irq, void *data)
+{
+        u32 bits;
+        u8 n;
+        irqreturn_t r;
+
+        bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
+        if (unlikely(!bits))
+                return IRQ_NONE;
+
+        r = IRQ_HANDLED;
+        for (n = 0; bits; n++) {
+                if (bits & MBOX_BIT(n)) {
+                        bits -= MBOX_BIT(n);
+                        if (read_mailbox[n]())
+                                r = IRQ_WAKE_THREAD;
+                }
+        }
+        return r;
+}
+
+static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
+{
+        ack_dbb_wakeup();
+        return IRQ_HANDLED;
+}
+
+void __init db5500_prcmu_early_init(void)
+{
+        tcdm_base = __io_address(U5500_PRCMU_TCDM_BASE);
+        spin_lock_init(&mb0_transfer.lock);
+        mutex_init(&mb5_transfer.lock);
+        init_completion(&mb5_transfer.work);
+}
+
+/**
+ * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
+ *
+ */
+int __init db5500_prcmu_init(void)
+{
+        int r = 0;
+
+        if (ux500_is_svp() || !cpu_is_u5500())
+                return -ENODEV;
+
+        /* Clean up the mailbox interrupts after pre-kernel code. */
+        writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLEAR);
+
+        r = request_threaded_irq(IRQ_DB5500_PRCMU1, prcmu_irq_handler,
+                prcmu_irq_thread_fn, 0, "prcmu", NULL);
+        if (r < 0) {
+                pr_err("prcmu: Failed to allocate IRQ_DB5500_PRCMU1.\n");
+                return -EBUSY;
+        }
+        return 0;
+}
+
+arch_initcall(db5500_prcmu_init);
diff --git a/drivers/mfd/db8500-prcmu-regs.h b/drivers/mfd/db8500-prcmu-regs.h
new file mode 100644
index 00000000000..3bbf04d5804
--- /dev/null
+++ b/drivers/mfd/db8500-prcmu-regs.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * PRCM Unit registers
+ */
+#ifndef __DB8500_PRCMU_REGS_H
+#define __DB8500_PRCMU_REGS_H
+
+#include <linux/bitops.h>
+#include <mach/hardware.h>
+
+#define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
+
+#define PRCM_ARM_PLLDIVPS 0x118
+#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE  BITS(0, 5)
+#define PRCM_ARM_PLLDIVPS_MAX_MASK      0xF
+
+#define PRCM_PLLARM_LOCKP 0x0A8
+#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 BIT(1)
+
+#define PRCM_ARM_CHGCLKREQ 0x114
+#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0)
+
+#define PRCM_PLLARM_ENABLE 0x98
+#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE   BIT(0)
+#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON  BIT(8)
+
+#define PRCM_ARMCLKFIX_MGT      0x0
+#define PRCM_A9_RESETN_CLR      0x1f4
+#define PRCM_A9_RESETN_SET      0x1f0
+#define PRCM_ARM_LS_CLAMP       0x30C
+#define PRCM_SRAM_A9            0x308
+
+/* ARM WFI Standby signal register */
+#define PRCM_ARM_WFI_STANDBY    0x130
+#define PRCM_IOCR               0x310
+#define PRCM_IOCR_IOFORCE BIT(0)
+
+/* CPU mailbox registers */
+#define PRCM_MBOX_CPU_VAL 0x0FC
+#define PRCM_MBOX_CPU_SET 0x100
+
+/* Dual A9 core interrupt management unit registers */
+#define PRCM_A9_MASK_REQ 0x328
+#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ BIT(0)
+
+#define PRCM_A9_MASK_ACK        0x32C
+#define PRCM_ARMITMSK31TO0      0x11C
+#define PRCM_ARMITMSK63TO32     0x120
+#define PRCM_ARMITMSK95TO64     0x124
+#define PRCM_ARMITMSK127TO96    0x128
+#define PRCM_POWER_STATE_VAL    0x25C
+#define PRCM_ARMITVAL31TO0      0x260
+#define PRCM_ARMITVAL63TO32     0x264
+#define PRCM_ARMITVAL95TO64     0x268
+#define PRCM_ARMITVAL127TO96    0x26C
+
+#define PRCM_HOSTACCESS_REQ 0x334
+#define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ BIT(0)
+
+#define PRCM_ARM_IT1_CLR 0x48C
+#define PRCM_ARM_IT1_VAL 0x494
+
+#define PRCM_ITSTATUS0          0x148
+#define PRCM_ITSTATUS1          0x150
+#define PRCM_ITSTATUS2          0x158
+#define PRCM_ITSTATUS3          0x160
+#define PRCM_ITSTATUS4          0x168
+#define PRCM_ITSTATUS5          0x484
+#define PRCM_ITCLEAR5           0x488
+#define PRCM_ARMIT_MASKXP70_IT  0x1018
+
+/* System reset register */
+#define PRCM_APE_SOFTRST 0x228
+
+/* Level shifter and clamp control registers */
+#define PRCM_MMIP_LS_CLAMP_SET 0x420
+#define PRCM_MMIP_LS_CLAMP_CLR 0x424
+
+/* PRCMU HW semaphore */
+#define PRCM_SEM 0x400
+#define PRCM_SEM_PRCM_SEM BIT(0)
+
+/* PRCMU clock/PLL/reset registers */
+#define PRCM_PLLDSI_FREQ        0x500
+#define PRCM_PLLDSI_ENABLE      0x504
+#define PRCM_PLLDSI_LOCKP       0x508
+#define PRCM_DSI_PLLOUT_SEL     0x530
+#define PRCM_DSITVCLK_DIV       0x52C
+#define PRCM_APE_RESETN_SET     0x1E4
+#define PRCM_APE_RESETN_CLR     0x1E8
+
+#define PRCM_TCR                0x1C8
+#define PRCM_TCR_TENSEL_MASK    BITS(0, 7)
+#define PRCM_TCR_STOP_TIMERS    BIT(16)
+#define PRCM_TCR_DOZE_MODE      BIT(17)
+
+#define PRCM_CLKOCR                     0x1CC
+#define PRCM_CLKOCR_CLKODIV0_SHIFT      0
+#define PRCM_CLKOCR_CLKODIV0_MASK       BITS(0, 5)
+#define PRCM_CLKOCR_CLKOSEL0_SHIFT      6
+#define PRCM_CLKOCR_CLKOSEL0_MASK       BITS(6, 8)
+#define PRCM_CLKOCR_CLKODIV1_SHIFT      16
+#define PRCM_CLKOCR_CLKODIV1_MASK       BITS(16, 21)
+#define PRCM_CLKOCR_CLKOSEL1_SHIFT      22
+#define PRCM_CLKOCR_CLKOSEL1_MASK       BITS(22, 24)
+#define PRCM_CLKOCR_CLK1TYPE            BIT(28)
+
+#define PRCM_SGACLK_MGT         0x014
+#define PRCM_UARTCLK_MGT        0x018
+#define PRCM_MSP02CLK_MGT       0x01C
+#define PRCM_MSP1CLK_MGT        0x288
+#define PRCM_I2CCLK_MGT         0x020
+#define PRCM_SDMMCCLK_MGT       0x024
+#define PRCM_SLIMCLK_MGT        0x028
+#define PRCM_PER1CLK_MGT        0x02C
+#define PRCM_PER2CLK_MGT        0x030
+#define PRCM_PER3CLK_MGT        0x034
+#define PRCM_PER5CLK_MGT        0x038
+#define PRCM_PER6CLK_MGT        0x03C
+#define PRCM_PER7CLK_MGT        0x040
+#define PRCM_LCDCLK_MGT         0x044
+#define PRCM_BMLCLK_MGT         0x04C
+#define PRCM_HSITXCLK_MGT       0x050
+#define PRCM_HSIRXCLK_MGT       0x054
+#define PRCM_HDMICLK_MGT        0x058
+#define PRCM_APEATCLK_MGT       0x05C
+#define PRCM_APETRACECLK_MGT    0x060
+#define PRCM_MCDECLK_MGT        0x064
+#define PRCM_IPI2CCLK_MGT       0x068
+#define PRCM_DSIALTCLK_MGT      0x06C
+#define PRCM_DMACLK_MGT         0x074
+#define PRCM_B2R2CLK_MGT        0x078
+#define PRCM_TVCLK_MGT          0x07C
+#define PRCM_UNIPROCLK_MGT      0x278
+#define PRCM_SSPCLK_MGT         0x280
+#define PRCM_RNGCLK_MGT         0x284
+#define PRCM_UICCCLK_MGT        0x27C
+
+#define PRCM_CLK_MGT_CLKPLLDIV_MASK     BITS(0, 4)
+#define PRCM_CLK_MGT_CLKPLLSW_MASK      BITS(5, 7)
+#define PRCM_CLK_MGT_CLKEN              BIT(8)
+
+/* ePOD and memory power signal control registers */
+#define PRCM_EPOD_C_SET         0x410
+#define PRCM_SRAM_LS_SLEEP      0x304
+
+/* Debug power control unit registers */
+#define PRCM_POWER_STATE_SET 0x254
+
+/* Miscellaneous unit registers */
+#define PRCM_DSI_SW_RESET 0x324
+#define PRCM_GPIOCR             0x138
+
+/* GPIOCR register */
+#define PRCM_GPIOCR_SPI2_SELECT BIT(23)
+
+#define PRCM_DDR_SUBSYS_APE_MINBW  0x438
+
+#endif /* __DB8500_PRCMU_REGS_H */
diff --git a/drivers/mfd/max77663-core.c b/drivers/mfd/max77663-core.c
new file mode 100644
index 00000000000..ff47cb123d0
--- /dev/null
+++ b/drivers/mfd/max77663-core.c
@@ -0,0 +1,1445 @@
+/*
+ * drivers/mfd/max77663-core.c
+ * Max77663 mfd driver (I2C bus access)
+ *
+ * Copyright 2011 Maxim Integrated Products, Inc.
+ * Copyright (C) 2011-2012 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ */
+
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/slab.h>
+#include <linux/ratelimit.h>
+#include <linux/kthread.h>
+#include <linux/mfd/core.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/uaccess.h>
+
+#include <linux/mfd/max77663-core.h>
+
+/* RTC i2c slave address */
+#define MAX77663_RTC_I2C_ADDR           0x48
+
+/* Registers */
+#define MAX77663_REG_IRQ_TOP            0x05
+#define MAX77663_REG_LBT_IRQ            0x06
+#define MAX77663_REG_SD_IRQ             0x07
+#define MAX77663_REG_LDOX_IRQ           0x08
+#define MAX77663_REG_LDO8_IRQ           0x09
+#define MAX77663_REG_GPIO_IRQ           0x0A
+#define MAX77663_REG_ONOFF_IRQ          0x0B
+#define MAX77663_REG_NVER               0x0C
+#define MAX77663_REG_IRQ_TOP_MASK       0x0D
+#define MAX77663_REG_LBT_IRQ_MASK       0x0E
+#define MAX77663_REG_SD_IRQ_MASK        0x0F
+#define MAX77663_REG_LDOX_IRQ_MASK      0x10
+#define MAX77663_REG_LDO8_IRQ_MASK      0x11
+#define MAX77663_REG_ONOFF_IRQ_MASK     0x12
+#define MAX77663_REG_GPIO_CTRL0         0x36
+#define MAX77663_REG_GPIO_CTRL1         0x37
+#define MAX77663_REG_GPIO_CTRL2         0x38
+#define MAX77663_REG_GPIO_CTRL3         0x39
+#define MAX77663_REG_GPIO_CTRL4         0x3A
+#define MAX77663_REG_GPIO_CTRL5         0x3B
+#define MAX77663_REG_GPIO_CTRL6         0x3C
+#define MAX77663_REG_GPIO_CTRL7         0x3D
+#define MAX77663_REG_GPIO_PU            0x3E
+#define MAX77663_REG_GPIO_PD            0x3F
+#define MAX77663_REG_GPIO_ALT           0x40
+#define MAX77663_REG_ONOFF_CFG1         0x41
+#define MAX77663_REG_ONOFF_CFG2         0x42
+
+#define IRQ_TOP_GLBL_MASK               (1 << 7)
+#define IRQ_TOP_GLBL_SHIFT              7
+#define IRQ_TOP_SD_MASK                 (1 << 6)
+#define IRQ_TOP_SD_SHIFT                6
+#define IRQ_TOP_LDO_MASK                (1 << 5)
+#define IRQ_TOP_LDO_SHIFT               5
+#define IRQ_TOP_GPIO_MASK               (1 << 4)
+#define IRQ_TOP_GPIO_SHIFT              4
+#define IRQ_TOP_RTC_MASK                (1 << 3)
+#define IRQ_TOP_RTC_SHIFT               3
+#define IRQ_TOP_32K_MASK                (1 << 2)
+#define IRQ_TOP_32K_SHIFT               2
+#define IRQ_TOP_ONOFF_MASK              (1 << 1)
+#define IRQ_TOP_ONOFF_SHIFT             1
+#define IRQ_TOP_NVER_MASK               (1 << 0)
+#define IRQ_TOP_NVER_SHIFT              0
+
+#define IRQ_GLBL_MASK                   (1 << 0)
+
+#define IRQ_LBT_BASE                    MAX77663_IRQ_LBT_LB
+#define IRQ_LBT_END                     MAX77663_IRQ_LBT_THERM_ALRM2
+
+#define IRQ_GPIO_BASE                   MAX77663_IRQ_GPIO0
+#define IRQ_GPIO_END                    MAX77663_IRQ_GPIO7
+
+#define IRQ_ONOFF_BASE                  MAX77663_IRQ_ONOFF_HRDPOWRN
+#define IRQ_ONOFF_END                   MAX77663_IRQ_ONOFF_ACOK_RISING
+
+#define GPIO_REG_ADDR(offset)           (MAX77663_REG_GPIO_CTRL0 + offset)
+
+#define GPIO_CTRL_DBNC_MASK             (3 << 6)
+#define GPIO_CTRL_DBNC_SHIFT            6
+#define GPIO_CTRL_REFE_IRQ_MASK         (3 << 4)
+#define GPIO_CTRL_REFE_IRQ_SHIFT        4
+#define GPIO_CTRL_DOUT_MASK             (1 << 3)
+#define GPIO_CTRL_DOUT_SHIFT            3
+#define GPIO_CTRL_DIN_MASK              (1 << 2)
+#define GPIO_CTRL_DIN_SHIFT             2
+#define GPIO_CTRL_DIR_MASK              (1 << 1)
+#define GPIO_CTRL_DIR_SHIFT             1
+#define GPIO_CTRL_OUT_DRV_MASK          (1 << 0)
+#define GPIO_CTRL_OUT_DRV_SHIFT         0
+
+#define GPIO_REFE_IRQ_NONE              0
+#define GPIO_REFE_IRQ_EDGE_FALLING      1
+#define GPIO_REFE_IRQ_EDGE_RISING       2
+#define GPIO_REFE_IRQ_EDGE_BOTH         3
+
+#define GPIO_DBNC_NONE                  0
+#define GPIO_DBNC_8MS                   1
+#define GPIO_DBNC_16MS                  2
+#define GPIO_DBNC_32MS                  3
+
+#define ONOFF_SFT_RST_MASK              (1 << 7)
+#define ONOFF_SLPEN_MASK                (1 << 2)
+#define ONOFF_PWR_OFF_MASK              (1 << 1)
+
+#define ONOFF_SLP_LPM_MASK              (1 << 5)
+
+enum {
+        CACHE_IRQ_LBT,
+        CACHE_IRQ_SD,
+        CACHE_IRQ_LDO,
+        CACHE_IRQ_ONOFF,
+        CACHE_IRQ_NR,
+};
+
+struct max77663_irq_data {
+        int mask_reg;
+        u16 mask;
+        u8 top_mask;
+        u8 top_shift;
+        int cache_idx;
+        bool is_rtc;
+        bool is_unmask;
+        u8 trigger_type;
+};
+
+struct max77663_chip {
+        struct device *dev;
+        struct i2c_client *i2c_power;
+        struct i2c_client *i2c_rtc;
+
+        struct max77663_platform_data *pdata;
+        struct mutex io_lock;
+
+        struct irq_chip irq;
+        struct mutex irq_lock;
+        int irq_base;
+        int irq_top_count[8];
+        u8 cache_irq_top_mask;
+        u16 cache_irq_mask[CACHE_IRQ_NR];
+
+        struct gpio_chip gpio;
+        int gpio_base;
+        u8 cache_gpio_ctrl[MAX77663_GPIO_NR];
+        u8 cache_gpio_pu;
+        u8 cache_gpio_pd;
+        u8 cache_gpio_alt;
+
+        u8 rtc_i2c_addr;
+};
+
+struct max77663_chip *max77663_chip;
+
+#define IRQ_DATA_LBT(_name, _shift)                     \
+        [MAX77663_IRQ_LBT_##_name] = {                  \
+                .mask_reg = MAX77663_REG_LBT_IRQ_MASK,  \
+                .mask = (1 << _shift),                  \
+                .top_mask = IRQ_TOP_GLBL_MASK,          \
+                .top_shift = IRQ_TOP_GLBL_SHIFT,        \
+                .cache_idx = CACHE_IRQ_LBT,             \
+        }
+
+#define IRQ_DATA_GPIO(_name)                            \
+        [MAX77663_IRQ_GPIO##_name] = {                  \
+                .mask = (1 << _name),                   \
+                .top_mask = IRQ_TOP_GPIO_MASK,          \
+                .top_shift = IRQ_TOP_GPIO_SHIFT,        \
+                .cache_idx = -1,                        \
+        }
+
+#define IRQ_DATA_ONOFF(_name, _shift)                   \
+        [MAX77663_IRQ_ONOFF_##_name] = {                \
+                .mask_reg = MAX77663_REG_ONOFF_IRQ_MASK,\
+                .mask = (1 << _shift),                  \
+                .top_mask = IRQ_TOP_ONOFF_MASK,         \
+                .top_shift = IRQ_TOP_ONOFF_SHIFT,       \
+                .cache_idx = CACHE_IRQ_ONOFF,           \
+        }
+
+static struct max77663_irq_data max77663_irqs[MAX77663_IRQ_NR] = {
+        IRQ_DATA_LBT(LB, 3),
+        IRQ_DATA_LBT(THERM_ALRM1, 2),
+        IRQ_DATA_LBT(THERM_ALRM2, 1),
+        IRQ_DATA_GPIO(0),
+        IRQ_DATA_GPIO(1),
+        IRQ_DATA_GPIO(2),
+        IRQ_DATA_GPIO(3),
+        IRQ_DATA_GPIO(4),
+        IRQ_DATA_GPIO(5),
+        IRQ_DATA_GPIO(6),
+        IRQ_DATA_GPIO(7),
+        IRQ_DATA_ONOFF(HRDPOWRN,     0),
+        IRQ_DATA_ONOFF(EN0_1SEC,     1),
+        IRQ_DATA_ONOFF(EN0_FALLING,  2),
+        IRQ_DATA_ONOFF(EN0_RISING,   3),
+        IRQ_DATA_ONOFF(LID_FALLING,  4),
+        IRQ_DATA_ONOFF(LID_RISING,   5),
+        IRQ_DATA_ONOFF(ACOK_FALLING, 6),
+        IRQ_DATA_ONOFF(ACOK_RISING,  7),
+        [MAX77663_IRQ_RTC] = {
+                .top_mask = IRQ_TOP_RTC_MASK,
+                .top_shift = IRQ_TOP_RTC_SHIFT,
+                .cache_idx = -1,
+                .is_rtc = 1,
+        },
+        [MAX77663_IRQ_SD_PF] = {
+                .mask_reg = MAX77663_REG_SD_IRQ_MASK,
+                .mask = 0xF8,
+                .top_mask = IRQ_TOP_SD_MASK,
+                .top_shift = IRQ_TOP_SD_SHIFT,
+                .cache_idx = CACHE_IRQ_SD,
+        },
+        [MAX77663_IRQ_LDO_PF] = {
+                .mask_reg = MAX77663_REG_LDOX_IRQ_MASK,
+                .mask = 0x1FF,
+                .top_mask = IRQ_TOP_LDO_MASK,
+                .top_shift = IRQ_TOP_LDO_SHIFT,
+                .cache_idx = CACHE_IRQ_LDO,
+        },
+        [MAX77663_IRQ_32K] = {
+                .top_mask = IRQ_TOP_32K_MASK,
+                .top_shift = IRQ_TOP_32K_SHIFT,
+                .cache_idx = -1,
+        },
+        [MAX77663_IRQ_NVER] = {
+                .top_mask = IRQ_TOP_NVER_MASK,
+                .top_shift = IRQ_TOP_NVER_SHIFT,
+                .cache_idx = -1,
+        },
+};
+
+/* MAX77663 PMU doesn't allow PWR_OFF and SFT_RST setting in ONOFF_CFG1
+ * at the same time. So if it try to set PWR_OFF and SFT_RST to ONOFF_CFG1
+ * simultaneously, handle only SFT_RST and ignore PWR_OFF.
+ */
+#define CHECK_ONOFF_CFG1_MASK   (ONOFF_SFT_RST_MASK | ONOFF_PWR_OFF_MASK)
+#define CHECK_ONOFF_CFG1(_addr, _val)                   \
+        unlikely((_addr == MAX77663_REG_ONOFF_CFG1) &&  \
+                 ((_val & CHECK_ONOFF_CFG1_MASK) == CHECK_ONOFF_CFG1_MASK))
+
+static inline int max77663_i2c_write(struct i2c_client *client, u8 addr,
+                                     void *src, u32 bytes)
+{
+        u8 buf[bytes + 1];
+        int ret;
+
+        dev_dbg(&client->dev, "i2c_write: addr=0x%02x, src=0x%02x, bytes=%u\n",
+                addr, *((u8 *)src), bytes);
+
+        if (client->addr == max77663_chip->rtc_i2c_addr) {
+                /* RTC registers support sequential writing */
+                buf[0] = addr;
+                memcpy(&buf[1], src, bytes);
+        } else {
+                /* Power registers support register-data pair writing */
+                u8 *src8 = (u8 *)src;
+                int i;
+
+                for (i = 0; i < (bytes * 2); i++) {
+                        if (i % 2) {
+                                if (CHECK_ONOFF_CFG1(buf[i - 1], *src8))
+                                        buf[i] = *src8++ & ~ONOFF_PWR_OFF_MASK;
+                                else
+                                        buf[i] = *src8++;
+                        } else {
+                                buf[i] = addr++;
+                        }
+                }
+                bytes = (bytes * 2) - 1;
+        }
+
+        ret = i2c_master_send(client, buf, bytes + 1);
+        if (ret < 0)
+                return ret;
+        return 0;
+}
+
+static inline int max77663_i2c_read(struct i2c_client *client, u8 addr,
+                                    void *dest, u32 bytes)
+{
+        int ret;
+
+        if (bytes > 1) {
+                ret = i2c_smbus_read_i2c_block_data(client, addr, bytes, dest);
+                if (ret < 0)
+                        return ret;
+        } else {
+                ret = i2c_smbus_read_byte_data(client, addr);
+                if (ret < 0)
+                        return ret;
+
+                *((u8 *)dest) = (u8)ret;
+        }
+
+        dev_dbg(&client->dev, "i2c_read: addr=0x%02x, dest=0x%02x, bytes=%u\n",
+                addr, *((u8 *)dest), bytes);
+        return 0;
+}
+
+int max77663_read(struct device *dev, u8 addr, void *values, u32 len,
+                  bool is_rtc)
+{
+        struct max77663_chip *chip = dev_get_drvdata(dev);
+        struct i2c_client *client = NULL;
+        int ret;
+
+        mutex_lock(&chip->io_lock);
+        if (!is_rtc)
+                client = chip->i2c_power;
+        else
+                client = chip->i2c_rtc;
+
+        ret = max77663_i2c_read(client, addr, values, len);
+        mutex_unlock(&chip->io_lock);
+        return ret;
+}
+EXPORT_SYMBOL(max77663_read);
+
+int max77663_write(struct device *dev, u8 addr, void *values, u32 len,
+                   bool is_rtc)
+{
+        struct max77663_chip *chip = dev_get_drvdata(dev);
+        struct i2c_client *client = NULL;
+        int ret;
+
+        mutex_lock(&chip->io_lock);
+        if (!is_rtc)
+                client = chip->i2c_power;
+        else
+                client = chip->i2c_rtc;
+
+        ret = max77663_i2c_write(client, addr, values, len);
+        mutex_unlock(&chip->io_lock);
+        return ret;
+}
+EXPORT_SYMBOL(max77663_write);
+
+int max77663_set_bits(struct device *dev, u8 addr, u8 mask, u8 value,
+                      bool is_rtc)
+{
+        struct max77663_chip *chip = dev_get_drvdata(dev);
+        struct i2c_client *client = NULL;
+        u8 tmp;
+        int ret;
+
+        mutex_lock(&chip->io_lock);
+        if (!is_rtc)
+                client = chip->i2c_power;
+        else
+                client = chip->i2c_rtc;
+
+        ret = max77663_i2c_read(client, addr, &tmp, 1);
+        if (ret == 0) {
+                value = (tmp & ~mask) | (value & mask);
+                ret = max77663_i2c_write(client, addr, &value, 1);
+        }
+        mutex_unlock(&chip->io_lock);
+        return ret;
+}
+EXPORT_SYMBOL(max77663_set_bits);
+
+static void max77663_power_off(void)
+{
+        struct max77663_chip *chip = max77663_chip;
+
+        if (!chip)
+                return;
+
+        dev_info(chip->dev, "%s: Global shutdown\n", __func__);
+        max77663_set_bits(chip->dev, MAX77663_REG_ONOFF_CFG1,
+                          ONOFF_SFT_RST_MASK, ONOFF_SFT_RST_MASK, 0);
+}
+
+static int max77663_sleep(struct max77663_chip *chip, bool on)
+{
+        int ret = 0;
+
+        if (chip->pdata->flags & SLP_LPM_ENABLE) {
+                /* Put the power rails into Low-Power mode during sleep mode,
+                 * if the power rail's power mode is GLPM. */
+                ret = max77663_set_bits(chip->dev, MAX77663_REG_ONOFF_CFG2,
+                                        ONOFF_SLP_LPM_MASK,
+                                        on ? ONOFF_SLP_LPM_MASK : 0, 0);
+                if (ret < 0)
+                        return ret;
+        }
+
+        /* Enable sleep that AP can be placed into sleep mode
+         * by pulling EN1 low */
+        return max77663_set_bits(chip->dev, MAX77663_REG_ONOFF_CFG1,
+                                 ONOFF_SLPEN_MASK,
+                                 on ? ONOFF_SLPEN_MASK : 0, 0);
+}
+
+static inline int max77663_cache_write(struct device *dev, u8 addr, u8 mask,
+                                       u8 val, u8 *cache)
+{
+        u8 new_val;
+        int ret;
+
+        new_val = (*cache & ~mask) | (val & mask);
+        if (*cache != new_val) {
+                ret = max77663_write(dev, addr, &new_val, 1, 0);
+                if (ret < 0)
+                        return ret;
+                *cache = new_val;
+        }
+        return 0;
+}
+
+static inline
+struct max77663_chip *max77663_chip_from_gpio(struct gpio_chip *gpio)
+{
+        return container_of(gpio, struct max77663_chip, gpio);
+}
+
+static int max77663_gpio_set_pull_up(struct max77663_chip *chip, int offset,
+                                     int pull_up)
+{
+        u8 val = 0;
+
+        if ((offset < MAX77663_GPIO0) || (MAX77663_GPIO7 < offset))
+                return -EINVAL;
+
+        if (pull_up == GPIO_PU_ENABLE)
+                val = (1 << offset);
+
+        return max77663_cache_write(chip->dev, MAX77663_REG_GPIO_PU,
+                                    (1 << offset), val, &chip->cache_gpio_pu);
+}
+
+static int max77663_gpio_set_pull_down(struct max77663_chip *chip, int offset,
+                                       int pull_down)
+{
+        u8 val = 0;
+
+        if ((offset < MAX77663_GPIO0) || (MAX77663_GPIO7 < offset))
+                return -EINVAL;
+
+        if (pull_down == GPIO_PD_ENABLE)
+                val = (1 << offset);
+
+        return max77663_cache_write(chip->dev, MAX77663_REG_GPIO_PD,
+                                    (1 << offset), val, &chip->cache_gpio_pd);
+}
+
+static inline
+int max77663_gpio_is_alternate(struct max77663_chip *chip, int offset)
+{
+        return (chip->cache_gpio_alt & (1 << offset)) ? 1 : 0;
+}
+
+int max77663_gpio_set_alternate(int gpio, int alternate)
+{
+        struct max77663_chip *chip = max77663_chip;
+        u8 val = 0;
+        int ret = 0;
+
+        if (!chip)
+                return -ENXIO;
+
+        gpio -= chip->gpio_base;
+        if ((gpio < MAX77663_GPIO0) || (MAX77663_GPIO7 < gpio))
+                return -EINVAL;
+
+        if (alternate == GPIO_ALT_ENABLE) {
+                val = (1 << gpio);
+                if (gpio == MAX77663_GPIO7) {
+                        ret = max77663_gpio_set_pull_up(chip, gpio, 0);
+                        if (ret < 0)
+                                return ret;
+
+                        ret = max77663_gpio_set_pull_down(chip, gpio, 0);
+                        if (ret < 0)
+                                return ret;
+                }
+        }
+
+        return max77663_cache_write(chip->dev, MAX77663_REG_GPIO_ALT,
+                                    (1 << gpio), val, &chip->cache_gpio_alt);
+}
+EXPORT_SYMBOL(max77663_gpio_set_alternate);
+
+static int max77663_gpio_dir_input(struct gpio_chip *gpio, unsigned offset)
+{
+        struct max77663_chip *chip = max77663_chip_from_gpio(gpio);
+
+        if (max77663_gpio_is_alternate(chip, offset)) {
+                dev_warn(chip->dev, "gpio_dir_input: "
+                        "gpio%u is used as alternate mode\n", offset);
+                return 0;
+        }
+
+        return max77663_cache_write(chip->dev, GPIO_REG_ADDR(offset),
+                                    GPIO_CTRL_DIR_MASK, GPIO_CTRL_DIR_MASK,
+                                    &chip->cache_gpio_ctrl[offset]);
+}
+
+static int max77663_gpio_get(struct gpio_chip *gpio, unsigned offset)
+{
+        struct max77663_chip *chip = max77663_chip_from_gpio(gpio);
+        u8 val;
+        int ret;
+
+        if (max77663_gpio_is_alternate(chip, offset)) {
+                dev_warn(chip->dev, "gpio_get: "
+                        "gpio%u is used as alternate mode\n", offset);
+                return 0;
+        }
+
+        ret = max77663_read(chip->dev, GPIO_REG_ADDR(offset), &val, 1, 0);
+        if (ret < 0)
+                return ret;
+
+        chip->cache_gpio_ctrl[offset] = val;
+        return (val & GPIO_CTRL_DIN_MASK) >> GPIO_CTRL_DIN_SHIFT;
+}
+
+static int max77663_gpio_dir_output(struct gpio_chip *gpio, unsigned offset,
+                                    int value)
+{
+        struct max77663_chip *chip = max77663_chip_from_gpio(gpio);
+        u8 mask = GPIO_CTRL_DIR_MASK | GPIO_CTRL_DOUT_MASK;
+        u8 val = (value ? 1 : 0) << GPIO_CTRL_DOUT_SHIFT;
+
+        if (max77663_gpio_is_alternate(chip, offset)) {
+                dev_warn(chip->dev, "gpio_dir_output: "
+                        "gpio%u is used as alternate mode\n", offset);
+                return 0;
+        }
+
+        return max77663_cache_write(chip->dev, GPIO_REG_ADDR(offset), mask, val,
+                                    &chip->cache_gpio_ctrl[offset]);
+}
+
+static int max77663_gpio_set_debounce(struct gpio_chip *gpio, unsigned offset,
+                                      unsigned debounce)
+{
+        struct max77663_chip *chip = max77663_chip_from_gpio(gpio);
+        u8 shift = GPIO_CTRL_DBNC_SHIFT;
+        u8 val = 0;
+
+        if (max77663_gpio_is_alternate(chip, offset)) {
+                dev_warn(chip->dev, "gpio_set_debounce: "
+                        "gpio%u is used as alternate mode\n", offset);
+                return 0;
+        }
+
+        if (debounce == 0)
+                val = 0;
+        else if ((0 < debounce) && (debounce <= 8))
+                val = (GPIO_DBNC_8MS << shift);
+        else if ((8 < debounce) && (debounce <= 16))
+                val = (GPIO_DBNC_16MS << shift);
+        else if ((16 < debounce) && (debounce <= 32))
+                val = (GPIO_DBNC_32MS << shift);
+        else
+                return -EINVAL;
+
+        return max77663_cache_write(chip->dev, GPIO_REG_ADDR(offset),
+                                    GPIO_CTRL_DBNC_MASK, val,
+                                    &chip->cache_gpio_ctrl[offset]);
+}
+
+static void max77663_gpio_set(struct gpio_chip *gpio, unsigned offset,
+                              int value)
+{
+        struct max77663_chip *chip = max77663_chip_from_gpio(gpio);
+        u8 val = (value ? 1 : 0) << GPIO_CTRL_DOUT_SHIFT;
+
+        if (max77663_gpio_is_alternate(chip, offset)) {
+                dev_warn(chip->dev, "gpio_set: "
+                        "gpio%u is used as alternate mode\n", offset);
+                return;
+        }
+
+        max77663_cache_write(chip->dev, GPIO_REG_ADDR(offset),
+                             GPIO_CTRL_DOUT_MASK, val,
+                             &chip->cache_gpio_ctrl[offset]);
+}
+
+static int max77663_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
+{
+        struct max77663_chip *chip = max77663_chip_from_gpio(gpio);
+
+        return chip->irq_base + IRQ_GPIO_BASE + offset;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void max77663_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gpio)
+{
+        struct max77663_chip *chip = max77663_chip_from_gpio(gpio);
+        int i;
+
+        for (i = 0; i < gpio->ngpio; i++) {
+                u8 ctrl_val;
+                const char *label;
+                int is_out;
+                int ret;
+
+                label = gpiochip_is_requested(gpio, i);
+                if (!label)
+                        label = "Unrequested";
+
+                seq_printf(s, " gpio-%-3d (%-20.20s) ", i + chip->gpio_base,
+                           label);
+
+                if (chip->cache_gpio_alt & (1 << i)) {
+                        seq_printf(s, "alt\n");
+                        continue;
+                }
+
+                ret = max77663_read(chip->dev, GPIO_REG_ADDR(i), &ctrl_val, 1,
+                                    0);
+                if (ret < 0) {
+                        seq_printf(s, "\n");
+                        continue;
+                }
+
+                is_out = ctrl_val & GPIO_CTRL_DIR_MASK ? 0 : 1;
+                seq_printf(s, "%s %s", (is_out ? "out" : "in"), (is_out ?
+                           (ctrl_val & GPIO_CTRL_DOUT_MASK ? "hi" : "lo")
+                           : (ctrl_val & GPIO_CTRL_DIN_MASK ? "hi" : "lo")));
+
+                if (!is_out) {
+                        int irq = gpio_to_irq(i + chip->gpio_base);
+                        struct irq_desc *desc = irq_to_desc(irq);
+                        u8 dbnc;
+
+                        if (irq >= 0 && desc->action) {
+                                u8 mask = GPIO_CTRL_REFE_IRQ_MASK;
+                                u8 shift = GPIO_CTRL_REFE_IRQ_SHIFT;
+                                char *trigger;
+
+                                switch ((ctrl_val & mask) >> shift) {
+                                case GPIO_REFE_IRQ_EDGE_FALLING:
+                                        trigger = "edge-falling";
+                                        break;
+                                case GPIO_REFE_IRQ_EDGE_RISING:
+                                        trigger = "edge-rising";
+                                        break;
+                                case GPIO_REFE_IRQ_EDGE_BOTH:
+                                        trigger = "edge-both";
+                                        break;
+                                default:
+                                        trigger = "masked";
+                                        break;
+                                }
+
+                                seq_printf(s, " irq-%d %s", irq, trigger);
+                        }
+
+                        dbnc = (ctrl_val & GPIO_CTRL_DBNC_MASK)
+                                >> GPIO_CTRL_DBNC_SHIFT;
+                        seq_printf(s, " debounce-%s",
+                                   dbnc ==  GPIO_DBNC_8MS ? "8ms" :
+                                   dbnc ==  GPIO_DBNC_16MS ? "16ms" :
+                                   dbnc ==  GPIO_DBNC_32MS ? "32ms" : "none");
+                } else {
+                        seq_printf(s, " %s",
+                                   (ctrl_val & GPIO_CTRL_OUT_DRV_MASK ?
+                                   "output-drive" : "open-drain"));
+                }
+
+                seq_printf(s, "\n");
+        }
+}
+#else
+#define max77663_gpio_dbg_show          NULL
+#endif /* CONFIG_DEBUG_FS */
+
+static int max77663_gpio_set_config(struct max77663_chip *chip,
+                                    struct max77663_gpio_config *gpio_cfg)
+{
+        int gpio = gpio_cfg->gpio;
+        u8 val = 0, mask = 0;
+        int ret = 0;
+
+        if ((gpio < MAX77663_GPIO0) || (MAX77663_GPIO7 < gpio))
+                return -EINVAL;
+
+        if (gpio_cfg->pull_up != GPIO_PU_DEF) {
+                ret = max77663_gpio_set_pull_up(chip, gpio, gpio_cfg->pull_up);
+                if (ret < 0) {
+                        dev_err(chip->dev, "gpio_set_config: "
+                                "Failed to set gpio%d pull-up\n", gpio);
+                        return ret;
+                }
+        }
+
+        if (gpio_cfg->pull_down != GPIO_PD_DEF) {
+                ret = max77663_gpio_set_pull_down(chip, gpio,
+                                                  gpio_cfg->pull_down);
+                if (ret < 0) {
+                        dev_err(chip->dev, "gpio_set_config: "
+                                "Failed to set gpio%d pull-down\n", gpio);
+                        return ret;
+                }
+        }
+
+        if (gpio_cfg->dir != GPIO_DIR_DEF) {
+                mask = GPIO_CTRL_DIR_MASK;
+                if (gpio_cfg->dir == GPIO_DIR_IN) {
+                        val |= GPIO_CTRL_DIR_MASK;
+                } else {
+                        if (gpio_cfg->dout != GPIO_DOUT_DEF) {
+                                mask |= GPIO_CTRL_DOUT_MASK;
+                                if (gpio_cfg->dout == GPIO_DOUT_HIGH)
+                                        val |= GPIO_CTRL_DOUT_MASK;
+                        }
+
+                        if (gpio_cfg->out_drv != GPIO_OUT_DRV_DEF) {
+                                mask |= GPIO_CTRL_OUT_DRV_MASK;
+                                if (gpio_cfg->out_drv == GPIO_OUT_DRV_PUSH_PULL)
+                                        val |= GPIO_CTRL_OUT_DRV_MASK;
+                        }
+                }
+
+                ret = max77663_cache_write(chip->dev, GPIO_REG_ADDR(gpio), mask,
+                                           val, &chip->cache_gpio_ctrl[gpio]);
+                if (ret < 0) {
+                        dev_err(chip->dev, "gpio_set_config: "
+                                "Failed to set gpio%d control\n", gpio);
+                        return ret;
+                }
+        }
+
+        if (gpio_cfg->alternate != GPIO_ALT_DEF) {
+                ret = max77663_gpio_set_alternate(gpio + chip->gpio_base,
+                                                  gpio_cfg->alternate);
+                if (ret < 0) {
+                        dev_err(chip->dev, "gpio_set_config: "
+                                "Failed to set gpio%d alternate\n", gpio);
+                        return ret;
+                }
+        }
+
+        return 0;
+}
+
+static int max77663_gpio_init(struct max77663_chip *chip)
+{
+        int i;
+        int ret;
+
+        chip->gpio.label = chip->i2c_power->name;
+        chip->gpio.dev = chip->dev;
+        chip->gpio.owner = THIS_MODULE;
+        chip->gpio.direction_input = max77663_gpio_dir_input;
+        chip->gpio.get = max77663_gpio_get;
+        chip->gpio.direction_output = max77663_gpio_dir_output;
+        chip->gpio.set_debounce = max77663_gpio_set_debounce;
+        chip->gpio.set = max77663_gpio_set;
+        chip->gpio.to_irq = max77663_gpio_to_irq;
+        chip->gpio.dbg_show = max77663_gpio_dbg_show;
+        chip->gpio.ngpio = MAX77663_GPIO_NR;
+        chip->gpio.can_sleep = 1;
+        if (chip->gpio_base)
+                chip->gpio.base = chip->gpio_base;
+        else
+                chip->gpio.base = -1;
+
+        ret = max77663_read(chip->dev, MAX77663_REG_GPIO_CTRL0,
+                            chip->cache_gpio_ctrl, MAX77663_GPIO_NR, 0);
+        if (ret < 0) {
+                dev_err(chip->dev, "gpio_init: Failed to get gpio control\n");
+                return ret;
+        }
+
+        ret = max77663_read(chip->dev, MAX77663_REG_GPIO_PU,
+                            &chip->cache_gpio_pu, 1, 0);
+        if (ret < 0) {
+                dev_err(chip->dev, "gpio_init: Failed to get gpio pull-up\n");
+                return ret;
+        }
+
+        ret = max77663_read(chip->dev, MAX77663_REG_GPIO_PD,
+                            &chip->cache_gpio_pd, 1, 0);
+        if (ret < 0) {
+                dev_err(chip->dev, "gpio_init: Failed to get gpio pull-down\n");
+                return ret;
+        }
+
+        ret = max77663_read(chip->dev, MAX77663_REG_GPIO_ALT,
+                            &chip->cache_gpio_alt, 1, 0);
+        if (ret < 0) {
+                dev_err(chip->dev, "gpio_init: Failed to get gpio alternate\n");
+                return ret;
+        }
+
+        ret = gpiochip_add(&chip->gpio);
+        if (ret < 0) {
+                dev_err(chip->dev, "gpio_init: Failed to add gpiochip\n");
+                return ret;
+        }
+        chip->gpio_base = chip->gpio.base;
+
+        for (i = 0; i < chip->pdata->num_gpio_cfgs; i++) {
+                ret = max77663_gpio_set_config(chip,
+                                               &chip->pdata->gpio_cfgs[i]);
+                if (ret < 0) {
+                        dev_err(chip->dev,
+                                "gpio_init: Failed to set gpio config\n");
+                        return ret;
+                }
+        }
+
+        return 0;
+}
+
+static void max77663_gpio_exit(struct max77663_chip *chip)
+{
+        if (gpiochip_remove(&chip->gpio) < 0)
+                dev_err(chip->dev, "gpio_exit: Failed to remove gpiochip\n");
+}
+
+static void max77663_irq_mask(struct irq_data *data)
+{
+        struct max77663_chip *chip = irq_data_get_irq_chip_data(data);
+
+        max77663_irqs[data->irq - chip->irq_base].is_unmask = 0;
+}
+
+static void max77663_irq_unmask(struct irq_data *data)
+{
+        struct max77663_chip *chip = irq_data_get_irq_chip_data(data);
+
+        max77663_irqs[data->irq - chip->irq_base].is_unmask = 1;
+}
+
+static void max77663_irq_lock(struct irq_data *data)
+{
+        struct max77663_chip *chip = irq_data_get_irq_chip_data(data);
+
+        mutex_lock(&chip->irq_lock);
+}
+
+static void max77663_irq_sync_unlock(struct irq_data *data)
+{
+        struct max77663_chip *chip = irq_data_get_irq_chip_data(data);
+        struct max77663_irq_data *irq_data =
+                        &max77663_irqs[data->irq - chip->irq_base];
+        int idx = irq_data->cache_idx;
+        u8 irq_top_mask = chip->cache_irq_top_mask;
+        u16 irq_mask = chip->cache_irq_mask[idx];
+        int update_irq_top = 0;
+        u32 len = 1;
+        int ret;
+
+        if (irq_data->is_unmask) {
+                if (chip->irq_top_count[irq_data->top_shift] == 0)
+                        update_irq_top = 1;
+                chip->irq_top_count[irq_data->top_shift]++;
+
+                if (irq_data->top_mask != IRQ_TOP_GLBL_MASK)
+                        irq_top_mask &= ~irq_data->top_mask;
+
+                if (idx != -1)
+                        irq_mask &= ~irq_data->mask;
+        } else {
+                if (chip->irq_top_count[irq_data->top_shift] == 1)
+                        update_irq_top = 1;
+
+                if (--chip->irq_top_count[irq_data->top_shift] < 0)
+                        chip->irq_top_count[irq_data->top_shift] = 0;
+
+                if (irq_data->top_mask != IRQ_TOP_GLBL_MASK)
+                        irq_top_mask |= irq_data->top_mask;
+
+                if (idx != -1)
+                        irq_mask |= irq_data->mask;
+        }
+
+        if ((idx != -1) && (irq_mask != chip->cache_irq_mask[idx])) {
+                if (irq_data->top_mask == IRQ_TOP_LDO_MASK)
+                        len = 2;
+
+                ret = max77663_write(chip->dev, irq_data->mask_reg,
+                                     &irq_mask, len, irq_data->is_rtc);
+                if (ret < 0)
+                        goto out;
+
+                chip->cache_irq_mask[idx] = irq_mask;
+        } else if ((idx == -1) && (irq_data->top_mask == IRQ_TOP_GPIO_MASK)) {
+                unsigned offset = data->irq - chip->irq_base - IRQ_GPIO_BASE;
+                u8 shift = GPIO_CTRL_REFE_IRQ_SHIFT;
+
+                if (irq_data->is_unmask) {
+                        if (irq_data->trigger_type)
+                                irq_mask = irq_data->trigger_type;
+                        else
+                                irq_mask = GPIO_REFE_IRQ_EDGE_FALLING << shift;
+                }
+
+                ret = max77663_cache_write(chip->dev, GPIO_REG_ADDR(offset),
+                                           GPIO_CTRL_REFE_IRQ_MASK, irq_mask,
+                                           &chip->cache_gpio_ctrl[offset]);
+                if (ret < 0)
+                        goto out;
+
+                if (irq_data->is_unmask)
+                        irq_data->trigger_type = irq_mask;
+        }
+
+        if (update_irq_top && (irq_top_mask != chip->cache_irq_top_mask)) {
+                ret = max77663_cache_write(chip->dev, MAX77663_REG_IRQ_TOP_MASK,
+                                           irq_data->top_mask, irq_top_mask,
+                                           &chip->cache_irq_top_mask);
+                if (ret < 0)
+                        goto out;
+        }
+
+out:
+        mutex_unlock(&chip->irq_lock);
+}
+
+static int max77663_irq_gpio_set_type(struct irq_data *data, unsigned int type)
+{
+        struct max77663_chip *chip = irq_data_get_irq_chip_data(data);
+        struct max77663_irq_data *irq_data =
+                        &max77663_irqs[data->irq - chip->irq_base];
+        unsigned offset = data->irq - chip->irq_base - IRQ_GPIO_BASE;
+        u8 shift = GPIO_CTRL_REFE_IRQ_SHIFT;
+        u8 val;
+
+        switch (type) {
+        case IRQ_TYPE_NONE:
+        case IRQ_TYPE_EDGE_FALLING:
+                val = (GPIO_REFE_IRQ_EDGE_FALLING << shift);
+                break;
+        case IRQ_TYPE_EDGE_RISING:
+                val = (GPIO_REFE_IRQ_EDGE_RISING << shift);
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                val = (GPIO_REFE_IRQ_EDGE_BOTH << shift);
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        irq_data->trigger_type = val;
+        if (!(chip->cache_gpio_ctrl[offset] & GPIO_CTRL_REFE_IRQ_MASK))
+                return 0;
+
+        return max77663_cache_write(chip->dev, GPIO_REG_ADDR(offset),
+                                    GPIO_CTRL_REFE_IRQ_MASK, val,
+                                    &chip->cache_gpio_ctrl[offset]);
+}
+
+static inline int max77663_do_irq(struct max77663_chip *chip, u8 addr,
+                                  int irq_base, int irq_end)
+{
+        struct max77663_irq_data *irq_data = NULL;
+        int irqs_to_handle[irq_end - irq_base + 1];
+        int handled = 0;
+        u16 val;
+        u32 len = 1;
+        int i;
+        int ret;
+
+        ret = max77663_read(chip->dev, addr, &val, len, 0);
+        if (ret < 0)
+                return ret;
+
+        for (i = irq_base; i <= irq_end; i++) {
+                irq_data = &max77663_irqs[i];
+                if (val & irq_data->mask) {
+                        irqs_to_handle[handled] = i + chip->irq_base;
+                        handled++;
+                }
+        }
+
+        for (i = 0; i < handled; i++)
+                handle_nested_irq(irqs_to_handle[i]);
+
+        return 0;
+}
+
+static irqreturn_t max77663_irq(int irq, void *data)
+{
+        struct max77663_chip *chip = data;
+        u8 irq_top;
+        int ret;
+
+        ret = max77663_read(chip->dev, MAX77663_REG_IRQ_TOP, &irq_top, 1, 0);
+        if (ret < 0) {
+                dev_err(chip->dev, "irq: Failed to get irq top status\n");
+                return IRQ_NONE;
+        }
+
+        if (irq_top & IRQ_TOP_GLBL_MASK) {
+                ret = max77663_do_irq(chip, MAX77663_REG_LBT_IRQ, IRQ_LBT_BASE,
+                                      IRQ_LBT_END);
+                if (ret < 0)
+                        return IRQ_NONE;
+        }
+
+        if (irq_top & IRQ_TOP_GPIO_MASK) {
+                ret = max77663_do_irq(chip, MAX77663_REG_GPIO_IRQ,
+                                      IRQ_GPIO_BASE, IRQ_GPIO_END);
+                if (ret < 0)
+                        return IRQ_NONE;
+        }
+
+        if (irq_top & IRQ_TOP_ONOFF_MASK) {
+                ret = max77663_do_irq(chip, MAX77663_REG_ONOFF_IRQ,
+                                      IRQ_ONOFF_BASE, IRQ_ONOFF_END);
+                if (ret < 0)
+                        return IRQ_NONE;
+        }
+
+        if (irq_top & IRQ_TOP_RTC_MASK)
+                handle_nested_irq(MAX77663_IRQ_RTC + chip->irq_base);
+
+        if (irq_top & IRQ_TOP_SD_MASK)
+                handle_nested_irq(MAX77663_IRQ_SD_PF + chip->irq_base);
+
+        if (irq_top & IRQ_TOP_LDO_MASK)
+                handle_nested_irq(MAX77663_IRQ_LDO_PF + chip->irq_base);
+
+        if (irq_top & IRQ_TOP_32K_MASK)
+                handle_nested_irq(MAX77663_IRQ_32K + chip->irq_base);
+
+        if (irq_top & IRQ_TOP_NVER_MASK)
+                handle_nested_irq(MAX77663_IRQ_NVER + chip->irq_base);
+
+        return IRQ_HANDLED;
+}
+
+static struct irq_chip max77663_irq_gpio_chip = {
+        .name = "max77663-irq",
+        .irq_mask = max77663_irq_mask,
+        .irq_unmask = max77663_irq_unmask,
+        .irq_set_type = max77663_irq_gpio_set_type,
+        .irq_bus_lock = max77663_irq_lock,
+        .irq_bus_sync_unlock = max77663_irq_sync_unlock,
+};
+
+static struct irq_chip max77663_irq_chip = {
+        .name = "max77663-irq",
+        .irq_mask = max77663_irq_mask,
+        .irq_unmask = max77663_irq_unmask,
+        .irq_bus_lock = max77663_irq_lock,
+        .irq_bus_sync_unlock = max77663_irq_sync_unlock,
+};
+
+static int max77663_irq_init(struct max77663_chip *chip)
+{
+        u32 temp;
+        int i, ret = 0;
+
+        mutex_init(&chip->irq_lock);
+
+        /* Mask all interrupts */
+        chip->cache_irq_top_mask = 0xFF;
+        chip->cache_irq_mask[CACHE_IRQ_LBT] = 0x0F;
+        chip->cache_irq_mask[CACHE_IRQ_SD] = 0xFF;
+        chip->cache_irq_mask[CACHE_IRQ_LDO] = 0xFFFF;
+        chip->cache_irq_mask[CACHE_IRQ_ONOFF] = 0xFF;
+
+        max77663_write(chip->dev, MAX77663_REG_IRQ_TOP_MASK,
+                       &chip->cache_irq_top_mask, 1, 0);
+        max77663_write(chip->dev, MAX77663_REG_LBT_IRQ_MASK,
+                       &chip->cache_irq_mask[CACHE_IRQ_LBT], 1, 0);
+        max77663_write(chip->dev, MAX77663_REG_SD_IRQ_MASK,
+                       &chip->cache_irq_mask[CACHE_IRQ_SD], 1, 0);
+        max77663_write(chip->dev, MAX77663_REG_LDOX_IRQ_MASK,
+                       &chip->cache_irq_mask[CACHE_IRQ_LDO], 2, 0);
+        max77663_write(chip->dev, MAX77663_REG_ONOFF_IRQ_MASK,
+                       &chip->cache_irq_mask[CACHE_IRQ_ONOFF], 1, 0);
+
+        /* Clear all interrups */
+        max77663_read(chip->dev, MAX77663_REG_LBT_IRQ, &temp, 1, 0);
+        max77663_read(chip->dev, MAX77663_REG_SD_IRQ, &temp, 1, 0);
+        max77663_read(chip->dev, MAX77663_REG_LDOX_IRQ, &temp, 2, 0);
+        max77663_read(chip->dev, MAX77663_REG_GPIO_IRQ, &temp, 1, 0);
+        max77663_read(chip->dev, MAX77663_REG_ONOFF_IRQ, &temp, 1, 0);
+
+        for (i = chip->irq_base; i < (MAX77663_IRQ_NR + chip->irq_base); i++) {
+                if (i >= NR_IRQS) {
+                        dev_err(chip->dev,
+                                "irq_init: Can't set irq chip for irq %d\n", i);
+                        continue;
+                }
+
+                irq_set_chip_data(i, chip);
+
+                if ((IRQ_GPIO_BASE <= i - chip->irq_base) &&
+                                (i - chip->irq_base <= IRQ_GPIO_END))
+                        irq_set_chip_and_handler(i, &max77663_irq_gpio_chip,
+                                                 handle_edge_irq);
+                else
+                        irq_set_chip_and_handler(i, &max77663_irq_chip,
+                                                 handle_edge_irq);
+#ifdef CONFIG_ARM
+                set_irq_flags(i, IRQF_VALID);
+#else
+                irq_set_noprobe(i);
+#endif
+                irq_set_nested_thread(i, 1);
+        }
+
+        ret = request_threaded_irq(chip->i2c_power->irq, NULL, max77663_irq,
+                                   IRQF_ONESHOT, "max77663", chip);
+        if (ret) {
+                dev_err(chip->dev, "irq_init: Failed to request irq %d\n",
+                        chip->i2c_power->irq);
+                return ret;
+        }
+
+        device_init_wakeup(chip->dev, 1);
+        enable_irq_wake(chip->i2c_power->irq);
+
+        chip->cache_irq_top_mask &= ~IRQ_TOP_GLBL_MASK;
+        max77663_write(chip->dev, MAX77663_REG_IRQ_TOP_MASK,
+                       &chip->cache_irq_top_mask, 1, 0);
+
+        chip->cache_irq_mask[CACHE_IRQ_LBT] &= ~IRQ_GLBL_MASK;
+        max77663_write(chip->dev, MAX77663_REG_LBT_IRQ_MASK,
+                       &chip->cache_irq_mask[CACHE_IRQ_LBT], 1, 0);
+
+        return 0;
+}
+
+static void max77663_irq_exit(struct max77663_chip *chip)
+{
+        if (chip->i2c_power->irq)
+                free_irq(chip->i2c_power->irq, chip);
+}
+
+#ifdef CONFIG_DEBUG_FS
+static struct dentry *max77663_dentry_regs;
+
+static int max77663_debugfs_dump_regs(struct max77663_chip *chip, char *label,
+                                      u8 *addrs, int num_addrs, char *buf,
+                                      ssize_t *len, int is_rtc)
+{
+        ssize_t count = *len;
+        u8 val;
+        int ret = 0;
+        int i;
+
+        count += sprintf(buf + count, "%s\n", label);
+        if (count >= PAGE_SIZE - 1)
+                return -ERANGE;
+
+        for (i = 0; i < num_addrs; i++) {
+                count += sprintf(buf + count, "0x%02x: ", addrs[i]);
+                if (count >= PAGE_SIZE - 1)
+                        return -ERANGE;
+
+                ret = max77663_read(chip->dev, addrs[i], &val, 1, is_rtc);
+                if (ret == 0)
+                        count += sprintf(buf + count, "0x%02x\n", val);
+                else
+                        count += sprintf(buf + count, "<read fail: %d>\n", ret);
+
+                if (count >= PAGE_SIZE - 1)
+                        return -ERANGE;
+        }
+
+        *len = count;
+        return 0;
+}
+
+static int max77663_debugfs_regs_open(struct inode *inode, struct file *file)
+{
+        file->private_data = inode->i_private;
+        return 0;
+}
+
+static ssize_t max77663_debugfs_regs_read(struct file *file,
+                                          char __user *user_buf,
+                                          size_t count, loff_t *ppos)
+{
+        struct max77663_chip *chip = file->private_data;
+        char *buf;
+        size_t len = 0;
+        ssize_t ret;
+
+        /* Excluded interrupt status register to prevent register clear */
+        u8 global_regs[] = { 0x00, 0x01, 0x02, 0x05, 0x0D, 0x0E, 0x13 };
+        u8 sd_regs[] = {
+                0x07, 0x0F, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D,
+                0x1E, 0x1F, 0x20, 0x21, 0x22
+        };
+        u8 ldo_regs[] = {
+                0x10, 0x11, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A,
+                0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34,
+                0x35
+        };
+        u8 gpio_regs[] = {
+                0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F,
+                0x40
+        };
+        u8 rtc_regs[] = {
+                0x01, 0x02, 0x03, 0x04, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
+                0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
+                0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B
+        };
+        u8 osc_32k_regs[] = { 0x03 };
+        u8 bbc_regs[] = { 0x04 };
+        u8 onoff_regs[] = { 0x12, 0x15, 0x41, 0x42 };
+        u8 fps_regs[] = {
+                0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C,
+                0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56,
+                0x57
+        };
+        u8 cid_regs[] = { 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D };
+
+        buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
+        if (!buf)
+                return -ENOMEM;
+
+        len += sprintf(buf + len, "MAX77663 Registers\n");
+        max77663_debugfs_dump_regs(chip, "[Global]", global_regs,
+                                   ARRAY_SIZE(global_regs), buf, &len, 0);
+        max77663_debugfs_dump_regs(chip, "[Step-Down]", sd_regs,
+                                   ARRAY_SIZE(sd_regs), buf, &len, 0);
+        max77663_debugfs_dump_regs(chip, "[LDO]", ldo_regs,
+                                   ARRAY_SIZE(ldo_regs), buf, &len, 0);
+        max77663_debugfs_dump_regs(chip, "[GPIO]", gpio_regs,
+                                   ARRAY_SIZE(gpio_regs), buf, &len, 0);
+        max77663_debugfs_dump_regs(chip, "[RTC]", rtc_regs,
+                                   ARRAY_SIZE(rtc_regs), buf, &len, 1);
+        max77663_debugfs_dump_regs(chip, "[32kHz Oscillator]", osc_32k_regs,
+                                   ARRAY_SIZE(osc_32k_regs), buf, &len, 0);
+        max77663_debugfs_dump_regs(chip, "[Backup Battery Charger]", bbc_regs,
+                                   ARRAY_SIZE(bbc_regs), buf, &len, 0);
+        max77663_debugfs_dump_regs(chip, "[On/OFF Controller]", onoff_regs,
+                                   ARRAY_SIZE(onoff_regs), buf, &len, 0);
+        max77663_debugfs_dump_regs(chip, "[Flexible Power Sequencer]", fps_regs,
+                                   ARRAY_SIZE(fps_regs), buf, &len, 0);
+        max77663_debugfs_dump_regs(chip, "[Chip Identification]", cid_regs,
+                                   ARRAY_SIZE(cid_regs), buf, &len, 0);
+
+        ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
+        kfree(buf);
+
+        return ret;
+}
+
+static const struct file_operations max77663_debugfs_regs_fops = {
+        .open = max77663_debugfs_regs_open,
+        .read = max77663_debugfs_regs_read,
+};
+
+static void max77663_debugfs_init(struct max77663_chip *chip)
+{
+        max77663_dentry_regs = debugfs_create_file(chip->i2c_power->name,
+                                                   0444, 0, chip,
+                                                   &max77663_debugfs_regs_fops);
+        if (!max77663_dentry_regs)
+                dev_warn(chip->dev,
+                         "debugfs_init: Failed to create debugfs file\n");
+}
+
+static void max77663_debugfs_exit(struct max77663_chip *chip)
+{
+        debugfs_remove(max77663_dentry_regs);
+}
+#else
+static inline void max77663_debugfs_init(struct max77663_chip *chip)
+{
+}
+
+static inline void max77663_debugfs_exit(struct max77663_chip *chip)
+{
+}
+#endif /* CONFIG_DEBUG_FS */
+
+static int max77663_probe(struct i2c_client *client,
+                          const struct i2c_device_id *id)
+{
+        struct max77663_platform_data *pdata = client->dev.platform_data;
+        struct max77663_chip *chip;
+        int ret = 0;
+
+        if (pdata == NULL) {
+                dev_err(&client->dev, "probe: Invalid platform_data\n");
+                ret = -ENODEV;
+                goto out;
+        }
+
+        chip = kzalloc(sizeof(struct max77663_chip), GFP_KERNEL);
+        if (chip == NULL) {
+                dev_err(&client->dev, "probe: kzalloc() failed\n");
+                ret = -ENOMEM;
+                goto out;
+        }
+        max77663_chip = chip;
+
+        chip->i2c_power = client;
+        i2c_set_clientdata(client, chip);
+
+        if (pdata->rtc_i2c_addr)
+                chip->rtc_i2c_addr = pdata->rtc_i2c_addr;
+        else
+                chip->rtc_i2c_addr = MAX77663_RTC_I2C_ADDR;
+
+        chip->i2c_rtc = i2c_new_dummy(client->adapter, chip->rtc_i2c_addr);
+        i2c_set_clientdata(chip->i2c_rtc, chip);
+
+        chip->dev = &client->dev;
+        chip->pdata = pdata;
+        chip->irq_base = pdata->irq_base;
+        chip->gpio_base = pdata->gpio_base;
+        mutex_init(&chip->io_lock);
+
+        max77663_gpio_init(chip);
+        max77663_irq_init(chip);
+        max77663_debugfs_init(chip);
+        ret = max77663_sleep(chip, false);
+        if (ret < 0) {
+                dev_err(&client->dev, "probe: Failed to disable sleep\n");
+                goto out_exit;
+        }
+
+        if (pdata->use_power_off && !pm_power_off)
+                pm_power_off = max77663_power_off;
+
+        ret = mfd_add_devices(&client->dev, 0, pdata->sub_devices,
+                              pdata->num_subdevs, NULL, 0);
+        if (ret != 0) {
+                dev_err(&client->dev, "probe: Failed to add subdev: %d\n", ret);
+                goto out_exit;
+        }
+
+        return 0;
+
+out_exit:
+        max77663_debugfs_exit(chip);
+        max77663_gpio_exit(chip);
+        max77663_irq_exit(chip);
+        mutex_destroy(&chip->io_lock);
+        max77663_chip = NULL;
+        kfree(chip);
+out:
+        return ret;
+}
+
+static int __devexit max77663_remove(struct i2c_client *client)
+{
+        struct max77663_chip *chip = i2c_get_clientdata(client);
+
+        mfd_remove_devices(chip->dev);
+        max77663_debugfs_exit(chip);
+        max77663_irq_exit(chip);
+        max77663_gpio_exit(chip);
+        mutex_destroy(&chip->io_lock);
+        max77663_chip = NULL;
+        kfree(chip);
+
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int max77663_suspend(struct device *dev)
+{
+        struct i2c_client *client = to_i2c_client(dev);
+        struct max77663_chip *chip = i2c_get_clientdata(client);
+        int ret;
+
+        if (client->irq)
+                disable_irq(client->irq);
+
+        ret = max77663_sleep(chip, true);
+        if (ret < 0)
+                dev_err(dev, "suspend: Failed to enable sleep\n");
+
+        return ret;
+}
+
+static int max77663_resume(struct device *dev)
+{
+        struct i2c_client *client = to_i2c_client(dev);
+        struct max77663_chip *chip = i2c_get_clientdata(client);
+        int ret;
+
+        ret = max77663_sleep(chip, false);
+        if (ret < 0) {
+                dev_err(dev, "resume: Failed to disable sleep\n");
+                return ret;
+        }
+
+        if (client->irq)
+                enable_irq(client->irq);
+
+        return 0;
+}
+#else
+#define max77663_suspend      NULL
+#define max77663_resume       NULL
+#endif /* CONFIG_PM */
+
+static const struct i2c_device_id max77663_id[] = {
+        {"max77663", 0},
+        {},
+};
+MODULE_DEVICE_TABLE(i2c, max77663_id);
+
+static const struct dev_pm_ops max77663_pm = {
+        .suspend = max77663_suspend,
+        .resume = max77663_resume,
+};
+
+static struct i2c_driver max77663_driver = {
+        .driver = {
+                .name = "max77663",
+                .owner = THIS_MODULE,
+                .pm = &max77663_pm,
+        },
+        .probe = max77663_probe,
+        .remove = __devexit_p(max77663_remove),
+        .id_table = max77663_id,
+};
+
+static int __init max77663_init(void)
+{
+        return i2c_add_driver(&max77663_driver);
+}
+subsys_initcall(max77663_init);
+
+static void __exit max77663_exit(void)
+{
+        i2c_del_driver(&max77663_driver);
+}
+module_exit(max77663_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("MAX77663 Multi Function Device Core Driver");
+MODULE_VERSION("1.0");
diff --git a/drivers/mfd/max8907c-irq.c b/drivers/mfd/max8907c-irq.c
new file mode 100644
index 00000000000..8d6e9600e7f
--- /dev/null
+++ b/drivers/mfd/max8907c-irq.c
@@ -0,0 +1,425 @@
+/*
+ * Battery driver for Maxim MAX8907C
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ * Based on driver/mfd/max8925-core.c, Copyright (C) 2009-2010 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/max8907c.h>
+
+struct max8907c_irq_data {
+        int     reg;
+        int     mask_reg;
+        int     enable;         /* enable or not */
+        int     offs;           /* bit offset in mask register */
+        bool    is_rtc;
+        int     wake;
+};
+
+static struct max8907c_irq_data max8907c_irqs[] = {
+        [MAX8907C_IRQ_VCHG_DC_OVP] = {
+                .reg            = MAX8907C_REG_CHG_IRQ1,
+                .mask_reg       = MAX8907C_REG_CHG_IRQ1_MASK,
+                .offs           = 1 << 0,
+        },
+        [MAX8907C_IRQ_VCHG_DC_F] = {
+                .reg            = MAX8907C_REG_CHG_IRQ1,
+                .mask_reg       = MAX8907C_REG_CHG_IRQ1_MASK,
+                .offs           = 1 << 1,
+        },
+        [MAX8907C_IRQ_VCHG_DC_R] = {
+                .reg            = MAX8907C_REG_CHG_IRQ1,
+                .mask_reg       = MAX8907C_REG_CHG_IRQ1_MASK,
+                .offs           = 1 << 2,
+        },
+        [MAX8907C_IRQ_VCHG_THM_OK_R] = {
+                .reg            = MAX8907C_REG_CHG_IRQ2,
+                .mask_reg       = MAX8907C_REG_CHG_IRQ2_MASK,
+                .offs           = 1 << 0,
+        },
+        [MAX8907C_IRQ_VCHG_THM_OK_F] = {
+                .reg            = MAX8907C_REG_CHG_IRQ2,
+                .mask_reg       = MAX8907C_REG_CHG_IRQ2_MASK,
+                .offs           = 1 << 1,
+        },
+        [MAX8907C_IRQ_VCHG_MBATTLOW_F] = {
+                .reg            = MAX8907C_REG_CHG_IRQ2,
+                .mask_reg       = MAX8907C_REG_CHG_IRQ2_MASK,
+                .offs           = 1 << 2,
+        },
+        [MAX8907C_IRQ_VCHG_MBATTLOW_R] = {
+                .reg            = MAX8907C_REG_CHG_IRQ2,
+                .mask_reg       = MAX8907C_REG_CHG_IRQ2_MASK,
+                .offs           = 1 << 3,
+        },
+        [MAX8907C_IRQ_VCHG_RST] = {
+                .reg            = MAX8907C_REG_CHG_IRQ2,
+                .mask_reg       = MAX8907C_REG_CHG_IRQ2_MASK,
+                .offs           = 1 << 4,
+        },
+        [MAX8907C_IRQ_VCHG_DONE] = {
+                .reg            = MAX8907C_REG_CHG_IRQ2,
+                .mask_reg       = MAX8907C_REG_CHG_IRQ2_MASK,
+                .offs           = 1 << 5,
+        },
+        [MAX8907C_IRQ_VCHG_TOPOFF] = {
+                .reg            = MAX8907C_REG_CHG_IRQ2,
+                .mask_reg       = MAX8907C_REG_CHG_IRQ2_MASK,
+                .offs           = 1 << 6,
+        },
+        [MAX8907C_IRQ_VCHG_TMR_FAULT] = {
+                .reg            = MAX8907C_REG_CHG_IRQ2,
+                .mask_reg       = MAX8907C_REG_CHG_IRQ2_MASK,
+                .offs           = 1 << 7,
+        },
+        [MAX8907C_IRQ_GPM_RSTIN] = {
+                .reg            = MAX8907C_REG_ON_OFF_IRQ1,
+                .mask_reg       = MAX8907C_REG_ON_OFF_IRQ1_MASK,
+                .offs           = 1 << 0,
+        },
+        [MAX8907C_IRQ_GPM_MPL] = {
+                .reg            = MAX8907C_REG_ON_OFF_IRQ1,
+                .mask_reg       = MAX8907C_REG_ON_OFF_IRQ1_MASK,
+                .offs           = 1 << 1,
+        },
+        [MAX8907C_IRQ_GPM_SW_3SEC] = {
+                .reg            = MAX8907C_REG_ON_OFF_IRQ1,
+                .mask_reg       = MAX8907C_REG_ON_OFF_IRQ1_MASK,
+                .offs           = 1 << 2,
+        },
+        [MAX8907C_IRQ_GPM_EXTON_F] = {
+                .reg            = MAX8907C_REG_ON_OFF_IRQ1,
+                .mask_reg       = MAX8907C_REG_ON_OFF_IRQ1_MASK,
+                .offs           = 1 << 3,
+        },
+        [MAX8907C_IRQ_GPM_EXTON_R] = {
+                .reg            = MAX8907C_REG_ON_OFF_IRQ1,
+                .mask_reg       = MAX8907C_REG_ON_OFF_IRQ1_MASK,
+                .offs           = 1 << 4,
+        },
+        [MAX8907C_IRQ_GPM_SW_1SEC] = {
+                .reg            = MAX8907C_REG_ON_OFF_IRQ1,
+                .mask_reg       = MAX8907C_REG_ON_OFF_IRQ1_MASK,
+                .offs           = 1 << 5,
+        },
+        [MAX8907C_IRQ_GPM_SW_F] = {
+                .reg            = MAX8907C_REG_ON_OFF_IRQ1,
+                .mask_reg       = MAX8907C_REG_ON_OFF_IRQ1_MASK,
+                .offs           = 1 << 6,
+        },
+        [MAX8907C_IRQ_GPM_SW_R] = {
+                .reg            = MAX8907C_REG_ON_OFF_IRQ1,
+                .mask_reg       = MAX8907C_REG_ON_OFF_IRQ1_MASK,
+                .offs           = 1 << 7,
+        },
+        [MAX8907C_IRQ_GPM_SYSCKEN_F] = {
+                .reg            = MAX8907C_REG_ON_OFF_IRQ2,
+                .mask_reg       = MAX8907C_REG_ON_OFF_IRQ2_MASK,
+                .offs           = 1 << 0,
+        },
+        [MAX8907C_IRQ_GPM_SYSCKEN_R] = {
+                .reg            = MAX8907C_REG_ON_OFF_IRQ2,
+                .mask_reg       = MAX8907C_REG_ON_OFF_IRQ2_MASK,
+                .offs           = 1 << 1,
+        },
+        [MAX8907C_IRQ_RTC_ALARM1] = {
+                .reg            = MAX8907C_REG_RTC_IRQ,
+                .mask_reg       = MAX8907C_REG_RTC_IRQ_MASK,
+                .offs           = 1 << 2,
+                .is_rtc         = true,
+        },
+        [MAX8907C_IRQ_RTC_ALARM0] = {
+                .reg            = MAX8907C_REG_RTC_IRQ,
+                .mask_reg       = MAX8907C_REG_RTC_IRQ_MASK,
+                .offs           = 1 << 3,
+                .is_rtc         = true,
+        },
+};
+
+static inline struct max8907c_irq_data *irq_to_max8907c(struct max8907c *chip,
+                                                      int irq)
+{
+        return &max8907c_irqs[irq - chip->irq_base];
+}
+
+static irqreturn_t max8907c_irq(int irq, void *data)
+{
+        struct max8907c *chip = data;
+        struct max8907c_irq_data *irq_data;
+        struct i2c_client *i2c;
+        int read_reg = -1, value = 0;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(max8907c_irqs); i++) {
+                irq_data = &max8907c_irqs[i];
+
+                if (irq_data->is_rtc)
+                        i2c = chip->i2c_rtc;
+                else
+                        i2c = chip->i2c_power;
+
+                if (read_reg != irq_data->reg) {
+                        read_reg = irq_data->reg;
+                        value = max8907c_reg_read(i2c, irq_data->reg);
+                }
+
+                if (value & irq_data->enable)
+                        handle_nested_irq(chip->irq_base + i);
+        }
+        return IRQ_HANDLED;
+}
+
+static void max8907c_irq_lock(struct irq_data *data)
+{
+        struct max8907c *chip = irq_data_get_irq_chip_data(data);
+
+        mutex_lock(&chip->irq_lock);
+}
+
+static void max8907c_irq_sync_unlock(struct irq_data *data)
+{
+        struct max8907c *chip = irq_data_get_irq_chip_data(data);
+        struct max8907c_irq_data *irq_data;
+        unsigned char irq_chg[2], irq_on[2];
+        unsigned char irq_rtc;
+        int i;
+
+        irq_chg[0] = irq_chg[1] = irq_on[0] = irq_on[1] = irq_rtc = 0xFF;
+
+        for (i = 0; i < ARRAY_SIZE(max8907c_irqs); i++) {
+                irq_data = &max8907c_irqs[i];
+                /* 1 -- disable, 0 -- enable */
+                switch (irq_data->mask_reg) {
+                case MAX8907C_REG_CHG_IRQ1_MASK:
+                        irq_chg[0] &= ~irq_data->enable;
+                        break;
+                case MAX8907C_REG_CHG_IRQ2_MASK:
+                        irq_chg[1] &= ~irq_data->enable;
+                        break;
+                case MAX8907C_REG_ON_OFF_IRQ1_MASK:
+                        irq_on[0] &= ~irq_data->enable;
+                        break;
+                case MAX8907C_REG_ON_OFF_IRQ2_MASK:
+                        irq_on[1] &= ~irq_data->enable;
+                        break;
+                case MAX8907C_REG_RTC_IRQ_MASK:
+                        irq_rtc &= ~irq_data->enable;
+                        break;
+                default:
+                        dev_err(chip->dev, "wrong IRQ\n");
+                        break;
+                }
+        }
+        /* update mask into registers */
+        if (chip->cache_chg[0] != irq_chg[0]) {
+                chip->cache_chg[0] = irq_chg[0];
+                max8907c_reg_write(chip->i2c_power, MAX8907C_REG_CHG_IRQ1_MASK,
+                        irq_chg[0]);
+        }
+        if (chip->cache_chg[1] != irq_chg[1]) {
+                chip->cache_chg[1] = irq_chg[1];
+                max8907c_reg_write(chip->i2c_power, MAX8907C_REG_CHG_IRQ2_MASK,
+                        irq_chg[1]);
+        }
+        if (chip->cache_on[0] != irq_on[0]) {
+                chip->cache_on[0] = irq_on[0];
+                max8907c_reg_write(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ1_MASK,
+                                irq_on[0]);
+        }
+        if (chip->cache_on[1] != irq_on[1]) {
+                chip->cache_on[1] = irq_on[1];
+                max8907c_reg_write(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ2_MASK,
+                                irq_on[1]);
+        }
+        if (chip->cache_rtc != irq_rtc) {
+                chip->cache_rtc = irq_rtc;
+                max8907c_reg_write(chip->i2c_rtc, MAX8907C_REG_RTC_IRQ_MASK,
+                                   irq_rtc);
+        }
+
+        mutex_unlock(&chip->irq_lock);
+}
+
+static void max8907c_irq_enable(struct irq_data *data)
+{
+        struct max8907c *chip = irq_data_get_irq_chip_data(data);
+        max8907c_irqs[data->irq - chip->irq_base].enable
+                = max8907c_irqs[data->irq - chip->irq_base].offs;
+}
+
+static void max8907c_irq_disable(struct irq_data *data)
+{
+        struct max8907c *chip = irq_data_get_irq_chip_data(data);
+        max8907c_irqs[data->irq - chip->irq_base].enable = 0;
+}
+
+static int max8907c_irq_set_wake(struct irq_data *data, unsigned int on)
+{
+        struct max8907c *chip = irq_data_get_irq_chip_data(data);
+        if (on) {
+                max8907c_irqs[data->irq - chip->irq_base].wake
+                        = max8907c_irqs[data->irq - chip->irq_base].enable;
+        } else {
+                max8907c_irqs[data->irq - chip->irq_base].wake = 0;
+        }
+        return 0;
+}
+
+static struct irq_chip max8907c_irq_chip = {
+        .name                   = "max8907c",
+        .irq_bus_lock           = max8907c_irq_lock,
+        .irq_bus_sync_unlock    = max8907c_irq_sync_unlock,
+        .irq_enable             = max8907c_irq_enable,
+        .irq_disable            = max8907c_irq_disable,
+        .irq_set_wake           = max8907c_irq_set_wake,
+};
+
+int max8907c_irq_init(struct max8907c *chip, int irq, int irq_base)
+{
+        unsigned long flags = IRQF_ONESHOT;
+        struct irq_desc *desc;
+        int i, ret;
+        int __irq;
+
+        if (!irq_base || !irq) {
+                dev_warn(chip->dev, "No interrupt support\n");
+                return -EINVAL;
+        }
+        /* clear all interrupts */
+        max8907c_reg_read(chip->i2c_power, MAX8907C_REG_CHG_IRQ1);
+        max8907c_reg_read(chip->i2c_power, MAX8907C_REG_CHG_IRQ2);
+        max8907c_reg_read(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ1);
+        max8907c_reg_read(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ2);
+        max8907c_reg_read(chip->i2c_rtc, MAX8907C_REG_RTC_IRQ);
+        /* mask all interrupts */
+        max8907c_reg_write(chip->i2c_rtc, MAX8907C_REG_ALARM0_CNTL, 0);
+        max8907c_reg_write(chip->i2c_rtc, MAX8907C_REG_ALARM1_CNTL, 0);
+        max8907c_reg_write(chip->i2c_power, MAX8907C_REG_CHG_IRQ1_MASK, 0xff);
+        max8907c_reg_write(chip->i2c_power, MAX8907C_REG_CHG_IRQ2_MASK, 0xff);
+        max8907c_reg_write(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ1_MASK, 0xff);
+        max8907c_reg_write(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ2_MASK, 0xff);
+        max8907c_reg_write(chip->i2c_rtc, MAX8907C_REG_RTC_IRQ_MASK, 0xff);
+
+        chip->cache_chg[0] = chip->cache_chg[1] =
+                chip->cache_on[0] = chip->cache_on[1] =
+                chip->cache_rtc = 0xFF;
+
+        mutex_init(&chip->irq_lock);
+        chip->core_irq = irq;
+        chip->irq_base = irq_base;
+        desc = irq_to_desc(chip->core_irq);
+
+        /* register with genirq */
+        for (i = 0; i < ARRAY_SIZE(max8907c_irqs); i++) {
+                __irq = i + chip->irq_base;
+                irq_set_chip_data(__irq, chip);
+                irq_set_chip_and_handler(__irq, &max8907c_irq_chip,
+                                         handle_edge_irq);
+                irq_set_nested_thread(__irq, 1);
+#ifdef CONFIG_ARM
+                /* ARM requires an extra step to clear IRQ_NOREQUEST, which it
+                 * sets on behalf of every irq_chip.
+                 */
+                set_irq_flags(__irq, IRQF_VALID);
+#else
+                irq_set_noprobe(__irq);
+#endif
+        }
+
+        ret = request_threaded_irq(irq, NULL, max8907c_irq, flags,
+                                   "max8907c", chip);
+        if (ret) {
+                dev_err(chip->dev, "Failed to request core IRQ: %d\n", ret);
+                chip->core_irq = 0;
+        }
+
+        device_init_wakeup(chip->dev, 1);
+
+        return ret;
+}
+
+int max8907c_suspend(struct i2c_client *i2c, pm_message_t state)
+{
+        struct max8907c *chip = i2c_get_clientdata(i2c);
+
+        struct max8907c_irq_data *irq_data;
+        unsigned char irq_chg[2], irq_on[2];
+        unsigned char irq_rtc;
+        int i;
+
+        irq_chg[0] = irq_chg[1] = irq_on[0] = irq_on[1] = irq_rtc = 0xFF;
+
+        for (i = 0; i < ARRAY_SIZE(max8907c_irqs); i++) {
+                irq_data = &max8907c_irqs[i];
+                /* 1 -- disable, 0 -- enable */
+                switch (irq_data->mask_reg) {
+                case MAX8907C_REG_CHG_IRQ1_MASK:
+                        irq_chg[0] &= ~irq_data->wake;
+                        break;
+                case MAX8907C_REG_CHG_IRQ2_MASK:
+                        irq_chg[1] &= ~irq_data->wake;
+                        break;
+                case MAX8907C_REG_ON_OFF_IRQ1_MASK:
+                        irq_on[0] &= ~irq_data->wake;
+                        break;
+                case MAX8907C_REG_ON_OFF_IRQ2_MASK:
+                        irq_on[1] &= ~irq_data->wake;
+                        break;
+                case MAX8907C_REG_RTC_IRQ_MASK:
+                        irq_rtc &= ~irq_data->wake;
+                        break;
+                default:
+                        dev_err(chip->dev, "wrong IRQ\n");
+                        break;
+                }
+        }
+
+        max8907c_reg_write(chip->i2c_power, MAX8907C_REG_CHG_IRQ1_MASK, irq_chg[0]);
+        max8907c_reg_write(chip->i2c_power, MAX8907C_REG_CHG_IRQ2_MASK, irq_chg[1]);
+        max8907c_reg_write(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ1_MASK, irq_on[0]);
+        max8907c_reg_write(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ2_MASK, irq_on[1]);
+        max8907c_reg_write(chip->i2c_rtc, MAX8907C_REG_RTC_IRQ_MASK, irq_rtc);
+
+        if (device_may_wakeup(chip->dev))
+                enable_irq_wake(chip->core_irq);
+        else
+                disable_irq(chip->core_irq);
+
+        return 0;
+}
+
+int max8907c_resume(struct i2c_client *i2c)
+{
+        struct max8907c *chip = i2c_get_clientdata(i2c);
+
+        if (device_may_wakeup(chip->dev))
+                disable_irq_wake(chip->core_irq);
+        else
+                enable_irq(chip->core_irq);
+
+        max8907c_reg_write(chip->i2c_power, MAX8907C_REG_CHG_IRQ1_MASK, chip->cache_chg[0]);
+        max8907c_reg_write(chip->i2c_power, MAX8907C_REG_CHG_IRQ2_MASK, chip->cache_chg[1]);
+        max8907c_reg_write(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ1_MASK, chip->cache_on[0]);
+        max8907c_reg_write(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ2_MASK, chip->cache_on[1]);
+        max8907c_reg_write(chip->i2c_rtc, MAX8907C_REG_RTC_IRQ_MASK, chip->cache_rtc);
+
+        return 0;
+}
+
+void max8907c_irq_free(struct max8907c *chip)
+{
+        if (chip->core_irq)
+                free_irq(chip->core_irq, chip);
+}
+
diff --git a/drivers/mfd/max8907c.c b/drivers/mfd/max8907c.c
new file mode 100644
index 00000000000..d03dbced21e
--- /dev/null
+++ b/drivers/mfd/max8907c.c
@@ -0,0 +1,376 @@
+/*
+ * max8907c.c - mfd driver for MAX8907c
+ *
+ * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/max8907c.h>
+
+static struct mfd_cell cells[] = {
+        {.name = "max8907-regulator",},
+        {.name = "max8907c-rtc",},
+};
+
+static int max8907c_i2c_read(struct i2c_client *i2c, u8 reg, u8 count, u8 *dest)
+{
+        struct i2c_msg xfer[2];
+        int ret = 0;
+
+        xfer[0].addr = i2c->addr;
+        xfer[0].flags = I2C_M_NOSTART;
+        xfer[0].len = 1;
+        xfer[0].buf = &reg;
+
+        xfer[1].addr = i2c->addr;
+        xfer[1].flags = I2C_M_RD;
+        xfer[1].len = count;
+        xfer[1].buf = dest;
+
+        ret = i2c_transfer(i2c->adapter, xfer, 2);
+        if (ret < 0)
+                return ret;
+        if (ret != 2)
+                return -EIO;
+
+        return 0;
+}
+
+static int max8907c_i2c_write(struct i2c_client *i2c, u8 reg, u8 count, const u8 *src)
+{
+        u8 msg[0x100 + 1];
+        int ret = 0;
+
+        msg[0] = reg;
+        memcpy(&msg[1], src, count);
+
+        ret = i2c_master_send(i2c, msg, count + 1);
+        if (ret < 0)
+                return ret;
+        if (ret != count + 1)
+                return -EIO;
+
+        return 0;
+}
+
+int max8907c_reg_read(struct i2c_client *i2c, u8 reg)
+{
+        int ret;
+        u8 val;
+
+        ret = max8907c_i2c_read(i2c, reg, 1, &val);
+
+        pr_debug("max8907c: reg read  reg=%x, val=%x\n",
+                 (unsigned int)reg, (unsigned int)val);
+
+        if (ret != 0)
+                pr_err("Failed to read max8907c I2C driver: %d\n", ret);
+        return val;
+}
+EXPORT_SYMBOL_GPL(max8907c_reg_read);
+
+int max8907c_reg_bulk_read(struct i2c_client *i2c, u8 reg, u8 count, u8 *val)
+{
+        int ret;
+
+        ret = max8907c_i2c_read(i2c, reg, count, val);
+
+        pr_debug("max8907c: reg read  reg=%x, val=%x\n",
+                 (unsigned int)reg, (unsigned int)*val);
+
+        if (ret != 0)
+                pr_err("Failed to read max8907c I2C driver: %d\n", ret);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(max8907c_reg_bulk_read);
+
+int max8907c_reg_write(struct i2c_client *i2c, u8 reg, u8 val)
+{
+        struct max8907c *max8907c = i2c_get_clientdata(i2c);
+        int ret;
+
+        pr_debug("max8907c: reg write  reg=%x, val=%x\n",
+                 (unsigned int)reg, (unsigned int)val);
+
+        mutex_lock(&max8907c->io_lock);
+        ret = max8907c_i2c_write(i2c, reg, 1, &val);
+        mutex_unlock(&max8907c->io_lock);
+
+        if (ret != 0)
+                pr_err("Failed to write max8907c I2C driver: %d\n", ret);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(max8907c_reg_write);
+
+int max8907c_reg_bulk_write(struct i2c_client *i2c, u8 reg, u8 count, u8 *val)
+{
+        struct max8907c *max8907c = i2c_get_clientdata(i2c);
+        int ret;
+
+        pr_debug("max8907c: reg write  reg=%x, val=%x\n",
+                 (unsigned int)reg, (unsigned int)*val);
+
+        mutex_lock(&max8907c->io_lock);
+        ret = max8907c_i2c_write(i2c, reg, count, val);
+        mutex_unlock(&max8907c->io_lock);
+
+        if (ret != 0)
+                pr_err("Failed to write max8907c I2C driver: %d\n", ret);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(max8907c_reg_bulk_write);
+
+int max8907c_set_bits(struct i2c_client *i2c, u8 reg, u8 mask, u8 val)
+{
+        struct max8907c *max8907c = i2c_get_clientdata(i2c);
+        u8 tmp;
+        int ret;
+
+        pr_debug("max8907c: reg write  reg=%02X, val=%02X, mask=%02X\n",
+                 (unsigned int)reg, (unsigned int)val, (unsigned int)mask);
+
+        mutex_lock(&max8907c->io_lock);
+        ret = max8907c_i2c_read(i2c, reg, 1, &tmp);
+        if (ret == 0) {
+                val = (tmp & ~mask) | (val & mask);
+                ret = max8907c_i2c_write(i2c, reg, 1, &val);
+        }
+        mutex_unlock(&max8907c->io_lock);
+
+        if (ret != 0)
+                pr_err("Failed to write max8907c I2C driver: %d\n", ret);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(max8907c_set_bits);
+
+static struct i2c_client *max8907c_client = NULL;
+static void max8907c_power_off(void)
+{
+        if (!max8907c_client)
+                return;
+
+        max8907c_set_bits(max8907c_client, MAX8907C_REG_RESET_CNFG,
+                                                MAX8907C_MASK_POWER_OFF, 0x40);
+}
+
+void max8907c_deep_sleep(int enter)
+{
+        if (!max8907c_client)
+                return;
+
+        if (enter) {
+                max8907c_reg_write(max8907c_client, MAX8907C_REG_SDSEQCNT1,
+                                                MAX8907C_POWER_UP_DELAY_CNT12);
+                max8907c_reg_write(max8907c_client, MAX8907C_REG_SDSEQCNT2,
+                                                        MAX8907C_DELAY_CNT0);
+                max8907c_reg_write(max8907c_client, MAX8907C_REG_SDCTL2,
+                                                        MAX8907C_SD_SEQ2);
+        } else {
+                max8907c_reg_write(max8907c_client, MAX8907C_REG_SDSEQCNT1,
+                                                        MAX8907C_DELAY_CNT0);
+                max8907c_reg_write(max8907c_client, MAX8907C_REG_SDCTL2,
+                                                        MAX8907C_SD_SEQ1);
+                max8907c_reg_write(max8907c_client, MAX8907C_REG_SDSEQCNT2,
+                                MAX8907C_POWER_UP_DELAY_CNT1 | MAX8907C_POWER_DOWN_DELAY_CNT12);
+        }
+}
+
+static int max8907c_remove_subdev(struct device *dev, void *unused)
+{
+        platform_device_unregister(to_platform_device(dev));
+        return 0;
+}
+
+static int max8907c_remove_subdevs(struct max8907c *max8907c)
+{
+        return device_for_each_child(max8907c->dev, NULL,
+                                     max8907c_remove_subdev);
+}
+
+static int max8097c_add_subdevs(struct max8907c *max8907c,
+                                struct max8907c_platform_data *pdata)
+{
+        struct platform_device *pdev;
+        int ret;
+        int i;
+
+        for (i = 0; i < pdata->num_subdevs; i++) {
+                pdev = platform_device_alloc(pdata->subdevs[i]->name,
+                                             pdata->subdevs[i]->id);
+
+                pdev->dev.parent = max8907c->dev;
+                pdev->dev.platform_data = pdata->subdevs[i]->dev.platform_data;
+
+                ret = platform_device_add(pdev);
+                if (ret)
+                        goto error;
+        }
+        return 0;
+
+error:
+        max8907c_remove_subdevs(max8907c);
+        return ret;
+}
+
+int max8907c_pwr_en_config(void)
+{
+        int ret;
+        u8 data;
+
+        if (!max8907c_client)
+                return -EINVAL;
+
+        /*
+         * Enable/disable PWREN h/w control mechanism (PWREN signal must be
+         * inactive = high at this time)
+         */
+        ret = max8907c_set_bits(max8907c_client, MAX8907C_REG_RESET_CNFG,
+                                        MAX8907C_MASK_PWR_EN, MAX8907C_PWR_EN);
+        if (ret != 0)
+                return ret;
+
+        /*
+         * When enabled, connect PWREN to SEQ2 by clearing SEQ2 configuration
+         * settings for silicon revision that requires s/w WAR. On other
+         * MAX8907B revisions PWREN is always connected to SEQ2.
+         */
+        data = max8907c_reg_read(max8907c_client, MAX8907C_REG_II2RR);
+
+        if (data == MAX8907B_II2RR_PWREN_WAR) {
+                data = 0x00;
+                ret = max8907c_reg_write(max8907c_client, MAX8907C_REG_SEQ2CNFG, data);
+        }
+        return ret;
+}
+
+int max8907c_pwr_en_attach(void)
+{
+        int ret;
+
+        if (!max8907c_client)
+                return -EINVAL;
+
+        /* No sequencer delay for CPU rail when it is attached */
+        ret = max8907c_reg_write(max8907c_client, MAX8907C_REG_SDSEQCNT1,
+                                                        MAX8907C_DELAY_CNT0);
+        if (ret != 0)
+                return ret;
+
+        return max8907c_set_bits(max8907c_client, MAX8907C_REG_SDCTL1,
+                                        MAX8907C_MASK_CTL_SEQ, MAX8907C_CTL_SEQ);
+}
+
+static int max8907c_i2c_probe(struct i2c_client *i2c,
+                              const struct i2c_device_id *id)
+{
+        struct max8907c *max8907c;
+        struct max8907c_platform_data *pdata = i2c->dev.platform_data;
+        int ret;
+        int i;
+
+        max8907c = kzalloc(sizeof(struct max8907c), GFP_KERNEL);
+        if (max8907c == NULL)
+                return -ENOMEM;
+
+        max8907c->dev = &i2c->dev;
+        dev_set_drvdata(max8907c->dev, max8907c);
+
+        max8907c->i2c_power = i2c;
+        i2c_set_clientdata(i2c, max8907c);
+
+        max8907c->i2c_rtc = i2c_new_dummy(i2c->adapter, RTC_I2C_ADDR);
+        i2c_set_clientdata(max8907c->i2c_rtc, max8907c);
+
+        mutex_init(&max8907c->io_lock);
+
+        for (i = 0; i < ARRAY_SIZE(cells); i++) {
+                cells[i].platform_data = max8907c;
+                cells[i].pdata_size = sizeof(*max8907c);
+        }
+        ret = mfd_add_devices(max8907c->dev, -1, cells, ARRAY_SIZE(cells),
+                              NULL, 0);
+        if (ret != 0) {
+                i2c_unregister_device(max8907c->i2c_rtc);
+                kfree(max8907c);
+                pr_debug("max8907c: failed to add MFD devices   %X\n", ret);
+                return ret;
+        }
+
+        max8907c_client = i2c;
+
+        max8907c_irq_init(max8907c, i2c->irq, pdata->irq_base);
+
+        ret = max8097c_add_subdevs(max8907c, pdata);
+
+        if (pdata->use_power_off && !pm_power_off)
+                pm_power_off = max8907c_power_off;
+
+        if (pdata->max8907c_setup)
+                return pdata->max8907c_setup();
+
+        return ret;
+}
+
+static int max8907c_i2c_remove(struct i2c_client *i2c)
+{
+        struct max8907c *max8907c = i2c_get_clientdata(i2c);
+
+        max8907c_remove_subdevs(max8907c);
+        i2c_unregister_device(max8907c->i2c_rtc);
+        mfd_remove_devices(max8907c->dev);
+        max8907c_irq_free(max8907c);
+        kfree(max8907c);
+
+        return 0;
+}
+
+static const struct i2c_device_id max8907c_i2c_id[] = {
+        {"max8907c", 0},
+        {}
+};
+
+MODULE_DEVICE_TABLE(i2c, max8907c_i2c_id);
+
+static struct i2c_driver max8907c_i2c_driver = {
+        .driver = {
+                   .name = "max8907c",
+                   .owner = THIS_MODULE,
+                   },
+        .probe = max8907c_i2c_probe,
+        .remove = max8907c_i2c_remove,
+        .suspend = max8907c_suspend,
+        .resume = max8907c_resume,
+        .id_table = max8907c_i2c_id,
+};
+
+static int __init max8907c_i2c_init(void)
+{
+        int ret = -ENODEV;
+
+        ret = i2c_add_driver(&max8907c_i2c_driver);
+        if (ret != 0)
+                pr_err("Failed to register I2C driver: %d\n", ret);
+
+        return ret;
+}
+
+subsys_initcall(max8907c_i2c_init);
+
+static void __exit max8907c_i2c_exit(void)
+{
+        i2c_del_driver(&max8907c_i2c_driver);
+}
+
+module_exit(max8907c_i2c_exit);
+
+MODULE_DESCRIPTION("MAX8907C multi-function core driver");
+MODULE_AUTHOR("Gyungoh Yoo <jack.yoo@maxim-ic.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/ricoh583.c b/drivers/mfd/ricoh583.c
new file mode 100644
index 00000000000..a29053ebaf8
--- /dev/null
+++ b/drivers/mfd/ricoh583.c
@@ -0,0 +1,1213 @@
+/*
+ * driver/mfd/ricoh583.c
+ *
+ * Core driver implementation to access RICOH583 power management chip.
+ *
+ * Copyright (C) 2011 NVIDIA Corporation
+ *
+ * Copyright (C) 2011 RICOH COMPANY,LTD
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ */
+/*#define DEBUG                 1*/
+/*#define VERBOSE_DEBUG         1*/
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/ricoh583.h>
+
+#define RICOH_ONOFFSEL_REG      0x10
+#define RICOH_SWCTL_REG         0x5E
+
+/* Interrupt enable register */
+#define RICOH583_INT_EN_SYS1    0x19
+#define RICOH583_INT_EN_SYS2    0x1D
+#define RICOH583_INT_EN_DCDC    0x41
+#define RICOH583_INT_EN_RTC     0xED
+#define RICOH583_INT_EN_ADC1    0x90
+#define RICOH583_INT_EN_ADC2    0x91
+#define RICOH583_INT_EN_ADC3    0x92
+#define RICOH583_INT_EN_GPIO    0xA8
+
+/* interrupt status registers (monitor regs in Ricoh)*/
+#define RICOH583_INTC_INTPOL    0xAD
+#define RICOH583_INTC_INTEN     0xAE
+#define RICOH583_INTC_INTMON    0xAF
+
+#define RICOH583_INT_MON_GRP    0xAF
+#define RICOH583_INT_MON_SYS1   0x1B
+#define RICOH583_INT_MON_SYS2   0x1F
+#define RICOH583_INT_MON_DCDC   0x43
+#define RICOH583_INT_MON_RTC    0xEE
+
+/* interrupt clearing registers */
+#define RICOH583_INT_IR_SYS1    0x1A
+#define RICOH583_INT_IR_SYS2    0x1E
+#define RICOH583_INT_IR_DCDC    0x42
+#define RICOH583_INT_IR_RTC     0xEE
+#define RICOH583_INT_IR_ADCL    0x94
+#define RICOH583_INT_IR_ADCH    0x95
+#define RICOH583_INT_IR_ADCEND  0x96
+#define RICOH583_INT_IR_GPIOR   0xA9
+#define RICOH583_INT_IR_GPIOF   0xAA
+
+/* GPIO register base address */
+#define RICOH583_GPIO_IOSEL     0xA0
+#define RICOH583_GPIO_PDEN      0xA1
+#define RICOH583_GPIO_IOOUT     0xA2
+#define RICOH583_GPIO_PGSEL     0xA3
+#define RICOH583_GPIO_GPINV     0xA4
+#define RICOH583_GPIO_GPDEB     0xA5
+#define RICOH583_GPIO_GPEDGE1   0xA6
+#define RICOH583_GPIO_GPEDGE2   0xA7
+#define RICOH583_GPIO_EN_GPIR   0xA8
+#define RICOH583_GPIO_MON_IOIN  0xAB
+#define RICOH583_GPIO_GPOFUNC   0xAC
+#define RICOH583_INTC_INTEN     0xAE
+
+enum int_type {
+        SYS_INT  = 0x1,
+        DCDC_INT = 0x2,
+        RTC_INT  = 0x4,
+        ADC_INT  = 0x8,
+        GPIO_INT = 0x10,
+};
+
+struct ricoh583_irq_data {
+        u8      int_type;
+        u8      master_bit;
+        u8      int_en_bit;
+        u8      mask_reg_index;
+        int     grp_index;
+};
+
+struct deepsleep_control_data {
+        u8 reg_add;
+        u8 ds_pos_bit;
+};
+
+#define RICOH583_IRQ(_int_type, _master_bit, _grp_index, _int_bit, _mask_ind) \
+        {                                               \
+                .int_type       = _int_type,            \
+                .master_bit     = _master_bit,          \
+                .grp_index      = _grp_index,           \
+                .int_en_bit     = _int_bit,             \
+                .mask_reg_index = _mask_ind,            \
+        }
+
+static const struct ricoh583_irq_data ricoh583_irqs[] = {
+        [RICOH583_IRQ_ONKEY]            = RICOH583_IRQ(SYS_INT,  0, 0, 0, 0),
+        [RICOH583_IRQ_ACOK]             = RICOH583_IRQ(SYS_INT,  0, 1, 1, 0),
+        [RICOH583_IRQ_LIDOPEN]          = RICOH583_IRQ(SYS_INT,  0, 2, 2, 0),
+        [RICOH583_IRQ_PREOT]            = RICOH583_IRQ(SYS_INT,  0, 3, 3, 0),
+        [RICOH583_IRQ_CLKSTP]           = RICOH583_IRQ(SYS_INT,  0, 4, 4, 0),
+        [RICOH583_IRQ_ONKEY_OFF]        = RICOH583_IRQ(SYS_INT,  0, 5, 5, 0),
+        [RICOH583_IRQ_WD]               = RICOH583_IRQ(SYS_INT,  0, 7, 7, 0),
+        [RICOH583_IRQ_EN_PWRREQ1]       = RICOH583_IRQ(SYS_INT,  0, 8, 0, 1),
+        [RICOH583_IRQ_EN_PWRREQ2]       = RICOH583_IRQ(SYS_INT,  0, 9, 1, 1),
+        [RICOH583_IRQ_PRE_VINDET]       = RICOH583_IRQ(SYS_INT,  0, 10, 2, 1),
+
+        [RICOH583_IRQ_DC0LIM]           = RICOH583_IRQ(DCDC_INT, 1, 0, 0, 2),
+        [RICOH583_IRQ_DC1LIM]           = RICOH583_IRQ(DCDC_INT, 1, 1, 1, 2),
+        [RICOH583_IRQ_DC2LIM]           = RICOH583_IRQ(DCDC_INT, 1, 2, 2, 2),
+        [RICOH583_IRQ_DC3LIM]           = RICOH583_IRQ(DCDC_INT, 1, 3, 3, 2),
+
+        [RICOH583_IRQ_CTC]              = RICOH583_IRQ(RTC_INT,  2, 0, 0, 3),
+        [RICOH583_IRQ_YALE]             = RICOH583_IRQ(RTC_INT,  2, 5, 5, 3),
+        [RICOH583_IRQ_DALE]             = RICOH583_IRQ(RTC_INT,  2, 6, 6, 3),
+        [RICOH583_IRQ_WALE]             = RICOH583_IRQ(RTC_INT,  2, 7, 7, 3),
+
+        [RICOH583_IRQ_AIN1L]            = RICOH583_IRQ(ADC_INT,  3, 0, 0, 4),
+        [RICOH583_IRQ_AIN2L]            = RICOH583_IRQ(ADC_INT,  3, 1, 1, 4),
+        [RICOH583_IRQ_AIN3L]            = RICOH583_IRQ(ADC_INT,  3, 2, 2, 4),
+        [RICOH583_IRQ_VBATL]            = RICOH583_IRQ(ADC_INT,  3, 3, 3, 4),
+        [RICOH583_IRQ_VIN3L]            = RICOH583_IRQ(ADC_INT,  3, 4, 4, 4),
+        [RICOH583_IRQ_VIN8L]            = RICOH583_IRQ(ADC_INT,  3, 5, 5, 4),
+        [RICOH583_IRQ_AIN1H]            = RICOH583_IRQ(ADC_INT,  3, 6, 0, 5),
+        [RICOH583_IRQ_AIN2H]            = RICOH583_IRQ(ADC_INT,  3, 7, 1, 5),
+        [RICOH583_IRQ_AIN3H]            = RICOH583_IRQ(ADC_INT,  3, 8, 2, 5),
+        [RICOH583_IRQ_VBATH]            = RICOH583_IRQ(ADC_INT,  3, 9, 3, 5),
+        [RICOH583_IRQ_VIN3H]            = RICOH583_IRQ(ADC_INT,  3, 10, 4, 5),
+        [RICOH583_IRQ_VIN8H]            = RICOH583_IRQ(ADC_INT,  3, 11, 5, 5),
+        [RICOH583_IRQ_ADCEND]           = RICOH583_IRQ(ADC_INT,  3, 12, 0, 6),
+
+        [RICOH583_IRQ_GPIO0]            = RICOH583_IRQ(GPIO_INT, 4, 0, 0, 7),
+        [RICOH583_IRQ_GPIO1]            = RICOH583_IRQ(GPIO_INT, 4, 1, 1, 7),
+        [RICOH583_IRQ_GPIO2]            = RICOH583_IRQ(GPIO_INT, 4, 2, 2, 7),
+        [RICOH583_IRQ_GPIO3]            = RICOH583_IRQ(GPIO_INT, 4, 3, 3, 7),
+        [RICOH583_IRQ_GPIO4]            = RICOH583_IRQ(GPIO_INT, 4, 4, 4, 7),
+        [RICOH583_IRQ_GPIO5]            = RICOH583_IRQ(GPIO_INT, 4, 5, 5, 7),
+        [RICOH583_IRQ_GPIO6]            = RICOH583_IRQ(GPIO_INT, 4, 6, 6, 7),
+        [RICOH583_IRQ_GPIO7]            = RICOH583_IRQ(GPIO_INT, 4, 7, 7, 7),
+        [RICOH583_NR_IRQS]              = RICOH583_IRQ(GPIO_INT, 4, 8, 8, 7),
+};
+
+#define DEEPSLEEP_INIT(_id, _reg, _pos)         \
+        [RICOH583_DS_##_id] = {.reg_add = _reg, .ds_pos_bit = _pos}
+
+static struct deepsleep_control_data deepsleep_data[] = {
+        DEEPSLEEP_INIT(DC1, 0x21, 4),
+        DEEPSLEEP_INIT(DC2, 0x22, 0),
+        DEEPSLEEP_INIT(DC3, 0x22, 4),
+        DEEPSLEEP_INIT(LDO0, 0x23, 0),
+        DEEPSLEEP_INIT(LDO1, 0x23, 4),
+        DEEPSLEEP_INIT(LDO2, 0x24, 0),
+        DEEPSLEEP_INIT(LDO3, 0x24, 4),
+        DEEPSLEEP_INIT(LDO4, 0x25, 0),
+        DEEPSLEEP_INIT(LDO5, 0x25, 4),
+        DEEPSLEEP_INIT(LDO6, 0x26, 0),
+        DEEPSLEEP_INIT(LDO7, 0x26, 4),
+        DEEPSLEEP_INIT(LDO8, 0x27, 0),
+        DEEPSLEEP_INIT(LDO9, 0x27, 4),
+        DEEPSLEEP_INIT(PSO0, 0x28, 0),
+        DEEPSLEEP_INIT(PSO1, 0x28, 4),
+        DEEPSLEEP_INIT(PSO2, 0x29, 0),
+        DEEPSLEEP_INIT(PSO3, 0x29, 4),
+        DEEPSLEEP_INIT(PSO4, 0x2A, 0),
+        DEEPSLEEP_INIT(PSO5, 0x2A, 4),
+        DEEPSLEEP_INIT(PSO6, 0x2B, 0),
+        DEEPSLEEP_INIT(PSO7, 0x2B, 4),
+};
+
+#define MAX_INTERRUPT_MASKS     8
+#define MAX_MAIN_INTERRUPT      5
+#define EXT_PWR_REQ             \
+        (RICOH583_EXT_PWRREQ1_CONTROL | RICOH583_EXT_PWRREQ2_CONTROL)
+
+struct ricoh583 {
+        struct device           *dev;
+        struct i2c_client       *client;
+        struct mutex            io_lock;
+        int                     gpio_base;
+        struct gpio_chip        gpio;
+        int                     irq_base;
+        struct irq_chip         irq_chip;
+        struct mutex            irq_lock;
+        unsigned long           group_irq_en[MAX_MAIN_INTERRUPT];
+
+        /* For main interrupt bits in INTC */
+        u8                      intc_inten_cache;
+        u8                      intc_inten_reg;
+
+        /* For group interrupt bits and address */
+        u8                      irq_en_cache[MAX_INTERRUPT_MASKS];
+        u8                      irq_en_reg[MAX_INTERRUPT_MASKS];
+        u8                      irq_en_add[MAX_INTERRUPT_MASKS];
+
+        /* Interrupt monitor and clear register */
+        u8                      irq_mon_add[MAX_INTERRUPT_MASKS + 1];
+        u8                      irq_clr_add[MAX_INTERRUPT_MASKS + 1];
+        u8                      main_int_type[MAX_INTERRUPT_MASKS + 1];
+
+        /* For gpio edge */
+        u8                      gpedge_cache[2];
+        u8                      gpedge_reg[2];
+        u8                      gpedge_add[2];
+};
+
+static inline int __ricoh583_read(struct i2c_client *client,
+                                  u8 reg, uint8_t *val)
+{
+        int ret;
+
+        ret = i2c_smbus_read_byte_data(client, reg);
+        if (ret < 0) {
+                dev_err(&client->dev, "failed reading at 0x%02x\n", reg);
+                return ret;
+        }
+
+        *val = (uint8_t)ret;
+        dev_dbg(&client->dev, "ricoh583: reg read  reg=%x, val=%x\n",
+                                reg, *val);
+        return 0;
+}
+
+static inline int __ricoh583_bulk_reads(struct i2c_client *client, u8 reg,
+                                int len, uint8_t *val)
+{
+        int ret;
+        int i;
+
+        ret = i2c_smbus_read_i2c_block_data(client, reg, len, val);
+        if (ret < 0) {
+                dev_err(&client->dev, "failed reading from 0x%02x\n", reg);
+                return ret;
+        }
+        for (i = 0; i < len; ++i) {
+                dev_dbg(&client->dev, "ricoh583: reg read  reg=%x, val=%x\n",
+                                reg + i, *(val + i));
+        }
+        return 0;
+}
+
+static inline int __ricoh583_write(struct i2c_client *client,
+                                 u8 reg, uint8_t val)
+{
+        int ret;
+
+        dev_dbg(&client->dev, "ricoh583: reg write  reg=%x, val=%x\n",
+                                reg, val);
+        ret = i2c_smbus_write_byte_data(client, reg, val);
+        if (ret < 0) {
+                dev_err(&client->dev, "failed writing 0x%02x to 0x%02x\n",
+                                val, reg);
+                return ret;
+        }
+
+        return 0;
+}
+
+static inline int __ricoh583_bulk_writes(struct i2c_client *client, u8 reg,
+                                  int len, uint8_t *val)
+{
+        int ret;
+        int i;
+
+        for (i = 0; i < len; ++i) {
+                dev_dbg(&client->dev, "ricoh583: reg write  reg=%x, val=%x\n",
+                                reg + i, *(val + i));
+        }
+
+        ret = i2c_smbus_write_i2c_block_data(client, reg, len, val);
+        if (ret < 0) {
+                dev_err(&client->dev, "failed writings to 0x%02x\n", reg);
+                return ret;
+        }
+
+        return 0;
+}
+
+int ricoh583_write(struct device *dev, u8 reg, uint8_t val)
+{
+        struct ricoh583 *ricoh583 = dev_get_drvdata(dev);
+        int ret = 0;
+
+        mutex_lock(&ricoh583->io_lock);
+        ret = __ricoh583_write(to_i2c_client(dev), reg, val);
+        mutex_unlock(&ricoh583->io_lock);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(ricoh583_write);
+
+int ricoh583_bulk_writes(struct device *dev, u8 reg, u8 len, uint8_t *val)
+{
+        struct ricoh583 *ricoh583 = dev_get_drvdata(dev);
+        int ret = 0;
+
+        mutex_lock(&ricoh583->io_lock);
+        ret = __ricoh583_bulk_writes(to_i2c_client(dev), reg, len, val);
+        mutex_unlock(&ricoh583->io_lock);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(ricoh583_bulk_writes);
+
+int ricoh583_read(struct device *dev, u8 reg, uint8_t *val)
+{
+        return __ricoh583_read(to_i2c_client(dev), reg, val);
+}
+EXPORT_SYMBOL_GPL(ricoh583_read);
+
+int ricoh583_bulk_reads(struct device *dev, u8 reg, u8 len, uint8_t *val)
+{
+        return __ricoh583_bulk_reads(to_i2c_client(dev), reg, len, val);
+}
+EXPORT_SYMBOL_GPL(ricoh583_bulk_reads);
+
+int ricoh583_set_bits(struct device *dev, u8 reg, uint8_t bit_mask)
+{
+        struct ricoh583 *ricoh583 = dev_get_drvdata(dev);
+        uint8_t reg_val;
+        int ret = 0;
+
+        mutex_lock(&ricoh583->io_lock);
+
+        ret = __ricoh583_read(to_i2c_client(dev), reg, &reg_val);
+        if (ret)
+                goto out;
+
+        if ((reg_val & bit_mask) != bit_mask) {
+                reg_val |= bit_mask;
+                ret = __ricoh583_write(to_i2c_client(dev), reg, reg_val);
+        }
+out:
+        mutex_unlock(&ricoh583->io_lock);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(ricoh583_set_bits);
+
+int ricoh583_clr_bits(struct device *dev, u8 reg, uint8_t bit_mask)
+{
+        struct ricoh583 *ricoh583 = dev_get_drvdata(dev);
+        uint8_t reg_val;
+        int ret = 0;
+
+        mutex_lock(&ricoh583->io_lock);
+
+        ret = __ricoh583_read(to_i2c_client(dev), reg, &reg_val);
+        if (ret)
+                goto out;
+
+        if (reg_val & bit_mask) {
+                reg_val &= ~bit_mask;
+                ret = __ricoh583_write(to_i2c_client(dev), reg, reg_val);
+        }
+out:
+        mutex_unlock(&ricoh583->io_lock);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(ricoh583_clr_bits);
+
+int ricoh583_update(struct device *dev, u8 reg, uint8_t val, uint8_t mask)
+{
+        struct ricoh583 *ricoh583 = dev_get_drvdata(dev);
+        uint8_t reg_val;
+        int ret = 0;
+
+        mutex_lock(&ricoh583->io_lock);
+
+        ret = __ricoh583_read(ricoh583->client, reg, &reg_val);
+        if (ret)
+                goto out;
+
+        if ((reg_val & mask) != val) {
+                reg_val = (reg_val & ~mask) | (val & mask);
+                ret = __ricoh583_write(ricoh583->client, reg, reg_val);
+        }
+out:
+        mutex_unlock(&ricoh583->io_lock);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(ricoh583_update);
+
+static int __ricoh583_set_ext_pwrreq1_control(struct device *dev,
+        enum ricoh583_deepsleep_control_id id,
+        enum ricoh583_ext_pwrreq_control ext_pwr, int slots)
+{
+        int ret;
+        uint8_t sleepseq_val;
+        u8 en_bit;
+        u8 slot_bit;
+
+        if (!(ext_pwr & RICOH583_EXT_PWRREQ1_CONTROL))
+                return 0;
+
+        if (id == RICOH583_DS_DC0) {
+                dev_err(dev, "PWRREQ1 is invalid control for rail %d\n", id);
+                return -EINVAL;
+        }
+
+        en_bit = deepsleep_data[id].ds_pos_bit;
+        slot_bit = en_bit + 1;
+        ret = ricoh583_read(dev, deepsleep_data[id].reg_add, &sleepseq_val);
+        if (ret < 0) {
+                dev_err(dev, "Error in reading reg 0x%x\n",
+                                deepsleep_data[id].reg_add);
+                return ret;
+        }
+
+        sleepseq_val &= ~(0xF << en_bit);
+        sleepseq_val |= (1 << en_bit);
+        sleepseq_val |= ((slots & 0x7) << slot_bit);
+        ret = ricoh583_set_bits(dev, RICOH_ONOFFSEL_REG, (1 << 1));
+        if (ret < 0) {
+                dev_err(dev, "Error in updating the 0x%02x register\n",
+                                RICOH_ONOFFSEL_REG);
+                return ret;
+        }
+
+        ret = ricoh583_write(dev, deepsleep_data[id].reg_add, sleepseq_val);
+        if (ret < 0) {
+                dev_err(dev, "Error in writing reg 0x%x\n",
+                                deepsleep_data[id].reg_add);
+                return ret;
+        }
+
+        if (id == RICOH583_DS_LDO4) {
+                ret = ricoh583_write(dev, RICOH_SWCTL_REG, 0x1);
+                if (ret < 0)
+                        dev_err(dev, "Error in writing reg 0x%x\n",
+                                RICOH_SWCTL_REG);
+        }
+        return ret;
+}
+
+static int __ricoh583_set_ext_pwrreq2_control(struct device *dev,
+        enum ricoh583_deepsleep_control_id id,
+        enum ricoh583_ext_pwrreq_control ext_pwr)
+{
+        int ret;
+
+        if (!(ext_pwr & RICOH583_EXT_PWRREQ2_CONTROL))
+                return 0;
+
+        if (id != RICOH583_DS_DC0) {
+                dev_err(dev, "PWRREQ2 is invalid control for rail %d\n", id);
+                return -EINVAL;
+        }
+
+        ret = ricoh583_set_bits(dev, RICOH_ONOFFSEL_REG, (1 << 2));
+        if (ret < 0)
+                dev_err(dev, "Error in updating the ONOFFSEL 0x10 register\n");
+        return ret;
+}
+
+int ricoh583_ext_power_req_config(struct device *dev,
+        enum ricoh583_deepsleep_control_id id,
+        enum ricoh583_ext_pwrreq_control ext_pwr_req,
+        int deepsleep_slot_nr)
+{
+        if ((ext_pwr_req & EXT_PWR_REQ) == EXT_PWR_REQ)
+                return -EINVAL;
+
+        if (ext_pwr_req & RICOH583_EXT_PWRREQ1_CONTROL)
+                return __ricoh583_set_ext_pwrreq1_control(dev, id,
+                                ext_pwr_req, deepsleep_slot_nr);
+
+        if (ext_pwr_req & RICOH583_EXT_PWRREQ2_CONTROL)
+                return __ricoh583_set_ext_pwrreq2_control(dev,
+                        id, ext_pwr_req);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(ricoh583_ext_power_req_config);
+
+static int __devinit ricoh583_ext_power_init(struct ricoh583 *ricoh583,
+        struct ricoh583_platform_data *pdata)
+{
+        int ret;
+        int i;
+        uint8_t on_off_val = 0;
+
+        /*  Clear ONOFFSEL register */
+        mutex_lock(&ricoh583->io_lock);
+        if (pdata->enable_shutdown_pin)
+                on_off_val |= 0x1;
+
+        ret = __ricoh583_write(ricoh583->client, RICOH_ONOFFSEL_REG,
+                                        on_off_val);
+        if (ret < 0)
+                dev_err(ricoh583->dev, "Error in writing reg %d error: "
+                                "%d\n", RICOH_ONOFFSEL_REG, ret);
+
+        ret = __ricoh583_write(ricoh583->client, RICOH_SWCTL_REG, 0x0);
+        if (ret < 0)
+                dev_err(ricoh583->dev, "Error in writing reg %d error: "
+                                "%d\n", RICOH_SWCTL_REG, ret);
+
+        /* Clear sleepseq register */
+        for (i = 0x21; i < 0x2B; ++i) {
+                ret = __ricoh583_write(ricoh583->client, i, 0x0);
+                if (ret < 0)
+                        dev_err(ricoh583->dev, "Error in writing reg 0x%02x "
+                                "error: %d\n", i, ret);
+        }
+        mutex_unlock(&ricoh583->io_lock);
+        return 0;
+}
+
+static struct i2c_client *ricoh583_i2c_client;
+int ricoh583_power_off(void)
+{
+        if (!ricoh583_i2c_client)
+                return -EINVAL;
+
+        return 0;
+}
+
+static int ricoh583_gpio_get(struct gpio_chip *gc, unsigned offset)
+{
+        struct ricoh583 *ricoh583 = container_of(gc, struct ricoh583, gpio);
+        uint8_t val;
+        int ret;
+
+        ret = __ricoh583_read(ricoh583->client, RICOH583_GPIO_MON_IOIN, &val);
+        if (ret < 0)
+                return ret;
+
+        return ((val & (0x1 << offset)) != 0);
+}
+
+static void ricoh583_gpio_set(struct gpio_chip *chip, unsigned offset,
+                        int value)
+{
+        struct ricoh583 *ricoh583 = container_of(chip, struct ricoh583, gpio);
+        if (value)
+                ricoh583_set_bits(ricoh583->dev, RICOH583_GPIO_IOOUT,
+                                                1 << offset);
+        else
+                ricoh583_clr_bits(ricoh583->dev, RICOH583_GPIO_IOOUT,
+                                                1 << offset);
+}
+
+static int ricoh583_gpio_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct ricoh583 *ricoh583 = container_of(chip, struct ricoh583, gpio);
+
+        return ricoh583_clr_bits(ricoh583->dev, RICOH583_GPIO_IOSEL,
+                                                1 << offset);
+}
+
+static int ricoh583_gpio_output(struct gpio_chip *chip, unsigned offset,
+                                int value)
+{
+        struct ricoh583 *ricoh583 = container_of(chip, struct ricoh583, gpio);
+
+        ricoh583_gpio_set(chip, offset, value);
+        return ricoh583_set_bits(ricoh583->dev, RICOH583_GPIO_IOSEL,
+                                                1 << offset);
+}
+
+static int ricoh583_gpio_to_irq(struct gpio_chip *chip, unsigned off)
+{
+        struct ricoh583 *ricoh583 = container_of(chip, struct ricoh583, gpio);
+
+        if ((off >= 0) && (off < 8))
+                return ricoh583->irq_base + RICOH583_IRQ_GPIO0 + off;
+
+        return -EIO;
+}
+
+static int ricoh583_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+        struct ricoh583 *ricoh583 = container_of(chip, struct ricoh583, gpio);
+        int ret;
+
+        ret = ricoh583_clr_bits(ricoh583->dev, RICOH583_GPIO_PGSEL,
+                        1 << offset);
+        if (ret < 0)
+                dev_err(ricoh583->dev, "%s(): The error in writing register "
+                        "0x%02x\n", __func__, RICOH583_GPIO_PGSEL);
+        return ret;
+}
+
+static void ricoh583_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+        struct ricoh583 *ricoh583 = container_of(chip, struct ricoh583, gpio);
+        int ret;
+
+        ret = ricoh583_set_bits(ricoh583->dev, RICOH583_GPIO_PGSEL,
+                                1 << offset);
+        if (ret < 0)
+                dev_err(ricoh583->dev, "%s(): The error in writing register "
+                        "0x%02x\n", __func__, RICOH583_GPIO_PGSEL);
+}
+
+static void __devinit ricoh583_gpio_init(struct ricoh583 *ricoh583,
+        struct ricoh583_platform_data *pdata)
+{
+        int ret;
+        int i;
+        struct ricoh583_gpio_init_data *ginit;
+
+        if (pdata->gpio_base  <= 0)
+                return;
+
+        ret = ricoh583_write(ricoh583->dev, RICOH583_GPIO_PGSEL, 0xEF);
+        if (ret < 0) {
+                dev_err(ricoh583->dev, "%s(): The error in writing register "
+                        "0x%02x\n", __func__, RICOH583_GPIO_PGSEL);
+                return;
+        }
+
+        for (i = 0; i < pdata->num_gpioinit_data; ++i) {
+                ginit = &pdata->gpio_init_data[i];
+                if (!ginit->init_apply)
+                        continue;
+                if (ginit->pulldn_en)
+                        ret = ricoh583_set_bits(ricoh583->dev,
+                                        RICOH583_GPIO_PDEN, 1 << i);
+                else
+                        ret = ricoh583_clr_bits(ricoh583->dev,
+                                        RICOH583_GPIO_PDEN, 1 << i);
+                if (ret < 0)
+                        dev_err(ricoh583->dev, "Gpio %d init "
+                                "pden configuration failed: %d\n", i, ret);
+
+                if (ginit->output_mode_en) {
+                        if (ginit->output_val)
+                                ret = ricoh583_set_bits(ricoh583->dev,
+                                        RICOH583_GPIO_IOOUT, 1 << i);
+                        else
+                                ret = ricoh583_clr_bits(ricoh583->dev,
+                                        RICOH583_GPIO_IOOUT, 1 << i);
+                        if (!ret)
+                                ret = ricoh583_set_bits(ricoh583->dev,
+                                        RICOH583_GPIO_IOSEL, 1 << i);
+                } else
+                        ret = ricoh583_clr_bits(ricoh583->dev,
+                                        RICOH583_GPIO_IOSEL, 1 << i);
+
+                if (ret < 0)
+                        dev_err(ricoh583->dev, "Gpio %d init "
+                                "dir configuration failed: %d\n", i, ret);
+
+                ret = ricoh583_clr_bits(ricoh583->dev, RICOH583_GPIO_PGSEL,
+                                        1 << i);
+                if (ret < 0)
+                        dev_err(ricoh583->dev, "%s(): The error in writing "
+                                "register 0x%02x\n", __func__,
+                                RICOH583_GPIO_PGSEL);
+        }
+
+        ricoh583->gpio.owner            = THIS_MODULE;
+        ricoh583->gpio.label            = ricoh583->client->name;
+        ricoh583->gpio.dev              = ricoh583->dev;
+        ricoh583->gpio.base             = pdata->gpio_base;
+        ricoh583->gpio.ngpio            = RICOH583_NR_GPIO;
+        ricoh583->gpio.can_sleep        = 1;
+
+        ricoh583->gpio.request  = ricoh583_gpio_request;
+        ricoh583->gpio.free     = ricoh583_gpio_free;
+        ricoh583->gpio.direction_input  = ricoh583_gpio_input;
+        ricoh583->gpio.direction_output = ricoh583_gpio_output;
+        ricoh583->gpio.set              = ricoh583_gpio_set;
+        ricoh583->gpio.get              = ricoh583_gpio_get;
+        ricoh583->gpio.to_irq      = ricoh583_gpio_to_irq;
+
+        ret = gpiochip_add(&ricoh583->gpio);
+        if (ret)
+                dev_warn(ricoh583->dev, "GPIO registration failed: %d\n", ret);
+}
+
+static void ricoh583_irq_lock(struct irq_data *irq_data)
+{
+        struct ricoh583 *ricoh583 = irq_data_get_irq_chip_data(irq_data);
+
+        mutex_lock(&ricoh583->irq_lock);
+}
+
+static void ricoh583_irq_unmask(struct irq_data *irq_data)
+{
+        struct ricoh583 *ricoh583 = irq_data_get_irq_chip_data(irq_data);
+        unsigned int __irq = irq_data->irq - ricoh583->irq_base;
+        const struct ricoh583_irq_data *data = &ricoh583_irqs[__irq];
+
+        ricoh583->group_irq_en[data->grp_index] |= (1 << data->grp_index);
+        if (ricoh583->group_irq_en[data->grp_index])
+                ricoh583->intc_inten_reg |= 1 << data->master_bit;
+
+        ricoh583->irq_en_reg[data->mask_reg_index] |= 1 << data->int_en_bit;
+}
+
+static void ricoh583_irq_mask(struct irq_data *irq_data)
+{
+        struct ricoh583 *ricoh583 = irq_data_get_irq_chip_data(irq_data);
+        unsigned int __irq = irq_data->irq - ricoh583->irq_base;
+        const struct ricoh583_irq_data *data = &ricoh583_irqs[__irq];
+
+        ricoh583->group_irq_en[data->grp_index] &= ~(1 << data->grp_index);
+        if (!ricoh583->group_irq_en[data->grp_index])
+                ricoh583->intc_inten_reg &= ~(1 << data->master_bit);
+
+        ricoh583->irq_en_reg[data->mask_reg_index] &= ~(1 << data->int_en_bit);
+}
+
+static void ricoh583_irq_sync_unlock(struct irq_data *irq_data)
+{
+        struct ricoh583 *ricoh583 = irq_data_get_irq_chip_data(irq_data);
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(ricoh583->gpedge_reg); i++) {
+                if (ricoh583->gpedge_reg[i] != ricoh583->gpedge_cache[i]) {
+                        if (!WARN_ON(__ricoh583_write(ricoh583->client,
+                                                    ricoh583->gpedge_add[i],
+                                                    ricoh583->gpedge_reg[i])))
+                                ricoh583->gpedge_cache[i] =
+                                                ricoh583->gpedge_reg[i];
+                }
+        }
+
+        for (i = 0; i < ARRAY_SIZE(ricoh583->irq_en_reg); i++) {
+                if (ricoh583->irq_en_reg[i] != ricoh583->irq_en_cache[i]) {
+                        if (!WARN_ON(__ricoh583_write(ricoh583->client,
+                                            ricoh583->irq_en_add[i],
+                                                    ricoh583->irq_en_reg[i])))
+                                ricoh583->irq_en_cache[i] =
+                                                ricoh583->irq_en_reg[i];
+                }
+        }
+
+        if (ricoh583->intc_inten_reg != ricoh583->intc_inten_cache) {
+                if (!WARN_ON(__ricoh583_write(ricoh583->client,
+                                RICOH583_INTC_INTEN, ricoh583->intc_inten_reg)))
+                        ricoh583->intc_inten_cache = ricoh583->intc_inten_reg;
+        }
+
+        mutex_unlock(&ricoh583->irq_lock);
+}
+
+static int ricoh583_irq_set_type(struct irq_data *irq_data, unsigned int type)
+{
+        struct ricoh583 *ricoh583 = irq_data_get_irq_chip_data(irq_data);
+        unsigned int __irq = irq_data->irq - ricoh583->irq_base;
+        const struct ricoh583_irq_data *data = &ricoh583_irqs[__irq];
+        int val = 0;
+        int gpedge_index;
+        int gpedge_bit_pos;
+
+        if (data->int_type & GPIO_INT) {
+                gpedge_index = data->int_en_bit / 4;
+                gpedge_bit_pos = data->int_en_bit % 4;
+
+                if (type & IRQ_TYPE_EDGE_FALLING)
+                        val |= 0x2;
+
+                if (type & IRQ_TYPE_EDGE_RISING)
+                        val |= 0x1;
+
+                ricoh583->gpedge_reg[gpedge_index] &= ~(3 << gpedge_bit_pos);
+                ricoh583->gpedge_reg[gpedge_index] |= (val << gpedge_bit_pos);
+                ricoh583_irq_unmask(irq_data);
+        }
+        return 0;
+}
+
+static irqreturn_t ricoh583_irq(int irq, void *data)
+{
+        struct ricoh583 *ricoh583 = data;
+        u8 int_sts[9];
+        u8 master_int;
+        int i;
+        int ret;
+        u8 rtc_int_sts = 0;
+
+        /* Clear the status */
+        for (i = 0; i < 9; i++)
+                int_sts[i] = 0;
+
+        ret  = __ricoh583_read(ricoh583->client, RICOH583_INTC_INTMON,
+                                                &master_int);
+        if (ret < 0) {
+                dev_err(ricoh583->dev, "Error in reading reg 0x%02x "
+                        "error: %d\n", RICOH583_INTC_INTMON, ret);
+                return IRQ_HANDLED;
+        }
+
+        for (i = 0; i < 9; ++i) {
+                if (!(master_int & ricoh583->main_int_type[i]))
+                        continue;
+                ret = __ricoh583_read(ricoh583->client,
+                                ricoh583->irq_mon_add[i], &int_sts[i]);
+                if (ret < 0) {
+                        dev_err(ricoh583->dev, "Error in reading reg 0x%02x "
+                                "error: %d\n", ricoh583->irq_mon_add[i], ret);
+                        int_sts[i] = 0;
+                        continue;
+                }
+
+                if (ricoh583->main_int_type[i] & RTC_INT) {
+                        rtc_int_sts = 0;
+                        if (int_sts[i] & 0x1)
+                                rtc_int_sts |= BIT(6);
+                        if (int_sts[i] & 0x2)
+                                rtc_int_sts |= BIT(7);
+                        if (int_sts[i] & 0x4)
+                                rtc_int_sts |= BIT(0);
+                        if (int_sts[i] & 0x8)
+                                rtc_int_sts |= BIT(5);
+                }
+
+                ret = __ricoh583_write(ricoh583->client,
+                                ricoh583->irq_clr_add[i], ~int_sts[i]);
+                if (ret < 0) {
+                        dev_err(ricoh583->dev, "Error in reading reg 0x%02x "
+                                "error: %d\n", ricoh583->irq_clr_add[i], ret);
+                }
+                if (ricoh583->main_int_type[i] & RTC_INT)
+                        int_sts[i] = rtc_int_sts;
+        }
+
+        /* Merge gpio interrupts  for rising and falling case*/
+        int_sts[7] |= int_sts[8];
+
+        /* Call interrupt handler if enabled */
+        for (i = 0; i < RICOH583_NR_IRQS; ++i) {
+                const struct ricoh583_irq_data *data = &ricoh583_irqs[i];
+                if ((int_sts[data->mask_reg_index] & (1 << data->int_en_bit)) &&
+                        (ricoh583->group_irq_en[data->master_bit] &
+                                        (1 << data->grp_index)))
+                        handle_nested_irq(ricoh583->irq_base + i);
+        }
+        return IRQ_HANDLED;
+}
+
+static int __devinit ricoh583_irq_init(struct ricoh583 *ricoh583, int irq,
+                                int irq_base)
+{
+        int i, ret;
+
+        if (!irq_base) {
+                dev_warn(ricoh583->dev, "No interrupt support on IRQ base\n");
+                return -EINVAL;
+        }
+
+        mutex_init(&ricoh583->irq_lock);
+
+        /* Initialize all locals to 0 */
+        for (i = 0; i < MAX_INTERRUPT_MASKS; i++) {
+                ricoh583->irq_en_cache[i] = 0;
+                ricoh583->irq_en_reg[i] = 0;
+        }
+        ricoh583->intc_inten_cache = 0;
+        ricoh583->intc_inten_reg = 0;
+        for (i = 0; i < 2; i++) {
+                ricoh583->gpedge_cache[i] = 0;
+                ricoh583->gpedge_reg[i] = 0;
+        }
+
+        /* Interrupt enable register */
+        ricoh583->gpedge_add[0] = RICOH583_GPIO_GPEDGE2;
+        ricoh583->gpedge_add[1] = RICOH583_GPIO_GPEDGE1;
+        ricoh583->irq_en_add[0] = RICOH583_INT_EN_SYS1;
+        ricoh583->irq_en_add[1] = RICOH583_INT_EN_SYS2;
+        ricoh583->irq_en_add[2] = RICOH583_INT_EN_DCDC;
+        ricoh583->irq_en_add[3] = RICOH583_INT_EN_RTC;
+        ricoh583->irq_en_add[4] = RICOH583_INT_EN_ADC1;
+        ricoh583->irq_en_add[5] = RICOH583_INT_EN_ADC2;
+        ricoh583->irq_en_add[6] = RICOH583_INT_EN_ADC3;
+        ricoh583->irq_en_add[7] = RICOH583_INT_EN_GPIO;
+
+        /* Interrupt status monitor register */
+        ricoh583->irq_mon_add[0] = RICOH583_INT_MON_SYS1;
+        ricoh583->irq_mon_add[1] = RICOH583_INT_MON_SYS2;
+        ricoh583->irq_mon_add[2] = RICOH583_INT_MON_DCDC;
+        ricoh583->irq_mon_add[3] = RICOH583_INT_MON_RTC;
+        ricoh583->irq_mon_add[4] = RICOH583_INT_IR_ADCL;
+        ricoh583->irq_mon_add[5] = RICOH583_INT_IR_ADCH;
+        ricoh583->irq_mon_add[6] = RICOH583_INT_IR_ADCEND;
+        ricoh583->irq_mon_add[7] = RICOH583_INT_IR_GPIOF;
+        ricoh583->irq_mon_add[8] = RICOH583_INT_IR_GPIOR;
+
+        /* Interrupt status clear register */
+        ricoh583->irq_clr_add[0] = RICOH583_INT_IR_SYS1;
+        ricoh583->irq_clr_add[1] = RICOH583_INT_IR_SYS2;
+        ricoh583->irq_clr_add[2] = RICOH583_INT_IR_DCDC;
+        ricoh583->irq_clr_add[3] = RICOH583_INT_IR_RTC;
+        ricoh583->irq_clr_add[4] = RICOH583_INT_IR_ADCL;
+        ricoh583->irq_clr_add[5] = RICOH583_INT_IR_ADCH;
+        ricoh583->irq_clr_add[6] = RICOH583_INT_IR_ADCEND;
+        ricoh583->irq_clr_add[7] = RICOH583_INT_IR_GPIOF;
+        ricoh583->irq_clr_add[8] = RICOH583_INT_IR_GPIOR;
+
+        ricoh583->main_int_type[0] = SYS_INT;
+        ricoh583->main_int_type[1] = SYS_INT;
+        ricoh583->main_int_type[2] = DCDC_INT;
+        ricoh583->main_int_type[3] = RTC_INT;
+        ricoh583->main_int_type[4] = ADC_INT;
+        ricoh583->main_int_type[5] = ADC_INT;
+        ricoh583->main_int_type[6] = ADC_INT;
+        ricoh583->main_int_type[7] = GPIO_INT;
+        ricoh583->main_int_type[8] = GPIO_INT;
+
+        /* Initailize all int register to 0 */
+        for (i = 0; i < MAX_INTERRUPT_MASKS; i++)  {
+                ret = __ricoh583_write(ricoh583->client,
+                                ricoh583->irq_en_add[i],
+                                ricoh583->irq_en_reg[i]);
+                if (ret < 0)
+                        dev_err(ricoh583->dev, "Error in writing reg 0x%02x "
+                                "error: %d\n", ricoh583->irq_en_add[i], ret);
+        }
+
+        for (i = 0; i < 2; i++)  {
+                ret = __ricoh583_write(ricoh583->client,
+                                ricoh583->gpedge_add[i],
+                                ricoh583->gpedge_reg[i]);
+                if (ret < 0)
+                        dev_err(ricoh583->dev, "Error in writing reg 0x%02x "
+                                "error: %d\n", ricoh583->gpedge_add[i], ret);
+        }
+
+        ret = __ricoh583_write(ricoh583->client, RICOH583_INTC_INTEN, 0x0);
+        if (ret < 0)
+                dev_err(ricoh583->dev, "Error in writing reg 0x%02x "
+                                "error: %d\n", RICOH583_INTC_INTEN, ret);
+
+        /* Clear all interrupts in case they woke up active. */
+        for (i = 0; i < 9; i++)  {
+                ret = __ricoh583_write(ricoh583->client,
+                                        ricoh583->irq_clr_add[i], 0);
+                if (ret < 0)
+                        dev_err(ricoh583->dev, "Error in writing reg 0x%02x "
+                                "error: %d\n", ricoh583->irq_clr_add[i], ret);
+        }
+
+        ricoh583->irq_base = irq_base;
+        ricoh583->irq_chip.name = "ricoh583";
+        ricoh583->irq_chip.irq_mask = ricoh583_irq_mask;
+        ricoh583->irq_chip.irq_unmask = ricoh583_irq_unmask;
+        ricoh583->irq_chip.irq_bus_lock = ricoh583_irq_lock;
+        ricoh583->irq_chip.irq_bus_sync_unlock = ricoh583_irq_sync_unlock;
+        ricoh583->irq_chip.irq_set_type = ricoh583_irq_set_type;
+
+        for (i = 0; i < RICOH583_NR_IRQS; i++) {
+                int __irq = i + ricoh583->irq_base;
+                irq_set_chip_data(__irq, ricoh583);
+                irq_set_chip_and_handler(__irq, &ricoh583->irq_chip,
+                                         handle_simple_irq);
+                irq_set_nested_thread(__irq, 1);
+#ifdef CONFIG_ARM
+                set_irq_flags(__irq, IRQF_VALID);
+#endif
+        }
+
+        ret = request_threaded_irq(irq, NULL, ricoh583_irq, IRQF_ONESHOT,
+                                   "ricoh583", ricoh583);
+        if (ret < 0)
+                dev_err(ricoh583->dev, "Error in registering interrupt "
+                                "error: %d\n", ret);
+        if (!ret) {
+                device_init_wakeup(ricoh583->dev, 1);
+                enable_irq_wake(irq);
+        }
+        return ret;
+}
+
+static int ricoh583_remove_subdev(struct device *dev, void *unused)
+{
+        platform_device_unregister(to_platform_device(dev));
+        return 0;
+}
+
+static int ricoh583_remove_subdevs(struct ricoh583 *ricoh583)
+{
+        return device_for_each_child(ricoh583->dev, NULL,
+                                     ricoh583_remove_subdev);
+}
+
+static int __devinit ricoh583_add_subdevs(struct ricoh583 *ricoh583,
+                                struct ricoh583_platform_data *pdata)
+{
+        struct ricoh583_subdev_info *subdev;
+        struct platform_device *pdev;
+        int i, ret = 0;
+
+        for (i = 0; i < pdata->num_subdevs; i++) {
+                subdev = &pdata->subdevs[i];
+
+                pdev = platform_device_alloc(subdev->name, subdev->id);
+
+                pdev->dev.parent = ricoh583->dev;
+                pdev->dev.platform_data = subdev->platform_data;
+
+                ret = platform_device_add(pdev);
+                if (ret)
+                        goto failed;
+        }
+        return 0;
+
+failed:
+        ricoh583_remove_subdevs(ricoh583);
+        return ret;
+}
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+static void print_regs(const char *header, struct seq_file *s,
+                struct i2c_client *client, int start_offset,
+                int end_offset)
+{
+        uint8_t reg_val;
+        int i;
+        int ret;
+
+        seq_printf(s, "%s\n", header);
+        for (i = start_offset; i <= end_offset; ++i) {
+                ret = __ricoh583_read(client, i, &reg_val);
+                if (ret >= 0)
+                        seq_printf(s, "Reg 0x%02x Value 0x%02x\n", i, reg_val);
+        }
+        seq_printf(s, "------------------\n");
+}
+
+static int dbg_tps_show(struct seq_file *s, void *unused)
+{
+        struct ricoh583 *tps = s->private;
+        struct i2c_client *client = tps->client;
+
+        seq_printf(s, "RICOH583 Registers\n");
+        seq_printf(s, "------------------\n");
+
+        print_regs("System Regs",              s, client, 0x0, 0xF);
+        print_regs("Power Control Regs",        s, client, 0x10, 0x2B);
+        print_regs("DCDC1 Regs",                s, client, 0x30, 0x43);
+        print_regs("DCDC1 Regs",                s, client, 0x60, 0x63);
+        print_regs("LDO   Regs",                s, client, 0x50, 0x5F);
+        print_regs("LDO   Regs",                s, client, 0x64, 0x6D);
+        print_regs("ADC  Regs",          s, client, 0x70, 0x72);
+        print_regs("ADC  Regs",          s, client, 0x74, 0x8B);
+        print_regs("ADC  Regs",          s, client, 0x90, 0x96);
+        print_regs("GPIO Regs",          s, client, 0xA0, 0xAC);
+        print_regs("INTC Regs",          s, client, 0xAD, 0xAF);
+        print_regs("RTC  Regs",          s, client, 0xE0, 0xEE);
+        print_regs("RTC  Regs",          s, client, 0xF0, 0xF4);
+        return 0;
+}
+
+static int dbg_tps_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, dbg_tps_show, inode->i_private);
+}
+
+static const struct file_operations debug_fops = {
+        .open      = dbg_tps_open,
+        .read      = seq_read,
+        .llseek  = seq_lseek,
+        .release        = single_release,
+};
+static void __init ricoh583_debuginit(struct ricoh583 *tps)
+{
+        (void)debugfs_create_file("ricoh583", S_IRUGO, NULL,
+                        tps, &debug_fops);
+}
+#else
+static void __init ricoh583_debuginit(struct ricoh583 *tpsi)
+{
+        return;
+}
+#endif
+
+static int ricoh583_i2c_probe(struct i2c_client *i2c,
+                              const struct i2c_device_id *id)
+{
+        struct ricoh583 *ricoh583;
+        struct ricoh583_platform_data *pdata = i2c->dev.platform_data;
+        int ret;
+
+        ricoh583 = kzalloc(sizeof(struct ricoh583), GFP_KERNEL);
+        if (ricoh583 == NULL)
+                return -ENOMEM;
+
+        ricoh583->client = i2c;
+        ricoh583->dev = &i2c->dev;
+        i2c_set_clientdata(i2c, ricoh583);
+
+        mutex_init(&ricoh583->io_lock);
+
+        ret = ricoh583_ext_power_init(ricoh583, pdata);
+        if (ret < 0)
+                goto err_irq_init;
+
+        if (i2c->irq) {
+                ret = ricoh583_irq_init(ricoh583, i2c->irq, pdata->irq_base);
+                if (ret) {
+                        dev_err(&i2c->dev, "IRQ init failed: %d\n", ret);
+                        goto err_irq_init;
+                }
+        }
+
+        ret = ricoh583_add_subdevs(ricoh583, pdata);
+        if (ret) {
+                dev_err(&i2c->dev, "add devices failed: %d\n", ret);
+                goto err_add_devs;
+        }
+
+        ricoh583_gpio_init(ricoh583, pdata);
+
+        ricoh583_debuginit(ricoh583);
+
+        ricoh583_i2c_client = i2c;
+        return 0;
+
+err_add_devs:
+        if (i2c->irq)
+                free_irq(i2c->irq, ricoh583);
+err_irq_init:
+        kfree(ricoh583);
+        return ret;
+}
+
+static int  __devexit ricoh583_i2c_remove(struct i2c_client *i2c)
+{
+        struct ricoh583 *ricoh583 = i2c_get_clientdata(i2c);
+
+        if (i2c->irq)
+                free_irq(i2c->irq, ricoh583);
+
+        ricoh583_remove_subdevs(ricoh583);
+        kfree(ricoh583);
+        return 0;
+}
+
+#ifdef CONFIG_PM
+static int ricoh583_i2c_suspend(struct i2c_client *i2c, pm_message_t state)
+{
+        if (i2c->irq)
+                disable_irq(i2c->irq);
+        return 0;
+}
+
+
+static int ricoh583_i2c_resume(struct i2c_client *i2c)
+{
+        if (i2c->irq)
+                enable_irq(i2c->irq);
+        return 0;
+}
+
+#endif
+
+static const struct i2c_device_id ricoh583_i2c_id[] = {
+        {"ricoh583", 0},
+        {}
+};
+
+MODULE_DEVICE_TABLE(i2c, ricoh583_i2c_id);
+
+static struct i2c_driver ricoh583_i2c_driver = {
+        .driver = {
+                   .name = "ricoh583",
+                   .owner = THIS_MODULE,
+                   },
+        .probe = ricoh583_i2c_probe,
+        .remove = __devexit_p(ricoh583_i2c_remove),
+#ifdef CONFIG_PM
+        .suspend = ricoh583_i2c_suspend,
+        .resume = ricoh583_i2c_resume,
+#endif
+        .id_table = ricoh583_i2c_id,
+};
+
+
+static int __init ricoh583_i2c_init(void)
+{
+        int ret = -ENODEV;
+        ret = i2c_add_driver(&ricoh583_i2c_driver);
+        if (ret != 0)
+                pr_err("Failed to register I2C driver: %d\n", ret);
+
+        return ret;
+}
+
+subsys_initcall(ricoh583_i2c_init);
+
+static void __exit ricoh583_i2c_exit(void)
+{
+        i2c_del_driver(&ricoh583_i2c_driver);
+}
+
+module_exit(ricoh583_i2c_exit);
+
+MODULE_DESCRIPTION("RICOH583 multi-function core driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/tps65910-irq.c b/drivers/mfd/tps65910-irq.c
new file mode 100644
index 00000000000..c9ed5c00a62
--- /dev/null
+++ b/drivers/mfd/tps65910-irq.c
@@ -0,0 +1,232 @@
+/*
+ * tps65910-irq.c  --  TI TPS6591x
+ *
+ * Copyright 2010 Texas Instruments Inc.
+ *
+ * Author: Graeme Gregory <gg@slimlogic.co.uk>
+ * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/bug.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/mfd/tps65910.h>
+
+static inline int irq_to_tps65910_irq(struct tps65910 *tps65910,
+                                                        int irq)
+{
+        return (irq - tps65910->irq_base);
+}
+
+/*
+ * This is a threaded IRQ handler so can access I2C/SPI.  Since all
+ * interrupts are clear on read the IRQ line will be reasserted and
+ * the physical IRQ will be handled again if another interrupt is
+ * asserted while we run - in the normal course of events this is a
+ * rare occurrence so we save I2C/SPI reads.  We're also assuming that
+ * it's rare to get lots of interrupts firing simultaneously so try to
+ * minimise I/O.
+ */
+static irqreturn_t tps65910_irq(int irq, void *irq_data)
+{
+        struct tps65910 *tps65910 = irq_data;
+        u32 irq_sts;
+        u32 irq_mask;
+        u8 reg;
+        int i;
+
+        tps65910->read(tps65910, TPS65910_INT_STS, 1, &reg);
+        irq_sts = reg;
+        tps65910->read(tps65910, TPS65910_INT_STS2, 1, &reg);
+        irq_sts |= reg << 8;
+        switch (tps65910_chip_id(tps65910)) {
+        case TPS65911:
+                tps65910->read(tps65910, TPS65910_INT_STS3, 1, &reg);
+                irq_sts |= reg << 16;
+        }
+
+        tps65910->read(tps65910, TPS65910_INT_MSK, 1, &reg);
+        irq_mask = reg;
+        tps65910->read(tps65910, TPS65910_INT_MSK2, 1, &reg);
+        irq_mask |= reg << 8;
+        switch (tps65910_chip_id(tps65910)) {
+        case TPS65911:
+                tps65910->read(tps65910, TPS65910_INT_MSK3, 1, &reg);
+                irq_mask |= reg << 16;
+        }
+
+        irq_sts &= ~irq_mask;
+
+        if (!irq_sts)
+                return IRQ_NONE;
+
+        for (i = 0; i < tps65910->irq_num; i++) {
+
+                if (!(irq_sts & (1 << i)))
+                        continue;
+
+                handle_nested_irq(tps65910->irq_base + i);
+        }
+
+        /* Write the STS register back to clear IRQs we handled */
+        reg = irq_sts & 0xFF;
+        irq_sts >>= 8;
+        tps65910->write(tps65910, TPS65910_INT_STS, 1, &reg);
+        reg = irq_sts & 0xFF;
+        tps65910->write(tps65910, TPS65910_INT_STS2, 1, &reg);
+        switch (tps65910_chip_id(tps65910)) {
+        case TPS65911:
+                reg = irq_sts >> 8;
+                tps65910->write(tps65910, TPS65910_INT_STS3, 1, &reg);
+        }
+
+        return IRQ_HANDLED;
+}
+
+static void tps65910_irq_lock(struct irq_data *data)
+{
+        struct tps65910 *tps65910 = irq_data_get_irq_chip_data(data);
+
+        mutex_lock(&tps65910->irq_lock);
+}
+
+static void tps65910_irq_sync_unlock(struct irq_data *data)
+{
+        struct tps65910 *tps65910 = irq_data_get_irq_chip_data(data);
+        u32 reg_mask;
+        u8 reg;
+
+        tps65910->read(tps65910, TPS65910_INT_MSK, 1, &reg);
+        reg_mask = reg;
+        tps65910->read(tps65910, TPS65910_INT_MSK2, 1, &reg);
+        reg_mask |= reg << 8;
+        switch (tps65910_chip_id(tps65910)) {
+        case TPS65911:
+                tps65910->read(tps65910, TPS65910_INT_MSK3, 1, &reg);
+                reg_mask |= reg << 16;
+        }
+
+        if (tps65910->irq_mask != reg_mask) {
+                reg = tps65910->irq_mask & 0xFF;
+                tps65910->write(tps65910, TPS65910_INT_MSK, 1, &reg);
+                reg = tps65910->irq_mask >> 8 & 0xFF;
+                tps65910->write(tps65910, TPS65910_INT_MSK2, 1, &reg);
+                switch (tps65910_chip_id(tps65910)) {
+                case TPS65911:
+                        reg = tps65910->irq_mask >> 16;
+                        tps65910->write(tps65910, TPS65910_INT_MSK3, 1, &reg);
+                }
+        }
+        mutex_unlock(&tps65910->irq_lock);
+}
+
+static void tps65910_irq_enable(struct irq_data *data)
+{
+        struct tps65910 *tps65910 = irq_data_get_irq_chip_data(data);
+
+        tps65910->irq_mask &= ~( 1 << irq_to_tps65910_irq(tps65910, data->irq));
+}
+
+static void tps65910_irq_disable(struct irq_data *data)
+{
+        struct tps65910 *tps65910 = irq_data_get_irq_chip_data(data);
+
+        tps65910->irq_mask |= ( 1 << irq_to_tps65910_irq(tps65910, data->irq));
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int tps65910_irq_set_wake(struct irq_data *data, unsigned int enable)
+{
+        struct tps65910 *tps65910 = irq_data_get_irq_chip_data(data);
+        return irq_set_irq_wake(tps65910->chip_irq, enable);
+}
+#else
+#define tps65910_irq_set_wake NULL
+#endif
+
+static struct irq_chip tps65910_irq_chip = {
+        .name = "tps65910",
+        .irq_bus_lock = tps65910_irq_lock,
+        .irq_bus_sync_unlock = tps65910_irq_sync_unlock,
+        .irq_disable = tps65910_irq_disable,
+        .irq_enable = tps65910_irq_enable,
+        .irq_set_wake = tps65910_irq_set_wake,
+};
+
+int tps65910_irq_init(struct tps65910 *tps65910, int irq,
+                    struct tps65910_platform_data *pdata)
+{
+        int ret, cur_irq;
+        int flags = IRQF_ONESHOT;
+
+        if (!irq) {
+                dev_warn(tps65910->dev, "No interrupt support, no core IRQ\n");
+                return -EINVAL;
+        }
+
+        if (!pdata || !pdata->irq_base) {
+                dev_warn(tps65910->dev, "No interrupt support, no IRQ base\n");
+                return -EINVAL;
+        }
+
+        tps65910->irq_mask = 0xFFFFFF;
+
+        mutex_init(&tps65910->irq_lock);
+        tps65910->chip_irq = irq;
+        tps65910->irq_base = pdata->irq_base;
+
+        switch (tps65910_chip_id(tps65910)) {
+        case TPS65910:
+                tps65910->irq_num = TPS65910_NUM_IRQ;
+                break;
+        case TPS65911:
+                tps65910->irq_num = TPS65911_NUM_IRQ;
+                break;
+        }
+
+        /* Register with genirq */
+        for (cur_irq = tps65910->irq_base;
+             cur_irq < tps65910->irq_num + tps65910->irq_base;
+             cur_irq++) {
+                irq_set_chip_data(cur_irq, tps65910);
+                irq_set_chip_and_handler(cur_irq, &tps65910_irq_chip,
+                                         handle_edge_irq);
+                irq_set_nested_thread(cur_irq, 1);
+
+                /* ARM needs us to explicitly flag the IRQ as valid
+                 * and will set them noprobe when we do so. */
+#ifdef CONFIG_ARM
+                set_irq_flags(cur_irq, IRQF_VALID);
+#else
+                irq_set_noprobe(cur_irq);
+#endif
+        }
+
+        ret = request_threaded_irq(irq, NULL, tps65910_irq, flags,
+                                   "tps65910", tps65910);
+
+        irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
+
+        if (ret != 0)
+                dev_err(tps65910->dev, "Failed to request IRQ: %d\n", ret);
+
+        return ret;
+}
+
+int tps65910_irq_exit(struct tps65910 *tps65910)
+{
+        if (tps65910->chip_irq)
+                free_irq(tps65910->chip_irq, tps65910);
+        return 0;
+}
diff --git a/drivers/mfd/tps6591x.c b/drivers/mfd/tps6591x.c
new file mode 100644
index 00000000000..bd60e09c316
--- /dev/null
+++ b/drivers/mfd/tps6591x.c
@@ -0,0 +1,930 @@
+/*
+ * driver/mfd/tps6591x.c
+ *
+ * Core driver for TI TPS6591x PMIC family
+ *
+ * Copyright (C) 2011 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+
+#include <linux/mfd/core.h>
+#include <linux/mfd/tps6591x.h>
+
+/* device control registers */
+#define TPS6591X_DEVCTRL        0x3F
+#define DEVCTRL_PWR_OFF_SEQ     (1 << 7)
+#define DEVCTRL_DEV_ON          (1 << 2)
+#define DEVCTRL_DEV_SLP         (1 << 1)
+#define TPS6591X_DEVCTRL2       0x40
+
+/* device sleep on registers */
+#define TPS6591X_SLEEP_KEEP_ON  0x42
+#define SLEEP_KEEP_ON_THERM     (1 << 7)
+#define SLEEP_KEEP_ON_CLKOUT32K (1 << 6)
+#define SLEEP_KEEP_ON_VRTC      (1 << 5)
+#define SLEEP_KEEP_ON_I2CHS     (1 << 4)
+
+/* interrupt status registers */
+#define TPS6591X_INT_STS        0x50
+#define TPS6591X_INT_STS2       0x52
+#define TPS6591X_INT_STS3       0x54
+
+/* interrupt mask registers */
+#define TPS6591X_INT_MSK        0x51
+#define TPS6591X_INT_MSK2       0x53
+#define TPS6591X_INT_MSK3       0x55
+
+/* GPIO register base address */
+#define TPS6591X_GPIO_BASE_ADDR 0x60
+
+/* silicon version number */
+#define TPS6591X_VERNUM         0x80
+
+#define TPS6591X_GPIO_SLEEP     7
+#define TPS6591X_GPIO_PDEN      3
+#define TPS6591X_GPIO_DIR       2
+
+enum irq_type {
+        EVENT,
+        GPIO,
+};
+
+struct tps6591x_irq_data {
+        u8              mask_reg;
+        u8              mask_pos;
+        enum irq_type   type;
+};
+
+#define TPS6591X_IRQ(_reg, _mask_pos, _type)    \
+        {                                       \
+                .mask_reg       = (_reg),       \
+                .mask_pos       = (_mask_pos),  \
+                .type           = (_type),      \
+        }
+
+static const struct tps6591x_irq_data tps6591x_irqs[] = {
+        [TPS6591X_INT_PWRHOLD_F]        = TPS6591X_IRQ(0, 0, EVENT),
+        [TPS6591X_INT_VMBHI]            = TPS6591X_IRQ(0, 1, EVENT),
+        [TPS6591X_INT_PWRON]            = TPS6591X_IRQ(0, 2, EVENT),
+        [TPS6591X_INT_PWRON_LP]         = TPS6591X_IRQ(0, 3, EVENT),
+        [TPS6591X_INT_PWRHOLD_R]        = TPS6591X_IRQ(0, 4, EVENT),
+        [TPS6591X_INT_HOTDIE]           = TPS6591X_IRQ(0, 5, EVENT),
+        [TPS6591X_INT_RTC_ALARM]        = TPS6591X_IRQ(0, 6, EVENT),
+        [TPS6591X_INT_RTC_PERIOD]       = TPS6591X_IRQ(0, 7, EVENT),
+        [TPS6591X_INT_GPIO0]            = TPS6591X_IRQ(1, 0, GPIO),
+        [TPS6591X_INT_GPIO1]            = TPS6591X_IRQ(1, 2, GPIO),
+        [TPS6591X_INT_GPIO2]            = TPS6591X_IRQ(1, 4, GPIO),
+        [TPS6591X_INT_GPIO3]            = TPS6591X_IRQ(1, 6, GPIO),
+        [TPS6591X_INT_GPIO4]            = TPS6591X_IRQ(2, 0, GPIO),
+        [TPS6591X_INT_GPIO5]            = TPS6591X_IRQ(2, 2, GPIO),
+        [TPS6591X_INT_WTCHDG]           = TPS6591X_IRQ(2, 4, EVENT),
+        [TPS6591X_INT_VMBCH2_H]         = TPS6591X_IRQ(2, 5, EVENT),
+        [TPS6591X_INT_VMBCH2_L]         = TPS6591X_IRQ(2, 6, EVENT),
+        [TPS6591X_INT_PWRDN]            = TPS6591X_IRQ(2, 7, EVENT),
+};
+
+struct tps6591x {
+        struct mutex            lock;
+        struct device           *dev;
+        struct i2c_client       *client;
+
+        struct gpio_chip        gpio;
+        struct irq_chip         irq_chip;
+        struct mutex            irq_lock;
+        int                     irq_base;
+        int                     irq_main;
+        u32                     irq_en;
+        u8                      mask_cache[3];
+        u8                      mask_reg[3];
+};
+
+static inline int __tps6591x_read(struct i2c_client *client,
+                                  int reg, uint8_t *val)
+{
+        int ret;
+
+        ret = i2c_smbus_read_byte_data(client, reg);
+        if (ret < 0) {
+                dev_err(&client->dev, "failed reading at 0x%02x\n", reg);
+                return ret;
+        }
+
+        *val = (uint8_t)ret;
+
+        return 0;
+}
+
+static inline int __tps6591x_reads(struct i2c_client *client, int reg,
+                                int len, uint8_t *val)
+{
+        int ret;
+
+        ret = i2c_smbus_read_i2c_block_data(client, reg, len, val);
+        if (ret < 0) {
+                dev_err(&client->dev, "failed reading from 0x%02x\n", reg);
+                return ret;
+        }
+
+        return 0;
+}
+
+static inline int __tps6591x_write(struct i2c_client *client,
+                                 int reg, uint8_t val)
+{
+        int ret;
+        ret = i2c_smbus_write_byte_data(client, reg, val);
+        if (ret < 0) {
+                dev_err(&client->dev, "failed writing 0x%02x to 0x%02x\n",
+                                val, reg);
+                return ret;
+        }
+
+        return 0;
+}
+
+static inline int __tps6591x_writes(struct i2c_client *client, int reg,
+                                  int len, uint8_t *val)
+{
+        int ret;
+
+        ret = i2c_smbus_write_i2c_block_data(client, reg, len, val);
+        if (ret < 0) {
+                dev_err(&client->dev, "failed writings to 0x%02x\n", reg);
+                return ret;
+        }
+
+        return 0;
+}
+
+int tps6591x_write(struct device *dev, int reg, uint8_t val)
+{
+        struct tps6591x *tps6591x = dev_get_drvdata(dev);
+        int ret = 0;
+
+        mutex_lock(&tps6591x->lock);
+        ret = __tps6591x_write(to_i2c_client(dev), reg, val);
+        mutex_unlock(&tps6591x->lock);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(tps6591x_write);
+
+int tps6591x_writes(struct device *dev, int reg, int len, uint8_t *val)
+{
+        struct tps6591x *tps6591x = dev_get_drvdata(dev);
+        int ret = 0;
+
+        mutex_lock(&tps6591x->lock);
+        ret = __tps6591x_writes(to_i2c_client(dev), reg, len, val);
+        mutex_unlock(&tps6591x->lock);
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(tps6591x_writes);
+
+int tps6591x_read(struct device *dev, int reg, uint8_t *val)
+{
+        return __tps6591x_read(to_i2c_client(dev), reg, val);
+}
+EXPORT_SYMBOL_GPL(tps6591x_read);
+
+int tps6591x_reads(struct device *dev, int reg, int len, uint8_t *val)
+{
+        return __tps6591x_reads(to_i2c_client(dev), reg, len, val);
+}
+EXPORT_SYMBOL_GPL(tps6591x_reads);
+
+int tps6591x_set_bits(struct device *dev, int reg, uint8_t bit_mask)
+{
+        struct tps6591x *tps6591x = dev_get_drvdata(dev);
+        uint8_t reg_val;
+        int ret = 0;
+
+        mutex_lock(&tps6591x->lock);
+
+        ret = __tps6591x_read(to_i2c_client(dev), reg, &reg_val);
+        if (ret)
+                goto out;
+
+        if ((reg_val & bit_mask) != bit_mask) {
+                reg_val |= bit_mask;
+                ret = __tps6591x_write(to_i2c_client(dev), reg, reg_val);
+        }
+out:
+        mutex_unlock(&tps6591x->lock);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(tps6591x_set_bits);
+
+int tps6591x_clr_bits(struct device *dev, int reg, uint8_t bit_mask)
+{
+        struct tps6591x *tps6591x = dev_get_drvdata(dev);
+        uint8_t reg_val;
+        int ret = 0;
+
+        mutex_lock(&tps6591x->lock);
+
+        ret = __tps6591x_read(to_i2c_client(dev), reg, &reg_val);
+        if (ret)
+                goto out;
+
+        if (reg_val & bit_mask) {
+                reg_val &= ~bit_mask;
+                ret = __tps6591x_write(to_i2c_client(dev), reg, reg_val);
+        }
+out:
+        mutex_unlock(&tps6591x->lock);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(tps6591x_clr_bits);
+
+int tps6591x_update(struct device *dev, int reg, uint8_t val, uint8_t mask)
+{
+        struct tps6591x *tps6591x = dev_get_drvdata(dev);
+        uint8_t reg_val;
+        int ret = 0;
+
+        mutex_lock(&tps6591x->lock);
+
+        ret = __tps6591x_read(tps6591x->client, reg, &reg_val);
+        if (ret)
+                goto out;
+
+        if ((reg_val & mask) != val) {
+                reg_val = (reg_val & ~mask) | (val & mask);
+                ret = __tps6591x_write(tps6591x->client, reg, reg_val);
+        }
+out:
+        mutex_unlock(&tps6591x->lock);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(tps6591x_update);
+
+static struct i2c_client *tps6591x_i2c_client;
+static void tps6591x_power_off(void)
+{
+        struct device *dev = NULL;
+
+        if (!tps6591x_i2c_client)
+                return;
+
+        dev = &tps6591x_i2c_client->dev;
+
+        if (tps6591x_set_bits(dev, TPS6591X_DEVCTRL, DEVCTRL_PWR_OFF_SEQ) < 0)
+                return;
+
+        tps6591x_clr_bits(dev, TPS6591X_DEVCTRL, DEVCTRL_DEV_ON);
+}
+
+static int tps6591x_gpio_get(struct gpio_chip *gc, unsigned offset)
+{
+        struct tps6591x *tps6591x = container_of(gc, struct tps6591x, gpio);
+        uint8_t val;
+        int ret;
+
+        ret = __tps6591x_read(tps6591x->client, TPS6591X_GPIO_BASE_ADDR +
+                        offset, &val);
+        if (ret)
+                return ret;
+
+        if (val & 0x4)
+                return val & 0x1;
+        else
+                return (val & 0x2) ? 1 : 0;
+}
+
+static void tps6591x_gpio_set(struct gpio_chip *chip, unsigned offset,
+                        int value)
+{
+
+        struct tps6591x *tps6591x = container_of(chip, struct tps6591x, gpio);
+
+        tps6591x_update(tps6591x->dev, TPS6591X_GPIO_BASE_ADDR + offset,
+                        value, 0x1);
+}
+
+static int tps6591x_gpio_input(struct gpio_chip *gc, unsigned offset)
+{
+        struct tps6591x *tps6591x = container_of(gc, struct tps6591x, gpio);
+        uint8_t reg_val;
+        int ret;
+
+        ret = __tps6591x_read(tps6591x->client, TPS6591X_GPIO_BASE_ADDR +
+                        offset, &reg_val);
+        if (ret)
+                return ret;
+
+        reg_val &= ~0x4;
+        return __tps6591x_write(tps6591x->client, TPS6591X_GPIO_BASE_ADDR +
+                        offset, reg_val);
+}
+
+static int tps6591x_gpio_output(struct gpio_chip *gc, unsigned offset,
+                                int value)
+{
+        struct tps6591x *tps6591x = container_of(gc, struct tps6591x, gpio);
+        uint8_t reg_val, val;
+        int ret;
+
+        ret = __tps6591x_read(tps6591x->client, TPS6591X_GPIO_BASE_ADDR +
+                        offset, &reg_val);
+        if (ret)
+                return ret;
+
+        reg_val &= ~0x1;
+        val = (value & 0x1) | 0x4;
+        reg_val = reg_val | val;
+        return __tps6591x_write(tps6591x->client, TPS6591X_GPIO_BASE_ADDR +
+                        offset, reg_val);
+}
+
+static int tps6591x_gpio_to_irq(struct gpio_chip *gc, unsigned off)
+{
+        struct tps6591x *tps6591x;
+        tps6591x = container_of(gc, struct tps6591x, gpio);
+
+        if ((off >= 0) && (off <= TPS6591X_INT_GPIO5 - TPS6591X_INT_GPIO0))
+                return tps6591x->irq_base + TPS6591X_INT_GPIO0 + off;
+
+        return -EIO;
+}
+
+static void tps6591x_gpio_init(struct tps6591x *tps6591x,
+                        struct tps6591x_platform_data *pdata)
+{
+        int ret;
+        int gpio_base = pdata->gpio_base;
+        int i;
+        u8 gpio_reg;
+        struct tps6591x_gpio_init_data *ginit;
+
+        if (gpio_base <= 0)
+                return;
+
+        for (i = 0; i < pdata->num_gpioinit_data; ++i) {
+                ginit = &pdata->gpio_init_data[i];
+                if (!ginit->init_apply)
+                        continue;
+                gpio_reg = (ginit->sleep_en << TPS6591X_GPIO_SLEEP) |
+                                (ginit->pulldn_en << TPS6591X_GPIO_PDEN) |
+                                (ginit->output_mode_en << TPS6591X_GPIO_DIR);
+
+                if (ginit->output_mode_en)
+                        gpio_reg |= ginit->output_val;
+
+                ret =  __tps6591x_write(tps6591x->client,
+                                TPS6591X_GPIO_BASE_ADDR + i, gpio_reg);
+                if (ret < 0)
+                        dev_err(&tps6591x->client->dev, "Gpio %d init "
+                                "configuration failed: %d\n", i, ret);
+        }
+
+        tps6591x->gpio.owner            = THIS_MODULE;
+        tps6591x->gpio.label            = tps6591x->client->name;
+        tps6591x->gpio.dev              = tps6591x->dev;
+        tps6591x->gpio.base             = gpio_base;
+        tps6591x->gpio.ngpio            = TPS6591X_GPIO_NR;
+        tps6591x->gpio.can_sleep        = 1;
+
+        tps6591x->gpio.direction_input  = tps6591x_gpio_input;
+        tps6591x->gpio.direction_output = tps6591x_gpio_output;
+        tps6591x->gpio.set              = tps6591x_gpio_set;
+        tps6591x->gpio.get              = tps6591x_gpio_get;
+        tps6591x->gpio.to_irq           = tps6591x_gpio_to_irq;
+
+        ret = gpiochip_add(&tps6591x->gpio);
+        if (ret)
+                dev_warn(tps6591x->dev, "GPIO registration failed: %d\n", ret);
+}
+
+static int __remove_subdev(struct device *dev, void *unused)
+{
+        platform_device_unregister(to_platform_device(dev));
+        return 0;
+}
+
+static int tps6591x_remove_subdevs(struct tps6591x *tps6591x)
+{
+        return device_for_each_child(tps6591x->dev, NULL, __remove_subdev);
+}
+
+static void tps6591x_irq_lock(struct irq_data *data)
+{
+        struct tps6591x *tps6591x = irq_data_get_irq_chip_data(data);
+
+        mutex_lock(&tps6591x->irq_lock);
+}
+
+static void tps6591x_irq_mask(struct irq_data *irq_data)
+{
+        struct tps6591x *tps6591x = irq_data_get_irq_chip_data(irq_data);
+        unsigned int __irq = irq_data->irq - tps6591x->irq_base;
+        const struct tps6591x_irq_data *data = &tps6591x_irqs[__irq];
+
+        if (data->type == EVENT)
+                tps6591x->mask_reg[data->mask_reg] |= (1 << data->mask_pos);
+        else
+                tps6591x->mask_reg[data->mask_reg] |= (3 << data->mask_pos);
+
+        tps6591x->irq_en &= ~(1 << __irq);
+}
+
+static void tps6591x_irq_unmask(struct irq_data *irq_data)
+{
+        struct tps6591x *tps6591x = irq_data_get_irq_chip_data(irq_data);
+
+        unsigned int __irq = irq_data->irq - tps6591x->irq_base;
+        const struct tps6591x_irq_data *data = &tps6591x_irqs[__irq];
+
+        if (data->type == EVENT) {
+                tps6591x->mask_reg[data->mask_reg] &= ~(1 << data->mask_pos);
+                tps6591x->irq_en |= (1 << __irq);
+        }
+}
+
+static void tps6591x_irq_sync_unlock(struct irq_data *data)
+{
+        struct tps6591x *tps6591x = irq_data_get_irq_chip_data(data);
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(tps6591x->mask_reg); i++) {
+                if (tps6591x->mask_reg[i] != tps6591x->mask_cache[i]) {
+                        if (!WARN_ON(tps6591x_write(tps6591x->dev,
+                                                TPS6591X_INT_MSK + 2*i,
+                                                tps6591x->mask_reg[i])))
+                                tps6591x->mask_cache[i] = tps6591x->mask_reg[i];
+                }
+        }
+
+        mutex_unlock(&tps6591x->irq_lock);
+}
+
+static int tps6591x_irq_set_type(struct irq_data *irq_data, unsigned int type)
+{
+        struct tps6591x *tps6591x = irq_data_get_irq_chip_data(irq_data);
+
+        unsigned int __irq = irq_data->irq - tps6591x->irq_base;
+        const struct tps6591x_irq_data *data = &tps6591x_irqs[__irq];
+
+        if (data->type == GPIO) {
+                if (type & IRQ_TYPE_EDGE_FALLING)
+                        tps6591x->mask_reg[data->mask_reg]
+                                &= ~(1 << data->mask_pos);
+                else
+                        tps6591x->mask_reg[data->mask_reg]
+                                |= (1 << data->mask_pos);
+
+                if (type & IRQ_TYPE_EDGE_RISING)
+                        tps6591x->mask_reg[data->mask_reg]
+                                &= ~(2 << data->mask_pos);
+                else
+                        tps6591x->mask_reg[data->mask_reg]
+                                |= (2 << data->mask_pos);
+
+                tps6591x->irq_en |= (1 << __irq);
+        }
+
+        return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int tps6591x_irq_set_wake(struct irq_data *irq_data, unsigned int on)
+{
+        struct tps6591x *tps6591x = irq_data_get_irq_chip_data(irq_data);
+        return irq_set_irq_wake(tps6591x->irq_main, on);
+}
+#else
+#define tps6591x_irq_set_wake NULL
+#endif
+
+
+static irqreturn_t tps6591x_irq(int irq, void *data)
+{
+        struct tps6591x *tps6591x = data;
+        int ret = 0;
+        u8 tmp[3];
+        u8 int_ack;
+        u32 acks, mask = 0;
+        int i;
+
+        for (i = 0; i < 3; i++) {
+                ret = tps6591x_read(tps6591x->dev, TPS6591X_INT_STS + 2*i,
+                                &tmp[i]);
+                if (ret < 0) {
+                        dev_err(tps6591x->dev,
+                                "failed to read interrupt status\n");
+                        return IRQ_NONE;
+                }
+                if (tmp[i]) {
+                        /* Ack only those interrupts which are enabled */
+                        int_ack = tmp[i] & (~(tps6591x->mask_cache[i]));
+                        ret = tps6591x_write(tps6591x->dev,
+                                        TPS6591X_INT_STS + 2*i, int_ack);
+                        if (ret < 0) {
+                                dev_err(tps6591x->dev,
+                                        "failed to write interrupt status\n");
+                                return IRQ_NONE;
+                        }
+                }
+        }
+
+        acks = (tmp[2] << 16) | (tmp[1] << 8) | tmp[0];
+
+        for (i = 0; i < ARRAY_SIZE(tps6591x_irqs); i++) {
+                if (tps6591x_irqs[i].type == GPIO)
+                        mask = (3 << (tps6591x_irqs[i].mask_pos
+                                        + tps6591x_irqs[i].mask_reg*8));
+                else if (tps6591x_irqs[i].type == EVENT)
+                        mask = (1 << (tps6591x_irqs[i].mask_pos
+                                        + tps6591x_irqs[i].mask_reg*8));
+
+                if ((acks & mask) && (tps6591x->irq_en & (1 << i)))
+                        handle_nested_irq(tps6591x->irq_base + i);
+        }
+        return IRQ_HANDLED;
+}
+
+static int __devinit tps6591x_irq_init(struct tps6591x *tps6591x, int irq,
+                                int irq_base)
+{
+        int i, ret;
+
+        if (!irq_base) {
+                dev_warn(tps6591x->dev, "No interrupt support on IRQ base\n");
+                return -EINVAL;
+        }
+
+        mutex_init(&tps6591x->irq_lock);
+
+        tps6591x->mask_reg[0] = 0xFF;
+        tps6591x->mask_reg[1] = 0xFF;
+        tps6591x->mask_reg[2] = 0xFF;
+        for (i = 0; i < 3; i++) {
+                tps6591x->mask_cache[i] = tps6591x->mask_reg[i];
+                tps6591x_write(tps6591x->dev, TPS6591X_INT_MSK + 2*i,
+                                 tps6591x->mask_cache[i]);
+        }
+
+        for (i = 0; i < 3; i++)
+                tps6591x_write(tps6591x->dev, TPS6591X_INT_STS + 2*i, 0xff);
+
+        tps6591x->irq_base = irq_base;
+        tps6591x->irq_main = irq;
+
+        tps6591x->irq_chip.name = "tps6591x";
+        tps6591x->irq_chip.irq_mask = tps6591x_irq_mask;
+        tps6591x->irq_chip.irq_unmask = tps6591x_irq_unmask;
+        tps6591x->irq_chip.irq_bus_lock = tps6591x_irq_lock;
+        tps6591x->irq_chip.irq_bus_sync_unlock = tps6591x_irq_sync_unlock;
+        tps6591x->irq_chip.irq_set_type = tps6591x_irq_set_type;
+        tps6591x->irq_chip.irq_set_wake = tps6591x_irq_set_wake;
+
+        for (i = 0; i < ARRAY_SIZE(tps6591x_irqs); i++) {
+                int __irq = i + tps6591x->irq_base;
+                irq_set_chip_data(__irq, tps6591x);
+                irq_set_chip_and_handler(__irq, &tps6591x->irq_chip,
+                                         handle_simple_irq);
+                irq_set_nested_thread(__irq, 1);
+#ifdef CONFIG_ARM
+                set_irq_flags(__irq, IRQF_VALID);
+#endif
+        }
+
+        ret = request_threaded_irq(irq, NULL, tps6591x_irq, IRQF_ONESHOT,
+                                "tps6591x", tps6591x);
+        if (!ret) {
+                device_init_wakeup(tps6591x->dev, 1);
+                enable_irq_wake(irq);
+        }
+
+        return ret;
+}
+
+static int __devinit tps6591x_add_subdevs(struct tps6591x *tps6591x,
+                                          struct tps6591x_platform_data *pdata)
+{
+        struct tps6591x_subdev_info *subdev;
+        struct platform_device *pdev;
+        int i, ret = 0;
+
+        for (i = 0; i < pdata->num_subdevs; i++) {
+                subdev = &pdata->subdevs[i];
+
+                pdev = platform_device_alloc(subdev->name, subdev->id);
+
+                pdev->dev.parent = tps6591x->dev;
+                pdev->dev.platform_data = subdev->platform_data;
+
+                ret = platform_device_add(pdev);
+                if (ret)
+                        goto failed;
+        }
+        return 0;
+
+failed:
+        tps6591x_remove_subdevs(tps6591x);
+        return ret;
+}
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+static void print_regs(const char *header, struct seq_file *s,
+                struct i2c_client *client, int start_offset,
+                int end_offset)
+{
+        uint8_t reg_val;
+        int i;
+        int ret;
+
+        seq_printf(s, "%s\n", header);
+        for (i = start_offset; i <= end_offset; ++i) {
+                ret = __tps6591x_read(client, i, &reg_val);
+                if (ret >= 0)
+                        seq_printf(s, "Reg 0x%02x Value 0x%02x\n", i, reg_val);
+        }
+        seq_printf(s, "------------------\n");
+}
+
+static int dbg_tps_show(struct seq_file *s, void *unused)
+{
+        struct tps6591x *tps = s->private;
+        struct i2c_client *client = tps->client;
+
+        seq_printf(s, "TPS6591x Registers\n");
+        seq_printf(s, "------------------\n");
+
+        print_regs("Timing Regs",    s, client, 0x0, 0x6);
+        print_regs("Alarm Regs",     s, client, 0x8, 0xD);
+        print_regs("RTC Regs",       s, client, 0x10, 0x16);
+        print_regs("BCK Regs",       s, client, 0x17, 0x1B);
+        print_regs("PUADEN Regs",    s, client, 0x18, 0x18);
+        print_regs("REF Regs",       s, client, 0x1D, 0x1D);
+        print_regs("VDD Regs",       s, client, 0x1E, 0x29);
+        print_regs("LDO Regs",       s, client, 0x30, 0x37);
+        print_regs("THERM Regs",     s, client, 0x38, 0x38);
+        print_regs("BBCH Regs",      s, client, 0x39, 0x39);
+        print_regs("DCDCCNTRL Regs", s, client, 0x3E, 0x3E);
+        print_regs("DEV_CNTRL Regs", s, client, 0x3F, 0x40);
+        print_regs("SLEEP Regs",     s, client, 0x41, 0x44);
+        print_regs("EN1 Regs",       s, client, 0x45, 0x48);
+        print_regs("INT Regs",       s, client, 0x50, 0x55);
+        print_regs("GPIO Regs",      s, client, 0x60, 0x68);
+        print_regs("WATCHDOG Regs",  s, client, 0x69, 0x69);
+        print_regs("VMBCH Regs",     s, client, 0x6A, 0x6B);
+        print_regs("LED_CTRL Regs",  s, client, 0x6c, 0x6D);
+        print_regs("PWM_CTRL Regs",  s, client, 0x6E, 0x6F);
+        print_regs("SPARE Regs",     s, client, 0x70, 0x70);
+        print_regs("VERNUM Regs",    s, client, 0x80, 0x80);
+        return 0;
+}
+
+static int dbg_tps_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, dbg_tps_show, inode->i_private);
+}
+
+static const struct file_operations debug_fops = {
+        .open           = dbg_tps_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static void __init tps6591x_debuginit(struct tps6591x *tps)
+{
+        (void)debugfs_create_file("tps6591x", S_IRUGO, NULL,
+                        tps, &debug_fops);
+}
+#else
+static void __init tps6591x_debuginit(struct tps6591x *tpsi)
+{
+        return;
+}
+#endif
+
+static int __init tps6591x_sleepinit(struct tps6591x *tpsi,
+                                        struct tps6591x_platform_data *pdata)
+{
+        struct device *dev = NULL;
+        int ret = 0;
+
+        dev = tpsi->dev;
+
+        if (!pdata->dev_slp_en)
+                goto no_err_return;
+
+        /* pmu dev_slp_en is set. Make sure slp_keepon is available before
+         * allowing SLEEP device state */
+        if (!pdata->slp_keepon) {
+                dev_err(dev, "slp_keepon_data required for slp_en\n");
+                goto err_sleep_init;
+        }
+
+        /* enabling SLEEP device state */
+        ret = tps6591x_set_bits(dev, TPS6591X_DEVCTRL, DEVCTRL_DEV_SLP);
+        if (ret < 0) {
+                dev_err(dev, "set dev_slp failed: %d\n", ret);
+                goto err_sleep_init;
+        }
+
+        if (pdata->slp_keepon->therm_keepon) {
+                ret = tps6591x_set_bits(dev, TPS6591X_SLEEP_KEEP_ON,
+                                                SLEEP_KEEP_ON_THERM);
+                if (ret < 0) {
+                        dev_err(dev, "set therm_keepon failed: %d\n", ret);
+                        goto disable_dev_slp;
+                }
+        }
+
+        if (pdata->slp_keepon->clkout32k_keepon) {
+                ret = tps6591x_set_bits(dev, TPS6591X_SLEEP_KEEP_ON,
+                                                SLEEP_KEEP_ON_CLKOUT32K);
+                if (ret < 0) {
+                        dev_err(dev, "set clkout32k_keepon failed: %d\n", ret);
+                        goto disable_dev_slp;
+                }
+        }
+
+
+        if (pdata->slp_keepon->vrtc_keepon) {
+                ret = tps6591x_set_bits(dev, TPS6591X_SLEEP_KEEP_ON,
+                                                SLEEP_KEEP_ON_VRTC);
+                if (ret < 0) {
+                        dev_err(dev, "set vrtc_keepon failed: %d\n", ret);
+                        goto disable_dev_slp;
+                }
+        }
+
+        if (pdata->slp_keepon->i2chs_keepon) {
+                ret = tps6591x_set_bits(dev, TPS6591X_SLEEP_KEEP_ON,
+                                                SLEEP_KEEP_ON_I2CHS);
+                if (ret < 0) {
+                        dev_err(dev, "set i2chs_keepon failed: %d\n", ret);
+                        goto disable_dev_slp;
+                }
+        }
+
+no_err_return:
+        return 0;
+
+disable_dev_slp:
+        tps6591x_clr_bits(dev, TPS6591X_DEVCTRL, DEVCTRL_DEV_SLP);
+
+err_sleep_init:
+        return ret;
+}
+
+static int __devinit tps6591x_i2c_probe(struct i2c_client *client,
+                                        const struct i2c_device_id *id)
+{
+        struct tps6591x_platform_data *pdata = client->dev.platform_data;
+        struct tps6591x *tps6591x;
+        int ret;
+
+        if (!pdata) {
+                dev_err(&client->dev, "tps6591x requires platform data\n");
+                return -ENOTSUPP;
+        }
+
+        ret = i2c_smbus_read_byte_data(client, TPS6591X_VERNUM);
+        if (ret < 0) {
+                dev_err(&client->dev, "Silicon version number read"
+                                " failed: %d\n", ret);
+                return -EIO;
+        }
+
+        dev_info(&client->dev, "VERNUM is %02x\n", ret);
+
+        tps6591x = kzalloc(sizeof(struct tps6591x), GFP_KERNEL);
+        if (tps6591x == NULL)
+                return -ENOMEM;
+
+        tps6591x->client = client;
+        tps6591x->dev = &client->dev;
+        i2c_set_clientdata(client, tps6591x);
+
+        mutex_init(&tps6591x->lock);
+
+        if (client->irq) {
+                ret = tps6591x_irq_init(tps6591x, client->irq,
+                                        pdata->irq_base);
+                if (ret) {
+                        dev_err(&client->dev, "IRQ init failed: %d\n", ret);
+                        goto err_irq_init;
+                }
+        }
+
+        ret = tps6591x_add_subdevs(tps6591x, pdata);
+        if (ret) {
+                dev_err(&client->dev, "add devices failed: %d\n", ret);
+                goto err_add_devs;
+        }
+
+        tps6591x_gpio_init(tps6591x, pdata);
+
+        tps6591x_debuginit(tps6591x);
+
+        tps6591x_sleepinit(tps6591x, pdata);
+
+        if (pdata->use_power_off && !pm_power_off)
+                pm_power_off = tps6591x_power_off;
+
+        tps6591x_i2c_client = client;
+
+        return 0;
+
+err_add_devs:
+        if (client->irq)
+                free_irq(client->irq, tps6591x);
+err_irq_init:
+        kfree(tps6591x);
+        return ret;
+}
+
+static int __devexit tps6591x_i2c_remove(struct i2c_client *client)
+{
+        struct tps6591x *tps6591x = i2c_get_clientdata(client);
+
+        if (client->irq)
+                free_irq(client->irq, tps6591x);
+
+        if (gpiochip_remove(&tps6591x->gpio) < 0)
+                dev_err(&client->dev, "Error in removing the gpio driver\n");
+
+        kfree(tps6591x);
+        return 0;
+}
+#ifdef CONFIG_PM
+static int tps6591x_i2c_suspend(struct i2c_client *client, pm_message_t state)
+{
+        if (client->irq)
+                disable_irq(client->irq);
+        return 0;
+}
+
+static int tps6591x_i2c_resume(struct i2c_client *client)
+{
+        if (client->irq)
+                enable_irq(client->irq);
+        return 0;
+}
+#endif
+
+
+static const struct i2c_device_id tps6591x_id_table[] = {
+        { "tps6591x", 0 },
+        { },
+};
+MODULE_DEVICE_TABLE(i2c, tps6591x_id_table);
+
+static struct i2c_driver tps6591x_driver = {
+        .driver = {
+                .name   = "tps6591x",
+                .owner  = THIS_MODULE,
+        },
+        .probe          = tps6591x_i2c_probe,
+        .remove         = __devexit_p(tps6591x_i2c_remove),
+#ifdef CONFIG_PM
+        .suspend        = tps6591x_i2c_suspend,
+        .resume         = tps6591x_i2c_resume,
+#endif
+        .id_table       = tps6591x_id_table,
+};
+
+static int __init tps6591x_init(void)
+{
+        return i2c_add_driver(&tps6591x_driver);
+}
+subsys_initcall(tps6591x_init);
+
+static void __exit tps6591x_exit(void)
+{
+        i2c_del_driver(&tps6591x_driver);
+}
+module_exit(tps6591x_exit);
+
+MODULE_DESCRIPTION("TPS6591X core driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/tps8003x-gpadc.c b/drivers/mfd/tps8003x-gpadc.c
new file mode 100644
index 00000000000..5db912cc01f
--- /dev/null
+++ b/drivers/mfd/tps8003x-gpadc.c
@@ -0,0 +1,650 @@
+/*
+ * drivers/mfd/tps8003x-gpadc.c
+ *
+ * Gpadc for TI's tps80031
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/platform_device.h>
+#include <linux/miscdevice.h>
+#include <linux/slab.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/i2c/twl.h>
+#include <linux/mfd/tps80031.h>
+#include <linux/uaccess.h>
+#include <linux/spinlock.h>
+
+#define GPADC_CTRL      0x2e
+#define GPSELECT_ISB    0x35
+#define GPCH0_LSB       0x3b
+#define GPCH0_MSB       0x3c
+#define CTRL_P1         0x36
+#define TOGGLE1         0x90
+#define MISC1           0xe4
+
+#define CTRL_P1_SP1     BIT(3)
+#define TOGGLE1_GPADCR  BIT(1)
+#define GPADC_BUSY      (1 << 0)
+#define GPADC_EOC_SW    (1 << 1)
+#define SCALE           (1 << 15)
+
+#define TPS80031_GPADC_MAX_CHANNELS 17
+#define TPS80031_GPADC_IOC_MAGIC '`'
+#define TPS80031_GPADC_IOCX_ADC_RAW_READ _IO(TPS80031_GPADC_IOC_MAGIC, 0)
+
+struct tps80031_gpadc_user_parms {
+        int channel;
+        int status;
+        u16 result;
+};
+
+struct tps80031_calibration {
+        s32 gain_error;
+        s32 offset_error;
+};
+
+struct tps80031_ideal_code {
+        s16 code1;
+        s16 code2;
+};
+
+struct tps80031_scalar_channel {
+        uint8_t delta1_addr;
+        uint8_t delta1_mask;
+        uint8_t delta2_addr;
+        uint8_t delta2_mask;
+};
+
+static struct tps80031_calibration
+        tps80031_calib_tbl[TPS80031_GPADC_MAX_CHANNELS];
+static const uint32_t calibration_bit_map = 0x47FF;
+static const uint32_t scalar_bit_map = 0x4785;
+
+#define TPS80031_GPADC_TRIM1    0xCD
+#define TPS80031_GPADC_TRIM2    0xCE
+#define TPS80031_GPADC_TRIM3    0xCF
+#define TPS80031_GPADC_TRIM4    0xD0
+#define TPS80031_GPADC_TRIM5    0xD1
+#define TPS80031_GPADC_TRIM6    0xD2
+#define TPS80031_GPADC_TRIM7    0xD3
+#define TPS80031_GPADC_TRIM8    0xD4
+#define TPS80031_GPADC_TRIM9    0xD5
+#define TPS80031_GPADC_TRIM10   0xD6
+#define TPS80031_GPADC_TRIM11   0xD7
+#define TPS80031_GPADC_TRIM12   0xD8
+#define TPS80031_GPADC_TRIM13   0xD9
+#define TPS80031_GPADC_TRIM14   0xDA
+#define TPS80031_GPADC_TRIM15   0xDB
+#define TPS80031_GPADC_TRIM16   0xDC
+#define TPS80031_GPADC_TRIM19   0xFD
+
+static const struct tps80031_scalar_channel
+                tps80031_trim[TPS80031_GPADC_MAX_CHANNELS] = {
+        { TPS80031_GPADC_TRIM1, 0x7, TPS80031_GPADC_TRIM2, 0x07},
+        { 0x00, },
+        { TPS80031_GPADC_TRIM3, 0x1F, TPS80031_GPADC_TRIM4, 0x3F},
+        { 0x00, },
+        { 0x00, },
+        { 0x00, },
+        { 0x00, },
+        { TPS80031_GPADC_TRIM7, 0x1F, TPS80031_GPADC_TRIM8, 0x1F },
+        { TPS80031_GPADC_TRIM9, 0x0F, TPS80031_GPADC_TRIM10, 0x1F },
+        { TPS80031_GPADC_TRIM11, 0x0F, TPS80031_GPADC_TRIM12, 0x1F },
+        { TPS80031_GPADC_TRIM13, 0x0F, TPS80031_GPADC_TRIM14, 0x1F },
+        { 0x00, },
+        { 0x00, },
+        { 0x00, },
+        { TPS80031_GPADC_TRIM15, 0x0f, TPS80031_GPADC_TRIM16, 0x1F },
+        { 0x00, },
+        { 0x00 ,},
+};
+
+/*
+* actual scaler gain is multiplied by 8 for fixed point operation
+* 1.875 * 8 = 15
+*/
+static const uint16_t tps80031_gain[TPS80031_GPADC_MAX_CHANNELS] = {
+        1142,   /* CHANNEL 0 */
+        8,      /* CHANNEL 1 */
+        /* 1.875 */
+        15,     /* CHANNEL 2 */
+        8,      /* CHANNEL 3 */
+        8,      /* CHANNEL 4 */
+        8,      /* CHANNEL 5 */
+        8,      /* CHANNEL 6 */
+        /* 5 */
+        40,     /* CHANNEL 7 */
+        /* 6.25 */
+        50,     /* CHANNEL 8 */
+        /* 11.25 */
+        90,     /* CHANNEL 9 */
+        /* 6.875 */
+        55,     /* CHANNEL 10 */
+        /* 1.875 */
+        15,     /* CHANNEL 11 */
+        8,      /* CHANNEL 12 */
+        8,      /* CHANNEL 13 */
+        /* 6.875 */
+        55,     /* CHANNEL 14 */
+        8,      /* CHANNEL 15 */
+        8,      /* CHANNEL 16 */
+};
+
+/*
+* calibration not needed for channel 11, 12, 13, 15 and 16
+* calibration offset is same for channel 1, 3, 4, 5
+*/
+static const struct tps80031_ideal_code
+        tps80031_ideal[TPS80031_GPADC_MAX_CHANNELS] = {
+        {463,   2982},  /* CHANNEL 0 */
+        {328,   3604},  /* CHANNEL 1 */
+        {221,   3274},  /* CHANNEL 2 */
+        {328,   3604},  /* CHANNEL 3 */
+        {328,   3604},  /* CHANNEL 4 */
+        {328,   3604},  /* CHANNEL 5 */
+        {328,   3604},  /* CHANNEL 6 */
+        {1966,  3013},  /* CHANNEL 7 */
+        {328,   2754},  /* CHANNEL 8 */
+        {728,   3275},  /* CHANNEL 9 */
+        {596,   3274},  /* CHANNEL 10 */
+        {0,     0},     /* CHANNEL 11 */
+        {0,     0},     /* CHANNEL 12 */
+        {0,     0},     /* CHANNEL 13 */
+        {193,   2859},  /* CHANNEL 14 */
+        {0,     0},     /* CHANNEL 15 */
+        {0,     0},     /* CHANNEL 16 */
+};
+
+struct tps80031_gpadc_data {
+        struct device           *dev;
+        struct mutex            lock;
+};
+
+static struct tps80031_gpadc_data *the_gpadc;
+
+static ssize_t show_gain(struct device *dev,
+                struct device_attribute *devattr, char *buf)
+{
+        struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+        int value;
+        int status;
+
+        value = tps80031_calib_tbl[attr->index].gain_error;
+        status = sprintf(buf, "%d\n", value);
+        return status;
+}
+
+static ssize_t set_gain(struct device *dev,
+        struct device_attribute *devattr, const char *buf, size_t count)
+{
+        long val;
+        int status = count;
+
+        struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+        if ((strict_strtol(buf, 10, &val) < 0) || (val < 15000)
+                                     || (val > 60000))
+                return -EINVAL;
+        tps80031_calib_tbl[attr->index].gain_error = val;
+        return status;
+}
+
+static ssize_t show_offset(struct device *dev,
+                struct device_attribute *devattr, char *buf)
+{
+        struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+        int value;
+        int status;
+
+        value = tps80031_calib_tbl[attr->index].offset_error;
+        status = sprintf(buf, "%d\n", value);
+        return status;
+}
+
+static ssize_t set_offset(struct device *dev,
+        struct device_attribute *devattr, const char *buf, size_t count)
+{
+        long val;
+        int status = count;
+
+        struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
+        if ((strict_strtol(buf, 10, &val) < 0) || (val < 15000)
+                                                        || (val > 60000))
+                return -EINVAL;
+        tps80031_calib_tbl[attr->index].offset_error = val;
+        return status;
+}
+
+static int tps80031_reg_read(struct tps80031_gpadc_data *gpadc, int sid,
+                                int reg, uint8_t *val)
+{
+        int ret;
+
+        ret = tps80031_read(gpadc->dev->parent, sid, reg, val);
+        if (ret < 0)
+                dev_err(gpadc->dev, "Failed read register 0x%02x\n", reg);
+        return ret;
+}
+
+static int tps80031_reg_write(struct tps80031_gpadc_data *gpadc, int sid,
+                                int reg, uint8_t val)
+{
+        int ret;
+
+        ret = tps80031_write(gpadc->dev->parent, sid, reg, val);
+        if (ret < 0)
+                dev_err(gpadc->dev, "Failed write register 0x%02x\n", reg);
+        return ret;
+}
+
+static int tps80031_gpadc_channel_raw_read(struct tps80031_gpadc_data *gpadc)
+{
+        uint8_t msb, lsb;
+        int ret;
+        ret = tps80031_reg_read(gpadc, SLAVE_ID2, GPCH0_LSB, &lsb);
+        if (ret < 0)
+                return ret;
+        ret = tps80031_reg_read(gpadc, SLAVE_ID2, GPCH0_MSB, &msb);
+        if (ret < 0)
+                return ret;
+
+        return (int)((msb << 8) | lsb);
+}
+
+static int tps80031_gpadc_read_channels(struct tps80031_gpadc_data *gpadc,
+                                                uint32_t channel)
+{
+        uint8_t bits;
+        int gain_error;
+        int offset_error;
+        int raw_code;
+        int corrected_code;
+        int channel_value;
+        int raw_channel_value;
+
+        /* TPS80031 has 12bit ADC */
+        bits = 12;
+        raw_code = tps80031_gpadc_channel_raw_read(gpadc);
+        if (raw_code < 0)
+                return raw_code;
+        /*
+         * Channels 0,2,7,8,9,10,14 offst and gain cannot
+         * be fully compensated by software
+         */
+        if (channel == 7)
+                return raw_code;
+        /*
+         * multiply by 1000 to convert the unit to milli
+         * division by 1024 (>> bits) for 10/12 bit ADC
+         * division by 8 (>> 3) for actual scaler gain
+         */
+        raw_channel_value =
+                (raw_code * tps80031_gain[channel] * 1000) >> (bits + 3);
+
+        gain_error = tps80031_calib_tbl[channel].gain_error;
+        offset_error = tps80031_calib_tbl[channel].offset_error;
+        corrected_code = (raw_code * SCALE - offset_error) / gain_error;
+        channel_value =
+                (corrected_code * tps80031_gain[channel] * 1000) >> (bits + 3);
+        return channel_value;
+}
+
+static int tps80031_gpadc_wait_conversion_ready(
+        struct tps80031_gpadc_data *gpadc,
+                unsigned int timeout_ms)
+{
+        int ret;
+        unsigned long timeout;
+        timeout = jiffies + msecs_to_jiffies(timeout_ms);
+        do {
+                uint8_t reg;
+                ret = tps80031_reg_read(gpadc, SLAVE_ID2, CTRL_P1, &reg);
+                if (ret < 0)
+                        return ret;
+                if (!(reg & GPADC_BUSY) &&
+                                (reg & GPADC_EOC_SW))
+                        return 0;
+        } while (!time_after(jiffies, timeout));
+        return -EAGAIN;
+}
+
+static inline int tps80031_gpadc_config
+        (struct tps80031_gpadc_data *gpadc, int channel_no)
+{
+        int ret = 0;
+
+        ret = tps80031_reg_write(gpadc, SLAVE_ID2, TOGGLE1, TOGGLE1_GPADCR);
+        if (ret < 0)
+                return ret;
+
+        ret = tps80031_reg_write(gpadc, SLAVE_ID2, GPSELECT_ISB, channel_no);
+        if (ret < 0)
+                return ret;
+
+        ret = tps80031_reg_write(gpadc, SLAVE_ID2, GPADC_CTRL, 0xef);
+        if (ret < 0)
+                return ret;
+
+        ret = tps80031_reg_write(gpadc, SLAVE_ID1, MISC1, 0x02);
+        if (ret < 0)
+                return ret;
+
+        return ret;
+}
+
+int tps80031_gpadc_conversion(int channel_no)
+{
+        int ret = 0;
+        int read_value;
+
+        mutex_lock(&the_gpadc->lock);
+
+        ret = tps80031_gpadc_config(the_gpadc, channel_no);
+        if (ret < 0)
+                goto err;
+
+        /* start ADC conversion */
+        ret = tps80031_reg_write(the_gpadc, SLAVE_ID2, CTRL_P1, CTRL_P1_SP1);
+        if (ret < 0)
+                goto err;
+
+        /* Wait until conversion is ready (ctrl register returns EOC) */
+        ret = tps80031_gpadc_wait_conversion_ready(the_gpadc, 5);
+        if (ret) {
+                dev_dbg(the_gpadc->dev, "conversion timeout!\n");
+                goto err;
+        }
+
+        read_value = tps80031_gpadc_read_channels(the_gpadc, channel_no);
+        mutex_unlock(&the_gpadc->lock);
+        return read_value;
+err:
+        mutex_unlock(&the_gpadc->lock);
+        return ret;
+}
+EXPORT_SYMBOL_GPL(tps80031_gpadc_conversion);
+
+static SENSOR_DEVICE_ATTR(in0_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 0);
+static SENSOR_DEVICE_ATTR(in0_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 0);
+static SENSOR_DEVICE_ATTR(in1_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 1);
+static SENSOR_DEVICE_ATTR(in1_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 1);
+static SENSOR_DEVICE_ATTR(in2_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 2);
+static SENSOR_DEVICE_ATTR(in2_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 2);
+static SENSOR_DEVICE_ATTR(in3_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 3);
+static SENSOR_DEVICE_ATTR(in3_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 3);
+static SENSOR_DEVICE_ATTR(in4_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 4);
+static SENSOR_DEVICE_ATTR(in4_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 4);
+static SENSOR_DEVICE_ATTR(in5_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 5);
+static SENSOR_DEVICE_ATTR(in5_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 5);
+static SENSOR_DEVICE_ATTR(in6_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 6);
+static SENSOR_DEVICE_ATTR(in6_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 6);
+static SENSOR_DEVICE_ATTR(in7_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 7);
+static SENSOR_DEVICE_ATTR(in7_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 7);
+static SENSOR_DEVICE_ATTR(in8_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 8);
+static SENSOR_DEVICE_ATTR(in8_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 8);
+static SENSOR_DEVICE_ATTR(in9_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 9);
+static SENSOR_DEVICE_ATTR(in9_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 9);
+static SENSOR_DEVICE_ATTR(in10_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 10);
+static SENSOR_DEVICE_ATTR(in10_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 10);
+static SENSOR_DEVICE_ATTR(in11_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 11);
+static SENSOR_DEVICE_ATTR(in11_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 11);
+static SENSOR_DEVICE_ATTR(in12_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 12);
+static SENSOR_DEVICE_ATTR(in12_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 12);
+static SENSOR_DEVICE_ATTR(in13_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 13);
+static SENSOR_DEVICE_ATTR(in13_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 13);
+static SENSOR_DEVICE_ATTR(in14_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 14);
+static SENSOR_DEVICE_ATTR(in14_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 14);
+static SENSOR_DEVICE_ATTR(in15_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 15);
+static SENSOR_DEVICE_ATTR(in15_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 15);
+static SENSOR_DEVICE_ATTR(in16_gain, S_IRUGO|S_IWUSR, show_gain, set_gain, 16);
+static SENSOR_DEVICE_ATTR(in16_offset, S_IRUGO|S_IWUSR,
+                                                show_offset, set_offset, 16);
+
+#define IN_ATTRS(X)\
+        &sensor_dev_attr_in##X##_gain.dev_attr.attr,    \
+        &sensor_dev_attr_in##X##_offset.dev_attr.attr   \
+
+static struct attribute *tps80031_gpadc_attributes[] = {
+        IN_ATTRS(0),
+        IN_ATTRS(1),
+        IN_ATTRS(2),
+        IN_ATTRS(3),
+        IN_ATTRS(4),
+        IN_ATTRS(5),
+        IN_ATTRS(6),
+        IN_ATTRS(7),
+        IN_ATTRS(8),
+        IN_ATTRS(9),
+        IN_ATTRS(10),
+        IN_ATTRS(11),
+        IN_ATTRS(12),
+        IN_ATTRS(13),
+        IN_ATTRS(14),
+        IN_ATTRS(15),
+        IN_ATTRS(16),
+        NULL
+};
+
+static const struct attribute_group tps80031_gpadc_group = {
+        .attrs = tps80031_gpadc_attributes,
+};
+
+static long tps80031_gpadc_ioctl(struct file *filp, unsigned int cmd,
+                                                unsigned long arg)
+{
+        struct tps80031_gpadc_user_parms par;
+        int val, ret, channel_no;
+
+        ret = copy_from_user(&par, (void __user *) arg, sizeof(par));
+        if (ret) {
+                dev_dbg(the_gpadc->dev, "copy_from_user: %d\n", ret);
+                return -EACCES;
+        }
+        switch (cmd) {
+        case TPS80031_GPADC_IOCX_ADC_RAW_READ:
+                channel_no = par.channel;
+                val = tps80031_gpadc_conversion(channel_no);
+                if (likely(val > 0)) {
+                        par.status = 0;
+                        par.result = val;
+                } else if (val == 0) {
+                        par.status = -ENODATA;
+                } else {
+                        par.status = val;
+                }
+                break;
+        default:
+                return -EINVAL;
+        }
+        ret = copy_to_user((void __user *) arg, &par, sizeof(par));
+        if (ret) {
+                dev_dbg(the_gpadc->dev, "copy_to_user: %d\n", ret);
+                return -EACCES;
+        }
+        return 0;
+}
+
+static const struct file_operations tps80031_gpadc_fileops = {
+        .owner = THIS_MODULE,
+        .unlocked_ioctl = tps80031_gpadc_ioctl,
+};
+
+static struct miscdevice tps80031_gpadc_device = {
+        .minor = MISC_DYNAMIC_MINOR,
+        .name = "tps80031-gpadc",
+        .fops = &tps80031_gpadc_fileops
+};
+
+static int __devinit tps80031_gpadc_probe(struct platform_device *pdev)
+{
+        struct tps80031_gpadc_data *gpadc;
+
+        s16 delta_error1 = 0, delta_error2 = 0;
+        s16 ideal_code1, ideal_code2;
+        s16 scalar_delta1 = 0, scalar_delta2 = 0;
+        s32 gain_error_1;
+        s32 offset_error;
+        uint8_t l_delta1, l_delta2, h_delta2;
+        uint8_t l_scalar1, l_scalar2;
+        uint8_t sign;
+        uint8_t index;
+        int ret;
+
+        gpadc = devm_kzalloc(&pdev->dev, sizeof *gpadc, GFP_KERNEL);
+        if (!gpadc)
+                return -ENOMEM;
+
+        gpadc->dev = &pdev->dev;
+        ret = misc_register(&tps80031_gpadc_device);
+        if (ret) {
+                dev_dbg(&pdev->dev, "could not register misc_device\n");
+                return ret;
+        }
+
+        platform_set_drvdata(pdev, gpadc);
+        mutex_init(&gpadc->lock);
+
+        for (index = 0; index < TPS80031_GPADC_MAX_CHANNELS; index++) {
+                if (~calibration_bit_map & (1 << index))
+                        continue;
+
+                if (~scalar_bit_map & (1 << index)) {
+                        ret = tps80031_reg_read(gpadc, SLAVE_ID2,
+                                tps80031_trim[index].delta1_addr, &l_scalar1);
+                        if (ret < 0)
+                                goto err;
+                        ret = tps80031_reg_read(gpadc, SLAVE_ID2,
+                                tps80031_trim[index].delta2_addr, &l_scalar2);
+                        if (ret < 0)
+                                goto err;
+
+                        l_scalar1 &= tps80031_trim[index].delta1_mask;
+                        sign = l_scalar1 & 1;
+                        scalar_delta1 = l_scalar1 >> 1;
+                        if (sign)
+                                scalar_delta1 = 0 - scalar_delta1;
+                        l_scalar2 &= tps80031_trim[index].delta2_mask;
+                        sign = l_scalar2 & 1;
+                        scalar_delta2 = l_scalar2 >> 1;
+                        if (sign)
+                                scalar_delta2 = 0 - scalar_delta2;
+                } else {
+                        scalar_delta1 = 0;
+                        scalar_delta2 = 0;
+                }
+                ret = tps80031_reg_read(gpadc, SLAVE_ID2, TPS80031_GPADC_TRIM5,
+                                                        &l_delta1);
+                if (ret < 0)
+                        goto err;
+                ret = tps80031_reg_read(gpadc, SLAVE_ID2, TPS80031_GPADC_TRIM6,
+                                                        &l_delta2);
+                if (ret < 0)
+                        goto err;
+                ret = tps80031_reg_read(gpadc, SLAVE_ID2, TPS80031_GPADC_TRIM19,
+                                                        &h_delta2);
+                if (ret < 0)
+                        goto err;
+
+                sign = l_delta1 & 1;
+
+                delta_error1 = l_delta1 >> 1;
+                if (sign)
+                        delta_error1 = (0 - delta_error1);
+                sign = l_delta2 & 1;
+
+                delta_error2 = (l_delta2 >> 1) | (h_delta2 << 7);
+                if (sign)
+                        delta_error2 = (0 - delta_error2);
+                ideal_code1 = tps80031_ideal[index].code1 * 4;
+                ideal_code2 = tps80031_ideal[index].code2 * 4;
+
+                gain_error_1 = ((delta_error2 + scalar_delta2) -
+                                (delta_error1 - scalar_delta1)) *
+                                SCALE / (ideal_code2 - ideal_code1);
+                offset_error = (delta_error1 + scalar_delta1) *
+                                SCALE - gain_error_1 *  ideal_code1;
+
+                tps80031_calib_tbl[index].gain_error = gain_error_1 + SCALE;
+                tps80031_calib_tbl[index].offset_error = offset_error;
+        }
+
+        the_gpadc = gpadc;
+        ret = sysfs_create_group(&pdev->dev.kobj, &tps80031_gpadc_group);
+        if (ret) {
+                dev_err(&pdev->dev, "could not create sysfs files\n");
+                goto err;
+        }
+        return 0;
+err:
+        misc_deregister(&tps80031_gpadc_device);
+        return ret;
+}
+
+static int __devexit tps80031_gpadc_remove(struct platform_device *pdev)
+{
+        sysfs_remove_group(&pdev->dev.kobj, &tps80031_gpadc_group);
+        misc_deregister(&tps80031_gpadc_device);
+        return 0;
+}
+
+static struct platform_driver tps80031_gpadc_driver = {
+        .probe          = tps80031_gpadc_probe,
+        .remove         = __devexit_p(tps80031_gpadc_remove),
+        .driver         = {
+                .name   = "tps80031-gpadc",
+                .owner  = THIS_MODULE,
+        },
+};
+
+static int __init tps80031_gpadc_init(void)
+{
+        return platform_driver_register(&tps80031_gpadc_driver);
+}
+
+module_init(tps80031_gpadc_init);
+
+static void __exit tps80031_gpadc_exit(void)
+{
+        platform_driver_unregister(&tps80031_gpadc_driver);
+}
+
+module_exit(tps80031_gpadc_exit);
+MODULE_ALIAS("platform:tps80031-gpadc");
+MODULE_DESCRIPTION("tps80031 ADC driver");
diff --git a/drivers/mfd/twl6030-pwm.c b/drivers/mfd/twl6030-pwm.c
new file mode 100644
index 00000000000..e8fee147678
--- /dev/null
+++ b/drivers/mfd/twl6030-pwm.c
@@ -0,0 +1,165 @@
+/*
+ * twl6030_pwm.c
+ * Driver for PHOENIX (TWL6030) Pulse Width Modulator
+ *
+ * Copyright (C) 2010 Texas Instruments
+ * Author: Hemanth V <hemanthv@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/i2c/twl.h>
+#include <linux/slab.h>
+
+#define LED_PWM_CTRL1   0xF4
+#define LED_PWM_CTRL2   0xF5
+
+/* Max value for CTRL1 register */
+#define PWM_CTRL1_MAX   255
+
+/* Pull down disable */
+#define PWM_CTRL2_DIS_PD        (1 << 6)
+
+/* Current control 2.5 milli Amps */
+#define PWM_CTRL2_CURR_02       (2 << 4)
+
+/* LED supply source */
+#define PWM_CTRL2_SRC_VAC       (1 << 2)
+
+/* LED modes */
+#define PWM_CTRL2_MODE_HW       (0 << 0)
+#define PWM_CTRL2_MODE_SW       (1 << 0)
+#define PWM_CTRL2_MODE_DIS      (2 << 0)
+
+#define PWM_CTRL2_MODE_MASK     0x3
+
+struct pwm_device {
+        const char *label;
+        unsigned int pwm_id;
+};
+
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+        u8 duty_cycle;
+        int ret;
+
+        if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
+                return -EINVAL;
+
+        duty_cycle = (duty_ns * PWM_CTRL1_MAX) / period_ns;
+
+        ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, duty_cycle, LED_PWM_CTRL1);
+
+        if (ret < 0) {
+                pr_err("%s: Failed to configure PWM, Error %d\n",
+                        pwm->label, ret);
+                return ret;
+        }
+        return 0;
+}
+EXPORT_SYMBOL(pwm_config);
+
+int pwm_enable(struct pwm_device *pwm)
+{
+        u8 val;
+        int ret;
+
+        ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2);
+        if (ret < 0) {
+                pr_err("%s: Failed to enable PWM, Error %d\n", pwm->label, ret);
+                return ret;
+        }
+
+        /* Change mode to software control */
+        val &= ~PWM_CTRL2_MODE_MASK;
+        val |= PWM_CTRL2_MODE_SW;
+
+        ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, LED_PWM_CTRL2);
+        if (ret < 0) {
+                pr_err("%s: Failed to enable PWM, Error %d\n", pwm->label, ret);
+                return ret;
+        }
+
+        twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2);
+        return 0;
+}
+EXPORT_SYMBOL(pwm_enable);
+
+void pwm_disable(struct pwm_device *pwm)
+{
+        u8 val;
+        int ret;
+
+        ret = twl_i2c_read_u8(TWL6030_MODULE_ID1, &val, LED_PWM_CTRL2);
+        if (ret < 0) {
+                pr_err("%s: Failed to disable PWM, Error %d\n",
+                        pwm->label, ret);
+                return;
+        }
+
+        val &= ~PWM_CTRL2_MODE_MASK;
+        val |= PWM_CTRL2_MODE_HW;
+
+        ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, LED_PWM_CTRL2);
+        if (ret < 0) {
+                pr_err("%s: Failed to disable PWM, Error %d\n",
+                        pwm->label, ret);
+                return;
+        }
+        return;
+}
+EXPORT_SYMBOL(pwm_disable);
+
+struct pwm_device *pwm_request(int pwm_id, const char *label)
+{
+        u8 val;
+        int ret;
+        struct pwm_device *pwm;
+
+        pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
+        if (pwm == NULL) {
+                pr_err("%s: failed to allocate memory\n", label);
+                return NULL;
+        }
+
+        pwm->label = label;
+        pwm->pwm_id = pwm_id;
+
+        /* Configure PWM */
+        val = PWM_CTRL2_DIS_PD | PWM_CTRL2_CURR_02 | PWM_CTRL2_SRC_VAC |
+                PWM_CTRL2_MODE_HW;
+
+        ret = twl_i2c_write_u8(TWL6030_MODULE_ID1, val, LED_PWM_CTRL2);
+
+        if (ret < 0) {
+                pr_err("%s: Failed to configure PWM, Error %d\n",
+                         pwm->label, ret);
+
+                kfree(pwm);
+                return NULL;
+        }
+
+        return pwm;
+}
+EXPORT_SYMBOL(pwm_request);
+
+void pwm_free(struct pwm_device *pwm)
+{
+        pwm_disable(pwm);
+        kfree(pwm);
+}
+EXPORT_SYMBOL(pwm_free);
+
+MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/twl6040-core.c b/drivers/mfd/twl6040-core.c
new file mode 100644
index 00000000000..24d436c2fe4
--- /dev/null
+++ b/drivers/mfd/twl6040-core.c
@@ -0,0 +1,620 @@
+/*
+ * MFD driver for TWL6040 audio device
+ *
+ * Authors:     Misael Lopez Cruz <misael.lopez@ti.com>
+ *              Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
+ *              Peter Ujfalusi <peter.ujfalusi@ti.com>
+ *
+ * Copyright:   (C) 2011 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/i2c/twl.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/twl6040.h>
+
+static struct platform_device *twl6040_dev;
+
+int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg)
+{
+        int ret;
+        u8 val = 0;
+
+        mutex_lock(&twl6040->io_mutex);
+        ret = twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &val, reg);
+        if (ret < 0) {
+                mutex_unlock(&twl6040->io_mutex);
+                return ret;
+        }
+        mutex_unlock(&twl6040->io_mutex);
+
+        return val;
+}
+EXPORT_SYMBOL(twl6040_reg_read);
+
+int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg, u8 val)
+{
+        int ret;
+
+        mutex_lock(&twl6040->io_mutex);
+        ret = twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, val, reg);
+        mutex_unlock(&twl6040->io_mutex);
+
+        return ret;
+}
+EXPORT_SYMBOL(twl6040_reg_write);
+
+int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
+{
+        int ret;
+        u8 val;
+
+        mutex_lock(&twl6040->io_mutex);
+        ret = twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &val, reg);
+        if (ret)
+                goto out;
+
+        val |= mask;
+        ret = twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, val, reg);
+out:
+        mutex_unlock(&twl6040->io_mutex);
+        return ret;
+}
+EXPORT_SYMBOL(twl6040_set_bits);
+
+int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg, u8 mask)
+{
+        int ret;
+        u8 val;
+
+        mutex_lock(&twl6040->io_mutex);
+        ret = twl_i2c_read_u8(TWL_MODULE_AUDIO_VOICE, &val, reg);
+        if (ret)
+                goto out;
+
+        val &= ~mask;
+        ret = twl_i2c_write_u8(TWL_MODULE_AUDIO_VOICE, val, reg);
+out:
+        mutex_unlock(&twl6040->io_mutex);
+        return ret;
+}
+EXPORT_SYMBOL(twl6040_clear_bits);
+
+/* twl6040 codec manual power-up sequence */
+static int twl6040_power_up(struct twl6040 *twl6040)
+{
+        u8 ldoctl, ncpctl, lppllctl;
+        int ret;
+
+        /* enable high-side LDO, reference system and internal oscillator */
+        ldoctl = TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA;
+        ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+        if (ret)
+                return ret;
+        usleep_range(10000, 10500);
+
+        /* enable negative charge pump */
+        ncpctl = TWL6040_NCPENA;
+        ret = twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
+        if (ret)
+                goto ncp_err;
+        usleep_range(1000, 1500);
+
+        /* enable low-side LDO */
+        ldoctl |= TWL6040_LSLDOENA;
+        ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+        if (ret)
+                goto lsldo_err;
+        usleep_range(1000, 1500);
+
+        /* enable low-power PLL */
+        lppllctl = TWL6040_LPLLENA;
+        ret = twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
+        if (ret)
+                goto lppll_err;
+        usleep_range(5000, 5500);
+
+        /* disable internal oscillator */
+        ldoctl &= ~TWL6040_OSCENA;
+        ret = twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+        if (ret)
+                goto osc_err;
+
+        return 0;
+
+osc_err:
+        lppllctl &= ~TWL6040_LPLLENA;
+        twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
+lppll_err:
+        ldoctl &= ~TWL6040_LSLDOENA;
+        twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+lsldo_err:
+        ncpctl &= ~TWL6040_NCPENA;
+        twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
+ncp_err:
+        ldoctl &= ~(TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA);
+        twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+
+        return ret;
+}
+
+/* twl6040 manual power-down sequence */
+static void twl6040_power_down(struct twl6040 *twl6040)
+{
+        u8 ncpctl, ldoctl, lppllctl;
+
+        ncpctl = twl6040_reg_read(twl6040, TWL6040_REG_NCPCTL);
+        ldoctl = twl6040_reg_read(twl6040, TWL6040_REG_LDOCTL);
+        lppllctl = twl6040_reg_read(twl6040, TWL6040_REG_LPPLLCTL);
+
+        /* enable internal oscillator */
+        ldoctl |= TWL6040_OSCENA;
+        twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+        usleep_range(1000, 1500);
+
+        /* disable low-power PLL */
+        lppllctl &= ~TWL6040_LPLLENA;
+        twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
+
+        /* disable low-side LDO */
+        ldoctl &= ~TWL6040_LSLDOENA;
+        twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+
+        /* disable negative charge pump */
+        ncpctl &= ~TWL6040_NCPENA;
+        twl6040_reg_write(twl6040, TWL6040_REG_NCPCTL, ncpctl);
+
+        /* disable high-side LDO, reference system and internal oscillator */
+        ldoctl &= ~(TWL6040_HSLDOENA | TWL6040_REFENA | TWL6040_OSCENA);
+        twl6040_reg_write(twl6040, TWL6040_REG_LDOCTL, ldoctl);
+}
+
+static irqreturn_t twl6040_naudint_handler(int irq, void *data)
+{
+        struct twl6040 *twl6040 = data;
+        u8 intid, status;
+
+        intid = twl6040_reg_read(twl6040, TWL6040_REG_INTID);
+
+        if (intid & TWL6040_READYINT)
+                complete(&twl6040->ready);
+
+        if (intid & TWL6040_THINT) {
+                status = twl6040_reg_read(twl6040, TWL6040_REG_STATUS);
+                if (status & TWL6040_TSHUTDET) {
+                        dev_warn(&twl6040_dev->dev,
+                                 "Thermal shutdown, powering-off");
+                        twl6040_power(twl6040, 0);
+                } else {
+                        dev_warn(&twl6040_dev->dev,
+                                 "Leaving thermal shutdown, powering-on");
+                        twl6040_power(twl6040, 1);
+                }
+        }
+
+        return IRQ_HANDLED;
+}
+
+static int twl6040_power_up_completion(struct twl6040 *twl6040,
+                                       int naudint)
+{
+        int time_left;
+        u8 intid;
+
+        time_left = wait_for_completion_timeout(&twl6040->ready,
+                                                msecs_to_jiffies(144));
+        if (!time_left) {
+                intid = twl6040_reg_read(twl6040, TWL6040_REG_INTID);
+                if (!(intid & TWL6040_READYINT)) {
+                        dev_err(&twl6040_dev->dev,
+                                "timeout waiting for READYINT\n");
+                        return -ETIMEDOUT;
+                }
+        }
+
+        return 0;
+}
+
+int twl6040_power(struct twl6040 *twl6040, int on)
+{
+        int audpwron = twl6040->audpwron;
+        int naudint = twl6040->irq;
+        int ret = 0;
+
+        mutex_lock(&twl6040->mutex);
+
+        if (on) {
+                /* already powered-up */
+                if (twl6040->power_count++)
+                        goto out;
+
+                if (gpio_is_valid(audpwron)) {
+                        /* use AUDPWRON line */
+                        gpio_set_value(audpwron, 1);
+                        /* wait for power-up completion */
+                        ret = twl6040_power_up_completion(twl6040, naudint);
+                        if (ret) {
+                                dev_err(&twl6040_dev->dev,
+                                        "automatic power-down failed\n");
+                                twl6040->power_count = 0;
+                                goto out;
+                        }
+                } else {
+                        /* use manual power-up sequence */
+                        ret = twl6040_power_up(twl6040);
+                        if (ret) {
+                                dev_err(&twl6040_dev->dev,
+                                        "manual power-up failed\n");
+                                twl6040->power_count = 0;
+                                goto out;
+                        }
+                }
+                /* Default PLL configuration after power up */
+                twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL;
+                twl6040->sysclk = 19200000;
+        } else {
+                /* already powered-down */
+                if (!twl6040->power_count) {
+                        dev_err(&twl6040_dev->dev,
+                                "device is already powered-off\n");
+                        ret = -EPERM;
+                        goto out;
+                }
+
+                if (--twl6040->power_count)
+                        goto out;
+
+                if (gpio_is_valid(audpwron)) {
+                        /* use AUDPWRON line */
+                        gpio_set_value(audpwron, 0);
+
+                        /* power-down sequence latency */
+                        usleep_range(500, 700);
+                } else {
+                        /* use manual power-down sequence */
+                        twl6040_power_down(twl6040);
+                }
+                twl6040->sysclk = 0;
+        }
+
+out:
+        mutex_unlock(&twl6040->mutex);
+        return ret;
+}
+EXPORT_SYMBOL(twl6040_power);
+
+int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
+                    unsigned int freq_in, unsigned int freq_out)
+{
+        u8 hppllctl, lppllctl;
+        int ret = 0;
+
+        mutex_lock(&twl6040->mutex);
+
+        hppllctl = twl6040_reg_read(twl6040, TWL6040_REG_HPPLLCTL);
+        lppllctl = twl6040_reg_read(twl6040, TWL6040_REG_LPPLLCTL);
+
+        switch (pll_id) {
+        case TWL6040_SYSCLK_SEL_LPPLL:
+                /* low-power PLL divider */
+                switch (freq_out) {
+                case 17640000:
+                        lppllctl |= TWL6040_LPLLFIN;
+                        break;
+                case 19200000:
+                        lppllctl &= ~TWL6040_LPLLFIN;
+                        break;
+                default:
+                        dev_err(&twl6040_dev->dev,
+                                "freq_out %d not supported\n", freq_out);
+                        ret = -EINVAL;
+                        goto pll_out;
+                }
+                twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
+
+                switch (freq_in) {
+                case 32768:
+                        lppllctl |= TWL6040_LPLLENA;
+                        twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
+                                          lppllctl);
+                        mdelay(5);
+                        lppllctl &= ~TWL6040_HPLLSEL;
+                        twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL,
+                                          lppllctl);
+                        hppllctl &= ~TWL6040_HPLLENA;
+                        twl6040_reg_write(twl6040, TWL6040_REG_HPPLLCTL,
+                                          hppllctl);
+                        break;
+                default:
+                        dev_err(&twl6040_dev->dev,
+                                "freq_in %d not supported\n", freq_in);
+                        ret = -EINVAL;
+                        goto pll_out;
+                }
+                break;
+        case TWL6040_SYSCLK_SEL_HPPLL:
+                /* high-performance PLL can provide only 19.2 MHz */
+                if (freq_out != 19200000) {
+                        dev_err(&twl6040_dev->dev,
+                                "freq_out %d not supported\n", freq_out);
+                        ret = -EINVAL;
+                        goto pll_out;
+                }
+
+                hppllctl &= ~TWL6040_MCLK_MSK;
+
+                switch (freq_in) {
+                case 12000000:
+                        /* PLL enabled, active mode */
+                        hppllctl |= TWL6040_MCLK_12000KHZ |
+                                    TWL6040_HPLLENA;
+                        break;
+                case 19200000:
+                        /*
+                         * PLL disabled
+                         * (enable PLL if MCLK jitter quality
+                         *  doesn't meet specification)
+                         */
+                        hppllctl |= TWL6040_MCLK_19200KHZ;
+                        break;
+                case 26000000:
+                        /* PLL enabled, active mode */
+                        hppllctl |= TWL6040_MCLK_26000KHZ |
+                                    TWL6040_HPLLENA;
+                        break;
+                case 38400000:
+                        /* PLL enabled, active mode */
+                        hppllctl |= TWL6040_MCLK_38400KHZ |
+                                    TWL6040_HPLLENA;
+                        break;
+                default:
+                        dev_err(&twl6040_dev->dev,
+                                "freq_in %d not supported\n", freq_in);
+                        ret = -EINVAL;
+                        goto pll_out;
+                }
+
+                /* enable clock slicer to ensure input waveform is square */
+                hppllctl |= TWL6040_HPLLSQRENA;
+
+                twl6040_reg_write(twl6040, TWL6040_REG_HPPLLCTL, hppllctl);
+                usleep_range(500, 700);
+                lppllctl |= TWL6040_HPLLSEL;
+                twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
+                lppllctl &= ~TWL6040_LPLLENA;
+                twl6040_reg_write(twl6040, TWL6040_REG_LPPLLCTL, lppllctl);
+                break;
+        default:
+                dev_err(&twl6040_dev->dev, "unknown pll id %d\n", pll_id);
+                ret = -EINVAL;
+                goto pll_out;
+        }
+
+        twl6040->sysclk = freq_out;
+        twl6040->pll = pll_id;
+
+pll_out:
+        mutex_unlock(&twl6040->mutex);
+        return ret;
+}
+EXPORT_SYMBOL(twl6040_set_pll);
+
+int twl6040_get_pll(struct twl6040 *twl6040)
+{
+        if (twl6040->power_count)
+                return twl6040->pll;
+        else
+                return -ENODEV;
+}
+EXPORT_SYMBOL(twl6040_get_pll);
+
+unsigned int twl6040_get_sysclk(struct twl6040 *twl6040)
+{
+        return twl6040->sysclk;
+}
+EXPORT_SYMBOL(twl6040_get_sysclk);
+
+static struct resource twl6040_vibra_rsrc[] = {
+        {
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static struct resource twl6040_codec_rsrc[] = {
+        {
+                .flags = IORESOURCE_IRQ,
+        },
+};
+
+static int __devinit twl6040_probe(struct platform_device *pdev)
+{
+        struct twl4030_audio_data *pdata = pdev->dev.platform_data;
+        struct twl6040 *twl6040;
+        struct mfd_cell *cell = NULL;
+        int ret, children = 0;
+
+        if (!pdata) {
+                dev_err(&pdev->dev, "Platform data is missing\n");
+                return -EINVAL;
+        }
+
+        /* In order to operate correctly we need valid interrupt config */
+        if (!pdata->naudint_irq || !pdata->irq_base) {
+                dev_err(&pdev->dev, "Invalid IRQ configuration\n");
+                return -EINVAL;
+        }
+
+        twl6040 = kzalloc(sizeof(struct twl6040), GFP_KERNEL);
+        if (!twl6040)
+                return -ENOMEM;
+
+        platform_set_drvdata(pdev, twl6040);
+
+        twl6040_dev = pdev;
+        twl6040->dev = &pdev->dev;
+        twl6040->audpwron = pdata->audpwron_gpio;
+        twl6040->irq = pdata->naudint_irq;
+        twl6040->irq_base = pdata->irq_base;
+
+        mutex_init(&twl6040->mutex);
+        mutex_init(&twl6040->io_mutex);
+        init_completion(&twl6040->ready);
+
+        twl6040->rev = twl6040_reg_read(twl6040, TWL6040_REG_ASICREV);
+
+        if (gpio_is_valid(twl6040->audpwron)) {
+                ret = gpio_request(twl6040->audpwron, "audpwron");
+                if (ret)
+                        goto gpio1_err;
+
+                ret = gpio_direction_output(twl6040->audpwron, 0);
+                if (ret)
+                        goto gpio2_err;
+        }
+
+        /* ERRATA: Automatic power-up is not possible in ES1.0 */
+        if (twl6040->rev == TWL6040_REV_ES1_0)
+                twl6040->audpwron = -EINVAL;
+
+        /* codec interrupt */
+        ret = twl6040_irq_init(twl6040);
+        if (ret)
+                goto gpio2_err;
+
+        ret = request_threaded_irq(twl6040->irq_base + TWL6040_IRQ_READY,
+                                   NULL, twl6040_naudint_handler, 0,
+                                   "twl6040_irq_ready", twl6040);
+        if (ret) {
+                dev_err(twl6040->dev, "READY IRQ request failed: %d\n",
+                        ret);
+                goto irq_err;
+        }
+
+        /* dual-access registers controlled by I2C only */
+        twl6040_set_bits(twl6040, TWL6040_REG_ACCCTL, TWL6040_I2CSEL);
+
+        if (pdata->codec) {
+                int irq = twl6040->irq_base + TWL6040_IRQ_PLUG;
+
+                cell = &twl6040->cells[children];
+                cell->name = "twl6040-codec";
+                twl6040_codec_rsrc[0].start = irq;
+                twl6040_codec_rsrc[0].end = irq;
+                cell->resources = twl6040_codec_rsrc;
+                cell->num_resources = ARRAY_SIZE(twl6040_codec_rsrc);
+                cell->platform_data = pdata->codec;
+                cell->pdata_size = sizeof(*pdata->codec);
+                children++;
+        }
+
+        if (pdata->vibra) {
+                int irq = twl6040->irq_base + TWL6040_IRQ_VIB;
+
+                cell = &twl6040->cells[children];
+                cell->name = "twl6040-vibra";
+                twl6040_vibra_rsrc[0].start = irq;
+                twl6040_vibra_rsrc[0].end = irq;
+                cell->resources = twl6040_vibra_rsrc;
+                cell->num_resources = ARRAY_SIZE(twl6040_vibra_rsrc);
+
+                cell->platform_data = pdata->vibra;
+                cell->pdata_size = sizeof(*pdata->vibra);
+                children++;
+        }
+
+        if (children) {
+                ret = mfd_add_devices(&pdev->dev, pdev->id, twl6040->cells,
+                                      children, NULL, 0);
+                if (ret)
+                        goto mfd_err;
+        } else {
+                dev_err(&pdev->dev, "No platform data found for children\n");
+                ret = -ENODEV;
+                goto mfd_err;
+        }
+
+        return 0;
+
+mfd_err:
+        free_irq(twl6040->irq_base + TWL6040_IRQ_READY, twl6040);
+irq_err:
+        twl6040_irq_exit(twl6040);
+gpio2_err:
+        if (gpio_is_valid(twl6040->audpwron))
+                gpio_free(twl6040->audpwron);
+gpio1_err:
+        platform_set_drvdata(pdev, NULL);
+        kfree(twl6040);
+        twl6040_dev = NULL;
+        return ret;
+}
+
+static int __devexit twl6040_remove(struct platform_device *pdev)
+{
+        struct twl6040 *twl6040 = platform_get_drvdata(pdev);
+
+        if (twl6040->power_count)
+                twl6040_power(twl6040, 0);
+
+        if (gpio_is_valid(twl6040->audpwron))
+                gpio_free(twl6040->audpwron);
+
+        free_irq(twl6040->irq_base + TWL6040_IRQ_READY, twl6040);
+        twl6040_irq_exit(twl6040);
+
+        mfd_remove_devices(&pdev->dev);
+        platform_set_drvdata(pdev, NULL);
+        kfree(twl6040);
+        twl6040_dev = NULL;
+
+        return 0;
+}
+
+static struct platform_driver twl6040_driver = {
+        .probe          = twl6040_probe,
+        .remove         = __devexit_p(twl6040_remove),
+        .driver         = {
+                .owner  = THIS_MODULE,
+                .name   = "twl6040",
+        },
+};
+
+static int __devinit twl6040_init(void)
+{
+        return platform_driver_register(&twl6040_driver);
+}
+module_init(twl6040_init);
+
+static void __devexit twl6040_exit(void)
+{
+        platform_driver_unregister(&twl6040_driver);
+}
+
+module_exit(twl6040_exit);
+
+MODULE_DESCRIPTION("TWL6040 MFD");
+MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
+MODULE_AUTHOR("Jorge Eduardo Candelaria <jorge.candelaria@ti.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:twl6040");
diff --git a/drivers/mfd/twl6040-irq.c b/drivers/mfd/twl6040-irq.c
new file mode 100644
index 00000000000..b3f8ddaa28a
--- /dev/null
+++ b/drivers/mfd/twl6040-irq.c
@@ -0,0 +1,191 @@
+/*
+ * Interrupt controller support for TWL6040
+ *
+ * Author:     Misael Lopez Cruz <misael.lopez@ti.com>
+ *
+ * Copyright:   (C) 2011 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/twl6040.h>
+
+struct twl6040_irq_data {
+        int mask;
+        int status;
+};
+
+static struct twl6040_irq_data twl6040_irqs[] = {
+        {
+                .mask = TWL6040_THMSK,
+                .status = TWL6040_THINT,
+        },
+        {
+                .mask = TWL6040_PLUGMSK,
+                .status = TWL6040_PLUGINT | TWL6040_UNPLUGINT,
+        },
+        {
+                .mask = TWL6040_HOOKMSK,
+                .status = TWL6040_HOOKINT,
+        },
+        {
+                .mask = TWL6040_HFMSK,
+                .status = TWL6040_HFINT,
+        },
+        {
+                .mask = TWL6040_VIBMSK,
+                .status = TWL6040_VIBINT,
+        },
+        {
+                .mask = TWL6040_READYMSK,
+                .status = TWL6040_READYINT,
+        },
+};
+
+static inline
+struct twl6040_irq_data *irq_to_twl6040_irq(struct twl6040 *twl6040,
+                                            int irq)
+{
+        return &twl6040_irqs[irq - twl6040->irq_base];
+}
+
+static void twl6040_irq_lock(struct irq_data *data)
+{
+        struct twl6040 *twl6040 = irq_data_get_irq_chip_data(data);
+
+        mutex_lock(&twl6040->irq_mutex);
+}
+
+static void twl6040_irq_sync_unlock(struct irq_data *data)
+{
+        struct twl6040 *twl6040 = irq_data_get_irq_chip_data(data);
+
+        /* write back to hardware any change in irq mask */
+        if (twl6040->irq_masks_cur != twl6040->irq_masks_cache) {
+                twl6040->irq_masks_cache = twl6040->irq_masks_cur;
+                twl6040_reg_write(twl6040, TWL6040_REG_INTMR,
+                                  twl6040->irq_masks_cur);
+        }
+
+        mutex_unlock(&twl6040->irq_mutex);
+}
+
+static void twl6040_irq_enable(struct irq_data *data)
+{
+        struct twl6040 *twl6040 = irq_data_get_irq_chip_data(data);
+        struct twl6040_irq_data *irq_data = irq_to_twl6040_irq(twl6040,
+                                                               data->irq);
+
+        twl6040->irq_masks_cur &= ~irq_data->mask;
+}
+
+static void twl6040_irq_disable(struct irq_data *data)
+{
+        struct twl6040 *twl6040 = irq_data_get_irq_chip_data(data);
+        struct twl6040_irq_data *irq_data = irq_to_twl6040_irq(twl6040,
+                                                               data->irq);
+
+        twl6040->irq_masks_cur |= irq_data->mask;
+}
+
+static struct irq_chip twl6040_irq_chip = {
+        .name                   = "twl6040",
+        .irq_bus_lock           = twl6040_irq_lock,
+        .irq_bus_sync_unlock    = twl6040_irq_sync_unlock,
+        .irq_enable             = twl6040_irq_enable,
+        .irq_disable            = twl6040_irq_disable,
+};
+
+static irqreturn_t twl6040_irq_thread(int irq, void *data)
+{
+        struct twl6040 *twl6040 = data;
+        u8 intid;
+        int i;
+
+        intid = twl6040_reg_read(twl6040, TWL6040_REG_INTID);
+
+        /* apply masking and report (backwards to handle READYINT first) */
+        for (i = ARRAY_SIZE(twl6040_irqs) - 1; i >= 0; i--) {
+                if (twl6040->irq_masks_cur & twl6040_irqs[i].mask)
+                        intid &= ~twl6040_irqs[i].status;
+                if (intid & twl6040_irqs[i].status)
+                        handle_nested_irq(twl6040->irq_base + i);
+        }
+
+        /* ack unmasked irqs */
+        twl6040_reg_write(twl6040, TWL6040_REG_INTID, intid);
+
+        return IRQ_HANDLED;
+}
+
+int twl6040_irq_init(struct twl6040 *twl6040)
+{
+        int cur_irq, ret;
+        u8 val;
+
+        mutex_init(&twl6040->irq_mutex);
+
+        /* mask the individual interrupt sources */
+        twl6040->irq_masks_cur = TWL6040_ALLINT_MSK;
+        twl6040->irq_masks_cache = TWL6040_ALLINT_MSK;
+        twl6040_reg_write(twl6040, TWL6040_REG_INTMR, TWL6040_ALLINT_MSK);
+
+        /* Register them with genirq */
+        for (cur_irq = twl6040->irq_base;
+             cur_irq < twl6040->irq_base + ARRAY_SIZE(twl6040_irqs);
+             cur_irq++) {
+                irq_set_chip_data(cur_irq, twl6040);
+                irq_set_chip_and_handler(cur_irq, &twl6040_irq_chip,
+                                         handle_level_irq);
+                irq_set_nested_thread(cur_irq, 1);
+
+                /* ARM needs us to explicitly flag the IRQ as valid
+                 * and will set them noprobe when we do so. */
+#ifdef CONFIG_ARM
+                set_irq_flags(cur_irq, IRQF_VALID);
+#else
+                irq_set_noprobe(cur_irq);
+#endif
+        }
+
+        ret = request_threaded_irq(twl6040->irq, NULL, twl6040_irq_thread,
+                                   IRQF_ONESHOT, "twl6040", twl6040);
+        if (ret) {
+                dev_err(twl6040->dev, "failed to request IRQ %d: %d\n",
+                        twl6040->irq, ret);
+                return ret;
+        }
+
+        /* reset interrupts */
+        val = twl6040_reg_read(twl6040, TWL6040_REG_INTID);
+
+        /* interrupts cleared on write */
+        twl6040_clear_bits(twl6040, TWL6040_REG_ACCCTL, TWL6040_INTCLRMODE);
+
+        return 0;
+}
+EXPORT_SYMBOL(twl6040_irq_init);
+
+void twl6040_irq_exit(struct twl6040 *twl6040)
+{
+        free_irq(twl6040->irq, twl6040);
+}
+EXPORT_SYMBOL(twl6040_irq_exit);