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path: root/drivers/mfd/max77663-core.c
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-rw-r--r--drivers/mfd/max77663-core.c1445
1 files changed, 1445 insertions, 0 deletions
diff --git a/drivers/mfd/max77663-core.c b/drivers/mfd/max77663-core.c
new file mode 100644
index 00000000000..ff47cb123d0
--- /dev/null
+++ b/drivers/mfd/max77663-core.c
@@ -0,0 +1,1445 @@
1/*
2 * drivers/mfd/max77663-core.c
3 * Max77663 mfd driver (I2C bus access)
4 *
5 * Copyright 2011 Maxim Integrated Products, Inc.
6 * Copyright (C) 2011-2012 NVIDIA Corporation
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
12 *
13 */
14
15#include <linux/interrupt.h>
16#include <linux/i2c.h>
17#include <linux/gpio.h>
18#include <linux/slab.h>
19#include <linux/ratelimit.h>
20#include <linux/kthread.h>
21#include <linux/mfd/core.h>
22#include <linux/platform_device.h>
23#include <linux/seq_file.h>
24#include <linux/debugfs.h>
25#include <linux/delay.h>
26#include <linux/uaccess.h>
27
28#include <linux/mfd/max77663-core.h>
29
30/* RTC i2c slave address */
31#define MAX77663_RTC_I2C_ADDR 0x48
32
33/* Registers */
34#define MAX77663_REG_IRQ_TOP 0x05
35#define MAX77663_REG_LBT_IRQ 0x06
36#define MAX77663_REG_SD_IRQ 0x07
37#define MAX77663_REG_LDOX_IRQ 0x08
38#define MAX77663_REG_LDO8_IRQ 0x09
39#define MAX77663_REG_GPIO_IRQ 0x0A
40#define MAX77663_REG_ONOFF_IRQ 0x0B
41#define MAX77663_REG_NVER 0x0C
42#define MAX77663_REG_IRQ_TOP_MASK 0x0D
43#define MAX77663_REG_LBT_IRQ_MASK 0x0E
44#define MAX77663_REG_SD_IRQ_MASK 0x0F
45#define MAX77663_REG_LDOX_IRQ_MASK 0x10
46#define MAX77663_REG_LDO8_IRQ_MASK 0x11
47#define MAX77663_REG_ONOFF_IRQ_MASK 0x12
48#define MAX77663_REG_GPIO_CTRL0 0x36
49#define MAX77663_REG_GPIO_CTRL1 0x37
50#define MAX77663_REG_GPIO_CTRL2 0x38
51#define MAX77663_REG_GPIO_CTRL3 0x39
52#define MAX77663_REG_GPIO_CTRL4 0x3A
53#define MAX77663_REG_GPIO_CTRL5 0x3B
54#define MAX77663_REG_GPIO_CTRL6 0x3C
55#define MAX77663_REG_GPIO_CTRL7 0x3D
56#define MAX77663_REG_GPIO_PU 0x3E
57#define MAX77663_REG_GPIO_PD 0x3F
58#define MAX77663_REG_GPIO_ALT 0x40
59#define MAX77663_REG_ONOFF_CFG1 0x41
60#define MAX77663_REG_ONOFF_CFG2 0x42
61
62#define IRQ_TOP_GLBL_MASK (1 << 7)
63#define IRQ_TOP_GLBL_SHIFT 7
64#define IRQ_TOP_SD_MASK (1 << 6)
65#define IRQ_TOP_SD_SHIFT 6
66#define IRQ_TOP_LDO_MASK (1 << 5)
67#define IRQ_TOP_LDO_SHIFT 5
68#define IRQ_TOP_GPIO_MASK (1 << 4)
69#define IRQ_TOP_GPIO_SHIFT 4
70#define IRQ_TOP_RTC_MASK (1 << 3)
71#define IRQ_TOP_RTC_SHIFT 3
72#define IRQ_TOP_32K_MASK (1 << 2)
73#define IRQ_TOP_32K_SHIFT 2
74#define IRQ_TOP_ONOFF_MASK (1 << 1)
75#define IRQ_TOP_ONOFF_SHIFT 1
76#define IRQ_TOP_NVER_MASK (1 << 0)
77#define IRQ_TOP_NVER_SHIFT 0
78
79#define IRQ_GLBL_MASK (1 << 0)
80
81#define IRQ_LBT_BASE MAX77663_IRQ_LBT_LB
82#define IRQ_LBT_END MAX77663_IRQ_LBT_THERM_ALRM2
83
84#define IRQ_GPIO_BASE MAX77663_IRQ_GPIO0
85#define IRQ_GPIO_END MAX77663_IRQ_GPIO7
86
87#define IRQ_ONOFF_BASE MAX77663_IRQ_ONOFF_HRDPOWRN
88#define IRQ_ONOFF_END MAX77663_IRQ_ONOFF_ACOK_RISING
89
90#define GPIO_REG_ADDR(offset) (MAX77663_REG_GPIO_CTRL0 + offset)
91
92#define GPIO_CTRL_DBNC_MASK (3 << 6)
93#define GPIO_CTRL_DBNC_SHIFT 6
94#define GPIO_CTRL_REFE_IRQ_MASK (3 << 4)
95#define GPIO_CTRL_REFE_IRQ_SHIFT 4
96#define GPIO_CTRL_DOUT_MASK (1 << 3)
97#define GPIO_CTRL_DOUT_SHIFT 3
98#define GPIO_CTRL_DIN_MASK (1 << 2)
99#define GPIO_CTRL_DIN_SHIFT 2
100#define GPIO_CTRL_DIR_MASK (1 << 1)
101#define GPIO_CTRL_DIR_SHIFT 1
102#define GPIO_CTRL_OUT_DRV_MASK (1 << 0)
103#define GPIO_CTRL_OUT_DRV_SHIFT 0
104
105#define GPIO_REFE_IRQ_NONE 0
106#define GPIO_REFE_IRQ_EDGE_FALLING 1
107#define GPIO_REFE_IRQ_EDGE_RISING 2
108#define GPIO_REFE_IRQ_EDGE_BOTH 3
109
110#define GPIO_DBNC_NONE 0
111#define GPIO_DBNC_8MS 1
112#define GPIO_DBNC_16MS 2
113#define GPIO_DBNC_32MS 3
114
115#define ONOFF_SFT_RST_MASK (1 << 7)
116#define ONOFF_SLPEN_MASK (1 << 2)
117#define ONOFF_PWR_OFF_MASK (1 << 1)
118
119#define ONOFF_SLP_LPM_MASK (1 << 5)
120
121enum {
122 CACHE_IRQ_LBT,
123 CACHE_IRQ_SD,
124 CACHE_IRQ_LDO,
125 CACHE_IRQ_ONOFF,
126 CACHE_IRQ_NR,
127};
128
129struct max77663_irq_data {
130 int mask_reg;
131 u16 mask;
132 u8 top_mask;
133 u8 top_shift;
134 int cache_idx;
135 bool is_rtc;
136 bool is_unmask;
137 u8 trigger_type;
138};
139
140struct max77663_chip {
141 struct device *dev;
142 struct i2c_client *i2c_power;
143 struct i2c_client *i2c_rtc;
144
145 struct max77663_platform_data *pdata;
146 struct mutex io_lock;
147
148 struct irq_chip irq;
149 struct mutex irq_lock;
150 int irq_base;
151 int irq_top_count[8];
152 u8 cache_irq_top_mask;
153 u16 cache_irq_mask[CACHE_IRQ_NR];
154
155 struct gpio_chip gpio;
156 int gpio_base;
157 u8 cache_gpio_ctrl[MAX77663_GPIO_NR];
158 u8 cache_gpio_pu;
159 u8 cache_gpio_pd;
160 u8 cache_gpio_alt;
161
162 u8 rtc_i2c_addr;
163};
164
165struct max77663_chip *max77663_chip;
166
167#define IRQ_DATA_LBT(_name, _shift) \
168 [MAX77663_IRQ_LBT_##_name] = { \
169 .mask_reg = MAX77663_REG_LBT_IRQ_MASK, \
170 .mask = (1 << _shift), \
171 .top_mask = IRQ_TOP_GLBL_MASK, \
172 .top_shift = IRQ_TOP_GLBL_SHIFT, \
173 .cache_idx = CACHE_IRQ_LBT, \
174 }
175
176#define IRQ_DATA_GPIO(_name) \
177 [MAX77663_IRQ_GPIO##_name] = { \
178 .mask = (1 << _name), \
179 .top_mask = IRQ_TOP_GPIO_MASK, \
180 .top_shift = IRQ_TOP_GPIO_SHIFT, \
181 .cache_idx = -1, \
182 }
183
184#define IRQ_DATA_ONOFF(_name, _shift) \
185 [MAX77663_IRQ_ONOFF_##_name] = { \
186 .mask_reg = MAX77663_REG_ONOFF_IRQ_MASK,\
187 .mask = (1 << _shift), \
188 .top_mask = IRQ_TOP_ONOFF_MASK, \
189 .top_shift = IRQ_TOP_ONOFF_SHIFT, \
190 .cache_idx = CACHE_IRQ_ONOFF, \
191 }
192
193static struct max77663_irq_data max77663_irqs[MAX77663_IRQ_NR] = {
194 IRQ_DATA_LBT(LB, 3),
195 IRQ_DATA_LBT(THERM_ALRM1, 2),
196 IRQ_DATA_LBT(THERM_ALRM2, 1),
197 IRQ_DATA_GPIO(0),
198 IRQ_DATA_GPIO(1),
199 IRQ_DATA_GPIO(2),
200 IRQ_DATA_GPIO(3),
201 IRQ_DATA_GPIO(4),
202 IRQ_DATA_GPIO(5),
203 IRQ_DATA_GPIO(6),
204 IRQ_DATA_GPIO(7),
205 IRQ_DATA_ONOFF(HRDPOWRN, 0),
206 IRQ_DATA_ONOFF(EN0_1SEC, 1),
207 IRQ_DATA_ONOFF(EN0_FALLING, 2),
208 IRQ_DATA_ONOFF(EN0_RISING, 3),
209 IRQ_DATA_ONOFF(LID_FALLING, 4),
210 IRQ_DATA_ONOFF(LID_RISING, 5),
211 IRQ_DATA_ONOFF(ACOK_FALLING, 6),
212 IRQ_DATA_ONOFF(ACOK_RISING, 7),
213 [MAX77663_IRQ_RTC] = {
214 .top_mask = IRQ_TOP_RTC_MASK,
215 .top_shift = IRQ_TOP_RTC_SHIFT,
216 .cache_idx = -1,
217 .is_rtc = 1,
218 },
219 [MAX77663_IRQ_SD_PF] = {
220 .mask_reg = MAX77663_REG_SD_IRQ_MASK,
221 .mask = 0xF8,
222 .top_mask = IRQ_TOP_SD_MASK,
223 .top_shift = IRQ_TOP_SD_SHIFT,
224 .cache_idx = CACHE_IRQ_SD,
225 },
226 [MAX77663_IRQ_LDO_PF] = {
227 .mask_reg = MAX77663_REG_LDOX_IRQ_MASK,
228 .mask = 0x1FF,
229 .top_mask = IRQ_TOP_LDO_MASK,
230 .top_shift = IRQ_TOP_LDO_SHIFT,
231 .cache_idx = CACHE_IRQ_LDO,
232 },
233 [MAX77663_IRQ_32K] = {
234 .top_mask = IRQ_TOP_32K_MASK,
235 .top_shift = IRQ_TOP_32K_SHIFT,
236 .cache_idx = -1,
237 },
238 [MAX77663_IRQ_NVER] = {
239 .top_mask = IRQ_TOP_NVER_MASK,
240 .top_shift = IRQ_TOP_NVER_SHIFT,
241 .cache_idx = -1,
242 },
243};
244
245/* MAX77663 PMU doesn't allow PWR_OFF and SFT_RST setting in ONOFF_CFG1
246 * at the same time. So if it try to set PWR_OFF and SFT_RST to ONOFF_CFG1
247 * simultaneously, handle only SFT_RST and ignore PWR_OFF.
248 */
249#define CHECK_ONOFF_CFG1_MASK (ONOFF_SFT_RST_MASK | ONOFF_PWR_OFF_MASK)
250#define CHECK_ONOFF_CFG1(_addr, _val) \
251 unlikely((_addr == MAX77663_REG_ONOFF_CFG1) && \
252 ((_val & CHECK_ONOFF_CFG1_MASK) == CHECK_ONOFF_CFG1_MASK))
253
254static inline int max77663_i2c_write(struct i2c_client *client, u8 addr,
255 void *src, u32 bytes)
256{
257 u8 buf[bytes + 1];
258 int ret;
259
260 dev_dbg(&client->dev, "i2c_write: addr=0x%02x, src=0x%02x, bytes=%u\n",
261 addr, *((u8 *)src), bytes);
262
263 if (client->addr == max77663_chip->rtc_i2c_addr) {
264 /* RTC registers support sequential writing */
265 buf[0] = addr;
266 memcpy(&buf[1], src, bytes);
267 } else {
268 /* Power registers support register-data pair writing */
269 u8 *src8 = (u8 *)src;
270 int i;
271
272 for (i = 0; i < (bytes * 2); i++) {
273 if (i % 2) {
274 if (CHECK_ONOFF_CFG1(buf[i - 1], *src8))
275 buf[i] = *src8++ & ~ONOFF_PWR_OFF_MASK;
276 else
277 buf[i] = *src8++;
278 } else {
279 buf[i] = addr++;
280 }
281 }
282 bytes = (bytes * 2) - 1;
283 }
284
285 ret = i2c_master_send(client, buf, bytes + 1);
286 if (ret < 0)
287 return ret;
288 return 0;
289}
290
291static inline int max77663_i2c_read(struct i2c_client *client, u8 addr,
292 void *dest, u32 bytes)
293{
294 int ret;
295
296 if (bytes > 1) {
297 ret = i2c_smbus_read_i2c_block_data(client, addr, bytes, dest);
298 if (ret < 0)
299 return ret;
300 } else {
301 ret = i2c_smbus_read_byte_data(client, addr);
302 if (ret < 0)
303 return ret;
304
305 *((u8 *)dest) = (u8)ret;
306 }
307
308 dev_dbg(&client->dev, "i2c_read: addr=0x%02x, dest=0x%02x, bytes=%u\n",
309 addr, *((u8 *)dest), bytes);
310 return 0;
311}
312
313int max77663_read(struct device *dev, u8 addr, void *values, u32 len,
314 bool is_rtc)
315{
316 struct max77663_chip *chip = dev_get_drvdata(dev);
317 struct i2c_client *client = NULL;
318 int ret;
319
320 mutex_lock(&chip->io_lock);
321 if (!is_rtc)
322 client = chip->i2c_power;
323 else
324 client = chip->i2c_rtc;
325
326 ret = max77663_i2c_read(client, addr, values, len);
327 mutex_unlock(&chip->io_lock);
328 return ret;
329}
330EXPORT_SYMBOL(max77663_read);
331
332int max77663_write(struct device *dev, u8 addr, void *values, u32 len,
333 bool is_rtc)
334{
335 struct max77663_chip *chip = dev_get_drvdata(dev);
336 struct i2c_client *client = NULL;
337 int ret;
338
339 mutex_lock(&chip->io_lock);
340 if (!is_rtc)
341 client = chip->i2c_power;
342 else
343 client = chip->i2c_rtc;
344
345 ret = max77663_i2c_write(client, addr, values, len);
346 mutex_unlock(&chip->io_lock);
347 return ret;
348}
349EXPORT_SYMBOL(max77663_write);
350
351int max77663_set_bits(struct device *dev, u8 addr, u8 mask, u8 value,
352 bool is_rtc)
353{
354 struct max77663_chip *chip = dev_get_drvdata(dev);
355 struct i2c_client *client = NULL;
356 u8 tmp;
357 int ret;
358
359 mutex_lock(&chip->io_lock);
360 if (!is_rtc)
361 client = chip->i2c_power;
362 else
363 client = chip->i2c_rtc;
364
365 ret = max77663_i2c_read(client, addr, &tmp, 1);
366 if (ret == 0) {
367 value = (tmp & ~mask) | (value & mask);
368 ret = max77663_i2c_write(client, addr, &value, 1);
369 }
370 mutex_unlock(&chip->io_lock);
371 return ret;
372}
373EXPORT_SYMBOL(max77663_set_bits);
374
375static void max77663_power_off(void)
376{
377 struct max77663_chip *chip = max77663_chip;
378
379 if (!chip)
380 return;
381
382 dev_info(chip->dev, "%s: Global shutdown\n", __func__);
383 max77663_set_bits(chip->dev, MAX77663_REG_ONOFF_CFG1,
384 ONOFF_SFT_RST_MASK, ONOFF_SFT_RST_MASK, 0);
385}
386
387static int max77663_sleep(struct max77663_chip *chip, bool on)
388{
389 int ret = 0;
390
391 if (chip->pdata->flags & SLP_LPM_ENABLE) {
392 /* Put the power rails into Low-Power mode during sleep mode,
393 * if the power rail's power mode is GLPM. */
394 ret = max77663_set_bits(chip->dev, MAX77663_REG_ONOFF_CFG2,
395 ONOFF_SLP_LPM_MASK,
396 on ? ONOFF_SLP_LPM_MASK : 0, 0);
397 if (ret < 0)
398 return ret;
399 }
400
401 /* Enable sleep that AP can be placed into sleep mode
402 * by pulling EN1 low */
403 return max77663_set_bits(chip->dev, MAX77663_REG_ONOFF_CFG1,
404 ONOFF_SLPEN_MASK,
405 on ? ONOFF_SLPEN_MASK : 0, 0);
406}
407
408static inline int max77663_cache_write(struct device *dev, u8 addr, u8 mask,
409 u8 val, u8 *cache)
410{
411 u8 new_val;
412 int ret;
413
414 new_val = (*cache & ~mask) | (val & mask);
415 if (*cache != new_val) {
416 ret = max77663_write(dev, addr, &new_val, 1, 0);
417 if (ret < 0)
418 return ret;
419 *cache = new_val;
420 }
421 return 0;
422}
423
424static inline
425struct max77663_chip *max77663_chip_from_gpio(struct gpio_chip *gpio)
426{
427 return container_of(gpio, struct max77663_chip, gpio);
428}
429
430static int max77663_gpio_set_pull_up(struct max77663_chip *chip, int offset,
431 int pull_up)
432{
433 u8 val = 0;
434
435 if ((offset < MAX77663_GPIO0) || (MAX77663_GPIO7 < offset))
436 return -EINVAL;
437
438 if (pull_up == GPIO_PU_ENABLE)
439 val = (1 << offset);
440
441 return max77663_cache_write(chip->dev, MAX77663_REG_GPIO_PU,
442 (1 << offset), val, &chip->cache_gpio_pu);
443}
444
445static int max77663_gpio_set_pull_down(struct max77663_chip *chip, int offset,
446 int pull_down)
447{
448 u8 val = 0;
449
450 if ((offset < MAX77663_GPIO0) || (MAX77663_GPIO7 < offset))
451 return -EINVAL;
452
453 if (pull_down == GPIO_PD_ENABLE)
454 val = (1 << offset);
455
456 return max77663_cache_write(chip->dev, MAX77663_REG_GPIO_PD,
457 (1 << offset), val, &chip->cache_gpio_pd);
458}
459
460static inline
461int max77663_gpio_is_alternate(struct max77663_chip *chip, int offset)
462{
463 return (chip->cache_gpio_alt & (1 << offset)) ? 1 : 0;
464}
465
466int max77663_gpio_set_alternate(int gpio, int alternate)
467{
468 struct max77663_chip *chip = max77663_chip;
469 u8 val = 0;
470 int ret = 0;
471
472 if (!chip)
473 return -ENXIO;
474
475 gpio -= chip->gpio_base;
476 if ((gpio < MAX77663_GPIO0) || (MAX77663_GPIO7 < gpio))
477 return -EINVAL;
478
479 if (alternate == GPIO_ALT_ENABLE) {
480 val = (1 << gpio);
481 if (gpio == MAX77663_GPIO7) {
482 ret = max77663_gpio_set_pull_up(chip, gpio, 0);
483 if (ret < 0)
484 return ret;
485
486 ret = max77663_gpio_set_pull_down(chip, gpio, 0);
487 if (ret < 0)
488 return ret;
489 }
490 }
491
492 return max77663_cache_write(chip->dev, MAX77663_REG_GPIO_ALT,
493 (1 << gpio), val, &chip->cache_gpio_alt);
494}
495EXPORT_SYMBOL(max77663_gpio_set_alternate);
496
497static int max77663_gpio_dir_input(struct gpio_chip *gpio, unsigned offset)
498{
499 struct max77663_chip *chip = max77663_chip_from_gpio(gpio);
500
501 if (max77663_gpio_is_alternate(chip, offset)) {
502 dev_warn(chip->dev, "gpio_dir_input: "
503 "gpio%u is used as alternate mode\n", offset);
504 return 0;
505 }
506
507 return max77663_cache_write(chip->dev, GPIO_REG_ADDR(offset),
508 GPIO_CTRL_DIR_MASK, GPIO_CTRL_DIR_MASK,
509 &chip->cache_gpio_ctrl[offset]);
510}
511
512static int max77663_gpio_get(struct gpio_chip *gpio, unsigned offset)
513{
514 struct max77663_chip *chip = max77663_chip_from_gpio(gpio);
515 u8 val;
516 int ret;
517
518 if (max77663_gpio_is_alternate(chip, offset)) {
519 dev_warn(chip->dev, "gpio_get: "
520 "gpio%u is used as alternate mode\n", offset);
521 return 0;
522 }
523
524 ret = max77663_read(chip->dev, GPIO_REG_ADDR(offset), &val, 1, 0);
525 if (ret < 0)
526 return ret;
527
528 chip->cache_gpio_ctrl[offset] = val;
529 return (val & GPIO_CTRL_DIN_MASK) >> GPIO_CTRL_DIN_SHIFT;
530}
531
532static int max77663_gpio_dir_output(struct gpio_chip *gpio, unsigned offset,
533 int value)
534{
535 struct max77663_chip *chip = max77663_chip_from_gpio(gpio);
536 u8 mask = GPIO_CTRL_DIR_MASK | GPIO_CTRL_DOUT_MASK;
537 u8 val = (value ? 1 : 0) << GPIO_CTRL_DOUT_SHIFT;
538
539 if (max77663_gpio_is_alternate(chip, offset)) {
540 dev_warn(chip->dev, "gpio_dir_output: "
541 "gpio%u is used as alternate mode\n", offset);
542 return 0;
543 }
544
545 return max77663_cache_write(chip->dev, GPIO_REG_ADDR(offset), mask, val,
546 &chip->cache_gpio_ctrl[offset]);
547}
548
549static int max77663_gpio_set_debounce(struct gpio_chip *gpio, unsigned offset,
550 unsigned debounce)
551{
552 struct max77663_chip *chip = max77663_chip_from_gpio(gpio);
553 u8 shift = GPIO_CTRL_DBNC_SHIFT;
554 u8 val = 0;
555
556 if (max77663_gpio_is_alternate(chip, offset)) {
557 dev_warn(chip->dev, "gpio_set_debounce: "
558 "gpio%u is used as alternate mode\n", offset);
559 return 0;
560 }
561
562 if (debounce == 0)
563 val = 0;
564 else if ((0 < debounce) && (debounce <= 8))
565 val = (GPIO_DBNC_8MS << shift);
566 else if ((8 < debounce) && (debounce <= 16))
567 val = (GPIO_DBNC_16MS << shift);
568 else if ((16 < debounce) && (debounce <= 32))
569 val = (GPIO_DBNC_32MS << shift);
570 else
571 return -EINVAL;
572
573 return max77663_cache_write(chip->dev, GPIO_REG_ADDR(offset),
574 GPIO_CTRL_DBNC_MASK, val,
575 &chip->cache_gpio_ctrl[offset]);
576}
577
578static void max77663_gpio_set(struct gpio_chip *gpio, unsigned offset,
579 int value)
580{
581 struct max77663_chip *chip = max77663_chip_from_gpio(gpio);
582 u8 val = (value ? 1 : 0) << GPIO_CTRL_DOUT_SHIFT;
583
584 if (max77663_gpio_is_alternate(chip, offset)) {
585 dev_warn(chip->dev, "gpio_set: "
586 "gpio%u is used as alternate mode\n", offset);
587 return;
588 }
589
590 max77663_cache_write(chip->dev, GPIO_REG_ADDR(offset),
591 GPIO_CTRL_DOUT_MASK, val,
592 &chip->cache_gpio_ctrl[offset]);
593}
594
595static int max77663_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
596{
597 struct max77663_chip *chip = max77663_chip_from_gpio(gpio);
598
599 return chip->irq_base + IRQ_GPIO_BASE + offset;
600}
601
602#ifdef CONFIG_DEBUG_FS
603static void max77663_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gpio)
604{
605 struct max77663_chip *chip = max77663_chip_from_gpio(gpio);
606 int i;
607
608 for (i = 0; i < gpio->ngpio; i++) {
609 u8 ctrl_val;
610 const char *label;
611 int is_out;
612 int ret;
613
614 label = gpiochip_is_requested(gpio, i);
615 if (!label)
616 label = "Unrequested";
617
618 seq_printf(s, " gpio-%-3d (%-20.20s) ", i + chip->gpio_base,
619 label);
620
621 if (chip->cache_gpio_alt & (1 << i)) {
622 seq_printf(s, "alt\n");
623 continue;
624 }
625
626 ret = max77663_read(chip->dev, GPIO_REG_ADDR(i), &ctrl_val, 1,
627 0);
628 if (ret < 0) {
629 seq_printf(s, "\n");
630 continue;
631 }
632
633 is_out = ctrl_val & GPIO_CTRL_DIR_MASK ? 0 : 1;
634 seq_printf(s, "%s %s", (is_out ? "out" : "in"), (is_out ?
635 (ctrl_val & GPIO_CTRL_DOUT_MASK ? "hi" : "lo")
636 : (ctrl_val & GPIO_CTRL_DIN_MASK ? "hi" : "lo")));
637
638 if (!is_out) {
639 int irq = gpio_to_irq(i + chip->gpio_base);
640 struct irq_desc *desc = irq_to_desc(irq);
641 u8 dbnc;
642
643 if (irq >= 0 && desc->action) {
644 u8 mask = GPIO_CTRL_REFE_IRQ_MASK;
645 u8 shift = GPIO_CTRL_REFE_IRQ_SHIFT;
646 char *trigger;
647
648 switch ((ctrl_val & mask) >> shift) {
649 case GPIO_REFE_IRQ_EDGE_FALLING:
650 trigger = "edge-falling";
651 break;
652 case GPIO_REFE_IRQ_EDGE_RISING:
653 trigger = "edge-rising";
654 break;
655 case GPIO_REFE_IRQ_EDGE_BOTH:
656 trigger = "edge-both";
657 break;
658 default:
659 trigger = "masked";
660 break;
661 }
662
663 seq_printf(s, " irq-%d %s", irq, trigger);
664 }
665
666 dbnc = (ctrl_val & GPIO_CTRL_DBNC_MASK)
667 >> GPIO_CTRL_DBNC_SHIFT;
668 seq_printf(s, " debounce-%s",
669 dbnc == GPIO_DBNC_8MS ? "8ms" :
670 dbnc == GPIO_DBNC_16MS ? "16ms" :
671 dbnc == GPIO_DBNC_32MS ? "32ms" : "none");
672 } else {
673 seq_printf(s, " %s",
674 (ctrl_val & GPIO_CTRL_OUT_DRV_MASK ?
675 "output-drive" : "open-drain"));
676 }
677
678 seq_printf(s, "\n");
679 }
680}
681#else
682#define max77663_gpio_dbg_show NULL
683#endif /* CONFIG_DEBUG_FS */
684
685static int max77663_gpio_set_config(struct max77663_chip *chip,
686 struct max77663_gpio_config *gpio_cfg)
687{
688 int gpio = gpio_cfg->gpio;
689 u8 val = 0, mask = 0;
690 int ret = 0;
691
692 if ((gpio < MAX77663_GPIO0) || (MAX77663_GPIO7 < gpio))
693 return -EINVAL;
694
695 if (gpio_cfg->pull_up != GPIO_PU_DEF) {
696 ret = max77663_gpio_set_pull_up(chip, gpio, gpio_cfg->pull_up);
697 if (ret < 0) {
698 dev_err(chip->dev, "gpio_set_config: "
699 "Failed to set gpio%d pull-up\n", gpio);
700 return ret;
701 }
702 }
703
704 if (gpio_cfg->pull_down != GPIO_PD_DEF) {
705 ret = max77663_gpio_set_pull_down(chip, gpio,
706 gpio_cfg->pull_down);
707 if (ret < 0) {
708 dev_err(chip->dev, "gpio_set_config: "
709 "Failed to set gpio%d pull-down\n", gpio);
710 return ret;
711 }
712 }
713
714 if (gpio_cfg->dir != GPIO_DIR_DEF) {
715 mask = GPIO_CTRL_DIR_MASK;
716 if (gpio_cfg->dir == GPIO_DIR_IN) {
717 val |= GPIO_CTRL_DIR_MASK;
718 } else {
719 if (gpio_cfg->dout != GPIO_DOUT_DEF) {
720 mask |= GPIO_CTRL_DOUT_MASK;
721 if (gpio_cfg->dout == GPIO_DOUT_HIGH)
722 val |= GPIO_CTRL_DOUT_MASK;
723 }
724
725 if (gpio_cfg->out_drv != GPIO_OUT_DRV_DEF) {
726 mask |= GPIO_CTRL_OUT_DRV_MASK;
727 if (gpio_cfg->out_drv == GPIO_OUT_DRV_PUSH_PULL)
728 val |= GPIO_CTRL_OUT_DRV_MASK;
729 }
730 }
731
732 ret = max77663_cache_write(chip->dev, GPIO_REG_ADDR(gpio), mask,
733 val, &chip->cache_gpio_ctrl[gpio]);
734 if (ret < 0) {
735 dev_err(chip->dev, "gpio_set_config: "
736 "Failed to set gpio%d control\n", gpio);
737 return ret;
738 }
739 }
740
741 if (gpio_cfg->alternate != GPIO_ALT_DEF) {
742 ret = max77663_gpio_set_alternate(gpio + chip->gpio_base,
743 gpio_cfg->alternate);
744 if (ret < 0) {
745 dev_err(chip->dev, "gpio_set_config: "
746 "Failed to set gpio%d alternate\n", gpio);
747 return ret;
748 }
749 }
750
751 return 0;
752}
753
754static int max77663_gpio_init(struct max77663_chip *chip)
755{
756 int i;
757 int ret;
758
759 chip->gpio.label = chip->i2c_power->name;
760 chip->gpio.dev = chip->dev;
761 chip->gpio.owner = THIS_MODULE;
762 chip->gpio.direction_input = max77663_gpio_dir_input;
763 chip->gpio.get = max77663_gpio_get;
764 chip->gpio.direction_output = max77663_gpio_dir_output;
765 chip->gpio.set_debounce = max77663_gpio_set_debounce;
766 chip->gpio.set = max77663_gpio_set;
767 chip->gpio.to_irq = max77663_gpio_to_irq;
768 chip->gpio.dbg_show = max77663_gpio_dbg_show;
769 chip->gpio.ngpio = MAX77663_GPIO_NR;
770 chip->gpio.can_sleep = 1;
771 if (chip->gpio_base)
772 chip->gpio.base = chip->gpio_base;
773 else
774 chip->gpio.base = -1;
775
776 ret = max77663_read(chip->dev, MAX77663_REG_GPIO_CTRL0,
777 chip->cache_gpio_ctrl, MAX77663_GPIO_NR, 0);
778 if (ret < 0) {
779 dev_err(chip->dev, "gpio_init: Failed to get gpio control\n");
780 return ret;
781 }
782
783 ret = max77663_read(chip->dev, MAX77663_REG_GPIO_PU,
784 &chip->cache_gpio_pu, 1, 0);
785 if (ret < 0) {
786 dev_err(chip->dev, "gpio_init: Failed to get gpio pull-up\n");
787 return ret;
788 }
789
790 ret = max77663_read(chip->dev, MAX77663_REG_GPIO_PD,
791 &chip->cache_gpio_pd, 1, 0);
792 if (ret < 0) {
793 dev_err(chip->dev, "gpio_init: Failed to get gpio pull-down\n");
794 return ret;
795 }
796
797 ret = max77663_read(chip->dev, MAX77663_REG_GPIO_ALT,
798 &chip->cache_gpio_alt, 1, 0);
799 if (ret < 0) {
800 dev_err(chip->dev, "gpio_init: Failed to get gpio alternate\n");
801 return ret;
802 }
803
804 ret = gpiochip_add(&chip->gpio);
805 if (ret < 0) {
806 dev_err(chip->dev, "gpio_init: Failed to add gpiochip\n");
807 return ret;
808 }
809 chip->gpio_base = chip->gpio.base;
810
811 for (i = 0; i < chip->pdata->num_gpio_cfgs; i++) {
812 ret = max77663_gpio_set_config(chip,
813 &chip->pdata->gpio_cfgs[i]);
814 if (ret < 0) {
815 dev_err(chip->dev,
816 "gpio_init: Failed to set gpio config\n");
817 return ret;
818 }
819 }
820
821 return 0;
822}
823
824static void max77663_gpio_exit(struct max77663_chip *chip)
825{
826 if (gpiochip_remove(&chip->gpio) < 0)
827 dev_err(chip->dev, "gpio_exit: Failed to remove gpiochip\n");
828}
829
830static void max77663_irq_mask(struct irq_data *data)
831{
832 struct max77663_chip *chip = irq_data_get_irq_chip_data(data);
833
834 max77663_irqs[data->irq - chip->irq_base].is_unmask = 0;
835}
836
837static void max77663_irq_unmask(struct irq_data *data)
838{
839 struct max77663_chip *chip = irq_data_get_irq_chip_data(data);
840
841 max77663_irqs[data->irq - chip->irq_base].is_unmask = 1;
842}
843
844static void max77663_irq_lock(struct irq_data *data)
845{
846 struct max77663_chip *chip = irq_data_get_irq_chip_data(data);
847
848 mutex_lock(&chip->irq_lock);
849}
850
851static void max77663_irq_sync_unlock(struct irq_data *data)
852{
853 struct max77663_chip *chip = irq_data_get_irq_chip_data(data);
854 struct max77663_irq_data *irq_data =
855 &max77663_irqs[data->irq - chip->irq_base];
856 int idx = irq_data->cache_idx;
857 u8 irq_top_mask = chip->cache_irq_top_mask;
858 u16 irq_mask = chip->cache_irq_mask[idx];
859 int update_irq_top = 0;
860 u32 len = 1;
861 int ret;
862
863 if (irq_data->is_unmask) {
864 if (chip->irq_top_count[irq_data->top_shift] == 0)
865 update_irq_top = 1;
866 chip->irq_top_count[irq_data->top_shift]++;
867
868 if (irq_data->top_mask != IRQ_TOP_GLBL_MASK)
869 irq_top_mask &= ~irq_data->top_mask;
870
871 if (idx != -1)
872 irq_mask &= ~irq_data->mask;
873 } else {
874 if (chip->irq_top_count[irq_data->top_shift] == 1)
875 update_irq_top = 1;
876
877 if (--chip->irq_top_count[irq_data->top_shift] < 0)
878 chip->irq_top_count[irq_data->top_shift] = 0;
879
880 if (irq_data->top_mask != IRQ_TOP_GLBL_MASK)
881 irq_top_mask |= irq_data->top_mask;
882
883 if (idx != -1)
884 irq_mask |= irq_data->mask;
885 }
886
887 if ((idx != -1) && (irq_mask != chip->cache_irq_mask[idx])) {
888 if (irq_data->top_mask == IRQ_TOP_LDO_MASK)
889 len = 2;
890
891 ret = max77663_write(chip->dev, irq_data->mask_reg,
892 &irq_mask, len, irq_data->is_rtc);
893 if (ret < 0)
894 goto out;
895
896 chip->cache_irq_mask[idx] = irq_mask;
897 } else if ((idx == -1) && (irq_data->top_mask == IRQ_TOP_GPIO_MASK)) {
898 unsigned offset = data->irq - chip->irq_base - IRQ_GPIO_BASE;
899 u8 shift = GPIO_CTRL_REFE_IRQ_SHIFT;
900
901 if (irq_data->is_unmask) {
902 if (irq_data->trigger_type)
903 irq_mask = irq_data->trigger_type;
904 else
905 irq_mask = GPIO_REFE_IRQ_EDGE_FALLING << shift;
906 }
907
908 ret = max77663_cache_write(chip->dev, GPIO_REG_ADDR(offset),
909 GPIO_CTRL_REFE_IRQ_MASK, irq_mask,
910 &chip->cache_gpio_ctrl[offset]);
911 if (ret < 0)
912 goto out;
913
914 if (irq_data->is_unmask)
915 irq_data->trigger_type = irq_mask;
916 }
917
918 if (update_irq_top && (irq_top_mask != chip->cache_irq_top_mask)) {
919 ret = max77663_cache_write(chip->dev, MAX77663_REG_IRQ_TOP_MASK,
920 irq_data->top_mask, irq_top_mask,
921 &chip->cache_irq_top_mask);
922 if (ret < 0)
923 goto out;
924 }
925
926out:
927 mutex_unlock(&chip->irq_lock);
928}
929
930static int max77663_irq_gpio_set_type(struct irq_data *data, unsigned int type)
931{
932 struct max77663_chip *chip = irq_data_get_irq_chip_data(data);
933 struct max77663_irq_data *irq_data =
934 &max77663_irqs[data->irq - chip->irq_base];
935 unsigned offset = data->irq - chip->irq_base - IRQ_GPIO_BASE;
936 u8 shift = GPIO_CTRL_REFE_IRQ_SHIFT;
937 u8 val;
938
939 switch (type) {
940 case IRQ_TYPE_NONE:
941 case IRQ_TYPE_EDGE_FALLING:
942 val = (GPIO_REFE_IRQ_EDGE_FALLING << shift);
943 break;
944 case IRQ_TYPE_EDGE_RISING:
945 val = (GPIO_REFE_IRQ_EDGE_RISING << shift);
946 break;
947 case IRQ_TYPE_EDGE_BOTH:
948 val = (GPIO_REFE_IRQ_EDGE_BOTH << shift);
949 break;
950 default:
951 return -EINVAL;
952 }
953
954 irq_data->trigger_type = val;
955 if (!(chip->cache_gpio_ctrl[offset] & GPIO_CTRL_REFE_IRQ_MASK))
956 return 0;
957
958 return max77663_cache_write(chip->dev, GPIO_REG_ADDR(offset),
959 GPIO_CTRL_REFE_IRQ_MASK, val,
960 &chip->cache_gpio_ctrl[offset]);
961}
962
963static inline int max77663_do_irq(struct max77663_chip *chip, u8 addr,
964 int irq_base, int irq_end)
965{
966 struct max77663_irq_data *irq_data = NULL;
967 int irqs_to_handle[irq_end - irq_base + 1];
968 int handled = 0;
969 u16 val;
970 u32 len = 1;
971 int i;
972 int ret;
973
974 ret = max77663_read(chip->dev, addr, &val, len, 0);
975 if (ret < 0)
976 return ret;
977
978 for (i = irq_base; i <= irq_end; i++) {
979 irq_data = &max77663_irqs[i];
980 if (val & irq_data->mask) {
981 irqs_to_handle[handled] = i + chip->irq_base;
982 handled++;
983 }
984 }
985
986 for (i = 0; i < handled; i++)
987 handle_nested_irq(irqs_to_handle[i]);
988
989 return 0;
990}
991
992static irqreturn_t max77663_irq(int irq, void *data)
993{
994 struct max77663_chip *chip = data;
995 u8 irq_top;
996 int ret;
997
998 ret = max77663_read(chip->dev, MAX77663_REG_IRQ_TOP, &irq_top, 1, 0);
999 if (ret < 0) {
1000 dev_err(chip->dev, "irq: Failed to get irq top status\n");
1001 return IRQ_NONE;
1002 }
1003
1004 if (irq_top & IRQ_TOP_GLBL_MASK) {
1005 ret = max77663_do_irq(chip, MAX77663_REG_LBT_IRQ, IRQ_LBT_BASE,
1006 IRQ_LBT_END);
1007 if (ret < 0)
1008 return IRQ_NONE;
1009 }
1010
1011 if (irq_top & IRQ_TOP_GPIO_MASK) {
1012 ret = max77663_do_irq(chip, MAX77663_REG_GPIO_IRQ,
1013 IRQ_GPIO_BASE, IRQ_GPIO_END);
1014 if (ret < 0)
1015 return IRQ_NONE;
1016 }
1017
1018 if (irq_top & IRQ_TOP_ONOFF_MASK) {
1019 ret = max77663_do_irq(chip, MAX77663_REG_ONOFF_IRQ,
1020 IRQ_ONOFF_BASE, IRQ_ONOFF_END);
1021 if (ret < 0)
1022 return IRQ_NONE;
1023 }
1024
1025 if (irq_top & IRQ_TOP_RTC_MASK)
1026 handle_nested_irq(MAX77663_IRQ_RTC + chip->irq_base);
1027
1028 if (irq_top & IRQ_TOP_SD_MASK)
1029 handle_nested_irq(MAX77663_IRQ_SD_PF + chip->irq_base);
1030
1031 if (irq_top & IRQ_TOP_LDO_MASK)
1032 handle_nested_irq(MAX77663_IRQ_LDO_PF + chip->irq_base);
1033
1034 if (irq_top & IRQ_TOP_32K_MASK)
1035 handle_nested_irq(MAX77663_IRQ_32K + chip->irq_base);
1036
1037 if (irq_top & IRQ_TOP_NVER_MASK)
1038 handle_nested_irq(MAX77663_IRQ_NVER + chip->irq_base);
1039
1040 return IRQ_HANDLED;
1041}
1042
1043static struct irq_chip max77663_irq_gpio_chip = {
1044 .name = "max77663-irq",
1045 .irq_mask = max77663_irq_mask,
1046 .irq_unmask = max77663_irq_unmask,
1047 .irq_set_type = max77663_irq_gpio_set_type,
1048 .irq_bus_lock = max77663_irq_lock,
1049 .irq_bus_sync_unlock = max77663_irq_sync_unlock,
1050};
1051
1052static struct irq_chip max77663_irq_chip = {
1053 .name = "max77663-irq",
1054 .irq_mask = max77663_irq_mask,
1055 .irq_unmask = max77663_irq_unmask,
1056 .irq_bus_lock = max77663_irq_lock,
1057 .irq_bus_sync_unlock = max77663_irq_sync_unlock,
1058};
1059
1060static int max77663_irq_init(struct max77663_chip *chip)
1061{
1062 u32 temp;
1063 int i, ret = 0;
1064
1065 mutex_init(&chip->irq_lock);
1066
1067 /* Mask all interrupts */
1068 chip->cache_irq_top_mask = 0xFF;
1069 chip->cache_irq_mask[CACHE_IRQ_LBT] = 0x0F;
1070 chip->cache_irq_mask[CACHE_IRQ_SD] = 0xFF;
1071 chip->cache_irq_mask[CACHE_IRQ_LDO] = 0xFFFF;
1072 chip->cache_irq_mask[CACHE_IRQ_ONOFF] = 0xFF;
1073
1074 max77663_write(chip->dev, MAX77663_REG_IRQ_TOP_MASK,
1075 &chip->cache_irq_top_mask, 1, 0);
1076 max77663_write(chip->dev, MAX77663_REG_LBT_IRQ_MASK,
1077 &chip->cache_irq_mask[CACHE_IRQ_LBT], 1, 0);
1078 max77663_write(chip->dev, MAX77663_REG_SD_IRQ_MASK,
1079 &chip->cache_irq_mask[CACHE_IRQ_SD], 1, 0);
1080 max77663_write(chip->dev, MAX77663_REG_LDOX_IRQ_MASK,
1081 &chip->cache_irq_mask[CACHE_IRQ_LDO], 2, 0);
1082 max77663_write(chip->dev, MAX77663_REG_ONOFF_IRQ_MASK,
1083 &chip->cache_irq_mask[CACHE_IRQ_ONOFF], 1, 0);
1084
1085 /* Clear all interrups */
1086 max77663_read(chip->dev, MAX77663_REG_LBT_IRQ, &temp, 1, 0);
1087 max77663_read(chip->dev, MAX77663_REG_SD_IRQ, &temp, 1, 0);
1088 max77663_read(chip->dev, MAX77663_REG_LDOX_IRQ, &temp, 2, 0);
1089 max77663_read(chip->dev, MAX77663_REG_GPIO_IRQ, &temp, 1, 0);
1090 max77663_read(chip->dev, MAX77663_REG_ONOFF_IRQ, &temp, 1, 0);
1091
1092 for (i = chip->irq_base; i < (MAX77663_IRQ_NR + chip->irq_base); i++) {
1093 if (i >= NR_IRQS) {
1094 dev_err(chip->dev,
1095 "irq_init: Can't set irq chip for irq %d\n", i);
1096 continue;
1097 }
1098
1099 irq_set_chip_data(i, chip);
1100
1101 if ((IRQ_GPIO_BASE <= i - chip->irq_base) &&
1102 (i - chip->irq_base <= IRQ_GPIO_END))
1103 irq_set_chip_and_handler(i, &max77663_irq_gpio_chip,
1104 handle_edge_irq);
1105 else
1106 irq_set_chip_and_handler(i, &max77663_irq_chip,
1107 handle_edge_irq);
1108#ifdef CONFIG_ARM
1109 set_irq_flags(i, IRQF_VALID);
1110#else
1111 irq_set_noprobe(i);
1112#endif
1113 irq_set_nested_thread(i, 1);
1114 }
1115
1116 ret = request_threaded_irq(chip->i2c_power->irq, NULL, max77663_irq,
1117 IRQF_ONESHOT, "max77663", chip);
1118 if (ret) {
1119 dev_err(chip->dev, "irq_init: Failed to request irq %d\n",
1120 chip->i2c_power->irq);
1121 return ret;
1122 }
1123
1124 device_init_wakeup(chip->dev, 1);
1125 enable_irq_wake(chip->i2c_power->irq);
1126
1127 chip->cache_irq_top_mask &= ~IRQ_TOP_GLBL_MASK;
1128 max77663_write(chip->dev, MAX77663_REG_IRQ_TOP_MASK,
1129 &chip->cache_irq_top_mask, 1, 0);
1130
1131 chip->cache_irq_mask[CACHE_IRQ_LBT] &= ~IRQ_GLBL_MASK;
1132 max77663_write(chip->dev, MAX77663_REG_LBT_IRQ_MASK,
1133 &chip->cache_irq_mask[CACHE_IRQ_LBT], 1, 0);
1134
1135 return 0;
1136}
1137
1138static void max77663_irq_exit(struct max77663_chip *chip)
1139{
1140 if (chip->i2c_power->irq)
1141 free_irq(chip->i2c_power->irq, chip);
1142}
1143
1144#ifdef CONFIG_DEBUG_FS
1145static struct dentry *max77663_dentry_regs;
1146
1147static int max77663_debugfs_dump_regs(struct max77663_chip *chip, char *label,
1148 u8 *addrs, int num_addrs, char *buf,
1149 ssize_t *len, int is_rtc)
1150{
1151 ssize_t count = *len;
1152 u8 val;
1153 int ret = 0;
1154 int i;
1155
1156 count += sprintf(buf + count, "%s\n", label);
1157 if (count >= PAGE_SIZE - 1)
1158 return -ERANGE;
1159
1160 for (i = 0; i < num_addrs; i++) {
1161 count += sprintf(buf + count, "0x%02x: ", addrs[i]);
1162 if (count >= PAGE_SIZE - 1)
1163 return -ERANGE;
1164
1165 ret = max77663_read(chip->dev, addrs[i], &val, 1, is_rtc);
1166 if (ret == 0)
1167 count += sprintf(buf + count, "0x%02x\n", val);
1168 else
1169 count += sprintf(buf + count, "<read fail: %d>\n", ret);
1170
1171 if (count >= PAGE_SIZE - 1)
1172 return -ERANGE;
1173 }
1174
1175 *len = count;
1176 return 0;
1177}
1178
1179static int max77663_debugfs_regs_open(struct inode *inode, struct file *file)
1180{
1181 file->private_data = inode->i_private;
1182 return 0;
1183}
1184
1185static ssize_t max77663_debugfs_regs_read(struct file *file,
1186 char __user *user_buf,
1187 size_t count, loff_t *ppos)
1188{
1189 struct max77663_chip *chip = file->private_data;
1190 char *buf;
1191 size_t len = 0;
1192 ssize_t ret;
1193
1194 /* Excluded interrupt status register to prevent register clear */
1195 u8 global_regs[] = { 0x00, 0x01, 0x02, 0x05, 0x0D, 0x0E, 0x13 };
1196 u8 sd_regs[] = {
1197 0x07, 0x0F, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D,
1198 0x1E, 0x1F, 0x20, 0x21, 0x22
1199 };
1200 u8 ldo_regs[] = {
1201 0x10, 0x11, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A,
1202 0x2B, 0x2C, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x32, 0x33, 0x34,
1203 0x35
1204 };
1205 u8 gpio_regs[] = {
1206 0x36, 0x37, 0x38, 0x39, 0x3A, 0x3B, 0x3C, 0x3D, 0x3E, 0x3F,
1207 0x40
1208 };
1209 u8 rtc_regs[] = {
1210 0x01, 0x02, 0x03, 0x04, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B,
1211 0x0C, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
1212 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B
1213 };
1214 u8 osc_32k_regs[] = { 0x03 };
1215 u8 bbc_regs[] = { 0x04 };
1216 u8 onoff_regs[] = { 0x12, 0x15, 0x41, 0x42 };
1217 u8 fps_regs[] = {
1218 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C,
1219 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56,
1220 0x57
1221 };
1222 u8 cid_regs[] = { 0x58, 0x59, 0x5A, 0x5B, 0x5C, 0x5D };
1223
1224 buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
1225 if (!buf)
1226 return -ENOMEM;
1227
1228 len += sprintf(buf + len, "MAX77663 Registers\n");
1229 max77663_debugfs_dump_regs(chip, "[Global]", global_regs,
1230 ARRAY_SIZE(global_regs), buf, &len, 0);
1231 max77663_debugfs_dump_regs(chip, "[Step-Down]", sd_regs,
1232 ARRAY_SIZE(sd_regs), buf, &len, 0);
1233 max77663_debugfs_dump_regs(chip, "[LDO]", ldo_regs,
1234 ARRAY_SIZE(ldo_regs), buf, &len, 0);
1235 max77663_debugfs_dump_regs(chip, "[GPIO]", gpio_regs,
1236 ARRAY_SIZE(gpio_regs), buf, &len, 0);
1237 max77663_debugfs_dump_regs(chip, "[RTC]", rtc_regs,
1238 ARRAY_SIZE(rtc_regs), buf, &len, 1);
1239 max77663_debugfs_dump_regs(chip, "[32kHz Oscillator]", osc_32k_regs,
1240 ARRAY_SIZE(osc_32k_regs), buf, &len, 0);
1241 max77663_debugfs_dump_regs(chip, "[Backup Battery Charger]", bbc_regs,
1242 ARRAY_SIZE(bbc_regs), buf, &len, 0);
1243 max77663_debugfs_dump_regs(chip, "[On/OFF Controller]", onoff_regs,
1244 ARRAY_SIZE(onoff_regs), buf, &len, 0);
1245 max77663_debugfs_dump_regs(chip, "[Flexible Power Sequencer]", fps_regs,
1246 ARRAY_SIZE(fps_regs), buf, &len, 0);
1247 max77663_debugfs_dump_regs(chip, "[Chip Identification]", cid_regs,
1248 ARRAY_SIZE(cid_regs), buf, &len, 0);
1249
1250 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
1251 kfree(buf);
1252
1253 return ret;
1254}
1255
1256static const struct file_operations max77663_debugfs_regs_fops = {
1257 .open = max77663_debugfs_regs_open,
1258 .read = max77663_debugfs_regs_read,
1259};
1260
1261static void max77663_debugfs_init(struct max77663_chip *chip)
1262{
1263 max77663_dentry_regs = debugfs_create_file(chip->i2c_power->name,
1264 0444, 0, chip,
1265 &max77663_debugfs_regs_fops);
1266 if (!max77663_dentry_regs)
1267 dev_warn(chip->dev,
1268 "debugfs_init: Failed to create debugfs file\n");
1269}
1270
1271static void max77663_debugfs_exit(struct max77663_chip *chip)
1272{
1273 debugfs_remove(max77663_dentry_regs);
1274}
1275#else
1276static inline void max77663_debugfs_init(struct max77663_chip *chip)
1277{
1278}
1279
1280static inline void max77663_debugfs_exit(struct max77663_chip *chip)
1281{
1282}
1283#endif /* CONFIG_DEBUG_FS */
1284
1285static int max77663_probe(struct i2c_client *client,
1286 const struct i2c_device_id *id)
1287{
1288 struct max77663_platform_data *pdata = client->dev.platform_data;
1289 struct max77663_chip *chip;
1290 int ret = 0;
1291
1292 if (pdata == NULL) {
1293 dev_err(&client->dev, "probe: Invalid platform_data\n");
1294 ret = -ENODEV;
1295 goto out;
1296 }
1297
1298 chip = kzalloc(sizeof(struct max77663_chip), GFP_KERNEL);
1299 if (chip == NULL) {
1300 dev_err(&client->dev, "probe: kzalloc() failed\n");
1301 ret = -ENOMEM;
1302 goto out;
1303 }
1304 max77663_chip = chip;
1305
1306 chip->i2c_power = client;
1307 i2c_set_clientdata(client, chip);
1308
1309 if (pdata->rtc_i2c_addr)
1310 chip->rtc_i2c_addr = pdata->rtc_i2c_addr;
1311 else
1312 chip->rtc_i2c_addr = MAX77663_RTC_I2C_ADDR;
1313
1314 chip->i2c_rtc = i2c_new_dummy(client->adapter, chip->rtc_i2c_addr);
1315 i2c_set_clientdata(chip->i2c_rtc, chip);
1316
1317 chip->dev = &client->dev;
1318 chip->pdata = pdata;
1319 chip->irq_base = pdata->irq_base;
1320 chip->gpio_base = pdata->gpio_base;
1321 mutex_init(&chip->io_lock);
1322
1323 max77663_gpio_init(chip);
1324 max77663_irq_init(chip);
1325 max77663_debugfs_init(chip);
1326 ret = max77663_sleep(chip, false);
1327 if (ret < 0) {
1328 dev_err(&client->dev, "probe: Failed to disable sleep\n");
1329 goto out_exit;
1330 }
1331
1332 if (pdata->use_power_off && !pm_power_off)
1333 pm_power_off = max77663_power_off;
1334
1335 ret = mfd_add_devices(&client->dev, 0, pdata->sub_devices,
1336 pdata->num_subdevs, NULL, 0);
1337 if (ret != 0) {
1338 dev_err(&client->dev, "probe: Failed to add subdev: %d\n", ret);
1339 goto out_exit;
1340 }
1341
1342 return 0;
1343
1344out_exit:
1345 max77663_debugfs_exit(chip);
1346 max77663_gpio_exit(chip);
1347 max77663_irq_exit(chip);
1348 mutex_destroy(&chip->io_lock);
1349 max77663_chip = NULL;
1350 kfree(chip);
1351out:
1352 return ret;
1353}
1354
1355static int __devexit max77663_remove(struct i2c_client *client)
1356{
1357 struct max77663_chip *chip = i2c_get_clientdata(client);
1358
1359 mfd_remove_devices(chip->dev);
1360 max77663_debugfs_exit(chip);
1361 max77663_irq_exit(chip);
1362 max77663_gpio_exit(chip);
1363 mutex_destroy(&chip->io_lock);
1364 max77663_chip = NULL;
1365 kfree(chip);
1366
1367 return 0;
1368}
1369
1370#ifdef CONFIG_PM
1371static int max77663_suspend(struct device *dev)
1372{
1373 struct i2c_client *client = to_i2c_client(dev);
1374 struct max77663_chip *chip = i2c_get_clientdata(client);
1375 int ret;
1376
1377 if (client->irq)
1378 disable_irq(client->irq);
1379
1380 ret = max77663_sleep(chip, true);
1381 if (ret < 0)
1382 dev_err(dev, "suspend: Failed to enable sleep\n");
1383
1384 return ret;
1385}
1386
1387static int max77663_resume(struct device *dev)
1388{
1389 struct i2c_client *client = to_i2c_client(dev);
1390 struct max77663_chip *chip = i2c_get_clientdata(client);
1391 int ret;
1392
1393 ret = max77663_sleep(chip, false);
1394 if (ret < 0) {
1395 dev_err(dev, "resume: Failed to disable sleep\n");
1396 return ret;
1397 }
1398
1399 if (client->irq)
1400 enable_irq(client->irq);
1401
1402 return 0;
1403}
1404#else
1405#define max77663_suspend NULL
1406#define max77663_resume NULL
1407#endif /* CONFIG_PM */
1408
1409static const struct i2c_device_id max77663_id[] = {
1410 {"max77663", 0},
1411 {},
1412};
1413MODULE_DEVICE_TABLE(i2c, max77663_id);
1414
1415static const struct dev_pm_ops max77663_pm = {
1416 .suspend = max77663_suspend,
1417 .resume = max77663_resume,
1418};
1419
1420static struct i2c_driver max77663_driver = {
1421 .driver = {
1422 .name = "max77663",
1423 .owner = THIS_MODULE,
1424 .pm = &max77663_pm,
1425 },
1426 .probe = max77663_probe,
1427 .remove = __devexit_p(max77663_remove),
1428 .id_table = max77663_id,
1429};
1430
1431static int __init max77663_init(void)
1432{
1433 return i2c_add_driver(&max77663_driver);
1434}
1435subsys_initcall(max77663_init);
1436
1437static void __exit max77663_exit(void)
1438{
1439 i2c_del_driver(&max77663_driver);
1440}
1441module_exit(max77663_exit);
1442
1443MODULE_LICENSE("GPL v2");
1444MODULE_DESCRIPTION("MAX77663 Multi Function Device Core Driver");
1445MODULE_VERSION("1.0");
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 07:17:24 -0400