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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /drivers/media/video/s5p-fimc
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'drivers/media/video/s5p-fimc')
-rw-r--r--drivers/media/video/s5p-fimc/Makefile5
-rw-r--r--drivers/media/video/s5p-fimc/fimc-capture.c901
-rw-r--r--drivers/media/video/s5p-fimc/fimc-core.c1938
-rw-r--r--drivers/media/video/s5p-fimc/fimc-core.h707
-rw-r--r--drivers/media/video/s5p-fimc/fimc-reg.c685
-rw-r--r--drivers/media/video/s5p-fimc/mipi-csis.c724
-rw-r--r--drivers/media/video/s5p-fimc/mipi-csis.h22
-rw-r--r--drivers/media/video/s5p-fimc/regs-fimc.h297
8 files changed, 5279 insertions, 0 deletions
diff --git a/drivers/media/video/s5p-fimc/Makefile b/drivers/media/video/s5p-fimc/Makefile
new file mode 100644
index 00000000000..df6954ab1d9
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/Makefile
@@ -0,0 +1,5 @@
1s5p-fimc-objs := fimc-core.o fimc-reg.o fimc-capture.o
2s5p-csis-objs := mipi-csis.o
3
4obj-$(CONFIG_VIDEO_S5P_MIPI_CSIS) += s5p-csis.o
5obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) += s5p-fimc.o
diff --git a/drivers/media/video/s5p-fimc/fimc-capture.c b/drivers/media/video/s5p-fimc/fimc-capture.c
new file mode 100644
index 00000000000..0d730e55605
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/fimc-capture.c
@@ -0,0 +1,901 @@
1/*
2 * Samsung S5P/EXYNOS4 SoC series camera interface (camera capture) driver
3 *
4 * Copyright (C) 2010 - 2011 Samsung Electronics Co., Ltd.
5 * Author: Sylwester Nawrocki, <s.nawrocki@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/errno.h>
16#include <linux/bug.h>
17#include <linux/interrupt.h>
18#include <linux/device.h>
19#include <linux/platform_device.h>
20#include <linux/list.h>
21#include <linux/slab.h>
22#include <linux/clk.h>
23#include <linux/i2c.h>
24
25#include <linux/videodev2.h>
26#include <media/v4l2-device.h>
27#include <media/v4l2-ioctl.h>
28#include <media/v4l2-mem2mem.h>
29#include <media/videobuf2-core.h>
30#include <media/videobuf2-dma-contig.h>
31
32#include "fimc-core.h"
33
34static struct v4l2_subdev *fimc_subdev_register(struct fimc_dev *fimc,
35 struct s5p_fimc_isp_info *isp_info)
36{
37 struct i2c_adapter *i2c_adap;
38 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
39 struct v4l2_subdev *sd = NULL;
40
41 i2c_adap = i2c_get_adapter(isp_info->i2c_bus_num);
42 if (!i2c_adap)
43 return ERR_PTR(-ENOMEM);
44
45 sd = v4l2_i2c_new_subdev_board(&vid_cap->v4l2_dev, i2c_adap,
46 isp_info->board_info, NULL);
47 if (!sd) {
48 v4l2_err(&vid_cap->v4l2_dev, "failed to acquire subdev\n");
49 return NULL;
50 }
51
52 v4l2_info(&vid_cap->v4l2_dev, "subdevice %s registered successfuly\n",
53 isp_info->board_info->type);
54
55 return sd;
56}
57
58static void fimc_subdev_unregister(struct fimc_dev *fimc)
59{
60 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
61 struct i2c_client *client;
62
63 if (vid_cap->input_index < 0)
64 return; /* Subdevice already released or not registered. */
65
66 if (vid_cap->sd) {
67 v4l2_device_unregister_subdev(vid_cap->sd);
68 client = v4l2_get_subdevdata(vid_cap->sd);
69 i2c_unregister_device(client);
70 i2c_put_adapter(client->adapter);
71 vid_cap->sd = NULL;
72 }
73
74 vid_cap->input_index = -1;
75}
76
77/**
78 * fimc_subdev_attach - attach v4l2_subdev to camera host interface
79 *
80 * @fimc: FIMC device information
81 * @index: index to the array of available subdevices,
82 * -1 for full array search or non negative value
83 * to select specific subdevice
84 */
85static int fimc_subdev_attach(struct fimc_dev *fimc, int index)
86{
87 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
88 struct s5p_platform_fimc *pdata = fimc->pdata;
89 struct s5p_fimc_isp_info *isp_info;
90 struct v4l2_subdev *sd;
91 int i;
92
93 for (i = 0; i < pdata->num_clients; ++i) {
94 isp_info = &pdata->isp_info[i];
95
96 if (index >= 0 && i != index)
97 continue;
98
99 sd = fimc_subdev_register(fimc, isp_info);
100 if (!IS_ERR_OR_NULL(sd)) {
101 vid_cap->sd = sd;
102 vid_cap->input_index = i;
103
104 return 0;
105 }
106 }
107
108 vid_cap->input_index = -1;
109 vid_cap->sd = NULL;
110 v4l2_err(&vid_cap->v4l2_dev, "fimc%d: sensor attach failed\n",
111 fimc->id);
112 return -ENODEV;
113}
114
115static int fimc_isp_subdev_init(struct fimc_dev *fimc, unsigned int index)
116{
117 struct s5p_fimc_isp_info *isp_info;
118 struct s5p_platform_fimc *pdata = fimc->pdata;
119 int ret;
120
121 if (index >= pdata->num_clients)
122 return -EINVAL;
123
124 isp_info = &pdata->isp_info[index];
125
126 if (isp_info->clk_frequency)
127 clk_set_rate(fimc->clock[CLK_CAM], isp_info->clk_frequency);
128
129 ret = clk_enable(fimc->clock[CLK_CAM]);
130 if (ret)
131 return ret;
132
133 ret = fimc_subdev_attach(fimc, index);
134 if (ret)
135 return ret;
136
137 ret = fimc_hw_set_camera_polarity(fimc, isp_info);
138 if (ret)
139 return ret;
140
141 ret = v4l2_subdev_call(fimc->vid_cap.sd, core, s_power, 1);
142 if (!ret)
143 return ret;
144
145 /* enabling power failed so unregister subdev */
146 fimc_subdev_unregister(fimc);
147
148 v4l2_err(&fimc->vid_cap.v4l2_dev, "ISP initialization failed: %d\n",
149 ret);
150
151 return ret;
152}
153
154static int fimc_stop_capture(struct fimc_dev *fimc)
155{
156 unsigned long flags;
157 struct fimc_vid_cap *cap;
158 struct fimc_vid_buffer *buf;
159
160 cap = &fimc->vid_cap;
161
162 if (!fimc_capture_active(fimc))
163 return 0;
164
165 spin_lock_irqsave(&fimc->slock, flags);
166 set_bit(ST_CAPT_SHUT, &fimc->state);
167 fimc_deactivate_capture(fimc);
168 spin_unlock_irqrestore(&fimc->slock, flags);
169
170 wait_event_timeout(fimc->irq_queue,
171 !test_bit(ST_CAPT_SHUT, &fimc->state),
172 FIMC_SHUTDOWN_TIMEOUT);
173
174 v4l2_subdev_call(cap->sd, video, s_stream, 0);
175
176 spin_lock_irqsave(&fimc->slock, flags);
177 fimc->state &= ~(1 << ST_CAPT_RUN | 1 << ST_CAPT_PEND |
178 1 << ST_CAPT_SHUT | 1 << ST_CAPT_STREAM);
179
180 fimc->vid_cap.active_buf_cnt = 0;
181
182 /* Release buffers that were enqueued in the driver by videobuf2. */
183 while (!list_empty(&cap->pending_buf_q)) {
184 buf = pending_queue_pop(cap);
185 vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
186 }
187
188 while (!list_empty(&cap->active_buf_q)) {
189 buf = active_queue_pop(cap);
190 vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
191 }
192
193 spin_unlock_irqrestore(&fimc->slock, flags);
194
195 dbg("state: 0x%lx", fimc->state);
196 return 0;
197}
198
199static int start_streaming(struct vb2_queue *q)
200{
201 struct fimc_ctx *ctx = q->drv_priv;
202 struct fimc_dev *fimc = ctx->fimc_dev;
203 struct s5p_fimc_isp_info *isp_info;
204 int ret;
205
206 fimc_hw_reset(fimc);
207
208 ret = v4l2_subdev_call(fimc->vid_cap.sd, video, s_stream, 1);
209 if (ret && ret != -ENOIOCTLCMD)
210 return ret;
211
212 ret = fimc_prepare_config(ctx, ctx->state);
213 if (ret)
214 return ret;
215
216 isp_info = &fimc->pdata->isp_info[fimc->vid_cap.input_index];
217 fimc_hw_set_camera_type(fimc, isp_info);
218 fimc_hw_set_camera_source(fimc, isp_info);
219 fimc_hw_set_camera_offset(fimc, &ctx->s_frame);
220
221 if (ctx->state & FIMC_PARAMS) {
222 ret = fimc_set_scaler_info(ctx);
223 if (ret) {
224 err("Scaler setup error");
225 return ret;
226 }
227 fimc_hw_set_input_path(ctx);
228 fimc_hw_set_prescaler(ctx);
229 fimc_hw_set_mainscaler(ctx);
230 fimc_hw_set_target_format(ctx);
231 fimc_hw_set_rotation(ctx);
232 fimc_hw_set_effect(ctx);
233 }
234
235 fimc_hw_set_output_path(ctx);
236 fimc_hw_set_out_dma(ctx);
237
238 INIT_LIST_HEAD(&fimc->vid_cap.pending_buf_q);
239 INIT_LIST_HEAD(&fimc->vid_cap.active_buf_q);
240 fimc->vid_cap.active_buf_cnt = 0;
241 fimc->vid_cap.frame_count = 0;
242 fimc->vid_cap.buf_index = 0;
243
244 set_bit(ST_CAPT_PEND, &fimc->state);
245
246 return 0;
247}
248
249static int stop_streaming(struct vb2_queue *q)
250{
251 struct fimc_ctx *ctx = q->drv_priv;
252 struct fimc_dev *fimc = ctx->fimc_dev;
253
254 if (!fimc_capture_active(fimc))
255 return -EINVAL;
256
257 return fimc_stop_capture(fimc);
258}
259
260static unsigned int get_plane_size(struct fimc_frame *fr, unsigned int plane)
261{
262 if (!fr || plane >= fr->fmt->memplanes)
263 return 0;
264 return fr->f_width * fr->f_height * fr->fmt->depth[plane] / 8;
265}
266
267static int queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
268 unsigned int *num_planes, unsigned long sizes[],
269 void *allocators[])
270{
271 struct fimc_ctx *ctx = vq->drv_priv;
272 struct fimc_fmt *fmt = ctx->d_frame.fmt;
273 int i;
274
275 if (!fmt)
276 return -EINVAL;
277
278 *num_planes = fmt->memplanes;
279
280 for (i = 0; i < fmt->memplanes; i++) {
281 sizes[i] = get_plane_size(&ctx->d_frame, i);
282 allocators[i] = ctx->fimc_dev->alloc_ctx;
283 }
284
285 return 0;
286}
287
288static int buffer_prepare(struct vb2_buffer *vb)
289{
290 struct vb2_queue *vq = vb->vb2_queue;
291 struct fimc_ctx *ctx = vq->drv_priv;
292 struct v4l2_device *v4l2_dev = &ctx->fimc_dev->m2m.v4l2_dev;
293 int i;
294
295 if (!ctx->d_frame.fmt || vq->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
296 return -EINVAL;
297
298 for (i = 0; i < ctx->d_frame.fmt->memplanes; i++) {
299 unsigned long size = get_plane_size(&ctx->d_frame, i);
300
301 if (vb2_plane_size(vb, i) < size) {
302 v4l2_err(v4l2_dev, "User buffer too small (%ld < %ld)\n",
303 vb2_plane_size(vb, i), size);
304 return -EINVAL;
305 }
306
307 vb2_set_plane_payload(vb, i, size);
308 }
309
310 return 0;
311}
312
313static void buffer_queue(struct vb2_buffer *vb)
314{
315 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
316 struct fimc_dev *fimc = ctx->fimc_dev;
317 struct fimc_vid_buffer *buf
318 = container_of(vb, struct fimc_vid_buffer, vb);
319 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
320 unsigned long flags;
321 int min_bufs;
322
323 spin_lock_irqsave(&fimc->slock, flags);
324 fimc_prepare_addr(ctx, &buf->vb, &ctx->d_frame, &buf->paddr);
325
326 if (!test_bit(ST_CAPT_STREAM, &fimc->state)
327 && vid_cap->active_buf_cnt < FIMC_MAX_OUT_BUFS) {
328 /* Setup the buffer directly for processing. */
329 int buf_id = (vid_cap->reqbufs_count == 1) ? -1 :
330 vid_cap->buf_index;
331
332 fimc_hw_set_output_addr(fimc, &buf->paddr, buf_id);
333 buf->index = vid_cap->buf_index;
334 active_queue_add(vid_cap, buf);
335
336 if (++vid_cap->buf_index >= FIMC_MAX_OUT_BUFS)
337 vid_cap->buf_index = 0;
338 } else {
339 fimc_pending_queue_add(vid_cap, buf);
340 }
341
342 min_bufs = vid_cap->reqbufs_count > 1 ? 2 : 1;
343
344 if (vid_cap->active_buf_cnt >= min_bufs &&
345 !test_and_set_bit(ST_CAPT_STREAM, &fimc->state))
346 fimc_activate_capture(ctx);
347
348 spin_unlock_irqrestore(&fimc->slock, flags);
349}
350
351static void fimc_lock(struct vb2_queue *vq)
352{
353 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
354 mutex_lock(&ctx->fimc_dev->lock);
355}
356
357static void fimc_unlock(struct vb2_queue *vq)
358{
359 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
360 mutex_unlock(&ctx->fimc_dev->lock);
361}
362
363static struct vb2_ops fimc_capture_qops = {
364 .queue_setup = queue_setup,
365 .buf_prepare = buffer_prepare,
366 .buf_queue = buffer_queue,
367 .wait_prepare = fimc_unlock,
368 .wait_finish = fimc_lock,
369 .start_streaming = start_streaming,
370 .stop_streaming = stop_streaming,
371};
372
373static int fimc_capture_open(struct file *file)
374{
375 struct fimc_dev *fimc = video_drvdata(file);
376 int ret = 0;
377
378 dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state);
379
380 /* Return if the corresponding video mem2mem node is already opened. */
381 if (fimc_m2m_active(fimc))
382 return -EBUSY;
383
384 if (++fimc->vid_cap.refcnt == 1) {
385 ret = fimc_isp_subdev_init(fimc, 0);
386 if (ret) {
387 fimc->vid_cap.refcnt--;
388 return -EIO;
389 }
390 }
391
392 file->private_data = fimc->vid_cap.ctx;
393
394 return 0;
395}
396
397static int fimc_capture_close(struct file *file)
398{
399 struct fimc_dev *fimc = video_drvdata(file);
400
401 dbg("pid: %d, state: 0x%lx", task_pid_nr(current), fimc->state);
402
403 if (--fimc->vid_cap.refcnt == 0) {
404 fimc_stop_capture(fimc);
405 vb2_queue_release(&fimc->vid_cap.vbq);
406
407 v4l2_err(&fimc->vid_cap.v4l2_dev, "releasing ISP\n");
408
409 v4l2_subdev_call(fimc->vid_cap.sd, core, s_power, 0);
410 clk_disable(fimc->clock[CLK_CAM]);
411 fimc_subdev_unregister(fimc);
412 }
413
414 return 0;
415}
416
417static unsigned int fimc_capture_poll(struct file *file,
418 struct poll_table_struct *wait)
419{
420 struct fimc_ctx *ctx = file->private_data;
421 struct fimc_dev *fimc = ctx->fimc_dev;
422
423 return vb2_poll(&fimc->vid_cap.vbq, file, wait);
424}
425
426static int fimc_capture_mmap(struct file *file, struct vm_area_struct *vma)
427{
428 struct fimc_ctx *ctx = file->private_data;
429 struct fimc_dev *fimc = ctx->fimc_dev;
430
431 return vb2_mmap(&fimc->vid_cap.vbq, vma);
432}
433
434/* video device file operations */
435static const struct v4l2_file_operations fimc_capture_fops = {
436 .owner = THIS_MODULE,
437 .open = fimc_capture_open,
438 .release = fimc_capture_close,
439 .poll = fimc_capture_poll,
440 .unlocked_ioctl = video_ioctl2,
441 .mmap = fimc_capture_mmap,
442};
443
444static int fimc_vidioc_querycap_capture(struct file *file, void *priv,
445 struct v4l2_capability *cap)
446{
447 struct fimc_ctx *ctx = file->private_data;
448 struct fimc_dev *fimc = ctx->fimc_dev;
449
450 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
451 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
452 cap->bus_info[0] = 0;
453 cap->capabilities = V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_CAPTURE |
454 V4L2_CAP_VIDEO_CAPTURE_MPLANE;
455
456 return 0;
457}
458
459/* Synchronize formats of the camera interface input and attached sensor. */
460static int sync_capture_fmt(struct fimc_ctx *ctx)
461{
462 struct fimc_frame *frame = &ctx->s_frame;
463 struct fimc_dev *fimc = ctx->fimc_dev;
464 struct v4l2_mbus_framefmt *fmt = &fimc->vid_cap.fmt;
465 int ret;
466
467 fmt->width = ctx->d_frame.o_width;
468 fmt->height = ctx->d_frame.o_height;
469
470 ret = v4l2_subdev_call(fimc->vid_cap.sd, video, s_mbus_fmt, fmt);
471 if (ret == -ENOIOCTLCMD) {
472 err("s_mbus_fmt failed");
473 return ret;
474 }
475 dbg("w: %d, h: %d, code= %d", fmt->width, fmt->height, fmt->code);
476
477 frame->fmt = find_mbus_format(fmt, FMT_FLAGS_CAM);
478 if (!frame->fmt) {
479 err("fimc source format not found\n");
480 return -EINVAL;
481 }
482
483 frame->f_width = fmt->width;
484 frame->f_height = fmt->height;
485 frame->width = fmt->width;
486 frame->height = fmt->height;
487 frame->o_width = fmt->width;
488 frame->o_height = fmt->height;
489 frame->offs_h = 0;
490 frame->offs_v = 0;
491
492 return 0;
493}
494
495static int fimc_cap_s_fmt_mplane(struct file *file, void *priv,
496 struct v4l2_format *f)
497{
498 struct fimc_ctx *ctx = priv;
499 struct fimc_dev *fimc = ctx->fimc_dev;
500 struct fimc_frame *frame;
501 struct v4l2_pix_format_mplane *pix;
502 int ret;
503 int i;
504
505 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
506 return -EINVAL;
507
508 ret = fimc_vidioc_try_fmt_mplane(file, priv, f);
509 if (ret)
510 return ret;
511
512 if (vb2_is_busy(&fimc->vid_cap.vbq) || fimc_capture_active(fimc))
513 return -EBUSY;
514
515 frame = &ctx->d_frame;
516
517 pix = &f->fmt.pix_mp;
518 frame->fmt = find_format(f, FMT_FLAGS_M2M | FMT_FLAGS_CAM);
519 if (!frame->fmt) {
520 err("fimc target format not found\n");
521 return -EINVAL;
522 }
523
524 for (i = 0; i < frame->fmt->colplanes; i++) {
525 frame->payload[i] =
526 (pix->width * pix->height * frame->fmt->depth[i]) >> 3;
527 }
528
529 /* Output DMA frame pixel size and offsets. */
530 frame->f_width = pix->plane_fmt[0].bytesperline * 8
531 / frame->fmt->depth[0];
532 frame->f_height = pix->height;
533 frame->width = pix->width;
534 frame->height = pix->height;
535 frame->o_width = pix->width;
536 frame->o_height = pix->height;
537 frame->offs_h = 0;
538 frame->offs_v = 0;
539
540 ctx->state |= (FIMC_PARAMS | FIMC_DST_FMT);
541
542 ret = sync_capture_fmt(ctx);
543 return ret;
544}
545
546static int fimc_cap_enum_input(struct file *file, void *priv,
547 struct v4l2_input *i)
548{
549 struct fimc_ctx *ctx = priv;
550 struct s5p_platform_fimc *pldata = ctx->fimc_dev->pdata;
551 struct s5p_fimc_isp_info *isp_info;
552
553 if (i->index >= pldata->num_clients)
554 return -EINVAL;
555
556 isp_info = &pldata->isp_info[i->index];
557
558 i->type = V4L2_INPUT_TYPE_CAMERA;
559 strncpy(i->name, isp_info->board_info->type, 32);
560 return 0;
561}
562
563static int fimc_cap_s_input(struct file *file, void *priv,
564 unsigned int i)
565{
566 struct fimc_ctx *ctx = priv;
567 struct fimc_dev *fimc = ctx->fimc_dev;
568 struct s5p_platform_fimc *pdata = fimc->pdata;
569
570 if (fimc_capture_active(ctx->fimc_dev))
571 return -EBUSY;
572
573 if (i >= pdata->num_clients)
574 return -EINVAL;
575
576
577 if (fimc->vid_cap.sd) {
578 int ret = v4l2_subdev_call(fimc->vid_cap.sd, core, s_power, 0);
579 if (ret)
580 err("s_power failed: %d", ret);
581
582 clk_disable(fimc->clock[CLK_CAM]);
583 }
584
585 /* Release the attached sensor subdevice. */
586 fimc_subdev_unregister(fimc);
587
588 return fimc_isp_subdev_init(fimc, i);
589}
590
591static int fimc_cap_g_input(struct file *file, void *priv,
592 unsigned int *i)
593{
594 struct fimc_ctx *ctx = priv;
595 struct fimc_vid_cap *cap = &ctx->fimc_dev->vid_cap;
596
597 *i = cap->input_index;
598 return 0;
599}
600
601static int fimc_cap_streamon(struct file *file, void *priv,
602 enum v4l2_buf_type type)
603{
604 struct fimc_ctx *ctx = priv;
605 struct fimc_dev *fimc = ctx->fimc_dev;
606
607 if (fimc_capture_active(fimc) || !fimc->vid_cap.sd)
608 return -EBUSY;
609
610 if (!(ctx->state & FIMC_DST_FMT)) {
611 v4l2_err(&fimc->vid_cap.v4l2_dev, "Format is not set\n");
612 return -EINVAL;
613 }
614
615 return vb2_streamon(&fimc->vid_cap.vbq, type);
616}
617
618static int fimc_cap_streamoff(struct file *file, void *priv,
619 enum v4l2_buf_type type)
620{
621 struct fimc_ctx *ctx = priv;
622 struct fimc_dev *fimc = ctx->fimc_dev;
623
624 return vb2_streamoff(&fimc->vid_cap.vbq, type);
625}
626
627static int fimc_cap_reqbufs(struct file *file, void *priv,
628 struct v4l2_requestbuffers *reqbufs)
629{
630 struct fimc_ctx *ctx = priv;
631 struct fimc_vid_cap *cap = &ctx->fimc_dev->vid_cap;
632 int ret;
633
634
635 ret = vb2_reqbufs(&cap->vbq, reqbufs);
636 if (!ret)
637 cap->reqbufs_count = reqbufs->count;
638
639 return ret;
640}
641
642static int fimc_cap_querybuf(struct file *file, void *priv,
643 struct v4l2_buffer *buf)
644{
645 struct fimc_ctx *ctx = priv;
646 struct fimc_vid_cap *cap = &ctx->fimc_dev->vid_cap;
647
648 return vb2_querybuf(&cap->vbq, buf);
649}
650
651static int fimc_cap_qbuf(struct file *file, void *priv,
652 struct v4l2_buffer *buf)
653{
654 struct fimc_ctx *ctx = priv;
655 struct fimc_vid_cap *cap = &ctx->fimc_dev->vid_cap;
656 return vb2_qbuf(&cap->vbq, buf);
657}
658
659static int fimc_cap_dqbuf(struct file *file, void *priv,
660 struct v4l2_buffer *buf)
661{
662 struct fimc_ctx *ctx = priv;
663 return vb2_dqbuf(&ctx->fimc_dev->vid_cap.vbq, buf,
664 file->f_flags & O_NONBLOCK);
665}
666
667static int fimc_cap_s_ctrl(struct file *file, void *priv,
668 struct v4l2_control *ctrl)
669{
670 struct fimc_ctx *ctx = priv;
671 int ret = -EINVAL;
672
673 /* Allow any controls but 90/270 rotation while streaming */
674 if (!fimc_capture_active(ctx->fimc_dev) ||
675 ctrl->id != V4L2_CID_ROTATE ||
676 (ctrl->value != 90 && ctrl->value != 270)) {
677 ret = check_ctrl_val(ctx, ctrl);
678 if (!ret) {
679 ret = fimc_s_ctrl(ctx, ctrl);
680 if (!ret)
681 ctx->state |= FIMC_PARAMS;
682 }
683 }
684 if (ret == -EINVAL)
685 ret = v4l2_subdev_call(ctx->fimc_dev->vid_cap.sd,
686 core, s_ctrl, ctrl);
687 return ret;
688}
689
690static int fimc_cap_cropcap(struct file *file, void *fh,
691 struct v4l2_cropcap *cr)
692{
693 struct fimc_frame *f;
694 struct fimc_ctx *ctx = fh;
695
696 if (cr->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
697 return -EINVAL;
698
699 f = &ctx->s_frame;
700
701 cr->bounds.left = 0;
702 cr->bounds.top = 0;
703 cr->bounds.width = f->o_width;
704 cr->bounds.height = f->o_height;
705 cr->defrect = cr->bounds;
706
707 return 0;
708}
709
710static int fimc_cap_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
711{
712 struct fimc_frame *f;
713 struct fimc_ctx *ctx = file->private_data;
714
715 f = &ctx->s_frame;
716
717 cr->c.left = f->offs_h;
718 cr->c.top = f->offs_v;
719 cr->c.width = f->width;
720 cr->c.height = f->height;
721
722 return 0;
723}
724
725static int fimc_cap_s_crop(struct file *file, void *fh,
726 struct v4l2_crop *cr)
727{
728 struct fimc_frame *f;
729 struct fimc_ctx *ctx = file->private_data;
730 struct fimc_dev *fimc = ctx->fimc_dev;
731 int ret = -EINVAL;
732
733 if (fimc_capture_active(fimc))
734 return -EBUSY;
735
736 ret = fimc_try_crop(ctx, cr);
737 if (ret)
738 return ret;
739
740 if (!(ctx->state & FIMC_DST_FMT)) {
741 v4l2_err(&fimc->vid_cap.v4l2_dev,
742 "Capture color format not set\n");
743 return -EINVAL; /* TODO: make sure this is the right value */
744 }
745
746 f = &ctx->s_frame;
747 /* Check for the pixel scaling ratio when cropping input image. */
748 ret = fimc_check_scaler_ratio(cr->c.width, cr->c.height,
749 ctx->d_frame.width, ctx->d_frame.height,
750 ctx->rotation);
751 if (ret) {
752 v4l2_err(&fimc->vid_cap.v4l2_dev, "Out of the scaler range\n");
753 return ret;
754 }
755
756 f->offs_h = cr->c.left;
757 f->offs_v = cr->c.top;
758 f->width = cr->c.width;
759 f->height = cr->c.height;
760
761 return 0;
762}
763
764
765static const struct v4l2_ioctl_ops fimc_capture_ioctl_ops = {
766 .vidioc_querycap = fimc_vidioc_querycap_capture,
767
768 .vidioc_enum_fmt_vid_cap_mplane = fimc_vidioc_enum_fmt_mplane,
769 .vidioc_try_fmt_vid_cap_mplane = fimc_vidioc_try_fmt_mplane,
770 .vidioc_s_fmt_vid_cap_mplane = fimc_cap_s_fmt_mplane,
771 .vidioc_g_fmt_vid_cap_mplane = fimc_vidioc_g_fmt_mplane,
772
773 .vidioc_reqbufs = fimc_cap_reqbufs,
774 .vidioc_querybuf = fimc_cap_querybuf,
775
776 .vidioc_qbuf = fimc_cap_qbuf,
777 .vidioc_dqbuf = fimc_cap_dqbuf,
778
779 .vidioc_streamon = fimc_cap_streamon,
780 .vidioc_streamoff = fimc_cap_streamoff,
781
782 .vidioc_queryctrl = fimc_vidioc_queryctrl,
783 .vidioc_g_ctrl = fimc_vidioc_g_ctrl,
784 .vidioc_s_ctrl = fimc_cap_s_ctrl,
785
786 .vidioc_g_crop = fimc_cap_g_crop,
787 .vidioc_s_crop = fimc_cap_s_crop,
788 .vidioc_cropcap = fimc_cap_cropcap,
789
790 .vidioc_enum_input = fimc_cap_enum_input,
791 .vidioc_s_input = fimc_cap_s_input,
792 .vidioc_g_input = fimc_cap_g_input,
793};
794
795/* fimc->lock must be already initialized */
796int fimc_register_capture_device(struct fimc_dev *fimc)
797{
798 struct v4l2_device *v4l2_dev = &fimc->vid_cap.v4l2_dev;
799 struct video_device *vfd;
800 struct fimc_vid_cap *vid_cap;
801 struct fimc_ctx *ctx;
802 struct v4l2_format f;
803 struct fimc_frame *fr;
804 struct vb2_queue *q;
805 int ret;
806
807 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
808 if (!ctx)
809 return -ENOMEM;
810
811 ctx->fimc_dev = fimc;
812 ctx->in_path = FIMC_CAMERA;
813 ctx->out_path = FIMC_DMA;
814 ctx->state = FIMC_CTX_CAP;
815
816 /* Default format of the output frames */
817 f.fmt.pix.pixelformat = V4L2_PIX_FMT_RGB32;
818 fr = &ctx->d_frame;
819 fr->fmt = find_format(&f, FMT_FLAGS_M2M);
820 fr->width = fr->f_width = fr->o_width = 640;
821 fr->height = fr->f_height = fr->o_height = 480;
822
823 if (!v4l2_dev->name[0])
824 snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
825 "%s.capture", dev_name(&fimc->pdev->dev));
826
827 ret = v4l2_device_register(NULL, v4l2_dev);
828 if (ret)
829 goto err_info;
830
831 vfd = video_device_alloc();
832 if (!vfd) {
833 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
834 goto err_v4l2_reg;
835 }
836
837 snprintf(vfd->name, sizeof(vfd->name), "%s:cap",
838 dev_name(&fimc->pdev->dev));
839
840 vfd->fops = &fimc_capture_fops;
841 vfd->ioctl_ops = &fimc_capture_ioctl_ops;
842 vfd->minor = -1;
843 vfd->release = video_device_release;
844 vfd->lock = &fimc->lock;
845 video_set_drvdata(vfd, fimc);
846
847 vid_cap = &fimc->vid_cap;
848 vid_cap->vfd = vfd;
849 vid_cap->active_buf_cnt = 0;
850 vid_cap->reqbufs_count = 0;
851 vid_cap->refcnt = 0;
852 /* Default color format for image sensor */
853 vid_cap->fmt.code = V4L2_MBUS_FMT_YUYV8_2X8;
854
855 INIT_LIST_HEAD(&vid_cap->pending_buf_q);
856 INIT_LIST_HEAD(&vid_cap->active_buf_q);
857 spin_lock_init(&ctx->slock);
858 vid_cap->ctx = ctx;
859
860 q = &fimc->vid_cap.vbq;
861 memset(q, 0, sizeof(*q));
862 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
863 q->io_modes = VB2_MMAP | VB2_USERPTR;
864 q->drv_priv = fimc->vid_cap.ctx;
865 q->ops = &fimc_capture_qops;
866 q->mem_ops = &vb2_dma_contig_memops;
867 q->buf_struct_size = sizeof(struct fimc_vid_buffer);
868
869 vb2_queue_init(q);
870
871 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
872 if (ret) {
873 v4l2_err(v4l2_dev, "Failed to register video device\n");
874 goto err_vd_reg;
875 }
876
877 v4l2_info(v4l2_dev,
878 "FIMC capture driver registered as /dev/video%d\n",
879 vfd->num);
880
881 return 0;
882
883err_vd_reg:
884 video_device_release(vfd);
885err_v4l2_reg:
886 v4l2_device_unregister(v4l2_dev);
887err_info:
888 kfree(ctx);
889 dev_err(&fimc->pdev->dev, "failed to install\n");
890 return ret;
891}
892
893void fimc_unregister_capture_device(struct fimc_dev *fimc)
894{
895 struct fimc_vid_cap *capture = &fimc->vid_cap;
896
897 if (capture->vfd)
898 video_unregister_device(capture->vfd);
899
900 kfree(capture->ctx);
901}
diff --git a/drivers/media/video/s5p-fimc/fimc-core.c b/drivers/media/video/s5p-fimc/fimc-core.c
new file mode 100644
index 00000000000..b062b1a6768
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/fimc-core.c
@@ -0,0 +1,1938 @@
1/*
2 * Samsung S5P/EXYNOS4 SoC series camera interface (video postprocessor) driver
3 *
4 * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
5 * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published
9 * by the Free Software Foundation, either version 2 of the License,
10 * or (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/errno.h>
17#include <linux/bug.h>
18#include <linux/interrupt.h>
19#include <linux/device.h>
20#include <linux/platform_device.h>
21#include <linux/list.h>
22#include <linux/io.h>
23#include <linux/slab.h>
24#include <linux/clk.h>
25#include <media/v4l2-ioctl.h>
26#include <media/videobuf2-core.h>
27#include <media/videobuf2-dma-contig.h>
28
29#include "fimc-core.h"
30
31static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
32 "sclk_fimc", "fimc", "sclk_cam"
33};
34
35static struct fimc_fmt fimc_formats[] = {
36 {
37 .name = "RGB565",
38 .fourcc = V4L2_PIX_FMT_RGB565,
39 .depth = { 16 },
40 .color = S5P_FIMC_RGB565,
41 .memplanes = 1,
42 .colplanes = 1,
43 .flags = FMT_FLAGS_M2M,
44 }, {
45 .name = "BGR666",
46 .fourcc = V4L2_PIX_FMT_BGR666,
47 .depth = { 32 },
48 .color = S5P_FIMC_RGB666,
49 .memplanes = 1,
50 .colplanes = 1,
51 .flags = FMT_FLAGS_M2M,
52 }, {
53 .name = "XRGB-8-8-8-8, 32 bpp",
54 .fourcc = V4L2_PIX_FMT_RGB32,
55 .depth = { 32 },
56 .color = S5P_FIMC_RGB888,
57 .memplanes = 1,
58 .colplanes = 1,
59 .flags = FMT_FLAGS_M2M,
60 }, {
61 .name = "YUV 4:2:2 packed, YCbYCr",
62 .fourcc = V4L2_PIX_FMT_YUYV,
63 .depth = { 16 },
64 .color = S5P_FIMC_YCBYCR422,
65 .memplanes = 1,
66 .colplanes = 1,
67 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
68 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
69 }, {
70 .name = "YUV 4:2:2 packed, CbYCrY",
71 .fourcc = V4L2_PIX_FMT_UYVY,
72 .depth = { 16 },
73 .color = S5P_FIMC_CBYCRY422,
74 .memplanes = 1,
75 .colplanes = 1,
76 .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
77 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
78 }, {
79 .name = "YUV 4:2:2 packed, CrYCbY",
80 .fourcc = V4L2_PIX_FMT_VYUY,
81 .depth = { 16 },
82 .color = S5P_FIMC_CRYCBY422,
83 .memplanes = 1,
84 .colplanes = 1,
85 .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
86 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
87 }, {
88 .name = "YUV 4:2:2 packed, YCrYCb",
89 .fourcc = V4L2_PIX_FMT_YVYU,
90 .depth = { 16 },
91 .color = S5P_FIMC_YCRYCB422,
92 .memplanes = 1,
93 .colplanes = 1,
94 .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
95 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
96 }, {
97 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
98 .fourcc = V4L2_PIX_FMT_YUV422P,
99 .depth = { 12 },
100 .color = S5P_FIMC_YCBYCR422,
101 .memplanes = 1,
102 .colplanes = 3,
103 .flags = FMT_FLAGS_M2M,
104 }, {
105 .name = "YUV 4:2:2 planar, Y/CbCr",
106 .fourcc = V4L2_PIX_FMT_NV16,
107 .depth = { 16 },
108 .color = S5P_FIMC_YCBYCR422,
109 .memplanes = 1,
110 .colplanes = 2,
111 .flags = FMT_FLAGS_M2M,
112 }, {
113 .name = "YUV 4:2:2 planar, Y/CrCb",
114 .fourcc = V4L2_PIX_FMT_NV61,
115 .depth = { 16 },
116 .color = S5P_FIMC_YCRYCB422,
117 .memplanes = 1,
118 .colplanes = 2,
119 .flags = FMT_FLAGS_M2M,
120 }, {
121 .name = "YUV 4:2:0 planar, YCbCr",
122 .fourcc = V4L2_PIX_FMT_YUV420,
123 .depth = { 12 },
124 .color = S5P_FIMC_YCBCR420,
125 .memplanes = 1,
126 .colplanes = 3,
127 .flags = FMT_FLAGS_M2M,
128 }, {
129 .name = "YUV 4:2:0 planar, Y/CbCr",
130 .fourcc = V4L2_PIX_FMT_NV12,
131 .depth = { 12 },
132 .color = S5P_FIMC_YCBCR420,
133 .memplanes = 1,
134 .colplanes = 2,
135 .flags = FMT_FLAGS_M2M,
136 }, {
137 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
138 .fourcc = V4L2_PIX_FMT_NV12M,
139 .color = S5P_FIMC_YCBCR420,
140 .depth = { 8, 4 },
141 .memplanes = 2,
142 .colplanes = 2,
143 .flags = FMT_FLAGS_M2M,
144 }, {
145 .name = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
146 .fourcc = V4L2_PIX_FMT_YUV420M,
147 .color = S5P_FIMC_YCBCR420,
148 .depth = { 8, 2, 2 },
149 .memplanes = 3,
150 .colplanes = 3,
151 .flags = FMT_FLAGS_M2M,
152 }, {
153 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
154 .fourcc = V4L2_PIX_FMT_NV12MT,
155 .color = S5P_FIMC_YCBCR420,
156 .depth = { 8, 4 },
157 .memplanes = 2,
158 .colplanes = 2,
159 .flags = FMT_FLAGS_M2M,
160 },
161};
162
163static struct v4l2_queryctrl fimc_ctrls[] = {
164 {
165 .id = V4L2_CID_HFLIP,
166 .type = V4L2_CTRL_TYPE_BOOLEAN,
167 .name = "Horizontal flip",
168 .minimum = 0,
169 .maximum = 1,
170 .default_value = 0,
171 }, {
172 .id = V4L2_CID_VFLIP,
173 .type = V4L2_CTRL_TYPE_BOOLEAN,
174 .name = "Vertical flip",
175 .minimum = 0,
176 .maximum = 1,
177 .default_value = 0,
178 }, {
179 .id = V4L2_CID_ROTATE,
180 .type = V4L2_CTRL_TYPE_INTEGER,
181 .name = "Rotation (CCW)",
182 .minimum = 0,
183 .maximum = 270,
184 .step = 90,
185 .default_value = 0,
186 },
187};
188
189
190static struct v4l2_queryctrl *get_ctrl(int id)
191{
192 int i;
193
194 for (i = 0; i < ARRAY_SIZE(fimc_ctrls); ++i)
195 if (id == fimc_ctrls[i].id)
196 return &fimc_ctrls[i];
197 return NULL;
198}
199
200int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot)
201{
202 int tx, ty;
203
204 if (rot == 90 || rot == 270) {
205 ty = dw;
206 tx = dh;
207 } else {
208 tx = dw;
209 ty = dh;
210 }
211
212 if ((sw >= SCALER_MAX_HRATIO * tx) || (sh >= SCALER_MAX_VRATIO * ty))
213 return -EINVAL;
214
215 return 0;
216}
217
218static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
219{
220 u32 sh = 6;
221
222 if (src >= 64 * tar)
223 return -EINVAL;
224
225 while (sh--) {
226 u32 tmp = 1 << sh;
227 if (src >= tar * tmp) {
228 *shift = sh, *ratio = tmp;
229 return 0;
230 }
231 }
232 *shift = 0, *ratio = 1;
233 return 0;
234}
235
236int fimc_set_scaler_info(struct fimc_ctx *ctx)
237{
238 struct fimc_scaler *sc = &ctx->scaler;
239 struct fimc_frame *s_frame = &ctx->s_frame;
240 struct fimc_frame *d_frame = &ctx->d_frame;
241 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
242 int tx, ty, sx, sy;
243 int ret;
244
245 if (ctx->rotation == 90 || ctx->rotation == 270) {
246 ty = d_frame->width;
247 tx = d_frame->height;
248 } else {
249 tx = d_frame->width;
250 ty = d_frame->height;
251 }
252 if (tx <= 0 || ty <= 0) {
253 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
254 "invalid target size: %d x %d", tx, ty);
255 return -EINVAL;
256 }
257
258 sx = s_frame->width;
259 sy = s_frame->height;
260 if (sx <= 0 || sy <= 0) {
261 err("invalid source size: %d x %d", sx, sy);
262 return -EINVAL;
263 }
264 sc->real_width = sx;
265 sc->real_height = sy;
266
267 ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
268 if (ret)
269 return ret;
270
271 ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
272 if (ret)
273 return ret;
274
275 sc->pre_dst_width = sx / sc->pre_hratio;
276 sc->pre_dst_height = sy / sc->pre_vratio;
277
278 if (variant->has_mainscaler_ext) {
279 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
280 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
281 } else {
282 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
283 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
284
285 }
286
287 sc->scaleup_h = (tx >= sx) ? 1 : 0;
288 sc->scaleup_v = (ty >= sy) ? 1 : 0;
289
290 /* check to see if input and output size/format differ */
291 if (s_frame->fmt->color == d_frame->fmt->color
292 && s_frame->width == d_frame->width
293 && s_frame->height == d_frame->height)
294 sc->copy_mode = 1;
295 else
296 sc->copy_mode = 0;
297
298 return 0;
299}
300
301static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
302{
303 struct vb2_buffer *src_vb, *dst_vb;
304 struct fimc_dev *fimc = ctx->fimc_dev;
305
306 if (!ctx || !ctx->m2m_ctx)
307 return;
308
309 src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
310 dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
311
312 if (src_vb && dst_vb) {
313 v4l2_m2m_buf_done(src_vb, vb_state);
314 v4l2_m2m_buf_done(dst_vb, vb_state);
315 v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
316 }
317}
318
319/* Complete the transaction which has been scheduled for execution. */
320static void fimc_m2m_shutdown(struct fimc_ctx *ctx)
321{
322 struct fimc_dev *fimc = ctx->fimc_dev;
323 int ret;
324
325 if (!fimc_m2m_pending(fimc))
326 return;
327
328 fimc_ctx_state_lock_set(FIMC_CTX_SHUT, ctx);
329
330 ret = wait_event_timeout(fimc->irq_queue,
331 !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
332 FIMC_SHUTDOWN_TIMEOUT);
333 /*
334 * In case of a timeout the buffers are not released in the interrupt
335 * handler so return them here with the error flag set, if there are
336 * any on the queue.
337 */
338 if (ret == 0)
339 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
340}
341
342static int stop_streaming(struct vb2_queue *q)
343{
344 struct fimc_ctx *ctx = q->drv_priv;
345
346 fimc_m2m_shutdown(ctx);
347
348 return 0;
349}
350
351static void fimc_capture_irq_handler(struct fimc_dev *fimc)
352{
353 struct fimc_vid_cap *cap = &fimc->vid_cap;
354 struct fimc_vid_buffer *v_buf;
355 struct timeval *tv;
356 struct timespec ts;
357
358 if (!list_empty(&cap->active_buf_q) &&
359 test_bit(ST_CAPT_RUN, &fimc->state)) {
360 ktime_get_real_ts(&ts);
361
362 v_buf = active_queue_pop(cap);
363
364 tv = &v_buf->vb.v4l2_buf.timestamp;
365 tv->tv_sec = ts.tv_sec;
366 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
367 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
368
369 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
370 }
371
372 if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
373 wake_up(&fimc->irq_queue);
374 return;
375 }
376
377 if (!list_empty(&cap->pending_buf_q)) {
378
379 v_buf = pending_queue_pop(cap);
380 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
381 v_buf->index = cap->buf_index;
382
383 /* Move the buffer to the capture active queue */
384 active_queue_add(cap, v_buf);
385
386 dbg("next frame: %d, done frame: %d",
387 fimc_hw_get_frame_index(fimc), v_buf->index);
388
389 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
390 cap->buf_index = 0;
391 }
392
393 if (cap->active_buf_cnt == 0) {
394 clear_bit(ST_CAPT_RUN, &fimc->state);
395
396 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
397 cap->buf_index = 0;
398 } else {
399 set_bit(ST_CAPT_RUN, &fimc->state);
400 }
401
402 dbg("frame: %d, active_buf_cnt: %d",
403 fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
404}
405
406static irqreturn_t fimc_isr(int irq, void *priv)
407{
408 struct fimc_dev *fimc = priv;
409 struct fimc_vid_cap *cap = &fimc->vid_cap;
410 struct fimc_ctx *ctx;
411
412 fimc_hw_clear_irq(fimc);
413
414 if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
415 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
416 if (ctx != NULL) {
417 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
418
419 spin_lock(&ctx->slock);
420 if (ctx->state & FIMC_CTX_SHUT) {
421 ctx->state &= ~FIMC_CTX_SHUT;
422 wake_up(&fimc->irq_queue);
423 }
424 spin_unlock(&ctx->slock);
425 }
426
427 return IRQ_HANDLED;
428 }
429
430 spin_lock(&fimc->slock);
431
432 if (test_bit(ST_CAPT_PEND, &fimc->state)) {
433 fimc_capture_irq_handler(fimc);
434
435 if (cap->active_buf_cnt == 1) {
436 fimc_deactivate_capture(fimc);
437 clear_bit(ST_CAPT_STREAM, &fimc->state);
438 }
439 }
440
441 spin_unlock(&fimc->slock);
442 return IRQ_HANDLED;
443}
444
445/* The color format (colplanes, memplanes) must be already configured. */
446int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
447 struct fimc_frame *frame, struct fimc_addr *paddr)
448{
449 int ret = 0;
450 u32 pix_size;
451
452 if (vb == NULL || frame == NULL)
453 return -EINVAL;
454
455 pix_size = frame->width * frame->height;
456
457 dbg("memplanes= %d, colplanes= %d, pix_size= %d",
458 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
459
460 paddr->y = vb2_dma_contig_plane_paddr(vb, 0);
461
462 if (frame->fmt->memplanes == 1) {
463 switch (frame->fmt->colplanes) {
464 case 1:
465 paddr->cb = 0;
466 paddr->cr = 0;
467 break;
468 case 2:
469 /* decompose Y into Y/Cb */
470 paddr->cb = (u32)(paddr->y + pix_size);
471 paddr->cr = 0;
472 break;
473 case 3:
474 paddr->cb = (u32)(paddr->y + pix_size);
475 /* decompose Y into Y/Cb/Cr */
476 if (S5P_FIMC_YCBCR420 == frame->fmt->color)
477 paddr->cr = (u32)(paddr->cb
478 + (pix_size >> 2));
479 else /* 422 */
480 paddr->cr = (u32)(paddr->cb
481 + (pix_size >> 1));
482 break;
483 default:
484 return -EINVAL;
485 }
486 } else {
487 if (frame->fmt->memplanes >= 2)
488 paddr->cb = vb2_dma_contig_plane_paddr(vb, 1);
489
490 if (frame->fmt->memplanes == 3)
491 paddr->cr = vb2_dma_contig_plane_paddr(vb, 2);
492 }
493
494 dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
495 paddr->y, paddr->cb, paddr->cr, ret);
496
497 return ret;
498}
499
500/* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
501static void fimc_set_yuv_order(struct fimc_ctx *ctx)
502{
503 /* The one only mode supported in SoC. */
504 ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
505 ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
506
507 /* Set order for 1 plane input formats. */
508 switch (ctx->s_frame.fmt->color) {
509 case S5P_FIMC_YCRYCB422:
510 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
511 break;
512 case S5P_FIMC_CBYCRY422:
513 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
514 break;
515 case S5P_FIMC_CRYCBY422:
516 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
517 break;
518 case S5P_FIMC_YCBYCR422:
519 default:
520 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
521 break;
522 }
523 dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
524
525 switch (ctx->d_frame.fmt->color) {
526 case S5P_FIMC_YCRYCB422:
527 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
528 break;
529 case S5P_FIMC_CBYCRY422:
530 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
531 break;
532 case S5P_FIMC_CRYCBY422:
533 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
534 break;
535 case S5P_FIMC_YCBYCR422:
536 default:
537 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
538 break;
539 }
540 dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
541}
542
543static void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
544{
545 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
546 u32 i, depth = 0;
547
548 for (i = 0; i < f->fmt->colplanes; i++)
549 depth += f->fmt->depth[i];
550
551 f->dma_offset.y_h = f->offs_h;
552 if (!variant->pix_hoff)
553 f->dma_offset.y_h *= (depth >> 3);
554
555 f->dma_offset.y_v = f->offs_v;
556
557 f->dma_offset.cb_h = f->offs_h;
558 f->dma_offset.cb_v = f->offs_v;
559
560 f->dma_offset.cr_h = f->offs_h;
561 f->dma_offset.cr_v = f->offs_v;
562
563 if (!variant->pix_hoff) {
564 if (f->fmt->colplanes == 3) {
565 f->dma_offset.cb_h >>= 1;
566 f->dma_offset.cr_h >>= 1;
567 }
568 if (f->fmt->color == S5P_FIMC_YCBCR420) {
569 f->dma_offset.cb_v >>= 1;
570 f->dma_offset.cr_v >>= 1;
571 }
572 }
573
574 dbg("in_offset: color= %d, y_h= %d, y_v= %d",
575 f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
576}
577
578/**
579 * fimc_prepare_config - check dimensions, operation and color mode
580 * and pre-calculate offset and the scaling coefficients.
581 *
582 * @ctx: hardware context information
583 * @flags: flags indicating which parameters to check/update
584 *
585 * Return: 0 if dimensions are valid or non zero otherwise.
586 */
587int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
588{
589 struct fimc_frame *s_frame, *d_frame;
590 struct vb2_buffer *vb = NULL;
591 int ret = 0;
592
593 s_frame = &ctx->s_frame;
594 d_frame = &ctx->d_frame;
595
596 if (flags & FIMC_PARAMS) {
597 /* Prepare the DMA offset ratios for scaler. */
598 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
599 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
600
601 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
602 s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
603 err("out of scaler range");
604 return -EINVAL;
605 }
606 fimc_set_yuv_order(ctx);
607 }
608
609 /* Input DMA mode is not allowed when the scaler is disabled. */
610 ctx->scaler.enabled = 1;
611
612 if (flags & FIMC_SRC_ADDR) {
613 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
614 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
615 if (ret)
616 return ret;
617 }
618
619 if (flags & FIMC_DST_ADDR) {
620 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
621 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
622 }
623
624 return ret;
625}
626
627static void fimc_dma_run(void *priv)
628{
629 struct fimc_ctx *ctx = priv;
630 struct fimc_dev *fimc;
631 unsigned long flags;
632 u32 ret;
633
634 if (WARN(!ctx, "null hardware context\n"))
635 return;
636
637 fimc = ctx->fimc_dev;
638
639 spin_lock_irqsave(&ctx->slock, flags);
640 set_bit(ST_M2M_PEND, &fimc->state);
641
642 ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
643 ret = fimc_prepare_config(ctx, ctx->state);
644 if (ret)
645 goto dma_unlock;
646
647 /* Reconfigure hardware if the context has changed. */
648 if (fimc->m2m.ctx != ctx) {
649 ctx->state |= FIMC_PARAMS;
650 fimc->m2m.ctx = ctx;
651 }
652
653 spin_lock(&fimc->slock);
654 fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
655
656 if (ctx->state & FIMC_PARAMS) {
657 fimc_hw_set_input_path(ctx);
658 fimc_hw_set_in_dma(ctx);
659 ret = fimc_set_scaler_info(ctx);
660 if (ret) {
661 spin_unlock(&fimc->slock);
662 goto dma_unlock;
663 }
664 fimc_hw_set_prescaler(ctx);
665 fimc_hw_set_mainscaler(ctx);
666 fimc_hw_set_target_format(ctx);
667 fimc_hw_set_rotation(ctx);
668 fimc_hw_set_effect(ctx);
669 }
670
671 fimc_hw_set_output_path(ctx);
672 if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
673 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
674
675 if (ctx->state & FIMC_PARAMS)
676 fimc_hw_set_out_dma(ctx);
677
678 fimc_activate_capture(ctx);
679
680 ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
681 FIMC_SRC_FMT | FIMC_DST_FMT);
682 fimc_hw_activate_input_dma(fimc, true);
683 spin_unlock(&fimc->slock);
684
685dma_unlock:
686 spin_unlock_irqrestore(&ctx->slock, flags);
687}
688
689static void fimc_job_abort(void *priv)
690{
691 fimc_m2m_shutdown(priv);
692}
693
694static int fimc_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
695 unsigned int *num_planes, unsigned long sizes[],
696 void *allocators[])
697{
698 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
699 struct fimc_frame *f;
700 int i;
701
702 f = ctx_get_frame(ctx, vq->type);
703 if (IS_ERR(f))
704 return PTR_ERR(f);
705 /*
706 * Return number of non-contigous planes (plane buffers)
707 * depending on the configured color format.
708 */
709 if (!f->fmt)
710 return -EINVAL;
711
712 *num_planes = f->fmt->memplanes;
713 for (i = 0; i < f->fmt->memplanes; i++) {
714 sizes[i] = (f->f_width * f->f_height * f->fmt->depth[i]) / 8;
715 allocators[i] = ctx->fimc_dev->alloc_ctx;
716 }
717 return 0;
718}
719
720static int fimc_buf_prepare(struct vb2_buffer *vb)
721{
722 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
723 struct fimc_frame *frame;
724 int i;
725
726 frame = ctx_get_frame(ctx, vb->vb2_queue->type);
727 if (IS_ERR(frame))
728 return PTR_ERR(frame);
729
730 for (i = 0; i < frame->fmt->memplanes; i++)
731 vb2_set_plane_payload(vb, i, frame->payload[i]);
732
733 return 0;
734}
735
736static void fimc_buf_queue(struct vb2_buffer *vb)
737{
738 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
739
740 dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
741
742 if (ctx->m2m_ctx)
743 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
744}
745
746static void fimc_lock(struct vb2_queue *vq)
747{
748 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
749 mutex_lock(&ctx->fimc_dev->lock);
750}
751
752static void fimc_unlock(struct vb2_queue *vq)
753{
754 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
755 mutex_unlock(&ctx->fimc_dev->lock);
756}
757
758static struct vb2_ops fimc_qops = {
759 .queue_setup = fimc_queue_setup,
760 .buf_prepare = fimc_buf_prepare,
761 .buf_queue = fimc_buf_queue,
762 .wait_prepare = fimc_unlock,
763 .wait_finish = fimc_lock,
764 .stop_streaming = stop_streaming,
765};
766
767static int fimc_m2m_querycap(struct file *file, void *priv,
768 struct v4l2_capability *cap)
769{
770 struct fimc_ctx *ctx = file->private_data;
771 struct fimc_dev *fimc = ctx->fimc_dev;
772
773 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
774 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
775 cap->bus_info[0] = 0;
776 cap->capabilities = V4L2_CAP_STREAMING |
777 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
778 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
779
780 return 0;
781}
782
783int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
784 struct v4l2_fmtdesc *f)
785{
786 struct fimc_fmt *fmt;
787
788 if (f->index >= ARRAY_SIZE(fimc_formats))
789 return -EINVAL;
790
791 fmt = &fimc_formats[f->index];
792 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
793 f->pixelformat = fmt->fourcc;
794
795 return 0;
796}
797
798int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
799 struct v4l2_format *f)
800{
801 struct fimc_ctx *ctx = priv;
802 struct fimc_frame *frame;
803 struct v4l2_pix_format_mplane *pixm;
804 int i;
805
806 frame = ctx_get_frame(ctx, f->type);
807 if (IS_ERR(frame))
808 return PTR_ERR(frame);
809
810 pixm = &f->fmt.pix_mp;
811
812 pixm->width = frame->width;
813 pixm->height = frame->height;
814 pixm->field = V4L2_FIELD_NONE;
815 pixm->pixelformat = frame->fmt->fourcc;
816 pixm->colorspace = V4L2_COLORSPACE_JPEG;
817 pixm->num_planes = frame->fmt->memplanes;
818
819 for (i = 0; i < pixm->num_planes; ++i) {
820 int bpl = frame->o_width;
821
822 if (frame->fmt->colplanes == 1) /* packed formats */
823 bpl = (bpl * frame->fmt->depth[0]) / 8;
824
825 pixm->plane_fmt[i].bytesperline = bpl;
826
827 pixm->plane_fmt[i].sizeimage = (frame->o_width *
828 frame->o_height * frame->fmt->depth[i]) / 8;
829 }
830
831 return 0;
832}
833
834struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask)
835{
836 struct fimc_fmt *fmt;
837 unsigned int i;
838
839 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
840 fmt = &fimc_formats[i];
841 if (fmt->fourcc == f->fmt.pix_mp.pixelformat &&
842 (fmt->flags & mask))
843 break;
844 }
845
846 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
847}
848
849struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
850 unsigned int mask)
851{
852 struct fimc_fmt *fmt;
853 unsigned int i;
854
855 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
856 fmt = &fimc_formats[i];
857 if (fmt->mbus_code == f->code && (fmt->flags & mask))
858 break;
859 }
860
861 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
862}
863
864
865int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
866 struct v4l2_format *f)
867{
868 struct fimc_ctx *ctx = priv;
869 struct fimc_dev *fimc = ctx->fimc_dev;
870 struct samsung_fimc_variant *variant = fimc->variant;
871 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
872 struct fimc_fmt *fmt;
873 u32 max_width, mod_x, mod_y, mask;
874 int i, is_output = 0;
875
876
877 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
878 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx))
879 return -EINVAL;
880 is_output = 1;
881 } else if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
882 return -EINVAL;
883 }
884
885 dbg("w: %d, h: %d", pix->width, pix->height);
886
887 mask = is_output ? FMT_FLAGS_M2M : FMT_FLAGS_M2M | FMT_FLAGS_CAM;
888 fmt = find_format(f, mask);
889 if (!fmt) {
890 v4l2_err(&fimc->m2m.v4l2_dev, "Fourcc format (0x%X) invalid.\n",
891 pix->pixelformat);
892 return -EINVAL;
893 }
894
895 if (pix->field == V4L2_FIELD_ANY)
896 pix->field = V4L2_FIELD_NONE;
897 else if (V4L2_FIELD_NONE != pix->field)
898 return -EINVAL;
899
900 if (is_output) {
901 max_width = variant->pix_limit->scaler_dis_w;
902 mod_x = ffs(variant->min_inp_pixsize) - 1;
903 } else {
904 max_width = variant->pix_limit->out_rot_dis_w;
905 mod_x = ffs(variant->min_out_pixsize) - 1;
906 }
907
908 if (tiled_fmt(fmt)) {
909 mod_x = 6; /* 64 x 32 pixels tile */
910 mod_y = 5;
911 } else {
912 if (fimc->id == 1 && variant->pix_hoff)
913 mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
914 else
915 mod_y = mod_x;
916 }
917
918 dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x, mod_y, max_width);
919
920 v4l_bound_align_image(&pix->width, 16, max_width, mod_x,
921 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
922
923 pix->num_planes = fmt->memplanes;
924 pix->colorspace = V4L2_COLORSPACE_JPEG;
925
926
927 for (i = 0; i < pix->num_planes; ++i) {
928 u32 bpl = pix->plane_fmt[i].bytesperline;
929 u32 *sizeimage = &pix->plane_fmt[i].sizeimage;
930
931 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
932 bpl = pix->width; /* Planar */
933
934 if (fmt->colplanes == 1 && /* Packed */
935 (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
936 bpl = (pix->width * fmt->depth[0]) / 8;
937
938 if (i == 0) /* Same bytesperline for each plane. */
939 mod_x = bpl;
940
941 pix->plane_fmt[i].bytesperline = mod_x;
942 *sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8;
943 }
944
945 return 0;
946}
947
948static int fimc_m2m_s_fmt_mplane(struct file *file, void *priv,
949 struct v4l2_format *f)
950{
951 struct fimc_ctx *ctx = priv;
952 struct fimc_dev *fimc = ctx->fimc_dev;
953 struct vb2_queue *vq;
954 struct fimc_frame *frame;
955 struct v4l2_pix_format_mplane *pix;
956 int i, ret = 0;
957
958 ret = fimc_vidioc_try_fmt_mplane(file, priv, f);
959 if (ret)
960 return ret;
961
962 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
963
964 if (vb2_is_busy(vq)) {
965 v4l2_err(&fimc->m2m.v4l2_dev, "queue (%d) busy\n", f->type);
966 return -EBUSY;
967 }
968
969 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
970 frame = &ctx->s_frame;
971 } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
972 frame = &ctx->d_frame;
973 } else {
974 v4l2_err(&fimc->m2m.v4l2_dev,
975 "Wrong buffer/video queue type (%d)\n", f->type);
976 return -EINVAL;
977 }
978
979 pix = &f->fmt.pix_mp;
980 frame->fmt = find_format(f, FMT_FLAGS_M2M);
981 if (!frame->fmt)
982 return -EINVAL;
983
984 for (i = 0; i < frame->fmt->colplanes; i++) {
985 frame->payload[i] =
986 (pix->width * pix->height * frame->fmt->depth[i]) / 8;
987 }
988
989 frame->f_width = pix->plane_fmt[0].bytesperline * 8 /
990 frame->fmt->depth[0];
991 frame->f_height = pix->height;
992 frame->width = pix->width;
993 frame->height = pix->height;
994 frame->o_width = pix->width;
995 frame->o_height = pix->height;
996 frame->offs_h = 0;
997 frame->offs_v = 0;
998
999 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1000 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
1001 else
1002 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
1003
1004 dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
1005
1006 return 0;
1007}
1008
1009static int fimc_m2m_reqbufs(struct file *file, void *priv,
1010 struct v4l2_requestbuffers *reqbufs)
1011{
1012 struct fimc_ctx *ctx = priv;
1013 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1014}
1015
1016static int fimc_m2m_querybuf(struct file *file, void *priv,
1017 struct v4l2_buffer *buf)
1018{
1019 struct fimc_ctx *ctx = priv;
1020 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1021}
1022
1023static int fimc_m2m_qbuf(struct file *file, void *priv,
1024 struct v4l2_buffer *buf)
1025{
1026 struct fimc_ctx *ctx = priv;
1027
1028 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1029}
1030
1031static int fimc_m2m_dqbuf(struct file *file, void *priv,
1032 struct v4l2_buffer *buf)
1033{
1034 struct fimc_ctx *ctx = priv;
1035 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1036}
1037
1038static int fimc_m2m_streamon(struct file *file, void *priv,
1039 enum v4l2_buf_type type)
1040{
1041 struct fimc_ctx *ctx = priv;
1042
1043 /* The source and target color format need to be set */
1044 if (V4L2_TYPE_IS_OUTPUT(type)) {
1045 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT, ctx))
1046 return -EINVAL;
1047 } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT, ctx)) {
1048 return -EINVAL;
1049 }
1050
1051 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1052}
1053
1054static int fimc_m2m_streamoff(struct file *file, void *priv,
1055 enum v4l2_buf_type type)
1056{
1057 struct fimc_ctx *ctx = priv;
1058 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1059}
1060
1061int fimc_vidioc_queryctrl(struct file *file, void *priv,
1062 struct v4l2_queryctrl *qc)
1063{
1064 struct fimc_ctx *ctx = priv;
1065 struct v4l2_queryctrl *c;
1066 int ret = -EINVAL;
1067
1068 c = get_ctrl(qc->id);
1069 if (c) {
1070 *qc = *c;
1071 return 0;
1072 }
1073
1074 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx)) {
1075 return v4l2_subdev_call(ctx->fimc_dev->vid_cap.sd,
1076 core, queryctrl, qc);
1077 }
1078 return ret;
1079}
1080
1081int fimc_vidioc_g_ctrl(struct file *file, void *priv,
1082 struct v4l2_control *ctrl)
1083{
1084 struct fimc_ctx *ctx = priv;
1085 struct fimc_dev *fimc = ctx->fimc_dev;
1086
1087 switch (ctrl->id) {
1088 case V4L2_CID_HFLIP:
1089 ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
1090 break;
1091 case V4L2_CID_VFLIP:
1092 ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
1093 break;
1094 case V4L2_CID_ROTATE:
1095 ctrl->value = ctx->rotation;
1096 break;
1097 default:
1098 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx)) {
1099 return v4l2_subdev_call(fimc->vid_cap.sd, core,
1100 g_ctrl, ctrl);
1101 } else {
1102 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
1103 return -EINVAL;
1104 }
1105 }
1106 dbg("ctrl->value= %d", ctrl->value);
1107
1108 return 0;
1109}
1110
1111int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1112{
1113 struct v4l2_queryctrl *c;
1114 c = get_ctrl(ctrl->id);
1115 if (!c)
1116 return -EINVAL;
1117
1118 if (ctrl->value < c->minimum || ctrl->value > c->maximum
1119 || (c->step != 0 && ctrl->value % c->step != 0)) {
1120 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
1121 "Invalid control value\n");
1122 return -ERANGE;
1123 }
1124
1125 return 0;
1126}
1127
1128int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1129{
1130 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
1131 struct fimc_dev *fimc = ctx->fimc_dev;
1132 int ret = 0;
1133
1134 switch (ctrl->id) {
1135 case V4L2_CID_HFLIP:
1136 if (ctrl->value)
1137 ctx->flip |= FLIP_X_AXIS;
1138 else
1139 ctx->flip &= ~FLIP_X_AXIS;
1140 break;
1141
1142 case V4L2_CID_VFLIP:
1143 if (ctrl->value)
1144 ctx->flip |= FLIP_Y_AXIS;
1145 else
1146 ctx->flip &= ~FLIP_Y_AXIS;
1147 break;
1148
1149 case V4L2_CID_ROTATE:
1150 if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1151 ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1152 ctx->s_frame.height, ctx->d_frame.width,
1153 ctx->d_frame.height, ctrl->value);
1154 }
1155
1156 if (ret) {
1157 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range\n");
1158 return -EINVAL;
1159 }
1160
1161 /* Check for the output rotator availability */
1162 if ((ctrl->value == 90 || ctrl->value == 270) &&
1163 (ctx->in_path == FIMC_DMA && !variant->has_out_rot))
1164 return -EINVAL;
1165 ctx->rotation = ctrl->value;
1166 break;
1167
1168 default:
1169 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
1170 return -EINVAL;
1171 }
1172
1173 fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1174
1175 return 0;
1176}
1177
1178static int fimc_m2m_s_ctrl(struct file *file, void *priv,
1179 struct v4l2_control *ctrl)
1180{
1181 struct fimc_ctx *ctx = priv;
1182 int ret = 0;
1183
1184 ret = check_ctrl_val(ctx, ctrl);
1185 if (ret)
1186 return ret;
1187
1188 ret = fimc_s_ctrl(ctx, ctrl);
1189 return 0;
1190}
1191
1192static int fimc_m2m_cropcap(struct file *file, void *fh,
1193 struct v4l2_cropcap *cr)
1194{
1195 struct fimc_frame *frame;
1196 struct fimc_ctx *ctx = fh;
1197
1198 frame = ctx_get_frame(ctx, cr->type);
1199 if (IS_ERR(frame))
1200 return PTR_ERR(frame);
1201
1202 cr->bounds.left = 0;
1203 cr->bounds.top = 0;
1204 cr->bounds.width = frame->f_width;
1205 cr->bounds.height = frame->f_height;
1206 cr->defrect = cr->bounds;
1207
1208 return 0;
1209}
1210
1211static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1212{
1213 struct fimc_frame *frame;
1214 struct fimc_ctx *ctx = file->private_data;
1215
1216 frame = ctx_get_frame(ctx, cr->type);
1217 if (IS_ERR(frame))
1218 return PTR_ERR(frame);
1219
1220 cr->c.left = frame->offs_h;
1221 cr->c.top = frame->offs_v;
1222 cr->c.width = frame->width;
1223 cr->c.height = frame->height;
1224
1225 return 0;
1226}
1227
1228int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1229{
1230 struct fimc_dev *fimc = ctx->fimc_dev;
1231 struct fimc_frame *f;
1232 u32 min_size, halign, depth = 0;
1233 bool is_capture_ctx;
1234 int i;
1235
1236 if (cr->c.top < 0 || cr->c.left < 0) {
1237 v4l2_err(&fimc->m2m.v4l2_dev,
1238 "doesn't support negative values for top & left\n");
1239 return -EINVAL;
1240 }
1241
1242 is_capture_ctx = fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx);
1243
1244 if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1245 f = is_capture_ctx ? &ctx->s_frame : &ctx->d_frame;
1246 else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
1247 !is_capture_ctx)
1248 f = &ctx->s_frame;
1249 else
1250 return -EINVAL;
1251
1252 min_size = (f == &ctx->s_frame) ?
1253 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1254
1255 /* Get pixel alignment constraints. */
1256 if (is_capture_ctx) {
1257 min_size = 16;
1258 halign = 4;
1259 } else {
1260 if (fimc->id == 1 && fimc->variant->pix_hoff)
1261 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1262 else
1263 halign = ffs(min_size) - 1;
1264 }
1265
1266 for (i = 0; i < f->fmt->colplanes; i++)
1267 depth += f->fmt->depth[i];
1268
1269 v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1270 ffs(min_size) - 1,
1271 &cr->c.height, min_size, f->o_height,
1272 halign, 64/(ALIGN(depth, 8)));
1273
1274 /* adjust left/top if cropping rectangle is out of bounds */
1275 if (cr->c.left + cr->c.width > f->o_width)
1276 cr->c.left = f->o_width - cr->c.width;
1277 if (cr->c.top + cr->c.height > f->o_height)
1278 cr->c.top = f->o_height - cr->c.height;
1279
1280 cr->c.left = round_down(cr->c.left, min_size);
1281 cr->c.top = round_down(cr->c.top, is_capture_ctx ? 16 : 8);
1282
1283 dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1284 cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1285 f->f_width, f->f_height);
1286
1287 return 0;
1288}
1289
1290static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1291{
1292 struct fimc_ctx *ctx = file->private_data;
1293 struct fimc_dev *fimc = ctx->fimc_dev;
1294 struct fimc_frame *f;
1295 int ret;
1296
1297 ret = fimc_try_crop(ctx, cr);
1298 if (ret)
1299 return ret;
1300
1301 f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1302 &ctx->s_frame : &ctx->d_frame;
1303
1304 /* Check to see if scaling ratio is within supported range */
1305 if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1306 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1307 ret = fimc_check_scaler_ratio(cr->c.width, cr->c.height,
1308 ctx->d_frame.width,
1309 ctx->d_frame.height,
1310 ctx->rotation);
1311 } else {
1312 ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1313 ctx->s_frame.height,
1314 cr->c.width, cr->c.height,
1315 ctx->rotation);
1316 }
1317 if (ret) {
1318 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range\n");
1319 return -EINVAL;
1320 }
1321 }
1322
1323 f->offs_h = cr->c.left;
1324 f->offs_v = cr->c.top;
1325 f->width = cr->c.width;
1326 f->height = cr->c.height;
1327
1328 fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1329
1330 return 0;
1331}
1332
1333static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1334 .vidioc_querycap = fimc_m2m_querycap,
1335
1336 .vidioc_enum_fmt_vid_cap_mplane = fimc_vidioc_enum_fmt_mplane,
1337 .vidioc_enum_fmt_vid_out_mplane = fimc_vidioc_enum_fmt_mplane,
1338
1339 .vidioc_g_fmt_vid_cap_mplane = fimc_vidioc_g_fmt_mplane,
1340 .vidioc_g_fmt_vid_out_mplane = fimc_vidioc_g_fmt_mplane,
1341
1342 .vidioc_try_fmt_vid_cap_mplane = fimc_vidioc_try_fmt_mplane,
1343 .vidioc_try_fmt_vid_out_mplane = fimc_vidioc_try_fmt_mplane,
1344
1345 .vidioc_s_fmt_vid_cap_mplane = fimc_m2m_s_fmt_mplane,
1346 .vidioc_s_fmt_vid_out_mplane = fimc_m2m_s_fmt_mplane,
1347
1348 .vidioc_reqbufs = fimc_m2m_reqbufs,
1349 .vidioc_querybuf = fimc_m2m_querybuf,
1350
1351 .vidioc_qbuf = fimc_m2m_qbuf,
1352 .vidioc_dqbuf = fimc_m2m_dqbuf,
1353
1354 .vidioc_streamon = fimc_m2m_streamon,
1355 .vidioc_streamoff = fimc_m2m_streamoff,
1356
1357 .vidioc_queryctrl = fimc_vidioc_queryctrl,
1358 .vidioc_g_ctrl = fimc_vidioc_g_ctrl,
1359 .vidioc_s_ctrl = fimc_m2m_s_ctrl,
1360
1361 .vidioc_g_crop = fimc_m2m_g_crop,
1362 .vidioc_s_crop = fimc_m2m_s_crop,
1363 .vidioc_cropcap = fimc_m2m_cropcap
1364
1365};
1366
1367static int queue_init(void *priv, struct vb2_queue *src_vq,
1368 struct vb2_queue *dst_vq)
1369{
1370 struct fimc_ctx *ctx = priv;
1371 int ret;
1372
1373 memset(src_vq, 0, sizeof(*src_vq));
1374 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1375 src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1376 src_vq->drv_priv = ctx;
1377 src_vq->ops = &fimc_qops;
1378 src_vq->mem_ops = &vb2_dma_contig_memops;
1379 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1380
1381 ret = vb2_queue_init(src_vq);
1382 if (ret)
1383 return ret;
1384
1385 memset(dst_vq, 0, sizeof(*dst_vq));
1386 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1387 dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1388 dst_vq->drv_priv = ctx;
1389 dst_vq->ops = &fimc_qops;
1390 dst_vq->mem_ops = &vb2_dma_contig_memops;
1391 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1392
1393 return vb2_queue_init(dst_vq);
1394}
1395
1396static int fimc_m2m_open(struct file *file)
1397{
1398 struct fimc_dev *fimc = video_drvdata(file);
1399 struct fimc_ctx *ctx = NULL;
1400
1401 dbg("pid: %d, state: 0x%lx, refcnt: %d",
1402 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1403
1404 /*
1405 * Return if the corresponding video capture node
1406 * is already opened.
1407 */
1408 if (fimc->vid_cap.refcnt > 0)
1409 return -EBUSY;
1410
1411 fimc->m2m.refcnt++;
1412 set_bit(ST_OUTDMA_RUN, &fimc->state);
1413
1414 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1415 if (!ctx)
1416 return -ENOMEM;
1417
1418 file->private_data = ctx;
1419 ctx->fimc_dev = fimc;
1420 /* Default color format */
1421 ctx->s_frame.fmt = &fimc_formats[0];
1422 ctx->d_frame.fmt = &fimc_formats[0];
1423 /* Setup the device context for mem2mem mode. */
1424 ctx->state = FIMC_CTX_M2M;
1425 ctx->flags = 0;
1426 ctx->in_path = FIMC_DMA;
1427 ctx->out_path = FIMC_DMA;
1428 spin_lock_init(&ctx->slock);
1429
1430 ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1431 if (IS_ERR(ctx->m2m_ctx)) {
1432 int err = PTR_ERR(ctx->m2m_ctx);
1433 kfree(ctx);
1434 return err;
1435 }
1436
1437 return 0;
1438}
1439
1440static int fimc_m2m_release(struct file *file)
1441{
1442 struct fimc_ctx *ctx = file->private_data;
1443 struct fimc_dev *fimc = ctx->fimc_dev;
1444
1445 dbg("pid: %d, state: 0x%lx, refcnt= %d",
1446 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1447
1448 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1449 kfree(ctx);
1450 if (--fimc->m2m.refcnt <= 0)
1451 clear_bit(ST_OUTDMA_RUN, &fimc->state);
1452
1453 return 0;
1454}
1455
1456static unsigned int fimc_m2m_poll(struct file *file,
1457 struct poll_table_struct *wait)
1458{
1459 struct fimc_ctx *ctx = file->private_data;
1460
1461 return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1462}
1463
1464
1465static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1466{
1467 struct fimc_ctx *ctx = file->private_data;
1468
1469 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1470}
1471
1472static const struct v4l2_file_operations fimc_m2m_fops = {
1473 .owner = THIS_MODULE,
1474 .open = fimc_m2m_open,
1475 .release = fimc_m2m_release,
1476 .poll = fimc_m2m_poll,
1477 .unlocked_ioctl = video_ioctl2,
1478 .mmap = fimc_m2m_mmap,
1479};
1480
1481static struct v4l2_m2m_ops m2m_ops = {
1482 .device_run = fimc_dma_run,
1483 .job_abort = fimc_job_abort,
1484};
1485
1486static int fimc_register_m2m_device(struct fimc_dev *fimc)
1487{
1488 struct video_device *vfd;
1489 struct platform_device *pdev;
1490 struct v4l2_device *v4l2_dev;
1491 int ret = 0;
1492
1493 if (!fimc)
1494 return -ENODEV;
1495
1496 pdev = fimc->pdev;
1497 v4l2_dev = &fimc->m2m.v4l2_dev;
1498
1499 /* set name if it is empty */
1500 if (!v4l2_dev->name[0])
1501 snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
1502 "%s.m2m", dev_name(&pdev->dev));
1503
1504 ret = v4l2_device_register(&pdev->dev, v4l2_dev);
1505 if (ret)
1506 goto err_m2m_r1;
1507
1508 vfd = video_device_alloc();
1509 if (!vfd) {
1510 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1511 goto err_m2m_r1;
1512 }
1513
1514 vfd->fops = &fimc_m2m_fops;
1515 vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
1516 vfd->minor = -1;
1517 vfd->release = video_device_release;
1518 vfd->lock = &fimc->lock;
1519
1520 snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
1521
1522 video_set_drvdata(vfd, fimc);
1523 platform_set_drvdata(pdev, fimc);
1524
1525 fimc->m2m.vfd = vfd;
1526 fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1527 if (IS_ERR(fimc->m2m.m2m_dev)) {
1528 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1529 ret = PTR_ERR(fimc->m2m.m2m_dev);
1530 goto err_m2m_r2;
1531 }
1532
1533 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
1534 if (ret) {
1535 v4l2_err(v4l2_dev,
1536 "%s(): failed to register video device\n", __func__);
1537 goto err_m2m_r3;
1538 }
1539 v4l2_info(v4l2_dev,
1540 "FIMC m2m driver registered as /dev/video%d\n", vfd->num);
1541
1542 return 0;
1543
1544err_m2m_r3:
1545 v4l2_m2m_release(fimc->m2m.m2m_dev);
1546err_m2m_r2:
1547 video_device_release(fimc->m2m.vfd);
1548err_m2m_r1:
1549 v4l2_device_unregister(v4l2_dev);
1550
1551 return ret;
1552}
1553
1554static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1555{
1556 if (fimc) {
1557 v4l2_m2m_release(fimc->m2m.m2m_dev);
1558 video_unregister_device(fimc->m2m.vfd);
1559
1560 v4l2_device_unregister(&fimc->m2m.v4l2_dev);
1561 }
1562}
1563
1564static void fimc_clk_release(struct fimc_dev *fimc)
1565{
1566 int i;
1567 for (i = 0; i < fimc->num_clocks; i++) {
1568 if (fimc->clock[i]) {
1569 clk_disable(fimc->clock[i]);
1570 clk_put(fimc->clock[i]);
1571 }
1572 }
1573}
1574
1575static int fimc_clk_get(struct fimc_dev *fimc)
1576{
1577 int i;
1578 for (i = 0; i < fimc->num_clocks; i++) {
1579 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1580
1581 if (!IS_ERR_OR_NULL(fimc->clock[i])) {
1582 clk_enable(fimc->clock[i]);
1583 continue;
1584 }
1585 dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
1586 fimc_clocks[i]);
1587 return -ENXIO;
1588 }
1589 return 0;
1590}
1591
1592static int fimc_probe(struct platform_device *pdev)
1593{
1594 struct fimc_dev *fimc;
1595 struct resource *res;
1596 struct samsung_fimc_driverdata *drv_data;
1597 struct s5p_platform_fimc *pdata;
1598 int ret = 0;
1599 int cap_input_index = -1;
1600
1601 dev_dbg(&pdev->dev, "%s():\n", __func__);
1602
1603 drv_data = (struct samsung_fimc_driverdata *)
1604 platform_get_device_id(pdev)->driver_data;
1605
1606 if (pdev->id >= drv_data->num_entities) {
1607 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1608 pdev->id);
1609 return -EINVAL;
1610 }
1611
1612 fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1613 if (!fimc)
1614 return -ENOMEM;
1615
1616 fimc->id = pdev->id;
1617 fimc->variant = drv_data->variant[fimc->id];
1618 fimc->pdev = pdev;
1619 pdata = pdev->dev.platform_data;
1620 fimc->pdata = pdata;
1621 fimc->state = ST_IDLE;
1622
1623 init_waitqueue_head(&fimc->irq_queue);
1624 spin_lock_init(&fimc->slock);
1625
1626 mutex_init(&fimc->lock);
1627
1628 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1629 if (!res) {
1630 dev_err(&pdev->dev, "failed to find the registers\n");
1631 ret = -ENOENT;
1632 goto err_info;
1633 }
1634
1635 fimc->regs_res = request_mem_region(res->start, resource_size(res),
1636 dev_name(&pdev->dev));
1637 if (!fimc->regs_res) {
1638 dev_err(&pdev->dev, "failed to obtain register region\n");
1639 ret = -ENOENT;
1640 goto err_info;
1641 }
1642
1643 fimc->regs = ioremap(res->start, resource_size(res));
1644 if (!fimc->regs) {
1645 dev_err(&pdev->dev, "failed to map registers\n");
1646 ret = -ENXIO;
1647 goto err_req_region;
1648 }
1649
1650 fimc->num_clocks = MAX_FIMC_CLOCKS - 1;
1651
1652 /* Check if a video capture node needs to be registered. */
1653 if (pdata && pdata->num_clients > 0) {
1654 cap_input_index = 0;
1655 fimc->num_clocks++;
1656 }
1657
1658 ret = fimc_clk_get(fimc);
1659 if (ret)
1660 goto err_regs_unmap;
1661 clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1662
1663 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1664 if (!res) {
1665 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1666 ret = -ENXIO;
1667 goto err_clk;
1668 }
1669 fimc->irq = res->start;
1670
1671 fimc_hw_reset(fimc);
1672
1673 ret = request_irq(fimc->irq, fimc_isr, 0, pdev->name, fimc);
1674 if (ret) {
1675 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1676 goto err_clk;
1677 }
1678
1679 /* Initialize contiguous memory allocator */
1680 fimc->alloc_ctx = vb2_dma_contig_init_ctx(&fimc->pdev->dev);
1681 if (IS_ERR(fimc->alloc_ctx)) {
1682 ret = PTR_ERR(fimc->alloc_ctx);
1683 goto err_irq;
1684 }
1685
1686 ret = fimc_register_m2m_device(fimc);
1687 if (ret)
1688 goto err_irq;
1689
1690 /* At least one camera sensor is required to register capture node */
1691 if (cap_input_index >= 0) {
1692 ret = fimc_register_capture_device(fimc);
1693 if (ret)
1694 goto err_m2m;
1695 clk_disable(fimc->clock[CLK_CAM]);
1696 }
1697 /*
1698 * Exclude the additional output DMA address registers by masking
1699 * them out on HW revisions that provide extended capabilites.
1700 */
1701 if (fimc->variant->out_buf_count > 4)
1702 fimc_hw_set_dma_seq(fimc, 0xF);
1703
1704 dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
1705 __func__, fimc->id);
1706
1707 return 0;
1708
1709err_m2m:
1710 fimc_unregister_m2m_device(fimc);
1711err_irq:
1712 free_irq(fimc->irq, fimc);
1713err_clk:
1714 fimc_clk_release(fimc);
1715err_regs_unmap:
1716 iounmap(fimc->regs);
1717err_req_region:
1718 release_resource(fimc->regs_res);
1719 kfree(fimc->regs_res);
1720err_info:
1721 kfree(fimc);
1722
1723 return ret;
1724}
1725
1726static int __devexit fimc_remove(struct platform_device *pdev)
1727{
1728 struct fimc_dev *fimc =
1729 (struct fimc_dev *)platform_get_drvdata(pdev);
1730
1731 free_irq(fimc->irq, fimc);
1732 fimc_hw_reset(fimc);
1733
1734 fimc_unregister_m2m_device(fimc);
1735 fimc_unregister_capture_device(fimc);
1736
1737 fimc_clk_release(fimc);
1738
1739 vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1740
1741 iounmap(fimc->regs);
1742 release_resource(fimc->regs_res);
1743 kfree(fimc->regs_res);
1744 kfree(fimc);
1745
1746 dev_info(&pdev->dev, "%s driver unloaded\n", pdev->name);
1747 return 0;
1748}
1749
1750/* Image pixel limits, similar across several FIMC HW revisions. */
1751static struct fimc_pix_limit s5p_pix_limit[4] = {
1752 [0] = {
1753 .scaler_en_w = 3264,
1754 .scaler_dis_w = 8192,
1755 .in_rot_en_h = 1920,
1756 .in_rot_dis_w = 8192,
1757 .out_rot_en_w = 1920,
1758 .out_rot_dis_w = 4224,
1759 },
1760 [1] = {
1761 .scaler_en_w = 4224,
1762 .scaler_dis_w = 8192,
1763 .in_rot_en_h = 1920,
1764 .in_rot_dis_w = 8192,
1765 .out_rot_en_w = 1920,
1766 .out_rot_dis_w = 4224,
1767 },
1768 [2] = {
1769 .scaler_en_w = 1920,
1770 .scaler_dis_w = 8192,
1771 .in_rot_en_h = 1280,
1772 .in_rot_dis_w = 8192,
1773 .out_rot_en_w = 1280,
1774 .out_rot_dis_w = 1920,
1775 },
1776 [3] = {
1777 .scaler_en_w = 1920,
1778 .scaler_dis_w = 8192,
1779 .in_rot_en_h = 1366,
1780 .in_rot_dis_w = 8192,
1781 .out_rot_en_w = 1366,
1782 .out_rot_dis_w = 1920,
1783 },
1784};
1785
1786static struct samsung_fimc_variant fimc0_variant_s5p = {
1787 .has_inp_rot = 1,
1788 .has_out_rot = 1,
1789 .min_inp_pixsize = 16,
1790 .min_out_pixsize = 16,
1791 .hor_offs_align = 8,
1792 .out_buf_count = 4,
1793 .pix_limit = &s5p_pix_limit[0],
1794};
1795
1796static struct samsung_fimc_variant fimc2_variant_s5p = {
1797 .min_inp_pixsize = 16,
1798 .min_out_pixsize = 16,
1799 .hor_offs_align = 8,
1800 .out_buf_count = 4,
1801 .pix_limit = &s5p_pix_limit[1],
1802};
1803
1804static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1805 .pix_hoff = 1,
1806 .has_inp_rot = 1,
1807 .has_out_rot = 1,
1808 .min_inp_pixsize = 16,
1809 .min_out_pixsize = 16,
1810 .hor_offs_align = 8,
1811 .out_buf_count = 4,
1812 .pix_limit = &s5p_pix_limit[1],
1813};
1814
1815static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1816 .pix_hoff = 1,
1817 .has_inp_rot = 1,
1818 .has_out_rot = 1,
1819 .has_mainscaler_ext = 1,
1820 .min_inp_pixsize = 16,
1821 .min_out_pixsize = 16,
1822 .hor_offs_align = 1,
1823 .out_buf_count = 4,
1824 .pix_limit = &s5p_pix_limit[2],
1825};
1826
1827static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1828 .pix_hoff = 1,
1829 .min_inp_pixsize = 16,
1830 .min_out_pixsize = 16,
1831 .hor_offs_align = 8,
1832 .out_buf_count = 4,
1833 .pix_limit = &s5p_pix_limit[2],
1834};
1835
1836static struct samsung_fimc_variant fimc0_variant_exynos4 = {
1837 .pix_hoff = 1,
1838 .has_inp_rot = 1,
1839 .has_out_rot = 1,
1840 .has_cistatus2 = 1,
1841 .has_mainscaler_ext = 1,
1842 .min_inp_pixsize = 16,
1843 .min_out_pixsize = 16,
1844 .hor_offs_align = 1,
1845 .out_buf_count = 32,
1846 .pix_limit = &s5p_pix_limit[1],
1847};
1848
1849static struct samsung_fimc_variant fimc2_variant_exynos4 = {
1850 .pix_hoff = 1,
1851 .has_cistatus2 = 1,
1852 .has_mainscaler_ext = 1,
1853 .min_inp_pixsize = 16,
1854 .min_out_pixsize = 16,
1855 .hor_offs_align = 1,
1856 .out_buf_count = 32,
1857 .pix_limit = &s5p_pix_limit[3],
1858};
1859
1860/* S5PC100 */
1861static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1862 .variant = {
1863 [0] = &fimc0_variant_s5p,
1864 [1] = &fimc0_variant_s5p,
1865 [2] = &fimc2_variant_s5p,
1866 },
1867 .num_entities = 3,
1868 .lclk_frequency = 133000000UL,
1869};
1870
1871/* S5PV210, S5PC110 */
1872static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1873 .variant = {
1874 [0] = &fimc0_variant_s5pv210,
1875 [1] = &fimc1_variant_s5pv210,
1876 [2] = &fimc2_variant_s5pv210,
1877 },
1878 .num_entities = 3,
1879 .lclk_frequency = 166000000UL,
1880};
1881
1882/* S5PV310, S5PC210 */
1883static struct samsung_fimc_driverdata fimc_drvdata_exynos4 = {
1884 .variant = {
1885 [0] = &fimc0_variant_exynos4,
1886 [1] = &fimc0_variant_exynos4,
1887 [2] = &fimc0_variant_exynos4,
1888 [3] = &fimc2_variant_exynos4,
1889 },
1890 .num_entities = 4,
1891 .lclk_frequency = 166000000UL,
1892};
1893
1894static struct platform_device_id fimc_driver_ids[] = {
1895 {
1896 .name = "s5p-fimc",
1897 .driver_data = (unsigned long)&fimc_drvdata_s5p,
1898 }, {
1899 .name = "s5pv210-fimc",
1900 .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
1901 }, {
1902 .name = "exynos4-fimc",
1903 .driver_data = (unsigned long)&fimc_drvdata_exynos4,
1904 },
1905 {},
1906};
1907MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1908
1909static struct platform_driver fimc_driver = {
1910 .probe = fimc_probe,
1911 .remove = __devexit_p(fimc_remove),
1912 .id_table = fimc_driver_ids,
1913 .driver = {
1914 .name = MODULE_NAME,
1915 .owner = THIS_MODULE,
1916 }
1917};
1918
1919static int __init fimc_init(void)
1920{
1921 int ret = platform_driver_register(&fimc_driver);
1922 if (ret)
1923 err("platform_driver_register failed: %d\n", ret);
1924 return ret;
1925}
1926
1927static void __exit fimc_exit(void)
1928{
1929 platform_driver_unregister(&fimc_driver);
1930}
1931
1932module_init(fimc_init);
1933module_exit(fimc_exit);
1934
1935MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1936MODULE_DESCRIPTION("S5P FIMC camera host interface/video postprocessor driver");
1937MODULE_LICENSE("GPL");
1938MODULE_VERSION("1.0.1");
diff --git a/drivers/media/video/s5p-fimc/fimc-core.h b/drivers/media/video/s5p-fimc/fimc-core.h
new file mode 100644
index 00000000000..1f70772daaf
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/fimc-core.h
@@ -0,0 +1,707 @@
1/*
2 * Copyright (C) 2010 - 2011 Samsung Electronics Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef FIMC_CORE_H_
10#define FIMC_CORE_H_
11
12/*#define DEBUG*/
13
14#include <linux/sched.h>
15#include <linux/spinlock.h>
16#include <linux/types.h>
17#include <linux/videodev2.h>
18#include <linux/io.h>
19#include <media/videobuf2-core.h>
20#include <media/v4l2-device.h>
21#include <media/v4l2-mem2mem.h>
22#include <media/v4l2-mediabus.h>
23#include <media/s5p_fimc.h>
24
25#include "regs-fimc.h"
26
27#define err(fmt, args...) \
28 printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
29
30#define dbg(fmt, args...) \
31 pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
32
33/* Time to wait for next frame VSYNC interrupt while stopping operation. */
34#define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
35#define MAX_FIMC_CLOCKS 3
36#define MODULE_NAME "s5p-fimc"
37#define FIMC_MAX_DEVS 4
38#define FIMC_MAX_OUT_BUFS 4
39#define SCALER_MAX_HRATIO 64
40#define SCALER_MAX_VRATIO 64
41#define DMA_MIN_SIZE 8
42
43/* indices to the clocks array */
44enum {
45 CLK_BUS,
46 CLK_GATE,
47 CLK_CAM,
48};
49
50enum fimc_dev_flags {
51 /* for m2m node */
52 ST_IDLE,
53 ST_OUTDMA_RUN,
54 ST_M2M_PEND,
55 /* for capture node */
56 ST_CAPT_PEND,
57 ST_CAPT_RUN,
58 ST_CAPT_STREAM,
59 ST_CAPT_SHUT,
60};
61
62#define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
63#define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
64
65#define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
66#define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
67
68enum fimc_datapath {
69 FIMC_CAMERA,
70 FIMC_DMA,
71 FIMC_LCDFIFO,
72 FIMC_WRITEBACK
73};
74
75enum fimc_color_fmt {
76 S5P_FIMC_RGB565 = 0x10,
77 S5P_FIMC_RGB666,
78 S5P_FIMC_RGB888,
79 S5P_FIMC_RGB30_LOCAL,
80 S5P_FIMC_YCBCR420 = 0x20,
81 S5P_FIMC_YCBYCR422,
82 S5P_FIMC_YCRYCB422,
83 S5P_FIMC_CBYCRY422,
84 S5P_FIMC_CRYCBY422,
85 S5P_FIMC_YCBCR444_LOCAL,
86};
87
88#define fimc_fmt_is_rgb(x) ((x) & 0x10)
89
90/* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
91#define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
92
93/* The embedded image effect selection */
94#define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS
95#define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY
96#define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE
97#define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE
98#define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING
99#define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE
100
101/* The hardware context state. */
102#define FIMC_PARAMS (1 << 0)
103#define FIMC_SRC_ADDR (1 << 1)
104#define FIMC_DST_ADDR (1 << 2)
105#define FIMC_SRC_FMT (1 << 3)
106#define FIMC_DST_FMT (1 << 4)
107#define FIMC_CTX_M2M (1 << 5)
108#define FIMC_CTX_CAP (1 << 6)
109#define FIMC_CTX_SHUT (1 << 7)
110
111/* Image conversion flags */
112#define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
113#define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
114#define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
115#define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
116#define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
117#define FIMC_SCAN_MODE_INTERLACED (1 << 2)
118/*
119 * YCbCr data dynamic range for RGB-YUV color conversion.
120 * Y/Cb/Cr: (0 ~ 255) */
121#define FIMC_COLOR_RANGE_WIDE (0 << 3)
122/* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
123#define FIMC_COLOR_RANGE_NARROW (1 << 3)
124
125#define FLIP_NONE 0
126#define FLIP_X_AXIS 1
127#define FLIP_Y_AXIS 2
128#define FLIP_XY_AXIS (FLIP_X_AXIS | FLIP_Y_AXIS)
129
130/**
131 * struct fimc_fmt - the driver's internal color format data
132 * @mbus_code: Media Bus pixel code, -1 if not applicable
133 * @name: format description
134 * @fourcc: the fourcc code for this format, 0 if not applicable
135 * @color: the corresponding fimc_color_fmt
136 * @memplanes: number of physically non-contiguous data planes
137 * @colplanes: number of physically contiguous data planes
138 * @depth: per plane driver's private 'number of bits per pixel'
139 * @flags: flags indicating which operation mode format applies to
140 */
141struct fimc_fmt {
142 enum v4l2_mbus_pixelcode mbus_code;
143 char *name;
144 u32 fourcc;
145 u32 color;
146 u16 memplanes;
147 u16 colplanes;
148 u8 depth[VIDEO_MAX_PLANES];
149 u16 flags;
150#define FMT_FLAGS_CAM (1 << 0)
151#define FMT_FLAGS_M2M (1 << 1)
152};
153
154/**
155 * struct fimc_dma_offset - pixel offset information for DMA
156 * @y_h: y value horizontal offset
157 * @y_v: y value vertical offset
158 * @cb_h: cb value horizontal offset
159 * @cb_v: cb value vertical offset
160 * @cr_h: cr value horizontal offset
161 * @cr_v: cr value vertical offset
162 */
163struct fimc_dma_offset {
164 int y_h;
165 int y_v;
166 int cb_h;
167 int cb_v;
168 int cr_h;
169 int cr_v;
170};
171
172/**
173 * struct fimc_effect - color effect information
174 * @type: effect type
175 * @pat_cb: cr value when type is "arbitrary"
176 * @pat_cr: cr value when type is "arbitrary"
177 */
178struct fimc_effect {
179 u32 type;
180 u8 pat_cb;
181 u8 pat_cr;
182};
183
184/**
185 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
186 * @scaleup_h: flag indicating scaling up horizontally
187 * @scaleup_v: flag indicating scaling up vertically
188 * @copy_mode: flag indicating transparent DMA transfer (no scaling
189 * and color format conversion)
190 * @enabled: flag indicating if the scaler is used
191 * @hfactor: horizontal shift factor
192 * @vfactor: vertical shift factor
193 * @pre_hratio: horizontal ratio of the prescaler
194 * @pre_vratio: vertical ratio of the prescaler
195 * @pre_dst_width: the prescaler's destination width
196 * @pre_dst_height: the prescaler's destination height
197 * @main_hratio: the main scaler's horizontal ratio
198 * @main_vratio: the main scaler's vertical ratio
199 * @real_width: source pixel (width - offset)
200 * @real_height: source pixel (height - offset)
201 */
202struct fimc_scaler {
203 unsigned int scaleup_h:1;
204 unsigned int scaleup_v:1;
205 unsigned int copy_mode:1;
206 unsigned int enabled:1;
207 u32 hfactor;
208 u32 vfactor;
209 u32 pre_hratio;
210 u32 pre_vratio;
211 u32 pre_dst_width;
212 u32 pre_dst_height;
213 u32 main_hratio;
214 u32 main_vratio;
215 u32 real_width;
216 u32 real_height;
217};
218
219/**
220 * struct fimc_addr - the FIMC physical address set for DMA
221 * @y: luminance plane physical address
222 * @cb: Cb plane physical address
223 * @cr: Cr plane physical address
224 */
225struct fimc_addr {
226 u32 y;
227 u32 cb;
228 u32 cr;
229};
230
231/**
232 * struct fimc_vid_buffer - the driver's video buffer
233 * @vb: v4l videobuf buffer
234 * @list: linked list structure for buffer queue
235 * @paddr: precalculated physical address set
236 * @index: buffer index for the output DMA engine
237 */
238struct fimc_vid_buffer {
239 struct vb2_buffer vb;
240 struct list_head list;
241 struct fimc_addr paddr;
242 int index;
243};
244
245/**
246 * struct fimc_frame - source/target frame properties
247 * @f_width: image full width (virtual screen size)
248 * @f_height: image full height (virtual screen size)
249 * @o_width: original image width as set by S_FMT
250 * @o_height: original image height as set by S_FMT
251 * @offs_h: image horizontal pixel offset
252 * @offs_v: image vertical pixel offset
253 * @width: image pixel width
254 * @height: image pixel weight
255 * @payload: image size in bytes (w x h x bpp)
256 * @paddr: image frame buffer physical addresses
257 * @dma_offset: DMA offset in bytes
258 * @fmt: fimc color format pointer
259 */
260struct fimc_frame {
261 u32 f_width;
262 u32 f_height;
263 u32 o_width;
264 u32 o_height;
265 u32 offs_h;
266 u32 offs_v;
267 u32 width;
268 u32 height;
269 unsigned long payload[VIDEO_MAX_PLANES];
270 struct fimc_addr paddr;
271 struct fimc_dma_offset dma_offset;
272 struct fimc_fmt *fmt;
273};
274
275/**
276 * struct fimc_m2m_device - v4l2 memory-to-memory device data
277 * @vfd: the video device node for v4l2 m2m mode
278 * @v4l2_dev: v4l2 device for m2m mode
279 * @m2m_dev: v4l2 memory-to-memory device data
280 * @ctx: hardware context data
281 * @refcnt: the reference counter
282 */
283struct fimc_m2m_device {
284 struct video_device *vfd;
285 struct v4l2_device v4l2_dev;
286 struct v4l2_m2m_dev *m2m_dev;
287 struct fimc_ctx *ctx;
288 int refcnt;
289};
290
291/**
292 * struct fimc_vid_cap - camera capture device information
293 * @ctx: hardware context data
294 * @vfd: video device node for camera capture mode
295 * @v4l2_dev: v4l2_device struct to manage subdevs
296 * @sd: pointer to camera sensor subdevice currently in use
297 * @fmt: Media Bus format configured at selected image sensor
298 * @pending_buf_q: the pending buffer queue head
299 * @active_buf_q: the queue head of buffers scheduled in hardware
300 * @vbq: the capture am video buffer queue
301 * @active_buf_cnt: number of video buffers scheduled in hardware
302 * @buf_index: index for managing the output DMA buffers
303 * @frame_count: the frame counter for statistics
304 * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
305 * @input_index: input (camera sensor) index
306 * @refcnt: driver's private reference counter
307 */
308struct fimc_vid_cap {
309 struct fimc_ctx *ctx;
310 struct vb2_alloc_ctx *alloc_ctx;
311 struct video_device *vfd;
312 struct v4l2_device v4l2_dev;
313 struct v4l2_subdev *sd;;
314 struct v4l2_mbus_framefmt fmt;
315 struct list_head pending_buf_q;
316 struct list_head active_buf_q;
317 struct vb2_queue vbq;
318 int active_buf_cnt;
319 int buf_index;
320 unsigned int frame_count;
321 unsigned int reqbufs_count;
322 int input_index;
323 int refcnt;
324};
325
326/**
327 * struct fimc_pix_limit - image pixel size limits in various IP configurations
328 *
329 * @scaler_en_w: max input pixel width when the scaler is enabled
330 * @scaler_dis_w: max input pixel width when the scaler is disabled
331 * @in_rot_en_h: max input width with the input rotator is on
332 * @in_rot_dis_w: max input width with the input rotator is off
333 * @out_rot_en_w: max output width with the output rotator on
334 * @out_rot_dis_w: max output width with the output rotator off
335 */
336struct fimc_pix_limit {
337 u16 scaler_en_w;
338 u16 scaler_dis_w;
339 u16 in_rot_en_h;
340 u16 in_rot_dis_w;
341 u16 out_rot_en_w;
342 u16 out_rot_dis_w;
343};
344
345/**
346 * struct samsung_fimc_variant - camera interface variant information
347 *
348 * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
349 * @has_inp_rot: set if has input rotator
350 * @has_out_rot: set if has output rotator
351 * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
352 * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
353 * are present in this IP revision
354 * @pix_limit: pixel size constraints for the scaler
355 * @min_inp_pixsize: minimum input pixel size
356 * @min_out_pixsize: minimum output pixel size
357 * @hor_offs_align: horizontal pixel offset aligment
358 * @out_buf_count: the number of buffers in output DMA sequence
359 */
360struct samsung_fimc_variant {
361 unsigned int pix_hoff:1;
362 unsigned int has_inp_rot:1;
363 unsigned int has_out_rot:1;
364 unsigned int has_cistatus2:1;
365 unsigned int has_mainscaler_ext:1;
366 struct fimc_pix_limit *pix_limit;
367 u16 min_inp_pixsize;
368 u16 min_out_pixsize;
369 u16 hor_offs_align;
370 u16 out_buf_count;
371};
372
373/**
374 * struct samsung_fimc_driverdata - per device type driver data for init time.
375 *
376 * @variant: the variant information for this driver.
377 * @dev_cnt: number of fimc sub-devices available in SoC
378 * @lclk_frequency: fimc bus clock frequency
379 */
380struct samsung_fimc_driverdata {
381 struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
382 unsigned long lclk_frequency;
383 int num_entities;
384};
385
386struct fimc_ctx;
387
388/**
389 * struct fimc_dev - abstraction for FIMC entity
390 * @slock: the spinlock protecting this data structure
391 * @lock: the mutex protecting this data structure
392 * @pdev: pointer to the FIMC platform device
393 * @pdata: pointer to the device platform data
394 * @variant: the IP variant information
395 * @id: FIMC device index (0..FIMC_MAX_DEVS)
396 * @num_clocks: the number of clocks managed by this device instance
397 * @clock: clocks required for FIMC operation
398 * @regs: the mapped hardware registers
399 * @regs_res: the resource claimed for IO registers
400 * @irq: FIMC interrupt number
401 * @irq_queue: interrupt handler waitqueue
402 * @m2m: memory-to-memory V4L2 device information
403 * @vid_cap: camera capture device information
404 * @state: flags used to synchronize m2m and capture mode operation
405 * @alloc_ctx: videobuf2 memory allocator context
406 */
407struct fimc_dev {
408 spinlock_t slock;
409 struct mutex lock;
410 struct platform_device *pdev;
411 struct s5p_platform_fimc *pdata;
412 struct samsung_fimc_variant *variant;
413 u16 id;
414 u16 num_clocks;
415 struct clk *clock[MAX_FIMC_CLOCKS];
416 void __iomem *regs;
417 struct resource *regs_res;
418 int irq;
419 wait_queue_head_t irq_queue;
420 struct fimc_m2m_device m2m;
421 struct fimc_vid_cap vid_cap;
422 unsigned long state;
423 struct vb2_alloc_ctx *alloc_ctx;
424};
425
426/**
427 * fimc_ctx - the device context data
428 * @slock: spinlock protecting this data structure
429 * @s_frame: source frame properties
430 * @d_frame: destination frame properties
431 * @out_order_1p: output 1-plane YCBCR order
432 * @out_order_2p: output 2-plane YCBCR order
433 * @in_order_1p input 1-plane YCBCR order
434 * @in_order_2p: input 2-plane YCBCR order
435 * @in_path: input mode (DMA or camera)
436 * @out_path: output mode (DMA or FIFO)
437 * @scaler: image scaler properties
438 * @effect: image effect
439 * @rotation: image clockwise rotation in degrees
440 * @flip: image flip mode
441 * @flags: additional flags for image conversion
442 * @state: flags to keep track of user configuration
443 * @fimc_dev: the FIMC device this context applies to
444 * @m2m_ctx: memory-to-memory device context
445 */
446struct fimc_ctx {
447 spinlock_t slock;
448 struct fimc_frame s_frame;
449 struct fimc_frame d_frame;
450 u32 out_order_1p;
451 u32 out_order_2p;
452 u32 in_order_1p;
453 u32 in_order_2p;
454 enum fimc_datapath in_path;
455 enum fimc_datapath out_path;
456 struct fimc_scaler scaler;
457 struct fimc_effect effect;
458 int rotation;
459 u32 flip;
460 u32 flags;
461 u32 state;
462 struct fimc_dev *fimc_dev;
463 struct v4l2_m2m_ctx *m2m_ctx;
464};
465
466static inline bool fimc_capture_active(struct fimc_dev *fimc)
467{
468 unsigned long flags;
469 bool ret;
470
471 spin_lock_irqsave(&fimc->slock, flags);
472 ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
473 fimc->state & (1 << ST_CAPT_PEND));
474 spin_unlock_irqrestore(&fimc->slock, flags);
475 return ret;
476}
477
478static inline void fimc_ctx_state_lock_set(u32 state, struct fimc_ctx *ctx)
479{
480 unsigned long flags;
481
482 spin_lock_irqsave(&ctx->slock, flags);
483 ctx->state |= state;
484 spin_unlock_irqrestore(&ctx->slock, flags);
485}
486
487static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
488{
489 unsigned long flags;
490 bool ret;
491
492 spin_lock_irqsave(&ctx->slock, flags);
493 ret = (ctx->state & mask) == mask;
494 spin_unlock_irqrestore(&ctx->slock, flags);
495 return ret;
496}
497
498static inline int tiled_fmt(struct fimc_fmt *fmt)
499{
500 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
501}
502
503static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
504{
505 u32 cfg = readl(dev->regs + S5P_CIGCTRL);
506 cfg |= S5P_CIGCTRL_IRQ_CLR;
507 writel(cfg, dev->regs + S5P_CIGCTRL);
508}
509
510static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
511{
512 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
513 if (on)
514 cfg |= S5P_CISCCTRL_SCALERSTART;
515 else
516 cfg &= ~S5P_CISCCTRL_SCALERSTART;
517 writel(cfg, dev->regs + S5P_CISCCTRL);
518}
519
520static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
521{
522 u32 cfg = readl(dev->regs + S5P_MSCTRL);
523 if (on)
524 cfg |= S5P_MSCTRL_ENVID;
525 else
526 cfg &= ~S5P_MSCTRL_ENVID;
527 writel(cfg, dev->regs + S5P_MSCTRL);
528}
529
530static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
531{
532 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
533 cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
534 writel(cfg, dev->regs + S5P_CIIMGCPT);
535}
536
537/**
538 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
539 * @mask: each bit corresponds to one of 32 output buffer registers set
540 * 1 to include buffer in the sequence, 0 to disable
541 *
542 * This function mask output DMA ring buffers, i.e. it allows to configure
543 * which of the output buffer address registers will be used by the DMA
544 * engine.
545 */
546static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
547{
548 writel(mask, dev->regs + S5P_CIFCNTSEQ);
549}
550
551static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
552 enum v4l2_buf_type type)
553{
554 struct fimc_frame *frame;
555
556 if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
557 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
558 frame = &ctx->s_frame;
559 else
560 return ERR_PTR(-EINVAL);
561 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
562 frame = &ctx->d_frame;
563 } else {
564 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
565 "Wrong buffer/video queue type (%d)\n", type);
566 return ERR_PTR(-EINVAL);
567 }
568
569 return frame;
570}
571
572/* Return an index to the buffer actually being written. */
573static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
574{
575 u32 reg;
576
577 if (dev->variant->has_cistatus2) {
578 reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F;
579 return reg > 0 ? --reg : reg;
580 } else {
581 reg = readl(dev->regs + S5P_CISTATUS);
582 return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
583 S5P_CISTATUS_FRAMECNT_SHIFT;
584 }
585}
586
587/* -----------------------------------------------------*/
588/* fimc-reg.c */
589void fimc_hw_reset(struct fimc_dev *fimc);
590void fimc_hw_set_rotation(struct fimc_ctx *ctx);
591void fimc_hw_set_target_format(struct fimc_ctx *ctx);
592void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
593void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
594void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
595void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
596void fimc_hw_set_mainscaler(struct fimc_ctx *ctx);
597void fimc_hw_en_capture(struct fimc_ctx *ctx);
598void fimc_hw_set_effect(struct fimc_ctx *ctx);
599void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
600void fimc_hw_set_input_path(struct fimc_ctx *ctx);
601void fimc_hw_set_output_path(struct fimc_ctx *ctx);
602void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
603void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
604 int index);
605int fimc_hw_set_camera_source(struct fimc_dev *fimc,
606 struct s5p_fimc_isp_info *cam);
607int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
608int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
609 struct s5p_fimc_isp_info *cam);
610int fimc_hw_set_camera_type(struct fimc_dev *fimc,
611 struct s5p_fimc_isp_info *cam);
612
613/* -----------------------------------------------------*/
614/* fimc-core.c */
615int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
616 struct v4l2_fmtdesc *f);
617int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
618 struct v4l2_format *f);
619int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
620 struct v4l2_format *f);
621int fimc_vidioc_queryctrl(struct file *file, void *priv,
622 struct v4l2_queryctrl *qc);
623int fimc_vidioc_g_ctrl(struct file *file, void *priv,
624 struct v4l2_control *ctrl);
625
626int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr);
627int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
628int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
629
630struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask);
631struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
632 unsigned int mask);
633
634int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot);
635int fimc_set_scaler_info(struct fimc_ctx *ctx);
636int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
637int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
638 struct fimc_frame *frame, struct fimc_addr *paddr);
639
640/* -----------------------------------------------------*/
641/* fimc-capture.c */
642int fimc_register_capture_device(struct fimc_dev *fimc);
643void fimc_unregister_capture_device(struct fimc_dev *fimc);
644int fimc_sensor_sd_init(struct fimc_dev *fimc, int index);
645int fimc_vid_cap_buf_queue(struct fimc_dev *fimc,
646 struct fimc_vid_buffer *fimc_vb);
647
648/* Locking: the caller holds fimc->slock */
649static inline void fimc_activate_capture(struct fimc_ctx *ctx)
650{
651 fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
652 fimc_hw_en_capture(ctx);
653}
654
655static inline void fimc_deactivate_capture(struct fimc_dev *fimc)
656{
657 fimc_hw_en_lastirq(fimc, true);
658 fimc_hw_dis_capture(fimc);
659 fimc_hw_enable_scaler(fimc, false);
660 fimc_hw_en_lastirq(fimc, false);
661}
662
663/*
664 * Add buf to the capture active buffers queue.
665 * Locking: Need to be called with fimc_dev::slock held.
666 */
667static inline void active_queue_add(struct fimc_vid_cap *vid_cap,
668 struct fimc_vid_buffer *buf)
669{
670 list_add_tail(&buf->list, &vid_cap->active_buf_q);
671 vid_cap->active_buf_cnt++;
672}
673
674/*
675 * Pop a video buffer from the capture active buffers queue
676 * Locking: Need to be called with fimc_dev::slock held.
677 */
678static inline struct fimc_vid_buffer *
679active_queue_pop(struct fimc_vid_cap *vid_cap)
680{
681 struct fimc_vid_buffer *buf;
682 buf = list_entry(vid_cap->active_buf_q.next,
683 struct fimc_vid_buffer, list);
684 list_del(&buf->list);
685 vid_cap->active_buf_cnt--;
686 return buf;
687}
688
689/* Add video buffer to the capture pending buffers queue */
690static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
691 struct fimc_vid_buffer *buf)
692{
693 list_add_tail(&buf->list, &vid_cap->pending_buf_q);
694}
695
696/* Add video buffer to the capture pending buffers queue */
697static inline struct fimc_vid_buffer *
698pending_queue_pop(struct fimc_vid_cap *vid_cap)
699{
700 struct fimc_vid_buffer *buf;
701 buf = list_entry(vid_cap->pending_buf_q.next,
702 struct fimc_vid_buffer, list);
703 list_del(&buf->list);
704 return buf;
705}
706
707#endif /* FIMC_CORE_H_ */
diff --git a/drivers/media/video/s5p-fimc/fimc-reg.c b/drivers/media/video/s5p-fimc/fimc-reg.c
new file mode 100644
index 00000000000..4893b2d91d8
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/fimc-reg.c
@@ -0,0 +1,685 @@
1/*
2 * Register interface file for Samsung Camera Interface (FIMC) driver
3 *
4 * Copyright (c) 2010 Samsung Electronics
5 *
6 * Sylwester Nawrocki, s.nawrocki@samsung.com
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/io.h>
14#include <linux/delay.h>
15#include <mach/map.h>
16#include <media/s5p_fimc.h>
17
18#include "fimc-core.h"
19
20
21void fimc_hw_reset(struct fimc_dev *dev)
22{
23 u32 cfg;
24
25 cfg = readl(dev->regs + S5P_CISRCFMT);
26 cfg |= S5P_CISRCFMT_ITU601_8BIT;
27 writel(cfg, dev->regs + S5P_CISRCFMT);
28
29 /* Software reset. */
30 cfg = readl(dev->regs + S5P_CIGCTRL);
31 cfg |= (S5P_CIGCTRL_SWRST | S5P_CIGCTRL_IRQ_LEVEL);
32 writel(cfg, dev->regs + S5P_CIGCTRL);
33 udelay(1000);
34
35 cfg = readl(dev->regs + S5P_CIGCTRL);
36 cfg &= ~S5P_CIGCTRL_SWRST;
37 writel(cfg, dev->regs + S5P_CIGCTRL);
38}
39
40static u32 fimc_hw_get_in_flip(struct fimc_ctx *ctx)
41{
42 u32 flip = S5P_MSCTRL_FLIP_NORMAL;
43
44 switch (ctx->flip) {
45 case FLIP_X_AXIS:
46 flip = S5P_MSCTRL_FLIP_X_MIRROR;
47 break;
48 case FLIP_Y_AXIS:
49 flip = S5P_MSCTRL_FLIP_Y_MIRROR;
50 break;
51 case FLIP_XY_AXIS:
52 flip = S5P_MSCTRL_FLIP_180;
53 break;
54 default:
55 break;
56 }
57 if (ctx->rotation <= 90)
58 return flip;
59
60 return (flip ^ S5P_MSCTRL_FLIP_180) & S5P_MSCTRL_FLIP_180;
61}
62
63static u32 fimc_hw_get_target_flip(struct fimc_ctx *ctx)
64{
65 u32 flip = S5P_CITRGFMT_FLIP_NORMAL;
66
67 switch (ctx->flip) {
68 case FLIP_X_AXIS:
69 flip = S5P_CITRGFMT_FLIP_X_MIRROR;
70 break;
71 case FLIP_Y_AXIS:
72 flip = S5P_CITRGFMT_FLIP_Y_MIRROR;
73 break;
74 case FLIP_XY_AXIS:
75 flip = S5P_CITRGFMT_FLIP_180;
76 break;
77 default:
78 break;
79 }
80 if (ctx->rotation <= 90)
81 return flip;
82
83 return (flip ^ S5P_CITRGFMT_FLIP_180) & S5P_CITRGFMT_FLIP_180;
84}
85
86void fimc_hw_set_rotation(struct fimc_ctx *ctx)
87{
88 u32 cfg, flip;
89 struct fimc_dev *dev = ctx->fimc_dev;
90
91 cfg = readl(dev->regs + S5P_CITRGFMT);
92 cfg &= ~(S5P_CITRGFMT_INROT90 | S5P_CITRGFMT_OUTROT90 |
93 S5P_CITRGFMT_FLIP_180);
94
95 /*
96 * The input and output rotator cannot work simultaneously.
97 * Use the output rotator in output DMA mode or the input rotator
98 * in direct fifo output mode.
99 */
100 if (ctx->rotation == 90 || ctx->rotation == 270) {
101 if (ctx->out_path == FIMC_LCDFIFO)
102 cfg |= S5P_CITRGFMT_INROT90;
103 else
104 cfg |= S5P_CITRGFMT_OUTROT90;
105 }
106
107 if (ctx->out_path == FIMC_DMA) {
108 cfg |= fimc_hw_get_target_flip(ctx);
109 writel(cfg, dev->regs + S5P_CITRGFMT);
110 } else {
111 /* LCD FIFO path */
112 flip = readl(dev->regs + S5P_MSCTRL);
113 flip &= ~S5P_MSCTRL_FLIP_MASK;
114 flip |= fimc_hw_get_in_flip(ctx);
115 writel(flip, dev->regs + S5P_MSCTRL);
116 }
117}
118
119void fimc_hw_set_target_format(struct fimc_ctx *ctx)
120{
121 u32 cfg;
122 struct fimc_dev *dev = ctx->fimc_dev;
123 struct fimc_frame *frame = &ctx->d_frame;
124
125 dbg("w= %d, h= %d color: %d", frame->width,
126 frame->height, frame->fmt->color);
127
128 cfg = readl(dev->regs + S5P_CITRGFMT);
129 cfg &= ~(S5P_CITRGFMT_FMT_MASK | S5P_CITRGFMT_HSIZE_MASK |
130 S5P_CITRGFMT_VSIZE_MASK);
131
132 switch (frame->fmt->color) {
133 case S5P_FIMC_RGB565...S5P_FIMC_RGB888:
134 cfg |= S5P_CITRGFMT_RGB;
135 break;
136 case S5P_FIMC_YCBCR420:
137 cfg |= S5P_CITRGFMT_YCBCR420;
138 break;
139 case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422:
140 if (frame->fmt->colplanes == 1)
141 cfg |= S5P_CITRGFMT_YCBCR422_1P;
142 else
143 cfg |= S5P_CITRGFMT_YCBCR422;
144 break;
145 default:
146 break;
147 }
148
149 if (ctx->rotation == 90 || ctx->rotation == 270) {
150 cfg |= S5P_CITRGFMT_HSIZE(frame->height);
151 cfg |= S5P_CITRGFMT_VSIZE(frame->width);
152 } else {
153
154 cfg |= S5P_CITRGFMT_HSIZE(frame->width);
155 cfg |= S5P_CITRGFMT_VSIZE(frame->height);
156 }
157
158 writel(cfg, dev->regs + S5P_CITRGFMT);
159
160 cfg = readl(dev->regs + S5P_CITAREA) & ~S5P_CITAREA_MASK;
161 cfg |= (frame->width * frame->height);
162 writel(cfg, dev->regs + S5P_CITAREA);
163}
164
165static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx)
166{
167 struct fimc_dev *dev = ctx->fimc_dev;
168 struct fimc_frame *frame = &ctx->d_frame;
169 u32 cfg;
170
171 cfg = S5P_ORIG_SIZE_HOR(frame->f_width);
172 cfg |= S5P_ORIG_SIZE_VER(frame->f_height);
173 writel(cfg, dev->regs + S5P_ORGOSIZE);
174
175 /* Select color space conversion equation (HD/SD size).*/
176 cfg = readl(dev->regs + S5P_CIGCTRL);
177 if (frame->f_width >= 1280) /* HD */
178 cfg |= S5P_CIGCTRL_CSC_ITU601_709;
179 else /* SD */
180 cfg &= ~S5P_CIGCTRL_CSC_ITU601_709;
181 writel(cfg, dev->regs + S5P_CIGCTRL);
182
183}
184
185void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
186{
187 u32 cfg;
188 struct fimc_dev *dev = ctx->fimc_dev;
189 struct fimc_frame *frame = &ctx->d_frame;
190 struct fimc_dma_offset *offset = &frame->dma_offset;
191
192 /* Set the input dma offsets. */
193 cfg = 0;
194 cfg |= S5P_CIO_OFFS_HOR(offset->y_h);
195 cfg |= S5P_CIO_OFFS_VER(offset->y_v);
196 writel(cfg, dev->regs + S5P_CIOYOFF);
197
198 cfg = 0;
199 cfg |= S5P_CIO_OFFS_HOR(offset->cb_h);
200 cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
201 writel(cfg, dev->regs + S5P_CIOCBOFF);
202
203 cfg = 0;
204 cfg |= S5P_CIO_OFFS_HOR(offset->cr_h);
205 cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
206 writel(cfg, dev->regs + S5P_CIOCROFF);
207
208 fimc_hw_set_out_dma_size(ctx);
209
210 /* Configure chroma components order. */
211 cfg = readl(dev->regs + S5P_CIOCTRL);
212
213 cfg &= ~(S5P_CIOCTRL_ORDER2P_MASK | S5P_CIOCTRL_ORDER422_MASK |
214 S5P_CIOCTRL_YCBCR_PLANE_MASK);
215
216 if (frame->fmt->colplanes == 1)
217 cfg |= ctx->out_order_1p;
218 else if (frame->fmt->colplanes == 2)
219 cfg |= ctx->out_order_2p | S5P_CIOCTRL_YCBCR_2PLANE;
220 else if (frame->fmt->colplanes == 3)
221 cfg |= S5P_CIOCTRL_YCBCR_3PLANE;
222
223 writel(cfg, dev->regs + S5P_CIOCTRL);
224}
225
226static void fimc_hw_en_autoload(struct fimc_dev *dev, int enable)
227{
228 u32 cfg = readl(dev->regs + S5P_ORGISIZE);
229 if (enable)
230 cfg |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
231 else
232 cfg &= ~S5P_CIREAL_ISIZE_AUTOLOAD_EN;
233 writel(cfg, dev->regs + S5P_ORGISIZE);
234}
235
236void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable)
237{
238 u32 cfg = readl(dev->regs + S5P_CIOCTRL);
239 if (enable)
240 cfg |= S5P_CIOCTRL_LASTIRQ_ENABLE;
241 else
242 cfg &= ~S5P_CIOCTRL_LASTIRQ_ENABLE;
243 writel(cfg, dev->regs + S5P_CIOCTRL);
244}
245
246void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
247{
248 struct fimc_dev *dev = ctx->fimc_dev;
249 struct fimc_scaler *sc = &ctx->scaler;
250 u32 cfg, shfactor;
251
252 shfactor = 10 - (sc->hfactor + sc->vfactor);
253
254 cfg = S5P_CISCPRERATIO_SHFACTOR(shfactor);
255 cfg |= S5P_CISCPRERATIO_HOR(sc->pre_hratio);
256 cfg |= S5P_CISCPRERATIO_VER(sc->pre_vratio);
257 writel(cfg, dev->regs + S5P_CISCPRERATIO);
258
259 cfg = S5P_CISCPREDST_WIDTH(sc->pre_dst_width);
260 cfg |= S5P_CISCPREDST_HEIGHT(sc->pre_dst_height);
261 writel(cfg, dev->regs + S5P_CISCPREDST);
262}
263
264static void fimc_hw_set_scaler(struct fimc_ctx *ctx)
265{
266 struct fimc_dev *dev = ctx->fimc_dev;
267 struct fimc_scaler *sc = &ctx->scaler;
268 struct fimc_frame *src_frame = &ctx->s_frame;
269 struct fimc_frame *dst_frame = &ctx->d_frame;
270 u32 cfg = 0;
271
272 if (!(ctx->flags & FIMC_COLOR_RANGE_NARROW))
273 cfg |= (S5P_CISCCTRL_CSCR2Y_WIDE | S5P_CISCCTRL_CSCY2R_WIDE);
274
275 if (!sc->enabled)
276 cfg |= S5P_CISCCTRL_SCALERBYPASS;
277
278 if (sc->scaleup_h)
279 cfg |= S5P_CISCCTRL_SCALEUP_H;
280
281 if (sc->scaleup_v)
282 cfg |= S5P_CISCCTRL_SCALEUP_V;
283
284 if (sc->copy_mode)
285 cfg |= S5P_CISCCTRL_ONE2ONE;
286
287
288 if (ctx->in_path == FIMC_DMA) {
289 if (src_frame->fmt->color == S5P_FIMC_RGB565)
290 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB565;
291 else if (src_frame->fmt->color == S5P_FIMC_RGB666)
292 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB666;
293 else if (src_frame->fmt->color == S5P_FIMC_RGB888)
294 cfg |= S5P_CISCCTRL_INRGB_FMT_RGB888;
295 }
296
297 if (ctx->out_path == FIMC_DMA) {
298 if (dst_frame->fmt->color == S5P_FIMC_RGB565)
299 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB565;
300 else if (dst_frame->fmt->color == S5P_FIMC_RGB666)
301 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB666;
302 else if (dst_frame->fmt->color == S5P_FIMC_RGB888)
303 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
304 } else {
305 cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
306
307 if (ctx->flags & FIMC_SCAN_MODE_INTERLACED)
308 cfg |= S5P_CISCCTRL_INTERLACE;
309 }
310
311 writel(cfg, dev->regs + S5P_CISCCTRL);
312}
313
314void fimc_hw_set_mainscaler(struct fimc_ctx *ctx)
315{
316 struct fimc_dev *dev = ctx->fimc_dev;
317 struct samsung_fimc_variant *variant = dev->variant;
318 struct fimc_scaler *sc = &ctx->scaler;
319 u32 cfg;
320
321 dbg("main_hratio= 0x%X main_vratio= 0x%X",
322 sc->main_hratio, sc->main_vratio);
323
324 fimc_hw_set_scaler(ctx);
325
326 cfg = readl(dev->regs + S5P_CISCCTRL);
327
328 if (variant->has_mainscaler_ext) {
329 cfg &= ~(S5P_CISCCTRL_MHRATIO_MASK | S5P_CISCCTRL_MVRATIO_MASK);
330 cfg |= S5P_CISCCTRL_MHRATIO_EXT(sc->main_hratio);
331 cfg |= S5P_CISCCTRL_MVRATIO_EXT(sc->main_vratio);
332 writel(cfg, dev->regs + S5P_CISCCTRL);
333
334 cfg = readl(dev->regs + S5P_CIEXTEN);
335
336 cfg &= ~(S5P_CIEXTEN_MVRATIO_EXT_MASK |
337 S5P_CIEXTEN_MHRATIO_EXT_MASK);
338 cfg |= S5P_CIEXTEN_MHRATIO_EXT(sc->main_hratio);
339 cfg |= S5P_CIEXTEN_MVRATIO_EXT(sc->main_vratio);
340 writel(cfg, dev->regs + S5P_CIEXTEN);
341 } else {
342 cfg &= ~(S5P_CISCCTRL_MHRATIO_MASK | S5P_CISCCTRL_MVRATIO_MASK);
343 cfg |= S5P_CISCCTRL_MHRATIO(sc->main_hratio);
344 cfg |= S5P_CISCCTRL_MVRATIO(sc->main_vratio);
345 writel(cfg, dev->regs + S5P_CISCCTRL);
346 }
347}
348
349void fimc_hw_en_capture(struct fimc_ctx *ctx)
350{
351 struct fimc_dev *dev = ctx->fimc_dev;
352
353 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
354
355 if (ctx->out_path == FIMC_DMA) {
356 /* one shot mode */
357 cfg |= S5P_CIIMGCPT_CPT_FREN_ENABLE | S5P_CIIMGCPT_IMGCPTEN;
358 } else {
359 /* Continuous frame capture mode (freerun). */
360 cfg &= ~(S5P_CIIMGCPT_CPT_FREN_ENABLE |
361 S5P_CIIMGCPT_CPT_FRMOD_CNT);
362 cfg |= S5P_CIIMGCPT_IMGCPTEN;
363 }
364
365 if (ctx->scaler.enabled)
366 cfg |= S5P_CIIMGCPT_IMGCPTEN_SC;
367
368 writel(cfg | S5P_CIIMGCPT_IMGCPTEN, dev->regs + S5P_CIIMGCPT);
369}
370
371void fimc_hw_set_effect(struct fimc_ctx *ctx)
372{
373 struct fimc_dev *dev = ctx->fimc_dev;
374 struct fimc_effect *effect = &ctx->effect;
375 u32 cfg = (S5P_CIIMGEFF_IE_ENABLE | S5P_CIIMGEFF_IE_SC_AFTER);
376
377 cfg |= effect->type;
378
379 if (effect->type == S5P_FIMC_EFFECT_ARBITRARY) {
380 cfg |= S5P_CIIMGEFF_PAT_CB(effect->pat_cb);
381 cfg |= S5P_CIIMGEFF_PAT_CR(effect->pat_cr);
382 }
383
384 writel(cfg, dev->regs + S5P_CIIMGEFF);
385}
386
387static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
388{
389 struct fimc_dev *dev = ctx->fimc_dev;
390 struct fimc_frame *frame = &ctx->s_frame;
391 u32 cfg_o = 0;
392 u32 cfg_r = 0;
393
394 if (FIMC_LCDFIFO == ctx->out_path)
395 cfg_r |= S5P_CIREAL_ISIZE_AUTOLOAD_EN;
396
397 cfg_o |= S5P_ORIG_SIZE_HOR(frame->f_width);
398 cfg_o |= S5P_ORIG_SIZE_VER(frame->f_height);
399 cfg_r |= S5P_CIREAL_ISIZE_WIDTH(frame->width);
400 cfg_r |= S5P_CIREAL_ISIZE_HEIGHT(frame->height);
401
402 writel(cfg_o, dev->regs + S5P_ORGISIZE);
403 writel(cfg_r, dev->regs + S5P_CIREAL_ISIZE);
404}
405
406void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
407{
408 struct fimc_dev *dev = ctx->fimc_dev;
409 struct fimc_frame *frame = &ctx->s_frame;
410 struct fimc_dma_offset *offset = &frame->dma_offset;
411 u32 cfg;
412
413 /* Set the pixel offsets. */
414 cfg = S5P_CIO_OFFS_HOR(offset->y_h);
415 cfg |= S5P_CIO_OFFS_VER(offset->y_v);
416 writel(cfg, dev->regs + S5P_CIIYOFF);
417
418 cfg = S5P_CIO_OFFS_HOR(offset->cb_h);
419 cfg |= S5P_CIO_OFFS_VER(offset->cb_v);
420 writel(cfg, dev->regs + S5P_CIICBOFF);
421
422 cfg = S5P_CIO_OFFS_HOR(offset->cr_h);
423 cfg |= S5P_CIO_OFFS_VER(offset->cr_v);
424 writel(cfg, dev->regs + S5P_CIICROFF);
425
426 /* Input original and real size. */
427 fimc_hw_set_in_dma_size(ctx);
428
429 /* Use DMA autoload only in FIFO mode. */
430 fimc_hw_en_autoload(dev, ctx->out_path == FIMC_LCDFIFO);
431
432 /* Set the input DMA to process single frame only. */
433 cfg = readl(dev->regs + S5P_MSCTRL);
434 cfg &= ~(S5P_MSCTRL_INFORMAT_MASK
435 | S5P_MSCTRL_IN_BURST_COUNT_MASK
436 | S5P_MSCTRL_INPUT_MASK
437 | S5P_MSCTRL_C_INT_IN_MASK
438 | S5P_MSCTRL_2P_IN_ORDER_MASK);
439
440 cfg |= (S5P_MSCTRL_IN_BURST_COUNT(4)
441 | S5P_MSCTRL_INPUT_MEMORY
442 | S5P_MSCTRL_FIFO_CTRL_FULL);
443
444 switch (frame->fmt->color) {
445 case S5P_FIMC_RGB565...S5P_FIMC_RGB888:
446 cfg |= S5P_MSCTRL_INFORMAT_RGB;
447 break;
448 case S5P_FIMC_YCBCR420:
449 cfg |= S5P_MSCTRL_INFORMAT_YCBCR420;
450
451 if (frame->fmt->colplanes == 2)
452 cfg |= ctx->in_order_2p | S5P_MSCTRL_C_INT_IN_2PLANE;
453 else
454 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
455
456 break;
457 case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422:
458 if (frame->fmt->colplanes == 1) {
459 cfg |= ctx->in_order_1p
460 | S5P_MSCTRL_INFORMAT_YCBCR422_1P;
461 } else {
462 cfg |= S5P_MSCTRL_INFORMAT_YCBCR422;
463
464 if (frame->fmt->colplanes == 2)
465 cfg |= ctx->in_order_2p
466 | S5P_MSCTRL_C_INT_IN_2PLANE;
467 else
468 cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
469 }
470 break;
471 default:
472 break;
473 }
474
475 writel(cfg, dev->regs + S5P_MSCTRL);
476
477 /* Input/output DMA linear/tiled mode. */
478 cfg = readl(dev->regs + S5P_CIDMAPARAM);
479 cfg &= ~S5P_CIDMAPARAM_TILE_MASK;
480
481 if (tiled_fmt(ctx->s_frame.fmt))
482 cfg |= S5P_CIDMAPARAM_R_64X32;
483
484 if (tiled_fmt(ctx->d_frame.fmt))
485 cfg |= S5P_CIDMAPARAM_W_64X32;
486
487 writel(cfg, dev->regs + S5P_CIDMAPARAM);
488}
489
490
491void fimc_hw_set_input_path(struct fimc_ctx *ctx)
492{
493 struct fimc_dev *dev = ctx->fimc_dev;
494
495 u32 cfg = readl(dev->regs + S5P_MSCTRL);
496 cfg &= ~S5P_MSCTRL_INPUT_MASK;
497
498 if (ctx->in_path == FIMC_DMA)
499 cfg |= S5P_MSCTRL_INPUT_MEMORY;
500 else
501 cfg |= S5P_MSCTRL_INPUT_EXTCAM;
502
503 writel(cfg, dev->regs + S5P_MSCTRL);
504}
505
506void fimc_hw_set_output_path(struct fimc_ctx *ctx)
507{
508 struct fimc_dev *dev = ctx->fimc_dev;
509
510 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
511 cfg &= ~S5P_CISCCTRL_LCDPATHEN_FIFO;
512 if (ctx->out_path == FIMC_LCDFIFO)
513 cfg |= S5P_CISCCTRL_LCDPATHEN_FIFO;
514 writel(cfg, dev->regs + S5P_CISCCTRL);
515}
516
517void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
518{
519 u32 cfg = readl(dev->regs + S5P_CIREAL_ISIZE);
520 cfg |= S5P_CIREAL_ISIZE_ADDR_CH_DIS;
521 writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
522
523 writel(paddr->y, dev->regs + S5P_CIIYSA(0));
524 writel(paddr->cb, dev->regs + S5P_CIICBSA(0));
525 writel(paddr->cr, dev->regs + S5P_CIICRSA(0));
526
527 cfg &= ~S5P_CIREAL_ISIZE_ADDR_CH_DIS;
528 writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
529}
530
531void fimc_hw_set_output_addr(struct fimc_dev *dev,
532 struct fimc_addr *paddr, int index)
533{
534 int i = (index == -1) ? 0 : index;
535 do {
536 writel(paddr->y, dev->regs + S5P_CIOYSA(i));
537 writel(paddr->cb, dev->regs + S5P_CIOCBSA(i));
538 writel(paddr->cr, dev->regs + S5P_CIOCRSA(i));
539 dbg("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
540 i, paddr->y, paddr->cb, paddr->cr);
541 } while (index == -1 && ++i < FIMC_MAX_OUT_BUFS);
542}
543
544int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
545 struct s5p_fimc_isp_info *cam)
546{
547 u32 cfg = readl(fimc->regs + S5P_CIGCTRL);
548
549 cfg &= ~(S5P_CIGCTRL_INVPOLPCLK | S5P_CIGCTRL_INVPOLVSYNC |
550 S5P_CIGCTRL_INVPOLHREF | S5P_CIGCTRL_INVPOLHSYNC);
551
552 if (cam->flags & FIMC_CLK_INV_PCLK)
553 cfg |= S5P_CIGCTRL_INVPOLPCLK;
554
555 if (cam->flags & FIMC_CLK_INV_VSYNC)
556 cfg |= S5P_CIGCTRL_INVPOLVSYNC;
557
558 if (cam->flags & FIMC_CLK_INV_HREF)
559 cfg |= S5P_CIGCTRL_INVPOLHREF;
560
561 if (cam->flags & FIMC_CLK_INV_HSYNC)
562 cfg |= S5P_CIGCTRL_INVPOLHSYNC;
563
564 writel(cfg, fimc->regs + S5P_CIGCTRL);
565
566 return 0;
567}
568
569int fimc_hw_set_camera_source(struct fimc_dev *fimc,
570 struct s5p_fimc_isp_info *cam)
571{
572 struct fimc_frame *f = &fimc->vid_cap.ctx->s_frame;
573 u32 cfg = 0;
574 u32 bus_width;
575 int i;
576
577 static const struct {
578 u32 pixelcode;
579 u32 cisrcfmt;
580 u16 bus_width;
581 } pix_desc[] = {
582 { V4L2_MBUS_FMT_YUYV8_2X8, S5P_CISRCFMT_ORDER422_YCBYCR, 8 },
583 { V4L2_MBUS_FMT_YVYU8_2X8, S5P_CISRCFMT_ORDER422_YCRYCB, 8 },
584 { V4L2_MBUS_FMT_VYUY8_2X8, S5P_CISRCFMT_ORDER422_CRYCBY, 8 },
585 { V4L2_MBUS_FMT_UYVY8_2X8, S5P_CISRCFMT_ORDER422_CBYCRY, 8 },
586 /* TODO: Add pixel codes for 16-bit bus width */
587 };
588
589 if (cam->bus_type == FIMC_ITU_601 || cam->bus_type == FIMC_ITU_656) {
590 for (i = 0; i < ARRAY_SIZE(pix_desc); i++) {
591 if (fimc->vid_cap.fmt.code == pix_desc[i].pixelcode) {
592 cfg = pix_desc[i].cisrcfmt;
593 bus_width = pix_desc[i].bus_width;
594 break;
595 }
596 }
597
598 if (i == ARRAY_SIZE(pix_desc)) {
599 v4l2_err(&fimc->vid_cap.v4l2_dev,
600 "Camera color format not supported: %d\n",
601 fimc->vid_cap.fmt.code);
602 return -EINVAL;
603 }
604
605 if (cam->bus_type == FIMC_ITU_601) {
606 if (bus_width == 8)
607 cfg |= S5P_CISRCFMT_ITU601_8BIT;
608 else if (bus_width == 16)
609 cfg |= S5P_CISRCFMT_ITU601_16BIT;
610 } /* else defaults to ITU-R BT.656 8-bit */
611 }
612
613 cfg |= S5P_CISRCFMT_HSIZE(f->o_width) | S5P_CISRCFMT_VSIZE(f->o_height);
614 writel(cfg, fimc->regs + S5P_CISRCFMT);
615 return 0;
616}
617
618
619int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f)
620{
621 u32 hoff2, voff2;
622
623 u32 cfg = readl(fimc->regs + S5P_CIWDOFST);
624
625 cfg &= ~(S5P_CIWDOFST_HOROFF_MASK | S5P_CIWDOFST_VEROFF_MASK);
626 cfg |= S5P_CIWDOFST_OFF_EN |
627 S5P_CIWDOFST_HOROFF(f->offs_h) |
628 S5P_CIWDOFST_VEROFF(f->offs_v);
629
630 writel(cfg, fimc->regs + S5P_CIWDOFST);
631
632 /* See CIWDOFSTn register description in the datasheet for details. */
633 hoff2 = f->o_width - f->width - f->offs_h;
634 voff2 = f->o_height - f->height - f->offs_v;
635 cfg = S5P_CIWDOFST2_HOROFF(hoff2) | S5P_CIWDOFST2_VEROFF(voff2);
636
637 writel(cfg, fimc->regs + S5P_CIWDOFST2);
638 return 0;
639}
640
641int fimc_hw_set_camera_type(struct fimc_dev *fimc,
642 struct s5p_fimc_isp_info *cam)
643{
644 u32 cfg, tmp;
645 struct fimc_vid_cap *vid_cap = &fimc->vid_cap;
646
647 cfg = readl(fimc->regs + S5P_CIGCTRL);
648
649 /* Select ITU B interface, disable Writeback path and test pattern. */
650 cfg &= ~(S5P_CIGCTRL_TESTPAT_MASK | S5P_CIGCTRL_SELCAM_ITU_A |
651 S5P_CIGCTRL_SELCAM_MIPI | S5P_CIGCTRL_CAMIF_SELWB |
652 S5P_CIGCTRL_SELCAM_MIPI_A);
653
654 if (cam->bus_type == FIMC_MIPI_CSI2) {
655 cfg |= S5P_CIGCTRL_SELCAM_MIPI;
656
657 if (cam->mux_id == 0)
658 cfg |= S5P_CIGCTRL_SELCAM_MIPI_A;
659
660 /* TODO: add remaining supported formats. */
661 if (vid_cap->fmt.code == V4L2_MBUS_FMT_VYUY8_2X8) {
662 tmp = S5P_CSIIMGFMT_YCBCR422_8BIT;
663 } else {
664 err("camera image format not supported: %d",
665 vid_cap->fmt.code);
666 return -EINVAL;
667 }
668 tmp |= (cam->csi_data_align == 32) << 8;
669
670 writel(tmp, fimc->regs + S5P_CSIIMGFMT);
671
672 } else if (cam->bus_type == FIMC_ITU_601 ||
673 cam->bus_type == FIMC_ITU_656) {
674 if (cam->mux_id == 0) /* ITU-A, ITU-B: 0, 1 */
675 cfg |= S5P_CIGCTRL_SELCAM_ITU_A;
676 } else if (cam->bus_type == FIMC_LCD_WB) {
677 cfg |= S5P_CIGCTRL_CAMIF_SELWB;
678 } else {
679 err("invalid camera bus type selected\n");
680 return -EINVAL;
681 }
682 writel(cfg, fimc->regs + S5P_CIGCTRL);
683
684 return 0;
685}
diff --git a/drivers/media/video/s5p-fimc/mipi-csis.c b/drivers/media/video/s5p-fimc/mipi-csis.c
new file mode 100644
index 00000000000..ef056d6605c
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/mipi-csis.c
@@ -0,0 +1,724 @@
1/*
2 * Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver
3 *
4 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
5 * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/errno.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/kernel.h>
20#include <linux/memory.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h>
24#include <linux/regulator/consumer.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
27#include <linux/videodev2.h>
28#include <media/v4l2-subdev.h>
29#include <plat/mipi_csis.h>
30#include "mipi-csis.h"
31
32static int debug;
33module_param(debug, int, 0644);
34MODULE_PARM_DESC(debug, "Debug level (0-1)");
35
36/* Register map definition */
37
38/* CSIS global control */
39#define S5PCSIS_CTRL 0x00
40#define S5PCSIS_CTRL_DPDN_DEFAULT (0 << 31)
41#define S5PCSIS_CTRL_DPDN_SWAP (1 << 31)
42#define S5PCSIS_CTRL_ALIGN_32BIT (1 << 20)
43#define S5PCSIS_CTRL_UPDATE_SHADOW (1 << 16)
44#define S5PCSIS_CTRL_WCLK_EXTCLK (1 << 8)
45#define S5PCSIS_CTRL_RESET (1 << 4)
46#define S5PCSIS_CTRL_ENABLE (1 << 0)
47
48/* D-PHY control */
49#define S5PCSIS_DPHYCTRL 0x04
50#define S5PCSIS_DPHYCTRL_HSS_MASK (0x1f << 27)
51#define S5PCSIS_DPHYCTRL_ENABLE (0x1f << 0)
52
53#define S5PCSIS_CONFIG 0x08
54#define S5PCSIS_CFG_FMT_YCBCR422_8BIT (0x1e << 2)
55#define S5PCSIS_CFG_FMT_RAW8 (0x2a << 2)
56#define S5PCSIS_CFG_FMT_RAW10 (0x2b << 2)
57#define S5PCSIS_CFG_FMT_RAW12 (0x2c << 2)
58/* User defined formats, x = 1...4 */
59#define S5PCSIS_CFG_FMT_USER(x) ((0x30 + x - 1) << 2)
60#define S5PCSIS_CFG_FMT_MASK (0x3f << 2)
61#define S5PCSIS_CFG_NR_LANE_MASK 3
62
63/* Interrupt mask. */
64#define S5PCSIS_INTMSK 0x10
65#define S5PCSIS_INTMSK_EN_ALL 0xf000003f
66#define S5PCSIS_INTSRC 0x14
67
68/* Pixel resolution */
69#define S5PCSIS_RESOL 0x2c
70#define CSIS_MAX_PIX_WIDTH 0xffff
71#define CSIS_MAX_PIX_HEIGHT 0xffff
72
73enum {
74 CSIS_CLK_MUX,
75 CSIS_CLK_GATE,
76};
77
78static char *csi_clock_name[] = {
79 [CSIS_CLK_MUX] = "sclk_csis",
80 [CSIS_CLK_GATE] = "csis",
81};
82#define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name)
83
84enum {
85 ST_POWERED = 1,
86 ST_STREAMING = 2,
87 ST_SUSPENDED = 4,
88};
89
90/**
91 * struct csis_state - the driver's internal state data structure
92 * @lock: mutex serializing the subdev and power management operations,
93 * protecting @format and @flags members
94 * @pads: CSIS pads array
95 * @sd: v4l2_subdev associated with CSIS device instance
96 * @pdev: CSIS platform device
97 * @regs_res: requested I/O register memory resource
98 * @regs: mmaped I/O registers memory
99 * @clock: CSIS clocks
100 * @irq: requested s5p-mipi-csis irq number
101 * @flags: the state variable for power and streaming control
102 * @csis_fmt: current CSIS pixel format
103 * @format: common media bus format for the source and sink pad
104 */
105struct csis_state {
106 struct mutex lock;
107 struct media_pad pads[CSIS_PADS_NUM];
108 struct v4l2_subdev sd;
109 struct platform_device *pdev;
110 struct resource *regs_res;
111 void __iomem *regs;
112 struct clk *clock[NUM_CSIS_CLOCKS];
113 int irq;
114 struct regulator *supply;
115 u32 flags;
116 const struct csis_pix_format *csis_fmt;
117 struct v4l2_mbus_framefmt format;
118};
119
120/**
121 * struct csis_pix_format - CSIS pixel format description
122 * @pix_width_alignment: horizontal pixel alignment, width will be
123 * multiple of 2^pix_width_alignment
124 * @code: corresponding media bus code
125 * @fmt_reg: S5PCSIS_CONFIG register value
126 */
127struct csis_pix_format {
128 unsigned int pix_width_alignment;
129 enum v4l2_mbus_pixelcode code;
130 u32 fmt_reg;
131};
132
133static const struct csis_pix_format s5pcsis_formats[] = {
134 {
135 .code = V4L2_MBUS_FMT_VYUY8_2X8,
136 .fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT,
137 }, {
138 .code = V4L2_MBUS_FMT_JPEG_1X8,
139 .fmt_reg = S5PCSIS_CFG_FMT_USER(1),
140 },
141};
142
143#define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r)
144#define s5pcsis_read(__csis, __r) readl(__csis->regs + __r)
145
146static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev)
147{
148 return container_of(sdev, struct csis_state, sd);
149}
150
151static const struct csis_pix_format *find_csis_format(
152 struct v4l2_mbus_framefmt *mf)
153{
154 int i;
155
156 for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++)
157 if (mf->code == s5pcsis_formats[i].code)
158 return &s5pcsis_formats[i];
159 return NULL;
160}
161
162static void s5pcsis_enable_interrupts(struct csis_state *state, bool on)
163{
164 u32 val = s5pcsis_read(state, S5PCSIS_INTMSK);
165
166 val = on ? val | S5PCSIS_INTMSK_EN_ALL :
167 val & ~S5PCSIS_INTMSK_EN_ALL;
168 s5pcsis_write(state, S5PCSIS_INTMSK, val);
169}
170
171static void s5pcsis_reset(struct csis_state *state)
172{
173 u32 val = s5pcsis_read(state, S5PCSIS_CTRL);
174
175 s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET);
176 udelay(10);
177}
178
179static void s5pcsis_system_enable(struct csis_state *state, int on)
180{
181 u32 val;
182
183 val = s5pcsis_read(state, S5PCSIS_CTRL);
184 if (on)
185 val |= S5PCSIS_CTRL_ENABLE;
186 else
187 val &= ~S5PCSIS_CTRL_ENABLE;
188 s5pcsis_write(state, S5PCSIS_CTRL, val);
189
190 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
191 if (on)
192 val |= S5PCSIS_DPHYCTRL_ENABLE;
193 else
194 val &= ~S5PCSIS_DPHYCTRL_ENABLE;
195 s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
196}
197
198/* Called with the state.lock mutex held */
199static void __s5pcsis_set_format(struct csis_state *state)
200{
201 struct v4l2_mbus_framefmt *mf = &state->format;
202 u32 val;
203
204 v4l2_dbg(1, debug, &state->sd, "fmt: %d, %d x %d\n",
205 mf->code, mf->width, mf->height);
206
207 /* Color format */
208 val = s5pcsis_read(state, S5PCSIS_CONFIG);
209 val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg;
210 s5pcsis_write(state, S5PCSIS_CONFIG, val);
211
212 /* Pixel resolution */
213 val = (mf->width << 16) | mf->height;
214 s5pcsis_write(state, S5PCSIS_RESOL, val);
215}
216
217static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle)
218{
219 u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
220
221 val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27);
222 s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
223}
224
225static void s5pcsis_set_params(struct csis_state *state)
226{
227 struct s5p_platform_mipi_csis *pdata = state->pdev->dev.platform_data;
228 u32 val;
229
230 val = s5pcsis_read(state, S5PCSIS_CONFIG);
231 val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (pdata->lanes - 1);
232 s5pcsis_write(state, S5PCSIS_CONFIG, val);
233
234 __s5pcsis_set_format(state);
235 s5pcsis_set_hsync_settle(state, pdata->hs_settle);
236
237 val = s5pcsis_read(state, S5PCSIS_CTRL);
238 if (pdata->alignment == 32)
239 val |= S5PCSIS_CTRL_ALIGN_32BIT;
240 else /* 24-bits */
241 val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
242 /* Not using external clock. */
243 val &= ~S5PCSIS_CTRL_WCLK_EXTCLK;
244 s5pcsis_write(state, S5PCSIS_CTRL, val);
245
246 /* Update the shadow register. */
247 val = s5pcsis_read(state, S5PCSIS_CTRL);
248 s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW);
249}
250
251static void s5pcsis_clk_put(struct csis_state *state)
252{
253 int i;
254
255 for (i = 0; i < NUM_CSIS_CLOCKS; i++)
256 if (!IS_ERR_OR_NULL(state->clock[i]))
257 clk_put(state->clock[i]);
258}
259
260static int s5pcsis_clk_get(struct csis_state *state)
261{
262 struct device *dev = &state->pdev->dev;
263 int i;
264
265 for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
266 state->clock[i] = clk_get(dev, csi_clock_name[i]);
267 if (IS_ERR(state->clock[i])) {
268 s5pcsis_clk_put(state);
269 dev_err(dev, "failed to get clock: %s\n",
270 csi_clock_name[i]);
271 return -ENXIO;
272 }
273 }
274 return 0;
275}
276
277static int s5pcsis_s_power(struct v4l2_subdev *sd, int on)
278{
279 struct csis_state *state = sd_to_csis_state(sd);
280 struct device *dev = &state->pdev->dev;
281
282 if (on)
283 return pm_runtime_get_sync(dev);
284
285 return pm_runtime_put_sync(dev);
286}
287
288static void s5pcsis_start_stream(struct csis_state *state)
289{
290 s5pcsis_reset(state);
291 s5pcsis_set_params(state);
292 s5pcsis_system_enable(state, true);
293 s5pcsis_enable_interrupts(state, true);
294}
295
296static void s5pcsis_stop_stream(struct csis_state *state)
297{
298 s5pcsis_enable_interrupts(state, false);
299 s5pcsis_system_enable(state, false);
300}
301
302/* v4l2_subdev operations */
303static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable)
304{
305 struct csis_state *state = sd_to_csis_state(sd);
306 int ret = 0;
307
308 v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n",
309 __func__, enable, state->flags);
310
311 if (enable) {
312 ret = pm_runtime_get_sync(&state->pdev->dev);
313 if (ret && ret != 1)
314 return ret;
315 }
316 mutex_lock(&state->lock);
317 if (enable) {
318 if (state->flags & ST_SUSPENDED) {
319 ret = -EBUSY;
320 goto unlock;
321 }
322 s5pcsis_start_stream(state);
323 state->flags |= ST_STREAMING;
324 } else {
325 s5pcsis_stop_stream(state);
326 state->flags &= ~ST_STREAMING;
327 }
328unlock:
329 mutex_unlock(&state->lock);
330 if (!enable)
331 pm_runtime_put(&state->pdev->dev);
332
333 return ret == 1 ? 0 : ret;
334}
335
336static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd,
337 struct v4l2_subdev_fh *fh,
338 struct v4l2_subdev_mbus_code_enum *code)
339{
340 if (code->index >= ARRAY_SIZE(s5pcsis_formats))
341 return -EINVAL;
342
343 code->code = s5pcsis_formats[code->index].code;
344 return 0;
345}
346
347static struct csis_pix_format const *s5pcsis_try_format(
348 struct v4l2_mbus_framefmt *mf)
349{
350 struct csis_pix_format const *csis_fmt;
351
352 csis_fmt = find_csis_format(mf);
353 if (csis_fmt == NULL)
354 csis_fmt = &s5pcsis_formats[0];
355
356 mf->code = csis_fmt->code;
357 v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH,
358 csis_fmt->pix_width_alignment,
359 &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1,
360 0);
361 return csis_fmt;
362}
363
364static struct v4l2_mbus_framefmt *__s5pcsis_get_format(
365 struct csis_state *state, struct v4l2_subdev_fh *fh,
366 u32 pad, enum v4l2_subdev_format_whence which)
367{
368 if (which == V4L2_SUBDEV_FORMAT_TRY)
369 return fh ? v4l2_subdev_get_try_format(fh, pad) : NULL;
370
371 return &state->format;
372}
373
374static int s5pcsis_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
375 struct v4l2_subdev_format *fmt)
376{
377 struct csis_state *state = sd_to_csis_state(sd);
378 struct csis_pix_format const *csis_fmt;
379 struct v4l2_mbus_framefmt *mf;
380
381 if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK)
382 return -EINVAL;
383
384 mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which);
385
386 if (fmt->pad == CSIS_PAD_SOURCE) {
387 if (mf) {
388 mutex_lock(&state->lock);
389 fmt->format = *mf;
390 mutex_unlock(&state->lock);
391 }
392 return 0;
393 }
394 csis_fmt = s5pcsis_try_format(&fmt->format);
395 if (mf) {
396 mutex_lock(&state->lock);
397 *mf = fmt->format;
398 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
399 state->csis_fmt = csis_fmt;
400 mutex_unlock(&state->lock);
401 }
402 return 0;
403}
404
405static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
406 struct v4l2_subdev_format *fmt)
407{
408 struct csis_state *state = sd_to_csis_state(sd);
409 struct v4l2_mbus_framefmt *mf;
410
411 if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK)
412 return -EINVAL;
413
414 mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which);
415 if (!mf)
416 return -EINVAL;
417
418 mutex_lock(&state->lock);
419 fmt->format = *mf;
420 mutex_unlock(&state->lock);
421 return 0;
422}
423
424static struct v4l2_subdev_core_ops s5pcsis_core_ops = {
425 .s_power = s5pcsis_s_power,
426};
427
428static struct v4l2_subdev_pad_ops s5pcsis_pad_ops = {
429 .enum_mbus_code = s5pcsis_enum_mbus_code,
430 .get_fmt = s5pcsis_get_fmt,
431 .set_fmt = s5pcsis_set_fmt,
432};
433
434static struct v4l2_subdev_video_ops s5pcsis_video_ops = {
435 .s_stream = s5pcsis_s_stream,
436};
437
438static struct v4l2_subdev_ops s5pcsis_subdev_ops = {
439 .core = &s5pcsis_core_ops,
440 .pad = &s5pcsis_pad_ops,
441 .video = &s5pcsis_video_ops,
442};
443
444static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id)
445{
446 struct csis_state *state = dev_id;
447 u32 val;
448
449 /* Just clear the interrupt pending bits. */
450 val = s5pcsis_read(state, S5PCSIS_INTSRC);
451 s5pcsis_write(state, S5PCSIS_INTSRC, val);
452
453 return IRQ_HANDLED;
454}
455
456static int __devinit s5pcsis_probe(struct platform_device *pdev)
457{
458 struct s5p_platform_mipi_csis *pdata;
459 struct resource *mem_res;
460 struct resource *regs_res;
461 struct csis_state *state;
462 int ret = -ENOMEM;
463
464 state = kzalloc(sizeof(*state), GFP_KERNEL);
465 if (!state)
466 return -ENOMEM;
467
468 mutex_init(&state->lock);
469 state->pdev = pdev;
470
471 pdata = pdev->dev.platform_data;
472 if (pdata == NULL || pdata->phy_enable == NULL) {
473 dev_err(&pdev->dev, "Platform data not fully specified\n");
474 goto e_free;
475 }
476
477 if ((pdev->id == 1 && pdata->lanes > CSIS1_MAX_LANES) ||
478 pdata->lanes > CSIS0_MAX_LANES) {
479 ret = -EINVAL;
480 dev_err(&pdev->dev, "Unsupported number of data lanes: %d\n",
481 pdata->lanes);
482 goto e_free;
483 }
484
485 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
486 if (!mem_res) {
487 dev_err(&pdev->dev, "Failed to get IO memory region\n");
488 goto e_free;
489 }
490
491 regs_res = request_mem_region(mem_res->start, resource_size(mem_res),
492 pdev->name);
493 if (!regs_res) {
494 dev_err(&pdev->dev, "Failed to request IO memory region\n");
495 goto e_free;
496 }
497 state->regs_res = regs_res;
498
499 state->regs = ioremap(mem_res->start, resource_size(mem_res));
500 if (!state->regs) {
501 dev_err(&pdev->dev, "Failed to remap IO region\n");
502 goto e_reqmem;
503 }
504
505 ret = s5pcsis_clk_get(state);
506 if (ret)
507 goto e_unmap;
508
509 clk_enable(state->clock[CSIS_CLK_MUX]);
510 if (pdata->clk_rate)
511 clk_set_rate(state->clock[CSIS_CLK_MUX], pdata->clk_rate);
512 else
513 dev_WARN(&pdev->dev, "No clock frequency specified!\n");
514
515 state->irq = platform_get_irq(pdev, 0);
516 if (state->irq < 0) {
517 ret = state->irq;
518 dev_err(&pdev->dev, "Failed to get irq\n");
519 goto e_clkput;
520 }
521
522 if (!pdata->fixed_phy_vdd) {
523 state->supply = regulator_get(&pdev->dev, "vdd");
524 if (IS_ERR(state->supply)) {
525 ret = PTR_ERR(state->supply);
526 state->supply = NULL;
527 goto e_clkput;
528 }
529 }
530
531 ret = request_irq(state->irq, s5pcsis_irq_handler, 0,
532 dev_name(&pdev->dev), state);
533 if (ret) {
534 dev_err(&pdev->dev, "request_irq failed\n");
535 goto e_regput;
536 }
537
538 v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops);
539 state->sd.owner = THIS_MODULE;
540 strlcpy(state->sd.name, dev_name(&pdev->dev), sizeof(state->sd.name));
541 state->csis_fmt = &s5pcsis_formats[0];
542
543 state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
544 state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
545 ret = media_entity_init(&state->sd.entity,
546 CSIS_PADS_NUM, state->pads, 0);
547 if (ret < 0)
548 goto e_irqfree;
549
550 /* This allows to retrieve the platform device id by the host driver */
551 v4l2_set_subdevdata(&state->sd, pdev);
552
553 /* .. and a pointer to the subdev. */
554 platform_set_drvdata(pdev, &state->sd);
555
556 state->flags = ST_SUSPENDED;
557 pm_runtime_enable(&pdev->dev);
558
559 return 0;
560
561e_irqfree:
562 free_irq(state->irq, state);
563e_regput:
564 if (state->supply)
565 regulator_put(state->supply);
566e_clkput:
567 clk_disable(state->clock[CSIS_CLK_MUX]);
568 s5pcsis_clk_put(state);
569e_unmap:
570 iounmap(state->regs);
571e_reqmem:
572 release_mem_region(regs_res->start, resource_size(regs_res));
573e_free:
574 kfree(state);
575 return ret;
576}
577
578static int s5pcsis_suspend(struct device *dev)
579{
580 struct s5p_platform_mipi_csis *pdata = dev->platform_data;
581 struct platform_device *pdev = to_platform_device(dev);
582 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
583 struct csis_state *state = sd_to_csis_state(sd);
584 int ret = 0;
585
586 v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
587 __func__, state->flags);
588
589 mutex_lock(&state->lock);
590 if (state->flags & ST_POWERED) {
591 s5pcsis_stop_stream(state);
592 ret = pdata->phy_enable(state->pdev, false);
593 if (ret)
594 goto unlock;
595 if (state->supply) {
596 ret = regulator_disable(state->supply);
597 if (ret)
598 goto unlock;
599 }
600 clk_disable(state->clock[CSIS_CLK_GATE]);
601 state->flags &= ~ST_POWERED;
602 }
603 state->flags |= ST_SUSPENDED;
604 unlock:
605 mutex_unlock(&state->lock);
606 return ret ? -EAGAIN : 0;
607}
608
609static int s5pcsis_resume(struct device *dev)
610{
611 struct s5p_platform_mipi_csis *pdata = dev->platform_data;
612 struct platform_device *pdev = to_platform_device(dev);
613 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
614 struct csis_state *state = sd_to_csis_state(sd);
615 int ret = 0;
616
617 v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
618 __func__, state->flags);
619
620 mutex_lock(&state->lock);
621 if (!(state->flags & ST_SUSPENDED))
622 goto unlock;
623
624 if (!(state->flags & ST_POWERED)) {
625 if (state->supply)
626 ret = regulator_enable(state->supply);
627 if (ret)
628 goto unlock;
629
630 ret = pdata->phy_enable(state->pdev, true);
631 if (!ret) {
632 state->flags |= ST_POWERED;
633 } else if (state->supply) {
634 regulator_disable(state->supply);
635 goto unlock;
636 }
637 clk_enable(state->clock[CSIS_CLK_GATE]);
638 }
639 if (state->flags & ST_STREAMING)
640 s5pcsis_start_stream(state);
641
642 state->flags &= ~ST_SUSPENDED;
643 unlock:
644 mutex_unlock(&state->lock);
645 return ret ? -EAGAIN : 0;
646}
647
648#ifdef CONFIG_PM_SLEEP
649static int s5pcsis_pm_suspend(struct device *dev)
650{
651 return s5pcsis_suspend(dev);
652}
653
654static int s5pcsis_pm_resume(struct device *dev)
655{
656 int ret;
657
658 ret = s5pcsis_resume(dev);
659
660 if (!ret) {
661 pm_runtime_disable(dev);
662 ret = pm_runtime_set_active(dev);
663 pm_runtime_enable(dev);
664 }
665
666 return ret;
667}
668#endif
669
670static int __devexit s5pcsis_remove(struct platform_device *pdev)
671{
672 struct v4l2_subdev *sd = platform_get_drvdata(pdev);
673 struct csis_state *state = sd_to_csis_state(sd);
674 struct resource *res = state->regs_res;
675
676 pm_runtime_disable(&pdev->dev);
677 s5pcsis_suspend(&pdev->dev);
678 clk_disable(state->clock[CSIS_CLK_MUX]);
679 pm_runtime_set_suspended(&pdev->dev);
680
681 s5pcsis_clk_put(state);
682 if (state->supply)
683 regulator_put(state->supply);
684
685 media_entity_cleanup(&state->sd.entity);
686 free_irq(state->irq, state);
687 iounmap(state->regs);
688 release_mem_region(res->start, resource_size(res));
689 kfree(state);
690
691 return 0;
692}
693
694static const struct dev_pm_ops s5pcsis_pm_ops = {
695 SET_RUNTIME_PM_OPS(s5pcsis_suspend, s5pcsis_resume, NULL)
696 SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_pm_suspend, s5pcsis_pm_resume)
697};
698
699static struct platform_driver s5pcsis_driver = {
700 .probe = s5pcsis_probe,
701 .remove = __devexit_p(s5pcsis_remove),
702 .driver = {
703 .name = CSIS_DRIVER_NAME,
704 .owner = THIS_MODULE,
705 .pm = &s5pcsis_pm_ops,
706 },
707};
708
709static int __init s5pcsis_init(void)
710{
711 return platform_driver_probe(&s5pcsis_driver, s5pcsis_probe);
712}
713
714static void __exit s5pcsis_exit(void)
715{
716 platform_driver_unregister(&s5pcsis_driver);
717}
718
719module_init(s5pcsis_init);
720module_exit(s5pcsis_exit);
721
722MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
723MODULE_DESCRIPTION("S5P/EXYNOS4 MIPI CSI receiver driver");
724MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/s5p-fimc/mipi-csis.h b/drivers/media/video/s5p-fimc/mipi-csis.h
new file mode 100644
index 00000000000..f5691336dd5
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/mipi-csis.h
@@ -0,0 +1,22 @@
1/*
2 * Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver
3 *
4 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef S5P_MIPI_CSIS_H_
11#define S5P_MIPI_CSIS_H_
12
13#define CSIS_DRIVER_NAME "s5p-mipi-csis"
14#define CSIS_MAX_ENTITIES 2
15#define CSIS0_MAX_LANES 4
16#define CSIS1_MAX_LANES 2
17
18#define CSIS_PAD_SINK 0
19#define CSIS_PAD_SOURCE 1
20#define CSIS_PADS_NUM 2
21
22#endif
diff --git a/drivers/media/video/s5p-fimc/regs-fimc.h b/drivers/media/video/s5p-fimc/regs-fimc.h
new file mode 100644
index 00000000000..0fea3e635d7
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/regs-fimc.h
@@ -0,0 +1,297 @@
1/*
2 * Register definition file for Samsung Camera Interface (FIMC) driver
3 *
4 * Copyright (c) 2010 Samsung Electronics
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef REGS_FIMC_H_
12#define REGS_FIMC_H_
13
14/* Input source format */
15#define S5P_CISRCFMT 0x00
16#define S5P_CISRCFMT_ITU601_8BIT (1 << 31)
17#define S5P_CISRCFMT_ITU601_16BIT (1 << 29)
18#define S5P_CISRCFMT_ORDER422_YCBYCR (0 << 14)
19#define S5P_CISRCFMT_ORDER422_YCRYCB (1 << 14)
20#define S5P_CISRCFMT_ORDER422_CBYCRY (2 << 14)
21#define S5P_CISRCFMT_ORDER422_CRYCBY (3 << 14)
22#define S5P_CISRCFMT_HSIZE(x) ((x) << 16)
23#define S5P_CISRCFMT_VSIZE(x) ((x) << 0)
24
25/* Window offset */
26#define S5P_CIWDOFST 0x04
27#define S5P_CIWDOFST_OFF_EN (1 << 31)
28#define S5P_CIWDOFST_CLROVFIY (1 << 30)
29#define S5P_CIWDOFST_CLROVRLB (1 << 29)
30#define S5P_CIWDOFST_HOROFF_MASK (0x7ff << 16)
31#define S5P_CIWDOFST_CLROVFICB (1 << 15)
32#define S5P_CIWDOFST_CLROVFICR (1 << 14)
33#define S5P_CIWDOFST_HOROFF(x) ((x) << 16)
34#define S5P_CIWDOFST_VEROFF(x) ((x) << 0)
35#define S5P_CIWDOFST_VEROFF_MASK (0xfff << 0)
36
37/* Global control */
38#define S5P_CIGCTRL 0x08
39#define S5P_CIGCTRL_SWRST (1 << 31)
40#define S5P_CIGCTRL_CAMRST_A (1 << 30)
41#define S5P_CIGCTRL_SELCAM_ITU_A (1 << 29)
42#define S5P_CIGCTRL_TESTPAT_NORMAL (0 << 27)
43#define S5P_CIGCTRL_TESTPAT_COLOR_BAR (1 << 27)
44#define S5P_CIGCTRL_TESTPAT_HOR_INC (2 << 27)
45#define S5P_CIGCTRL_TESTPAT_VER_INC (3 << 27)
46#define S5P_CIGCTRL_TESTPAT_MASK (3 << 27)
47#define S5P_CIGCTRL_TESTPAT_SHIFT (27)
48#define S5P_CIGCTRL_INVPOLPCLK (1 << 26)
49#define S5P_CIGCTRL_INVPOLVSYNC (1 << 25)
50#define S5P_CIGCTRL_INVPOLHREF (1 << 24)
51#define S5P_CIGCTRL_IRQ_OVFEN (1 << 22)
52#define S5P_CIGCTRL_HREF_MASK (1 << 21)
53#define S5P_CIGCTRL_IRQ_LEVEL (1 << 20)
54#define S5P_CIGCTRL_IRQ_CLR (1 << 19)
55#define S5P_CIGCTRL_IRQ_ENABLE (1 << 16)
56#define S5P_CIGCTRL_SHDW_DISABLE (1 << 12)
57#define S5P_CIGCTRL_SELCAM_MIPI_A (1 << 7)
58#define S5P_CIGCTRL_CAMIF_SELWB (1 << 6)
59/* 0 - ITU601; 1 - ITU709 */
60#define S5P_CIGCTRL_CSC_ITU601_709 (1 << 5)
61#define S5P_CIGCTRL_INVPOLHSYNC (1 << 4)
62#define S5P_CIGCTRL_SELCAM_MIPI (1 << 3)
63#define S5P_CIGCTRL_INTERLACE (1 << 0)
64
65/* Window offset 2 */
66#define S5P_CIWDOFST2 0x14
67#define S5P_CIWDOFST2_HOROFF_MASK (0xfff << 16)
68#define S5P_CIWDOFST2_VEROFF_MASK (0xfff << 0)
69#define S5P_CIWDOFST2_HOROFF(x) ((x) << 16)
70#define S5P_CIWDOFST2_VEROFF(x) ((x) << 0)
71
72/* Output DMA Y/Cb/Cr plane start addresses */
73#define S5P_CIOYSA(n) (0x18 + (n) * 4)
74#define S5P_CIOCBSA(n) (0x28 + (n) * 4)
75#define S5P_CIOCRSA(n) (0x38 + (n) * 4)
76
77/* Target image format */
78#define S5P_CITRGFMT 0x48
79#define S5P_CITRGFMT_INROT90 (1 << 31)
80#define S5P_CITRGFMT_YCBCR420 (0 << 29)
81#define S5P_CITRGFMT_YCBCR422 (1 << 29)
82#define S5P_CITRGFMT_YCBCR422_1P (2 << 29)
83#define S5P_CITRGFMT_RGB (3 << 29)
84#define S5P_CITRGFMT_FMT_MASK (3 << 29)
85#define S5P_CITRGFMT_HSIZE_MASK (0xfff << 16)
86#define S5P_CITRGFMT_FLIP_SHIFT (14)
87#define S5P_CITRGFMT_FLIP_NORMAL (0 << 14)
88#define S5P_CITRGFMT_FLIP_X_MIRROR (1 << 14)
89#define S5P_CITRGFMT_FLIP_Y_MIRROR (2 << 14)
90#define S5P_CITRGFMT_FLIP_180 (3 << 14)
91#define S5P_CITRGFMT_FLIP_MASK (3 << 14)
92#define S5P_CITRGFMT_OUTROT90 (1 << 13)
93#define S5P_CITRGFMT_VSIZE_MASK (0xfff << 0)
94#define S5P_CITRGFMT_HSIZE(x) ((x) << 16)
95#define S5P_CITRGFMT_VSIZE(x) ((x) << 0)
96
97/* Output DMA control */
98#define S5P_CIOCTRL 0x4c
99#define S5P_CIOCTRL_ORDER422_MASK (3 << 0)
100#define S5P_CIOCTRL_ORDER422_CRYCBY (0 << 0)
101#define S5P_CIOCTRL_ORDER422_CBYCRY (1 << 0)
102#define S5P_CIOCTRL_ORDER422_YCRYCB (2 << 0)
103#define S5P_CIOCTRL_ORDER422_YCBYCR (3 << 0)
104#define S5P_CIOCTRL_LASTIRQ_ENABLE (1 << 2)
105#define S5P_CIOCTRL_YCBCR_3PLANE (0 << 3)
106#define S5P_CIOCTRL_YCBCR_2PLANE (1 << 3)
107#define S5P_CIOCTRL_YCBCR_PLANE_MASK (1 << 3)
108#define S5P_CIOCTRL_ORDER2P_SHIFT (24)
109#define S5P_CIOCTRL_ORDER2P_MASK (3 << 24)
110#define S5P_CIOCTRL_ORDER422_2P_LSB_CRCB (0 << 24)
111
112/* Pre-scaler control 1 */
113#define S5P_CISCPRERATIO 0x50
114#define S5P_CISCPRERATIO_SHFACTOR(x) ((x) << 28)
115#define S5P_CISCPRERATIO_HOR(x) ((x) << 16)
116#define S5P_CISCPRERATIO_VER(x) ((x) << 0)
117
118#define S5P_CISCPREDST 0x54
119#define S5P_CISCPREDST_WIDTH(x) ((x) << 16)
120#define S5P_CISCPREDST_HEIGHT(x) ((x) << 0)
121
122/* Main scaler control */
123#define S5P_CISCCTRL 0x58
124#define S5P_CISCCTRL_SCALERBYPASS (1 << 31)
125#define S5P_CISCCTRL_SCALEUP_H (1 << 30)
126#define S5P_CISCCTRL_SCALEUP_V (1 << 29)
127#define S5P_CISCCTRL_CSCR2Y_WIDE (1 << 28)
128#define S5P_CISCCTRL_CSCY2R_WIDE (1 << 27)
129#define S5P_CISCCTRL_LCDPATHEN_FIFO (1 << 26)
130#define S5P_CISCCTRL_INTERLACE (1 << 25)
131#define S5P_CISCCTRL_SCALERSTART (1 << 15)
132#define S5P_CISCCTRL_INRGB_FMT_RGB565 (0 << 13)
133#define S5P_CISCCTRL_INRGB_FMT_RGB666 (1 << 13)
134#define S5P_CISCCTRL_INRGB_FMT_RGB888 (2 << 13)
135#define S5P_CISCCTRL_INRGB_FMT_MASK (3 << 13)
136#define S5P_CISCCTRL_OUTRGB_FMT_RGB565 (0 << 11)
137#define S5P_CISCCTRL_OUTRGB_FMT_RGB666 (1 << 11)
138#define S5P_CISCCTRL_OUTRGB_FMT_RGB888 (2 << 11)
139#define S5P_CISCCTRL_OUTRGB_FMT_MASK (3 << 11)
140#define S5P_CISCCTRL_RGB_EXT (1 << 10)
141#define S5P_CISCCTRL_ONE2ONE (1 << 9)
142#define S5P_CISCCTRL_MHRATIO(x) ((x) << 16)
143#define S5P_CISCCTRL_MVRATIO(x) ((x) << 0)
144#define S5P_CISCCTRL_MHRATIO_MASK (0x1ff << 16)
145#define S5P_CISCCTRL_MVRATIO_MASK (0x1ff << 0)
146#define S5P_CISCCTRL_MHRATIO_EXT(x) (((x) >> 6) << 16)
147#define S5P_CISCCTRL_MVRATIO_EXT(x) (((x) >> 6) << 0)
148
149/* Target area */
150#define S5P_CITAREA 0x5c
151#define S5P_CITAREA_MASK 0x0fffffff
152
153/* General status */
154#define S5P_CISTATUS 0x64
155#define S5P_CISTATUS_OVFIY (1 << 31)
156#define S5P_CISTATUS_OVFICB (1 << 30)
157#define S5P_CISTATUS_OVFICR (1 << 29)
158#define S5P_CISTATUS_VSYNC (1 << 28)
159#define S5P_CISTATUS_FRAMECNT_MASK (3 << 26)
160#define S5P_CISTATUS_FRAMECNT_SHIFT 26
161#define S5P_CISTATUS_WINOFF_EN (1 << 25)
162#define S5P_CISTATUS_IMGCPT_EN (1 << 22)
163#define S5P_CISTATUS_IMGCPT_SCEN (1 << 21)
164#define S5P_CISTATUS_VSYNC_A (1 << 20)
165#define S5P_CISTATUS_VSYNC_B (1 << 19)
166#define S5P_CISTATUS_OVRLB (1 << 18)
167#define S5P_CISTATUS_FRAME_END (1 << 17)
168#define S5P_CISTATUS_LASTCAPT_END (1 << 16)
169#define S5P_CISTATUS_VVALID_A (1 << 15)
170#define S5P_CISTATUS_VVALID_B (1 << 14)
171
172/* Indexes to the last and the currently processed buffer. */
173#define S5P_CISTATUS2 0x68
174
175/* Image capture control */
176#define S5P_CIIMGCPT 0xc0
177#define S5P_CIIMGCPT_IMGCPTEN (1 << 31)
178#define S5P_CIIMGCPT_IMGCPTEN_SC (1 << 30)
179#define S5P_CIIMGCPT_CPT_FREN_ENABLE (1 << 25)
180#define S5P_CIIMGCPT_CPT_FRMOD_CNT (1 << 18)
181
182/* Frame capture sequence */
183#define S5P_CICPTSEQ 0xc4
184
185/* Image effect */
186#define S5P_CIIMGEFF 0xd0
187#define S5P_CIIMGEFF_IE_DISABLE (0 << 30)
188#define S5P_CIIMGEFF_IE_ENABLE (1 << 30)
189#define S5P_CIIMGEFF_IE_SC_BEFORE (0 << 29)
190#define S5P_CIIMGEFF_IE_SC_AFTER (1 << 29)
191#define S5P_CIIMGEFF_FIN_BYPASS (0 << 26)
192#define S5P_CIIMGEFF_FIN_ARBITRARY (1 << 26)
193#define S5P_CIIMGEFF_FIN_NEGATIVE (2 << 26)
194#define S5P_CIIMGEFF_FIN_ARTFREEZE (3 << 26)
195#define S5P_CIIMGEFF_FIN_EMBOSSING (4 << 26)
196#define S5P_CIIMGEFF_FIN_SILHOUETTE (5 << 26)
197#define S5P_CIIMGEFF_FIN_MASK (7 << 26)
198#define S5P_CIIMGEFF_PAT_CBCR_MASK ((0xff < 13) | (0xff < 0))
199#define S5P_CIIMGEFF_PAT_CB(x) ((x) << 13)
200#define S5P_CIIMGEFF_PAT_CR(x) ((x) << 0)
201
202/* Input DMA Y/Cb/Cr plane start address 0/1 */
203#define S5P_CIIYSA(n) (0xd4 + (n) * 0x70)
204#define S5P_CIICBSA(n) (0xd8 + (n) * 0x70)
205#define S5P_CIICRSA(n) (0xdc + (n) * 0x70)
206
207/* Real input DMA image size */
208#define S5P_CIREAL_ISIZE 0xf8
209#define S5P_CIREAL_ISIZE_AUTOLOAD_EN (1 << 31)
210#define S5P_CIREAL_ISIZE_ADDR_CH_DIS (1 << 30)
211#define S5P_CIREAL_ISIZE_HEIGHT(x) ((x) << 16)
212#define S5P_CIREAL_ISIZE_WIDTH(x) ((x) << 0)
213
214
215/* Input DMA control */
216#define S5P_MSCTRL 0xfc
217#define S5P_MSCTRL_IN_BURST_COUNT_MASK (0xF << 24)
218#define S5P_MSCTRL_2P_IN_ORDER_MASK (3 << 16)
219#define S5P_MSCTRL_2P_IN_ORDER_SHIFT 16
220#define S5P_MSCTRL_C_INT_IN_3PLANE (0 << 15)
221#define S5P_MSCTRL_C_INT_IN_2PLANE (1 << 15)
222#define S5P_MSCTRL_C_INT_IN_MASK (1 << 15)
223#define S5P_MSCTRL_FLIP_SHIFT 13
224#define S5P_MSCTRL_FLIP_MASK (3 << 13)
225#define S5P_MSCTRL_FLIP_NORMAL (0 << 13)
226#define S5P_MSCTRL_FLIP_X_MIRROR (1 << 13)
227#define S5P_MSCTRL_FLIP_Y_MIRROR (2 << 13)
228#define S5P_MSCTRL_FLIP_180 (3 << 13)
229#define S5P_MSCTRL_FIFO_CTRL_FULL (1 << 12)
230#define S5P_MSCTRL_ORDER422_SHIFT 4
231#define S5P_MSCTRL_ORDER422_YCBYCR (0 << 4)
232#define S5P_MSCTRL_ORDER422_CBYCRY (1 << 4)
233#define S5P_MSCTRL_ORDER422_YCRYCB (2 << 4)
234#define S5P_MSCTRL_ORDER422_CRYCBY (3 << 4)
235#define S5P_MSCTRL_ORDER422_MASK (3 << 4)
236#define S5P_MSCTRL_INPUT_EXTCAM (0 << 3)
237#define S5P_MSCTRL_INPUT_MEMORY (1 << 3)
238#define S5P_MSCTRL_INPUT_MASK (1 << 3)
239#define S5P_MSCTRL_INFORMAT_YCBCR420 (0 << 1)
240#define S5P_MSCTRL_INFORMAT_YCBCR422 (1 << 1)
241#define S5P_MSCTRL_INFORMAT_YCBCR422_1P (2 << 1)
242#define S5P_MSCTRL_INFORMAT_RGB (3 << 1)
243#define S5P_MSCTRL_INFORMAT_MASK (3 << 1)
244#define S5P_MSCTRL_ENVID (1 << 0)
245#define S5P_MSCTRL_IN_BURST_COUNT(x) ((x) << 24)
246
247/* Output DMA Y/Cb/Cr offset */
248#define S5P_CIOYOFF 0x168
249#define S5P_CIOCBOFF 0x16c
250#define S5P_CIOCROFF 0x170
251
252/* Input DMA Y/Cb/Cr offset */
253#define S5P_CIIYOFF 0x174
254#define S5P_CIICBOFF 0x178
255#define S5P_CIICROFF 0x17c
256
257#define S5P_CIO_OFFS_VER(x) ((x) << 16)
258#define S5P_CIO_OFFS_HOR(x) ((x) << 0)
259
260/* Input DMA original image size */
261#define S5P_ORGISIZE 0x180
262
263/* Output DMA original image size */
264#define S5P_ORGOSIZE 0x184
265
266#define S5P_ORIG_SIZE_VER(x) ((x) << 16)
267#define S5P_ORIG_SIZE_HOR(x) ((x) << 0)
268
269/* Real output DMA image size (extension register) */
270#define S5P_CIEXTEN 0x188
271#define S5P_CIEXTEN_MHRATIO_EXT(x) (((x) & 0x3f) << 10)
272#define S5P_CIEXTEN_MVRATIO_EXT(x) ((x) & 0x3f)
273#define S5P_CIEXTEN_MHRATIO_EXT_MASK (0x3f << 10)
274#define S5P_CIEXTEN_MVRATIO_EXT_MASK 0x3f
275
276#define S5P_CIDMAPARAM 0x18c
277#define S5P_CIDMAPARAM_R_LINEAR (0 << 29)
278#define S5P_CIDMAPARAM_R_64X32 (3 << 29)
279#define S5P_CIDMAPARAM_W_LINEAR (0 << 13)
280#define S5P_CIDMAPARAM_W_64X32 (3 << 13)
281#define S5P_CIDMAPARAM_TILE_MASK ((3 << 29) | (3 << 13))
282
283/* MIPI CSI image format */
284#define S5P_CSIIMGFMT 0x194
285#define S5P_CSIIMGFMT_YCBCR422_8BIT 0x1e
286#define S5P_CSIIMGFMT_RAW8 0x2a
287#define S5P_CSIIMGFMT_RAW10 0x2b
288#define S5P_CSIIMGFMT_RAW12 0x2c
289#define S5P_CSIIMGFMT_USER1 0x30
290#define S5P_CSIIMGFMT_USER2 0x31
291#define S5P_CSIIMGFMT_USER3 0x32
292#define S5P_CSIIMGFMT_USER4 0x33
293
294/* Output frame buffer sequence mask */
295#define S5P_CIFCNTSEQ 0x1FC
296
297#endif /* REGS_FIMC_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-14 22:23:10 -0400