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path: root/drivers/media/video/s5p-fimc/fimc-core.c
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Diffstat (limited to 'drivers/media/video/s5p-fimc/fimc-core.c')
-rw-r--r--drivers/media/video/s5p-fimc/fimc-core.c1938
1 files changed, 1938 insertions, 0 deletions
diff --git a/drivers/media/video/s5p-fimc/fimc-core.c b/drivers/media/video/s5p-fimc/fimc-core.c
new file mode 100644
index 00000000000..b062b1a6768
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/fimc-core.c
@@ -0,0 +1,1938 @@
1/*
2 * Samsung S5P/EXYNOS4 SoC series camera interface (video postprocessor) driver
3 *
4 * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
5 * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published
9 * by the Free Software Foundation, either version 2 of the License,
10 * or (at your option) any later version.
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/errno.h>
17#include <linux/bug.h>
18#include <linux/interrupt.h>
19#include <linux/device.h>
20#include <linux/platform_device.h>
21#include <linux/list.h>
22#include <linux/io.h>
23#include <linux/slab.h>
24#include <linux/clk.h>
25#include <media/v4l2-ioctl.h>
26#include <media/videobuf2-core.h>
27#include <media/videobuf2-dma-contig.h>
28
29#include "fimc-core.h"
30
31static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
32 "sclk_fimc", "fimc", "sclk_cam"
33};
34
35static struct fimc_fmt fimc_formats[] = {
36 {
37 .name = "RGB565",
38 .fourcc = V4L2_PIX_FMT_RGB565,
39 .depth = { 16 },
40 .color = S5P_FIMC_RGB565,
41 .memplanes = 1,
42 .colplanes = 1,
43 .flags = FMT_FLAGS_M2M,
44 }, {
45 .name = "BGR666",
46 .fourcc = V4L2_PIX_FMT_BGR666,
47 .depth = { 32 },
48 .color = S5P_FIMC_RGB666,
49 .memplanes = 1,
50 .colplanes = 1,
51 .flags = FMT_FLAGS_M2M,
52 }, {
53 .name = "XRGB-8-8-8-8, 32 bpp",
54 .fourcc = V4L2_PIX_FMT_RGB32,
55 .depth = { 32 },
56 .color = S5P_FIMC_RGB888,
57 .memplanes = 1,
58 .colplanes = 1,
59 .flags = FMT_FLAGS_M2M,
60 }, {
61 .name = "YUV 4:2:2 packed, YCbYCr",
62 .fourcc = V4L2_PIX_FMT_YUYV,
63 .depth = { 16 },
64 .color = S5P_FIMC_YCBYCR422,
65 .memplanes = 1,
66 .colplanes = 1,
67 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
68 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
69 }, {
70 .name = "YUV 4:2:2 packed, CbYCrY",
71 .fourcc = V4L2_PIX_FMT_UYVY,
72 .depth = { 16 },
73 .color = S5P_FIMC_CBYCRY422,
74 .memplanes = 1,
75 .colplanes = 1,
76 .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
77 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
78 }, {
79 .name = "YUV 4:2:2 packed, CrYCbY",
80 .fourcc = V4L2_PIX_FMT_VYUY,
81 .depth = { 16 },
82 .color = S5P_FIMC_CRYCBY422,
83 .memplanes = 1,
84 .colplanes = 1,
85 .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
86 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
87 }, {
88 .name = "YUV 4:2:2 packed, YCrYCb",
89 .fourcc = V4L2_PIX_FMT_YVYU,
90 .depth = { 16 },
91 .color = S5P_FIMC_YCRYCB422,
92 .memplanes = 1,
93 .colplanes = 1,
94 .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
95 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
96 }, {
97 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
98 .fourcc = V4L2_PIX_FMT_YUV422P,
99 .depth = { 12 },
100 .color = S5P_FIMC_YCBYCR422,
101 .memplanes = 1,
102 .colplanes = 3,
103 .flags = FMT_FLAGS_M2M,
104 }, {
105 .name = "YUV 4:2:2 planar, Y/CbCr",
106 .fourcc = V4L2_PIX_FMT_NV16,
107 .depth = { 16 },
108 .color = S5P_FIMC_YCBYCR422,
109 .memplanes = 1,
110 .colplanes = 2,
111 .flags = FMT_FLAGS_M2M,
112 }, {
113 .name = "YUV 4:2:2 planar, Y/CrCb",
114 .fourcc = V4L2_PIX_FMT_NV61,
115 .depth = { 16 },
116 .color = S5P_FIMC_YCRYCB422,
117 .memplanes = 1,
118 .colplanes = 2,
119 .flags = FMT_FLAGS_M2M,
120 }, {
121 .name = "YUV 4:2:0 planar, YCbCr",
122 .fourcc = V4L2_PIX_FMT_YUV420,
123 .depth = { 12 },
124 .color = S5P_FIMC_YCBCR420,
125 .memplanes = 1,
126 .colplanes = 3,
127 .flags = FMT_FLAGS_M2M,
128 }, {
129 .name = "YUV 4:2:0 planar, Y/CbCr",
130 .fourcc = V4L2_PIX_FMT_NV12,
131 .depth = { 12 },
132 .color = S5P_FIMC_YCBCR420,
133 .memplanes = 1,
134 .colplanes = 2,
135 .flags = FMT_FLAGS_M2M,
136 }, {
137 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
138 .fourcc = V4L2_PIX_FMT_NV12M,
139 .color = S5P_FIMC_YCBCR420,
140 .depth = { 8, 4 },
141 .memplanes = 2,
142 .colplanes = 2,
143 .flags = FMT_FLAGS_M2M,
144 }, {
145 .name = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
146 .fourcc = V4L2_PIX_FMT_YUV420M,
147 .color = S5P_FIMC_YCBCR420,
148 .depth = { 8, 2, 2 },
149 .memplanes = 3,
150 .colplanes = 3,
151 .flags = FMT_FLAGS_M2M,
152 }, {
153 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
154 .fourcc = V4L2_PIX_FMT_NV12MT,
155 .color = S5P_FIMC_YCBCR420,
156 .depth = { 8, 4 },
157 .memplanes = 2,
158 .colplanes = 2,
159 .flags = FMT_FLAGS_M2M,
160 },
161};
162
163static struct v4l2_queryctrl fimc_ctrls[] = {
164 {
165 .id = V4L2_CID_HFLIP,
166 .type = V4L2_CTRL_TYPE_BOOLEAN,
167 .name = "Horizontal flip",
168 .minimum = 0,
169 .maximum = 1,
170 .default_value = 0,
171 }, {
172 .id = V4L2_CID_VFLIP,
173 .type = V4L2_CTRL_TYPE_BOOLEAN,
174 .name = "Vertical flip",
175 .minimum = 0,
176 .maximum = 1,
177 .default_value = 0,
178 }, {
179 .id = V4L2_CID_ROTATE,
180 .type = V4L2_CTRL_TYPE_INTEGER,
181 .name = "Rotation (CCW)",
182 .minimum = 0,
183 .maximum = 270,
184 .step = 90,
185 .default_value = 0,
186 },
187};
188
189
190static struct v4l2_queryctrl *get_ctrl(int id)
191{
192 int i;
193
194 for (i = 0; i < ARRAY_SIZE(fimc_ctrls); ++i)
195 if (id == fimc_ctrls[i].id)
196 return &fimc_ctrls[i];
197 return NULL;
198}
199
200int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot)
201{
202 int tx, ty;
203
204 if (rot == 90 || rot == 270) {
205 ty = dw;
206 tx = dh;
207 } else {
208 tx = dw;
209 ty = dh;
210 }
211
212 if ((sw >= SCALER_MAX_HRATIO * tx) || (sh >= SCALER_MAX_VRATIO * ty))
213 return -EINVAL;
214
215 return 0;
216}
217
218static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
219{
220 u32 sh = 6;
221
222 if (src >= 64 * tar)
223 return -EINVAL;
224
225 while (sh--) {
226 u32 tmp = 1 << sh;
227 if (src >= tar * tmp) {
228 *shift = sh, *ratio = tmp;
229 return 0;
230 }
231 }
232 *shift = 0, *ratio = 1;
233 return 0;
234}
235
236int fimc_set_scaler_info(struct fimc_ctx *ctx)
237{
238 struct fimc_scaler *sc = &ctx->scaler;
239 struct fimc_frame *s_frame = &ctx->s_frame;
240 struct fimc_frame *d_frame = &ctx->d_frame;
241 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
242 int tx, ty, sx, sy;
243 int ret;
244
245 if (ctx->rotation == 90 || ctx->rotation == 270) {
246 ty = d_frame->width;
247 tx = d_frame->height;
248 } else {
249 tx = d_frame->width;
250 ty = d_frame->height;
251 }
252 if (tx <= 0 || ty <= 0) {
253 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
254 "invalid target size: %d x %d", tx, ty);
255 return -EINVAL;
256 }
257
258 sx = s_frame->width;
259 sy = s_frame->height;
260 if (sx <= 0 || sy <= 0) {
261 err("invalid source size: %d x %d", sx, sy);
262 return -EINVAL;
263 }
264 sc->real_width = sx;
265 sc->real_height = sy;
266
267 ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
268 if (ret)
269 return ret;
270
271 ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
272 if (ret)
273 return ret;
274
275 sc->pre_dst_width = sx / sc->pre_hratio;
276 sc->pre_dst_height = sy / sc->pre_vratio;
277
278 if (variant->has_mainscaler_ext) {
279 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
280 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
281 } else {
282 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
283 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
284
285 }
286
287 sc->scaleup_h = (tx >= sx) ? 1 : 0;
288 sc->scaleup_v = (ty >= sy) ? 1 : 0;
289
290 /* check to see if input and output size/format differ */
291 if (s_frame->fmt->color == d_frame->fmt->color
292 && s_frame->width == d_frame->width
293 && s_frame->height == d_frame->height)
294 sc->copy_mode = 1;
295 else
296 sc->copy_mode = 0;
297
298 return 0;
299}
300
301static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
302{
303 struct vb2_buffer *src_vb, *dst_vb;
304 struct fimc_dev *fimc = ctx->fimc_dev;
305
306 if (!ctx || !ctx->m2m_ctx)
307 return;
308
309 src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
310 dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
311
312 if (src_vb && dst_vb) {
313 v4l2_m2m_buf_done(src_vb, vb_state);
314 v4l2_m2m_buf_done(dst_vb, vb_state);
315 v4l2_m2m_job_finish(fimc->m2m.m2m_dev, ctx->m2m_ctx);
316 }
317}
318
319/* Complete the transaction which has been scheduled for execution. */
320static void fimc_m2m_shutdown(struct fimc_ctx *ctx)
321{
322 struct fimc_dev *fimc = ctx->fimc_dev;
323 int ret;
324
325 if (!fimc_m2m_pending(fimc))
326 return;
327
328 fimc_ctx_state_lock_set(FIMC_CTX_SHUT, ctx);
329
330 ret = wait_event_timeout(fimc->irq_queue,
331 !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
332 FIMC_SHUTDOWN_TIMEOUT);
333 /*
334 * In case of a timeout the buffers are not released in the interrupt
335 * handler so return them here with the error flag set, if there are
336 * any on the queue.
337 */
338 if (ret == 0)
339 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
340}
341
342static int stop_streaming(struct vb2_queue *q)
343{
344 struct fimc_ctx *ctx = q->drv_priv;
345
346 fimc_m2m_shutdown(ctx);
347
348 return 0;
349}
350
351static void fimc_capture_irq_handler(struct fimc_dev *fimc)
352{
353 struct fimc_vid_cap *cap = &fimc->vid_cap;
354 struct fimc_vid_buffer *v_buf;
355 struct timeval *tv;
356 struct timespec ts;
357
358 if (!list_empty(&cap->active_buf_q) &&
359 test_bit(ST_CAPT_RUN, &fimc->state)) {
360 ktime_get_real_ts(&ts);
361
362 v_buf = active_queue_pop(cap);
363
364 tv = &v_buf->vb.v4l2_buf.timestamp;
365 tv->tv_sec = ts.tv_sec;
366 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
367 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
368
369 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
370 }
371
372 if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
373 wake_up(&fimc->irq_queue);
374 return;
375 }
376
377 if (!list_empty(&cap->pending_buf_q)) {
378
379 v_buf = pending_queue_pop(cap);
380 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
381 v_buf->index = cap->buf_index;
382
383 /* Move the buffer to the capture active queue */
384 active_queue_add(cap, v_buf);
385
386 dbg("next frame: %d, done frame: %d",
387 fimc_hw_get_frame_index(fimc), v_buf->index);
388
389 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
390 cap->buf_index = 0;
391 }
392
393 if (cap->active_buf_cnt == 0) {
394 clear_bit(ST_CAPT_RUN, &fimc->state);
395
396 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
397 cap->buf_index = 0;
398 } else {
399 set_bit(ST_CAPT_RUN, &fimc->state);
400 }
401
402 dbg("frame: %d, active_buf_cnt: %d",
403 fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
404}
405
406static irqreturn_t fimc_isr(int irq, void *priv)
407{
408 struct fimc_dev *fimc = priv;
409 struct fimc_vid_cap *cap = &fimc->vid_cap;
410 struct fimc_ctx *ctx;
411
412 fimc_hw_clear_irq(fimc);
413
414 if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
415 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
416 if (ctx != NULL) {
417 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
418
419 spin_lock(&ctx->slock);
420 if (ctx->state & FIMC_CTX_SHUT) {
421 ctx->state &= ~FIMC_CTX_SHUT;
422 wake_up(&fimc->irq_queue);
423 }
424 spin_unlock(&ctx->slock);
425 }
426
427 return IRQ_HANDLED;
428 }
429
430 spin_lock(&fimc->slock);
431
432 if (test_bit(ST_CAPT_PEND, &fimc->state)) {
433 fimc_capture_irq_handler(fimc);
434
435 if (cap->active_buf_cnt == 1) {
436 fimc_deactivate_capture(fimc);
437 clear_bit(ST_CAPT_STREAM, &fimc->state);
438 }
439 }
440
441 spin_unlock(&fimc->slock);
442 return IRQ_HANDLED;
443}
444
445/* The color format (colplanes, memplanes) must be already configured. */
446int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
447 struct fimc_frame *frame, struct fimc_addr *paddr)
448{
449 int ret = 0;
450 u32 pix_size;
451
452 if (vb == NULL || frame == NULL)
453 return -EINVAL;
454
455 pix_size = frame->width * frame->height;
456
457 dbg("memplanes= %d, colplanes= %d, pix_size= %d",
458 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
459
460 paddr->y = vb2_dma_contig_plane_paddr(vb, 0);
461
462 if (frame->fmt->memplanes == 1) {
463 switch (frame->fmt->colplanes) {
464 case 1:
465 paddr->cb = 0;
466 paddr->cr = 0;
467 break;
468 case 2:
469 /* decompose Y into Y/Cb */
470 paddr->cb = (u32)(paddr->y + pix_size);
471 paddr->cr = 0;
472 break;
473 case 3:
474 paddr->cb = (u32)(paddr->y + pix_size);
475 /* decompose Y into Y/Cb/Cr */
476 if (S5P_FIMC_YCBCR420 == frame->fmt->color)
477 paddr->cr = (u32)(paddr->cb
478 + (pix_size >> 2));
479 else /* 422 */
480 paddr->cr = (u32)(paddr->cb
481 + (pix_size >> 1));
482 break;
483 default:
484 return -EINVAL;
485 }
486 } else {
487 if (frame->fmt->memplanes >= 2)
488 paddr->cb = vb2_dma_contig_plane_paddr(vb, 1);
489
490 if (frame->fmt->memplanes == 3)
491 paddr->cr = vb2_dma_contig_plane_paddr(vb, 2);
492 }
493
494 dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
495 paddr->y, paddr->cb, paddr->cr, ret);
496
497 return ret;
498}
499
500/* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
501static void fimc_set_yuv_order(struct fimc_ctx *ctx)
502{
503 /* The one only mode supported in SoC. */
504 ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
505 ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
506
507 /* Set order for 1 plane input formats. */
508 switch (ctx->s_frame.fmt->color) {
509 case S5P_FIMC_YCRYCB422:
510 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
511 break;
512 case S5P_FIMC_CBYCRY422:
513 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
514 break;
515 case S5P_FIMC_CRYCBY422:
516 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
517 break;
518 case S5P_FIMC_YCBYCR422:
519 default:
520 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
521 break;
522 }
523 dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
524
525 switch (ctx->d_frame.fmt->color) {
526 case S5P_FIMC_YCRYCB422:
527 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
528 break;
529 case S5P_FIMC_CBYCRY422:
530 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
531 break;
532 case S5P_FIMC_CRYCBY422:
533 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
534 break;
535 case S5P_FIMC_YCBYCR422:
536 default:
537 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
538 break;
539 }
540 dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
541}
542
543static void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
544{
545 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
546 u32 i, depth = 0;
547
548 for (i = 0; i < f->fmt->colplanes; i++)
549 depth += f->fmt->depth[i];
550
551 f->dma_offset.y_h = f->offs_h;
552 if (!variant->pix_hoff)
553 f->dma_offset.y_h *= (depth >> 3);
554
555 f->dma_offset.y_v = f->offs_v;
556
557 f->dma_offset.cb_h = f->offs_h;
558 f->dma_offset.cb_v = f->offs_v;
559
560 f->dma_offset.cr_h = f->offs_h;
561 f->dma_offset.cr_v = f->offs_v;
562
563 if (!variant->pix_hoff) {
564 if (f->fmt->colplanes == 3) {
565 f->dma_offset.cb_h >>= 1;
566 f->dma_offset.cr_h >>= 1;
567 }
568 if (f->fmt->color == S5P_FIMC_YCBCR420) {
569 f->dma_offset.cb_v >>= 1;
570 f->dma_offset.cr_v >>= 1;
571 }
572 }
573
574 dbg("in_offset: color= %d, y_h= %d, y_v= %d",
575 f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
576}
577
578/**
579 * fimc_prepare_config - check dimensions, operation and color mode
580 * and pre-calculate offset and the scaling coefficients.
581 *
582 * @ctx: hardware context information
583 * @flags: flags indicating which parameters to check/update
584 *
585 * Return: 0 if dimensions are valid or non zero otherwise.
586 */
587int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
588{
589 struct fimc_frame *s_frame, *d_frame;
590 struct vb2_buffer *vb = NULL;
591 int ret = 0;
592
593 s_frame = &ctx->s_frame;
594 d_frame = &ctx->d_frame;
595
596 if (flags & FIMC_PARAMS) {
597 /* Prepare the DMA offset ratios for scaler. */
598 fimc_prepare_dma_offset(ctx, &ctx->s_frame);
599 fimc_prepare_dma_offset(ctx, &ctx->d_frame);
600
601 if (s_frame->height > (SCALER_MAX_VRATIO * d_frame->height) ||
602 s_frame->width > (SCALER_MAX_HRATIO * d_frame->width)) {
603 err("out of scaler range");
604 return -EINVAL;
605 }
606 fimc_set_yuv_order(ctx);
607 }
608
609 /* Input DMA mode is not allowed when the scaler is disabled. */
610 ctx->scaler.enabled = 1;
611
612 if (flags & FIMC_SRC_ADDR) {
613 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
614 ret = fimc_prepare_addr(ctx, vb, s_frame, &s_frame->paddr);
615 if (ret)
616 return ret;
617 }
618
619 if (flags & FIMC_DST_ADDR) {
620 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
621 ret = fimc_prepare_addr(ctx, vb, d_frame, &d_frame->paddr);
622 }
623
624 return ret;
625}
626
627static void fimc_dma_run(void *priv)
628{
629 struct fimc_ctx *ctx = priv;
630 struct fimc_dev *fimc;
631 unsigned long flags;
632 u32 ret;
633
634 if (WARN(!ctx, "null hardware context\n"))
635 return;
636
637 fimc = ctx->fimc_dev;
638
639 spin_lock_irqsave(&ctx->slock, flags);
640 set_bit(ST_M2M_PEND, &fimc->state);
641
642 ctx->state |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
643 ret = fimc_prepare_config(ctx, ctx->state);
644 if (ret)
645 goto dma_unlock;
646
647 /* Reconfigure hardware if the context has changed. */
648 if (fimc->m2m.ctx != ctx) {
649 ctx->state |= FIMC_PARAMS;
650 fimc->m2m.ctx = ctx;
651 }
652
653 spin_lock(&fimc->slock);
654 fimc_hw_set_input_addr(fimc, &ctx->s_frame.paddr);
655
656 if (ctx->state & FIMC_PARAMS) {
657 fimc_hw_set_input_path(ctx);
658 fimc_hw_set_in_dma(ctx);
659 ret = fimc_set_scaler_info(ctx);
660 if (ret) {
661 spin_unlock(&fimc->slock);
662 goto dma_unlock;
663 }
664 fimc_hw_set_prescaler(ctx);
665 fimc_hw_set_mainscaler(ctx);
666 fimc_hw_set_target_format(ctx);
667 fimc_hw_set_rotation(ctx);
668 fimc_hw_set_effect(ctx);
669 }
670
671 fimc_hw_set_output_path(ctx);
672 if (ctx->state & (FIMC_DST_ADDR | FIMC_PARAMS))
673 fimc_hw_set_output_addr(fimc, &ctx->d_frame.paddr, -1);
674
675 if (ctx->state & FIMC_PARAMS)
676 fimc_hw_set_out_dma(ctx);
677
678 fimc_activate_capture(ctx);
679
680 ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
681 FIMC_SRC_FMT | FIMC_DST_FMT);
682 fimc_hw_activate_input_dma(fimc, true);
683 spin_unlock(&fimc->slock);
684
685dma_unlock:
686 spin_unlock_irqrestore(&ctx->slock, flags);
687}
688
689static void fimc_job_abort(void *priv)
690{
691 fimc_m2m_shutdown(priv);
692}
693
694static int fimc_queue_setup(struct vb2_queue *vq, unsigned int *num_buffers,
695 unsigned int *num_planes, unsigned long sizes[],
696 void *allocators[])
697{
698 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
699 struct fimc_frame *f;
700 int i;
701
702 f = ctx_get_frame(ctx, vq->type);
703 if (IS_ERR(f))
704 return PTR_ERR(f);
705 /*
706 * Return number of non-contigous planes (plane buffers)
707 * depending on the configured color format.
708 */
709 if (!f->fmt)
710 return -EINVAL;
711
712 *num_planes = f->fmt->memplanes;
713 for (i = 0; i < f->fmt->memplanes; i++) {
714 sizes[i] = (f->f_width * f->f_height * f->fmt->depth[i]) / 8;
715 allocators[i] = ctx->fimc_dev->alloc_ctx;
716 }
717 return 0;
718}
719
720static int fimc_buf_prepare(struct vb2_buffer *vb)
721{
722 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
723 struct fimc_frame *frame;
724 int i;
725
726 frame = ctx_get_frame(ctx, vb->vb2_queue->type);
727 if (IS_ERR(frame))
728 return PTR_ERR(frame);
729
730 for (i = 0; i < frame->fmt->memplanes; i++)
731 vb2_set_plane_payload(vb, i, frame->payload[i]);
732
733 return 0;
734}
735
736static void fimc_buf_queue(struct vb2_buffer *vb)
737{
738 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
739
740 dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
741
742 if (ctx->m2m_ctx)
743 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
744}
745
746static void fimc_lock(struct vb2_queue *vq)
747{
748 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
749 mutex_lock(&ctx->fimc_dev->lock);
750}
751
752static void fimc_unlock(struct vb2_queue *vq)
753{
754 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
755 mutex_unlock(&ctx->fimc_dev->lock);
756}
757
758static struct vb2_ops fimc_qops = {
759 .queue_setup = fimc_queue_setup,
760 .buf_prepare = fimc_buf_prepare,
761 .buf_queue = fimc_buf_queue,
762 .wait_prepare = fimc_unlock,
763 .wait_finish = fimc_lock,
764 .stop_streaming = stop_streaming,
765};
766
767static int fimc_m2m_querycap(struct file *file, void *priv,
768 struct v4l2_capability *cap)
769{
770 struct fimc_ctx *ctx = file->private_data;
771 struct fimc_dev *fimc = ctx->fimc_dev;
772
773 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
774 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
775 cap->bus_info[0] = 0;
776 cap->capabilities = V4L2_CAP_STREAMING |
777 V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT |
778 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
779
780 return 0;
781}
782
783int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
784 struct v4l2_fmtdesc *f)
785{
786 struct fimc_fmt *fmt;
787
788 if (f->index >= ARRAY_SIZE(fimc_formats))
789 return -EINVAL;
790
791 fmt = &fimc_formats[f->index];
792 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
793 f->pixelformat = fmt->fourcc;
794
795 return 0;
796}
797
798int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
799 struct v4l2_format *f)
800{
801 struct fimc_ctx *ctx = priv;
802 struct fimc_frame *frame;
803 struct v4l2_pix_format_mplane *pixm;
804 int i;
805
806 frame = ctx_get_frame(ctx, f->type);
807 if (IS_ERR(frame))
808 return PTR_ERR(frame);
809
810 pixm = &f->fmt.pix_mp;
811
812 pixm->width = frame->width;
813 pixm->height = frame->height;
814 pixm->field = V4L2_FIELD_NONE;
815 pixm->pixelformat = frame->fmt->fourcc;
816 pixm->colorspace = V4L2_COLORSPACE_JPEG;
817 pixm->num_planes = frame->fmt->memplanes;
818
819 for (i = 0; i < pixm->num_planes; ++i) {
820 int bpl = frame->o_width;
821
822 if (frame->fmt->colplanes == 1) /* packed formats */
823 bpl = (bpl * frame->fmt->depth[0]) / 8;
824
825 pixm->plane_fmt[i].bytesperline = bpl;
826
827 pixm->plane_fmt[i].sizeimage = (frame->o_width *
828 frame->o_height * frame->fmt->depth[i]) / 8;
829 }
830
831 return 0;
832}
833
834struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask)
835{
836 struct fimc_fmt *fmt;
837 unsigned int i;
838
839 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
840 fmt = &fimc_formats[i];
841 if (fmt->fourcc == f->fmt.pix_mp.pixelformat &&
842 (fmt->flags & mask))
843 break;
844 }
845
846 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
847}
848
849struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
850 unsigned int mask)
851{
852 struct fimc_fmt *fmt;
853 unsigned int i;
854
855 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
856 fmt = &fimc_formats[i];
857 if (fmt->mbus_code == f->code && (fmt->flags & mask))
858 break;
859 }
860
861 return (i == ARRAY_SIZE(fimc_formats)) ? NULL : fmt;
862}
863
864
865int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
866 struct v4l2_format *f)
867{
868 struct fimc_ctx *ctx = priv;
869 struct fimc_dev *fimc = ctx->fimc_dev;
870 struct samsung_fimc_variant *variant = fimc->variant;
871 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
872 struct fimc_fmt *fmt;
873 u32 max_width, mod_x, mod_y, mask;
874 int i, is_output = 0;
875
876
877 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
878 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx))
879 return -EINVAL;
880 is_output = 1;
881 } else if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
882 return -EINVAL;
883 }
884
885 dbg("w: %d, h: %d", pix->width, pix->height);
886
887 mask = is_output ? FMT_FLAGS_M2M : FMT_FLAGS_M2M | FMT_FLAGS_CAM;
888 fmt = find_format(f, mask);
889 if (!fmt) {
890 v4l2_err(&fimc->m2m.v4l2_dev, "Fourcc format (0x%X) invalid.\n",
891 pix->pixelformat);
892 return -EINVAL;
893 }
894
895 if (pix->field == V4L2_FIELD_ANY)
896 pix->field = V4L2_FIELD_NONE;
897 else if (V4L2_FIELD_NONE != pix->field)
898 return -EINVAL;
899
900 if (is_output) {
901 max_width = variant->pix_limit->scaler_dis_w;
902 mod_x = ffs(variant->min_inp_pixsize) - 1;
903 } else {
904 max_width = variant->pix_limit->out_rot_dis_w;
905 mod_x = ffs(variant->min_out_pixsize) - 1;
906 }
907
908 if (tiled_fmt(fmt)) {
909 mod_x = 6; /* 64 x 32 pixels tile */
910 mod_y = 5;
911 } else {
912 if (fimc->id == 1 && variant->pix_hoff)
913 mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
914 else
915 mod_y = mod_x;
916 }
917
918 dbg("mod_x: %d, mod_y: %d, max_w: %d", mod_x, mod_y, max_width);
919
920 v4l_bound_align_image(&pix->width, 16, max_width, mod_x,
921 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
922
923 pix->num_planes = fmt->memplanes;
924 pix->colorspace = V4L2_COLORSPACE_JPEG;
925
926
927 for (i = 0; i < pix->num_planes; ++i) {
928 u32 bpl = pix->plane_fmt[i].bytesperline;
929 u32 *sizeimage = &pix->plane_fmt[i].sizeimage;
930
931 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
932 bpl = pix->width; /* Planar */
933
934 if (fmt->colplanes == 1 && /* Packed */
935 (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
936 bpl = (pix->width * fmt->depth[0]) / 8;
937
938 if (i == 0) /* Same bytesperline for each plane. */
939 mod_x = bpl;
940
941 pix->plane_fmt[i].bytesperline = mod_x;
942 *sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8;
943 }
944
945 return 0;
946}
947
948static int fimc_m2m_s_fmt_mplane(struct file *file, void *priv,
949 struct v4l2_format *f)
950{
951 struct fimc_ctx *ctx = priv;
952 struct fimc_dev *fimc = ctx->fimc_dev;
953 struct vb2_queue *vq;
954 struct fimc_frame *frame;
955 struct v4l2_pix_format_mplane *pix;
956 int i, ret = 0;
957
958 ret = fimc_vidioc_try_fmt_mplane(file, priv, f);
959 if (ret)
960 return ret;
961
962 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
963
964 if (vb2_is_busy(vq)) {
965 v4l2_err(&fimc->m2m.v4l2_dev, "queue (%d) busy\n", f->type);
966 return -EBUSY;
967 }
968
969 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
970 frame = &ctx->s_frame;
971 } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) {
972 frame = &ctx->d_frame;
973 } else {
974 v4l2_err(&fimc->m2m.v4l2_dev,
975 "Wrong buffer/video queue type (%d)\n", f->type);
976 return -EINVAL;
977 }
978
979 pix = &f->fmt.pix_mp;
980 frame->fmt = find_format(f, FMT_FLAGS_M2M);
981 if (!frame->fmt)
982 return -EINVAL;
983
984 for (i = 0; i < frame->fmt->colplanes; i++) {
985 frame->payload[i] =
986 (pix->width * pix->height * frame->fmt->depth[i]) / 8;
987 }
988
989 frame->f_width = pix->plane_fmt[0].bytesperline * 8 /
990 frame->fmt->depth[0];
991 frame->f_height = pix->height;
992 frame->width = pix->width;
993 frame->height = pix->height;
994 frame->o_width = pix->width;
995 frame->o_height = pix->height;
996 frame->offs_h = 0;
997 frame->offs_v = 0;
998
999 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1000 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
1001 else
1002 fimc_ctx_state_lock_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
1003
1004 dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
1005
1006 return 0;
1007}
1008
1009static int fimc_m2m_reqbufs(struct file *file, void *priv,
1010 struct v4l2_requestbuffers *reqbufs)
1011{
1012 struct fimc_ctx *ctx = priv;
1013 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1014}
1015
1016static int fimc_m2m_querybuf(struct file *file, void *priv,
1017 struct v4l2_buffer *buf)
1018{
1019 struct fimc_ctx *ctx = priv;
1020 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1021}
1022
1023static int fimc_m2m_qbuf(struct file *file, void *priv,
1024 struct v4l2_buffer *buf)
1025{
1026 struct fimc_ctx *ctx = priv;
1027
1028 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1029}
1030
1031static int fimc_m2m_dqbuf(struct file *file, void *priv,
1032 struct v4l2_buffer *buf)
1033{
1034 struct fimc_ctx *ctx = priv;
1035 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1036}
1037
1038static int fimc_m2m_streamon(struct file *file, void *priv,
1039 enum v4l2_buf_type type)
1040{
1041 struct fimc_ctx *ctx = priv;
1042
1043 /* The source and target color format need to be set */
1044 if (V4L2_TYPE_IS_OUTPUT(type)) {
1045 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT, ctx))
1046 return -EINVAL;
1047 } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT, ctx)) {
1048 return -EINVAL;
1049 }
1050
1051 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1052}
1053
1054static int fimc_m2m_streamoff(struct file *file, void *priv,
1055 enum v4l2_buf_type type)
1056{
1057 struct fimc_ctx *ctx = priv;
1058 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1059}
1060
1061int fimc_vidioc_queryctrl(struct file *file, void *priv,
1062 struct v4l2_queryctrl *qc)
1063{
1064 struct fimc_ctx *ctx = priv;
1065 struct v4l2_queryctrl *c;
1066 int ret = -EINVAL;
1067
1068 c = get_ctrl(qc->id);
1069 if (c) {
1070 *qc = *c;
1071 return 0;
1072 }
1073
1074 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx)) {
1075 return v4l2_subdev_call(ctx->fimc_dev->vid_cap.sd,
1076 core, queryctrl, qc);
1077 }
1078 return ret;
1079}
1080
1081int fimc_vidioc_g_ctrl(struct file *file, void *priv,
1082 struct v4l2_control *ctrl)
1083{
1084 struct fimc_ctx *ctx = priv;
1085 struct fimc_dev *fimc = ctx->fimc_dev;
1086
1087 switch (ctrl->id) {
1088 case V4L2_CID_HFLIP:
1089 ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
1090 break;
1091 case V4L2_CID_VFLIP:
1092 ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
1093 break;
1094 case V4L2_CID_ROTATE:
1095 ctrl->value = ctx->rotation;
1096 break;
1097 default:
1098 if (fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx)) {
1099 return v4l2_subdev_call(fimc->vid_cap.sd, core,
1100 g_ctrl, ctrl);
1101 } else {
1102 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
1103 return -EINVAL;
1104 }
1105 }
1106 dbg("ctrl->value= %d", ctrl->value);
1107
1108 return 0;
1109}
1110
1111int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1112{
1113 struct v4l2_queryctrl *c;
1114 c = get_ctrl(ctrl->id);
1115 if (!c)
1116 return -EINVAL;
1117
1118 if (ctrl->value < c->minimum || ctrl->value > c->maximum
1119 || (c->step != 0 && ctrl->value % c->step != 0)) {
1120 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
1121 "Invalid control value\n");
1122 return -ERANGE;
1123 }
1124
1125 return 0;
1126}
1127
1128int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl)
1129{
1130 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
1131 struct fimc_dev *fimc = ctx->fimc_dev;
1132 int ret = 0;
1133
1134 switch (ctrl->id) {
1135 case V4L2_CID_HFLIP:
1136 if (ctrl->value)
1137 ctx->flip |= FLIP_X_AXIS;
1138 else
1139 ctx->flip &= ~FLIP_X_AXIS;
1140 break;
1141
1142 case V4L2_CID_VFLIP:
1143 if (ctrl->value)
1144 ctx->flip |= FLIP_Y_AXIS;
1145 else
1146 ctx->flip &= ~FLIP_Y_AXIS;
1147 break;
1148
1149 case V4L2_CID_ROTATE:
1150 if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1151 ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1152 ctx->s_frame.height, ctx->d_frame.width,
1153 ctx->d_frame.height, ctrl->value);
1154 }
1155
1156 if (ret) {
1157 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range\n");
1158 return -EINVAL;
1159 }
1160
1161 /* Check for the output rotator availability */
1162 if ((ctrl->value == 90 || ctrl->value == 270) &&
1163 (ctx->in_path == FIMC_DMA && !variant->has_out_rot))
1164 return -EINVAL;
1165 ctx->rotation = ctrl->value;
1166 break;
1167
1168 default:
1169 v4l2_err(&fimc->m2m.v4l2_dev, "Invalid control\n");
1170 return -EINVAL;
1171 }
1172
1173 fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1174
1175 return 0;
1176}
1177
1178static int fimc_m2m_s_ctrl(struct file *file, void *priv,
1179 struct v4l2_control *ctrl)
1180{
1181 struct fimc_ctx *ctx = priv;
1182 int ret = 0;
1183
1184 ret = check_ctrl_val(ctx, ctrl);
1185 if (ret)
1186 return ret;
1187
1188 ret = fimc_s_ctrl(ctx, ctrl);
1189 return 0;
1190}
1191
1192static int fimc_m2m_cropcap(struct file *file, void *fh,
1193 struct v4l2_cropcap *cr)
1194{
1195 struct fimc_frame *frame;
1196 struct fimc_ctx *ctx = fh;
1197
1198 frame = ctx_get_frame(ctx, cr->type);
1199 if (IS_ERR(frame))
1200 return PTR_ERR(frame);
1201
1202 cr->bounds.left = 0;
1203 cr->bounds.top = 0;
1204 cr->bounds.width = frame->f_width;
1205 cr->bounds.height = frame->f_height;
1206 cr->defrect = cr->bounds;
1207
1208 return 0;
1209}
1210
1211static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1212{
1213 struct fimc_frame *frame;
1214 struct fimc_ctx *ctx = file->private_data;
1215
1216 frame = ctx_get_frame(ctx, cr->type);
1217 if (IS_ERR(frame))
1218 return PTR_ERR(frame);
1219
1220 cr->c.left = frame->offs_h;
1221 cr->c.top = frame->offs_v;
1222 cr->c.width = frame->width;
1223 cr->c.height = frame->height;
1224
1225 return 0;
1226}
1227
1228int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1229{
1230 struct fimc_dev *fimc = ctx->fimc_dev;
1231 struct fimc_frame *f;
1232 u32 min_size, halign, depth = 0;
1233 bool is_capture_ctx;
1234 int i;
1235
1236 if (cr->c.top < 0 || cr->c.left < 0) {
1237 v4l2_err(&fimc->m2m.v4l2_dev,
1238 "doesn't support negative values for top & left\n");
1239 return -EINVAL;
1240 }
1241
1242 is_capture_ctx = fimc_ctx_state_is_set(FIMC_CTX_CAP, ctx);
1243
1244 if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1245 f = is_capture_ctx ? &ctx->s_frame : &ctx->d_frame;
1246 else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE &&
1247 !is_capture_ctx)
1248 f = &ctx->s_frame;
1249 else
1250 return -EINVAL;
1251
1252 min_size = (f == &ctx->s_frame) ?
1253 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1254
1255 /* Get pixel alignment constraints. */
1256 if (is_capture_ctx) {
1257 min_size = 16;
1258 halign = 4;
1259 } else {
1260 if (fimc->id == 1 && fimc->variant->pix_hoff)
1261 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1262 else
1263 halign = ffs(min_size) - 1;
1264 }
1265
1266 for (i = 0; i < f->fmt->colplanes; i++)
1267 depth += f->fmt->depth[i];
1268
1269 v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1270 ffs(min_size) - 1,
1271 &cr->c.height, min_size, f->o_height,
1272 halign, 64/(ALIGN(depth, 8)));
1273
1274 /* adjust left/top if cropping rectangle is out of bounds */
1275 if (cr->c.left + cr->c.width > f->o_width)
1276 cr->c.left = f->o_width - cr->c.width;
1277 if (cr->c.top + cr->c.height > f->o_height)
1278 cr->c.top = f->o_height - cr->c.height;
1279
1280 cr->c.left = round_down(cr->c.left, min_size);
1281 cr->c.top = round_down(cr->c.top, is_capture_ctx ? 16 : 8);
1282
1283 dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1284 cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1285 f->f_width, f->f_height);
1286
1287 return 0;
1288}
1289
1290static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1291{
1292 struct fimc_ctx *ctx = file->private_data;
1293 struct fimc_dev *fimc = ctx->fimc_dev;
1294 struct fimc_frame *f;
1295 int ret;
1296
1297 ret = fimc_try_crop(ctx, cr);
1298 if (ret)
1299 return ret;
1300
1301 f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1302 &ctx->s_frame : &ctx->d_frame;
1303
1304 /* Check to see if scaling ratio is within supported range */
1305 if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1306 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1307 ret = fimc_check_scaler_ratio(cr->c.width, cr->c.height,
1308 ctx->d_frame.width,
1309 ctx->d_frame.height,
1310 ctx->rotation);
1311 } else {
1312 ret = fimc_check_scaler_ratio(ctx->s_frame.width,
1313 ctx->s_frame.height,
1314 cr->c.width, cr->c.height,
1315 ctx->rotation);
1316 }
1317 if (ret) {
1318 v4l2_err(&fimc->m2m.v4l2_dev, "Out of scaler range\n");
1319 return -EINVAL;
1320 }
1321 }
1322
1323 f->offs_h = cr->c.left;
1324 f->offs_v = cr->c.top;
1325 f->width = cr->c.width;
1326 f->height = cr->c.height;
1327
1328 fimc_ctx_state_lock_set(FIMC_PARAMS, ctx);
1329
1330 return 0;
1331}
1332
1333static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1334 .vidioc_querycap = fimc_m2m_querycap,
1335
1336 .vidioc_enum_fmt_vid_cap_mplane = fimc_vidioc_enum_fmt_mplane,
1337 .vidioc_enum_fmt_vid_out_mplane = fimc_vidioc_enum_fmt_mplane,
1338
1339 .vidioc_g_fmt_vid_cap_mplane = fimc_vidioc_g_fmt_mplane,
1340 .vidioc_g_fmt_vid_out_mplane = fimc_vidioc_g_fmt_mplane,
1341
1342 .vidioc_try_fmt_vid_cap_mplane = fimc_vidioc_try_fmt_mplane,
1343 .vidioc_try_fmt_vid_out_mplane = fimc_vidioc_try_fmt_mplane,
1344
1345 .vidioc_s_fmt_vid_cap_mplane = fimc_m2m_s_fmt_mplane,
1346 .vidioc_s_fmt_vid_out_mplane = fimc_m2m_s_fmt_mplane,
1347
1348 .vidioc_reqbufs = fimc_m2m_reqbufs,
1349 .vidioc_querybuf = fimc_m2m_querybuf,
1350
1351 .vidioc_qbuf = fimc_m2m_qbuf,
1352 .vidioc_dqbuf = fimc_m2m_dqbuf,
1353
1354 .vidioc_streamon = fimc_m2m_streamon,
1355 .vidioc_streamoff = fimc_m2m_streamoff,
1356
1357 .vidioc_queryctrl = fimc_vidioc_queryctrl,
1358 .vidioc_g_ctrl = fimc_vidioc_g_ctrl,
1359 .vidioc_s_ctrl = fimc_m2m_s_ctrl,
1360
1361 .vidioc_g_crop = fimc_m2m_g_crop,
1362 .vidioc_s_crop = fimc_m2m_s_crop,
1363 .vidioc_cropcap = fimc_m2m_cropcap
1364
1365};
1366
1367static int queue_init(void *priv, struct vb2_queue *src_vq,
1368 struct vb2_queue *dst_vq)
1369{
1370 struct fimc_ctx *ctx = priv;
1371 int ret;
1372
1373 memset(src_vq, 0, sizeof(*src_vq));
1374 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1375 src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1376 src_vq->drv_priv = ctx;
1377 src_vq->ops = &fimc_qops;
1378 src_vq->mem_ops = &vb2_dma_contig_memops;
1379 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1380
1381 ret = vb2_queue_init(src_vq);
1382 if (ret)
1383 return ret;
1384
1385 memset(dst_vq, 0, sizeof(*dst_vq));
1386 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1387 dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1388 dst_vq->drv_priv = ctx;
1389 dst_vq->ops = &fimc_qops;
1390 dst_vq->mem_ops = &vb2_dma_contig_memops;
1391 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1392
1393 return vb2_queue_init(dst_vq);
1394}
1395
1396static int fimc_m2m_open(struct file *file)
1397{
1398 struct fimc_dev *fimc = video_drvdata(file);
1399 struct fimc_ctx *ctx = NULL;
1400
1401 dbg("pid: %d, state: 0x%lx, refcnt: %d",
1402 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1403
1404 /*
1405 * Return if the corresponding video capture node
1406 * is already opened.
1407 */
1408 if (fimc->vid_cap.refcnt > 0)
1409 return -EBUSY;
1410
1411 fimc->m2m.refcnt++;
1412 set_bit(ST_OUTDMA_RUN, &fimc->state);
1413
1414 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1415 if (!ctx)
1416 return -ENOMEM;
1417
1418 file->private_data = ctx;
1419 ctx->fimc_dev = fimc;
1420 /* Default color format */
1421 ctx->s_frame.fmt = &fimc_formats[0];
1422 ctx->d_frame.fmt = &fimc_formats[0];
1423 /* Setup the device context for mem2mem mode. */
1424 ctx->state = FIMC_CTX_M2M;
1425 ctx->flags = 0;
1426 ctx->in_path = FIMC_DMA;
1427 ctx->out_path = FIMC_DMA;
1428 spin_lock_init(&ctx->slock);
1429
1430 ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1431 if (IS_ERR(ctx->m2m_ctx)) {
1432 int err = PTR_ERR(ctx->m2m_ctx);
1433 kfree(ctx);
1434 return err;
1435 }
1436
1437 return 0;
1438}
1439
1440static int fimc_m2m_release(struct file *file)
1441{
1442 struct fimc_ctx *ctx = file->private_data;
1443 struct fimc_dev *fimc = ctx->fimc_dev;
1444
1445 dbg("pid: %d, state: 0x%lx, refcnt= %d",
1446 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1447
1448 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1449 kfree(ctx);
1450 if (--fimc->m2m.refcnt <= 0)
1451 clear_bit(ST_OUTDMA_RUN, &fimc->state);
1452
1453 return 0;
1454}
1455
1456static unsigned int fimc_m2m_poll(struct file *file,
1457 struct poll_table_struct *wait)
1458{
1459 struct fimc_ctx *ctx = file->private_data;
1460
1461 return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1462}
1463
1464
1465static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1466{
1467 struct fimc_ctx *ctx = file->private_data;
1468
1469 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1470}
1471
1472static const struct v4l2_file_operations fimc_m2m_fops = {
1473 .owner = THIS_MODULE,
1474 .open = fimc_m2m_open,
1475 .release = fimc_m2m_release,
1476 .poll = fimc_m2m_poll,
1477 .unlocked_ioctl = video_ioctl2,
1478 .mmap = fimc_m2m_mmap,
1479};
1480
1481static struct v4l2_m2m_ops m2m_ops = {
1482 .device_run = fimc_dma_run,
1483 .job_abort = fimc_job_abort,
1484};
1485
1486static int fimc_register_m2m_device(struct fimc_dev *fimc)
1487{
1488 struct video_device *vfd;
1489 struct platform_device *pdev;
1490 struct v4l2_device *v4l2_dev;
1491 int ret = 0;
1492
1493 if (!fimc)
1494 return -ENODEV;
1495
1496 pdev = fimc->pdev;
1497 v4l2_dev = &fimc->m2m.v4l2_dev;
1498
1499 /* set name if it is empty */
1500 if (!v4l2_dev->name[0])
1501 snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
1502 "%s.m2m", dev_name(&pdev->dev));
1503
1504 ret = v4l2_device_register(&pdev->dev, v4l2_dev);
1505 if (ret)
1506 goto err_m2m_r1;
1507
1508 vfd = video_device_alloc();
1509 if (!vfd) {
1510 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1511 goto err_m2m_r1;
1512 }
1513
1514 vfd->fops = &fimc_m2m_fops;
1515 vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
1516 vfd->minor = -1;
1517 vfd->release = video_device_release;
1518 vfd->lock = &fimc->lock;
1519
1520 snprintf(vfd->name, sizeof(vfd->name), "%s:m2m", dev_name(&pdev->dev));
1521
1522 video_set_drvdata(vfd, fimc);
1523 platform_set_drvdata(pdev, fimc);
1524
1525 fimc->m2m.vfd = vfd;
1526 fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1527 if (IS_ERR(fimc->m2m.m2m_dev)) {
1528 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1529 ret = PTR_ERR(fimc->m2m.m2m_dev);
1530 goto err_m2m_r2;
1531 }
1532
1533 ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
1534 if (ret) {
1535 v4l2_err(v4l2_dev,
1536 "%s(): failed to register video device\n", __func__);
1537 goto err_m2m_r3;
1538 }
1539 v4l2_info(v4l2_dev,
1540 "FIMC m2m driver registered as /dev/video%d\n", vfd->num);
1541
1542 return 0;
1543
1544err_m2m_r3:
1545 v4l2_m2m_release(fimc->m2m.m2m_dev);
1546err_m2m_r2:
1547 video_device_release(fimc->m2m.vfd);
1548err_m2m_r1:
1549 v4l2_device_unregister(v4l2_dev);
1550
1551 return ret;
1552}
1553
1554static void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1555{
1556 if (fimc) {
1557 v4l2_m2m_release(fimc->m2m.m2m_dev);
1558 video_unregister_device(fimc->m2m.vfd);
1559
1560 v4l2_device_unregister(&fimc->m2m.v4l2_dev);
1561 }
1562}
1563
1564static void fimc_clk_release(struct fimc_dev *fimc)
1565{
1566 int i;
1567 for (i = 0; i < fimc->num_clocks; i++) {
1568 if (fimc->clock[i]) {
1569 clk_disable(fimc->clock[i]);
1570 clk_put(fimc->clock[i]);
1571 }
1572 }
1573}
1574
1575static int fimc_clk_get(struct fimc_dev *fimc)
1576{
1577 int i;
1578 for (i = 0; i < fimc->num_clocks; i++) {
1579 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1580
1581 if (!IS_ERR_OR_NULL(fimc->clock[i])) {
1582 clk_enable(fimc->clock[i]);
1583 continue;
1584 }
1585 dev_err(&fimc->pdev->dev, "failed to get fimc clock: %s\n",
1586 fimc_clocks[i]);
1587 return -ENXIO;
1588 }
1589 return 0;
1590}
1591
1592static int fimc_probe(struct platform_device *pdev)
1593{
1594 struct fimc_dev *fimc;
1595 struct resource *res;
1596 struct samsung_fimc_driverdata *drv_data;
1597 struct s5p_platform_fimc *pdata;
1598 int ret = 0;
1599 int cap_input_index = -1;
1600
1601 dev_dbg(&pdev->dev, "%s():\n", __func__);
1602
1603 drv_data = (struct samsung_fimc_driverdata *)
1604 platform_get_device_id(pdev)->driver_data;
1605
1606 if (pdev->id >= drv_data->num_entities) {
1607 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1608 pdev->id);
1609 return -EINVAL;
1610 }
1611
1612 fimc = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
1613 if (!fimc)
1614 return -ENOMEM;
1615
1616 fimc->id = pdev->id;
1617 fimc->variant = drv_data->variant[fimc->id];
1618 fimc->pdev = pdev;
1619 pdata = pdev->dev.platform_data;
1620 fimc->pdata = pdata;
1621 fimc->state = ST_IDLE;
1622
1623 init_waitqueue_head(&fimc->irq_queue);
1624 spin_lock_init(&fimc->slock);
1625
1626 mutex_init(&fimc->lock);
1627
1628 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1629 if (!res) {
1630 dev_err(&pdev->dev, "failed to find the registers\n");
1631 ret = -ENOENT;
1632 goto err_info;
1633 }
1634
1635 fimc->regs_res = request_mem_region(res->start, resource_size(res),
1636 dev_name(&pdev->dev));
1637 if (!fimc->regs_res) {
1638 dev_err(&pdev->dev, "failed to obtain register region\n");
1639 ret = -ENOENT;
1640 goto err_info;
1641 }
1642
1643 fimc->regs = ioremap(res->start, resource_size(res));
1644 if (!fimc->regs) {
1645 dev_err(&pdev->dev, "failed to map registers\n");
1646 ret = -ENXIO;
1647 goto err_req_region;
1648 }
1649
1650 fimc->num_clocks = MAX_FIMC_CLOCKS - 1;
1651
1652 /* Check if a video capture node needs to be registered. */
1653 if (pdata && pdata->num_clients > 0) {
1654 cap_input_index = 0;
1655 fimc->num_clocks++;
1656 }
1657
1658 ret = fimc_clk_get(fimc);
1659 if (ret)
1660 goto err_regs_unmap;
1661 clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1662
1663 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1664 if (!res) {
1665 dev_err(&pdev->dev, "failed to get IRQ resource\n");
1666 ret = -ENXIO;
1667 goto err_clk;
1668 }
1669 fimc->irq = res->start;
1670
1671 fimc_hw_reset(fimc);
1672
1673 ret = request_irq(fimc->irq, fimc_isr, 0, pdev->name, fimc);
1674 if (ret) {
1675 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1676 goto err_clk;
1677 }
1678
1679 /* Initialize contiguous memory allocator */
1680 fimc->alloc_ctx = vb2_dma_contig_init_ctx(&fimc->pdev->dev);
1681 if (IS_ERR(fimc->alloc_ctx)) {
1682 ret = PTR_ERR(fimc->alloc_ctx);
1683 goto err_irq;
1684 }
1685
1686 ret = fimc_register_m2m_device(fimc);
1687 if (ret)
1688 goto err_irq;
1689
1690 /* At least one camera sensor is required to register capture node */
1691 if (cap_input_index >= 0) {
1692 ret = fimc_register_capture_device(fimc);
1693 if (ret)
1694 goto err_m2m;
1695 clk_disable(fimc->clock[CLK_CAM]);
1696 }
1697 /*
1698 * Exclude the additional output DMA address registers by masking
1699 * them out on HW revisions that provide extended capabilites.
1700 */
1701 if (fimc->variant->out_buf_count > 4)
1702 fimc_hw_set_dma_seq(fimc, 0xF);
1703
1704 dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
1705 __func__, fimc->id);
1706
1707 return 0;
1708
1709err_m2m:
1710 fimc_unregister_m2m_device(fimc);
1711err_irq:
1712 free_irq(fimc->irq, fimc);
1713err_clk:
1714 fimc_clk_release(fimc);
1715err_regs_unmap:
1716 iounmap(fimc->regs);
1717err_req_region:
1718 release_resource(fimc->regs_res);
1719 kfree(fimc->regs_res);
1720err_info:
1721 kfree(fimc);
1722
1723 return ret;
1724}
1725
1726static int __devexit fimc_remove(struct platform_device *pdev)
1727{
1728 struct fimc_dev *fimc =
1729 (struct fimc_dev *)platform_get_drvdata(pdev);
1730
1731 free_irq(fimc->irq, fimc);
1732 fimc_hw_reset(fimc);
1733
1734 fimc_unregister_m2m_device(fimc);
1735 fimc_unregister_capture_device(fimc);
1736
1737 fimc_clk_release(fimc);
1738
1739 vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1740
1741 iounmap(fimc->regs);
1742 release_resource(fimc->regs_res);
1743 kfree(fimc->regs_res);
1744 kfree(fimc);
1745
1746 dev_info(&pdev->dev, "%s driver unloaded\n", pdev->name);
1747 return 0;
1748}
1749
1750/* Image pixel limits, similar across several FIMC HW revisions. */
1751static struct fimc_pix_limit s5p_pix_limit[4] = {
1752 [0] = {
1753 .scaler_en_w = 3264,
1754 .scaler_dis_w = 8192,
1755 .in_rot_en_h = 1920,
1756 .in_rot_dis_w = 8192,
1757 .out_rot_en_w = 1920,
1758 .out_rot_dis_w = 4224,
1759 },
1760 [1] = {
1761 .scaler_en_w = 4224,
1762 .scaler_dis_w = 8192,
1763 .in_rot_en_h = 1920,
1764 .in_rot_dis_w = 8192,
1765 .out_rot_en_w = 1920,
1766 .out_rot_dis_w = 4224,
1767 },
1768 [2] = {
1769 .scaler_en_w = 1920,
1770 .scaler_dis_w = 8192,
1771 .in_rot_en_h = 1280,
1772 .in_rot_dis_w = 8192,
1773 .out_rot_en_w = 1280,
1774 .out_rot_dis_w = 1920,
1775 },
1776 [3] = {
1777 .scaler_en_w = 1920,
1778 .scaler_dis_w = 8192,
1779 .in_rot_en_h = 1366,
1780 .in_rot_dis_w = 8192,
1781 .out_rot_en_w = 1366,
1782 .out_rot_dis_w = 1920,
1783 },
1784};
1785
1786static struct samsung_fimc_variant fimc0_variant_s5p = {
1787 .has_inp_rot = 1,
1788 .has_out_rot = 1,
1789 .min_inp_pixsize = 16,
1790 .min_out_pixsize = 16,
1791 .hor_offs_align = 8,
1792 .out_buf_count = 4,
1793 .pix_limit = &s5p_pix_limit[0],
1794};
1795
1796static struct samsung_fimc_variant fimc2_variant_s5p = {
1797 .min_inp_pixsize = 16,
1798 .min_out_pixsize = 16,
1799 .hor_offs_align = 8,
1800 .out_buf_count = 4,
1801 .pix_limit = &s5p_pix_limit[1],
1802};
1803
1804static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1805 .pix_hoff = 1,
1806 .has_inp_rot = 1,
1807 .has_out_rot = 1,
1808 .min_inp_pixsize = 16,
1809 .min_out_pixsize = 16,
1810 .hor_offs_align = 8,
1811 .out_buf_count = 4,
1812 .pix_limit = &s5p_pix_limit[1],
1813};
1814
1815static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1816 .pix_hoff = 1,
1817 .has_inp_rot = 1,
1818 .has_out_rot = 1,
1819 .has_mainscaler_ext = 1,
1820 .min_inp_pixsize = 16,
1821 .min_out_pixsize = 16,
1822 .hor_offs_align = 1,
1823 .out_buf_count = 4,
1824 .pix_limit = &s5p_pix_limit[2],
1825};
1826
1827static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1828 .pix_hoff = 1,
1829 .min_inp_pixsize = 16,
1830 .min_out_pixsize = 16,
1831 .hor_offs_align = 8,
1832 .out_buf_count = 4,
1833 .pix_limit = &s5p_pix_limit[2],
1834};
1835
1836static struct samsung_fimc_variant fimc0_variant_exynos4 = {
1837 .pix_hoff = 1,
1838 .has_inp_rot = 1,
1839 .has_out_rot = 1,
1840 .has_cistatus2 = 1,
1841 .has_mainscaler_ext = 1,
1842 .min_inp_pixsize = 16,
1843 .min_out_pixsize = 16,
1844 .hor_offs_align = 1,
1845 .out_buf_count = 32,
1846 .pix_limit = &s5p_pix_limit[1],
1847};
1848
1849static struct samsung_fimc_variant fimc2_variant_exynos4 = {
1850 .pix_hoff = 1,
1851 .has_cistatus2 = 1,
1852 .has_mainscaler_ext = 1,
1853 .min_inp_pixsize = 16,
1854 .min_out_pixsize = 16,
1855 .hor_offs_align = 1,
1856 .out_buf_count = 32,
1857 .pix_limit = &s5p_pix_limit[3],
1858};
1859
1860/* S5PC100 */
1861static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1862 .variant = {
1863 [0] = &fimc0_variant_s5p,
1864 [1] = &fimc0_variant_s5p,
1865 [2] = &fimc2_variant_s5p,
1866 },
1867 .num_entities = 3,
1868 .lclk_frequency = 133000000UL,
1869};
1870
1871/* S5PV210, S5PC110 */
1872static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1873 .variant = {
1874 [0] = &fimc0_variant_s5pv210,
1875 [1] = &fimc1_variant_s5pv210,
1876 [2] = &fimc2_variant_s5pv210,
1877 },
1878 .num_entities = 3,
1879 .lclk_frequency = 166000000UL,
1880};
1881
1882/* S5PV310, S5PC210 */
1883static struct samsung_fimc_driverdata fimc_drvdata_exynos4 = {
1884 .variant = {
1885 [0] = &fimc0_variant_exynos4,
1886 [1] = &fimc0_variant_exynos4,
1887 [2] = &fimc0_variant_exynos4,
1888 [3] = &fimc2_variant_exynos4,
1889 },
1890 .num_entities = 4,
1891 .lclk_frequency = 166000000UL,
1892};
1893
1894static struct platform_device_id fimc_driver_ids[] = {
1895 {
1896 .name = "s5p-fimc",
1897 .driver_data = (unsigned long)&fimc_drvdata_s5p,
1898 }, {
1899 .name = "s5pv210-fimc",
1900 .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
1901 }, {
1902 .name = "exynos4-fimc",
1903 .driver_data = (unsigned long)&fimc_drvdata_exynos4,
1904 },
1905 {},
1906};
1907MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1908
1909static struct platform_driver fimc_driver = {
1910 .probe = fimc_probe,
1911 .remove = __devexit_p(fimc_remove),
1912 .id_table = fimc_driver_ids,
1913 .driver = {
1914 .name = MODULE_NAME,
1915 .owner = THIS_MODULE,
1916 }
1917};
1918
1919static int __init fimc_init(void)
1920{
1921 int ret = platform_driver_register(&fimc_driver);
1922 if (ret)
1923 err("platform_driver_register failed: %d\n", ret);
1924 return ret;
1925}
1926
1927static void __exit fimc_exit(void)
1928{
1929 platform_driver_unregister(&fimc_driver);
1930}
1931
1932module_init(fimc_init);
1933module_exit(fimc_exit);
1934
1935MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
1936MODULE_DESCRIPTION("S5P FIMC camera host interface/video postprocessor driver");
1937MODULE_LICENSE("GPL");
1938MODULE_VERSION("1.0.1");
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-20 21:11:58 -0400