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-rw-r--r--drivers/media/video/s5p-fimc/fimc-core.h707
1 files changed, 707 insertions, 0 deletions
diff --git a/drivers/media/video/s5p-fimc/fimc-core.h b/drivers/media/video/s5p-fimc/fimc-core.h
new file mode 100644
index 00000000000..1f70772daaf
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/fimc-core.h
@@ -0,0 +1,707 @@
1/*
2 * Copyright (C) 2010 - 2011 Samsung Electronics Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef FIMC_CORE_H_
10#define FIMC_CORE_H_
11
12/*#define DEBUG*/
13
14#include <linux/sched.h>
15#include <linux/spinlock.h>
16#include <linux/types.h>
17#include <linux/videodev2.h>
18#include <linux/io.h>
19#include <media/videobuf2-core.h>
20#include <media/v4l2-device.h>
21#include <media/v4l2-mem2mem.h>
22#include <media/v4l2-mediabus.h>
23#include <media/s5p_fimc.h>
24
25#include "regs-fimc.h"
26
27#define err(fmt, args...) \
28 printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
29
30#define dbg(fmt, args...) \
31 pr_debug("%s:%d: " fmt "\n", __func__, __LINE__, ##args)
32
33/* Time to wait for next frame VSYNC interrupt while stopping operation. */
34#define FIMC_SHUTDOWN_TIMEOUT ((100*HZ)/1000)
35#define MAX_FIMC_CLOCKS 3
36#define MODULE_NAME "s5p-fimc"
37#define FIMC_MAX_DEVS 4
38#define FIMC_MAX_OUT_BUFS 4
39#define SCALER_MAX_HRATIO 64
40#define SCALER_MAX_VRATIO 64
41#define DMA_MIN_SIZE 8
42
43/* indices to the clocks array */
44enum {
45 CLK_BUS,
46 CLK_GATE,
47 CLK_CAM,
48};
49
50enum fimc_dev_flags {
51 /* for m2m node */
52 ST_IDLE,
53 ST_OUTDMA_RUN,
54 ST_M2M_PEND,
55 /* for capture node */
56 ST_CAPT_PEND,
57 ST_CAPT_RUN,
58 ST_CAPT_STREAM,
59 ST_CAPT_SHUT,
60};
61
62#define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
63#define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
64
65#define fimc_capture_running(dev) test_bit(ST_CAPT_RUN, &(dev)->state)
66#define fimc_capture_pending(dev) test_bit(ST_CAPT_PEND, &(dev)->state)
67
68enum fimc_datapath {
69 FIMC_CAMERA,
70 FIMC_DMA,
71 FIMC_LCDFIFO,
72 FIMC_WRITEBACK
73};
74
75enum fimc_color_fmt {
76 S5P_FIMC_RGB565 = 0x10,
77 S5P_FIMC_RGB666,
78 S5P_FIMC_RGB888,
79 S5P_FIMC_RGB30_LOCAL,
80 S5P_FIMC_YCBCR420 = 0x20,
81 S5P_FIMC_YCBYCR422,
82 S5P_FIMC_YCRYCB422,
83 S5P_FIMC_CBYCRY422,
84 S5P_FIMC_CRYCBY422,
85 S5P_FIMC_YCBCR444_LOCAL,
86};
87
88#define fimc_fmt_is_rgb(x) ((x) & 0x10)
89
90/* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats. */
91#define S5P_FIMC_LSB_CRCB S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
92
93/* The embedded image effect selection */
94#define S5P_FIMC_EFFECT_ORIGINAL S5P_CIIMGEFF_FIN_BYPASS
95#define S5P_FIMC_EFFECT_ARBITRARY S5P_CIIMGEFF_FIN_ARBITRARY
96#define S5P_FIMC_EFFECT_NEGATIVE S5P_CIIMGEFF_FIN_NEGATIVE
97#define S5P_FIMC_EFFECT_ARTFREEZE S5P_CIIMGEFF_FIN_ARTFREEZE
98#define S5P_FIMC_EFFECT_EMBOSSING S5P_CIIMGEFF_FIN_EMBOSSING
99#define S5P_FIMC_EFFECT_SIKHOUETTE S5P_CIIMGEFF_FIN_SILHOUETTE
100
101/* The hardware context state. */
102#define FIMC_PARAMS (1 << 0)
103#define FIMC_SRC_ADDR (1 << 1)
104#define FIMC_DST_ADDR (1 << 2)
105#define FIMC_SRC_FMT (1 << 3)
106#define FIMC_DST_FMT (1 << 4)
107#define FIMC_CTX_M2M (1 << 5)
108#define FIMC_CTX_CAP (1 << 6)
109#define FIMC_CTX_SHUT (1 << 7)
110
111/* Image conversion flags */
112#define FIMC_IN_DMA_ACCESS_TILED (1 << 0)
113#define FIMC_IN_DMA_ACCESS_LINEAR (0 << 0)
114#define FIMC_OUT_DMA_ACCESS_TILED (1 << 1)
115#define FIMC_OUT_DMA_ACCESS_LINEAR (0 << 1)
116#define FIMC_SCAN_MODE_PROGRESSIVE (0 << 2)
117#define FIMC_SCAN_MODE_INTERLACED (1 << 2)
118/*
119 * YCbCr data dynamic range for RGB-YUV color conversion.
120 * Y/Cb/Cr: (0 ~ 255) */
121#define FIMC_COLOR_RANGE_WIDE (0 << 3)
122/* Y (16 ~ 235), Cb/Cr (16 ~ 240) */
123#define FIMC_COLOR_RANGE_NARROW (1 << 3)
124
125#define FLIP_NONE 0
126#define FLIP_X_AXIS 1
127#define FLIP_Y_AXIS 2
128#define FLIP_XY_AXIS (FLIP_X_AXIS | FLIP_Y_AXIS)
129
130/**
131 * struct fimc_fmt - the driver's internal color format data
132 * @mbus_code: Media Bus pixel code, -1 if not applicable
133 * @name: format description
134 * @fourcc: the fourcc code for this format, 0 if not applicable
135 * @color: the corresponding fimc_color_fmt
136 * @memplanes: number of physically non-contiguous data planes
137 * @colplanes: number of physically contiguous data planes
138 * @depth: per plane driver's private 'number of bits per pixel'
139 * @flags: flags indicating which operation mode format applies to
140 */
141struct fimc_fmt {
142 enum v4l2_mbus_pixelcode mbus_code;
143 char *name;
144 u32 fourcc;
145 u32 color;
146 u16 memplanes;
147 u16 colplanes;
148 u8 depth[VIDEO_MAX_PLANES];
149 u16 flags;
150#define FMT_FLAGS_CAM (1 << 0)
151#define FMT_FLAGS_M2M (1 << 1)
152};
153
154/**
155 * struct fimc_dma_offset - pixel offset information for DMA
156 * @y_h: y value horizontal offset
157 * @y_v: y value vertical offset
158 * @cb_h: cb value horizontal offset
159 * @cb_v: cb value vertical offset
160 * @cr_h: cr value horizontal offset
161 * @cr_v: cr value vertical offset
162 */
163struct fimc_dma_offset {
164 int y_h;
165 int y_v;
166 int cb_h;
167 int cb_v;
168 int cr_h;
169 int cr_v;
170};
171
172/**
173 * struct fimc_effect - color effect information
174 * @type: effect type
175 * @pat_cb: cr value when type is "arbitrary"
176 * @pat_cr: cr value when type is "arbitrary"
177 */
178struct fimc_effect {
179 u32 type;
180 u8 pat_cb;
181 u8 pat_cr;
182};
183
184/**
185 * struct fimc_scaler - the configuration data for FIMC inetrnal scaler
186 * @scaleup_h: flag indicating scaling up horizontally
187 * @scaleup_v: flag indicating scaling up vertically
188 * @copy_mode: flag indicating transparent DMA transfer (no scaling
189 * and color format conversion)
190 * @enabled: flag indicating if the scaler is used
191 * @hfactor: horizontal shift factor
192 * @vfactor: vertical shift factor
193 * @pre_hratio: horizontal ratio of the prescaler
194 * @pre_vratio: vertical ratio of the prescaler
195 * @pre_dst_width: the prescaler's destination width
196 * @pre_dst_height: the prescaler's destination height
197 * @main_hratio: the main scaler's horizontal ratio
198 * @main_vratio: the main scaler's vertical ratio
199 * @real_width: source pixel (width - offset)
200 * @real_height: source pixel (height - offset)
201 */
202struct fimc_scaler {
203 unsigned int scaleup_h:1;
204 unsigned int scaleup_v:1;
205 unsigned int copy_mode:1;
206 unsigned int enabled:1;
207 u32 hfactor;
208 u32 vfactor;
209 u32 pre_hratio;
210 u32 pre_vratio;
211 u32 pre_dst_width;
212 u32 pre_dst_height;
213 u32 main_hratio;
214 u32 main_vratio;
215 u32 real_width;
216 u32 real_height;
217};
218
219/**
220 * struct fimc_addr - the FIMC physical address set for DMA
221 * @y: luminance plane physical address
222 * @cb: Cb plane physical address
223 * @cr: Cr plane physical address
224 */
225struct fimc_addr {
226 u32 y;
227 u32 cb;
228 u32 cr;
229};
230
231/**
232 * struct fimc_vid_buffer - the driver's video buffer
233 * @vb: v4l videobuf buffer
234 * @list: linked list structure for buffer queue
235 * @paddr: precalculated physical address set
236 * @index: buffer index for the output DMA engine
237 */
238struct fimc_vid_buffer {
239 struct vb2_buffer vb;
240 struct list_head list;
241 struct fimc_addr paddr;
242 int index;
243};
244
245/**
246 * struct fimc_frame - source/target frame properties
247 * @f_width: image full width (virtual screen size)
248 * @f_height: image full height (virtual screen size)
249 * @o_width: original image width as set by S_FMT
250 * @o_height: original image height as set by S_FMT
251 * @offs_h: image horizontal pixel offset
252 * @offs_v: image vertical pixel offset
253 * @width: image pixel width
254 * @height: image pixel weight
255 * @payload: image size in bytes (w x h x bpp)
256 * @paddr: image frame buffer physical addresses
257 * @dma_offset: DMA offset in bytes
258 * @fmt: fimc color format pointer
259 */
260struct fimc_frame {
261 u32 f_width;
262 u32 f_height;
263 u32 o_width;
264 u32 o_height;
265 u32 offs_h;
266 u32 offs_v;
267 u32 width;
268 u32 height;
269 unsigned long payload[VIDEO_MAX_PLANES];
270 struct fimc_addr paddr;
271 struct fimc_dma_offset dma_offset;
272 struct fimc_fmt *fmt;
273};
274
275/**
276 * struct fimc_m2m_device - v4l2 memory-to-memory device data
277 * @vfd: the video device node for v4l2 m2m mode
278 * @v4l2_dev: v4l2 device for m2m mode
279 * @m2m_dev: v4l2 memory-to-memory device data
280 * @ctx: hardware context data
281 * @refcnt: the reference counter
282 */
283struct fimc_m2m_device {
284 struct video_device *vfd;
285 struct v4l2_device v4l2_dev;
286 struct v4l2_m2m_dev *m2m_dev;
287 struct fimc_ctx *ctx;
288 int refcnt;
289};
290
291/**
292 * struct fimc_vid_cap - camera capture device information
293 * @ctx: hardware context data
294 * @vfd: video device node for camera capture mode
295 * @v4l2_dev: v4l2_device struct to manage subdevs
296 * @sd: pointer to camera sensor subdevice currently in use
297 * @fmt: Media Bus format configured at selected image sensor
298 * @pending_buf_q: the pending buffer queue head
299 * @active_buf_q: the queue head of buffers scheduled in hardware
300 * @vbq: the capture am video buffer queue
301 * @active_buf_cnt: number of video buffers scheduled in hardware
302 * @buf_index: index for managing the output DMA buffers
303 * @frame_count: the frame counter for statistics
304 * @reqbufs_count: the number of buffers requested in REQBUFS ioctl
305 * @input_index: input (camera sensor) index
306 * @refcnt: driver's private reference counter
307 */
308struct fimc_vid_cap {
309 struct fimc_ctx *ctx;
310 struct vb2_alloc_ctx *alloc_ctx;
311 struct video_device *vfd;
312 struct v4l2_device v4l2_dev;
313 struct v4l2_subdev *sd;;
314 struct v4l2_mbus_framefmt fmt;
315 struct list_head pending_buf_q;
316 struct list_head active_buf_q;
317 struct vb2_queue vbq;
318 int active_buf_cnt;
319 int buf_index;
320 unsigned int frame_count;
321 unsigned int reqbufs_count;
322 int input_index;
323 int refcnt;
324};
325
326/**
327 * struct fimc_pix_limit - image pixel size limits in various IP configurations
328 *
329 * @scaler_en_w: max input pixel width when the scaler is enabled
330 * @scaler_dis_w: max input pixel width when the scaler is disabled
331 * @in_rot_en_h: max input width with the input rotator is on
332 * @in_rot_dis_w: max input width with the input rotator is off
333 * @out_rot_en_w: max output width with the output rotator on
334 * @out_rot_dis_w: max output width with the output rotator off
335 */
336struct fimc_pix_limit {
337 u16 scaler_en_w;
338 u16 scaler_dis_w;
339 u16 in_rot_en_h;
340 u16 in_rot_dis_w;
341 u16 out_rot_en_w;
342 u16 out_rot_dis_w;
343};
344
345/**
346 * struct samsung_fimc_variant - camera interface variant information
347 *
348 * @pix_hoff: indicate whether horizontal offset is in pixels or in bytes
349 * @has_inp_rot: set if has input rotator
350 * @has_out_rot: set if has output rotator
351 * @has_cistatus2: 1 if CISTATUS2 register is present in this IP revision
352 * @has_mainscaler_ext: 1 if extended mainscaler ratios in CIEXTEN register
353 * are present in this IP revision
354 * @pix_limit: pixel size constraints for the scaler
355 * @min_inp_pixsize: minimum input pixel size
356 * @min_out_pixsize: minimum output pixel size
357 * @hor_offs_align: horizontal pixel offset aligment
358 * @out_buf_count: the number of buffers in output DMA sequence
359 */
360struct samsung_fimc_variant {
361 unsigned int pix_hoff:1;
362 unsigned int has_inp_rot:1;
363 unsigned int has_out_rot:1;
364 unsigned int has_cistatus2:1;
365 unsigned int has_mainscaler_ext:1;
366 struct fimc_pix_limit *pix_limit;
367 u16 min_inp_pixsize;
368 u16 min_out_pixsize;
369 u16 hor_offs_align;
370 u16 out_buf_count;
371};
372
373/**
374 * struct samsung_fimc_driverdata - per device type driver data for init time.
375 *
376 * @variant: the variant information for this driver.
377 * @dev_cnt: number of fimc sub-devices available in SoC
378 * @lclk_frequency: fimc bus clock frequency
379 */
380struct samsung_fimc_driverdata {
381 struct samsung_fimc_variant *variant[FIMC_MAX_DEVS];
382 unsigned long lclk_frequency;
383 int num_entities;
384};
385
386struct fimc_ctx;
387
388/**
389 * struct fimc_dev - abstraction for FIMC entity
390 * @slock: the spinlock protecting this data structure
391 * @lock: the mutex protecting this data structure
392 * @pdev: pointer to the FIMC platform device
393 * @pdata: pointer to the device platform data
394 * @variant: the IP variant information
395 * @id: FIMC device index (0..FIMC_MAX_DEVS)
396 * @num_clocks: the number of clocks managed by this device instance
397 * @clock: clocks required for FIMC operation
398 * @regs: the mapped hardware registers
399 * @regs_res: the resource claimed for IO registers
400 * @irq: FIMC interrupt number
401 * @irq_queue: interrupt handler waitqueue
402 * @m2m: memory-to-memory V4L2 device information
403 * @vid_cap: camera capture device information
404 * @state: flags used to synchronize m2m and capture mode operation
405 * @alloc_ctx: videobuf2 memory allocator context
406 */
407struct fimc_dev {
408 spinlock_t slock;
409 struct mutex lock;
410 struct platform_device *pdev;
411 struct s5p_platform_fimc *pdata;
412 struct samsung_fimc_variant *variant;
413 u16 id;
414 u16 num_clocks;
415 struct clk *clock[MAX_FIMC_CLOCKS];
416 void __iomem *regs;
417 struct resource *regs_res;
418 int irq;
419 wait_queue_head_t irq_queue;
420 struct fimc_m2m_device m2m;
421 struct fimc_vid_cap vid_cap;
422 unsigned long state;
423 struct vb2_alloc_ctx *alloc_ctx;
424};
425
426/**
427 * fimc_ctx - the device context data
428 * @slock: spinlock protecting this data structure
429 * @s_frame: source frame properties
430 * @d_frame: destination frame properties
431 * @out_order_1p: output 1-plane YCBCR order
432 * @out_order_2p: output 2-plane YCBCR order
433 * @in_order_1p input 1-plane YCBCR order
434 * @in_order_2p: input 2-plane YCBCR order
435 * @in_path: input mode (DMA or camera)
436 * @out_path: output mode (DMA or FIFO)
437 * @scaler: image scaler properties
438 * @effect: image effect
439 * @rotation: image clockwise rotation in degrees
440 * @flip: image flip mode
441 * @flags: additional flags for image conversion
442 * @state: flags to keep track of user configuration
443 * @fimc_dev: the FIMC device this context applies to
444 * @m2m_ctx: memory-to-memory device context
445 */
446struct fimc_ctx {
447 spinlock_t slock;
448 struct fimc_frame s_frame;
449 struct fimc_frame d_frame;
450 u32 out_order_1p;
451 u32 out_order_2p;
452 u32 in_order_1p;
453 u32 in_order_2p;
454 enum fimc_datapath in_path;
455 enum fimc_datapath out_path;
456 struct fimc_scaler scaler;
457 struct fimc_effect effect;
458 int rotation;
459 u32 flip;
460 u32 flags;
461 u32 state;
462 struct fimc_dev *fimc_dev;
463 struct v4l2_m2m_ctx *m2m_ctx;
464};
465
466static inline bool fimc_capture_active(struct fimc_dev *fimc)
467{
468 unsigned long flags;
469 bool ret;
470
471 spin_lock_irqsave(&fimc->slock, flags);
472 ret = !!(fimc->state & (1 << ST_CAPT_RUN) ||
473 fimc->state & (1 << ST_CAPT_PEND));
474 spin_unlock_irqrestore(&fimc->slock, flags);
475 return ret;
476}
477
478static inline void fimc_ctx_state_lock_set(u32 state, struct fimc_ctx *ctx)
479{
480 unsigned long flags;
481
482 spin_lock_irqsave(&ctx->slock, flags);
483 ctx->state |= state;
484 spin_unlock_irqrestore(&ctx->slock, flags);
485}
486
487static inline bool fimc_ctx_state_is_set(u32 mask, struct fimc_ctx *ctx)
488{
489 unsigned long flags;
490 bool ret;
491
492 spin_lock_irqsave(&ctx->slock, flags);
493 ret = (ctx->state & mask) == mask;
494 spin_unlock_irqrestore(&ctx->slock, flags);
495 return ret;
496}
497
498static inline int tiled_fmt(struct fimc_fmt *fmt)
499{
500 return fmt->fourcc == V4L2_PIX_FMT_NV12MT;
501}
502
503static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
504{
505 u32 cfg = readl(dev->regs + S5P_CIGCTRL);
506 cfg |= S5P_CIGCTRL_IRQ_CLR;
507 writel(cfg, dev->regs + S5P_CIGCTRL);
508}
509
510static inline void fimc_hw_enable_scaler(struct fimc_dev *dev, bool on)
511{
512 u32 cfg = readl(dev->regs + S5P_CISCCTRL);
513 if (on)
514 cfg |= S5P_CISCCTRL_SCALERSTART;
515 else
516 cfg &= ~S5P_CISCCTRL_SCALERSTART;
517 writel(cfg, dev->regs + S5P_CISCCTRL);
518}
519
520static inline void fimc_hw_activate_input_dma(struct fimc_dev *dev, bool on)
521{
522 u32 cfg = readl(dev->regs + S5P_MSCTRL);
523 if (on)
524 cfg |= S5P_MSCTRL_ENVID;
525 else
526 cfg &= ~S5P_MSCTRL_ENVID;
527 writel(cfg, dev->regs + S5P_MSCTRL);
528}
529
530static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
531{
532 u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
533 cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
534 writel(cfg, dev->regs + S5P_CIIMGCPT);
535}
536
537/**
538 * fimc_hw_set_dma_seq - configure output DMA buffer sequence
539 * @mask: each bit corresponds to one of 32 output buffer registers set
540 * 1 to include buffer in the sequence, 0 to disable
541 *
542 * This function mask output DMA ring buffers, i.e. it allows to configure
543 * which of the output buffer address registers will be used by the DMA
544 * engine.
545 */
546static inline void fimc_hw_set_dma_seq(struct fimc_dev *dev, u32 mask)
547{
548 writel(mask, dev->regs + S5P_CIFCNTSEQ);
549}
550
551static inline struct fimc_frame *ctx_get_frame(struct fimc_ctx *ctx,
552 enum v4l2_buf_type type)
553{
554 struct fimc_frame *frame;
555
556 if (V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE == type) {
557 if (fimc_ctx_state_is_set(FIMC_CTX_M2M, ctx))
558 frame = &ctx->s_frame;
559 else
560 return ERR_PTR(-EINVAL);
561 } else if (V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE == type) {
562 frame = &ctx->d_frame;
563 } else {
564 v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
565 "Wrong buffer/video queue type (%d)\n", type);
566 return ERR_PTR(-EINVAL);
567 }
568
569 return frame;
570}
571
572/* Return an index to the buffer actually being written. */
573static inline u32 fimc_hw_get_frame_index(struct fimc_dev *dev)
574{
575 u32 reg;
576
577 if (dev->variant->has_cistatus2) {
578 reg = readl(dev->regs + S5P_CISTATUS2) & 0x3F;
579 return reg > 0 ? --reg : reg;
580 } else {
581 reg = readl(dev->regs + S5P_CISTATUS);
582 return (reg & S5P_CISTATUS_FRAMECNT_MASK) >>
583 S5P_CISTATUS_FRAMECNT_SHIFT;
584 }
585}
586
587/* -----------------------------------------------------*/
588/* fimc-reg.c */
589void fimc_hw_reset(struct fimc_dev *fimc);
590void fimc_hw_set_rotation(struct fimc_ctx *ctx);
591void fimc_hw_set_target_format(struct fimc_ctx *ctx);
592void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
593void fimc_hw_en_lastirq(struct fimc_dev *fimc, int enable);
594void fimc_hw_en_irq(struct fimc_dev *fimc, int enable);
595void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
596void fimc_hw_set_mainscaler(struct fimc_ctx *ctx);
597void fimc_hw_en_capture(struct fimc_ctx *ctx);
598void fimc_hw_set_effect(struct fimc_ctx *ctx);
599void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
600void fimc_hw_set_input_path(struct fimc_ctx *ctx);
601void fimc_hw_set_output_path(struct fimc_ctx *ctx);
602void fimc_hw_set_input_addr(struct fimc_dev *fimc, struct fimc_addr *paddr);
603void fimc_hw_set_output_addr(struct fimc_dev *fimc, struct fimc_addr *paddr,
604 int index);
605int fimc_hw_set_camera_source(struct fimc_dev *fimc,
606 struct s5p_fimc_isp_info *cam);
607int fimc_hw_set_camera_offset(struct fimc_dev *fimc, struct fimc_frame *f);
608int fimc_hw_set_camera_polarity(struct fimc_dev *fimc,
609 struct s5p_fimc_isp_info *cam);
610int fimc_hw_set_camera_type(struct fimc_dev *fimc,
611 struct s5p_fimc_isp_info *cam);
612
613/* -----------------------------------------------------*/
614/* fimc-core.c */
615int fimc_vidioc_enum_fmt_mplane(struct file *file, void *priv,
616 struct v4l2_fmtdesc *f);
617int fimc_vidioc_g_fmt_mplane(struct file *file, void *priv,
618 struct v4l2_format *f);
619int fimc_vidioc_try_fmt_mplane(struct file *file, void *priv,
620 struct v4l2_format *f);
621int fimc_vidioc_queryctrl(struct file *file, void *priv,
622 struct v4l2_queryctrl *qc);
623int fimc_vidioc_g_ctrl(struct file *file, void *priv,
624 struct v4l2_control *ctrl);
625
626int fimc_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr);
627int check_ctrl_val(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
628int fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_control *ctrl);
629
630struct fimc_fmt *find_format(struct v4l2_format *f, unsigned int mask);
631struct fimc_fmt *find_mbus_format(struct v4l2_mbus_framefmt *f,
632 unsigned int mask);
633
634int fimc_check_scaler_ratio(int sw, int sh, int dw, int dh, int rot);
635int fimc_set_scaler_info(struct fimc_ctx *ctx);
636int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
637int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
638 struct fimc_frame *frame, struct fimc_addr *paddr);
639
640/* -----------------------------------------------------*/
641/* fimc-capture.c */
642int fimc_register_capture_device(struct fimc_dev *fimc);
643void fimc_unregister_capture_device(struct fimc_dev *fimc);
644int fimc_sensor_sd_init(struct fimc_dev *fimc, int index);
645int fimc_vid_cap_buf_queue(struct fimc_dev *fimc,
646 struct fimc_vid_buffer *fimc_vb);
647
648/* Locking: the caller holds fimc->slock */
649static inline void fimc_activate_capture(struct fimc_ctx *ctx)
650{
651 fimc_hw_enable_scaler(ctx->fimc_dev, ctx->scaler.enabled);
652 fimc_hw_en_capture(ctx);
653}
654
655static inline void fimc_deactivate_capture(struct fimc_dev *fimc)
656{
657 fimc_hw_en_lastirq(fimc, true);
658 fimc_hw_dis_capture(fimc);
659 fimc_hw_enable_scaler(fimc, false);
660 fimc_hw_en_lastirq(fimc, false);
661}
662
663/*
664 * Add buf to the capture active buffers queue.
665 * Locking: Need to be called with fimc_dev::slock held.
666 */
667static inline void active_queue_add(struct fimc_vid_cap *vid_cap,
668 struct fimc_vid_buffer *buf)
669{
670 list_add_tail(&buf->list, &vid_cap->active_buf_q);
671 vid_cap->active_buf_cnt++;
672}
673
674/*
675 * Pop a video buffer from the capture active buffers queue
676 * Locking: Need to be called with fimc_dev::slock held.
677 */
678static inline struct fimc_vid_buffer *
679active_queue_pop(struct fimc_vid_cap *vid_cap)
680{
681 struct fimc_vid_buffer *buf;
682 buf = list_entry(vid_cap->active_buf_q.next,
683 struct fimc_vid_buffer, list);
684 list_del(&buf->list);
685 vid_cap->active_buf_cnt--;
686 return buf;
687}
688
689/* Add video buffer to the capture pending buffers queue */
690static inline void fimc_pending_queue_add(struct fimc_vid_cap *vid_cap,
691 struct fimc_vid_buffer *buf)
692{
693 list_add_tail(&buf->list, &vid_cap->pending_buf_q);
694}
695
696/* Add video buffer to the capture pending buffers queue */
697static inline struct fimc_vid_buffer *
698pending_queue_pop(struct fimc_vid_cap *vid_cap)
699{
700 struct fimc_vid_buffer *buf;
701 buf = list_entry(vid_cap->pending_buf_q.next,
702 struct fimc_vid_buffer, list);
703 list_del(&buf->list);
704 return buf;
705}
706
707#endif /* FIMC_CORE_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-20 23:16:56 -0400