diff options
author | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-17 16:15:55 -0500 |
---|---|---|
committer | Jonathan Herman <hermanjl@cs.unc.edu> | 2013-01-17 16:15:55 -0500 |
commit | 8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch) | |
tree | a8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /arch/mips/include/asm/netlogic | |
parent | 406089d01562f1e2bf9f089fd7637009ebaad589 (diff) |
Patched in Tegra support.
Diffstat (limited to 'arch/mips/include/asm/netlogic')
21 files changed, 85 insertions, 2446 deletions
diff --git a/arch/mips/include/asm/netlogic/common.h b/arch/mips/include/asm/netlogic/common.h deleted file mode 100644 index 42bfd5f1eee..00000000000 --- a/arch/mips/include/asm/netlogic/common.h +++ /dev/null | |||
@@ -1,113 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | ||
3 | * reserved. | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the NetLogic | ||
9 | * license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or without | ||
12 | * modification, are permitted provided that the following conditions | ||
13 | * are met: | ||
14 | * | ||
15 | * 1. Redistributions of source code must retain the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer. | ||
17 | * 2. Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in | ||
19 | * the documentation and/or other materials provided with the | ||
20 | * distribution. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | ||
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | ||
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef _NETLOGIC_COMMON_H_ | ||
36 | #define _NETLOGIC_COMMON_H_ | ||
37 | |||
38 | /* | ||
39 | * Common SMP definitions | ||
40 | */ | ||
41 | #define RESET_VEC_PHYS 0x1fc00000 | ||
42 | #define RESET_DATA_PHYS (RESET_VEC_PHYS + (1<<10)) | ||
43 | #define BOOT_THREAD_MODE 0 | ||
44 | #define BOOT_NMI_LOCK 4 | ||
45 | #define BOOT_NMI_HANDLER 8 | ||
46 | |||
47 | #ifndef __ASSEMBLY__ | ||
48 | #include <linux/cpumask.h> | ||
49 | #include <linux/spinlock.h> | ||
50 | #include <asm/irq.h> | ||
51 | #include <asm/mach-netlogic/multi-node.h> | ||
52 | |||
53 | struct irq_desc; | ||
54 | void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc); | ||
55 | void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc); | ||
56 | void nlm_smp_irq_init(int hwcpuid); | ||
57 | void nlm_boot_secondary_cpus(void); | ||
58 | int nlm_wakeup_secondary_cpus(void); | ||
59 | void nlm_rmiboot_preboot(void); | ||
60 | void nlm_percpu_init(int hwcpuid); | ||
61 | |||
62 | static inline void | ||
63 | nlm_set_nmi_handler(void *handler) | ||
64 | { | ||
65 | char *reset_data; | ||
66 | |||
67 | reset_data = (char *)CKSEG1ADDR(RESET_DATA_PHYS); | ||
68 | *(int64_t *)(reset_data + BOOT_NMI_HANDLER) = (long)handler; | ||
69 | } | ||
70 | |||
71 | /* | ||
72 | * Misc. | ||
73 | */ | ||
74 | unsigned int nlm_get_cpu_frequency(void); | ||
75 | void nlm_node_init(int node); | ||
76 | extern struct plat_smp_ops nlm_smp_ops; | ||
77 | extern char nlm_reset_entry[], nlm_reset_entry_end[]; | ||
78 | |||
79 | extern unsigned int nlm_threads_per_core; | ||
80 | extern cpumask_t nlm_cpumask; | ||
81 | |||
82 | struct nlm_soc_info { | ||
83 | unsigned long coremask; /* cores enabled on the soc */ | ||
84 | unsigned long ebase; | ||
85 | uint64_t irqmask; | ||
86 | uint64_t sysbase; /* only for XLP */ | ||
87 | uint64_t picbase; | ||
88 | spinlock_t piclock; | ||
89 | }; | ||
90 | |||
91 | #define nlm_get_node(i) (&nlm_nodes[i]) | ||
92 | #ifdef CONFIG_CPU_XLR | ||
93 | #define nlm_current_node() (&nlm_nodes[0]) | ||
94 | #else | ||
95 | #define nlm_current_node() (&nlm_nodes[nlm_nodeid()]) | ||
96 | #endif | ||
97 | |||
98 | struct irq_data; | ||
99 | uint64_t nlm_pci_irqmask(int node); | ||
100 | void nlm_set_pic_extra_ack(int node, int irq, void (*xack)(struct irq_data *)); | ||
101 | |||
102 | /* | ||
103 | * The NR_IRQs is divided between nodes, each of them has a separate irq space | ||
104 | */ | ||
105 | static inline int nlm_irq_to_xirq(int node, int irq) | ||
106 | { | ||
107 | return node * NR_IRQS / NLM_NR_NODES + irq; | ||
108 | } | ||
109 | |||
110 | extern struct nlm_soc_info nlm_nodes[NLM_NR_NODES]; | ||
111 | extern int nlm_cpu_ready[]; | ||
112 | #endif | ||
113 | #endif /* _NETLOGIC_COMMON_H_ */ | ||
diff --git a/arch/mips/include/asm/netlogic/haldefs.h b/arch/mips/include/asm/netlogic/haldefs.h deleted file mode 100644 index 72a0c788b47..00000000000 --- a/arch/mips/include/asm/netlogic/haldefs.h +++ /dev/null | |||
@@ -1,163 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | ||
3 | * reserved. | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the NetLogic | ||
9 | * license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or without | ||
12 | * modification, are permitted provided that the following conditions | ||
13 | * are met: | ||
14 | * | ||
15 | * 1. Redistributions of source code must retain the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer. | ||
17 | * 2. Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in | ||
19 | * the documentation and/or other materials provided with the | ||
20 | * distribution. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | ||
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | ||
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef __NLM_HAL_HALDEFS_H__ | ||
36 | #define __NLM_HAL_HALDEFS_H__ | ||
37 | |||
38 | /* | ||
39 | * This file contains platform specific memory mapped IO implementation | ||
40 | * and will provide a way to read 32/64 bit memory mapped registers in | ||
41 | * all ABIs | ||
42 | */ | ||
43 | #if !defined(CONFIG_64BIT) && defined(CONFIG_CPU_XLP) | ||
44 | #error "o32 compile not supported on XLP yet" | ||
45 | #endif | ||
46 | /* | ||
47 | * For o32 compilation, we have to disable interrupts and enable KX bit to | ||
48 | * access 64 bit addresses or data. | ||
49 | * | ||
50 | * We need to disable interrupts because we save just the lower 32 bits of | ||
51 | * registers in interrupt handling. So if we get hit by an interrupt while | ||
52 | * using the upper 32 bits of a register, we lose. | ||
53 | */ | ||
54 | static inline uint32_t nlm_save_flags_kx(void) | ||
55 | { | ||
56 | return change_c0_status(ST0_KX | ST0_IE, ST0_KX); | ||
57 | } | ||
58 | |||
59 | static inline uint32_t nlm_save_flags_cop2(void) | ||
60 | { | ||
61 | return change_c0_status(ST0_CU2 | ST0_IE, ST0_CU2); | ||
62 | } | ||
63 | |||
64 | static inline void nlm_restore_flags(uint32_t sr) | ||
65 | { | ||
66 | write_c0_status(sr); | ||
67 | } | ||
68 | |||
69 | /* | ||
70 | * The n64 implementations are simple, the o32 implementations when they | ||
71 | * are added, will have to disable interrupts and enable KX before doing | ||
72 | * 64 bit ops. | ||
73 | */ | ||
74 | static inline uint32_t | ||
75 | nlm_read_reg(uint64_t base, uint32_t reg) | ||
76 | { | ||
77 | volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; | ||
78 | |||
79 | return *addr; | ||
80 | } | ||
81 | |||
82 | static inline void | ||
83 | nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) | ||
84 | { | ||
85 | volatile uint32_t *addr = (volatile uint32_t *)(long)base + reg; | ||
86 | |||
87 | *addr = val; | ||
88 | } | ||
89 | |||
90 | static inline uint64_t | ||
91 | nlm_read_reg64(uint64_t base, uint32_t reg) | ||
92 | { | ||
93 | uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); | ||
94 | volatile uint64_t *ptr = (volatile uint64_t *)(long)addr; | ||
95 | |||
96 | return *ptr; | ||
97 | } | ||
98 | |||
99 | static inline void | ||
100 | nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) | ||
101 | { | ||
102 | uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); | ||
103 | volatile uint64_t *ptr = (volatile uint64_t *)(long)addr; | ||
104 | |||
105 | *ptr = val; | ||
106 | } | ||
107 | |||
108 | /* | ||
109 | * Routines to store 32/64 bit values to 64 bit addresses, | ||
110 | * used when going thru XKPHYS to access registers | ||
111 | */ | ||
112 | static inline uint32_t | ||
113 | nlm_read_reg_xkphys(uint64_t base, uint32_t reg) | ||
114 | { | ||
115 | return nlm_read_reg(base, reg); | ||
116 | } | ||
117 | |||
118 | static inline void | ||
119 | nlm_write_reg_xkphys(uint64_t base, uint32_t reg, uint32_t val) | ||
120 | { | ||
121 | nlm_write_reg(base, reg, val); | ||
122 | } | ||
123 | |||
124 | static inline uint64_t | ||
125 | nlm_read_reg64_xkphys(uint64_t base, uint32_t reg) | ||
126 | { | ||
127 | return nlm_read_reg64(base, reg); | ||
128 | } | ||
129 | |||
130 | static inline void | ||
131 | nlm_write_reg64_xkphys(uint64_t base, uint32_t reg, uint64_t val) | ||
132 | { | ||
133 | nlm_write_reg64(base, reg, val); | ||
134 | } | ||
135 | |||
136 | /* Location where IO base is mapped */ | ||
137 | extern uint64_t nlm_io_base; | ||
138 | |||
139 | #if defined(CONFIG_CPU_XLP) | ||
140 | static inline uint64_t | ||
141 | nlm_pcicfg_base(uint32_t devoffset) | ||
142 | { | ||
143 | return nlm_io_base + devoffset; | ||
144 | } | ||
145 | |||
146 | static inline uint64_t | ||
147 | nlm_xkphys_map_pcibar0(uint64_t pcibase) | ||
148 | { | ||
149 | uint64_t paddr; | ||
150 | |||
151 | paddr = nlm_read_reg(pcibase, 0x4) & ~0xfu; | ||
152 | return (uint64_t)0x9000000000000000 | paddr; | ||
153 | } | ||
154 | #elif defined(CONFIG_CPU_XLR) | ||
155 | |||
156 | static inline uint64_t | ||
157 | nlm_mmio_base(uint32_t devoffset) | ||
158 | { | ||
159 | return nlm_io_base + devoffset; | ||
160 | } | ||
161 | #endif | ||
162 | |||
163 | #endif | ||
diff --git a/arch/mips/include/asm/netlogic/interrupt.h b/arch/mips/include/asm/netlogic/interrupt.h index ed5993d9b7b..a85aadb6cfd 100644 --- a/arch/mips/include/asm/netlogic/interrupt.h +++ b/arch/mips/include/asm/netlogic/interrupt.h | |||
@@ -39,7 +39,7 @@ | |||
39 | 39 | ||
40 | #define IRQ_IPI_SMP_FUNCTION 3 | 40 | #define IRQ_IPI_SMP_FUNCTION 3 |
41 | #define IRQ_IPI_SMP_RESCHEDULE 4 | 41 | #define IRQ_IPI_SMP_RESCHEDULE 4 |
42 | #define IRQ_FMN 5 | 42 | #define IRQ_MSGRING 6 |
43 | #define IRQ_TIMER 7 | 43 | #define IRQ_TIMER 7 |
44 | 44 | ||
45 | #endif | 45 | #endif |
diff --git a/arch/mips/include/asm/netlogic/mips-extns.h b/arch/mips/include/asm/netlogic/mips-extns.h index 32ba6d95d47..8c53d0ba4bf 100644 --- a/arch/mips/include/asm/netlogic/mips-extns.h +++ b/arch/mips/include/asm/netlogic/mips-extns.h | |||
@@ -73,146 +73,4 @@ static inline int hard_smp_processor_id(void) | |||
73 | return __read_32bit_c0_register($15, 1) & 0x3ff; | 73 | return __read_32bit_c0_register($15, 1) & 0x3ff; |
74 | } | 74 | } |
75 | 75 | ||
76 | static inline int nlm_nodeid(void) | ||
77 | { | ||
78 | return (__read_32bit_c0_register($15, 1) >> 5) & 0x3; | ||
79 | } | ||
80 | |||
81 | static inline unsigned int nlm_core_id(void) | ||
82 | { | ||
83 | return (read_c0_ebase() & 0x1c) >> 2; | ||
84 | } | ||
85 | |||
86 | static inline unsigned int nlm_thread_id(void) | ||
87 | { | ||
88 | return read_c0_ebase() & 0x3; | ||
89 | } | ||
90 | |||
91 | #define __read_64bit_c2_split(source, sel) \ | ||
92 | ({ \ | ||
93 | unsigned long long __val; \ | ||
94 | unsigned long __flags; \ | ||
95 | \ | ||
96 | local_irq_save(__flags); \ | ||
97 | if (sel == 0) \ | ||
98 | __asm__ __volatile__( \ | ||
99 | ".set\tmips64\n\t" \ | ||
100 | "dmfc2\t%M0, " #source "\n\t" \ | ||
101 | "dsll\t%L0, %M0, 32\n\t" \ | ||
102 | "dsra\t%M0, %M0, 32\n\t" \ | ||
103 | "dsra\t%L0, %L0, 32\n\t" \ | ||
104 | ".set\tmips0\n\t" \ | ||
105 | : "=r" (__val)); \ | ||
106 | else \ | ||
107 | __asm__ __volatile__( \ | ||
108 | ".set\tmips64\n\t" \ | ||
109 | "dmfc2\t%M0, " #source ", " #sel "\n\t" \ | ||
110 | "dsll\t%L0, %M0, 32\n\t" \ | ||
111 | "dsra\t%M0, %M0, 32\n\t" \ | ||
112 | "dsra\t%L0, %L0, 32\n\t" \ | ||
113 | ".set\tmips0\n\t" \ | ||
114 | : "=r" (__val)); \ | ||
115 | local_irq_restore(__flags); \ | ||
116 | \ | ||
117 | __val; \ | ||
118 | }) | ||
119 | |||
120 | #define __write_64bit_c2_split(source, sel, val) \ | ||
121 | do { \ | ||
122 | unsigned long __flags; \ | ||
123 | \ | ||
124 | local_irq_save(__flags); \ | ||
125 | if (sel == 0) \ | ||
126 | __asm__ __volatile__( \ | ||
127 | ".set\tmips64\n\t" \ | ||
128 | "dsll\t%L0, %L0, 32\n\t" \ | ||
129 | "dsrl\t%L0, %L0, 32\n\t" \ | ||
130 | "dsll\t%M0, %M0, 32\n\t" \ | ||
131 | "or\t%L0, %L0, %M0\n\t" \ | ||
132 | "dmtc2\t%L0, " #source "\n\t" \ | ||
133 | ".set\tmips0\n\t" \ | ||
134 | : : "r" (val)); \ | ||
135 | else \ | ||
136 | __asm__ __volatile__( \ | ||
137 | ".set\tmips64\n\t" \ | ||
138 | "dsll\t%L0, %L0, 32\n\t" \ | ||
139 | "dsrl\t%L0, %L0, 32\n\t" \ | ||
140 | "dsll\t%M0, %M0, 32\n\t" \ | ||
141 | "or\t%L0, %L0, %M0\n\t" \ | ||
142 | "dmtc2\t%L0, " #source ", " #sel "\n\t" \ | ||
143 | ".set\tmips0\n\t" \ | ||
144 | : : "r" (val)); \ | ||
145 | local_irq_restore(__flags); \ | ||
146 | } while (0) | ||
147 | |||
148 | #define __read_32bit_c2_register(source, sel) \ | ||
149 | ({ uint32_t __res; \ | ||
150 | if (sel == 0) \ | ||
151 | __asm__ __volatile__( \ | ||
152 | ".set\tmips32\n\t" \ | ||
153 | "mfc2\t%0, " #source "\n\t" \ | ||
154 | ".set\tmips0\n\t" \ | ||
155 | : "=r" (__res)); \ | ||
156 | else \ | ||
157 | __asm__ __volatile__( \ | ||
158 | ".set\tmips32\n\t" \ | ||
159 | "mfc2\t%0, " #source ", " #sel "\n\t" \ | ||
160 | ".set\tmips0\n\t" \ | ||
161 | : "=r" (__res)); \ | ||
162 | __res; \ | ||
163 | }) | ||
164 | |||
165 | #define __read_64bit_c2_register(source, sel) \ | ||
166 | ({ unsigned long long __res; \ | ||
167 | if (sizeof(unsigned long) == 4) \ | ||
168 | __res = __read_64bit_c2_split(source, sel); \ | ||
169 | else if (sel == 0) \ | ||
170 | __asm__ __volatile__( \ | ||
171 | ".set\tmips64\n\t" \ | ||
172 | "dmfc2\t%0, " #source "\n\t" \ | ||
173 | ".set\tmips0\n\t" \ | ||
174 | : "=r" (__res)); \ | ||
175 | else \ | ||
176 | __asm__ __volatile__( \ | ||
177 | ".set\tmips64\n\t" \ | ||
178 | "dmfc2\t%0, " #source ", " #sel "\n\t" \ | ||
179 | ".set\tmips0\n\t" \ | ||
180 | : "=r" (__res)); \ | ||
181 | __res; \ | ||
182 | }) | ||
183 | |||
184 | #define __write_64bit_c2_register(register, sel, value) \ | ||
185 | do { \ | ||
186 | if (sizeof(unsigned long) == 4) \ | ||
187 | __write_64bit_c2_split(register, sel, value); \ | ||
188 | else if (sel == 0) \ | ||
189 | __asm__ __volatile__( \ | ||
190 | ".set\tmips64\n\t" \ | ||
191 | "dmtc2\t%z0, " #register "\n\t" \ | ||
192 | ".set\tmips0\n\t" \ | ||
193 | : : "Jr" (value)); \ | ||
194 | else \ | ||
195 | __asm__ __volatile__( \ | ||
196 | ".set\tmips64\n\t" \ | ||
197 | "dmtc2\t%z0, " #register ", " #sel "\n\t" \ | ||
198 | ".set\tmips0\n\t" \ | ||
199 | : : "Jr" (value)); \ | ||
200 | } while (0) | ||
201 | |||
202 | #define __write_32bit_c2_register(reg, sel, value) \ | ||
203 | ({ \ | ||
204 | if (sel == 0) \ | ||
205 | __asm__ __volatile__( \ | ||
206 | ".set\tmips32\n\t" \ | ||
207 | "mtc2\t%z0, " #reg "\n\t" \ | ||
208 | ".set\tmips0\n\t" \ | ||
209 | : : "Jr" (value)); \ | ||
210 | else \ | ||
211 | __asm__ __volatile__( \ | ||
212 | ".set\tmips32\n\t" \ | ||
213 | "mtc2\t%z0, " #reg ", " #sel "\n\t" \ | ||
214 | ".set\tmips0\n\t" \ | ||
215 | : : "Jr" (value)); \ | ||
216 | }) | ||
217 | |||
218 | #endif /*_ASM_NLM_MIPS_EXTS_H */ | 76 | #endif /*_ASM_NLM_MIPS_EXTS_H */ |
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h b/arch/mips/include/asm/netlogic/xlp-hal/bridge.h deleted file mode 100644 index ca95133f1ad..00000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/bridge.h +++ /dev/null | |||
@@ -1,187 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | ||
3 | * reserved. | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the NetLogic | ||
9 | * license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or without | ||
12 | * modification, are permitted provided that the following conditions | ||
13 | * are met: | ||
14 | * | ||
15 | * 1. Redistributions of source code must retain the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer. | ||
17 | * 2. Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in | ||
19 | * the documentation and/or other materials provided with the | ||
20 | * distribution. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | ||
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | ||
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef __NLM_HAL_BRIDGE_H__ | ||
36 | #define __NLM_HAL_BRIDGE_H__ | ||
37 | |||
38 | /** | ||
39 | * @file_name mio.h | ||
40 | * @author Netlogic Microsystems | ||
41 | * @brief Basic definitions of XLP memory and io subsystem | ||
42 | */ | ||
43 | |||
44 | /* | ||
45 | * BRIDGE specific registers | ||
46 | * | ||
47 | * These registers start after the PCIe header, which has 0x40 | ||
48 | * standard entries | ||
49 | */ | ||
50 | #define BRIDGE_MODE 0x00 | ||
51 | #define BRIDGE_PCI_CFG_BASE 0x01 | ||
52 | #define BRIDGE_PCI_CFG_LIMIT 0x02 | ||
53 | #define BRIDGE_PCIE_CFG_BASE 0x03 | ||
54 | #define BRIDGE_PCIE_CFG_LIMIT 0x04 | ||
55 | #define BRIDGE_BUSNUM_BAR0 0x05 | ||
56 | #define BRIDGE_BUSNUM_BAR1 0x06 | ||
57 | #define BRIDGE_BUSNUM_BAR2 0x07 | ||
58 | #define BRIDGE_BUSNUM_BAR3 0x08 | ||
59 | #define BRIDGE_BUSNUM_BAR4 0x09 | ||
60 | #define BRIDGE_BUSNUM_BAR5 0x0a | ||
61 | #define BRIDGE_BUSNUM_BAR6 0x0b | ||
62 | #define BRIDGE_FLASH_BAR0 0x0c | ||
63 | #define BRIDGE_FLASH_BAR1 0x0d | ||
64 | #define BRIDGE_FLASH_BAR2 0x0e | ||
65 | #define BRIDGE_FLASH_BAR3 0x0f | ||
66 | #define BRIDGE_FLASH_LIMIT0 0x10 | ||
67 | #define BRIDGE_FLASH_LIMIT1 0x11 | ||
68 | #define BRIDGE_FLASH_LIMIT2 0x12 | ||
69 | #define BRIDGE_FLASH_LIMIT3 0x13 | ||
70 | |||
71 | #define BRIDGE_DRAM_BAR(i) (0x14 + (i)) | ||
72 | #define BRIDGE_DRAM_BAR0 0x14 | ||
73 | #define BRIDGE_DRAM_BAR1 0x15 | ||
74 | #define BRIDGE_DRAM_BAR2 0x16 | ||
75 | #define BRIDGE_DRAM_BAR3 0x17 | ||
76 | #define BRIDGE_DRAM_BAR4 0x18 | ||
77 | #define BRIDGE_DRAM_BAR5 0x19 | ||
78 | #define BRIDGE_DRAM_BAR6 0x1a | ||
79 | #define BRIDGE_DRAM_BAR7 0x1b | ||
80 | |||
81 | #define BRIDGE_DRAM_LIMIT(i) (0x1c + (i)) | ||
82 | #define BRIDGE_DRAM_LIMIT0 0x1c | ||
83 | #define BRIDGE_DRAM_LIMIT1 0x1d | ||
84 | #define BRIDGE_DRAM_LIMIT2 0x1e | ||
85 | #define BRIDGE_DRAM_LIMIT3 0x1f | ||
86 | #define BRIDGE_DRAM_LIMIT4 0x20 | ||
87 | #define BRIDGE_DRAM_LIMIT5 0x21 | ||
88 | #define BRIDGE_DRAM_LIMIT6 0x22 | ||
89 | #define BRIDGE_DRAM_LIMIT7 0x23 | ||
90 | |||
91 | #define BRIDGE_DRAM_NODE_TRANSLN0 0x24 | ||
92 | #define BRIDGE_DRAM_NODE_TRANSLN1 0x25 | ||
93 | #define BRIDGE_DRAM_NODE_TRANSLN2 0x26 | ||
94 | #define BRIDGE_DRAM_NODE_TRANSLN3 0x27 | ||
95 | #define BRIDGE_DRAM_NODE_TRANSLN4 0x28 | ||
96 | #define BRIDGE_DRAM_NODE_TRANSLN5 0x29 | ||
97 | #define BRIDGE_DRAM_NODE_TRANSLN6 0x2a | ||
98 | #define BRIDGE_DRAM_NODE_TRANSLN7 0x2b | ||
99 | #define BRIDGE_DRAM_CHNL_TRANSLN0 0x2c | ||
100 | #define BRIDGE_DRAM_CHNL_TRANSLN1 0x2d | ||
101 | #define BRIDGE_DRAM_CHNL_TRANSLN2 0x2e | ||
102 | #define BRIDGE_DRAM_CHNL_TRANSLN3 0x2f | ||
103 | #define BRIDGE_DRAM_CHNL_TRANSLN4 0x30 | ||
104 | #define BRIDGE_DRAM_CHNL_TRANSLN5 0x31 | ||
105 | #define BRIDGE_DRAM_CHNL_TRANSLN6 0x32 | ||
106 | #define BRIDGE_DRAM_CHNL_TRANSLN7 0x33 | ||
107 | #define BRIDGE_PCIEMEM_BASE0 0x34 | ||
108 | #define BRIDGE_PCIEMEM_BASE1 0x35 | ||
109 | #define BRIDGE_PCIEMEM_BASE2 0x36 | ||
110 | #define BRIDGE_PCIEMEM_BASE3 0x37 | ||
111 | #define BRIDGE_PCIEMEM_LIMIT0 0x38 | ||
112 | #define BRIDGE_PCIEMEM_LIMIT1 0x39 | ||
113 | #define BRIDGE_PCIEMEM_LIMIT2 0x3a | ||
114 | #define BRIDGE_PCIEMEM_LIMIT3 0x3b | ||
115 | #define BRIDGE_PCIEIO_BASE0 0x3c | ||
116 | #define BRIDGE_PCIEIO_BASE1 0x3d | ||
117 | #define BRIDGE_PCIEIO_BASE2 0x3e | ||
118 | #define BRIDGE_PCIEIO_BASE3 0x3f | ||
119 | #define BRIDGE_PCIEIO_LIMIT0 0x40 | ||
120 | #define BRIDGE_PCIEIO_LIMIT1 0x41 | ||
121 | #define BRIDGE_PCIEIO_LIMIT2 0x42 | ||
122 | #define BRIDGE_PCIEIO_LIMIT3 0x43 | ||
123 | #define BRIDGE_PCIEMEM_BASE4 0x44 | ||
124 | #define BRIDGE_PCIEMEM_BASE5 0x45 | ||
125 | #define BRIDGE_PCIEMEM_BASE6 0x46 | ||
126 | #define BRIDGE_PCIEMEM_LIMIT4 0x47 | ||
127 | #define BRIDGE_PCIEMEM_LIMIT5 0x48 | ||
128 | #define BRIDGE_PCIEMEM_LIMIT6 0x49 | ||
129 | #define BRIDGE_PCIEIO_BASE4 0x4a | ||
130 | #define BRIDGE_PCIEIO_BASE5 0x4b | ||
131 | #define BRIDGE_PCIEIO_BASE6 0x4c | ||
132 | #define BRIDGE_PCIEIO_LIMIT4 0x4d | ||
133 | #define BRIDGE_PCIEIO_LIMIT5 0x4e | ||
134 | #define BRIDGE_PCIEIO_LIMIT6 0x4f | ||
135 | #define BRIDGE_NBU_EVENT_CNT_CTL 0x50 | ||
136 | #define BRIDGE_EVNTCTR1_LOW 0x51 | ||
137 | #define BRIDGE_EVNTCTR1_HI 0x52 | ||
138 | #define BRIDGE_EVNT_CNT_CTL2 0x53 | ||
139 | #define BRIDGE_EVNTCTR2_LOW 0x54 | ||
140 | #define BRIDGE_EVNTCTR2_HI 0x55 | ||
141 | #define BRIDGE_TRACEBUF_MATCH0 0x56 | ||
142 | #define BRIDGE_TRACEBUF_MATCH1 0x57 | ||
143 | #define BRIDGE_TRACEBUF_MATCH_LOW 0x58 | ||
144 | #define BRIDGE_TRACEBUF_MATCH_HI 0x59 | ||
145 | #define BRIDGE_TRACEBUF_CTRL 0x5a | ||
146 | #define BRIDGE_TRACEBUF_INIT 0x5b | ||
147 | #define BRIDGE_TRACEBUF_ACCESS 0x5c | ||
148 | #define BRIDGE_TRACEBUF_READ_DATA0 0x5d | ||
149 | #define BRIDGE_TRACEBUF_READ_DATA1 0x5d | ||
150 | #define BRIDGE_TRACEBUF_READ_DATA2 0x5f | ||
151 | #define BRIDGE_TRACEBUF_READ_DATA3 0x60 | ||
152 | #define BRIDGE_TRACEBUF_STATUS 0x61 | ||
153 | #define BRIDGE_ADDRESS_ERROR0 0x62 | ||
154 | #define BRIDGE_ADDRESS_ERROR1 0x63 | ||
155 | #define BRIDGE_ADDRESS_ERROR2 0x64 | ||
156 | #define BRIDGE_TAG_ECC_ADDR_ERROR0 0x65 | ||
157 | #define BRIDGE_TAG_ECC_ADDR_ERROR1 0x66 | ||
158 | #define BRIDGE_TAG_ECC_ADDR_ERROR2 0x67 | ||
159 | #define BRIDGE_LINE_FLUSH0 0x68 | ||
160 | #define BRIDGE_LINE_FLUSH1 0x69 | ||
161 | #define BRIDGE_NODE_ID 0x6a | ||
162 | #define BRIDGE_ERROR_INTERRUPT_EN 0x6b | ||
163 | #define BRIDGE_PCIE0_WEIGHT 0x2c0 | ||
164 | #define BRIDGE_PCIE1_WEIGHT 0x2c1 | ||
165 | #define BRIDGE_PCIE2_WEIGHT 0x2c2 | ||
166 | #define BRIDGE_PCIE3_WEIGHT 0x2c3 | ||
167 | #define BRIDGE_USB_WEIGHT 0x2c4 | ||
168 | #define BRIDGE_NET_WEIGHT 0x2c5 | ||
169 | #define BRIDGE_POE_WEIGHT 0x2c6 | ||
170 | #define BRIDGE_CMS_WEIGHT 0x2c7 | ||
171 | #define BRIDGE_DMAENG_WEIGHT 0x2c8 | ||
172 | #define BRIDGE_SEC_WEIGHT 0x2c9 | ||
173 | #define BRIDGE_COMP_WEIGHT 0x2ca | ||
174 | #define BRIDGE_GIO_WEIGHT 0x2cb | ||
175 | #define BRIDGE_FLASH_WEIGHT 0x2cc | ||
176 | |||
177 | #ifndef __ASSEMBLY__ | ||
178 | |||
179 | #define nlm_read_bridge_reg(b, r) nlm_read_reg(b, r) | ||
180 | #define nlm_write_bridge_reg(b, r, v) nlm_write_reg(b, r, v) | ||
181 | #define nlm_get_bridge_pcibase(node) \ | ||
182 | nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node)) | ||
183 | #define nlm_get_bridge_regbase(node) \ | ||
184 | (nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ) | ||
185 | |||
186 | #endif /* __ASSEMBLY__ */ | ||
187 | #endif /* __NLM_HAL_BRIDGE_H__ */ | ||
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h b/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h deleted file mode 100644 index 7b63a6b722a..00000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/cpucontrol.h +++ /dev/null | |||
@@ -1,85 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | ||
3 | * reserved. | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the NetLogic | ||
9 | * license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or without | ||
12 | * modification, are permitted provided that the following conditions | ||
13 | * are met: | ||
14 | * | ||
15 | * 1. Redistributions of source code must retain the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer. | ||
17 | * 2. Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in | ||
19 | * the documentation and/or other materials provided with the | ||
20 | * distribution. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | ||
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | ||
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef __NLM_HAL_CPUCONTROL_H__ | ||
36 | #define __NLM_HAL_CPUCONTROL_H__ | ||
37 | |||
38 | #define CPU_BLOCKID_IFU 0 | ||
39 | #define CPU_BLOCKID_ICU 1 | ||
40 | #define CPU_BLOCKID_IEU 2 | ||
41 | #define CPU_BLOCKID_LSU 3 | ||
42 | #define CPU_BLOCKID_MMU 4 | ||
43 | #define CPU_BLOCKID_PRF 5 | ||
44 | #define CPU_BLOCKID_SCH 7 | ||
45 | #define CPU_BLOCKID_SCU 8 | ||
46 | #define CPU_BLOCKID_FPU 9 | ||
47 | #define CPU_BLOCKID_MAP 10 | ||
48 | |||
49 | #define LSU_DEFEATURE 0x304 | ||
50 | #define LSU_DEBUG_ADDR 0x305 | ||
51 | #define LSU_DEBUG_DATA0 0x306 | ||
52 | #define LSU_CERRLOG_REGID 0x309 | ||
53 | #define SCHED_DEFEATURE 0x700 | ||
54 | |||
55 | /* Offsets of interest from the 'MAP' Block */ | ||
56 | #define MAP_THREADMODE 0x00 | ||
57 | #define MAP_EXT_EBASE_ENABLE 0x04 | ||
58 | #define MAP_CCDI_CONFIG 0x08 | ||
59 | #define MAP_THRD0_CCDI_STATUS 0x0c | ||
60 | #define MAP_THRD1_CCDI_STATUS 0x10 | ||
61 | #define MAP_THRD2_CCDI_STATUS 0x14 | ||
62 | #define MAP_THRD3_CCDI_STATUS 0x18 | ||
63 | #define MAP_THRD0_DEBUG_MODE 0x1c | ||
64 | #define MAP_THRD1_DEBUG_MODE 0x20 | ||
65 | #define MAP_THRD2_DEBUG_MODE 0x24 | ||
66 | #define MAP_THRD3_DEBUG_MODE 0x28 | ||
67 | #define MAP_MISC_STATE 0x60 | ||
68 | #define MAP_DEBUG_READ_CTL 0x64 | ||
69 | #define MAP_DEBUG_READ_REG0 0x68 | ||
70 | #define MAP_DEBUG_READ_REG1 0x6c | ||
71 | |||
72 | #define MMU_SETUP 0x400 | ||
73 | #define MMU_LFSRSEED 0x401 | ||
74 | #define MMU_HPW_NUM_PAGE_LVL 0x410 | ||
75 | #define MMU_PGWKR_PGDBASE 0x411 | ||
76 | #define MMU_PGWKR_PGDSHFT 0x412 | ||
77 | #define MMU_PGWKR_PGDMASK 0x413 | ||
78 | #define MMU_PGWKR_PUDSHFT 0x414 | ||
79 | #define MMU_PGWKR_PUDMASK 0x415 | ||
80 | #define MMU_PGWKR_PMDSHFT 0x416 | ||
81 | #define MMU_PGWKR_PMDMASK 0x417 | ||
82 | #define MMU_PGWKR_PTESHFT 0x418 | ||
83 | #define MMU_PGWKR_PTEMASK 0x419 | ||
84 | |||
85 | #endif /* __NLM_CPUCONTROL_H__ */ | ||
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h b/arch/mips/include/asm/netlogic/xlp-hal/iomap.h deleted file mode 100644 index 2c63f975464..00000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/iomap.h +++ /dev/null | |||
@@ -1,156 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | ||
3 | * reserved. | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the NetLogic | ||
9 | * license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or without | ||
12 | * modification, are permitted provided that the following conditions | ||
13 | * are met: | ||
14 | * | ||
15 | * 1. Redistributions of source code must retain the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer. | ||
17 | * 2. Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in | ||
19 | * the documentation and/or other materials provided with the | ||
20 | * distribution. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | ||
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | ||
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef __NLM_HAL_IOMAP_H__ | ||
36 | #define __NLM_HAL_IOMAP_H__ | ||
37 | |||
38 | #define XLP_DEFAULT_IO_BASE 0x18000000 | ||
39 | #define XLP_DEFAULT_PCI_ECFG_BASE XLP_DEFAULT_IO_BASE | ||
40 | #define XLP_DEFAULT_PCI_CFG_BASE 0x1c000000 | ||
41 | |||
42 | #define NMI_BASE 0xbfc00000 | ||
43 | #define XLP_IO_CLK 133333333 | ||
44 | |||
45 | #define XLP_PCIE_CFG_SIZE 0x1000 /* 4K */ | ||
46 | #define XLP_PCIE_DEV_BLK_SIZE (8 * XLP_PCIE_CFG_SIZE) | ||
47 | #define XLP_PCIE_BUS_BLK_SIZE (256 * XLP_PCIE_DEV_BLK_SIZE) | ||
48 | #define XLP_IO_SIZE (64 << 20) /* ECFG space size */ | ||
49 | #define XLP_IO_PCI_HDRSZ 0x100 | ||
50 | #define XLP_IO_DEV(node, dev) ((dev) + (node) * 8) | ||
51 | #define XLP_HDR_OFFSET(node, bus, dev, fn) (((bus) << 20) | \ | ||
52 | ((XLP_IO_DEV(node, dev)) << 15) | ((fn) << 12)) | ||
53 | |||
54 | #define XLP_IO_BRIDGE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 0) | ||
55 | /* coherent inter chip */ | ||
56 | #define XLP_IO_CIC0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 1) | ||
57 | #define XLP_IO_CIC1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 2) | ||
58 | #define XLP_IO_CIC2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 3) | ||
59 | #define XLP_IO_PIC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 0, 4) | ||
60 | |||
61 | #define XLP_IO_PCIE_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 1, i) | ||
62 | #define XLP_IO_PCIE0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 0) | ||
63 | #define XLP_IO_PCIE1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 1) | ||
64 | #define XLP_IO_PCIE2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 2) | ||
65 | #define XLP_IO_PCIE3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 1, 3) | ||
66 | |||
67 | #define XLP_IO_USB_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 2, i) | ||
68 | #define XLP_IO_USB_EHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 0) | ||
69 | #define XLP_IO_USB_OHCI0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 1) | ||
70 | #define XLP_IO_USB_OHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 2) | ||
71 | #define XLP_IO_USB_EHCI1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 3) | ||
72 | #define XLP_IO_USB_OHCI2_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 4) | ||
73 | #define XLP_IO_USB_OHCI3_OFFSET(node) XLP_HDR_OFFSET(node, 0, 2, 5) | ||
74 | |||
75 | #define XLP_IO_NAE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 0) | ||
76 | #define XLP_IO_POE_OFFSET(node) XLP_HDR_OFFSET(node, 0, 3, 1) | ||
77 | |||
78 | #define XLP_IO_CMS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 4, 0) | ||
79 | |||
80 | #define XLP_IO_DMA_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 1) | ||
81 | #define XLP_IO_SEC_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 2) | ||
82 | #define XLP_IO_CMP_OFFSET(node) XLP_HDR_OFFSET(node, 0, 5, 3) | ||
83 | |||
84 | #define XLP_IO_UART_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, i) | ||
85 | #define XLP_IO_UART0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 0) | ||
86 | #define XLP_IO_UART1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 1) | ||
87 | #define XLP_IO_I2C_OFFSET(node, i) XLP_HDR_OFFSET(node, 0, 6, 2 + i) | ||
88 | #define XLP_IO_I2C0_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 2) | ||
89 | #define XLP_IO_I2C1_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 3) | ||
90 | #define XLP_IO_GPIO_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 4) | ||
91 | /* system management */ | ||
92 | #define XLP_IO_SYS_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 5) | ||
93 | #define XLP_IO_JTAG_OFFSET(node) XLP_HDR_OFFSET(node, 0, 6, 6) | ||
94 | |||
95 | #define XLP_IO_NOR_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 0) | ||
96 | #define XLP_IO_NAND_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 1) | ||
97 | #define XLP_IO_SPI_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 2) | ||
98 | /* SD flash */ | ||
99 | #define XLP_IO_SD_OFFSET(node) XLP_HDR_OFFSET(node, 0, 7, 3) | ||
100 | #define XLP_IO_MMC_OFFSET(node, slot) \ | ||
101 | ((XLP_IO_SD_OFFSET(node))+(slot*0x100)+XLP_IO_PCI_HDRSZ) | ||
102 | |||
103 | /* PCI config header register id's */ | ||
104 | #define XLP_PCI_CFGREG0 0x00 | ||
105 | #define XLP_PCI_CFGREG1 0x01 | ||
106 | #define XLP_PCI_CFGREG2 0x02 | ||
107 | #define XLP_PCI_CFGREG3 0x03 | ||
108 | #define XLP_PCI_CFGREG4 0x04 | ||
109 | #define XLP_PCI_CFGREG5 0x05 | ||
110 | #define XLP_PCI_DEVINFO_REG0 0x30 | ||
111 | #define XLP_PCI_DEVINFO_REG1 0x31 | ||
112 | #define XLP_PCI_DEVINFO_REG2 0x32 | ||
113 | #define XLP_PCI_DEVINFO_REG3 0x33 | ||
114 | #define XLP_PCI_DEVINFO_REG4 0x34 | ||
115 | #define XLP_PCI_DEVINFO_REG5 0x35 | ||
116 | #define XLP_PCI_DEVINFO_REG6 0x36 | ||
117 | #define XLP_PCI_DEVINFO_REG7 0x37 | ||
118 | #define XLP_PCI_DEVSCRATCH_REG0 0x38 | ||
119 | #define XLP_PCI_DEVSCRATCH_REG1 0x39 | ||
120 | #define XLP_PCI_DEVSCRATCH_REG2 0x3a | ||
121 | #define XLP_PCI_DEVSCRATCH_REG3 0x3b | ||
122 | #define XLP_PCI_MSGSTN_REG 0x3c | ||
123 | #define XLP_PCI_IRTINFO_REG 0x3d | ||
124 | #define XLP_PCI_UCODEINFO_REG 0x3e | ||
125 | #define XLP_PCI_SBB_WT_REG 0x3f | ||
126 | |||
127 | /* PCI IDs for SoC device */ | ||
128 | #define PCI_VENDOR_NETLOGIC 0x184e | ||
129 | |||
130 | #define PCI_DEVICE_ID_NLM_ROOT 0x1001 | ||
131 | #define PCI_DEVICE_ID_NLM_ICI 0x1002 | ||
132 | #define PCI_DEVICE_ID_NLM_PIC 0x1003 | ||
133 | #define PCI_DEVICE_ID_NLM_PCIE 0x1004 | ||
134 | #define PCI_DEVICE_ID_NLM_EHCI 0x1007 | ||
135 | #define PCI_DEVICE_ID_NLM_OHCI 0x1008 | ||
136 | #define PCI_DEVICE_ID_NLM_NAE 0x1009 | ||
137 | #define PCI_DEVICE_ID_NLM_POE 0x100A | ||
138 | #define PCI_DEVICE_ID_NLM_FMN 0x100B | ||
139 | #define PCI_DEVICE_ID_NLM_RAID 0x100D | ||
140 | #define PCI_DEVICE_ID_NLM_SAE 0x100D | ||
141 | #define PCI_DEVICE_ID_NLM_RSA 0x100E | ||
142 | #define PCI_DEVICE_ID_NLM_CMP 0x100F | ||
143 | #define PCI_DEVICE_ID_NLM_UART 0x1010 | ||
144 | #define PCI_DEVICE_ID_NLM_I2C 0x1011 | ||
145 | #define PCI_DEVICE_ID_NLM_NOR 0x1015 | ||
146 | #define PCI_DEVICE_ID_NLM_NAND 0x1016 | ||
147 | #define PCI_DEVICE_ID_NLM_MMC 0x1018 | ||
148 | |||
149 | #ifndef __ASSEMBLY__ | ||
150 | |||
151 | #define nlm_read_pci_reg(b, r) nlm_read_reg(b, r) | ||
152 | #define nlm_write_pci_reg(b, r, v) nlm_write_reg(b, r, v) | ||
153 | |||
154 | #endif /* !__ASSEMBLY */ | ||
155 | |||
156 | #endif /* __NLM_HAL_IOMAP_H__ */ | ||
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h b/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h deleted file mode 100644 index 66c323d1bd7..00000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/pcibus.h +++ /dev/null | |||
@@ -1,76 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2003-2012 Broadcom Corporation | ||
3 | * All Rights Reserved | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the Broadcom | ||
9 | * license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or without | ||
12 | * modification, are permitted provided that the following conditions | ||
13 | * are met: | ||
14 | * | ||
15 | * 1. Redistributions of source code must retain the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer. | ||
17 | * 2. Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in | ||
19 | * the documentation and/or other materials provided with the | ||
20 | * distribution. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR | ||
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE | ||
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef __NLM_HAL_PCIBUS_H__ | ||
36 | #define __NLM_HAL_PCIBUS_H__ | ||
37 | |||
38 | /* PCIE Memory and IO regions */ | ||
39 | #define PCIE_MEM_BASE 0xd0000000ULL | ||
40 | #define PCIE_MEM_LIMIT 0xdfffffffULL | ||
41 | #define PCIE_IO_BASE 0x14000000ULL | ||
42 | #define PCIE_IO_LIMIT 0x15ffffffULL | ||
43 | |||
44 | #define PCIE_BRIDGE_CMD 0x1 | ||
45 | #define PCIE_BRIDGE_MSI_CAP 0x14 | ||
46 | #define PCIE_BRIDGE_MSI_ADDRL 0x15 | ||
47 | #define PCIE_BRIDGE_MSI_ADDRH 0x16 | ||
48 | #define PCIE_BRIDGE_MSI_DATA 0x17 | ||
49 | |||
50 | /* XLP Global PCIE configuration space registers */ | ||
51 | #define PCIE_BYTE_SWAP_MEM_BASE 0x247 | ||
52 | #define PCIE_BYTE_SWAP_MEM_LIM 0x248 | ||
53 | #define PCIE_BYTE_SWAP_IO_BASE 0x249 | ||
54 | #define PCIE_BYTE_SWAP_IO_LIM 0x24A | ||
55 | #define PCIE_MSI_STATUS 0x25A | ||
56 | #define PCIE_MSI_EN 0x25B | ||
57 | #define PCIE_INT_EN0 0x261 | ||
58 | |||
59 | /* PCIE_MSI_EN */ | ||
60 | #define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF | ||
61 | |||
62 | /* PCIE_INT_EN0 */ | ||
63 | #define PCIE_MSI_INT_EN (1 << 9) | ||
64 | |||
65 | #ifndef __ASSEMBLY__ | ||
66 | |||
67 | #define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r) | ||
68 | #define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v) | ||
69 | #define nlm_get_pcie_base(node, inst) \ | ||
70 | nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst)) | ||
71 | #define nlm_get_pcie_regbase(node, inst) \ | ||
72 | (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ) | ||
73 | |||
74 | int xlp_pcie_link_irt(int link); | ||
75 | #endif | ||
76 | #endif /* __NLM_HAL_PCIBUS_H__ */ | ||
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/pic.h b/arch/mips/include/asm/netlogic/xlp-hal/pic.h deleted file mode 100644 index b2e53a5383a..00000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/pic.h +++ /dev/null | |||
@@ -1,387 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | ||
3 | * reserved. | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the NetLogic | ||
9 | * license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or without | ||
12 | * modification, are permitted provided that the following conditions | ||
13 | * are met: | ||
14 | * | ||
15 | * 1. Redistributions of source code must retain the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer. | ||
17 | * 2. Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in | ||
19 | * the documentation and/or other materials provided with the | ||
20 | * distribution. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | ||
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | ||
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef _NLM_HAL_PIC_H | ||
36 | #define _NLM_HAL_PIC_H | ||
37 | |||
38 | /* PIC Specific registers */ | ||
39 | #define PIC_CTRL 0x00 | ||
40 | |||
41 | /* PIC control register defines */ | ||
42 | #define PIC_CTRL_ITV 32 /* interrupt timeout value */ | ||
43 | #define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */ | ||
44 | #define PIC_CTRL_ITE 18 /* interrupt timeout enable */ | ||
45 | #define PIC_CTRL_STE 10 /* system timer interrupt enable */ | ||
46 | #define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */ | ||
47 | #define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */ | ||
48 | #define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */ | ||
49 | #define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */ | ||
50 | #define PIC_CTRL_WTE 0 /* watchdog timer enable */ | ||
51 | |||
52 | /* PIC Status register defines */ | ||
53 | #define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */ | ||
54 | #define PIC_ITE_STATUS 32 /* interrupt timeout status */ | ||
55 | #define PIC_STS_STATUS 4 /* System timer interrupt status */ | ||
56 | #define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */ | ||
57 | #define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */ | ||
58 | |||
59 | /* PIC IPI control register offsets */ | ||
60 | #define PIC_IPICTRL_NMI 32 | ||
61 | #define PIC_IPICTRL_RIV 20 /* received interrupt vector */ | ||
62 | #define PIC_IPICTRL_IDB 16 /* interrupt destination base */ | ||
63 | #define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */ | ||
64 | |||
65 | /* PIC IRT register offsets */ | ||
66 | #define PIC_IRT_ENABLE 31 | ||
67 | #define PIC_IRT_NMI 29 | ||
68 | #define PIC_IRT_SCH 28 /* Scheduling scheme */ | ||
69 | #define PIC_IRT_RVEC 20 /* Interrupt receive vectors */ | ||
70 | #define PIC_IRT_DT 19 /* Destination type */ | ||
71 | #define PIC_IRT_DB 16 /* Destination base */ | ||
72 | #define PIC_IRT_DTE 0 /* Destination thread enables */ | ||
73 | |||
74 | #define PIC_BYTESWAP 0x02 | ||
75 | #define PIC_STATUS 0x04 | ||
76 | #define PIC_INTR_TIMEOUT 0x06 | ||
77 | #define PIC_ICI0_INTR_TIMEOUT 0x08 | ||
78 | #define PIC_ICI1_INTR_TIMEOUT 0x0a | ||
79 | #define PIC_ICI2_INTR_TIMEOUT 0x0c | ||
80 | #define PIC_IPI_CTL 0x0e | ||
81 | #define PIC_INT_ACK 0x10 | ||
82 | #define PIC_INT_PENDING0 0x12 | ||
83 | #define PIC_INT_PENDING1 0x14 | ||
84 | #define PIC_INT_PENDING2 0x16 | ||
85 | |||
86 | #define PIC_WDOG0_MAXVAL 0x18 | ||
87 | #define PIC_WDOG0_COUNT 0x1a | ||
88 | #define PIC_WDOG0_ENABLE0 0x1c | ||
89 | #define PIC_WDOG0_ENABLE1 0x1e | ||
90 | #define PIC_WDOG0_BEATCMD 0x20 | ||
91 | #define PIC_WDOG0_BEAT0 0x22 | ||
92 | #define PIC_WDOG0_BEAT1 0x24 | ||
93 | |||
94 | #define PIC_WDOG1_MAXVAL 0x26 | ||
95 | #define PIC_WDOG1_COUNT 0x28 | ||
96 | #define PIC_WDOG1_ENABLE0 0x2a | ||
97 | #define PIC_WDOG1_ENABLE1 0x2c | ||
98 | #define PIC_WDOG1_BEATCMD 0x2e | ||
99 | #define PIC_WDOG1_BEAT0 0x30 | ||
100 | #define PIC_WDOG1_BEAT1 0x32 | ||
101 | |||
102 | #define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0)) | ||
103 | #define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0)) | ||
104 | #define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0)) | ||
105 | #define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0)) | ||
106 | #define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0)) | ||
107 | #define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0)) | ||
108 | #define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0)) | ||
109 | |||
110 | #define PIC_TIMER0_MAXVAL 0x34 | ||
111 | #define PIC_TIMER1_MAXVAL 0x36 | ||
112 | #define PIC_TIMER2_MAXVAL 0x38 | ||
113 | #define PIC_TIMER3_MAXVAL 0x3a | ||
114 | #define PIC_TIMER4_MAXVAL 0x3c | ||
115 | #define PIC_TIMER5_MAXVAL 0x3e | ||
116 | #define PIC_TIMER6_MAXVAL 0x40 | ||
117 | #define PIC_TIMER7_MAXVAL 0x42 | ||
118 | #define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2)) | ||
119 | |||
120 | #define PIC_TIMER0_COUNT 0x44 | ||
121 | #define PIC_TIMER1_COUNT 0x46 | ||
122 | #define PIC_TIMER2_COUNT 0x48 | ||
123 | #define PIC_TIMER3_COUNT 0x4a | ||
124 | #define PIC_TIMER4_COUNT 0x4c | ||
125 | #define PIC_TIMER5_COUNT 0x4e | ||
126 | #define PIC_TIMER6_COUNT 0x50 | ||
127 | #define PIC_TIMER7_COUNT 0x52 | ||
128 | #define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2)) | ||
129 | |||
130 | #define PIC_ITE0_N0_N1 0x54 | ||
131 | #define PIC_ITE1_N0_N1 0x58 | ||
132 | #define PIC_ITE2_N0_N1 0x5c | ||
133 | #define PIC_ITE3_N0_N1 0x60 | ||
134 | #define PIC_ITE4_N0_N1 0x64 | ||
135 | #define PIC_ITE5_N0_N1 0x68 | ||
136 | #define PIC_ITE6_N0_N1 0x6c | ||
137 | #define PIC_ITE7_N0_N1 0x70 | ||
138 | #define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4)) | ||
139 | |||
140 | #define PIC_ITE0_N2_N3 0x56 | ||
141 | #define PIC_ITE1_N2_N3 0x5a | ||
142 | #define PIC_ITE2_N2_N3 0x5e | ||
143 | #define PIC_ITE3_N2_N3 0x62 | ||
144 | #define PIC_ITE4_N2_N3 0x66 | ||
145 | #define PIC_ITE5_N2_N3 0x6a | ||
146 | #define PIC_ITE6_N2_N3 0x6e | ||
147 | #define PIC_ITE7_N2_N3 0x72 | ||
148 | #define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4)) | ||
149 | |||
150 | #define PIC_IRT0 0x74 | ||
151 | #define PIC_IRT(i) (PIC_IRT0 + ((i) * 2)) | ||
152 | |||
153 | #define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL | ||
154 | |||
155 | /* | ||
156 | * IRT Map | ||
157 | */ | ||
158 | #define PIC_NUM_IRTS 160 | ||
159 | |||
160 | #define PIC_IRT_WD_0_INDEX 0 | ||
161 | #define PIC_IRT_WD_1_INDEX 1 | ||
162 | #define PIC_IRT_WD_NMI_0_INDEX 2 | ||
163 | #define PIC_IRT_WD_NMI_1_INDEX 3 | ||
164 | #define PIC_IRT_TIMER_0_INDEX 4 | ||
165 | #define PIC_IRT_TIMER_1_INDEX 5 | ||
166 | #define PIC_IRT_TIMER_2_INDEX 6 | ||
167 | #define PIC_IRT_TIMER_3_INDEX 7 | ||
168 | #define PIC_IRT_TIMER_4_INDEX 8 | ||
169 | #define PIC_IRT_TIMER_5_INDEX 9 | ||
170 | #define PIC_IRT_TIMER_6_INDEX 10 | ||
171 | #define PIC_IRT_TIMER_7_INDEX 11 | ||
172 | #define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX | ||
173 | #define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX) | ||
174 | |||
175 | |||
176 | /* 11 and 12 */ | ||
177 | #define PIC_NUM_MSG_Q_IRTS 32 | ||
178 | #define PIC_IRT_MSG_Q0_INDEX 12 | ||
179 | #define PIC_IRT_MSG_Q_INDEX(qid) ((qid) + PIC_IRT_MSG_Q0_INDEX) | ||
180 | /* 12 to 43 */ | ||
181 | #define PIC_IRT_MSG_0_INDEX 44 | ||
182 | #define PIC_IRT_MSG_1_INDEX 45 | ||
183 | /* 44 and 45 */ | ||
184 | #define PIC_NUM_PCIE_MSIX_IRTS 32 | ||
185 | #define PIC_IRT_PCIE_MSIX_0_INDEX 46 | ||
186 | #define PIC_IRT_PCIE_MSIX_INDEX(num) ((num) + PIC_IRT_PCIE_MSIX_0_INDEX) | ||
187 | /* 46 to 77 */ | ||
188 | #define PIC_NUM_PCIE_LINK_IRTS 4 | ||
189 | #define PIC_IRT_PCIE_LINK_0_INDEX 78 | ||
190 | #define PIC_IRT_PCIE_LINK_1_INDEX 79 | ||
191 | #define PIC_IRT_PCIE_LINK_2_INDEX 80 | ||
192 | #define PIC_IRT_PCIE_LINK_3_INDEX 81 | ||
193 | #define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX) | ||
194 | /* 78 to 81 */ | ||
195 | #define PIC_NUM_NA_IRTS 32 | ||
196 | /* 82 to 113 */ | ||
197 | #define PIC_IRT_NA_0_INDEX 82 | ||
198 | #define PIC_IRT_NA_INDEX(num) ((num) + PIC_IRT_NA_0_INDEX) | ||
199 | #define PIC_IRT_POE_INDEX 114 | ||
200 | |||
201 | #define PIC_NUM_USB_IRTS 6 | ||
202 | #define PIC_IRT_USB_0_INDEX 115 | ||
203 | #define PIC_IRT_EHCI_0_INDEX 115 | ||
204 | #define PIC_IRT_OHCI_0_INDEX 116 | ||
205 | #define PIC_IRT_OHCI_1_INDEX 117 | ||
206 | #define PIC_IRT_EHCI_1_INDEX 118 | ||
207 | #define PIC_IRT_OHCI_2_INDEX 119 | ||
208 | #define PIC_IRT_OHCI_3_INDEX 120 | ||
209 | #define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX) | ||
210 | /* 115 to 120 */ | ||
211 | #define PIC_IRT_GDX_INDEX 121 | ||
212 | #define PIC_IRT_SEC_INDEX 122 | ||
213 | #define PIC_IRT_RSA_INDEX 123 | ||
214 | |||
215 | #define PIC_NUM_COMP_IRTS 4 | ||
216 | #define PIC_IRT_COMP_0_INDEX 124 | ||
217 | #define PIC_IRT_COMP_INDEX(num) ((num) + PIC_IRT_COMP_0_INDEX) | ||
218 | /* 124 to 127 */ | ||
219 | #define PIC_IRT_GBU_INDEX 128 | ||
220 | #define PIC_IRT_ICC_0_INDEX 129 /* ICC - Inter Chip Coherency */ | ||
221 | #define PIC_IRT_ICC_1_INDEX 130 | ||
222 | #define PIC_IRT_ICC_2_INDEX 131 | ||
223 | #define PIC_IRT_CAM_INDEX 132 | ||
224 | #define PIC_IRT_UART_0_INDEX 133 | ||
225 | #define PIC_IRT_UART_1_INDEX 134 | ||
226 | #define PIC_IRT_I2C_0_INDEX 135 | ||
227 | #define PIC_IRT_I2C_1_INDEX 136 | ||
228 | #define PIC_IRT_SYS_0_INDEX 137 | ||
229 | #define PIC_IRT_SYS_1_INDEX 138 | ||
230 | #define PIC_IRT_JTAG_INDEX 139 | ||
231 | #define PIC_IRT_PIC_INDEX 140 | ||
232 | #define PIC_IRT_NBU_INDEX 141 | ||
233 | #define PIC_IRT_TCU_INDEX 142 | ||
234 | #define PIC_IRT_GCU_INDEX 143 /* GBC - Global Coherency */ | ||
235 | #define PIC_IRT_DMC_0_INDEX 144 | ||
236 | #define PIC_IRT_DMC_1_INDEX 145 | ||
237 | |||
238 | #define PIC_NUM_GPIO_IRTS 4 | ||
239 | #define PIC_IRT_GPIO_0_INDEX 146 | ||
240 | #define PIC_IRT_GPIO_INDEX(num) ((num) + PIC_IRT_GPIO_0_INDEX) | ||
241 | |||
242 | /* 146 to 149 */ | ||
243 | #define PIC_IRT_NOR_INDEX 150 | ||
244 | #define PIC_IRT_NAND_INDEX 151 | ||
245 | #define PIC_IRT_SPI_INDEX 152 | ||
246 | #define PIC_IRT_MMC_INDEX 153 | ||
247 | |||
248 | #define PIC_CLOCK_TIMER 7 | ||
249 | #define PIC_IRQ_BASE 8 | ||
250 | |||
251 | #if !defined(LOCORE) && !defined(__ASSEMBLY__) | ||
252 | |||
253 | #define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE) | ||
254 | #define PIC_IRT_LAST_IRQ 63 | ||
255 | #define PIC_IRQ_IS_IRT(irq) ((irq) >= PIC_IRT_FIRST_IRQ) | ||
256 | |||
257 | /* | ||
258 | * Misc | ||
259 | */ | ||
260 | #define PIC_IRT_VALID 1 | ||
261 | #define PIC_LOCAL_SCHEDULING 1 | ||
262 | #define PIC_GLOBAL_SCHEDULING 0 | ||
263 | |||
264 | #define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) | ||
265 | #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) | ||
266 | #define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) | ||
267 | #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) | ||
268 | |||
269 | /* IRT and h/w interrupt routines */ | ||
270 | static inline int | ||
271 | nlm_pic_read_irt(uint64_t base, int irt_index) | ||
272 | { | ||
273 | return nlm_read_pic_reg(base, PIC_IRT(irt_index)); | ||
274 | } | ||
275 | |||
276 | static inline void | ||
277 | nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu) | ||
278 | { | ||
279 | uint64_t val; | ||
280 | |||
281 | val = nlm_read_pic_reg(base, PIC_IRT(irt)); | ||
282 | /* clear cpuset and mask */ | ||
283 | val &= ~((0x7ull << 16) | 0xffff); | ||
284 | /* set DB, cpuset and cpumask */ | ||
285 | val |= (1 << 19) | ((cpu >> 4) << 16) | (1 << (cpu & 0xf)); | ||
286 | nlm_write_pic_reg(base, PIC_IRT(irt), val); | ||
287 | } | ||
288 | |||
289 | static inline void | ||
290 | nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, | ||
291 | int sch, int vec, int dt, int db, int dte) | ||
292 | { | ||
293 | uint64_t val; | ||
294 | |||
295 | val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) | | ||
296 | ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) | | ||
297 | ((dt & 0x1) << 19) | ((db & 0x7) << 16) | | ||
298 | (dte & 0xffff); | ||
299 | |||
300 | nlm_write_pic_reg(base, PIC_IRT(irt_num), val); | ||
301 | } | ||
302 | |||
303 | static inline void | ||
304 | nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, | ||
305 | int sch, int vec, int cpu) | ||
306 | { | ||
307 | nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, | ||
308 | (cpu >> 4), /* thread group */ | ||
309 | 1 << (cpu & 0xf)); /* thread mask */ | ||
310 | } | ||
311 | |||
312 | static inline uint64_t | ||
313 | nlm_pic_read_timer(uint64_t base, int timer) | ||
314 | { | ||
315 | return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); | ||
316 | } | ||
317 | |||
318 | static inline void | ||
319 | nlm_pic_write_timer(uint64_t base, int timer, uint64_t value) | ||
320 | { | ||
321 | nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value); | ||
322 | } | ||
323 | |||
324 | static inline void | ||
325 | nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) | ||
326 | { | ||
327 | uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL); | ||
328 | int en; | ||
329 | |||
330 | en = (irq > 0); | ||
331 | nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value); | ||
332 | nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer), | ||
333 | en, 0, 0, irq, cpu); | ||
334 | |||
335 | /* enable the timer */ | ||
336 | pic_ctrl |= (1 << (PIC_CTRL_STE + timer)); | ||
337 | nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl); | ||
338 | } | ||
339 | |||
340 | static inline void | ||
341 | nlm_pic_enable_irt(uint64_t base, int irt) | ||
342 | { | ||
343 | uint64_t reg; | ||
344 | |||
345 | reg = nlm_read_pic_reg(base, PIC_IRT(irt)); | ||
346 | nlm_write_pic_reg(base, PIC_IRT(irt), reg | (1u << 31)); | ||
347 | } | ||
348 | |||
349 | static inline void | ||
350 | nlm_pic_disable_irt(uint64_t base, int irt) | ||
351 | { | ||
352 | uint64_t reg; | ||
353 | |||
354 | reg = nlm_read_pic_reg(base, PIC_IRT(irt)); | ||
355 | nlm_write_pic_reg(base, PIC_IRT(irt), reg & ~((uint64_t)1 << 31)); | ||
356 | } | ||
357 | |||
358 | static inline void | ||
359 | nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) | ||
360 | { | ||
361 | uint64_t ipi; | ||
362 | |||
363 | ipi = (nmi << 31) | (irq << 20); | ||
364 | ipi |= ((hwt >> 4) << 16) | (1 << (hwt & 0xf)); /* cpuset and mask */ | ||
365 | nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); | ||
366 | } | ||
367 | |||
368 | static inline void | ||
369 | nlm_pic_ack(uint64_t base, int irt_num) | ||
370 | { | ||
371 | nlm_write_pic_reg(base, PIC_INT_ACK, irt_num); | ||
372 | |||
373 | /* Ack the Status register for Watchdog & System timers */ | ||
374 | if (irt_num < 12) | ||
375 | nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num)); | ||
376 | } | ||
377 | |||
378 | static inline void | ||
379 | nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt) | ||
380 | { | ||
381 | nlm_pic_write_irt_direct(base, irt, 0, 0, 0, irq, hwt); | ||
382 | } | ||
383 | |||
384 | int nlm_irq_to_irt(int irq); | ||
385 | |||
386 | #endif /* __ASSEMBLY__ */ | ||
387 | #endif /* _NLM_HAL_PIC_H */ | ||
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/sys.h b/arch/mips/include/asm/netlogic/xlp-hal/sys.h deleted file mode 100644 index 258e8cc00e9..00000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/sys.h +++ /dev/null | |||
@@ -1,128 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | ||
3 | * reserved. | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the NetLogic | ||
9 | * license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or without | ||
12 | * modification, are permitted provided that the following conditions | ||
13 | * are met: | ||
14 | * | ||
15 | * 1. Redistributions of source code must retain the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer. | ||
17 | * 2. Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in | ||
19 | * the documentation and/or other materials provided with the | ||
20 | * distribution. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | ||
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | ||
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef __NLM_HAL_SYS_H__ | ||
36 | #define __NLM_HAL_SYS_H__ | ||
37 | |||
38 | /** | ||
39 | * @file_name sys.h | ||
40 | * @author Netlogic Microsystems | ||
41 | * @brief HAL for System configuration registers | ||
42 | */ | ||
43 | #define SYS_CHIP_RESET 0x00 | ||
44 | #define SYS_POWER_ON_RESET_CFG 0x01 | ||
45 | #define SYS_EFUSE_DEVICE_CFG_STATUS0 0x02 | ||
46 | #define SYS_EFUSE_DEVICE_CFG_STATUS1 0x03 | ||
47 | #define SYS_EFUSE_DEVICE_CFG_STATUS2 0x04 | ||
48 | #define SYS_EFUSE_DEVICE_CFG3 0x05 | ||
49 | #define SYS_EFUSE_DEVICE_CFG4 0x06 | ||
50 | #define SYS_EFUSE_DEVICE_CFG5 0x07 | ||
51 | #define SYS_EFUSE_DEVICE_CFG6 0x08 | ||
52 | #define SYS_EFUSE_DEVICE_CFG7 0x09 | ||
53 | #define SYS_PLL_CTRL 0x0a | ||
54 | #define SYS_CPU_RESET 0x0b | ||
55 | #define SYS_CPU_NONCOHERENT_MODE 0x0d | ||
56 | #define SYS_CORE_DFS_DIS_CTRL 0x0e | ||
57 | #define SYS_CORE_DFS_RST_CTRL 0x0f | ||
58 | #define SYS_CORE_DFS_BYP_CTRL 0x10 | ||
59 | #define SYS_CORE_DFS_PHA_CTRL 0x11 | ||
60 | #define SYS_CORE_DFS_DIV_INC_CTRL 0x12 | ||
61 | #define SYS_CORE_DFS_DIV_DEC_CTRL 0x13 | ||
62 | #define SYS_CORE_DFS_DIV_VALUE 0x14 | ||
63 | #define SYS_RESET 0x15 | ||
64 | #define SYS_DFS_DIS_CTRL 0x16 | ||
65 | #define SYS_DFS_RST_CTRL 0x17 | ||
66 | #define SYS_DFS_BYP_CTRL 0x18 | ||
67 | #define SYS_DFS_DIV_INC_CTRL 0x19 | ||
68 | #define SYS_DFS_DIV_DEC_CTRL 0x1a | ||
69 | #define SYS_DFS_DIV_VALUE0 0x1b | ||
70 | #define SYS_DFS_DIV_VALUE1 0x1c | ||
71 | #define SYS_SENSE_AMP_DLY 0x1d | ||
72 | #define SYS_SOC_SENSE_AMP_DLY 0x1e | ||
73 | #define SYS_CTRL0 0x1f | ||
74 | #define SYS_CTRL1 0x20 | ||
75 | #define SYS_TIMEOUT_BS1 0x21 | ||
76 | #define SYS_BYTE_SWAP 0x22 | ||
77 | #define SYS_VRM_VID 0x23 | ||
78 | #define SYS_PWR_RAM_CMD 0x24 | ||
79 | #define SYS_PWR_RAM_ADDR 0x25 | ||
80 | #define SYS_PWR_RAM_DATA0 0x26 | ||
81 | #define SYS_PWR_RAM_DATA1 0x27 | ||
82 | #define SYS_PWR_RAM_DATA2 0x28 | ||
83 | #define SYS_PWR_UCODE 0x29 | ||
84 | #define SYS_CPU0_PWR_STATUS 0x2a | ||
85 | #define SYS_CPU1_PWR_STATUS 0x2b | ||
86 | #define SYS_CPU2_PWR_STATUS 0x2c | ||
87 | #define SYS_CPU3_PWR_STATUS 0x2d | ||
88 | #define SYS_CPU4_PWR_STATUS 0x2e | ||
89 | #define SYS_CPU5_PWR_STATUS 0x2f | ||
90 | #define SYS_CPU6_PWR_STATUS 0x30 | ||
91 | #define SYS_CPU7_PWR_STATUS 0x31 | ||
92 | #define SYS_STATUS 0x32 | ||
93 | #define SYS_INT_POL 0x33 | ||
94 | #define SYS_INT_TYPE 0x34 | ||
95 | #define SYS_INT_STATUS 0x35 | ||
96 | #define SYS_INT_MASK0 0x36 | ||
97 | #define SYS_INT_MASK1 0x37 | ||
98 | #define SYS_UCO_S_ECC 0x38 | ||
99 | #define SYS_UCO_M_ECC 0x39 | ||
100 | #define SYS_UCO_ADDR 0x3a | ||
101 | #define SYS_UCO_INSTR 0x3b | ||
102 | #define SYS_MEM_BIST0 0x3c | ||
103 | #define SYS_MEM_BIST1 0x3d | ||
104 | #define SYS_MEM_BIST2 0x3e | ||
105 | #define SYS_MEM_BIST3 0x3f | ||
106 | #define SYS_MEM_BIST4 0x40 | ||
107 | #define SYS_MEM_BIST5 0x41 | ||
108 | #define SYS_MEM_BIST6 0x42 | ||
109 | #define SYS_MEM_BIST7 0x43 | ||
110 | #define SYS_MEM_BIST8 0x44 | ||
111 | #define SYS_MEM_BIST9 0x45 | ||
112 | #define SYS_MEM_BIST10 0x46 | ||
113 | #define SYS_MEM_BIST11 0x47 | ||
114 | #define SYS_MEM_BIST12 0x48 | ||
115 | #define SYS_SCRTCH0 0x49 | ||
116 | #define SYS_SCRTCH1 0x4a | ||
117 | #define SYS_SCRTCH2 0x4b | ||
118 | #define SYS_SCRTCH3 0x4c | ||
119 | |||
120 | #ifndef __ASSEMBLY__ | ||
121 | |||
122 | #define nlm_read_sys_reg(b, r) nlm_read_reg(b, r) | ||
123 | #define nlm_write_sys_reg(b, r, v) nlm_write_reg(b, r, v) | ||
124 | #define nlm_get_sys_pcibase(node) nlm_pcicfg_base(XLP_IO_SYS_OFFSET(node)) | ||
125 | #define nlm_get_sys_regbase(node) (nlm_get_sys_pcibase(node) + XLP_IO_PCI_HDRSZ) | ||
126 | |||
127 | #endif | ||
128 | #endif | ||
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/uart.h b/arch/mips/include/asm/netlogic/xlp-hal/uart.h deleted file mode 100644 index 6a7046ca094..00000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/uart.h +++ /dev/null | |||
@@ -1,191 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | ||
3 | * reserved. | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the NetLogic | ||
9 | * license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or without | ||
12 | * modification, are permitted provided that the following conditions | ||
13 | * are met: | ||
14 | * | ||
15 | * 1. Redistributions of source code must retain the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer. | ||
17 | * 2. Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in | ||
19 | * the documentation and/or other materials provided with the | ||
20 | * distribution. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | ||
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | ||
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef __XLP_HAL_UART_H__ | ||
36 | #define __XLP_HAL_UART_H__ | ||
37 | |||
38 | /* UART Specific registers */ | ||
39 | #define UART_RX_DATA 0x00 | ||
40 | #define UART_TX_DATA 0x00 | ||
41 | |||
42 | #define UART_INT_EN 0x01 | ||
43 | #define UART_INT_ID 0x02 | ||
44 | #define UART_FIFO_CTL 0x02 | ||
45 | #define UART_LINE_CTL 0x03 | ||
46 | #define UART_MODEM_CTL 0x04 | ||
47 | #define UART_LINE_STS 0x05 | ||
48 | #define UART_MODEM_STS 0x06 | ||
49 | |||
50 | #define UART_DIVISOR0 0x00 | ||
51 | #define UART_DIVISOR1 0x01 | ||
52 | |||
53 | #define BASE_BAUD (XLP_IO_CLK/16) | ||
54 | #define BAUD_DIVISOR(baud) (BASE_BAUD / baud) | ||
55 | |||
56 | /* LCR mask values */ | ||
57 | #define LCR_5BITS 0x00 | ||
58 | #define LCR_6BITS 0x01 | ||
59 | #define LCR_7BITS 0x02 | ||
60 | #define LCR_8BITS 0x03 | ||
61 | #define LCR_STOPB 0x04 | ||
62 | #define LCR_PENAB 0x08 | ||
63 | #define LCR_PODD 0x00 | ||
64 | #define LCR_PEVEN 0x10 | ||
65 | #define LCR_PONE 0x20 | ||
66 | #define LCR_PZERO 0x30 | ||
67 | #define LCR_SBREAK 0x40 | ||
68 | #define LCR_EFR_ENABLE 0xbf | ||
69 | #define LCR_DLAB 0x80 | ||
70 | |||
71 | /* MCR mask values */ | ||
72 | #define MCR_DTR 0x01 | ||
73 | #define MCR_RTS 0x02 | ||
74 | #define MCR_DRS 0x04 | ||
75 | #define MCR_IE 0x08 | ||
76 | #define MCR_LOOPBACK 0x10 | ||
77 | |||
78 | /* FCR mask values */ | ||
79 | #define FCR_RCV_RST 0x02 | ||
80 | #define FCR_XMT_RST 0x04 | ||
81 | #define FCR_RX_LOW 0x00 | ||
82 | #define FCR_RX_MEDL 0x40 | ||
83 | #define FCR_RX_MEDH 0x80 | ||
84 | #define FCR_RX_HIGH 0xc0 | ||
85 | |||
86 | /* IER mask values */ | ||
87 | #define IER_ERXRDY 0x1 | ||
88 | #define IER_ETXRDY 0x2 | ||
89 | #define IER_ERLS 0x4 | ||
90 | #define IER_EMSC 0x8 | ||
91 | |||
92 | #if !defined(LOCORE) && !defined(__ASSEMBLY__) | ||
93 | |||
94 | #define nlm_read_uart_reg(b, r) nlm_read_reg(b, r) | ||
95 | #define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v) | ||
96 | #define nlm_get_uart_pcibase(node, inst) \ | ||
97 | nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst)) | ||
98 | #define nlm_get_uart_regbase(node, inst) \ | ||
99 | (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) | ||
100 | |||
101 | static inline void | ||
102 | nlm_uart_set_baudrate(uint64_t base, int baud) | ||
103 | { | ||
104 | uint32_t lcr; | ||
105 | |||
106 | lcr = nlm_read_uart_reg(base, UART_LINE_CTL); | ||
107 | |||
108 | /* enable divisor register, and write baud values */ | ||
109 | nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7)); | ||
110 | nlm_write_uart_reg(base, UART_DIVISOR0, | ||
111 | (BAUD_DIVISOR(baud) & 0xff)); | ||
112 | nlm_write_uart_reg(base, UART_DIVISOR1, | ||
113 | ((BAUD_DIVISOR(baud) >> 8) & 0xff)); | ||
114 | |||
115 | /* restore default lcr */ | ||
116 | nlm_write_uart_reg(base, UART_LINE_CTL, lcr); | ||
117 | } | ||
118 | |||
119 | static inline void | ||
120 | nlm_uart_outbyte(uint64_t base, char c) | ||
121 | { | ||
122 | uint32_t lsr; | ||
123 | |||
124 | for (;;) { | ||
125 | lsr = nlm_read_uart_reg(base, UART_LINE_STS); | ||
126 | if (lsr & 0x20) | ||
127 | break; | ||
128 | } | ||
129 | |||
130 | nlm_write_uart_reg(base, UART_TX_DATA, (int)c); | ||
131 | } | ||
132 | |||
133 | static inline char | ||
134 | nlm_uart_inbyte(uint64_t base) | ||
135 | { | ||
136 | int data, lsr; | ||
137 | |||
138 | for (;;) { | ||
139 | lsr = nlm_read_uart_reg(base, UART_LINE_STS); | ||
140 | if (lsr & 0x80) { /* parity/frame/break-error - push a zero */ | ||
141 | data = 0; | ||
142 | break; | ||
143 | } | ||
144 | if (lsr & 0x01) { /* Rx data */ | ||
145 | data = nlm_read_uart_reg(base, UART_RX_DATA); | ||
146 | break; | ||
147 | } | ||
148 | } | ||
149 | |||
150 | return (char)data; | ||
151 | } | ||
152 | |||
153 | static inline int | ||
154 | nlm_uart_init(uint64_t base, int baud, int databits, int stopbits, | ||
155 | int parity, int int_en, int loopback) | ||
156 | { | ||
157 | uint32_t lcr; | ||
158 | |||
159 | lcr = 0; | ||
160 | if (databits >= 8) | ||
161 | lcr |= LCR_8BITS; | ||
162 | else if (databits == 7) | ||
163 | lcr |= LCR_7BITS; | ||
164 | else if (databits == 6) | ||
165 | lcr |= LCR_6BITS; | ||
166 | else | ||
167 | lcr |= LCR_5BITS; | ||
168 | |||
169 | if (stopbits > 1) | ||
170 | lcr |= LCR_STOPB; | ||
171 | |||
172 | lcr |= parity << 3; | ||
173 | |||
174 | /* setup default lcr */ | ||
175 | nlm_write_uart_reg(base, UART_LINE_CTL, lcr); | ||
176 | |||
177 | /* Reset the FIFOs */ | ||
178 | nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST); | ||
179 | |||
180 | nlm_uart_set_baudrate(base, baud); | ||
181 | |||
182 | if (loopback) | ||
183 | nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f); | ||
184 | |||
185 | if (int_en) | ||
186 | nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY); | ||
187 | |||
188 | return 0; | ||
189 | } | ||
190 | #endif /* !LOCORE && !__ASSEMBLY__ */ | ||
191 | #endif /* __XLP_HAL_UART_H__ */ | ||
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/usb.h b/arch/mips/include/asm/netlogic/xlp-hal/usb.h deleted file mode 100644 index a9cd350dfb6..00000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/usb.h +++ /dev/null | |||
@@ -1,64 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2003-2012 Broadcom Corporation | ||
3 | * All Rights Reserved | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the Broadcom | ||
9 | * license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or without | ||
12 | * modification, are permitted provided that the following conditions | ||
13 | * are met: | ||
14 | * | ||
15 | * 1. Redistributions of source code must retain the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer. | ||
17 | * 2. Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in | ||
19 | * the documentation and/or other materials provided with the | ||
20 | * distribution. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR | ||
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE | ||
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef __NLM_HAL_USB_H__ | ||
36 | #define __NLM_HAL_USB_H__ | ||
37 | |||
38 | #define USB_CTL_0 0x01 | ||
39 | #define USB_PHY_0 0x0A | ||
40 | #define USB_PHY_RESET 0x01 | ||
41 | #define USB_PHY_PORT_RESET_0 0x10 | ||
42 | #define USB_PHY_PORT_RESET_1 0x20 | ||
43 | #define USB_CONTROLLER_RESET 0x01 | ||
44 | #define USB_INT_STATUS 0x0E | ||
45 | #define USB_INT_EN 0x0F | ||
46 | #define USB_PHY_INTERRUPT_EN 0x01 | ||
47 | #define USB_OHCI_INTERRUPT_EN 0x02 | ||
48 | #define USB_OHCI_INTERRUPT1_EN 0x04 | ||
49 | #define USB_OHCI_INTERRUPT2_EN 0x08 | ||
50 | #define USB_CTRL_INTERRUPT_EN 0x10 | ||
51 | |||
52 | #ifndef __ASSEMBLY__ | ||
53 | |||
54 | #define nlm_read_usb_reg(b, r) nlm_read_reg(b, r) | ||
55 | #define nlm_write_usb_reg(b, r, v) nlm_write_reg(b, r, v) | ||
56 | #define nlm_get_usb_pcibase(node, inst) \ | ||
57 | nlm_pcicfg_base(XLP_IO_USB_OFFSET(node, inst)) | ||
58 | #define nlm_get_usb_hcd_base(node, inst) \ | ||
59 | nlm_xkphys_map_pcibar0(nlm_get_usb_pcibase(node, inst)) | ||
60 | #define nlm_get_usb_regbase(node, inst) \ | ||
61 | (nlm_get_usb_pcibase(node, inst) + XLP_IO_PCI_HDRSZ) | ||
62 | |||
63 | #endif | ||
64 | #endif /* __NLM_HAL_USB_H__ */ | ||
diff --git a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h b/arch/mips/include/asm/netlogic/xlp-hal/xlp.h deleted file mode 100644 index 7e47209327a..00000000000 --- a/arch/mips/include/asm/netlogic/xlp-hal/xlp.h +++ /dev/null | |||
@@ -1,64 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | ||
3 | * reserved. | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the NetLogic | ||
9 | * license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or without | ||
12 | * modification, are permitted provided that the following conditions | ||
13 | * are met: | ||
14 | * | ||
15 | * 1. Redistributions of source code must retain the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer. | ||
17 | * 2. Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in | ||
19 | * the documentation and/or other materials provided with the | ||
20 | * distribution. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | ||
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | ||
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef _NLM_HAL_XLP_H | ||
36 | #define _NLM_HAL_XLP_H | ||
37 | |||
38 | #define PIC_UART_0_IRQ 17 | ||
39 | #define PIC_UART_1_IRQ 18 | ||
40 | #define PIC_PCIE_LINK_0_IRQ 19 | ||
41 | #define PIC_PCIE_LINK_1_IRQ 20 | ||
42 | #define PIC_PCIE_LINK_2_IRQ 21 | ||
43 | #define PIC_PCIE_LINK_3_IRQ 22 | ||
44 | #define PIC_EHCI_0_IRQ 23 | ||
45 | #define PIC_EHCI_1_IRQ 24 | ||
46 | #define PIC_OHCI_0_IRQ 25 | ||
47 | #define PIC_OHCI_1_IRQ 26 | ||
48 | #define PIC_OHCI_2_IRQ 27 | ||
49 | #define PIC_OHCI_3_IRQ 28 | ||
50 | #define PIC_MMC_IRQ 29 | ||
51 | #define PIC_I2C_0_IRQ 30 | ||
52 | #define PIC_I2C_1_IRQ 31 | ||
53 | |||
54 | #ifndef __ASSEMBLY__ | ||
55 | |||
56 | /* SMP support functions */ | ||
57 | void xlp_boot_core0_siblings(void); | ||
58 | void xlp_wakeup_secondary_cpus(void); | ||
59 | |||
60 | void xlp_mmu_init(void); | ||
61 | void nlm_hal_init(void); | ||
62 | |||
63 | #endif /* !__ASSEMBLY__ */ | ||
64 | #endif /* _ASM_NLM_XLP_H */ | ||
diff --git a/arch/mips/include/asm/netlogic/xlr/bridge.h b/arch/mips/include/asm/netlogic/xlr/bridge.h deleted file mode 100644 index 2d02428c4f1..00000000000 --- a/arch/mips/include/asm/netlogic/xlr/bridge.h +++ /dev/null | |||
@@ -1,104 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2003-2012 Broadcom Corporation | ||
3 | * All Rights Reserved | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the Broadcom | ||
9 | * license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or without | ||
12 | * modification, are permitted provided that the following conditions | ||
13 | * are met: | ||
14 | * | ||
15 | * 1. Redistributions of source code must retain the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer. | ||
17 | * 2. Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in | ||
19 | * the documentation and/or other materials provided with the | ||
20 | * distribution. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR | ||
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE | ||
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | #ifndef _ASM_NLM_BRIDGE_H_ | ||
35 | #define _ASM_NLM_BRIDGE_H_ | ||
36 | |||
37 | #define BRIDGE_DRAM_0_BAR 0 | ||
38 | #define BRIDGE_DRAM_1_BAR 1 | ||
39 | #define BRIDGE_DRAM_2_BAR 2 | ||
40 | #define BRIDGE_DRAM_3_BAR 3 | ||
41 | #define BRIDGE_DRAM_4_BAR 4 | ||
42 | #define BRIDGE_DRAM_5_BAR 5 | ||
43 | #define BRIDGE_DRAM_6_BAR 6 | ||
44 | #define BRIDGE_DRAM_7_BAR 7 | ||
45 | #define BRIDGE_DRAM_CHN_0_MTR_0_BAR 8 | ||
46 | #define BRIDGE_DRAM_CHN_0_MTR_1_BAR 9 | ||
47 | #define BRIDGE_DRAM_CHN_0_MTR_2_BAR 10 | ||
48 | #define BRIDGE_DRAM_CHN_0_MTR_3_BAR 11 | ||
49 | #define BRIDGE_DRAM_CHN_0_MTR_4_BAR 12 | ||
50 | #define BRIDGE_DRAM_CHN_0_MTR_5_BAR 13 | ||
51 | #define BRIDGE_DRAM_CHN_0_MTR_6_BAR 14 | ||
52 | #define BRIDGE_DRAM_CHN_0_MTR_7_BAR 15 | ||
53 | #define BRIDGE_DRAM_CHN_1_MTR_0_BAR 16 | ||
54 | #define BRIDGE_DRAM_CHN_1_MTR_1_BAR 17 | ||
55 | #define BRIDGE_DRAM_CHN_1_MTR_2_BAR 18 | ||
56 | #define BRIDGE_DRAM_CHN_1_MTR_3_BAR 19 | ||
57 | #define BRIDGE_DRAM_CHN_1_MTR_4_BAR 20 | ||
58 | #define BRIDGE_DRAM_CHN_1_MTR_5_BAR 21 | ||
59 | #define BRIDGE_DRAM_CHN_1_MTR_6_BAR 22 | ||
60 | #define BRIDGE_DRAM_CHN_1_MTR_7_BAR 23 | ||
61 | #define BRIDGE_CFG_BAR 24 | ||
62 | #define BRIDGE_PHNX_IO_BAR 25 | ||
63 | #define BRIDGE_FLASH_BAR 26 | ||
64 | #define BRIDGE_SRAM_BAR 27 | ||
65 | #define BRIDGE_HTMEM_BAR 28 | ||
66 | #define BRIDGE_HTINT_BAR 29 | ||
67 | #define BRIDGE_HTPIC_BAR 30 | ||
68 | #define BRIDGE_HTSM_BAR 31 | ||
69 | #define BRIDGE_HTIO_BAR 32 | ||
70 | #define BRIDGE_HTCFG_BAR 33 | ||
71 | #define BRIDGE_PCIXCFG_BAR 34 | ||
72 | #define BRIDGE_PCIXMEM_BAR 35 | ||
73 | #define BRIDGE_PCIXIO_BAR 36 | ||
74 | #define BRIDGE_DEVICE_MASK 37 | ||
75 | #define BRIDGE_AERR_INTR_LOG1 38 | ||
76 | #define BRIDGE_AERR_INTR_LOG2 39 | ||
77 | #define BRIDGE_AERR_INTR_LOG3 40 | ||
78 | #define BRIDGE_AERR_DEV_STAT 41 | ||
79 | #define BRIDGE_AERR1_LOG1 42 | ||
80 | #define BRIDGE_AERR1_LOG2 43 | ||
81 | #define BRIDGE_AERR1_LOG3 44 | ||
82 | #define BRIDGE_AERR1_DEV_STAT 45 | ||
83 | #define BRIDGE_AERR_INTR_EN 46 | ||
84 | #define BRIDGE_AERR_UPG 47 | ||
85 | #define BRIDGE_AERR_CLEAR 48 | ||
86 | #define BRIDGE_AERR1_CLEAR 49 | ||
87 | #define BRIDGE_SBE_COUNTS 50 | ||
88 | #define BRIDGE_DBE_COUNTS 51 | ||
89 | #define BRIDGE_BITERR_INT_EN 52 | ||
90 | |||
91 | #define BRIDGE_SYS2IO_CREDITS 53 | ||
92 | #define BRIDGE_EVNT_CNT_CTRL1 54 | ||
93 | #define BRIDGE_EVNT_COUNTER1 55 | ||
94 | #define BRIDGE_EVNT_CNT_CTRL2 56 | ||
95 | #define BRIDGE_EVNT_COUNTER2 57 | ||
96 | #define BRIDGE_RESERVED1 58 | ||
97 | |||
98 | #define BRIDGE_DEFEATURE 59 | ||
99 | #define BRIDGE_SCRATCH0 60 | ||
100 | #define BRIDGE_SCRATCH1 61 | ||
101 | #define BRIDGE_SCRATCH2 62 | ||
102 | #define BRIDGE_SCRATCH3 63 | ||
103 | |||
104 | #endif | ||
diff --git a/arch/mips/include/asm/netlogic/xlr/flash.h b/arch/mips/include/asm/netlogic/xlr/flash.h deleted file mode 100644 index f8aca5472b6..00000000000 --- a/arch/mips/include/asm/netlogic/xlr/flash.h +++ /dev/null | |||
@@ -1,55 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2003-2012 Broadcom Corporation | ||
3 | * All Rights Reserved | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the Broadcom | ||
9 | * license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or without | ||
12 | * modification, are permitted provided that the following conditions | ||
13 | * are met: | ||
14 | * | ||
15 | * 1. Redistributions of source code must retain the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer. | ||
17 | * 2. Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in | ||
19 | * the documentation and/or other materials provided with the | ||
20 | * distribution. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR | ||
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE | ||
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | #ifndef _ASM_NLM_FLASH_H_ | ||
35 | #define _ASM_NLM_FLASH_H_ | ||
36 | |||
37 | #define FLASH_CSBASE_ADDR(cs) (cs) | ||
38 | #define FLASH_CSADDR_MASK(cs) (0x10 + (cs)) | ||
39 | #define FLASH_CSDEV_PARM(cs) (0x20 + (cs)) | ||
40 | #define FLASH_CSTIME_PARMA(cs) (0x30 + (cs)) | ||
41 | #define FLASH_CSTIME_PARMB(cs) (0x40 + (cs)) | ||
42 | |||
43 | #define FLASH_INT_MASK 0x50 | ||
44 | #define FLASH_INT_STATUS 0x60 | ||
45 | #define FLASH_ERROR_STATUS 0x70 | ||
46 | #define FLASH_ERROR_ADDR 0x80 | ||
47 | |||
48 | #define FLASH_NAND_CLE(cs) (0x90 + (cs)) | ||
49 | #define FLASH_NAND_ALE(cs) (0xa0 + (cs)) | ||
50 | |||
51 | #define FLASH_NAND_CSDEV_PARAM 0x000041e6 | ||
52 | #define FLASH_NAND_CSTIME_PARAMA 0x4f400e22 | ||
53 | #define FLASH_NAND_CSTIME_PARAMB 0x000083cf | ||
54 | |||
55 | #endif | ||
diff --git a/arch/mips/include/asm/netlogic/xlr/fmn.h b/arch/mips/include/asm/netlogic/xlr/fmn.h deleted file mode 100644 index 68d5167c86b..00000000000 --- a/arch/mips/include/asm/netlogic/xlr/fmn.h +++ /dev/null | |||
@@ -1,363 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2003-2012 Broadcom Corporation | ||
3 | * All Rights Reserved | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the Broadcom | ||
9 | * license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or without | ||
12 | * modification, are permitted provided that the following conditions | ||
13 | * are met: | ||
14 | * | ||
15 | * 1. Redistributions of source code must retain the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer. | ||
17 | * 2. Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in | ||
19 | * the documentation and/or other materials provided with the | ||
20 | * distribution. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR | ||
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE | ||
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef _NLM_FMN_H_ | ||
36 | #define _NLM_FMN_H_ | ||
37 | |||
38 | #include <asm/netlogic/mips-extns.h> /* for COP2 access */ | ||
39 | |||
40 | /* Station IDs */ | ||
41 | #define FMN_STNID_CPU0 0x00 | ||
42 | #define FMN_STNID_CPU1 0x08 | ||
43 | #define FMN_STNID_CPU2 0x10 | ||
44 | #define FMN_STNID_CPU3 0x18 | ||
45 | #define FMN_STNID_CPU4 0x20 | ||
46 | #define FMN_STNID_CPU5 0x28 | ||
47 | #define FMN_STNID_CPU6 0x30 | ||
48 | #define FMN_STNID_CPU7 0x38 | ||
49 | |||
50 | #define FMN_STNID_XGS0_TX 64 | ||
51 | #define FMN_STNID_XMAC0_00_TX 64 | ||
52 | #define FMN_STNID_XMAC0_01_TX 65 | ||
53 | #define FMN_STNID_XMAC0_02_TX 66 | ||
54 | #define FMN_STNID_XMAC0_03_TX 67 | ||
55 | #define FMN_STNID_XMAC0_04_TX 68 | ||
56 | #define FMN_STNID_XMAC0_05_TX 69 | ||
57 | #define FMN_STNID_XMAC0_06_TX 70 | ||
58 | #define FMN_STNID_XMAC0_07_TX 71 | ||
59 | #define FMN_STNID_XMAC0_08_TX 72 | ||
60 | #define FMN_STNID_XMAC0_09_TX 73 | ||
61 | #define FMN_STNID_XMAC0_10_TX 74 | ||
62 | #define FMN_STNID_XMAC0_11_TX 75 | ||
63 | #define FMN_STNID_XMAC0_12_TX 76 | ||
64 | #define FMN_STNID_XMAC0_13_TX 77 | ||
65 | #define FMN_STNID_XMAC0_14_TX 78 | ||
66 | #define FMN_STNID_XMAC0_15_TX 79 | ||
67 | |||
68 | #define FMN_STNID_XGS1_TX 80 | ||
69 | #define FMN_STNID_XMAC1_00_TX 80 | ||
70 | #define FMN_STNID_XMAC1_01_TX 81 | ||
71 | #define FMN_STNID_XMAC1_02_TX 82 | ||
72 | #define FMN_STNID_XMAC1_03_TX 83 | ||
73 | #define FMN_STNID_XMAC1_04_TX 84 | ||
74 | #define FMN_STNID_XMAC1_05_TX 85 | ||
75 | #define FMN_STNID_XMAC1_06_TX 86 | ||
76 | #define FMN_STNID_XMAC1_07_TX 87 | ||
77 | #define FMN_STNID_XMAC1_08_TX 88 | ||
78 | #define FMN_STNID_XMAC1_09_TX 89 | ||
79 | #define FMN_STNID_XMAC1_10_TX 90 | ||
80 | #define FMN_STNID_XMAC1_11_TX 91 | ||
81 | #define FMN_STNID_XMAC1_12_TX 92 | ||
82 | #define FMN_STNID_XMAC1_13_TX 93 | ||
83 | #define FMN_STNID_XMAC1_14_TX 94 | ||
84 | #define FMN_STNID_XMAC1_15_TX 95 | ||
85 | |||
86 | #define FMN_STNID_GMAC 96 | ||
87 | #define FMN_STNID_GMACJFR_0 96 | ||
88 | #define FMN_STNID_GMACRFR_0 97 | ||
89 | #define FMN_STNID_GMACTX0 98 | ||
90 | #define FMN_STNID_GMACTX1 99 | ||
91 | #define FMN_STNID_GMACTX2 100 | ||
92 | #define FMN_STNID_GMACTX3 101 | ||
93 | #define FMN_STNID_GMACJFR_1 102 | ||
94 | #define FMN_STNID_GMACRFR_1 103 | ||
95 | |||
96 | #define FMN_STNID_DMA 104 | ||
97 | #define FMN_STNID_DMA_0 104 | ||
98 | #define FMN_STNID_DMA_1 105 | ||
99 | #define FMN_STNID_DMA_2 106 | ||
100 | #define FMN_STNID_DMA_3 107 | ||
101 | |||
102 | #define FMN_STNID_XGS0FR 112 | ||
103 | #define FMN_STNID_XMAC0JFR 112 | ||
104 | #define FMN_STNID_XMAC0RFR 113 | ||
105 | |||
106 | #define FMN_STNID_XGS1FR 114 | ||
107 | #define FMN_STNID_XMAC1JFR 114 | ||
108 | #define FMN_STNID_XMAC1RFR 115 | ||
109 | #define FMN_STNID_SEC 120 | ||
110 | #define FMN_STNID_SEC0 120 | ||
111 | #define FMN_STNID_SEC1 121 | ||
112 | #define FMN_STNID_SEC2 122 | ||
113 | #define FMN_STNID_SEC3 123 | ||
114 | #define FMN_STNID_PK0 124 | ||
115 | #define FMN_STNID_SEC_RSA 124 | ||
116 | #define FMN_STNID_SEC_RSVD0 125 | ||
117 | #define FMN_STNID_SEC_RSVD1 126 | ||
118 | #define FMN_STNID_SEC_RSVD2 127 | ||
119 | |||
120 | #define FMN_STNID_GMAC1 80 | ||
121 | #define FMN_STNID_GMAC1_FR_0 81 | ||
122 | #define FMN_STNID_GMAC1_TX0 82 | ||
123 | #define FMN_STNID_GMAC1_TX1 83 | ||
124 | #define FMN_STNID_GMAC1_TX2 84 | ||
125 | #define FMN_STNID_GMAC1_TX3 85 | ||
126 | #define FMN_STNID_GMAC1_FR_1 87 | ||
127 | #define FMN_STNID_GMAC0 96 | ||
128 | #define FMN_STNID_GMAC0_FR_0 97 | ||
129 | #define FMN_STNID_GMAC0_TX0 98 | ||
130 | #define FMN_STNID_GMAC0_TX1 99 | ||
131 | #define FMN_STNID_GMAC0_TX2 100 | ||
132 | #define FMN_STNID_GMAC0_TX3 101 | ||
133 | #define FMN_STNID_GMAC0_FR_1 103 | ||
134 | #define FMN_STNID_CMP_0 108 | ||
135 | #define FMN_STNID_CMP_1 109 | ||
136 | #define FMN_STNID_CMP_2 110 | ||
137 | #define FMN_STNID_CMP_3 111 | ||
138 | #define FMN_STNID_PCIE_0 116 | ||
139 | #define FMN_STNID_PCIE_1 117 | ||
140 | #define FMN_STNID_PCIE_2 118 | ||
141 | #define FMN_STNID_PCIE_3 119 | ||
142 | #define FMN_STNID_XLS_PK0 121 | ||
143 | |||
144 | #define nlm_read_c2_cc0(s) __read_32bit_c2_register($16, s) | ||
145 | #define nlm_read_c2_cc1(s) __read_32bit_c2_register($17, s) | ||
146 | #define nlm_read_c2_cc2(s) __read_32bit_c2_register($18, s) | ||
147 | #define nlm_read_c2_cc3(s) __read_32bit_c2_register($19, s) | ||
148 | #define nlm_read_c2_cc4(s) __read_32bit_c2_register($20, s) | ||
149 | #define nlm_read_c2_cc5(s) __read_32bit_c2_register($21, s) | ||
150 | #define nlm_read_c2_cc6(s) __read_32bit_c2_register($22, s) | ||
151 | #define nlm_read_c2_cc7(s) __read_32bit_c2_register($23, s) | ||
152 | #define nlm_read_c2_cc8(s) __read_32bit_c2_register($24, s) | ||
153 | #define nlm_read_c2_cc9(s) __read_32bit_c2_register($25, s) | ||
154 | #define nlm_read_c2_cc10(s) __read_32bit_c2_register($26, s) | ||
155 | #define nlm_read_c2_cc11(s) __read_32bit_c2_register($27, s) | ||
156 | #define nlm_read_c2_cc12(s) __read_32bit_c2_register($28, s) | ||
157 | #define nlm_read_c2_cc13(s) __read_32bit_c2_register($29, s) | ||
158 | #define nlm_read_c2_cc14(s) __read_32bit_c2_register($30, s) | ||
159 | #define nlm_read_c2_cc15(s) __read_32bit_c2_register($31, s) | ||
160 | |||
161 | #define nlm_write_c2_cc0(s, v) __write_32bit_c2_register($16, s, v) | ||
162 | #define nlm_write_c2_cc1(s, v) __write_32bit_c2_register($17, s, v) | ||
163 | #define nlm_write_c2_cc2(s, v) __write_32bit_c2_register($18, s, v) | ||
164 | #define nlm_write_c2_cc3(s, v) __write_32bit_c2_register($19, s, v) | ||
165 | #define nlm_write_c2_cc4(s, v) __write_32bit_c2_register($20, s, v) | ||
166 | #define nlm_write_c2_cc5(s, v) __write_32bit_c2_register($21, s, v) | ||
167 | #define nlm_write_c2_cc6(s, v) __write_32bit_c2_register($22, s, v) | ||
168 | #define nlm_write_c2_cc7(s, v) __write_32bit_c2_register($23, s, v) | ||
169 | #define nlm_write_c2_cc8(s, v) __write_32bit_c2_register($24, s, v) | ||
170 | #define nlm_write_c2_cc9(s, v) __write_32bit_c2_register($25, s, v) | ||
171 | #define nlm_write_c2_cc10(s, v) __write_32bit_c2_register($26, s, v) | ||
172 | #define nlm_write_c2_cc11(s, v) __write_32bit_c2_register($27, s, v) | ||
173 | #define nlm_write_c2_cc12(s, v) __write_32bit_c2_register($28, s, v) | ||
174 | #define nlm_write_c2_cc13(s, v) __write_32bit_c2_register($29, s, v) | ||
175 | #define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v) | ||
176 | #define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v) | ||
177 | |||
178 | #define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0) | ||
179 | #define nlm_read_c2_config() __read_32bit_c2_register($3, 0) | ||
180 | #define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v) | ||
181 | #define nlm_read_c2_bucksize(b) __read_32bit_c2_register($4, b) | ||
182 | #define nlm_write_c2_bucksize(b, v) __write_32bit_c2_register($4, b, v) | ||
183 | |||
184 | #define nlm_read_c2_rx_msg0() __read_64bit_c2_register($1, 0) | ||
185 | #define nlm_read_c2_rx_msg1() __read_64bit_c2_register($1, 1) | ||
186 | #define nlm_read_c2_rx_msg2() __read_64bit_c2_register($1, 2) | ||
187 | #define nlm_read_c2_rx_msg3() __read_64bit_c2_register($1, 3) | ||
188 | |||
189 | #define nlm_write_c2_tx_msg0(v) __write_64bit_c2_register($0, 0, v) | ||
190 | #define nlm_write_c2_tx_msg1(v) __write_64bit_c2_register($0, 1, v) | ||
191 | #define nlm_write_c2_tx_msg2(v) __write_64bit_c2_register($0, 2, v) | ||
192 | #define nlm_write_c2_tx_msg3(v) __write_64bit_c2_register($0, 3, v) | ||
193 | |||
194 | #define FMN_STN_RX_QSIZE 256 | ||
195 | #define FMN_NSTATIONS 128 | ||
196 | #define FMN_CORE_NBUCKETS 8 | ||
197 | |||
198 | static inline void nlm_msgsnd(unsigned int stid) | ||
199 | { | ||
200 | __asm__ volatile ( | ||
201 | ".set push\n" | ||
202 | ".set noreorder\n" | ||
203 | ".set noat\n" | ||
204 | "move $1, %0\n" | ||
205 | "c2 0x10001\n" /* msgsnd $1 */ | ||
206 | ".set pop\n" | ||
207 | : : "r" (stid) : "$1" | ||
208 | ); | ||
209 | } | ||
210 | |||
211 | static inline void nlm_msgld(unsigned int pri) | ||
212 | { | ||
213 | __asm__ volatile ( | ||
214 | ".set push\n" | ||
215 | ".set noreorder\n" | ||
216 | ".set noat\n" | ||
217 | "move $1, %0\n" | ||
218 | "c2 0x10002\n" /* msgld $1 */ | ||
219 | ".set pop\n" | ||
220 | : : "r" (pri) : "$1" | ||
221 | ); | ||
222 | } | ||
223 | |||
224 | static inline void nlm_msgwait(unsigned int mask) | ||
225 | { | ||
226 | __asm__ volatile ( | ||
227 | ".set push\n" | ||
228 | ".set noreorder\n" | ||
229 | ".set noat\n" | ||
230 | "move $8, %0\n" | ||
231 | "c2 0x10003\n" /* msgwait $1 */ | ||
232 | ".set pop\n" | ||
233 | : : "r" (mask) : "$1" | ||
234 | ); | ||
235 | } | ||
236 | |||
237 | /* | ||
238 | * Disable interrupts and enable COP2 access | ||
239 | */ | ||
240 | static inline uint32_t nlm_cop2_enable(void) | ||
241 | { | ||
242 | uint32_t sr = read_c0_status(); | ||
243 | |||
244 | write_c0_status((sr & ~ST0_IE) | ST0_CU2); | ||
245 | return sr; | ||
246 | } | ||
247 | |||
248 | static inline void nlm_cop2_restore(uint32_t sr) | ||
249 | { | ||
250 | write_c0_status(sr); | ||
251 | } | ||
252 | |||
253 | static inline void nlm_fmn_setup_intr(int irq, unsigned int tmask) | ||
254 | { | ||
255 | uint32_t config; | ||
256 | |||
257 | config = (1 << 24) /* interrupt water mark - 1 msg */ | ||
258 | | (irq << 16) /* irq */ | ||
259 | | (tmask << 8) /* thread mask */ | ||
260 | | 0x2; /* enable watermark intr, disable empty intr */ | ||
261 | nlm_write_c2_config(config); | ||
262 | } | ||
263 | |||
264 | struct nlm_fmn_msg { | ||
265 | uint64_t msg0; | ||
266 | uint64_t msg1; | ||
267 | uint64_t msg2; | ||
268 | uint64_t msg3; | ||
269 | }; | ||
270 | |||
271 | static inline int nlm_fmn_send(unsigned int size, unsigned int code, | ||
272 | unsigned int stid, struct nlm_fmn_msg *msg) | ||
273 | { | ||
274 | unsigned int dest; | ||
275 | uint32_t status; | ||
276 | int i; | ||
277 | |||
278 | /* | ||
279 | * Make sure that all the writes pending at the cpu are flushed. | ||
280 | * Any writes pending on CPU will not be see by devices. L1/L2 | ||
281 | * caches are coherent with IO, so no cache flush needed. | ||
282 | */ | ||
283 | __asm __volatile("sync"); | ||
284 | |||
285 | /* Load TX message buffers */ | ||
286 | nlm_write_c2_tx_msg0(msg->msg0); | ||
287 | nlm_write_c2_tx_msg1(msg->msg1); | ||
288 | nlm_write_c2_tx_msg2(msg->msg2); | ||
289 | nlm_write_c2_tx_msg3(msg->msg3); | ||
290 | dest = ((size - 1) << 16) | (code << 8) | stid; | ||
291 | |||
292 | /* | ||
293 | * Retry a few times on credit fail, this should be a | ||
294 | * transient condition, unless there is a configuration | ||
295 | * failure, or the receiver is stuck. | ||
296 | */ | ||
297 | for (i = 0; i < 8; i++) { | ||
298 | nlm_msgsnd(dest); | ||
299 | status = nlm_read_c2_status(0); | ||
300 | if ((status & 0x2) == 1) | ||
301 | pr_info("Send pending fail!\n"); | ||
302 | if ((status & 0x4) == 0) | ||
303 | return 0; | ||
304 | } | ||
305 | |||
306 | /* If there is a credit failure, return error */ | ||
307 | return status & 0x06; | ||
308 | } | ||
309 | |||
310 | static inline int nlm_fmn_receive(int bucket, int *size, int *code, int *stid, | ||
311 | struct nlm_fmn_msg *msg) | ||
312 | { | ||
313 | uint32_t status, tmp; | ||
314 | |||
315 | nlm_msgld(bucket); | ||
316 | |||
317 | /* wait for load pending to clear */ | ||
318 | do { | ||
319 | status = nlm_read_c2_status(1); | ||
320 | } while ((status & 0x08) != 0); | ||
321 | |||
322 | /* receive error bits */ | ||
323 | tmp = status & 0x30; | ||
324 | if (tmp != 0) | ||
325 | return tmp; | ||
326 | |||
327 | *size = ((status & 0xc0) >> 6) + 1; | ||
328 | *code = (status & 0xff00) >> 8; | ||
329 | *stid = (status & 0x7f0000) >> 16; | ||
330 | msg->msg0 = nlm_read_c2_rx_msg0(); | ||
331 | msg->msg1 = nlm_read_c2_rx_msg1(); | ||
332 | msg->msg2 = nlm_read_c2_rx_msg2(); | ||
333 | msg->msg3 = nlm_read_c2_rx_msg3(); | ||
334 | |||
335 | return 0; | ||
336 | } | ||
337 | |||
338 | struct xlr_fmn_info { | ||
339 | int num_buckets; | ||
340 | int start_stn_id; | ||
341 | int end_stn_id; | ||
342 | int credit_config[128]; | ||
343 | }; | ||
344 | |||
345 | struct xlr_board_fmn_config { | ||
346 | int bucket_size[128]; /* size of buckets for all stations */ | ||
347 | struct xlr_fmn_info cpu[8]; | ||
348 | struct xlr_fmn_info gmac[2]; | ||
349 | struct xlr_fmn_info dma; | ||
350 | struct xlr_fmn_info cmp; | ||
351 | struct xlr_fmn_info sae; | ||
352 | struct xlr_fmn_info xgmac[2]; | ||
353 | }; | ||
354 | |||
355 | extern int nlm_register_fmn_handler(int start, int end, | ||
356 | void (*fn)(int, int, int, int, struct nlm_fmn_msg *, void *), | ||
357 | void *arg); | ||
358 | extern void xlr_percpu_fmn_init(void); | ||
359 | extern void nlm_setup_fmn_irq(void); | ||
360 | extern void xlr_board_info_setup(void); | ||
361 | |||
362 | extern struct xlr_board_fmn_config xlr_board_fmn_config; | ||
363 | #endif | ||
diff --git a/arch/mips/include/asm/netlogic/xlr/gpio.h b/arch/mips/include/asm/netlogic/xlr/gpio.h index 8492e835b11..51f6ad4aeb1 100644 --- a/arch/mips/include/asm/netlogic/xlr/gpio.h +++ b/arch/mips/include/asm/netlogic/xlr/gpio.h | |||
@@ -35,40 +35,39 @@ | |||
35 | #ifndef _ASM_NLM_GPIO_H | 35 | #ifndef _ASM_NLM_GPIO_H |
36 | #define _ASM_NLM_GPIO_H | 36 | #define _ASM_NLM_GPIO_H |
37 | 37 | ||
38 | #define GPIO_INT_EN_REG 0 | 38 | #define NETLOGIC_GPIO_INT_EN_REG 0 |
39 | #define GPIO_INPUT_INVERSION_REG 1 | 39 | #define NETLOGIC_GPIO_INPUT_INVERSION_REG 1 |
40 | #define GPIO_IO_DIR_REG 2 | 40 | #define NETLOGIC_GPIO_IO_DIR_REG 2 |
41 | #define GPIO_IO_DATA_WR_REG 3 | 41 | #define NETLOGIC_GPIO_IO_DATA_WR_REG 3 |
42 | #define GPIO_IO_DATA_RD_REG 4 | 42 | #define NETLOGIC_GPIO_IO_DATA_RD_REG 4 |
43 | 43 | ||
44 | #define GPIO_SWRESET_REG 8 | 44 | #define NETLOGIC_GPIO_SWRESET_REG 8 |
45 | #define GPIO_DRAM1_CNTRL_REG 9 | 45 | #define NETLOGIC_GPIO_DRAM1_CNTRL_REG 9 |
46 | #define GPIO_DRAM1_RATIO_REG 10 | 46 | #define NETLOGIC_GPIO_DRAM1_RATIO_REG 10 |
47 | #define GPIO_DRAM1_RESET_REG 11 | 47 | #define NETLOGIC_GPIO_DRAM1_RESET_REG 11 |
48 | #define GPIO_DRAM1_STATUS_REG 12 | 48 | #define NETLOGIC_GPIO_DRAM1_STATUS_REG 12 |
49 | #define GPIO_DRAM2_CNTRL_REG 13 | 49 | #define NETLOGIC_GPIO_DRAM2_CNTRL_REG 13 |
50 | #define GPIO_DRAM2_RATIO_REG 14 | 50 | #define NETLOGIC_GPIO_DRAM2_RATIO_REG 14 |
51 | #define GPIO_DRAM2_RESET_REG 15 | 51 | #define NETLOGIC_GPIO_DRAM2_RESET_REG 15 |
52 | #define GPIO_DRAM2_STATUS_REG 16 | 52 | #define NETLOGIC_GPIO_DRAM2_STATUS_REG 16 |
53 | 53 | ||
54 | #define GPIO_PWRON_RESET_CFG_REG 21 | 54 | #define NETLOGIC_GPIO_PWRON_RESET_CFG_REG 21 |
55 | #define GPIO_BIST_ALL_GO_STATUS_REG 24 | 55 | #define NETLOGIC_GPIO_BIST_ALL_GO_STATUS_REG 24 |
56 | #define GPIO_BIST_CPU_GO_STATUS_REG 25 | 56 | #define NETLOGIC_GPIO_BIST_CPU_GO_STATUS_REG 25 |
57 | #define GPIO_BIST_DEV_GO_STATUS_REG 26 | 57 | #define NETLOGIC_GPIO_BIST_DEV_GO_STATUS_REG 26 |
58 | 58 | ||
59 | #define GPIO_FUSE_BANK_REG 35 | 59 | #define NETLOGIC_GPIO_FUSE_BANK_REG 35 |
60 | #define GPIO_CPU_RESET_REG 40 | 60 | #define NETLOGIC_GPIO_CPU_RESET_REG 40 |
61 | #define GPIO_RNG_REG 43 | 61 | #define NETLOGIC_GPIO_RNG_REG 43 |
62 | 62 | ||
63 | #define PWRON_RESET_PCMCIA_BOOT 17 | 63 | #define NETLOGIC_PWRON_RESET_PCMCIA_BOOT 17 |
64 | #define NETLOGIC_GPIO_LED_BITMAP 0x1700000 | ||
65 | #define NETLOGIC_GPIO_LED_0_SHIFT 20 | ||
66 | #define NETLOGIC_GPIO_LED_1_SHIFT 24 | ||
64 | 67 | ||
65 | #define GPIO_LED_BITMAP 0x1700000 | 68 | #define NETLOGIC_GPIO_LED_OUTPUT_CODE_RESET 0x01 |
66 | #define GPIO_LED_0_SHIFT 20 | 69 | #define NETLOGIC_GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02 |
67 | #define GPIO_LED_1_SHIFT 24 | 70 | #define NETLOGIC_GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03 |
68 | 71 | #define NETLOGIC_GPIO_LED_OUTPUT_CODE_MAIN 0x04 | |
69 | #define GPIO_LED_OUTPUT_CODE_RESET 0x01 | ||
70 | #define GPIO_LED_OUTPUT_CODE_HARD_RESET 0x02 | ||
71 | #define GPIO_LED_OUTPUT_CODE_SOFT_RESET 0x03 | ||
72 | #define GPIO_LED_OUTPUT_CODE_MAIN 0x04 | ||
73 | 72 | ||
74 | #endif | 73 | #endif |
diff --git a/arch/mips/include/asm/netlogic/xlr/iomap.h b/arch/mips/include/asm/netlogic/xlr/iomap.h index 2e768f032e8..2e3a4dd5304 100644 --- a/arch/mips/include/asm/netlogic/xlr/iomap.h +++ b/arch/mips/include/asm/netlogic/xlr/iomap.h | |||
@@ -106,4 +106,26 @@ | |||
106 | #define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 | 106 | #define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000 |
107 | #define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 | 107 | #define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000 |
108 | 108 | ||
109 | #ifndef __ASSEMBLY__ | ||
110 | #include <linux/types.h> | ||
111 | #include <asm/byteorder.h> | ||
112 | |||
113 | typedef volatile __u32 nlm_reg_t; | ||
114 | extern unsigned long netlogic_io_base; | ||
115 | |||
116 | /* FIXME read once in write_reg */ | ||
117 | #ifdef CONFIG_CPU_LITTLE_ENDIAN | ||
118 | #define netlogic_read_reg(base, offset) ((base)[(offset)]) | ||
119 | #define netlogic_write_reg(base, offset, value) ((base)[(offset)] = (value)) | ||
120 | #else | ||
121 | #define netlogic_read_reg(base, offset) (be32_to_cpu((base)[(offset)])) | ||
122 | #define netlogic_write_reg(base, offset, value) \ | ||
123 | ((base)[(offset)] = cpu_to_be32((value))) | ||
124 | #endif | ||
125 | |||
126 | #define netlogic_read_reg_le32(base, offset) (le32_to_cpu((base)[(offset)])) | ||
127 | #define netlogic_write_reg_le32(base, offset, value) \ | ||
128 | ((base)[(offset)] = cpu_to_le32((value))) | ||
129 | #define netlogic_io_mmio(offset) ((nlm_reg_t *)(netlogic_io_base+(offset))) | ||
130 | #endif /* __ASSEMBLY__ */ | ||
109 | #endif | 131 | #endif |
diff --git a/arch/mips/include/asm/netlogic/xlr/msidef.h b/arch/mips/include/asm/netlogic/xlr/msidef.h deleted file mode 100644 index 7e39d40be4f..00000000000 --- a/arch/mips/include/asm/netlogic/xlr/msidef.h +++ /dev/null | |||
@@ -1,84 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights | ||
3 | * reserved. | ||
4 | * | ||
5 | * This software is available to you under a choice of one of two | ||
6 | * licenses. You may choose to be licensed under the terms of the GNU | ||
7 | * General Public License (GPL) Version 2, available from the file | ||
8 | * COPYING in the main directory of this source tree, or the NetLogic | ||
9 | * license below: | ||
10 | * | ||
11 | * Redistribution and use in source and binary forms, with or without | ||
12 | * modification, are permitted provided that the following conditions | ||
13 | * are met: | ||
14 | * | ||
15 | * 1. Redistributions of source code must retain the above copyright | ||
16 | * notice, this list of conditions and the following disclaimer. | ||
17 | * 2. Redistributions in binary form must reproduce the above copyright | ||
18 | * notice, this list of conditions and the following disclaimer in | ||
19 | * the documentation and/or other materials provided with the | ||
20 | * distribution. | ||
21 | * | ||
22 | * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR | ||
23 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | ||
24 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | ||
25 | * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE | ||
26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | ||
27 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | ||
28 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR | ||
29 | * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, | ||
30 | * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE | ||
31 | * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN | ||
32 | * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | ||
33 | */ | ||
34 | |||
35 | #ifndef ASM_RMI_MSIDEF_H | ||
36 | #define ASM_RMI_MSIDEF_H | ||
37 | |||
38 | /* | ||
39 | * Constants for Intel APIC based MSI messages. | ||
40 | * Adapted for the RMI XLR using identical defines | ||
41 | */ | ||
42 | |||
43 | /* | ||
44 | * Shifts for MSI data | ||
45 | */ | ||
46 | |||
47 | #define MSI_DATA_VECTOR_SHIFT 0 | ||
48 | #define MSI_DATA_VECTOR_MASK 0x000000ff | ||
49 | #define MSI_DATA_VECTOR(v) (((v) << MSI_DATA_VECTOR_SHIFT) & \ | ||
50 | MSI_DATA_VECTOR_MASK) | ||
51 | |||
52 | #define MSI_DATA_DELIVERY_MODE_SHIFT 8 | ||
53 | #define MSI_DATA_DELIVERY_FIXED (0 << MSI_DATA_DELIVERY_MODE_SHIFT) | ||
54 | #define MSI_DATA_DELIVERY_LOWPRI (1 << MSI_DATA_DELIVERY_MODE_SHIFT) | ||
55 | |||
56 | #define MSI_DATA_LEVEL_SHIFT 14 | ||
57 | #define MSI_DATA_LEVEL_DEASSERT (0 << MSI_DATA_LEVEL_SHIFT) | ||
58 | #define MSI_DATA_LEVEL_ASSERT (1 << MSI_DATA_LEVEL_SHIFT) | ||
59 | |||
60 | #define MSI_DATA_TRIGGER_SHIFT 15 | ||
61 | #define MSI_DATA_TRIGGER_EDGE (0 << MSI_DATA_TRIGGER_SHIFT) | ||
62 | #define MSI_DATA_TRIGGER_LEVEL (1 << MSI_DATA_TRIGGER_SHIFT) | ||
63 | |||
64 | /* | ||
65 | * Shift/mask fields for msi address | ||
66 | */ | ||
67 | |||
68 | #define MSI_ADDR_BASE_HI 0 | ||
69 | #define MSI_ADDR_BASE_LO 0xfee00000 | ||
70 | |||
71 | #define MSI_ADDR_DEST_MODE_SHIFT 2 | ||
72 | #define MSI_ADDR_DEST_MODE_PHYSICAL (0 << MSI_ADDR_DEST_MODE_SHIFT) | ||
73 | #define MSI_ADDR_DEST_MODE_LOGICAL (1 << MSI_ADDR_DEST_MODE_SHIFT) | ||
74 | |||
75 | #define MSI_ADDR_REDIRECTION_SHIFT 3 | ||
76 | #define MSI_ADDR_REDIRECTION_CPU (0 << MSI_ADDR_REDIRECTION_SHIFT) | ||
77 | #define MSI_ADDR_REDIRECTION_LOWPRI (1 << MSI_ADDR_REDIRECTION_SHIFT) | ||
78 | |||
79 | #define MSI_ADDR_DEST_ID_SHIFT 12 | ||
80 | #define MSI_ADDR_DEST_ID_MASK 0x00ffff0 | ||
81 | #define MSI_ADDR_DEST_ID(dest) (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \ | ||
82 | MSI_ADDR_DEST_ID_MASK) | ||
83 | |||
84 | #endif /* ASM_RMI_MSIDEF_H */ | ||
diff --git a/arch/mips/include/asm/netlogic/xlr/pic.h b/arch/mips/include/asm/netlogic/xlr/pic.h index 9a691b1f91b..5cceb746f08 100644 --- a/arch/mips/include/asm/netlogic/xlr/pic.h +++ b/arch/mips/include/asm/netlogic/xlr/pic.h | |||
@@ -193,70 +193,39 @@ | |||
193 | /* end XLS */ | 193 | /* end XLS */ |
194 | 194 | ||
195 | #ifndef __ASSEMBLY__ | 195 | #ifndef __ASSEMBLY__ |
196 | 196 | static inline void pic_send_ipi(u32 ipi) | |
197 | #define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \ | ||
198 | ((irq) <= PIC_TIMER_7_IRQ)) | ||
199 | #define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \ | ||
200 | ((irq) <= PIC_IRT_LAST_IRQ)) | ||
201 | |||
202 | static inline int | ||
203 | nlm_irq_to_irt(int irq) | ||
204 | { | ||
205 | if (PIC_IRQ_IS_IRT(irq) == 0) | ||
206 | return -1; | ||
207 | |||
208 | return PIC_IRQ_TO_INTR(irq); | ||
209 | } | ||
210 | |||
211 | static inline int | ||
212 | nlm_irt_to_irq(int irt) | ||
213 | { | 197 | { |
198 | nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); | ||
214 | 199 | ||
215 | return PIC_INTR_TO_IRQ(irt); | 200 | netlogic_write_reg(mmio, PIC_IPI, ipi); |
216 | } | 201 | } |
217 | 202 | ||
218 | static inline void | 203 | static inline u32 pic_read_control(void) |
219 | nlm_pic_enable_irt(uint64_t base, int irt) | ||
220 | { | 204 | { |
221 | uint32_t reg; | 205 | nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); |
222 | 206 | ||
223 | reg = nlm_read_reg(base, PIC_IRT_1(irt)); | 207 | return netlogic_read_reg(mmio, PIC_CTRL); |
224 | nlm_write_reg(base, PIC_IRT_1(irt), reg | (1u << 31)); | ||
225 | } | 208 | } |
226 | 209 | ||
227 | static inline void | 210 | static inline void pic_write_control(u32 control) |
228 | nlm_pic_disable_irt(uint64_t base, int irt) | ||
229 | { | 211 | { |
230 | uint32_t reg; | 212 | nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); |
231 | 213 | ||
232 | reg = nlm_read_reg(base, PIC_IRT_1(irt)); | 214 | netlogic_write_reg(mmio, PIC_CTRL, control); |
233 | nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31)); | ||
234 | } | 215 | } |
235 | 216 | ||
236 | static inline void | 217 | static inline void pic_update_control(u32 control) |
237 | nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) | ||
238 | { | 218 | { |
239 | unsigned int tid, pid; | 219 | nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET); |
240 | 220 | ||
241 | tid = hwt & 0x3; | 221 | netlogic_write_reg(mmio, PIC_CTRL, |
242 | pid = (hwt >> 2) & 0x07; | 222 | (control | netlogic_read_reg(mmio, PIC_CTRL))); |
243 | nlm_write_reg(base, PIC_IPI, | ||
244 | (pid << 20) | (tid << 16) | (nmi << 8) | irq); | ||
245 | } | 223 | } |
246 | 224 | ||
247 | static inline void | 225 | #define PIC_IRQ_IS_EDGE_TRIGGERED(irq) (((irq) >= PIC_TIMER_0_IRQ) && \ |
248 | nlm_pic_ack(uint64_t base, int irt) | 226 | ((irq) <= PIC_TIMER_7_IRQ)) |
249 | { | 227 | #define PIC_IRQ_IS_IRT(irq) (((irq) >= PIC_IRT_FIRST_IRQ) && \ |
250 | nlm_write_reg(base, PIC_INT_ACK, 1u << irt); | 228 | ((irq) <= PIC_IRT_LAST_IRQ)) |
251 | } | ||
252 | |||
253 | static inline void | ||
254 | nlm_pic_init_irt(uint64_t base, int irt, int irq, int hwt) | ||
255 | { | ||
256 | nlm_write_reg(base, PIC_IRT_0(irt), (1u << hwt)); | ||
257 | /* local scheduling, invalid, level by default */ | ||
258 | nlm_write_reg(base, PIC_IRT_1(irt), | ||
259 | (1 << 30) | (1 << 6) | irq); | ||
260 | } | ||
261 | #endif | 229 | #endif |
230 | |||
262 | #endif /* _ASM_NLM_XLR_PIC_H */ | 231 | #endif /* _ASM_NLM_XLR_PIC_H */ |
diff --git a/arch/mips/include/asm/netlogic/xlr/xlr.h b/arch/mips/include/asm/netlogic/xlr/xlr.h index c1667e0c272..3e6372692a0 100644 --- a/arch/mips/include/asm/netlogic/xlr/xlr.h +++ b/arch/mips/include/asm/netlogic/xlr/xlr.h | |||
@@ -40,8 +40,17 @@ struct uart_port; | |||
40 | unsigned int nlm_xlr_uart_in(struct uart_port *, int); | 40 | unsigned int nlm_xlr_uart_in(struct uart_port *, int); |
41 | void nlm_xlr_uart_out(struct uart_port *, int, int); | 41 | void nlm_xlr_uart_out(struct uart_port *, int, int); |
42 | 42 | ||
43 | /* SMP helpers */ | 43 | /* SMP support functions */ |
44 | void xlr_wakeup_secondary_cpus(void); | 44 | struct irq_desc; |
45 | void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc); | ||
46 | void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc); | ||
47 | int nlm_wakeup_secondary_cpus(u32 wakeup_mask); | ||
48 | void nlm_smp_irq_init(void); | ||
49 | void nlm_boot_smp_nmi(void); | ||
50 | void prom_pre_boot_secondary_cpus(void); | ||
51 | |||
52 | extern struct plat_smp_ops nlm_smp_ops; | ||
53 | extern unsigned long nlm_common_ebase; | ||
45 | 54 | ||
46 | /* XLS B silicon "Rook" */ | 55 | /* XLS B silicon "Rook" */ |
47 | static inline unsigned int nlm_chip_is_xls_b(void) | 56 | static inline unsigned int nlm_chip_is_xls_b(void) |
@@ -51,8 +60,10 @@ static inline unsigned int nlm_chip_is_xls_b(void) | |||
51 | return ((prid & 0xf000) == 0x4000); | 60 | return ((prid & 0xf000) == 0x4000); |
52 | } | 61 | } |
53 | 62 | ||
54 | /* XLR chip types */ | 63 | /* |
55 | /* The XLS product line has chip versions 0x[48c]? */ | 64 | * XLR chip types |
65 | */ | ||
66 | /* The XLS product line has chip versions 0x[48c]? */ | ||
56 | static inline unsigned int nlm_chip_is_xls(void) | 67 | static inline unsigned int nlm_chip_is_xls(void) |
57 | { | 68 | { |
58 | uint32_t prid = read_c0_prid(); | 69 | uint32_t prid = read_c0_prid(); |