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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
commit8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch)
treea8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /arch/mips/include/asm/mach-bcm63xx
parent406089d01562f1e2bf9f089fd7637009ebaad589 (diff)
Patched in Tegra support.
Diffstat (limited to 'arch/mips/include/asm/mach-bcm63xx')
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h800
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h12
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h91
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h17
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h5
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h12
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h12
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h38
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h35
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h681
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h21
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h11
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h22
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h1
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/ioremap.h43
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/irq.h7
-rw-r--r--arch/mips/include/asm/mach-bcm63xx/war.h1
17 files changed, 267 insertions, 1542 deletions
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
index dbd5b5ad07a..96a2391ad85 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
@@ -9,31 +9,16 @@
9 * compile time if only one CPU support is enabled (idea stolen from 9 * compile time if only one CPU support is enabled (idea stolen from
10 * arm mach-types) 10 * arm mach-types)
11 */ 11 */
12#define BCM6328_CPU_ID 0x6328
13#define BCM6338_CPU_ID 0x6338 12#define BCM6338_CPU_ID 0x6338
14#define BCM6345_CPU_ID 0x6345 13#define BCM6345_CPU_ID 0x6345
15#define BCM6348_CPU_ID 0x6348 14#define BCM6348_CPU_ID 0x6348
16#define BCM6358_CPU_ID 0x6358 15#define BCM6358_CPU_ID 0x6358
17#define BCM6368_CPU_ID 0x6368
18 16
19void __init bcm63xx_cpu_init(void); 17void __init bcm63xx_cpu_init(void);
20u16 __bcm63xx_get_cpu_id(void); 18u16 __bcm63xx_get_cpu_id(void);
21u16 bcm63xx_get_cpu_rev(void); 19u16 bcm63xx_get_cpu_rev(void);
22unsigned int bcm63xx_get_cpu_freq(void); 20unsigned int bcm63xx_get_cpu_freq(void);
23 21
24#ifdef CONFIG_BCM63XX_CPU_6328
25# ifdef bcm63xx_get_cpu_id
26# undef bcm63xx_get_cpu_id
27# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
28# define BCMCPU_RUNTIME_DETECT
29# else
30# define bcm63xx_get_cpu_id() BCM6328_CPU_ID
31# endif
32# define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
33#else
34# define BCMCPU_IS_6328() (0)
35#endif
36
37#ifdef CONFIG_BCM63XX_CPU_6338 22#ifdef CONFIG_BCM63XX_CPU_6338
38# ifdef bcm63xx_get_cpu_id 23# ifdef bcm63xx_get_cpu_id
39# undef bcm63xx_get_cpu_id 24# undef bcm63xx_get_cpu_id
@@ -86,19 +71,6 @@ unsigned int bcm63xx_get_cpu_freq(void);
86# define BCMCPU_IS_6358() (0) 71# define BCMCPU_IS_6358() (0)
87#endif 72#endif
88 73
89#ifdef CONFIG_BCM63XX_CPU_6368
90# ifdef bcm63xx_get_cpu_id
91# undef bcm63xx_get_cpu_id
92# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
93# define BCMCPU_RUNTIME_DETECT
94# else
95# define bcm63xx_get_cpu_id() BCM6368_CPU_ID
96# endif
97# define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
98#else
99# define BCMCPU_IS_6368() (0)
100#endif
101
102#ifndef bcm63xx_get_cpu_id 74#ifndef bcm63xx_get_cpu_id
103#error "No CPU support configured" 75#error "No CPU support configured"
104#endif 76#endif
@@ -120,107 +92,30 @@ enum bcm63xx_regs_set {
120 RSET_OHCI0, 92 RSET_OHCI0,
121 RSET_OHCI_PRIV, 93 RSET_OHCI_PRIV,
122 RSET_USBH_PRIV, 94 RSET_USBH_PRIV,
123 RSET_USBD,
124 RSET_USBDMA,
125 RSET_MPI, 95 RSET_MPI,
126 RSET_PCMCIA, 96 RSET_PCMCIA,
127 RSET_PCIE,
128 RSET_DSL, 97 RSET_DSL,
129 RSET_ENET0, 98 RSET_ENET0,
130 RSET_ENET1, 99 RSET_ENET1,
131 RSET_ENETDMA, 100 RSET_ENETDMA,
132 RSET_ENETDMAC,
133 RSET_ENETDMAS,
134 RSET_ENETSW,
135 RSET_EHCI0, 101 RSET_EHCI0,
136 RSET_SDRAM, 102 RSET_SDRAM,
137 RSET_MEMC, 103 RSET_MEMC,
138 RSET_DDR, 104 RSET_DDR,
139 RSET_M2M,
140 RSET_ATM,
141 RSET_XTM,
142 RSET_XTMDMA,
143 RSET_XTMDMAC,
144 RSET_XTMDMAS,
145 RSET_PCM,
146 RSET_PCMDMA,
147 RSET_PCMDMAC,
148 RSET_PCMDMAS,
149 RSET_RNG,
150 RSET_MISC
151}; 105};
152 106
153#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) 107#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
154#define RSET_DSL_SIZE 4096 108#define RSET_DSL_SIZE 4096
155#define RSET_WDT_SIZE 12 109#define RSET_WDT_SIZE 12
156#define BCM_6338_RSET_SPI_SIZE 64
157#define BCM_6348_RSET_SPI_SIZE 64
158#define BCM_6358_RSET_SPI_SIZE 1804
159#define BCM_6368_RSET_SPI_SIZE 1804
160#define RSET_ENET_SIZE 2048 110#define RSET_ENET_SIZE 2048
161#define RSET_ENETDMA_SIZE 2048 111#define RSET_ENETDMA_SIZE 2048
162#define RSET_ENETSW_SIZE 65536
163#define RSET_UART_SIZE 24 112#define RSET_UART_SIZE 24
164#define RSET_UDC_SIZE 256 113#define RSET_UDC_SIZE 256
165#define RSET_OHCI_SIZE 256 114#define RSET_OHCI_SIZE 256
166#define RSET_EHCI_SIZE 256 115#define RSET_EHCI_SIZE 256
167#define RSET_USBD_SIZE 256
168#define RSET_USBDMA_SIZE 1280
169#define RSET_PCMCIA_SIZE 12 116#define RSET_PCMCIA_SIZE 12
170#define RSET_M2M_SIZE 256
171#define RSET_ATM_SIZE 4096
172#define RSET_XTM_SIZE 10240
173#define RSET_XTMDMA_SIZE 256
174#define RSET_XTMDMAC_SIZE(chans) (16 * (chans))
175#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
176#define RSET_RNG_SIZE 20
177 117
178/* 118/*
179 * 6328 register sets base address
180 */
181#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
182#define BCM_6328_PERF_BASE (0xb0000000)
183#define BCM_6328_TIMER_BASE (0xb0000040)
184#define BCM_6328_WDT_BASE (0xb000005c)
185#define BCM_6328_UART0_BASE (0xb0000100)
186#define BCM_6328_UART1_BASE (0xb0000120)
187#define BCM_6328_GPIO_BASE (0xb0000080)
188#define BCM_6328_SPI_BASE (0xdeadbeef)
189#define BCM_6328_UDC0_BASE (0xdeadbeef)
190#define BCM_6328_USBDMA_BASE (0xb000c000)
191#define BCM_6328_OHCI0_BASE (0xb0002600)
192#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
193#define BCM_6328_USBH_PRIV_BASE (0xb0002700)
194#define BCM_6328_USBD_BASE (0xb0002400)
195#define BCM_6328_MPI_BASE (0xdeadbeef)
196#define BCM_6328_PCMCIA_BASE (0xdeadbeef)
197#define BCM_6328_PCIE_BASE (0xb0e40000)
198#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
199#define BCM_6328_DSL_BASE (0xb0001900)
200#define BCM_6328_UBUS_BASE (0xdeadbeef)
201#define BCM_6328_ENET0_BASE (0xdeadbeef)
202#define BCM_6328_ENET1_BASE (0xdeadbeef)
203#define BCM_6328_ENETDMA_BASE (0xb000d800)
204#define BCM_6328_ENETDMAC_BASE (0xb000da00)
205#define BCM_6328_ENETDMAS_BASE (0xb000dc00)
206#define BCM_6328_ENETSW_BASE (0xb0e00000)
207#define BCM_6328_EHCI0_BASE (0xb0002500)
208#define BCM_6328_SDRAM_BASE (0xdeadbeef)
209#define BCM_6328_MEMC_BASE (0xdeadbeef)
210#define BCM_6328_DDR_BASE (0xb0003000)
211#define BCM_6328_M2M_BASE (0xdeadbeef)
212#define BCM_6328_ATM_BASE (0xdeadbeef)
213#define BCM_6328_XTM_BASE (0xdeadbeef)
214#define BCM_6328_XTMDMA_BASE (0xb000b800)
215#define BCM_6328_XTMDMAC_BASE (0xdeadbeef)
216#define BCM_6328_XTMDMAS_BASE (0xdeadbeef)
217#define BCM_6328_PCM_BASE (0xb000a800)
218#define BCM_6328_PCMDMA_BASE (0xdeadbeef)
219#define BCM_6328_PCMDMAC_BASE (0xdeadbeef)
220#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
221#define BCM_6328_RNG_BASE (0xdeadbeef)
222#define BCM_6328_MISC_BASE (0xb0001800)
223/*
224 * 6338 register sets base address 119 * 6338 register sets base address
225 */ 120 */
226#define BCM_6338_DSL_LMEM_BASE (0xfff00000) 121#define BCM_6338_DSL_LMEM_BASE (0xfff00000)
@@ -237,35 +132,19 @@ enum bcm63xx_regs_set {
237#define BCM_6338_OHCI0_BASE (0xdeadbeef) 132#define BCM_6338_OHCI0_BASE (0xdeadbeef)
238#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) 133#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000)
239#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) 134#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef)
240#define BCM_6338_USBD_BASE (0xdeadbeef)
241#define BCM_6338_MPI_BASE (0xfffe3160) 135#define BCM_6338_MPI_BASE (0xfffe3160)
242#define BCM_6338_PCMCIA_BASE (0xdeadbeef) 136#define BCM_6338_PCMCIA_BASE (0xdeadbeef)
243#define BCM_6338_PCIE_BASE (0xdeadbeef)
244#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) 137#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
245#define BCM_6338_DSL_BASE (0xfffe1000) 138#define BCM_6338_DSL_BASE (0xfffe1000)
139#define BCM_6338_SAR_BASE (0xfffe2000)
246#define BCM_6338_UBUS_BASE (0xdeadbeef) 140#define BCM_6338_UBUS_BASE (0xdeadbeef)
247#define BCM_6338_ENET0_BASE (0xfffe2800) 141#define BCM_6338_ENET0_BASE (0xfffe2800)
248#define BCM_6338_ENET1_BASE (0xdeadbeef) 142#define BCM_6338_ENET1_BASE (0xdeadbeef)
249#define BCM_6338_ENETDMA_BASE (0xfffe2400) 143#define BCM_6338_ENETDMA_BASE (0xfffe2400)
250#define BCM_6338_ENETDMAC_BASE (0xfffe2500)
251#define BCM_6338_ENETDMAS_BASE (0xfffe2600)
252#define BCM_6338_ENETSW_BASE (0xdeadbeef)
253#define BCM_6338_EHCI0_BASE (0xdeadbeef) 144#define BCM_6338_EHCI0_BASE (0xdeadbeef)
254#define BCM_6338_SDRAM_BASE (0xfffe3100) 145#define BCM_6338_SDRAM_BASE (0xfffe3100)
255#define BCM_6338_MEMC_BASE (0xdeadbeef) 146#define BCM_6338_MEMC_BASE (0xdeadbeef)
256#define BCM_6338_DDR_BASE (0xdeadbeef) 147#define BCM_6338_DDR_BASE (0xdeadbeef)
257#define BCM_6338_M2M_BASE (0xdeadbeef)
258#define BCM_6338_ATM_BASE (0xfffe2000)
259#define BCM_6338_XTM_BASE (0xdeadbeef)
260#define BCM_6338_XTMDMA_BASE (0xdeadbeef)
261#define BCM_6338_XTMDMAC_BASE (0xdeadbeef)
262#define BCM_6338_XTMDMAS_BASE (0xdeadbeef)
263#define BCM_6338_PCM_BASE (0xdeadbeef)
264#define BCM_6338_PCMDMA_BASE (0xdeadbeef)
265#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
266#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
267#define BCM_6338_RNG_BASE (0xdeadbeef)
268#define BCM_6338_MISC_BASE (0xdeadbeef)
269 148
270/* 149/*
271 * 6345 register sets base address 150 * 6345 register sets base address
@@ -283,36 +162,20 @@ enum bcm63xx_regs_set {
283#define BCM_6345_USBDMA_BASE (0xfffe2800) 162#define BCM_6345_USBDMA_BASE (0xfffe2800)
284#define BCM_6345_ENET0_BASE (0xfffe1800) 163#define BCM_6345_ENET0_BASE (0xfffe1800)
285#define BCM_6345_ENETDMA_BASE (0xfffe2800) 164#define BCM_6345_ENETDMA_BASE (0xfffe2800)
286#define BCM_6345_ENETDMAC_BASE (0xfffe2900)
287#define BCM_6345_ENETDMAS_BASE (0xfffe2a00)
288#define BCM_6345_ENETSW_BASE (0xdeadbeef)
289#define BCM_6345_PCMCIA_BASE (0xfffe2028) 165#define BCM_6345_PCMCIA_BASE (0xfffe2028)
290#define BCM_6345_MPI_BASE (0xfffe2000) 166#define BCM_6345_MPI_BASE (0xdeadbeef)
291#define BCM_6345_PCIE_BASE (0xdeadbeef)
292#define BCM_6345_OHCI0_BASE (0xfffe2100) 167#define BCM_6345_OHCI0_BASE (0xfffe2100)
293#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) 168#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200)
294#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) 169#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef)
295#define BCM_6345_USBD_BASE (0xdeadbeef)
296#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) 170#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300)
297#define BCM_6345_DSL_BASE (0xdeadbeef) 171#define BCM_6345_DSL_BASE (0xdeadbeef)
172#define BCM_6345_SAR_BASE (0xdeadbeef)
298#define BCM_6345_UBUS_BASE (0xdeadbeef) 173#define BCM_6345_UBUS_BASE (0xdeadbeef)
299#define BCM_6345_ENET1_BASE (0xdeadbeef) 174#define BCM_6345_ENET1_BASE (0xdeadbeef)
300#define BCM_6345_EHCI0_BASE (0xdeadbeef) 175#define BCM_6345_EHCI0_BASE (0xdeadbeef)
301#define BCM_6345_SDRAM_BASE (0xfffe2300) 176#define BCM_6345_SDRAM_BASE (0xfffe2300)
302#define BCM_6345_MEMC_BASE (0xdeadbeef) 177#define BCM_6345_MEMC_BASE (0xdeadbeef)
303#define BCM_6345_DDR_BASE (0xdeadbeef) 178#define BCM_6345_DDR_BASE (0xdeadbeef)
304#define BCM_6345_M2M_BASE (0xdeadbeef)
305#define BCM_6345_ATM_BASE (0xfffe4000)
306#define BCM_6345_XTM_BASE (0xdeadbeef)
307#define BCM_6345_XTMDMA_BASE (0xdeadbeef)
308#define BCM_6345_XTMDMAC_BASE (0xdeadbeef)
309#define BCM_6345_XTMDMAS_BASE (0xdeadbeef)
310#define BCM_6345_PCM_BASE (0xdeadbeef)
311#define BCM_6345_PCMDMA_BASE (0xdeadbeef)
312#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
313#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
314#define BCM_6345_RNG_BASE (0xdeadbeef)
315#define BCM_6345_MISC_BASE (0xdeadbeef)
316 179
317/* 180/*
318 * 6348 register sets base address 181 * 6348 register sets base address
@@ -326,38 +189,20 @@ enum bcm63xx_regs_set {
326#define BCM_6348_GPIO_BASE (0xfffe0400) 189#define BCM_6348_GPIO_BASE (0xfffe0400)
327#define BCM_6348_SPI_BASE (0xfffe0c00) 190#define BCM_6348_SPI_BASE (0xfffe0c00)
328#define BCM_6348_UDC0_BASE (0xfffe1000) 191#define BCM_6348_UDC0_BASE (0xfffe1000)
329#define BCM_6348_USBDMA_BASE (0xdeadbeef)
330#define BCM_6348_OHCI0_BASE (0xfffe1b00) 192#define BCM_6348_OHCI0_BASE (0xfffe1b00)
331#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) 193#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
332#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) 194#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
333#define BCM_6348_USBD_BASE (0xdeadbeef)
334#define BCM_6348_MPI_BASE (0xfffe2000) 195#define BCM_6348_MPI_BASE (0xfffe2000)
335#define BCM_6348_PCMCIA_BASE (0xfffe2054) 196#define BCM_6348_PCMCIA_BASE (0xfffe2054)
336#define BCM_6348_PCIE_BASE (0xdeadbeef)
337#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) 197#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
338#define BCM_6348_M2M_BASE (0xfffe2800)
339#define BCM_6348_DSL_BASE (0xfffe3000) 198#define BCM_6348_DSL_BASE (0xfffe3000)
340#define BCM_6348_ENET0_BASE (0xfffe6000) 199#define BCM_6348_ENET0_BASE (0xfffe6000)
341#define BCM_6348_ENET1_BASE (0xfffe6800) 200#define BCM_6348_ENET1_BASE (0xfffe6800)
342#define BCM_6348_ENETDMA_BASE (0xfffe7000) 201#define BCM_6348_ENETDMA_BASE (0xfffe7000)
343#define BCM_6348_ENETDMAC_BASE (0xfffe7100)
344#define BCM_6348_ENETDMAS_BASE (0xfffe7200)
345#define BCM_6348_ENETSW_BASE (0xdeadbeef)
346#define BCM_6348_EHCI0_BASE (0xdeadbeef) 202#define BCM_6348_EHCI0_BASE (0xdeadbeef)
347#define BCM_6348_SDRAM_BASE (0xfffe2300) 203#define BCM_6348_SDRAM_BASE (0xfffe2300)
348#define BCM_6348_MEMC_BASE (0xdeadbeef) 204#define BCM_6348_MEMC_BASE (0xdeadbeef)
349#define BCM_6348_DDR_BASE (0xdeadbeef) 205#define BCM_6348_DDR_BASE (0xdeadbeef)
350#define BCM_6348_ATM_BASE (0xfffe4000)
351#define BCM_6348_XTM_BASE (0xdeadbeef)
352#define BCM_6348_XTMDMA_BASE (0xdeadbeef)
353#define BCM_6348_XTMDMAC_BASE (0xdeadbeef)
354#define BCM_6348_XTMDMAS_BASE (0xdeadbeef)
355#define BCM_6348_PCM_BASE (0xdeadbeef)
356#define BCM_6348_PCMDMA_BASE (0xdeadbeef)
357#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
358#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
359#define BCM_6348_RNG_BASE (0xdeadbeef)
360#define BCM_6348_MISC_BASE (0xdeadbeef)
361 206
362/* 207/*
363 * 6358 register sets base address 208 * 6358 register sets base address
@@ -369,203 +214,222 @@ enum bcm63xx_regs_set {
369#define BCM_6358_UART0_BASE (0xfffe0100) 214#define BCM_6358_UART0_BASE (0xfffe0100)
370#define BCM_6358_UART1_BASE (0xfffe0120) 215#define BCM_6358_UART1_BASE (0xfffe0120)
371#define BCM_6358_GPIO_BASE (0xfffe0080) 216#define BCM_6358_GPIO_BASE (0xfffe0080)
372#define BCM_6358_SPI_BASE (0xfffe0800) 217#define BCM_6358_SPI_BASE (0xdeadbeef)
373#define BCM_6358_UDC0_BASE (0xfffe0800) 218#define BCM_6358_UDC0_BASE (0xfffe0800)
374#define BCM_6358_USBDMA_BASE (0xdeadbeef)
375#define BCM_6358_OHCI0_BASE (0xfffe1400) 219#define BCM_6358_OHCI0_BASE (0xfffe1400)
376#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) 220#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
377#define BCM_6358_USBH_PRIV_BASE (0xfffe1500) 221#define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
378#define BCM_6358_USBD_BASE (0xdeadbeef)
379#define BCM_6358_MPI_BASE (0xfffe1000) 222#define BCM_6358_MPI_BASE (0xfffe1000)
380#define BCM_6358_PCMCIA_BASE (0xfffe1054) 223#define BCM_6358_PCMCIA_BASE (0xfffe1054)
381#define BCM_6358_PCIE_BASE (0xdeadbeef)
382#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) 224#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
383#define BCM_6358_M2M_BASE (0xdeadbeef)
384#define BCM_6358_DSL_BASE (0xfffe3000) 225#define BCM_6358_DSL_BASE (0xfffe3000)
385#define BCM_6358_ENET0_BASE (0xfffe4000) 226#define BCM_6358_ENET0_BASE (0xfffe4000)
386#define BCM_6358_ENET1_BASE (0xfffe4800) 227#define BCM_6358_ENET1_BASE (0xfffe4800)
387#define BCM_6358_ENETDMA_BASE (0xfffe5000) 228#define BCM_6358_ENETDMA_BASE (0xfffe5000)
388#define BCM_6358_ENETDMAC_BASE (0xfffe5100)
389#define BCM_6358_ENETDMAS_BASE (0xfffe5200)
390#define BCM_6358_ENETSW_BASE (0xdeadbeef)
391#define BCM_6358_EHCI0_BASE (0xfffe1300) 229#define BCM_6358_EHCI0_BASE (0xfffe1300)
392#define BCM_6358_SDRAM_BASE (0xdeadbeef) 230#define BCM_6358_SDRAM_BASE (0xdeadbeef)
393#define BCM_6358_MEMC_BASE (0xfffe1200) 231#define BCM_6358_MEMC_BASE (0xfffe1200)
394#define BCM_6358_DDR_BASE (0xfffe12a0) 232#define BCM_6358_DDR_BASE (0xfffe12a0)
395#define BCM_6358_ATM_BASE (0xfffe2000)
396#define BCM_6358_XTM_BASE (0xdeadbeef)
397#define BCM_6358_XTMDMA_BASE (0xdeadbeef)
398#define BCM_6358_XTMDMAC_BASE (0xdeadbeef)
399#define BCM_6358_XTMDMAS_BASE (0xdeadbeef)
400#define BCM_6358_PCM_BASE (0xfffe1600)
401#define BCM_6358_PCMDMA_BASE (0xfffe1800)
402#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
403#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
404#define BCM_6358_RNG_BASE (0xdeadbeef)
405#define BCM_6358_MISC_BASE (0xdeadbeef)
406
407
408/*
409 * 6368 register sets base address
410 */
411#define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
412#define BCM_6368_PERF_BASE (0xb0000000)
413#define BCM_6368_TIMER_BASE (0xb0000040)
414#define BCM_6368_WDT_BASE (0xb000005c)
415#define BCM_6368_UART0_BASE (0xb0000100)
416#define BCM_6368_UART1_BASE (0xb0000120)
417#define BCM_6368_GPIO_BASE (0xb0000080)
418#define BCM_6368_SPI_BASE (0xb0000800)
419#define BCM_6368_UDC0_BASE (0xdeadbeef)
420#define BCM_6368_USBDMA_BASE (0xb0004800)
421#define BCM_6368_OHCI0_BASE (0xb0001600)
422#define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
423#define BCM_6368_USBH_PRIV_BASE (0xb0001700)
424#define BCM_6368_USBD_BASE (0xb0001400)
425#define BCM_6368_MPI_BASE (0xb0001000)
426#define BCM_6368_PCMCIA_BASE (0xb0001054)
427#define BCM_6368_PCIE_BASE (0xdeadbeef)
428#define BCM_6368_SDRAM_REGS_BASE (0xdeadbeef)
429#define BCM_6368_M2M_BASE (0xdeadbeef)
430#define BCM_6368_DSL_BASE (0xdeadbeef)
431#define BCM_6368_ENET0_BASE (0xdeadbeef)
432#define BCM_6368_ENET1_BASE (0xdeadbeef)
433#define BCM_6368_ENETDMA_BASE (0xb0006800)
434#define BCM_6368_ENETDMAC_BASE (0xb0006a00)
435#define BCM_6368_ENETDMAS_BASE (0xb0006c00)
436#define BCM_6368_ENETSW_BASE (0xb0f00000)
437#define BCM_6368_EHCI0_BASE (0xb0001500)
438#define BCM_6368_SDRAM_BASE (0xdeadbeef)
439#define BCM_6368_MEMC_BASE (0xb0001200)
440#define BCM_6368_DDR_BASE (0xb0001280)
441#define BCM_6368_ATM_BASE (0xdeadbeef)
442#define BCM_6368_XTM_BASE (0xb0001800)
443#define BCM_6368_XTMDMA_BASE (0xb0005000)
444#define BCM_6368_XTMDMAC_BASE (0xb0005200)
445#define BCM_6368_XTMDMAS_BASE (0xb0005400)
446#define BCM_6368_PCM_BASE (0xb0004000)
447#define BCM_6368_PCMDMA_BASE (0xb0005800)
448#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
449#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
450#define BCM_6368_RNG_BASE (0xb0004180)
451#define BCM_6368_MISC_BASE (0xdeadbeef)
452 233
453 234
454extern const unsigned long *bcm63xx_regs_base; 235extern const unsigned long *bcm63xx_regs_base;
455 236
456#define __GEN_RSET_BASE(__cpu, __rset) \
457 case RSET_## __rset : \
458 return BCM_## __cpu ##_## __rset ##_BASE;
459
460#define __GEN_RSET(__cpu) \
461 switch (set) { \
462 __GEN_RSET_BASE(__cpu, DSL_LMEM) \
463 __GEN_RSET_BASE(__cpu, PERF) \
464 __GEN_RSET_BASE(__cpu, TIMER) \
465 __GEN_RSET_BASE(__cpu, WDT) \
466 __GEN_RSET_BASE(__cpu, UART0) \
467 __GEN_RSET_BASE(__cpu, UART1) \
468 __GEN_RSET_BASE(__cpu, GPIO) \
469 __GEN_RSET_BASE(__cpu, SPI) \
470 __GEN_RSET_BASE(__cpu, UDC0) \
471 __GEN_RSET_BASE(__cpu, OHCI0) \
472 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
473 __GEN_RSET_BASE(__cpu, USBH_PRIV) \
474 __GEN_RSET_BASE(__cpu, USBD) \
475 __GEN_RSET_BASE(__cpu, USBDMA) \
476 __GEN_RSET_BASE(__cpu, MPI) \
477 __GEN_RSET_BASE(__cpu, PCMCIA) \
478 __GEN_RSET_BASE(__cpu, PCIE) \
479 __GEN_RSET_BASE(__cpu, DSL) \
480 __GEN_RSET_BASE(__cpu, ENET0) \
481 __GEN_RSET_BASE(__cpu, ENET1) \
482 __GEN_RSET_BASE(__cpu, ENETDMA) \
483 __GEN_RSET_BASE(__cpu, ENETDMAC) \
484 __GEN_RSET_BASE(__cpu, ENETDMAS) \
485 __GEN_RSET_BASE(__cpu, ENETSW) \
486 __GEN_RSET_BASE(__cpu, EHCI0) \
487 __GEN_RSET_BASE(__cpu, SDRAM) \
488 __GEN_RSET_BASE(__cpu, MEMC) \
489 __GEN_RSET_BASE(__cpu, DDR) \
490 __GEN_RSET_BASE(__cpu, M2M) \
491 __GEN_RSET_BASE(__cpu, ATM) \
492 __GEN_RSET_BASE(__cpu, XTM) \
493 __GEN_RSET_BASE(__cpu, XTMDMA) \
494 __GEN_RSET_BASE(__cpu, XTMDMAC) \
495 __GEN_RSET_BASE(__cpu, XTMDMAS) \
496 __GEN_RSET_BASE(__cpu, PCM) \
497 __GEN_RSET_BASE(__cpu, PCMDMA) \
498 __GEN_RSET_BASE(__cpu, PCMDMAC) \
499 __GEN_RSET_BASE(__cpu, PCMDMAS) \
500 __GEN_RSET_BASE(__cpu, RNG) \
501 __GEN_RSET_BASE(__cpu, MISC) \
502 }
503
504#define __GEN_CPU_REGS_TABLE(__cpu) \
505 [RSET_DSL_LMEM] = BCM_## __cpu ##_DSL_LMEM_BASE, \
506 [RSET_PERF] = BCM_## __cpu ##_PERF_BASE, \
507 [RSET_TIMER] = BCM_## __cpu ##_TIMER_BASE, \
508 [RSET_WDT] = BCM_## __cpu ##_WDT_BASE, \
509 [RSET_UART0] = BCM_## __cpu ##_UART0_BASE, \
510 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
511 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
512 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
513 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
514 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
515 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
516 [RSET_USBH_PRIV] = BCM_## __cpu ##_USBH_PRIV_BASE, \
517 [RSET_USBD] = BCM_## __cpu ##_USBD_BASE, \
518 [RSET_USBDMA] = BCM_## __cpu ##_USBDMA_BASE, \
519 [RSET_MPI] = BCM_## __cpu ##_MPI_BASE, \
520 [RSET_PCMCIA] = BCM_## __cpu ##_PCMCIA_BASE, \
521 [RSET_PCIE] = BCM_## __cpu ##_PCIE_BASE, \
522 [RSET_DSL] = BCM_## __cpu ##_DSL_BASE, \
523 [RSET_ENET0] = BCM_## __cpu ##_ENET0_BASE, \
524 [RSET_ENET1] = BCM_## __cpu ##_ENET1_BASE, \
525 [RSET_ENETDMA] = BCM_## __cpu ##_ENETDMA_BASE, \
526 [RSET_ENETDMAC] = BCM_## __cpu ##_ENETDMAC_BASE, \
527 [RSET_ENETDMAS] = BCM_## __cpu ##_ENETDMAS_BASE, \
528 [RSET_ENETSW] = BCM_## __cpu ##_ENETSW_BASE, \
529 [RSET_EHCI0] = BCM_## __cpu ##_EHCI0_BASE, \
530 [RSET_SDRAM] = BCM_## __cpu ##_SDRAM_BASE, \
531 [RSET_MEMC] = BCM_## __cpu ##_MEMC_BASE, \
532 [RSET_DDR] = BCM_## __cpu ##_DDR_BASE, \
533 [RSET_M2M] = BCM_## __cpu ##_M2M_BASE, \
534 [RSET_ATM] = BCM_## __cpu ##_ATM_BASE, \
535 [RSET_XTM] = BCM_## __cpu ##_XTM_BASE, \
536 [RSET_XTMDMA] = BCM_## __cpu ##_XTMDMA_BASE, \
537 [RSET_XTMDMAC] = BCM_## __cpu ##_XTMDMAC_BASE, \
538 [RSET_XTMDMAS] = BCM_## __cpu ##_XTMDMAS_BASE, \
539 [RSET_PCM] = BCM_## __cpu ##_PCM_BASE, \
540 [RSET_PCMDMA] = BCM_## __cpu ##_PCMDMA_BASE, \
541 [RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
542 [RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
543 [RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \
544 [RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
545
546
547static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) 237static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
548{ 238{
549#ifdef BCMCPU_RUNTIME_DETECT 239#ifdef BCMCPU_RUNTIME_DETECT
550 return bcm63xx_regs_base[set]; 240 return bcm63xx_regs_base[set];
551#else 241#else
552#ifdef CONFIG_BCM63XX_CPU_6328
553 __GEN_RSET(6328)
554#endif
555#ifdef CONFIG_BCM63XX_CPU_6338 242#ifdef CONFIG_BCM63XX_CPU_6338
556 __GEN_RSET(6338) 243 switch (set) {
244 case RSET_DSL_LMEM:
245 return BCM_6338_DSL_LMEM_BASE;
246 case RSET_PERF:
247 return BCM_6338_PERF_BASE;
248 case RSET_TIMER:
249 return BCM_6338_TIMER_BASE;
250 case RSET_WDT:
251 return BCM_6338_WDT_BASE;
252 case RSET_UART0:
253 return BCM_6338_UART0_BASE;
254 case RSET_UART1:
255 return BCM_6338_UART1_BASE;
256 case RSET_GPIO:
257 return BCM_6338_GPIO_BASE;
258 case RSET_SPI:
259 return BCM_6338_SPI_BASE;
260 case RSET_UDC0:
261 return BCM_6338_UDC0_BASE;
262 case RSET_OHCI0:
263 return BCM_6338_OHCI0_BASE;
264 case RSET_OHCI_PRIV:
265 return BCM_6338_OHCI_PRIV_BASE;
266 case RSET_USBH_PRIV:
267 return BCM_6338_USBH_PRIV_BASE;
268 case RSET_MPI:
269 return BCM_6338_MPI_BASE;
270 case RSET_PCMCIA:
271 return BCM_6338_PCMCIA_BASE;
272 case RSET_DSL:
273 return BCM_6338_DSL_BASE;
274 case RSET_ENET0:
275 return BCM_6338_ENET0_BASE;
276 case RSET_ENET1:
277 return BCM_6338_ENET1_BASE;
278 case RSET_ENETDMA:
279 return BCM_6338_ENETDMA_BASE;
280 case RSET_EHCI0:
281 return BCM_6338_EHCI0_BASE;
282 case RSET_SDRAM:
283 return BCM_6338_SDRAM_BASE;
284 case RSET_MEMC:
285 return BCM_6338_MEMC_BASE;
286 case RSET_DDR:
287 return BCM_6338_DDR_BASE;
288 }
557#endif 289#endif
558#ifdef CONFIG_BCM63XX_CPU_6345 290#ifdef CONFIG_BCM63XX_CPU_6345
559 __GEN_RSET(6345) 291 switch (set) {
292 case RSET_DSL_LMEM:
293 return BCM_6345_DSL_LMEM_BASE;
294 case RSET_PERF:
295 return BCM_6345_PERF_BASE;
296 case RSET_TIMER:
297 return BCM_6345_TIMER_BASE;
298 case RSET_WDT:
299 return BCM_6345_WDT_BASE;
300 case RSET_UART0:
301 return BCM_6345_UART0_BASE;
302 case RSET_UART1:
303 return BCM_6345_UART1_BASE;
304 case RSET_GPIO:
305 return BCM_6345_GPIO_BASE;
306 case RSET_SPI:
307 return BCM_6345_SPI_BASE;
308 case RSET_UDC0:
309 return BCM_6345_UDC0_BASE;
310 case RSET_OHCI0:
311 return BCM_6345_OHCI0_BASE;
312 case RSET_OHCI_PRIV:
313 return BCM_6345_OHCI_PRIV_BASE;
314 case RSET_USBH_PRIV:
315 return BCM_6345_USBH_PRIV_BASE;
316 case RSET_MPI:
317 return BCM_6345_MPI_BASE;
318 case RSET_PCMCIA:
319 return BCM_6345_PCMCIA_BASE;
320 case RSET_DSL:
321 return BCM_6345_DSL_BASE;
322 case RSET_ENET0:
323 return BCM_6345_ENET0_BASE;
324 case RSET_ENET1:
325 return BCM_6345_ENET1_BASE;
326 case RSET_ENETDMA:
327 return BCM_6345_ENETDMA_BASE;
328 case RSET_EHCI0:
329 return BCM_6345_EHCI0_BASE;
330 case RSET_SDRAM:
331 return BCM_6345_SDRAM_BASE;
332 case RSET_MEMC:
333 return BCM_6345_MEMC_BASE;
334 case RSET_DDR:
335 return BCM_6345_DDR_BASE;
336 }
560#endif 337#endif
561#ifdef CONFIG_BCM63XX_CPU_6348 338#ifdef CONFIG_BCM63XX_CPU_6348
562 __GEN_RSET(6348) 339 switch (set) {
340 case RSET_DSL_LMEM:
341 return BCM_6348_DSL_LMEM_BASE;
342 case RSET_PERF:
343 return BCM_6348_PERF_BASE;
344 case RSET_TIMER:
345 return BCM_6348_TIMER_BASE;
346 case RSET_WDT:
347 return BCM_6348_WDT_BASE;
348 case RSET_UART0:
349 return BCM_6348_UART0_BASE;
350 case RSET_UART1:
351 return BCM_6348_UART1_BASE;
352 case RSET_GPIO:
353 return BCM_6348_GPIO_BASE;
354 case RSET_SPI:
355 return BCM_6348_SPI_BASE;
356 case RSET_UDC0:
357 return BCM_6348_UDC0_BASE;
358 case RSET_OHCI0:
359 return BCM_6348_OHCI0_BASE;
360 case RSET_OHCI_PRIV:
361 return BCM_6348_OHCI_PRIV_BASE;
362 case RSET_USBH_PRIV:
363 return BCM_6348_USBH_PRIV_BASE;
364 case RSET_MPI:
365 return BCM_6348_MPI_BASE;
366 case RSET_PCMCIA:
367 return BCM_6348_PCMCIA_BASE;
368 case RSET_DSL:
369 return BCM_6348_DSL_BASE;
370 case RSET_ENET0:
371 return BCM_6348_ENET0_BASE;
372 case RSET_ENET1:
373 return BCM_6348_ENET1_BASE;
374 case RSET_ENETDMA:
375 return BCM_6348_ENETDMA_BASE;
376 case RSET_EHCI0:
377 return BCM_6348_EHCI0_BASE;
378 case RSET_SDRAM:
379 return BCM_6348_SDRAM_BASE;
380 case RSET_MEMC:
381 return BCM_6348_MEMC_BASE;
382 case RSET_DDR:
383 return BCM_6348_DDR_BASE;
384 }
563#endif 385#endif
564#ifdef CONFIG_BCM63XX_CPU_6358 386#ifdef CONFIG_BCM63XX_CPU_6358
565 __GEN_RSET(6358) 387 switch (set) {
566#endif 388 case RSET_DSL_LMEM:
567#ifdef CONFIG_BCM63XX_CPU_6368 389 return BCM_6358_DSL_LMEM_BASE;
568 __GEN_RSET(6368) 390 case RSET_PERF:
391 return BCM_6358_PERF_BASE;
392 case RSET_TIMER:
393 return BCM_6358_TIMER_BASE;
394 case RSET_WDT:
395 return BCM_6358_WDT_BASE;
396 case RSET_UART0:
397 return BCM_6358_UART0_BASE;
398 case RSET_UART1:
399 return BCM_6358_UART1_BASE;
400 case RSET_GPIO:
401 return BCM_6358_GPIO_BASE;
402 case RSET_SPI:
403 return BCM_6358_SPI_BASE;
404 case RSET_UDC0:
405 return BCM_6358_UDC0_BASE;
406 case RSET_OHCI0:
407 return BCM_6358_OHCI0_BASE;
408 case RSET_OHCI_PRIV:
409 return BCM_6358_OHCI_PRIV_BASE;
410 case RSET_USBH_PRIV:
411 return BCM_6358_USBH_PRIV_BASE;
412 case RSET_MPI:
413 return BCM_6358_MPI_BASE;
414 case RSET_PCMCIA:
415 return BCM_6358_PCMCIA_BASE;
416 case RSET_ENET0:
417 return BCM_6358_ENET0_BASE;
418 case RSET_ENET1:
419 return BCM_6358_ENET1_BASE;
420 case RSET_ENETDMA:
421 return BCM_6358_ENETDMA_BASE;
422 case RSET_DSL:
423 return BCM_6358_DSL_BASE;
424 case RSET_EHCI0:
425 return BCM_6358_EHCI0_BASE;
426 case RSET_SDRAM:
427 return BCM_6358_SDRAM_BASE;
428 case RSET_MEMC:
429 return BCM_6358_MEMC_BASE;
430 case RSET_DDR:
431 return BCM_6358_DDR_BASE;
432 }
569#endif 433#endif
570#endif 434#endif
571 /* unreached */ 435 /* unreached */
@@ -577,7 +441,6 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
577 */ 441 */
578enum bcm63xx_irq { 442enum bcm63xx_irq {
579 IRQ_TIMER = 0, 443 IRQ_TIMER = 0,
580 IRQ_SPI,
581 IRQ_UART0, 444 IRQ_UART0,
582 IRQ_UART1, 445 IRQ_UART1,
583 IRQ_DSL, 446 IRQ_DSL,
@@ -586,326 +449,97 @@ enum bcm63xx_irq {
586 IRQ_ENET_PHY, 449 IRQ_ENET_PHY,
587 IRQ_OHCI0, 450 IRQ_OHCI0,
588 IRQ_EHCI0, 451 IRQ_EHCI0,
589 IRQ_USBD, 452 IRQ_PCMCIA0,
590 IRQ_USBD_RXDMA0,
591 IRQ_USBD_TXDMA0,
592 IRQ_USBD_RXDMA1,
593 IRQ_USBD_TXDMA1,
594 IRQ_USBD_RXDMA2,
595 IRQ_USBD_TXDMA2,
596 IRQ_ENET0_RXDMA, 453 IRQ_ENET0_RXDMA,
597 IRQ_ENET0_TXDMA, 454 IRQ_ENET0_TXDMA,
598 IRQ_ENET1_RXDMA, 455 IRQ_ENET1_RXDMA,
599 IRQ_ENET1_TXDMA, 456 IRQ_ENET1_TXDMA,
600 IRQ_PCI, 457 IRQ_PCI,
601 IRQ_PCMCIA, 458 IRQ_PCMCIA,
602 IRQ_ATM,
603 IRQ_ENETSW_RXDMA0,
604 IRQ_ENETSW_RXDMA1,
605 IRQ_ENETSW_RXDMA2,
606 IRQ_ENETSW_RXDMA3,
607 IRQ_ENETSW_TXDMA0,
608 IRQ_ENETSW_TXDMA1,
609 IRQ_ENETSW_TXDMA2,
610 IRQ_ENETSW_TXDMA3,
611 IRQ_XTM,
612 IRQ_XTM_DMA0,
613}; 459};
614 460
615/* 461/*
616 * 6328 irqs
617 */
618#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
619
620#define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
621#define BCM_6328_SPI_IRQ 0
622#define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
623#define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
624#define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
625#define BCM_6328_UDC0_IRQ 0
626#define BCM_6328_ENET0_IRQ 0
627#define BCM_6328_ENET1_IRQ 0
628#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
629#define BCM_6328_OHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 9)
630#define BCM_6328_EHCI0_IRQ (BCM_6328_HIGH_IRQ_BASE + 10)
631#define BCM_6328_USBD_IRQ (IRQ_INTERNAL_BASE + 4)
632#define BCM_6328_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 5)
633#define BCM_6328_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 6)
634#define BCM_6328_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 7)
635#define BCM_6328_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 8)
636#define BCM_6328_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 9)
637#define BCM_6328_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 10)
638#define BCM_6328_PCMCIA_IRQ 0
639#define BCM_6328_ENET0_RXDMA_IRQ 0
640#define BCM_6328_ENET0_TXDMA_IRQ 0
641#define BCM_6328_ENET1_RXDMA_IRQ 0
642#define BCM_6328_ENET1_TXDMA_IRQ 0
643#define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
644#define BCM_6328_ATM_IRQ 0
645#define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0)
646#define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1)
647#define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2)
648#define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3)
649#define BCM_6328_ENETSW_TXDMA0_IRQ 0
650#define BCM_6328_ENETSW_TXDMA1_IRQ 0
651#define BCM_6328_ENETSW_TXDMA2_IRQ 0
652#define BCM_6328_ENETSW_TXDMA3_IRQ 0
653#define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31)
654#define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11)
655
656#define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
657#define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
658#define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
659#define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
660#define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
661#define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
662
663/*
664 * 6338 irqs 462 * 6338 irqs
665 */ 463 */
666#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 464#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
667#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1) 465#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
668#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 466#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
669#define BCM_6338_UART1_IRQ 0 467#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
670#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) 468#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
469#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
470#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
671#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 471#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
672#define BCM_6338_ENET1_IRQ 0
673#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 472#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
674#define BCM_6338_OHCI0_IRQ 0 473#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
675#define BCM_6338_EHCI0_IRQ 0 474#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11)
676#define BCM_6338_USBD_IRQ 0 475#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
677#define BCM_6338_USBD_RXDMA0_IRQ 0 476#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
678#define BCM_6338_USBD_TXDMA0_IRQ 0 477#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
679#define BCM_6338_USBD_RXDMA1_IRQ 0
680#define BCM_6338_USBD_TXDMA1_IRQ 0
681#define BCM_6338_USBD_RXDMA2_IRQ 0
682#define BCM_6338_USBD_TXDMA2_IRQ 0
683#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 478#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
684#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 479#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
685#define BCM_6338_ENET1_RXDMA_IRQ 0 480#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
686#define BCM_6338_ENET1_TXDMA_IRQ 0
687#define BCM_6338_PCI_IRQ 0
688#define BCM_6338_PCMCIA_IRQ 0
689#define BCM_6338_ATM_IRQ 0
690#define BCM_6338_ENETSW_RXDMA0_IRQ 0
691#define BCM_6338_ENETSW_RXDMA1_IRQ 0
692#define BCM_6338_ENETSW_RXDMA2_IRQ 0
693#define BCM_6338_ENETSW_RXDMA3_IRQ 0
694#define BCM_6338_ENETSW_TXDMA0_IRQ 0
695#define BCM_6338_ENETSW_TXDMA1_IRQ 0
696#define BCM_6338_ENETSW_TXDMA2_IRQ 0
697#define BCM_6338_ENETSW_TXDMA3_IRQ 0
698#define BCM_6338_XTM_IRQ 0
699#define BCM_6338_XTM_DMA0_IRQ 0
700 481
701/* 482/*
702 * 6345 irqs 483 * 6345 irqs
703 */ 484 */
704#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 485#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
705#define BCM_6345_SPI_IRQ 0
706#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 486#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
707#define BCM_6345_UART1_IRQ 0
708#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) 487#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
488#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
489#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
709#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) 490#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
710#define BCM_6345_ENET1_IRQ 0
711#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) 491#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
712#define BCM_6345_OHCI0_IRQ 0
713#define BCM_6345_EHCI0_IRQ 0
714#define BCM_6345_USBD_IRQ 0
715#define BCM_6345_USBD_RXDMA0_IRQ 0
716#define BCM_6345_USBD_TXDMA0_IRQ 0
717#define BCM_6345_USBD_RXDMA1_IRQ 0
718#define BCM_6345_USBD_TXDMA1_IRQ 0
719#define BCM_6345_USBD_RXDMA2_IRQ 0
720#define BCM_6345_USBD_TXDMA2_IRQ 0
721#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) 492#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
722#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) 493#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2)
723#define BCM_6345_ENET1_RXDMA_IRQ 0 494#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5)
724#define BCM_6345_ENET1_TXDMA_IRQ 0 495#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6)
725#define BCM_6345_PCI_IRQ 0 496#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9)
726#define BCM_6345_PCMCIA_IRQ 0 497#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10)
727#define BCM_6345_ATM_IRQ 0 498#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13)
728#define BCM_6345_ENETSW_RXDMA0_IRQ 0 499#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14)
729#define BCM_6345_ENETSW_RXDMA1_IRQ 0 500#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15)
730#define BCM_6345_ENETSW_RXDMA2_IRQ 0 501#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16)
731#define BCM_6345_ENETSW_RXDMA3_IRQ 0 502#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17)
732#define BCM_6345_ENETSW_TXDMA0_IRQ 0 503#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18)
733#define BCM_6345_ENETSW_TXDMA1_IRQ 0
734#define BCM_6345_ENETSW_TXDMA2_IRQ 0
735#define BCM_6345_ENETSW_TXDMA3_IRQ 0
736#define BCM_6345_XTM_IRQ 0
737#define BCM_6345_XTM_DMA0_IRQ 0
738 504
739/* 505/*
740 * 6348 irqs 506 * 6348 irqs
741 */ 507 */
742#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 508#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
743#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
744#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 509#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
745#define BCM_6348_UART1_IRQ 0
746#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) 510#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
747#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
748#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) 511#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
512#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
749#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 513#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
750#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) 514#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
751#define BCM_6348_EHCI0_IRQ 0
752#define BCM_6348_USBD_IRQ 0
753#define BCM_6348_USBD_RXDMA0_IRQ 0
754#define BCM_6348_USBD_TXDMA0_IRQ 0
755#define BCM_6348_USBD_RXDMA1_IRQ 0
756#define BCM_6348_USBD_TXDMA1_IRQ 0
757#define BCM_6348_USBD_RXDMA2_IRQ 0
758#define BCM_6348_USBD_TXDMA2_IRQ 0
759#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) 515#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
760#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) 516#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
761#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) 517#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
762#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) 518#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
763#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
764#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 519#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
765#define BCM_6348_ATM_IRQ (IRQ_INTERNAL_BASE + 5) 520#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
766#define BCM_6348_ENETSW_RXDMA0_IRQ 0
767#define BCM_6348_ENETSW_RXDMA1_IRQ 0
768#define BCM_6348_ENETSW_RXDMA2_IRQ 0
769#define BCM_6348_ENETSW_RXDMA3_IRQ 0
770#define BCM_6348_ENETSW_TXDMA0_IRQ 0
771#define BCM_6348_ENETSW_TXDMA1_IRQ 0
772#define BCM_6348_ENETSW_TXDMA2_IRQ 0
773#define BCM_6348_ENETSW_TXDMA3_IRQ 0
774#define BCM_6348_XTM_IRQ 0
775#define BCM_6348_XTM_DMA0_IRQ 0
776 521
777/* 522/*
778 * 6358 irqs 523 * 6358 irqs
779 */ 524 */
780#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) 525#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
781#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
782#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) 526#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
783#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3) 527#define BCM_6358_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
784#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) 528#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
785#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
786#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) 529#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
530#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
787#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) 531#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
788#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
789#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) 532#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
790#define BCM_6358_USBD_IRQ 0
791#define BCM_6358_USBD_RXDMA0_IRQ 0
792#define BCM_6358_USBD_TXDMA0_IRQ 0
793#define BCM_6358_USBD_RXDMA1_IRQ 0
794#define BCM_6358_USBD_TXDMA1_IRQ 0
795#define BCM_6358_USBD_RXDMA2_IRQ 0
796#define BCM_6358_USBD_TXDMA2_IRQ 0
797#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) 533#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
798#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) 534#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
799#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) 535#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
800#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) 536#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
537#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
801#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) 538#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
802#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) 539#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
803#define BCM_6358_ATM_IRQ (IRQ_INTERNAL_BASE + 19)
804#define BCM_6358_ENETSW_RXDMA0_IRQ 0
805#define BCM_6358_ENETSW_RXDMA1_IRQ 0
806#define BCM_6358_ENETSW_RXDMA2_IRQ 0
807#define BCM_6358_ENETSW_RXDMA3_IRQ 0
808#define BCM_6358_ENETSW_TXDMA0_IRQ 0
809#define BCM_6358_ENETSW_TXDMA1_IRQ 0
810#define BCM_6358_ENETSW_TXDMA2_IRQ 0
811#define BCM_6358_ENETSW_TXDMA3_IRQ 0
812#define BCM_6358_XTM_IRQ 0
813#define BCM_6358_XTM_DMA0_IRQ 0
814
815#define BCM_6358_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 23)
816#define BCM_6358_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 24)
817#define BCM_6358_EXT_IRQ0 (IRQ_INTERNAL_BASE + 25)
818#define BCM_6358_EXT_IRQ1 (IRQ_INTERNAL_BASE + 26)
819#define BCM_6358_EXT_IRQ2 (IRQ_INTERNAL_BASE + 27)
820#define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
821
822/*
823 * 6368 irqs
824 */
825#define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
826
827#define BCM_6368_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
828#define BCM_6368_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
829#define BCM_6368_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
830#define BCM_6368_UART1_IRQ (IRQ_INTERNAL_BASE + 3)
831#define BCM_6368_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
832#define BCM_6368_ENET0_IRQ 0
833#define BCM_6368_ENET1_IRQ 0
834#define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
835#define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
836#define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
837#define BCM_6368_USBD_IRQ (IRQ_INTERNAL_BASE + 8)
838#define BCM_6368_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 26)
839#define BCM_6368_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 27)
840#define BCM_6368_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 28)
841#define BCM_6368_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 29)
842#define BCM_6368_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 30)
843#define BCM_6368_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 31)
844#define BCM_6368_PCMCIA_IRQ 0
845#define BCM_6368_ENET0_RXDMA_IRQ 0
846#define BCM_6368_ENET0_TXDMA_IRQ 0
847#define BCM_6368_ENET1_RXDMA_IRQ 0
848#define BCM_6368_ENET1_TXDMA_IRQ 0
849#define BCM_6368_PCI_IRQ (IRQ_INTERNAL_BASE + 13)
850#define BCM_6368_ATM_IRQ 0
851#define BCM_6368_ENETSW_RXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 0)
852#define BCM_6368_ENETSW_RXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 1)
853#define BCM_6368_ENETSW_RXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 2)
854#define BCM_6368_ENETSW_RXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 3)
855#define BCM_6368_ENETSW_TXDMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 4)
856#define BCM_6368_ENETSW_TXDMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 5)
857#define BCM_6368_ENETSW_TXDMA2_IRQ (BCM_6368_HIGH_IRQ_BASE + 6)
858#define BCM_6368_ENETSW_TXDMA3_IRQ (BCM_6368_HIGH_IRQ_BASE + 7)
859#define BCM_6368_XTM_IRQ (IRQ_INTERNAL_BASE + 11)
860#define BCM_6368_XTM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 8)
861
862#define BCM_6368_PCM_DMA0_IRQ (BCM_6368_HIGH_IRQ_BASE + 30)
863#define BCM_6368_PCM_DMA1_IRQ (BCM_6368_HIGH_IRQ_BASE + 31)
864#define BCM_6368_EXT_IRQ0 (IRQ_INTERNAL_BASE + 20)
865#define BCM_6368_EXT_IRQ1 (IRQ_INTERNAL_BASE + 21)
866#define BCM_6368_EXT_IRQ2 (IRQ_INTERNAL_BASE + 22)
867#define BCM_6368_EXT_IRQ3 (IRQ_INTERNAL_BASE + 23)
868#define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
869#define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
870 540
871extern const int *bcm63xx_irqs; 541extern const int *bcm63xx_irqs;
872 542
873#define __GEN_CPU_IRQ_TABLE(__cpu) \
874 [IRQ_TIMER] = BCM_## __cpu ##_TIMER_IRQ, \
875 [IRQ_SPI] = BCM_## __cpu ##_SPI_IRQ, \
876 [IRQ_UART0] = BCM_## __cpu ##_UART0_IRQ, \
877 [IRQ_UART1] = BCM_## __cpu ##_UART1_IRQ, \
878 [IRQ_DSL] = BCM_## __cpu ##_DSL_IRQ, \
879 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
880 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
881 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
882 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
883 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
884 [IRQ_USBD] = BCM_## __cpu ##_USBD_IRQ, \
885 [IRQ_USBD_RXDMA0] = BCM_## __cpu ##_USBD_RXDMA0_IRQ, \
886 [IRQ_USBD_TXDMA0] = BCM_## __cpu ##_USBD_TXDMA0_IRQ, \
887 [IRQ_USBD_RXDMA1] = BCM_## __cpu ##_USBD_RXDMA1_IRQ, \
888 [IRQ_USBD_TXDMA1] = BCM_## __cpu ##_USBD_TXDMA1_IRQ, \
889 [IRQ_USBD_RXDMA2] = BCM_## __cpu ##_USBD_RXDMA2_IRQ, \
890 [IRQ_USBD_TXDMA2] = BCM_## __cpu ##_USBD_TXDMA2_IRQ, \
891 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
892 [IRQ_ENET0_TXDMA] = BCM_## __cpu ##_ENET0_TXDMA_IRQ, \
893 [IRQ_ENET1_RXDMA] = BCM_## __cpu ##_ENET1_RXDMA_IRQ, \
894 [IRQ_ENET1_TXDMA] = BCM_## __cpu ##_ENET1_TXDMA_IRQ, \
895 [IRQ_PCI] = BCM_## __cpu ##_PCI_IRQ, \
896 [IRQ_PCMCIA] = BCM_## __cpu ##_PCMCIA_IRQ, \
897 [IRQ_ATM] = BCM_## __cpu ##_ATM_IRQ, \
898 [IRQ_ENETSW_RXDMA0] = BCM_## __cpu ##_ENETSW_RXDMA0_IRQ, \
899 [IRQ_ENETSW_RXDMA1] = BCM_## __cpu ##_ENETSW_RXDMA1_IRQ, \
900 [IRQ_ENETSW_RXDMA2] = BCM_## __cpu ##_ENETSW_RXDMA2_IRQ, \
901 [IRQ_ENETSW_RXDMA3] = BCM_## __cpu ##_ENETSW_RXDMA3_IRQ, \
902 [IRQ_ENETSW_TXDMA0] = BCM_## __cpu ##_ENETSW_TXDMA0_IRQ, \
903 [IRQ_ENETSW_TXDMA1] = BCM_## __cpu ##_ENETSW_TXDMA1_IRQ, \
904 [IRQ_ENETSW_TXDMA2] = BCM_## __cpu ##_ENETSW_TXDMA2_IRQ, \
905 [IRQ_ENETSW_TXDMA3] = BCM_## __cpu ##_ENETSW_TXDMA3_IRQ, \
906 [IRQ_XTM] = BCM_## __cpu ##_XTM_IRQ, \
907 [IRQ_XTM_DMA0] = BCM_## __cpu ##_XTM_DMA0_IRQ, \
908
909static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) 543static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
910{ 544{
911 return bcm63xx_irqs[irq]; 545 return bcm63xx_irqs[irq];
@@ -916,8 +550,4 @@ static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
916 */ 550 */
917unsigned int bcm63xx_get_memory_size(void); 551unsigned int bcm63xx_get_memory_size(void);
918 552
919void bcm63xx_machine_halt(void);
920
921void bcm63xx_machine_reboot(void);
922
923#endif /* !BCM63XX_CPU_H_ */ 553#endif /* !BCM63XX_CPU_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
deleted file mode 100644
index 354b8481ec4..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_flash.h
+++ /dev/null
@@ -1,12 +0,0 @@
1#ifndef __BCM63XX_FLASH_H
2#define __BCM63XX_FLASH_H
3
4enum {
5 BCM63XX_FLASH_TYPE_PARALLEL,
6 BCM63XX_FLASH_TYPE_SERIAL,
7 BCM63XX_FLASH_TYPE_NAND,
8};
9
10int __init bcm63xx_flash_register(void);
11
12#endif /* __BCM63XX_FLASH_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
deleted file mode 100644
index c9bae136260..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
+++ /dev/null
@@ -1,91 +0,0 @@
1#ifndef BCM63XX_DEV_SPI_H
2#define BCM63XX_DEV_SPI_H
3
4#include <linux/types.h>
5#include <bcm63xx_io.h>
6#include <bcm63xx_regs.h>
7
8int __init bcm63xx_spi_register(void);
9
10struct bcm63xx_spi_pdata {
11 unsigned int fifo_size;
12 unsigned int msg_type_shift;
13 unsigned int msg_ctl_width;
14 int bus_num;
15 int num_chipselect;
16 u32 speed_hz;
17};
18
19enum bcm63xx_regs_spi {
20 SPI_CMD,
21 SPI_INT_STATUS,
22 SPI_INT_MASK_ST,
23 SPI_INT_MASK,
24 SPI_ST,
25 SPI_CLK_CFG,
26 SPI_FILL_BYTE,
27 SPI_MSG_TAIL,
28 SPI_RX_TAIL,
29 SPI_MSG_CTL,
30 SPI_MSG_DATA,
31 SPI_RX_DATA,
32};
33
34#define __GEN_SPI_RSET_BASE(__cpu, __rset) \
35 case SPI_## __rset: \
36 return SPI_## __cpu ##_## __rset;
37
38#define __GEN_SPI_RSET(__cpu) \
39 switch (reg) { \
40 __GEN_SPI_RSET_BASE(__cpu, CMD) \
41 __GEN_SPI_RSET_BASE(__cpu, INT_STATUS) \
42 __GEN_SPI_RSET_BASE(__cpu, INT_MASK_ST) \
43 __GEN_SPI_RSET_BASE(__cpu, INT_MASK) \
44 __GEN_SPI_RSET_BASE(__cpu, ST) \
45 __GEN_SPI_RSET_BASE(__cpu, CLK_CFG) \
46 __GEN_SPI_RSET_BASE(__cpu, FILL_BYTE) \
47 __GEN_SPI_RSET_BASE(__cpu, MSG_TAIL) \
48 __GEN_SPI_RSET_BASE(__cpu, RX_TAIL) \
49 __GEN_SPI_RSET_BASE(__cpu, MSG_CTL) \
50 __GEN_SPI_RSET_BASE(__cpu, MSG_DATA) \
51 __GEN_SPI_RSET_BASE(__cpu, RX_DATA) \
52 }
53
54#define __GEN_SPI_REGS_TABLE(__cpu) \
55 [SPI_CMD] = SPI_## __cpu ##_CMD, \
56 [SPI_INT_STATUS] = SPI_## __cpu ##_INT_STATUS, \
57 [SPI_INT_MASK_ST] = SPI_## __cpu ##_INT_MASK_ST, \
58 [SPI_INT_MASK] = SPI_## __cpu ##_INT_MASK, \
59 [SPI_ST] = SPI_## __cpu ##_ST, \
60 [SPI_CLK_CFG] = SPI_## __cpu ##_CLK_CFG, \
61 [SPI_FILL_BYTE] = SPI_## __cpu ##_FILL_BYTE, \
62 [SPI_MSG_TAIL] = SPI_## __cpu ##_MSG_TAIL, \
63 [SPI_RX_TAIL] = SPI_## __cpu ##_RX_TAIL, \
64 [SPI_MSG_CTL] = SPI_## __cpu ##_MSG_CTL, \
65 [SPI_MSG_DATA] = SPI_## __cpu ##_MSG_DATA, \
66 [SPI_RX_DATA] = SPI_## __cpu ##_RX_DATA,
67
68static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
69{
70#ifdef BCMCPU_RUNTIME_DETECT
71 extern const unsigned long *bcm63xx_regs_spi;
72
73 return bcm63xx_regs_spi[reg];
74#else
75#ifdef CONFIG_BCM63XX_CPU_6338
76 __GEN_SPI_RSET(6338)
77#endif
78#ifdef CONFIG_BCM63XX_CPU_6348
79 __GEN_SPI_RSET(6348)
80#endif
81#ifdef CONFIG_BCM63XX_CPU_6358
82 __GEN_SPI_RSET(6358)
83#endif
84#ifdef CONFIG_BCM63XX_CPU_6368
85 __GEN_SPI_RSET(6368)
86#endif
87#endif
88 return 0;
89}
90
91#endif /* BCM63XX_DEV_SPI_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h
deleted file mode 100644
index 5d6d6986f40..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_usbd.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef BCM63XX_DEV_USB_USBD_H_
2#define BCM63XX_DEV_USB_USBD_H_
3
4/*
5 * usb device platform data
6 */
7struct bcm63xx_usbd_platform_data {
8 /* board can only support full speed (USB 1.1) */
9 int use_fullspeed;
10
11 /* 0-based port index, for chips with >1 USB PHY */
12 int port_no;
13};
14
15int bcm63xx_usbd_register(const struct bcm63xx_usbd_platform_data *pd);
16
17#endif /* BCM63XX_DEV_USB_USBD_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
index 0a9891f7580..3999ec0aa7f 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
@@ -2,23 +2,18 @@
2#define BCM63XX_GPIO_H 2#define BCM63XX_GPIO_H
3 3
4#include <linux/init.h> 4#include <linux/init.h>
5#include <bcm63xx_cpu.h>
6 5
7int __init bcm63xx_gpio_init(void); 6int __init bcm63xx_gpio_init(void);
8 7
9static inline unsigned long bcm63xx_gpio_count(void) 8static inline unsigned long bcm63xx_gpio_count(void)
10{ 9{
11 switch (bcm63xx_get_cpu_id()) { 10 switch (bcm63xx_get_cpu_id()) {
12 case BCM6328_CPU_ID:
13 return 32;
14 case BCM6358_CPU_ID: 11 case BCM6358_CPU_ID:
15 return 40; 12 return 40;
16 case BCM6338_CPU_ID: 13 case BCM6338_CPU_ID:
17 return 8; 14 return 8;
18 case BCM6345_CPU_ID: 15 case BCM6345_CPU_ID:
19 return 16; 16 return 16;
20 case BCM6368_CPU_ID:
21 return 38;
22 case BCM6348_CPU_ID: 17 case BCM6348_CPU_ID:
23 default: 18 default:
24 return 37; 19 return 37;
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
index 03a54df5fb8..91180fac6ed 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
@@ -1,7 +1,7 @@
1#ifndef BCM63XX_IO_H_ 1#ifndef BCM63XX_IO_H_
2#define BCM63XX_IO_H_ 2#define BCM63XX_IO_H_
3 3
4#include <asm/mach-bcm63xx/bcm63xx_cpu.h> 4#include "bcm63xx_cpu.h"
5 5
6/* 6/*
7 * Physical memory map, RAM is mapped at 0x0. 7 * Physical memory map, RAM is mapped at 0x0.
@@ -40,10 +40,6 @@
40#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \ 40#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \
41 BCM_CB_MEM_SIZE - 1) 41 BCM_CB_MEM_SIZE - 1)
42 42
43#define BCM_PCIE_MEM_BASE_PA 0x10f00000
44#define BCM_PCIE_MEM_SIZE (16 * 1024 * 1024)
45#define BCM_PCIE_MEM_END_PA (BCM_PCIE_MEM_BASE_PA + \
46 BCM_PCIE_MEM_SIZE - 1)
47 43
48/* 44/*
49 * Internal registers are accessed through KSEG3 45 * Internal registers are accessed through KSEG3
@@ -53,11 +49,9 @@
53#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a)) 49#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a))
54#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a)) 50#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a))
55#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a)) 51#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a))
56#define bcm_readq(a) (*(volatile u64 *) BCM_REGS_VA(a))
57#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v)) 52#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v))
58#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v)) 53#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v))
59#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v)) 54#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v))
60#define bcm_writeq(v, a) (*(volatile u64 *) BCM_REGS_VA((a)) = (v))
61 55
62/* 56/*
63 * IO helpers to access register set for current CPU 57 * IO helpers to access register set for current CPU
@@ -89,15 +83,11 @@
89#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o)) 83#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o))
90#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o)) 84#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o))
91#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o)) 85#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o))
92#define bcm_pcie_readl(o) bcm_rset_readl(RSET_PCIE, (o))
93#define bcm_pcie_writel(v, o) bcm_rset_writel(RSET_PCIE, (v), (o))
94#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o)) 86#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o))
95#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o)) 87#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o))
96#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o)) 88#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o))
97#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o)) 89#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o))
98#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o)) 90#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
99#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o)) 91#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
100#define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o))
101#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o))
102 92
103#endif /* ! BCM63XX_IO_H_ */ 93#endif /* ! BCM63XX_IO_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
index 0c3074b871b..5f95577c821 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h
@@ -3,11 +3,13 @@
3 3
4#include <bcm63xx_cpu.h> 4#include <bcm63xx_cpu.h>
5 5
6#define IRQ_MIPS_BASE 0
6#define IRQ_INTERNAL_BASE 8 7#define IRQ_INTERNAL_BASE 8
7#define IRQ_EXTERNAL_BASE 100 8
8#define IRQ_EXT_0 (IRQ_EXTERNAL_BASE + 0) 9#define IRQ_EXT_BASE (IRQ_MIPS_BASE + 3)
9#define IRQ_EXT_1 (IRQ_EXTERNAL_BASE + 1) 10#define IRQ_EXT_0 (IRQ_EXT_BASE + 0)
10#define IRQ_EXT_2 (IRQ_EXTERNAL_BASE + 2) 11#define IRQ_EXT_1 (IRQ_EXT_BASE + 1)
11#define IRQ_EXT_3 (IRQ_EXTERNAL_BASE + 3) 12#define IRQ_EXT_2 (IRQ_EXT_BASE + 2)
13#define IRQ_EXT_3 (IRQ_EXT_BASE + 3)
12 14
13#endif /* ! BCM63XX_IRQ_H_ */ 15#endif /* ! BCM63XX_IRQ_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h
deleted file mode 100644
index a5bbff31c89..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_iudma.h
+++ /dev/null
@@ -1,38 +0,0 @@
1#ifndef BCM63XX_IUDMA_H_
2#define BCM63XX_IUDMA_H_
3
4#include <linux/types.h>
5
6/*
7 * rx/tx dma descriptor
8 */
9struct bcm_enet_desc {
10 u32 len_stat;
11 u32 address;
12};
13
14/* control */
15#define DMADESC_LENGTH_SHIFT 16
16#define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT)
17#define DMADESC_OWNER_MASK (1 << 15)
18#define DMADESC_EOP_MASK (1 << 14)
19#define DMADESC_SOP_MASK (1 << 13)
20#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
21#define DMADESC_WRAP_MASK (1 << 12)
22#define DMADESC_USB_NOZERO_MASK (1 << 1)
23#define DMADESC_USB_ZERO_MASK (1 << 0)
24
25/* status */
26#define DMADESC_UNDER_MASK (1 << 9)
27#define DMADESC_APPEND_CRC (1 << 8)
28#define DMADESC_OVSIZE_MASK (1 << 4)
29#define DMADESC_RXER_MASK (1 << 2)
30#define DMADESC_CRC_MASK (1 << 1)
31#define DMADESC_OV_MASK (1 << 0)
32#define DMADESC_ERR_MASK (DMADESC_UNDER_MASK | \
33 DMADESC_OVSIZE_MASK | \
34 DMADESC_RXER_MASK | \
35 DMADESC_CRC_MASK | \
36 DMADESC_OV_MASK)
37
38#endif /* ! BCM63XX_IUDMA_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
deleted file mode 100644
index 62d6a3b4d3b..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_nvram.h
+++ /dev/null
@@ -1,35 +0,0 @@
1#ifndef BCM63XX_NVRAM_H
2#define BCM63XX_NVRAM_H
3
4#include <linux/types.h>
5
6/**
7 * bcm63xx_nvram_init() - initializes nvram
8 * @nvram: address of the nvram data
9 *
10 * Initialized the local nvram copy from the target address and checks
11 * its checksum.
12 *
13 * Returns 0 on success.
14 */
15int __init bcm63xx_nvram_init(void *nvram);
16
17/**
18 * bcm63xx_nvram_get_name() - returns the board name according to nvram
19 *
20 * Returns the board name field from nvram. Note that it might not be
21 * null terminated if it is exactly 16 bytes long.
22 */
23u8 *bcm63xx_nvram_get_name(void);
24
25/**
26 * bcm63xx_nvram_get_mac_address() - register & return a new mac address
27 * @mac: pointer to array for allocated mac
28 *
29 * Registers and returns a mac address from the allocated macs from nvram.
30 *
31 * Returns 0 on success.
32 */
33int bcm63xx_nvram_get_mac_address(u8 *mac);
34
35#endif /* BCM63XX_NVRAM_H */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
index c3eeb90b480..0ed5230243c 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
@@ -15,30 +15,6 @@
15/* Clock Control register */ 15/* Clock Control register */
16#define PERF_CKCTL_REG 0x4 16#define PERF_CKCTL_REG 0x4
17 17
18#define CKCTL_6328_PHYMIPS_EN (1 << 0)
19#define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
20#define CKCTL_6328_ADSL_AFE_EN (1 << 2)
21#define CKCTL_6328_ADSL_EN (1 << 3)
22#define CKCTL_6328_MIPS_EN (1 << 4)
23#define CKCTL_6328_SAR_EN (1 << 5)
24#define CKCTL_6328_PCM_EN (1 << 6)
25#define CKCTL_6328_USBD_EN (1 << 7)
26#define CKCTL_6328_USBH_EN (1 << 8)
27#define CKCTL_6328_HSSPI_EN (1 << 9)
28#define CKCTL_6328_PCIE_EN (1 << 10)
29#define CKCTL_6328_ROBOSW_EN (1 << 11)
30
31#define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \
32 CKCTL_6328_ADSL_QPROC_EN | \
33 CKCTL_6328_ADSL_AFE_EN | \
34 CKCTL_6328_ADSL_EN | \
35 CKCTL_6328_SAR_EN | \
36 CKCTL_6328_PCM_EN | \
37 CKCTL_6328_USBD_EN | \
38 CKCTL_6328_USBH_EN | \
39 CKCTL_6328_ROBOSW_EN | \
40 CKCTL_6328_PCIE_EN)
41
42#define CKCTL_6338_ADSLPHY_EN (1 << 0) 18#define CKCTL_6338_ADSLPHY_EN (1 << 0)
43#define CKCTL_6338_MPI_EN (1 << 1) 19#define CKCTL_6338_MPI_EN (1 << 1)
44#define CKCTL_6338_DRAM_EN (1 << 2) 20#define CKCTL_6338_DRAM_EN (1 << 2)
@@ -53,18 +29,13 @@
53 CKCTL_6338_SAR_EN | \ 29 CKCTL_6338_SAR_EN | \
54 CKCTL_6338_SPI_EN) 30 CKCTL_6338_SPI_EN)
55 31
56/* BCM6345 clock bits are shifted by 16 on the left, because of the test 32#define CKCTL_6345_CPU_EN (1 << 0)
57 * control register which is 16-bits wide. That way we do not have any 33#define CKCTL_6345_BUS_EN (1 << 1)
58 * specific BCM6345 code for handling clocks, and writing 0 to the test 34#define CKCTL_6345_EBI_EN (1 << 2)
59 * control register is fine. 35#define CKCTL_6345_UART_EN (1 << 3)
60 */ 36#define CKCTL_6345_ADSLPHY_EN (1 << 4)
61#define CKCTL_6345_CPU_EN (1 << 16) 37#define CKCTL_6345_ENET_EN (1 << 7)
62#define CKCTL_6345_BUS_EN (1 << 17) 38#define CKCTL_6345_USBH_EN (1 << 8)
63#define CKCTL_6345_EBI_EN (1 << 18)
64#define CKCTL_6345_UART_EN (1 << 19)
65#define CKCTL_6345_ADSLPHY_EN (1 << 20)
66#define CKCTL_6345_ENET_EN (1 << 23)
67#define CKCTL_6345_USBH_EN (1 << 24)
68 39
69#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ 40#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \
70 CKCTL_6345_USBH_EN | \ 41 CKCTL_6345_USBH_EN | \
@@ -112,104 +83,30 @@
112 CKCTL_6358_USBSU_EN | \ 83 CKCTL_6358_USBSU_EN | \
113 CKCTL_6358_EPHY_EN) 84 CKCTL_6358_EPHY_EN)
114 85
115#define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
116#define CKCTL_6368_VDSL_AFE_EN (1 << 3)
117#define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
118#define CKCTL_6368_VDSL_EN (1 << 5)
119#define CKCTL_6368_PHYMIPS_EN (1 << 6)
120#define CKCTL_6368_SWPKT_USB_EN (1 << 7)
121#define CKCTL_6368_SWPKT_SAR_EN (1 << 8)
122#define CKCTL_6368_SPI_EN (1 << 9)
123#define CKCTL_6368_USBD_EN (1 << 10)
124#define CKCTL_6368_SAR_EN (1 << 11)
125#define CKCTL_6368_ROBOSW_EN (1 << 12)
126#define CKCTL_6368_UTOPIA_EN (1 << 13)
127#define CKCTL_6368_PCM_EN (1 << 14)
128#define CKCTL_6368_USBH_EN (1 << 15)
129#define CKCTL_6368_DISABLE_GLESS_EN (1 << 16)
130#define CKCTL_6368_NAND_EN (1 << 17)
131#define CKCTL_6368_IPSEC_EN (1 << 18)
132
133#define CKCTL_6368_ALL_SAFE_EN (CKCTL_6368_SWPKT_USB_EN | \
134 CKCTL_6368_SWPKT_SAR_EN | \
135 CKCTL_6368_SPI_EN | \
136 CKCTL_6368_USBD_EN | \
137 CKCTL_6368_SAR_EN | \
138 CKCTL_6368_ROBOSW_EN | \
139 CKCTL_6368_UTOPIA_EN | \
140 CKCTL_6368_PCM_EN | \
141 CKCTL_6368_USBH_EN | \
142 CKCTL_6368_DISABLE_GLESS_EN | \
143 CKCTL_6368_NAND_EN | \
144 CKCTL_6368_IPSEC_EN)
145
146/* System PLL Control register */ 86/* System PLL Control register */
147#define PERF_SYS_PLL_CTL_REG 0x8 87#define PERF_SYS_PLL_CTL_REG 0x8
148#define SYS_PLL_SOFT_RESET 0x1 88#define SYS_PLL_SOFT_RESET 0x1
149 89
150/* Interrupt Mask register */ 90/* Interrupt Mask register */
151#define PERF_IRQMASK_6328_REG 0x20 91#define PERF_IRQMASK_REG 0xc
152#define PERF_IRQMASK_6338_REG 0xc
153#define PERF_IRQMASK_6345_REG 0xc
154#define PERF_IRQMASK_6348_REG 0xc
155#define PERF_IRQMASK_6358_REG 0xc
156#define PERF_IRQMASK_6368_REG 0x20
157 92
158/* Interrupt Status register */ 93/* Interrupt Status register */
159#define PERF_IRQSTAT_6328_REG 0x28 94#define PERF_IRQSTAT_REG 0x10
160#define PERF_IRQSTAT_6338_REG 0x10
161#define PERF_IRQSTAT_6345_REG 0x10
162#define PERF_IRQSTAT_6348_REG 0x10
163#define PERF_IRQSTAT_6358_REG 0x10
164#define PERF_IRQSTAT_6368_REG 0x28
165 95
166/* External Interrupt Configuration register */ 96/* External Interrupt Configuration register */
167#define PERF_EXTIRQ_CFG_REG_6328 0x18 97#define PERF_EXTIRQ_CFG_REG 0x14
168#define PERF_EXTIRQ_CFG_REG_6338 0x14
169#define PERF_EXTIRQ_CFG_REG_6345 0x14
170#define PERF_EXTIRQ_CFG_REG_6348 0x14
171#define PERF_EXTIRQ_CFG_REG_6358 0x14
172#define PERF_EXTIRQ_CFG_REG_6368 0x18
173
174#define PERF_EXTIRQ_CFG_REG2_6368 0x1c
175
176/* for 6348 only */
177#define EXTIRQ_CFG_SENSE_6348(x) (1 << (x))
178#define EXTIRQ_CFG_STAT_6348(x) (1 << (x + 5))
179#define EXTIRQ_CFG_CLEAR_6348(x) (1 << (x + 10))
180#define EXTIRQ_CFG_MASK_6348(x) (1 << (x + 15))
181#define EXTIRQ_CFG_BOTHEDGE_6348(x) (1 << (x + 20))
182#define EXTIRQ_CFG_LEVELSENSE_6348(x) (1 << (x + 25))
183#define EXTIRQ_CFG_CLEAR_ALL_6348 (0xf << 10)
184#define EXTIRQ_CFG_MASK_ALL_6348 (0xf << 15)
185
186/* for all others */
187#define EXTIRQ_CFG_SENSE(x) (1 << (x)) 98#define EXTIRQ_CFG_SENSE(x) (1 << (x))
188#define EXTIRQ_CFG_STAT(x) (1 << (x + 4)) 99#define EXTIRQ_CFG_STAT(x) (1 << (x + 5))
189#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 8)) 100#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10))
190#define EXTIRQ_CFG_MASK(x) (1 << (x + 12)) 101#define EXTIRQ_CFG_MASK(x) (1 << (x + 15))
191#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 16)) 102#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20))
192#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 20)) 103#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25))
193#define EXTIRQ_CFG_CLEAR_ALL (0xf << 8) 104
194#define EXTIRQ_CFG_MASK_ALL (0xf << 12) 105#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10)
106#define EXTIRQ_CFG_MASK_ALL (0xf << 15)
195 107
196/* Soft Reset register */ 108/* Soft Reset register */
197#define PERF_SOFTRESET_REG 0x28 109#define PERF_SOFTRESET_REG 0x28
198#define PERF_SOFTRESET_6328_REG 0x10
199#define PERF_SOFTRESET_6358_REG 0x34
200#define PERF_SOFTRESET_6368_REG 0x10
201
202#define SOFTRESET_6328_SPI_MASK (1 << 0)
203#define SOFTRESET_6328_EPHY_MASK (1 << 1)
204#define SOFTRESET_6328_SAR_MASK (1 << 2)
205#define SOFTRESET_6328_ENETSW_MASK (1 << 3)
206#define SOFTRESET_6328_USBS_MASK (1 << 4)
207#define SOFTRESET_6328_USBH_MASK (1 << 5)
208#define SOFTRESET_6328_PCM_MASK (1 << 6)
209#define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7)
210#define SOFTRESET_6328_PCIE_MASK (1 << 8)
211#define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9)
212#define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10)
213 110
214#define SOFTRESET_6338_SPI_MASK (1 << 0) 111#define SOFTRESET_6338_SPI_MASK (1 << 0)
215#define SOFTRESET_6338_ENET_MASK (1 << 2) 112#define SOFTRESET_6338_ENET_MASK (1 << 2)
@@ -250,24 +147,6 @@
250 SOFTRESET_6348_ACLC_MASK | \ 147 SOFTRESET_6348_ACLC_MASK | \
251 SOFTRESET_6348_ADSLMIPSPLL_MASK) 148 SOFTRESET_6348_ADSLMIPSPLL_MASK)
252 149
253#define SOFTRESET_6358_SPI_MASK (1 << 0)
254#define SOFTRESET_6358_ENET_MASK (1 << 2)
255#define SOFTRESET_6358_MPI_MASK (1 << 3)
256#define SOFTRESET_6358_EPHY_MASK (1 << 6)
257#define SOFTRESET_6358_SAR_MASK (1 << 7)
258#define SOFTRESET_6358_USBH_MASK (1 << 12)
259#define SOFTRESET_6358_PCM_MASK (1 << 13)
260#define SOFTRESET_6358_ADSL_MASK (1 << 14)
261
262#define SOFTRESET_6368_SPI_MASK (1 << 0)
263#define SOFTRESET_6368_MPI_MASK (1 << 3)
264#define SOFTRESET_6368_EPHY_MASK (1 << 6)
265#define SOFTRESET_6368_SAR_MASK (1 << 7)
266#define SOFTRESET_6368_ENETSW_MASK (1 << 10)
267#define SOFTRESET_6368_USBS_MASK (1 << 11)
268#define SOFTRESET_6368_USBH_MASK (1 << 12)
269#define SOFTRESET_6368_PCM_MASK (1 << 13)
270
271/* MIPS PLL control register */ 150/* MIPS PLL control register */
272#define PERF_MIPSPLLCTL_REG 0x34 151#define PERF_MIPSPLLCTL_REG 0x34
273#define MIPSPLLCTL_N1_SHIFT 20 152#define MIPSPLLCTL_N1_SHIFT 20
@@ -363,8 +242,6 @@
363/* Watchdog reset length register */ 242/* Watchdog reset length register */
364#define WDT_RSTLEN_REG 0x8 243#define WDT_RSTLEN_REG 0x8
365 244
366/* Watchdog soft reset register (BCM6328 only) */
367#define WDT_SOFTRESET_REG 0xc
368 245
369/************************************************************************* 246/*************************************************************************
370 * _REG relative to RSET_UARTx 247 * _REG relative to RSET_UARTx
@@ -495,7 +372,6 @@
495#define GPIO_CTL_LO_REG 0x4 372#define GPIO_CTL_LO_REG 0x4
496#define GPIO_DATA_HI_REG 0x8 373#define GPIO_DATA_HI_REG 0x8
497#define GPIO_DATA_LO_REG 0xC 374#define GPIO_DATA_LO_REG 0xC
498#define GPIO_DATA_LO_REG_6345 0x8
499 375
500/* GPIO mux registers and constants */ 376/* GPIO mux registers and constants */
501#define GPIO_MODE_REG 0x18 377#define GPIO_MODE_REG 0x18
@@ -526,59 +402,6 @@
526#define GPIO_MODE_6358_SERIAL_LED (1 << 10) 402#define GPIO_MODE_6358_SERIAL_LED (1 << 10)
527#define GPIO_MODE_6358_UTOPIA (1 << 12) 403#define GPIO_MODE_6358_UTOPIA (1 << 12)
528 404
529#define GPIO_MODE_6368_ANALOG_AFE_0 (1 << 0)
530#define GPIO_MODE_6368_ANALOG_AFE_1 (1 << 1)
531#define GPIO_MODE_6368_SYS_IRQ (1 << 2)
532#define GPIO_MODE_6368_SERIAL_LED_DATA (1 << 3)
533#define GPIO_MODE_6368_SERIAL_LED_CLK (1 << 4)
534#define GPIO_MODE_6368_INET_LED (1 << 5)
535#define GPIO_MODE_6368_EPHY0_LED (1 << 6)
536#define GPIO_MODE_6368_EPHY1_LED (1 << 7)
537#define GPIO_MODE_6368_EPHY2_LED (1 << 8)
538#define GPIO_MODE_6368_EPHY3_LED (1 << 9)
539#define GPIO_MODE_6368_ROBOSW_LED_DAT (1 << 10)
540#define GPIO_MODE_6368_ROBOSW_LED_CLK (1 << 11)
541#define GPIO_MODE_6368_ROBOSW_LED0 (1 << 12)
542#define GPIO_MODE_6368_ROBOSW_LED1 (1 << 13)
543#define GPIO_MODE_6368_USBD_LED (1 << 14)
544#define GPIO_MODE_6368_NTR_PULSE (1 << 15)
545#define GPIO_MODE_6368_PCI_REQ1 (1 << 16)
546#define GPIO_MODE_6368_PCI_GNT1 (1 << 17)
547#define GPIO_MODE_6368_PCI_INTB (1 << 18)
548#define GPIO_MODE_6368_PCI_REQ0 (1 << 19)
549#define GPIO_MODE_6368_PCI_GNT0 (1 << 20)
550#define GPIO_MODE_6368_PCMCIA_CD1 (1 << 22)
551#define GPIO_MODE_6368_PCMCIA_CD2 (1 << 23)
552#define GPIO_MODE_6368_PCMCIA_VS1 (1 << 24)
553#define GPIO_MODE_6368_PCMCIA_VS2 (1 << 25)
554#define GPIO_MODE_6368_EBI_CS2 (1 << 26)
555#define GPIO_MODE_6368_EBI_CS3 (1 << 27)
556#define GPIO_MODE_6368_SPI_SSN2 (1 << 28)
557#define GPIO_MODE_6368_SPI_SSN3 (1 << 29)
558#define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
559#define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
560
561
562#define GPIO_PINMUX_OTHR_REG 0x24
563#define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
564#define GPIO_PINMUX_OTHR_6328_USB_MASK (3 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
565#define GPIO_PINMUX_OTHR_6328_USB_HOST (1 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
566#define GPIO_PINMUX_OTHR_6328_USB_DEV (2 << GPIO_PINMUX_OTHR_6328_USB_SHIFT)
567
568#define GPIO_BASEMODE_6368_REG 0x38
569#define GPIO_BASEMODE_6368_UART2 0x1
570#define GPIO_BASEMODE_6368_GPIO 0x0
571#define GPIO_BASEMODE_6368_MASK 0x7
572/* those bits must be kept as read in gpio basemode register*/
573
574#define GPIO_STRAPBUS_REG 0x40
575#define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
576#define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
577#define STRAPBUS_6368_BOOT_SEL_MASK 0x3
578#define STRAPBUS_6368_BOOT_SEL_NAND 0
579#define STRAPBUS_6368_BOOT_SEL_SERIAL 1
580#define STRAPBUS_6368_BOOT_SEL_PARALLEL 3
581
582 405
583/************************************************************************* 406/*************************************************************************
584 * _REG relative to RSET_ENET 407 * _REG relative to RSET_ENET
@@ -692,12 +515,6 @@
692#define ENETDMA_BUFALLOC_FORCE_SHIFT 31 515#define ENETDMA_BUFALLOC_FORCE_SHIFT 31
693#define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) 516#define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
694 517
695/* Global interrupt status */
696#define ENETDMA_GLB_IRQSTAT_REG (0x40)
697
698/* Global interrupt mask */
699#define ENETDMA_GLB_IRQMASK_REG (0x44)
700
701/* Channel Configuration register */ 518/* Channel Configuration register */
702#define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) 519#define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
703#define ENETDMA_CHANCFG_EN_SHIFT 0 520#define ENETDMA_CHANCFG_EN_SHIFT 0
@@ -731,58 +548,6 @@
731 548
732 549
733/************************************************************************* 550/*************************************************************************
734 * _REG relative to RSET_ENETDMAC
735 *************************************************************************/
736
737/* Channel Configuration register */
738#define ENETDMAC_CHANCFG_REG(x) ((x) * 0x10)
739#define ENETDMAC_CHANCFG_EN_SHIFT 0
740#define ENETDMAC_CHANCFG_EN_MASK (1 << ENETDMAC_CHANCFG_EN_SHIFT)
741#define ENETDMAC_CHANCFG_PKTHALT_SHIFT 1
742#define ENETDMAC_CHANCFG_PKTHALT_MASK (1 << ENETDMAC_CHANCFG_PKTHALT_SHIFT)
743#define ENETDMAC_CHANCFG_BUFHALT_SHIFT 2
744#define ENETDMAC_CHANCFG_BUFHALT_MASK (1 << ENETDMAC_CHANCFG_BUFHALT_SHIFT)
745
746/* Interrupt Control/Status register */
747#define ENETDMAC_IR_REG(x) (0x4 + (x) * 0x10)
748#define ENETDMAC_IR_BUFDONE_MASK (1 << 0)
749#define ENETDMAC_IR_PKTDONE_MASK (1 << 1)
750#define ENETDMAC_IR_NOTOWNER_MASK (1 << 2)
751
752/* Interrupt Mask register */
753#define ENETDMAC_IRMASK_REG(x) (0x8 + (x) * 0x10)
754
755/* Maximum Burst Length */
756#define ENETDMAC_MAXBURST_REG(x) (0xc + (x) * 0x10)
757
758
759/*************************************************************************
760 * _REG relative to RSET_ENETDMAS
761 *************************************************************************/
762
763/* Ring Start Address register */
764#define ENETDMAS_RSTART_REG(x) ((x) * 0x10)
765
766/* State Ram Word 2 */
767#define ENETDMAS_SRAM2_REG(x) (0x4 + (x) * 0x10)
768
769/* State Ram Word 3 */
770#define ENETDMAS_SRAM3_REG(x) (0x8 + (x) * 0x10)
771
772/* State Ram Word 4 */
773#define ENETDMAS_SRAM4_REG(x) (0xc + (x) * 0x10)
774
775
776/*************************************************************************
777 * _REG relative to RSET_ENETSW
778 *************************************************************************/
779
780/* MIB register */
781#define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
782#define ENETSW_MIB_REG_COUNT 47
783
784
785/*************************************************************************
786 * _REG relative to RSET_OHCI_PRIV 551 * _REG relative to RSET_OHCI_PRIV
787 *************************************************************************/ 552 *************************************************************************/
788 553
@@ -797,11 +562,7 @@
797 * _REG relative to RSET_USBH_PRIV 562 * _REG relative to RSET_USBH_PRIV
798 *************************************************************************/ 563 *************************************************************************/
799 564
800#define USBH_PRIV_SWAP_6358_REG 0x0 565#define USBH_PRIV_SWAP_REG 0x0
801#define USBH_PRIV_SWAP_6368_REG 0x1c
802
803#define USBH_PRIV_SWAP_USBD_SHIFT 6
804#define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT)
805#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 566#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
806#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) 567#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
807#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 568#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
@@ -811,160 +572,7 @@
811#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 572#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
812#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) 573#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
813 574
814#define USBH_PRIV_UTMI_CTL_6368_REG 0x10 575#define USBH_PRIV_TEST_REG 0x24
815#define USBH_PRIV_UTMI_CTL_NODRIV_SHIFT 12
816#define USBH_PRIV_UTMI_CTL_NODRIV_MASK (0xf << USBH_PRIV_UTMI_CTL_NODRIV_SHIFT)
817#define USBH_PRIV_UTMI_CTL_HOSTB_SHIFT 0
818#define USBH_PRIV_UTMI_CTL_HOSTB_MASK (0xf << USBH_PRIV_UTMI_CTL_HOSTB_SHIFT)
819
820#define USBH_PRIV_TEST_6358_REG 0x24
821#define USBH_PRIV_TEST_6368_REG 0x14
822
823#define USBH_PRIV_SETUP_6368_REG 0x28
824#define USBH_PRIV_SETUP_IOC_SHIFT 4
825#define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
826
827
828/*************************************************************************
829 * _REG relative to RSET_USBD
830 *************************************************************************/
831
832/* General control */
833#define USBD_CONTROL_REG 0x00
834#define USBD_CONTROL_TXZLENINS_SHIFT 14
835#define USBD_CONTROL_TXZLENINS_MASK (1 << USBD_CONTROL_TXZLENINS_SHIFT)
836#define USBD_CONTROL_AUTO_CSRS_SHIFT 13
837#define USBD_CONTROL_AUTO_CSRS_MASK (1 << USBD_CONTROL_AUTO_CSRS_SHIFT)
838#define USBD_CONTROL_RXZSCFG_SHIFT 12
839#define USBD_CONTROL_RXZSCFG_MASK (1 << USBD_CONTROL_RXZSCFG_SHIFT)
840#define USBD_CONTROL_INIT_SEL_SHIFT 8
841#define USBD_CONTROL_INIT_SEL_MASK (0xf << USBD_CONTROL_INIT_SEL_SHIFT)
842#define USBD_CONTROL_FIFO_RESET_SHIFT 6
843#define USBD_CONTROL_FIFO_RESET_MASK (3 << USBD_CONTROL_FIFO_RESET_SHIFT)
844#define USBD_CONTROL_SETUPERRLOCK_SHIFT 5
845#define USBD_CONTROL_SETUPERRLOCK_MASK (1 << USBD_CONTROL_SETUPERRLOCK_SHIFT)
846#define USBD_CONTROL_DONE_CSRS_SHIFT 0
847#define USBD_CONTROL_DONE_CSRS_MASK (1 << USBD_CONTROL_DONE_CSRS_SHIFT)
848
849/* Strap options */
850#define USBD_STRAPS_REG 0x04
851#define USBD_STRAPS_APP_SELF_PWR_SHIFT 10
852#define USBD_STRAPS_APP_SELF_PWR_MASK (1 << USBD_STRAPS_APP_SELF_PWR_SHIFT)
853#define USBD_STRAPS_APP_DISCON_SHIFT 9
854#define USBD_STRAPS_APP_DISCON_MASK (1 << USBD_STRAPS_APP_DISCON_SHIFT)
855#define USBD_STRAPS_APP_CSRPRGSUP_SHIFT 8
856#define USBD_STRAPS_APP_CSRPRGSUP_MASK (1 << USBD_STRAPS_APP_CSRPRGSUP_SHIFT)
857#define USBD_STRAPS_APP_RMTWKUP_SHIFT 6
858#define USBD_STRAPS_APP_RMTWKUP_MASK (1 << USBD_STRAPS_APP_RMTWKUP_SHIFT)
859#define USBD_STRAPS_APP_RAM_IF_SHIFT 7
860#define USBD_STRAPS_APP_RAM_IF_MASK (1 << USBD_STRAPS_APP_RAM_IF_SHIFT)
861#define USBD_STRAPS_APP_8BITPHY_SHIFT 2
862#define USBD_STRAPS_APP_8BITPHY_MASK (1 << USBD_STRAPS_APP_8BITPHY_SHIFT)
863#define USBD_STRAPS_SPEED_SHIFT 0
864#define USBD_STRAPS_SPEED_MASK (3 << USBD_STRAPS_SPEED_SHIFT)
865
866/* Stall control */
867#define USBD_STALL_REG 0x08
868#define USBD_STALL_UPDATE_SHIFT 7
869#define USBD_STALL_UPDATE_MASK (1 << USBD_STALL_UPDATE_SHIFT)
870#define USBD_STALL_ENABLE_SHIFT 6
871#define USBD_STALL_ENABLE_MASK (1 << USBD_STALL_ENABLE_SHIFT)
872#define USBD_STALL_EPNUM_SHIFT 0
873#define USBD_STALL_EPNUM_MASK (0xf << USBD_STALL_EPNUM_SHIFT)
874
875/* General status */
876#define USBD_STATUS_REG 0x0c
877#define USBD_STATUS_SOF_SHIFT 16
878#define USBD_STATUS_SOF_MASK (0x7ff << USBD_STATUS_SOF_SHIFT)
879#define USBD_STATUS_SPD_SHIFT 12
880#define USBD_STATUS_SPD_MASK (3 << USBD_STATUS_SPD_SHIFT)
881#define USBD_STATUS_ALTINTF_SHIFT 8
882#define USBD_STATUS_ALTINTF_MASK (0xf << USBD_STATUS_ALTINTF_SHIFT)
883#define USBD_STATUS_INTF_SHIFT 4
884#define USBD_STATUS_INTF_MASK (0xf << USBD_STATUS_INTF_SHIFT)
885#define USBD_STATUS_CFG_SHIFT 0
886#define USBD_STATUS_CFG_MASK (0xf << USBD_STATUS_CFG_SHIFT)
887
888/* Other events */
889#define USBD_EVENTS_REG 0x10
890#define USBD_EVENTS_USB_LINK_SHIFT 10
891#define USBD_EVENTS_USB_LINK_MASK (1 << USBD_EVENTS_USB_LINK_SHIFT)
892
893/* IRQ status */
894#define USBD_EVENT_IRQ_STATUS_REG 0x14
895
896/* IRQ level (2 bits per IRQ event) */
897#define USBD_EVENT_IRQ_CFG_HI_REG 0x18
898
899#define USBD_EVENT_IRQ_CFG_LO_REG 0x1c
900
901#define USBD_EVENT_IRQ_CFG_SHIFT(x) ((x & 0xf) << 1)
902#define USBD_EVENT_IRQ_CFG_MASK(x) (3 << USBD_EVENT_IRQ_CFG_SHIFT(x))
903#define USBD_EVENT_IRQ_CFG_RISING(x) (0 << USBD_EVENT_IRQ_CFG_SHIFT(x))
904#define USBD_EVENT_IRQ_CFG_FALLING(x) (1 << USBD_EVENT_IRQ_CFG_SHIFT(x))
905
906/* IRQ mask (1=unmasked) */
907#define USBD_EVENT_IRQ_MASK_REG 0x20
908
909/* IRQ bits */
910#define USBD_EVENT_IRQ_USB_LINK 10
911#define USBD_EVENT_IRQ_SETCFG 9
912#define USBD_EVENT_IRQ_SETINTF 8
913#define USBD_EVENT_IRQ_ERRATIC_ERR 7
914#define USBD_EVENT_IRQ_SET_CSRS 6
915#define USBD_EVENT_IRQ_SUSPEND 5
916#define USBD_EVENT_IRQ_EARLY_SUSPEND 4
917#define USBD_EVENT_IRQ_SOF 3
918#define USBD_EVENT_IRQ_ENUM_ON 2
919#define USBD_EVENT_IRQ_SETUP 1
920#define USBD_EVENT_IRQ_USB_RESET 0
921
922/* TX FIFO partitioning */
923#define USBD_TXFIFO_CONFIG_REG 0x40
924#define USBD_TXFIFO_CONFIG_END_SHIFT 16
925#define USBD_TXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
926#define USBD_TXFIFO_CONFIG_START_SHIFT 0
927#define USBD_TXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
928
929/* RX FIFO partitioning */
930#define USBD_RXFIFO_CONFIG_REG 0x44
931#define USBD_RXFIFO_CONFIG_END_SHIFT 16
932#define USBD_RXFIFO_CONFIG_END_MASK (0xff << USBD_TXFIFO_CONFIG_END_SHIFT)
933#define USBD_RXFIFO_CONFIG_START_SHIFT 0
934#define USBD_RXFIFO_CONFIG_START_MASK (0xff << USBD_TXFIFO_CONFIG_START_SHIFT)
935
936/* TX FIFO/endpoint configuration */
937#define USBD_TXFIFO_EPSIZE_REG 0x48
938
939/* RX FIFO/endpoint configuration */
940#define USBD_RXFIFO_EPSIZE_REG 0x4c
941
942/* Endpoint<->DMA mappings */
943#define USBD_EPNUM_TYPEMAP_REG 0x50
944#define USBD_EPNUM_TYPEMAP_TYPE_SHIFT 8
945#define USBD_EPNUM_TYPEMAP_TYPE_MASK (0x3 << USBD_EPNUM_TYPEMAP_TYPE_SHIFT)
946#define USBD_EPNUM_TYPEMAP_DMA_CH_SHIFT 0
947#define USBD_EPNUM_TYPEMAP_DMA_CH_MASK (0xf << USBD_EPNUM_TYPEMAP_DMACH_SHIFT)
948
949/* Misc per-endpoint settings */
950#define USBD_CSR_SETUPADDR_REG 0x80
951#define USBD_CSR_SETUPADDR_DEF 0xb550
952
953#define USBD_CSR_EP_REG(x) (0x84 + (x) * 4)
954#define USBD_CSR_EP_MAXPKT_SHIFT 19
955#define USBD_CSR_EP_MAXPKT_MASK (0x7ff << USBD_CSR_EP_MAXPKT_SHIFT)
956#define USBD_CSR_EP_ALTIFACE_SHIFT 15
957#define USBD_CSR_EP_ALTIFACE_MASK (0xf << USBD_CSR_EP_ALTIFACE_SHIFT)
958#define USBD_CSR_EP_IFACE_SHIFT 11
959#define USBD_CSR_EP_IFACE_MASK (0xf << USBD_CSR_EP_IFACE_SHIFT)
960#define USBD_CSR_EP_CFG_SHIFT 7
961#define USBD_CSR_EP_CFG_MASK (0xf << USBD_CSR_EP_CFG_SHIFT)
962#define USBD_CSR_EP_TYPE_SHIFT 5
963#define USBD_CSR_EP_TYPE_MASK (3 << USBD_CSR_EP_TYPE_SHIFT)
964#define USBD_CSR_EP_DIR_SHIFT 4
965#define USBD_CSR_EP_DIR_MASK (1 << USBD_CSR_EP_DIR_SHIFT)
966#define USBD_CSR_EP_LOG_SHIFT 0
967#define USBD_CSR_EP_LOG_MASK (0xf << USBD_CSR_EP_LOG_SHIFT)
968 576
969 577
970/************************************************************************* 578/*************************************************************************
@@ -1126,8 +734,6 @@
1126#define SDRAM_CFG_BANK_SHIFT 13 734#define SDRAM_CFG_BANK_SHIFT 13
1127#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) 735#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
1128 736
1129#define SDRAM_MBASE_REG 0xc
1130
1131#define SDRAM_PRIO_REG 0x2C 737#define SDRAM_PRIO_REG 0x2C
1132#define SDRAM_PRIO_MIPS_SHIFT 29 738#define SDRAM_PRIO_MIPS_SHIFT 29
1133#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) 739#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
@@ -1154,8 +760,6 @@
1154 * _REG relative to RSET_DDR 760 * _REG relative to RSET_DDR
1155 *************************************************************************/ 761 *************************************************************************/
1156 762
1157#define DDR_CSEND_REG 0x8
1158
1159#define DDR_DMIPSPLLCFG_REG 0x18 763#define DDR_DMIPSPLLCFG_REG 0x18
1160#define DMIPSPLLCFG_M1_SHIFT 0 764#define DMIPSPLLCFG_M1_SHIFT 0
1161#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) 765#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
@@ -1164,249 +768,4 @@
1164#define DMIPSPLLCFG_N2_SHIFT 29 768#define DMIPSPLLCFG_N2_SHIFT 29
1165#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) 769#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
1166 770
1167#define DDR_DMIPSPLLCFG_6368_REG 0x20
1168#define DMIPSPLLCFG_6368_P1_SHIFT 0
1169#define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT)
1170#define DMIPSPLLCFG_6368_P2_SHIFT 4
1171#define DMIPSPLLCFG_6368_P2_MASK (0xf << DMIPSPLLCFG_6368_P2_SHIFT)
1172#define DMIPSPLLCFG_6368_NDIV_SHIFT 16
1173#define DMIPSPLLCFG_6368_NDIV_MASK (0x1ff << DMIPSPLLCFG_6368_NDIV_SHIFT)
1174
1175#define DDR_DMIPSPLLDIV_6368_REG 0x24
1176#define DMIPSPLLDIV_6368_MDIV_SHIFT 0
1177#define DMIPSPLLDIV_6368_MDIV_MASK (0xff << DMIPSPLLDIV_6368_MDIV_SHIFT)
1178
1179
1180/*************************************************************************
1181 * _REG relative to RSET_M2M
1182 *************************************************************************/
1183
1184#define M2M_RX 0
1185#define M2M_TX 1
1186
1187#define M2M_SRC_REG(x) ((x) * 0x40 + 0x00)
1188#define M2M_DST_REG(x) ((x) * 0x40 + 0x04)
1189#define M2M_SIZE_REG(x) ((x) * 0x40 + 0x08)
1190
1191#define M2M_CTRL_REG(x) ((x) * 0x40 + 0x0c)
1192#define M2M_CTRL_ENABLE_MASK (1 << 0)
1193#define M2M_CTRL_IRQEN_MASK (1 << 1)
1194#define M2M_CTRL_ERROR_CLR_MASK (1 << 6)
1195#define M2M_CTRL_DONE_CLR_MASK (1 << 7)
1196#define M2M_CTRL_NOINC_MASK (1 << 8)
1197#define M2M_CTRL_PCMCIASWAP_MASK (1 << 9)
1198#define M2M_CTRL_SWAPBYTE_MASK (1 << 10)
1199#define M2M_CTRL_ENDIAN_MASK (1 << 11)
1200
1201#define M2M_STAT_REG(x) ((x) * 0x40 + 0x10)
1202#define M2M_STAT_DONE (1 << 0)
1203#define M2M_STAT_ERROR (1 << 1)
1204
1205#define M2M_SRCID_REG(x) ((x) * 0x40 + 0x14)
1206#define M2M_DSTID_REG(x) ((x) * 0x40 + 0x18)
1207
1208/*************************************************************************
1209 * _REG relative to RSET_RNG
1210 *************************************************************************/
1211
1212#define RNG_CTRL 0x00
1213#define RNG_EN (1 << 0)
1214
1215#define RNG_STAT 0x04
1216#define RNG_AVAIL_MASK (0xff000000)
1217
1218#define RNG_DATA 0x08
1219#define RNG_THRES 0x0c
1220#define RNG_MASK 0x10
1221
1222/*************************************************************************
1223 * _REG relative to RSET_SPI
1224 *************************************************************************/
1225
1226/* BCM 6338 SPI core */
1227#define SPI_6338_CMD 0x00 /* 16-bits register */
1228#define SPI_6338_INT_STATUS 0x02
1229#define SPI_6338_INT_MASK_ST 0x03
1230#define SPI_6338_INT_MASK 0x04
1231#define SPI_6338_ST 0x05
1232#define SPI_6338_CLK_CFG 0x06
1233#define SPI_6338_FILL_BYTE 0x07
1234#define SPI_6338_MSG_TAIL 0x09
1235#define SPI_6338_RX_TAIL 0x0b
1236#define SPI_6338_MSG_CTL 0x40 /* 8-bits register */
1237#define SPI_6338_MSG_CTL_WIDTH 8
1238#define SPI_6338_MSG_DATA 0x41
1239#define SPI_6338_MSG_DATA_SIZE 0x3f
1240#define SPI_6338_RX_DATA 0x80
1241#define SPI_6338_RX_DATA_SIZE 0x3f
1242
1243/* BCM 6348 SPI core */
1244#define SPI_6348_CMD 0x00 /* 16-bits register */
1245#define SPI_6348_INT_STATUS 0x02
1246#define SPI_6348_INT_MASK_ST 0x03
1247#define SPI_6348_INT_MASK 0x04
1248#define SPI_6348_ST 0x05
1249#define SPI_6348_CLK_CFG 0x06
1250#define SPI_6348_FILL_BYTE 0x07
1251#define SPI_6348_MSG_TAIL 0x09
1252#define SPI_6348_RX_TAIL 0x0b
1253#define SPI_6348_MSG_CTL 0x40 /* 8-bits register */
1254#define SPI_6348_MSG_CTL_WIDTH 8
1255#define SPI_6348_MSG_DATA 0x41
1256#define SPI_6348_MSG_DATA_SIZE 0x3f
1257#define SPI_6348_RX_DATA 0x80
1258#define SPI_6348_RX_DATA_SIZE 0x3f
1259
1260/* BCM 6358 SPI core */
1261#define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
1262#define SPI_6358_MSG_CTL_WIDTH 16
1263#define SPI_6358_MSG_DATA 0x02
1264#define SPI_6358_MSG_DATA_SIZE 0x21e
1265#define SPI_6358_RX_DATA 0x400
1266#define SPI_6358_RX_DATA_SIZE 0x220
1267#define SPI_6358_CMD 0x700 /* 16-bits register */
1268#define SPI_6358_INT_STATUS 0x702
1269#define SPI_6358_INT_MASK_ST 0x703
1270#define SPI_6358_INT_MASK 0x704
1271#define SPI_6358_ST 0x705
1272#define SPI_6358_CLK_CFG 0x706
1273#define SPI_6358_FILL_BYTE 0x707
1274#define SPI_6358_MSG_TAIL 0x709
1275#define SPI_6358_RX_TAIL 0x70B
1276
1277/* BCM 6358 SPI core */
1278#define SPI_6368_MSG_CTL 0x00 /* 16-bits register */
1279#define SPI_6368_MSG_CTL_WIDTH 16
1280#define SPI_6368_MSG_DATA 0x02
1281#define SPI_6368_MSG_DATA_SIZE 0x21e
1282#define SPI_6368_RX_DATA 0x400
1283#define SPI_6368_RX_DATA_SIZE 0x220
1284#define SPI_6368_CMD 0x700 /* 16-bits register */
1285#define SPI_6368_INT_STATUS 0x702
1286#define SPI_6368_INT_MASK_ST 0x703
1287#define SPI_6368_INT_MASK 0x704
1288#define SPI_6368_ST 0x705
1289#define SPI_6368_CLK_CFG 0x706
1290#define SPI_6368_FILL_BYTE 0x707
1291#define SPI_6368_MSG_TAIL 0x709
1292#define SPI_6368_RX_TAIL 0x70B
1293
1294/* Shared SPI definitions */
1295
1296/* Message configuration */
1297#define SPI_FD_RW 0x00
1298#define SPI_HD_W 0x01
1299#define SPI_HD_R 0x02
1300#define SPI_BYTE_CNT_SHIFT 0
1301#define SPI_6338_MSG_TYPE_SHIFT 6
1302#define SPI_6348_MSG_TYPE_SHIFT 6
1303#define SPI_6358_MSG_TYPE_SHIFT 14
1304#define SPI_6368_MSG_TYPE_SHIFT 14
1305
1306/* Command */
1307#define SPI_CMD_NOOP 0x00
1308#define SPI_CMD_SOFT_RESET 0x01
1309#define SPI_CMD_HARD_RESET 0x02
1310#define SPI_CMD_START_IMMEDIATE 0x03
1311#define SPI_CMD_COMMAND_SHIFT 0
1312#define SPI_CMD_COMMAND_MASK 0x000f
1313#define SPI_CMD_DEVICE_ID_SHIFT 4
1314#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
1315#define SPI_CMD_ONE_BYTE_SHIFT 11
1316#define SPI_CMD_ONE_WIRE_SHIFT 12
1317#define SPI_DEV_ID_0 0
1318#define SPI_DEV_ID_1 1
1319#define SPI_DEV_ID_2 2
1320#define SPI_DEV_ID_3 3
1321
1322/* Interrupt mask */
1323#define SPI_INTR_CMD_DONE 0x01
1324#define SPI_INTR_RX_OVERFLOW 0x02
1325#define SPI_INTR_TX_UNDERFLOW 0x04
1326#define SPI_INTR_TX_OVERFLOW 0x08
1327#define SPI_INTR_RX_UNDERFLOW 0x10
1328#define SPI_INTR_CLEAR_ALL 0x1f
1329
1330/* Status */
1331#define SPI_RX_EMPTY 0x02
1332#define SPI_CMD_BUSY 0x04
1333#define SPI_SERIAL_BUSY 0x08
1334
1335/* Clock configuration */
1336#define SPI_CLK_20MHZ 0x00
1337#define SPI_CLK_0_391MHZ 0x01
1338#define SPI_CLK_0_781MHZ 0x02 /* default */
1339#define SPI_CLK_1_563MHZ 0x03
1340#define SPI_CLK_3_125MHZ 0x04
1341#define SPI_CLK_6_250MHZ 0x05
1342#define SPI_CLK_12_50MHZ 0x06
1343#define SPI_CLK_MASK 0x07
1344#define SPI_SSOFFTIME_MASK 0x38
1345#define SPI_SSOFFTIME_SHIFT 3
1346#define SPI_BYTE_SWAP 0x80
1347
1348/*************************************************************************
1349 * _REG relative to RSET_MISC
1350 *************************************************************************/
1351#define MISC_SERDES_CTRL_REG 0x0
1352#define SERDES_PCIE_EN (1 << 0)
1353#define SERDES_PCIE_EXD_EN (1 << 15)
1354
1355#define MISC_STRAPBUS_6328_REG 0x240
1356#define STRAPBUS_6328_FCVO_SHIFT 7
1357#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
1358#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
1359#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
1360
1361/*************************************************************************
1362 * _REG relative to RSET_PCIE
1363 *************************************************************************/
1364
1365#define PCIE_CONFIG2_REG 0x408
1366#define CONFIG2_BAR1_SIZE_EN 1
1367#define CONFIG2_BAR1_SIZE_MASK 0xf
1368
1369#define PCIE_IDVAL3_REG 0x43c
1370#define IDVAL3_CLASS_CODE_MASK 0xffffff
1371#define IDVAL3_SUBCLASS_SHIFT 8
1372#define IDVAL3_CLASS_SHIFT 16
1373
1374#define PCIE_DLSTATUS_REG 0x1048
1375#define DLSTATUS_PHYLINKUP (1 << 13)
1376
1377#define PCIE_BRIDGE_OPT1_REG 0x2820
1378#define OPT1_RD_BE_OPT_EN (1 << 7)
1379#define OPT1_RD_REPLY_BE_FIX_EN (1 << 9)
1380#define OPT1_PCIE_BRIDGE_HOLE_DET_EN (1 << 11)
1381#define OPT1_L1_INT_STATUS_MASK_POL (1 << 12)
1382
1383#define PCIE_BRIDGE_OPT2_REG 0x2824
1384#define OPT2_UBUS_UR_DECODE_DIS (1 << 2)
1385#define OPT2_TX_CREDIT_CHK_EN (1 << 4)
1386#define OPT2_CFG_TYPE1_BD_SEL (1 << 7)
1387#define OPT2_CFG_TYPE1_BUS_NO_SHIFT 16
1388#define OPT2_CFG_TYPE1_BUS_NO_MASK (0xff << OPT2_CFG_TYPE1_BUS_NO_SHIFT)
1389
1390#define PCIE_BRIDGE_BAR0_BASEMASK_REG 0x2828
1391#define PCIE_BRIDGE_BAR1_BASEMASK_REG 0x2830
1392#define BASEMASK_REMAP_EN (1 << 0)
1393#define BASEMASK_SWAP_EN (1 << 1)
1394#define BASEMASK_MASK_SHIFT 4
1395#define BASEMASK_MASK_MASK (0xfff << BASEMASK_MASK_SHIFT)
1396#define BASEMASK_BASE_SHIFT 20
1397#define BASEMASK_BASE_MASK (0xfff << BASEMASK_BASE_SHIFT)
1398
1399#define PCIE_BRIDGE_BAR0_REBASE_ADDR_REG 0x282c
1400#define PCIE_BRIDGE_BAR1_REBASE_ADDR_REG 0x2834
1401#define REBASE_ADDR_BASE_SHIFT 20
1402#define REBASE_ADDR_BASE_MASK (0xfff << REBASE_ADDR_BASE_SHIFT)
1403
1404#define PCIE_BRIDGE_RC_INT_MASK_REG 0x2854
1405#define PCIE_RC_INT_A (1 << 0)
1406#define PCIE_RC_INT_B (1 << 1)
1407#define PCIE_RC_INT_C (1 << 2)
1408#define PCIE_RC_INT_D (1 << 3)
1409
1410#define PCIE_DEVICE_OFFSET 0x8000
1411
1412#endif /* BCM63XX_REGS_H_ */ 771#endif /* BCM63XX_REGS_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
deleted file mode 100644
index 3a6eb9c1adc..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_reset.h
+++ /dev/null
@@ -1,21 +0,0 @@
1#ifndef __BCM63XX_RESET_H
2#define __BCM63XX_RESET_H
3
4enum bcm63xx_core_reset {
5 BCM63XX_RESET_SPI,
6 BCM63XX_RESET_ENET,
7 BCM63XX_RESET_USBH,
8 BCM63XX_RESET_USBD,
9 BCM63XX_RESET_SAR,
10 BCM63XX_RESET_DSL,
11 BCM63XX_RESET_EPHY,
12 BCM63XX_RESET_ENETSW,
13 BCM63XX_RESET_PCM,
14 BCM63XX_RESET_MPI,
15 BCM63XX_RESET_PCIE,
16 BCM63XX_RESET_PCIE_EXT,
17};
18
19void bcm63xx_core_set_reset(enum bcm63xx_core_reset, int reset);
20
21#endif
diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
index 1e6b587f62c..ed72e6a26b7 100644
--- a/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
+++ b/arch/mips/include/asm/mach-bcm63xx/bcm963xx_tag.h
@@ -16,6 +16,7 @@
16#define TAGINFO1_LEN 30 /* Length of vendor information field1 in tag */ 16#define TAGINFO1_LEN 30 /* Length of vendor information field1 in tag */
17#define FLASHLAYOUTVER_LEN 4 /* Length of Flash Layout Version String tag */ 17#define FLASHLAYOUTVER_LEN 4 /* Length of Flash Layout Version String tag */
18#define TAGINFO2_LEN 16 /* Length of vendor information field2 in tag */ 18#define TAGINFO2_LEN 16 /* Length of vendor information field2 in tag */
19#define CRC_LEN 4 /* Length of CRC in bytes */
19#define ALTTAGINFO_LEN 54 /* Alternate length for vendor information; Pirelli */ 20#define ALTTAGINFO_LEN 54 /* Alternate length for vendor information; Pirelli */
20 21
21#define NUM_PIRELLI 2 22#define NUM_PIRELLI 2
@@ -76,19 +77,19 @@ struct bcm_tag {
76 /* 192-195: Version flash layout */ 77 /* 192-195: Version flash layout */
77 char flash_layout_ver[FLASHLAYOUTVER_LEN]; 78 char flash_layout_ver[FLASHLAYOUTVER_LEN];
78 /* 196-199: kernel+rootfs CRC32 */ 79 /* 196-199: kernel+rootfs CRC32 */
79 __u32 fskernel_crc; 80 char fskernel_crc[CRC_LEN];
80 /* 200-215: Unused except on Alice Gate where is is information */ 81 /* 200-215: Unused except on Alice Gate where is is information */
81 char information2[TAGINFO2_LEN]; 82 char information2[TAGINFO2_LEN];
82 /* 216-219: CRC32 of image less imagetag (kernel for Alice Gate) */ 83 /* 216-219: CRC32 of image less imagetag (kernel for Alice Gate) */
83 __u32 image_crc; 84 char image_crc[CRC_LEN];
84 /* 220-223: CRC32 of rootfs partition */ 85 /* 220-223: CRC32 of rootfs partition */
85 __u32 rootfs_crc; 86 char rootfs_crc[CRC_LEN];
86 /* 224-227: CRC32 of kernel partition */ 87 /* 224-227: CRC32 of kernel partition */
87 __u32 kernel_crc; 88 char kernel_crc[CRC_LEN];
88 /* 228-235: Unused at present */ 89 /* 228-235: Unused at present */
89 char reserved1[8]; 90 char reserved1[8];
90 /* 236-239: CRC32 of header excluding last 20 bytes */ 91 /* 236-239: CRC32 of header excluding last 20 bytes */
91 __u32 header_crc; 92 char header_crc[CRC_LEN];
92 /* 240-255: Unused at present */ 93 /* 240-255: Unused at present */
93 char reserved2[16]; 94 char reserved2[16];
94}; 95};
diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
index 682bcf3b492..474daaa5349 100644
--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
@@ -5,7 +5,6 @@
5#include <linux/gpio.h> 5#include <linux/gpio.h>
6#include <linux/leds.h> 6#include <linux/leds.h>
7#include <bcm63xx_dev_enet.h> 7#include <bcm63xx_dev_enet.h>
8#include <bcm63xx_dev_usb_usbd.h>
9#include <bcm63xx_dev_dsp.h> 8#include <bcm63xx_dev_dsp.h>
10 9
11/* 10/*
@@ -15,6 +14,23 @@
15#define BCM963XX_NVRAM_OFFSET 0x580 14#define BCM963XX_NVRAM_OFFSET 0x580
16 15
17/* 16/*
17 * nvram structure
18 */
19struct bcm963xx_nvram {
20 u32 version;
21 u8 reserved1[256];
22 u8 name[16];
23 u32 main_tp_number;
24 u32 psi_size;
25 u32 mac_addr_count;
26 u8 mac_addr_base[6];
27 u8 reserved2[2];
28 u32 checksum_old;
29 u8 reserved3[720];
30 u32 checksum_high;
31};
32
33/*
18 * board definition 34 * board definition
19 */ 35 */
20struct board_info { 36struct board_info {
@@ -28,7 +44,6 @@ struct board_info {
28 unsigned int has_pccard:1; 44 unsigned int has_pccard:1;
29 unsigned int has_ohci0:1; 45 unsigned int has_ohci0:1;
30 unsigned int has_ehci0:1; 46 unsigned int has_ehci0:1;
31 unsigned int has_usbd:1;
32 unsigned int has_dsp:1; 47 unsigned int has_dsp:1;
33 unsigned int has_uart0:1; 48 unsigned int has_uart0:1;
34 unsigned int has_uart1:1; 49 unsigned int has_uart1:1;
@@ -37,9 +52,6 @@ struct board_info {
37 struct bcm63xx_enet_platform_data enet0; 52 struct bcm63xx_enet_platform_data enet0;
38 struct bcm63xx_enet_platform_data enet1; 53 struct bcm63xx_enet_platform_data enet1;
39 54
40 /* USB config */
41 struct bcm63xx_usbd_platform_data usbd;
42
43 /* DSP config */ 55 /* DSP config */
44 struct bcm63xx_dsp_platform_data dsp; 56 struct bcm63xx_dsp_platform_data dsp;
45 57
diff --git a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
index e9c408e8ff4..f453c01d067 100644
--- a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h
@@ -37,7 +37,6 @@
37#define cpu_has_mips64r2 0 37#define cpu_has_mips64r2 0
38 38
39#define cpu_has_dsp 0 39#define cpu_has_dsp 0
40#define cpu_has_dsp2 0
41#define cpu_has_mipsmt 0 40#define cpu_has_mipsmt 0
42#define cpu_has_userlocal 0 41#define cpu_has_userlocal 0
43 42
diff --git a/arch/mips/include/asm/mach-bcm63xx/ioremap.h b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
deleted file mode 100644
index 30931c42379..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
+++ /dev/null
@@ -1,43 +0,0 @@
1#ifndef BCM63XX_IOREMAP_H_
2#define BCM63XX_IOREMAP_H_
3
4#include <bcm63xx_cpu.h>
5
6static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
7{
8 return phys_addr;
9}
10
11static inline int is_bcm63xx_internal_registers(phys_t offset)
12{
13 switch (bcm63xx_get_cpu_id()) {
14 case BCM6338_CPU_ID:
15 case BCM6345_CPU_ID:
16 case BCM6348_CPU_ID:
17 case BCM6358_CPU_ID:
18 if (offset >= 0xfff00000)
19 return 1;
20 break;
21 case BCM6328_CPU_ID:
22 case BCM6368_CPU_ID:
23 if (offset >= 0xb0000000 && offset < 0xb1000000)
24 return 1;
25 break;
26 }
27 return 0;
28}
29
30static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
31 unsigned long flags)
32{
33 if (is_bcm63xx_internal_registers(offset))
34 return (void __iomem *)offset;
35 return NULL;
36}
37
38static inline int plat_iounmap(const volatile void __iomem *addr)
39{
40 return is_bcm63xx_internal_registers((unsigned long)addr);
41}
42
43#endif /* BCM63XX_IOREMAP_H_ */
diff --git a/arch/mips/include/asm/mach-bcm63xx/irq.h b/arch/mips/include/asm/mach-bcm63xx/irq.h
deleted file mode 100644
index 9332e788a5c..00000000000
--- a/arch/mips/include/asm/mach-bcm63xx/irq.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef __ASM_MACH_BCM63XX_IRQ_H
2#define __ASM_MACH_BCM63XX_IRQ_H
3
4#define NR_IRQS 128
5#define MIPS_CPU_IRQ_BASE 0
6
7#endif
diff --git a/arch/mips/include/asm/mach-bcm63xx/war.h b/arch/mips/include/asm/mach-bcm63xx/war.h
index 05ee8671bef..8e3f3fdf320 100644
--- a/arch/mips/include/asm/mach-bcm63xx/war.h
+++ b/arch/mips/include/asm/mach-bcm63xx/war.h
@@ -17,6 +17,7 @@
17#define MIPS4K_ICACHE_REFILL_WAR 0 17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0 18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0 19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
20#define ICACHE_REFILLS_WORKAROUND_WAR 0 21#define ICACHE_REFILLS_WORKAROUND_WAR 0
21#define R10000_LLSC_WAR 0 22#define R10000_LLSC_WAR 0
22#define MIPS34K_MISSED_ITLB_WAR 0 23#define MIPS34K_MISSED_ITLB_WAR 0
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 17:01:46 -0400