aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/include/asm
diff options
context:
space:
mode:
authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-22 10:38:37 -0500
commitfcc9d2e5a6c89d22b8b773a64fb4ad21ac318446 (patch)
treea57612d1888735a2ec7972891b68c1ac5ec8faea /arch/mips/include/asm
parent8dea78da5cee153b8af9c07a2745f6c55057fe12 (diff)
Added missing tegra files.HEADmaster
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r--arch/mips/include/asm/auxvec.h4
-rw-r--r--arch/mips/include/asm/bitsperlong.h8
-rw-r--r--arch/mips/include/asm/byteorder.h19
-rw-r--r--arch/mips/include/asm/cachectl.h26
-rw-r--r--arch/mips/include/asm/fcntl.h77
-rw-r--r--arch/mips/include/asm/ioctl.h27
-rw-r--r--arch/mips/include/asm/ioctls.h110
-rw-r--r--arch/mips/include/asm/ipcbuf.h28
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx.h43
-rw-r--r--arch/mips/include/asm/mach-db1x00/db1x00.h79
-rw-r--r--arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h67
-rw-r--r--arch/mips/include/asm/mach-mipssim/war.h25
-rw-r--r--arch/mips/include/asm/mach-pb1x00/mc146818rtc.h34
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1000.h87
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1200.h141
-rw-r--r--arch/mips/include/asm/mach-pb1x00/pb1550.h73
-rw-r--r--arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h47
-rw-r--r--arch/mips/include/asm/mach-yosemite/war.h25
-rw-r--r--arch/mips/include/asm/mips-boards/simint.h31
-rw-r--r--arch/mips/include/asm/mman.h86
-rw-r--r--arch/mips/include/asm/msgbuf.h47
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pcieep-defs.h1365
-rw-r--r--arch/mips/include/asm/param.h16
-rw-r--r--arch/mips/include/asm/poll.h9
-rw-r--r--arch/mips/include/asm/posix_types.h144
-rw-r--r--arch/mips/include/asm/resource.h35
-rw-r--r--arch/mips/include/asm/sembuf.h22
-rw-r--r--arch/mips/include/asm/sgidefs.h44
-rw-r--r--arch/mips/include/asm/shmbuf.h38
-rw-r--r--arch/mips/include/asm/smvp.h19
-rw-r--r--arch/mips/include/asm/sockios.h26
-rw-r--r--arch/mips/include/asm/stat.h132
-rw-r--r--arch/mips/include/asm/statfs.h100
-rw-r--r--arch/mips/include/asm/swab.h59
-rw-r--r--arch/mips/include/asm/sysmips.h25
-rw-r--r--arch/mips/include/asm/system.h235
-rw-r--r--arch/mips/include/asm/termbits.h227
-rw-r--r--arch/mips/include/asm/titan_dep.h231
38 files changed, 3811 insertions, 0 deletions
diff --git a/arch/mips/include/asm/auxvec.h b/arch/mips/include/asm/auxvec.h
new file mode 100644
index 00000000000..7cf7f2d2194
--- /dev/null
+++ b/arch/mips/include/asm/auxvec.h
@@ -0,0 +1,4 @@
1#ifndef _ASM_AUXVEC_H
2#define _ASM_AUXVEC_H
3
4#endif /* _ASM_AUXVEC_H */
diff --git a/arch/mips/include/asm/bitsperlong.h b/arch/mips/include/asm/bitsperlong.h
new file mode 100644
index 00000000000..3e4c10a8e78
--- /dev/null
+++ b/arch/mips/include/asm/bitsperlong.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_MIPS_BITSPERLONG_H
2#define __ASM_MIPS_BITSPERLONG_H
3
4#define __BITS_PER_LONG _MIPS_SZLONG
5
6#include <asm-generic/bitsperlong.h>
7
8#endif /* __ASM_MIPS_BITSPERLONG_H */
diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
new file mode 100644
index 00000000000..9579051ff1c
--- /dev/null
+++ b/arch/mips/include/asm/byteorder.h
@@ -0,0 +1,19 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996, 99, 2003 by Ralf Baechle
7 */
8#ifndef _ASM_BYTEORDER_H
9#define _ASM_BYTEORDER_H
10
11#if defined(__MIPSEB__)
12#include <linux/byteorder/big_endian.h>
13#elif defined(__MIPSEL__)
14#include <linux/byteorder/little_endian.h>
15#else
16# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
17#endif
18
19#endif /* _ASM_BYTEORDER_H */
diff --git a/arch/mips/include/asm/cachectl.h b/arch/mips/include/asm/cachectl.h
new file mode 100644
index 00000000000..f3ce721861d
--- /dev/null
+++ b/arch/mips/include/asm/cachectl.h
@@ -0,0 +1,26 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
7 */
8#ifndef _ASM_CACHECTL
9#define _ASM_CACHECTL
10
11/*
12 * Options for cacheflush system call
13 */
14#define ICACHE (1<<0) /* flush instruction cache */
15#define DCACHE (1<<1) /* writeback and flush data cache */
16#define BCACHE (ICACHE|DCACHE) /* flush both caches */
17
18/*
19 * Caching modes for the cachectl(2) call
20 *
21 * cachectl(2) is currently not supported and returns ENOSYS.
22 */
23#define CACHEABLE 0 /* make pages cacheable */
24#define UNCACHEABLE 1 /* make pages uncacheable */
25
26#endif /* _ASM_CACHECTL */
diff --git a/arch/mips/include/asm/fcntl.h b/arch/mips/include/asm/fcntl.h
new file mode 100644
index 00000000000..75eddedcfc3
--- /dev/null
+++ b/arch/mips/include/asm/fcntl.h
@@ -0,0 +1,77 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle
7 */
8#ifndef _ASM_FCNTL_H
9#define _ASM_FCNTL_H
10
11
12#define O_APPEND 0x0008
13#define O_DSYNC 0x0010 /* used to be O_SYNC, see below */
14#define O_NONBLOCK 0x0080
15#define O_CREAT 0x0100 /* not fcntl */
16#define O_TRUNC 0x0200 /* not fcntl */
17#define O_EXCL 0x0400 /* not fcntl */
18#define O_NOCTTY 0x0800 /* not fcntl */
19#define FASYNC 0x1000 /* fcntl, for BSD compatibility */
20#define O_LARGEFILE 0x2000 /* allow large file opens */
21/*
22 * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using
23 * the O_SYNC flag. We continue to use the existing numerical value
24 * for O_DSYNC semantics now, but using the correct symbolic name for it.
25 * This new value is used to request true Posix O_SYNC semantics. It is
26 * defined in this strange way to make sure applications compiled against
27 * new headers get at least O_DSYNC semantics on older kernels.
28 *
29 * This has the nice side-effect that we can simply test for O_DSYNC
30 * wherever we do not care if O_DSYNC or O_SYNC is used.
31 *
32 * Note: __O_SYNC must never be used directly.
33 */
34#define __O_SYNC 0x4000
35#define O_SYNC (__O_SYNC|O_DSYNC)
36#define O_DIRECT 0x8000 /* direct disk access hint */
37
38#define F_GETLK 14
39#define F_SETLK 6
40#define F_SETLKW 7
41
42#define F_SETOWN 24 /* for sockets. */
43#define F_GETOWN 23 /* for sockets. */
44
45#ifndef __mips64
46#define F_GETLK64 33 /* using 'struct flock64' */
47#define F_SETLK64 34
48#define F_SETLKW64 35
49#endif
50
51/*
52 * The flavours of struct flock. "struct flock" is the ABI compliant
53 * variant. Finally struct flock64 is the LFS variant of struct flock. As
54 * a historic accident and inconsistence with the ABI definition it doesn't
55 * contain all the same fields as struct flock.
56 */
57
58#ifdef CONFIG_32BIT
59#include <linux/types.h>
60
61struct flock {
62 short l_type;
63 short l_whence;
64 off_t l_start;
65 off_t l_len;
66 long l_sysid;
67 __kernel_pid_t l_pid;
68 long pad[4];
69};
70
71#define HAVE_ARCH_STRUCT_FLOCK
72
73#endif /* CONFIG_32BIT */
74
75#include <asm-generic/fcntl.h>
76
77#endif /* _ASM_FCNTL_H */
diff --git a/arch/mips/include/asm/ioctl.h b/arch/mips/include/asm/ioctl.h
new file mode 100644
index 00000000000..c515a1a4c47
--- /dev/null
+++ b/arch/mips/include/asm/ioctl.h
@@ -0,0 +1,27 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) 2009 Wind River Systems
8 * Written by Ralf Baechle <ralf@linux-mips.org>
9 */
10#ifndef __ASM_IOCTL_H
11#define __ASM_IOCTL_H
12
13#define _IOC_SIZEBITS 13
14#define _IOC_DIRBITS 3
15
16/*
17 * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
18 * And this turns out useful to catch old ioctl numbers in header
19 * files for us.
20 */
21#define _IOC_NONE 1U
22#define _IOC_READ 2U
23#define _IOC_WRITE 4U
24
25#include <asm-generic/ioctl.h>
26
27#endif /* __ASM_IOCTL_H */
diff --git a/arch/mips/include/asm/ioctls.h b/arch/mips/include/asm/ioctls.h
new file mode 100644
index 00000000000..92403c3d600
--- /dev/null
+++ b/arch/mips/include/asm/ioctls.h
@@ -0,0 +1,110 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995, 1996, 2001 Ralf Baechle
7 * Copyright (C) 2001 MIPS Technologies, Inc.
8 */
9#ifndef __ASM_IOCTLS_H
10#define __ASM_IOCTLS_H
11
12#include <asm/ioctl.h>
13
14#define TCGETA 0x5401
15#define TCSETA 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */
16#define TCSETAW 0x5403
17#define TCSETAF 0x5404
18
19#define TCSBRK 0x5405
20#define TCXONC 0x5406
21#define TCFLSH 0x5407
22
23#define TCGETS 0x540d
24#define TCSETS 0x540e
25#define TCSETSW 0x540f
26#define TCSETSF 0x5410
27
28#define TIOCEXCL 0x740d /* set exclusive use of tty */
29#define TIOCNXCL 0x740e /* reset exclusive use of tty */
30#define TIOCOUTQ 0x7472 /* output queue size */
31#define TIOCSTI 0x5472 /* simulate terminal input */
32#define TIOCMGET 0x741d /* get all modem bits */
33#define TIOCMBIS 0x741b /* bis modem bits */
34#define TIOCMBIC 0x741c /* bic modem bits */
35#define TIOCMSET 0x741a /* set all modem bits */
36#define TIOCPKT 0x5470 /* pty: set/clear packet mode */
37#define TIOCPKT_DATA 0x00 /* data packet */
38#define TIOCPKT_FLUSHREAD 0x01 /* flush packet */
39#define TIOCPKT_FLUSHWRITE 0x02 /* flush packet */
40#define TIOCPKT_STOP 0x04 /* stop output */
41#define TIOCPKT_START 0x08 /* start output */
42#define TIOCPKT_NOSTOP 0x10 /* no more ^S, ^Q */
43#define TIOCPKT_DOSTOP 0x20 /* now do ^S ^Q */
44#define TIOCPKT_IOCTL 0x40 /* state change of pty driver */
45#define TIOCSWINSZ _IOW('t', 103, struct winsize) /* set window size */
46#define TIOCGWINSZ _IOR('t', 104, struct winsize) /* get window size */
47#define TIOCNOTTY 0x5471 /* void tty association */
48#define TIOCSETD 0x7401
49#define TIOCGETD 0x7400
50
51#define FIOCLEX 0x6601
52#define FIONCLEX 0x6602
53#define FIOASYNC 0x667d
54#define FIONBIO 0x667e
55#define FIOQSIZE 0x667f
56
57#define TIOCGLTC 0x7474 /* get special local chars */
58#define TIOCSLTC 0x7475 /* set special local chars */
59#define TIOCSPGRP _IOW('t', 118, int) /* set pgrp of tty */
60#define TIOCGPGRP _IOR('t', 119, int) /* get pgrp of tty */
61#define TIOCCONS _IOW('t', 120, int) /* become virtual console */
62
63#define FIONREAD 0x467f
64#define TIOCINQ FIONREAD
65
66#define TIOCGETP 0x7408
67#define TIOCSETP 0x7409
68#define TIOCSETN 0x740a /* TIOCSETP wo flush */
69
70/* #define TIOCSETA _IOW('t', 20, struct termios) set termios struct */
71/* #define TIOCSETAW _IOW('t', 21, struct termios) drain output, set */
72/* #define TIOCSETAF _IOW('t', 22, struct termios) drn out, fls in, set */
73/* #define TIOCGETD _IOR('t', 26, int) get line discipline */
74/* #define TIOCSETD _IOW('t', 27, int) set line discipline */
75 /* 127-124 compat */
76
77#define TIOCSBRK 0x5427 /* BSD compatibility */
78#define TIOCCBRK 0x5428 /* BSD compatibility */
79#define TIOCGSID 0x7416 /* Return the session ID of FD */
80#define TCGETS2 _IOR('T', 0x2A, struct termios2)
81#define TCSETS2 _IOW('T', 0x2B, struct termios2)
82#define TCSETSW2 _IOW('T', 0x2C, struct termios2)
83#define TCSETSF2 _IOW('T', 0x2D, struct termios2)
84#define TIOCGPTN _IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
85#define TIOCSPTLCK _IOW('T', 0x31, int) /* Lock/unlock Pty */
86#define TIOCGDEV _IOR('T', 0x32, unsigned int) /* Get primary device node of /dev/console */
87#define TIOCSIG _IOW('T', 0x36, int) /* Generate signal on Pty slave */
88#define TIOCVHANGUP 0x5437
89
90/* I hope the range from 0x5480 on is free ... */
91#define TIOCSCTTY 0x5480 /* become controlling tty */
92#define TIOCGSOFTCAR 0x5481
93#define TIOCSSOFTCAR 0x5482
94#define TIOCLINUX 0x5483
95#define TIOCGSERIAL 0x5484
96#define TIOCSSERIAL 0x5485
97#define TCSBRKP 0x5486 /* Needed for POSIX tcsendbreak() */
98#define TIOCSERCONFIG 0x5488
99#define TIOCSERGWILD 0x5489
100#define TIOCSERSWILD 0x548a
101#define TIOCGLCKTRMIOS 0x548b
102#define TIOCSLCKTRMIOS 0x548c
103#define TIOCSERGSTRUCT 0x548d /* For debugging only */
104#define TIOCSERGETLSR 0x548e /* Get line status register */
105#define TIOCSERGETMULTI 0x548f /* Get multiport config */
106#define TIOCSERSETMULTI 0x5490 /* Set multiport config */
107#define TIOCMIWAIT 0x5491 /* wait for a change on serial input line(s) */
108#define TIOCGICOUNT 0x5492 /* read serial port inline interrupt counts */
109
110#endif /* __ASM_IOCTLS_H */
diff --git a/arch/mips/include/asm/ipcbuf.h b/arch/mips/include/asm/ipcbuf.h
new file mode 100644
index 00000000000..d47d08f264e
--- /dev/null
+++ b/arch/mips/include/asm/ipcbuf.h
@@ -0,0 +1,28 @@
1#ifndef _ASM_IPCBUF_H
2#define _ASM_IPCBUF_H
3
4/*
5 * The ipc64_perm structure for alpha architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 32-bit seq
11 * - 2 miscellaneous 64-bit values
12 */
13
14struct ipc64_perm
15{
16 __kernel_key_t key;
17 __kernel_uid_t uid;
18 __kernel_gid_t gid;
19 __kernel_uid_t cuid;
20 __kernel_gid_t cgid;
21 __kernel_mode_t mode;
22 unsigned short seq;
23 unsigned short __pad1;
24 unsigned long __unused1;
25 unsigned long __unused2;
26};
27
28#endif /* _ASM_IPCBUF_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx.h b/arch/mips/include/asm/mach-au1x00/au1xxx.h
new file mode 100644
index 00000000000..1b3655090ed
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx.h
@@ -0,0 +1,43 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
12 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
13 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
14 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
15 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
16 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _AU1XXX_H_
24#define _AU1XXX_H_
25
26#include <asm/mach-au1x00/au1000.h>
27
28#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
29 defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
30#include <asm/mach-db1x00/db1x00.h>
31
32#elif defined(CONFIG_MIPS_PB1550)
33#include <asm/mach-pb1x00/pb1550.h>
34
35#elif defined(CONFIG_MIPS_PB1200)
36#include <asm/mach-pb1x00/pb1200.h>
37
38#elif defined(CONFIG_MIPS_DB1200)
39#include <asm/mach-db1x00/db1200.h>
40
41#endif
42
43#endif /* _AU1XXX_H_ */
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
new file mode 100644
index 00000000000..a919dac525a
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/db1x00.h
@@ -0,0 +1,79 @@
1/*
2 * AMD Alchemy DBAu1x00 Reference Boards
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_DB1X00_H
28#define __ASM_DB1X00_H
29
30#include <asm/mach-au1x00/au1xxx_psc.h>
31
32#ifdef CONFIG_MIPS_DB1550
33
34#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
35#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
36#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
37#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
38
39#define SPI_PSC_BASE PSC0_BASE_ADDR
40#define AC97_PSC_BASE PSC1_BASE_ADDR
41#define SMBUS_PSC_BASE PSC2_BASE_ADDR
42#define I2S_PSC_BASE PSC3_BASE_ADDR
43
44#define NAND_PHYS_ADDR 0x20000000
45
46#endif
47
48/*
49 * NAND defines
50 *
51 * Timing values as described in databook, * ns value stripped of the
52 * lower 2 bits.
53 * These defines are here rather than an Au1550 generic file because
54 * the parts chosen on another board may be different and may require
55 * different timings.
56 */
57#define NAND_T_H (18 >> 2)
58#define NAND_T_PUL (30 >> 2)
59#define NAND_T_SU (30 >> 2)
60#define NAND_T_WH (30 >> 2)
61
62/* Bitfield shift amounts */
63#define NAND_T_H_SHIFT 0
64#define NAND_T_PUL_SHIFT 4
65#define NAND_T_SU_SHIFT 8
66#define NAND_T_WH_SHIFT 12
67
68#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
69 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
70 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
71 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
72#define NAND_CS 1
73
74/* Should be done by YAMON */
75#define NAND_STCFG 0x00400005 /* 8-bit NAND */
76#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
77#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
78
79#endif /* __ASM_DB1X00_H */
diff --git a/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h b/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h
new file mode 100644
index 00000000000..27aaaa5d925
--- /dev/null
+++ b/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h
@@ -0,0 +1,67 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 2004 Chris Dearman
7 */
8#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
10
11
12/*
13 * CPU feature overrides for MIPS boards
14 */
15#ifdef CONFIG_CPU_MIPS32
16#define cpu_has_tlb 1
17#define cpu_has_4kex 1
18#define cpu_has_4k_cache 1
19#define cpu_has_fpu 0
20/* #define cpu_has_32fpr ? */
21#define cpu_has_counter 1
22/* #define cpu_has_watch ? */
23#define cpu_has_divec 1
24#define cpu_has_vce 0
25/* #define cpu_has_cache_cdex_p ? */
26/* #define cpu_has_cache_cdex_s ? */
27/* #define cpu_has_prefetch ? */
28#define cpu_has_mcheck 1
29/* #define cpu_has_ejtag ? */
30#define cpu_has_llsc 1
31/* #define cpu_has_vtag_icache ? */
32/* #define cpu_has_dc_aliases ? */
33/* #define cpu_has_ic_fills_f_dc ? */
34#define cpu_has_clo_clz 1
35#define cpu_has_nofpuex 0
36/* #define cpu_has_64bits ? */
37/* #define cpu_has_64bit_zero_reg ? */
38/* #define cpu_has_inclusive_pcaches ? */
39#endif
40
41#ifdef CONFIG_CPU_MIPS64
42#define cpu_has_tlb 1
43#define cpu_has_4kex 1
44#define cpu_has_4k_cache 1
45/* #define cpu_has_fpu ? */
46/* #define cpu_has_32fpr ? */
47#define cpu_has_counter 1
48/* #define cpu_has_watch ? */
49#define cpu_has_divec 1
50#define cpu_has_vce 0
51/* #define cpu_has_cache_cdex_p ? */
52/* #define cpu_has_cache_cdex_s ? */
53/* #define cpu_has_prefetch ? */
54#define cpu_has_mcheck 1
55/* #define cpu_has_ejtag ? */
56#define cpu_has_llsc 1
57/* #define cpu_has_vtag_icache ? */
58/* #define cpu_has_dc_aliases ? */
59/* #define cpu_has_ic_fills_f_dc ? */
60#define cpu_has_clo_clz 1
61#define cpu_has_nofpuex 0
62/* #define cpu_has_64bits ? */
63/* #define cpu_has_64bit_zero_reg ? */
64/* #define cpu_has_inclusive_pcaches ? */
65#endif
66
67#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-mipssim/war.h b/arch/mips/include/asm/mach-mipssim/war.h
new file mode 100644
index 00000000000..c8a74a3515e
--- /dev/null
+++ b/arch/mips/include/asm/mach-mipssim/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H
9#define __ASM_MIPS_MACH_MIPSSIM_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 0
21#define ICACHE_REFILLS_WORKAROUND_WAR 0
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
new file mode 100644
index 00000000000..622c58710e5
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
@@ -0,0 +1,34 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1998, 2001, 03 by Ralf Baechle
7 *
8 * RTC routines for PC style attached Dallas chip.
9 */
10#ifndef __ASM_MACH_AU1XX_MC146818RTC_H
11#define __ASM_MACH_AU1XX_MC146818RTC_H
12
13#include <asm/io.h>
14#include <asm/mach-au1x00/au1000.h>
15
16#define RTC_PORT(x) (0x0c000000 + (x))
17#define RTC_IRQ 8
18#define PB1500_RTC_ADDR 0x0c000000
19
20static inline unsigned char CMOS_READ(unsigned long offset)
21{
22 offset <<= 2;
23 return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff);
24}
25
26static inline void CMOS_WRITE(unsigned char data, unsigned long offset)
27{
28 offset <<= 2;
29 au_writel(data, offset + PB1500_RTC_ADDR);
30}
31
32#define RTC_ALWAYS_BCD 1
33
34#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h
new file mode 100644
index 00000000000..65059255dc1
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1000.h
@@ -0,0 +1,87 @@
1/*
2 * Alchemy Semi Pb1000 Reference Board
3 *
4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 *
7 * ########################################################################
8 *
9 * This program is free software; you can distribute it and/or modify it
10 * under the terms of the GNU General Public License (Version 2) as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
21 *
22 * ########################################################################
23 *
24 *
25 */
26#ifndef __ASM_PB1000_H
27#define __ASM_PB1000_H
28
29/* PCMCIA PB1000 specific defines */
30#define PCMCIA_MAX_SOCK 1
31#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
32
33#define PB1000_PCR 0xBE000000
34# define PCR_SLOT_0_VPP0 (1 << 0)
35# define PCR_SLOT_0_VPP1 (1 << 1)
36# define PCR_SLOT_0_VCC0 (1 << 2)
37# define PCR_SLOT_0_VCC1 (1 << 3)
38# define PCR_SLOT_0_RST (1 << 4)
39# define PCR_SLOT_1_VPP0 (1 << 8)
40# define PCR_SLOT_1_VPP1 (1 << 9)
41# define PCR_SLOT_1_VCC0 (1 << 10)
42# define PCR_SLOT_1_VCC1 (1 << 11)
43# define PCR_SLOT_1_RST (1 << 12)
44
45#define PB1000_MDR 0xBE000004
46# define MDR_PI (1 << 5) /* PCMCIA int latch */
47# define MDR_EPI (1 << 14) /* enable PCMCIA int */
48# define MDR_CPI (1 << 15) /* clear PCMCIA int */
49
50#define PB1000_ACR1 0xBE000008
51# define ACR1_SLOT_0_CD1 (1 << 0) /* card detect 1 */
52# define ACR1_SLOT_0_CD2 (1 << 1) /* card detect 2 */
53# define ACR1_SLOT_0_READY (1 << 2) /* ready */
54# define ACR1_SLOT_0_STATUS (1 << 3) /* status change */
55# define ACR1_SLOT_0_VS1 (1 << 4) /* voltage sense 1 */
56# define ACR1_SLOT_0_VS2 (1 << 5) /* voltage sense 2 */
57# define ACR1_SLOT_0_INPACK (1 << 6) /* inpack pin status */
58# define ACR1_SLOT_1_CD1 (1 << 8) /* card detect 1 */
59# define ACR1_SLOT_1_CD2 (1 << 9) /* card detect 2 */
60# define ACR1_SLOT_1_READY (1 << 10) /* ready */
61# define ACR1_SLOT_1_STATUS (1 << 11) /* status change */
62# define ACR1_SLOT_1_VS1 (1 << 12) /* voltage sense 1 */
63# define ACR1_SLOT_1_VS2 (1 << 13) /* voltage sense 2 */
64# define ACR1_SLOT_1_INPACK (1 << 14) /* inpack pin status */
65
66#define CPLD_AUX0 0xBE00000C
67#define CPLD_AUX1 0xBE000010
68#define CPLD_AUX2 0xBE000014
69
70/* Voltage levels */
71
72/* VPPEN1 - VPPEN0 */
73#define VPP_GND ((0 << 1) | (0 << 0))
74#define VPP_5V ((1 << 1) | (0 << 0))
75#define VPP_3V ((0 << 1) | (1 << 0))
76#define VPP_12V ((0 << 1) | (1 << 0))
77#define VPP_HIZ ((1 << 1) | (1 << 0))
78
79/* VCCEN1 - VCCEN0 */
80#define VCC_3V ((0 << 1) | (1 << 0))
81#define VCC_5V ((1 << 1) | (0 << 0))
82#define VCC_HIZ ((0 << 1) | (0 << 0))
83
84/* VPP/VCC */
85#define SET_VCC_VPP(VCC, VPP, SLOT) \
86 ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
87#endif /* __ASM_PB1000_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
new file mode 100644
index 00000000000..fce4332ebb7
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -0,0 +1,141 @@
1/*
2 * AMD Alchemy Pb1200 Reference Board
3 * Board Registers defines.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 *
23 */
24#ifndef __ASM_PB1200_H
25#define __ASM_PB1200_H
26
27#include <linux/types.h>
28#include <asm/mach-au1x00/au1000.h>
29#include <asm/mach-au1x00/au1xxx_psc.h>
30
31#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
32#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
33#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
34#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
35
36/*
37 * SPI and SMB are muxed on the Pb1200 board.
38 * Refer to board documentation.
39 */
40#define SPI_PSC_BASE PSC0_BASE_ADDR
41#define SMBUS_PSC_BASE PSC0_BASE_ADDR
42/*
43 * AC97 and I2S are muxed on the Pb1200 board.
44 * Refer to board documentation.
45 */
46#define AC97_PSC_BASE PSC1_BASE_ADDR
47#define I2S_PSC_BASE PSC1_BASE_ADDR
48
49
50#define BCSR_SYSTEM_VDDI 0x001F
51#define BCSR_SYSTEM_POWEROFF 0x4000
52#define BCSR_SYSTEM_RESET 0x8000
53
54/* Bit positions for the different interrupt sources */
55#define BCSR_INT_IDE 0x0001
56#define BCSR_INT_ETH 0x0002
57#define BCSR_INT_PC0 0x0004
58#define BCSR_INT_PC0STSCHG 0x0008
59#define BCSR_INT_PC1 0x0010
60#define BCSR_INT_PC1STSCHG 0x0020
61#define BCSR_INT_DC 0x0040
62#define BCSR_INT_FLASHBUSY 0x0080
63#define BCSR_INT_PC0INSERT 0x0100
64#define BCSR_INT_PC0EJECT 0x0200
65#define BCSR_INT_PC1INSERT 0x0400
66#define BCSR_INT_PC1EJECT 0x0800
67#define BCSR_INT_SD0INSERT 0x1000
68#define BCSR_INT_SD0EJECT 0x2000
69#define BCSR_INT_SD1INSERT 0x4000
70#define BCSR_INT_SD1EJECT 0x8000
71
72#define SMC91C111_PHYS_ADDR 0x0D000300
73#define SMC91C111_INT PB1200_ETH_INT
74
75#define IDE_PHYS_ADDR 0x0C800000
76#define IDE_REG_SHIFT 5
77#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
78#define IDE_INT PB1200_IDE_INT
79#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
80#define IDE_RQSIZE 128
81
82#define NAND_PHYS_ADDR 0x1C000000
83
84/*
85 * Timing values as described in databook, * ns value stripped of
86 * lower 2 bits.
87 * These defines are here rather than an Au1200 generic file because
88 * the parts chosen on another board may be different and may require
89 * different timings.
90 */
91#define NAND_T_H (18 >> 2)
92#define NAND_T_PUL (30 >> 2)
93#define NAND_T_SU (30 >> 2)
94#define NAND_T_WH (30 >> 2)
95
96/* Bitfield shift amounts */
97#define NAND_T_H_SHIFT 0
98#define NAND_T_PUL_SHIFT 4
99#define NAND_T_SU_SHIFT 8
100#define NAND_T_WH_SHIFT 12
101
102#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
103 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
104 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
105 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
106
107/*
108 * External Interrupts for Pb1200 as of 8/6/2004.
109 * Bit positions in the CPLD registers can be calculated by taking
110 * the interrupt define and subtracting the PB1200_INT_BEGIN value.
111 *
112 * Example: IDE bis pos is = 64 - 64
113 * ETH bit pos is = 65 - 64
114 */
115enum external_pb1200_ints {
116 PB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
117
118 PB1200_IDE_INT = PB1200_INT_BEGIN,
119 PB1200_ETH_INT,
120 PB1200_PC0_INT,
121 PB1200_PC0_STSCHG_INT,
122 PB1200_PC1_INT,
123 PB1200_PC1_STSCHG_INT,
124 PB1200_DC_INT,
125 PB1200_FLASHBUSY_INT,
126 PB1200_PC0_INSERT_INT,
127 PB1200_PC0_EJECT_INT,
128 PB1200_PC1_INSERT_INT,
129 PB1200_PC1_EJECT_INT,
130 PB1200_SD0_INSERT_INT,
131 PB1200_SD0_EJECT_INT,
132 PB1200_SD1_INSERT_INT,
133 PB1200_SD1_EJECT_INT,
134
135 PB1200_INT_END = PB1200_INT_BEGIN + 15
136};
137
138/* NAND chip select */
139#define NAND_CS 1
140
141#endif /* __ASM_PB1200_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
new file mode 100644
index 00000000000..f835c88e959
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -0,0 +1,73 @@
1/*
2 * AMD Alchemy Semi PB1550 Reference Board
3 * Board Registers defines.
4 *
5 * Copyright 2004 Embedded Edge LLC.
6 * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
7 *
8 * ########################################################################
9 *
10 * This program is free software; you can distribute it and/or modify it
11 * under the terms of the GNU General Public License (Version 2) as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed in the hope it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * for more details.
18 *
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, write to the Free Software Foundation, Inc.,
21 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
22 *
23 * ########################################################################
24 *
25 *
26 */
27#ifndef __ASM_PB1550_H
28#define __ASM_PB1550_H
29
30#include <linux/types.h>
31#include <asm/mach-au1x00/au1xxx_psc.h>
32
33#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
34#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
35#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
36#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
37
38#define SPI_PSC_BASE PSC0_BASE_ADDR
39#define AC97_PSC_BASE PSC1_BASE_ADDR
40#define SMBUS_PSC_BASE PSC2_BASE_ADDR
41#define I2S_PSC_BASE PSC3_BASE_ADDR
42
43/*
44 * Timing values as described in databook, * ns value stripped of
45 * lower 2 bits.
46 * These defines are here rather than an SOC1550 generic file because
47 * the parts chosen on another board may be different and may require
48 * different timings.
49 */
50#define NAND_T_H (18 >> 2)
51#define NAND_T_PUL (30 >> 2)
52#define NAND_T_SU (30 >> 2)
53#define NAND_T_WH (30 >> 2)
54
55/* Bitfield shift amounts */
56#define NAND_T_H_SHIFT 0
57#define NAND_T_PUL_SHIFT 4
58#define NAND_T_SU_SHIFT 8
59#define NAND_T_WH_SHIFT 12
60
61#define NAND_TIMING (((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
62 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
63 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
64 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT))
65
66#define NAND_CS 1
67
68/* Should be done by YAMON */
69#define NAND_STCFG 0x00400005 /* 8-bit NAND */
70#define NAND_STTIME 0x00007774 /* valid for 396 MHz SD=2 only */
71#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
72
73#endif /* __ASM_PB1550_H */
diff --git a/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h
new file mode 100644
index 00000000000..470e5e9e10d
--- /dev/null
+++ b/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h
@@ -0,0 +1,47 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
7 */
8#ifndef __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
10
11/*
12 * Momentum Jaguar ATX always has the RM9000 processor.
13 */
14#define cpu_has_watch 1
15#define cpu_has_mips16 0
16#define cpu_has_divec 0
17#define cpu_has_vce 0
18#define cpu_has_cache_cdex_p 0
19#define cpu_has_cache_cdex_s 0
20#define cpu_has_prefetch 1
21#define cpu_has_mcheck 0
22#define cpu_has_ejtag 0
23
24#define cpu_has_llsc 1
25#define cpu_has_vtag_icache 0
26#define cpu_has_dc_aliases 0
27#define cpu_has_ic_fills_f_dc 0
28#define cpu_has_dsp 0
29#define cpu_has_mipsmt 0
30#define cpu_has_userlocal 0
31#define cpu_icache_snoops_remote_store 0
32
33#define cpu_has_nofpuex 0
34#define cpu_has_64bits 1
35
36#define cpu_has_inclusive_pcaches 0
37
38#define cpu_dcache_line_size() 32
39#define cpu_icache_line_size() 32
40#define cpu_scache_line_size() 32
41
42#define cpu_has_mips32r1 0
43#define cpu_has_mips32r2 0
44#define cpu_has_mips64r1 0
45#define cpu_has_mips64r2 0
46
47#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-yosemite/war.h b/arch/mips/include/asm/mach-yosemite/war.h
new file mode 100644
index 00000000000..e5c6d53efc8
--- /dev/null
+++ b/arch/mips/include/asm/mach-yosemite/war.h
@@ -0,0 +1,25 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 */
8#ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H
9#define __ASM_MIPS_MACH_YOSEMITE_WAR_H
10
11#define R4600_V1_INDEX_ICACHEOP_WAR 0
12#define R4600_V1_HIT_CACHEOP_WAR 0
13#define R4600_V2_HIT_CACHEOP_WAR 0
14#define R5432_CP0_INTERRUPT_WAR 0
15#define BCM1250_M3_WAR 0
16#define SIBYTE_1956_WAR 0
17#define MIPS4K_ICACHE_REFILL_WAR 0
18#define MIPS_CACHE_SYNC_WAR 0
19#define TX49XX_ICACHE_INDEX_INV_WAR 0
20#define RM9000_CDEX_SMP_WAR 1
21#define ICACHE_REFILLS_WORKAROUND_WAR 1
22#define R10000_LLSC_WAR 0
23#define MIPS34K_MISSED_ITLB_WAR 0
24
25#endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */
diff --git a/arch/mips/include/asm/mips-boards/simint.h b/arch/mips/include/asm/mips-boards/simint.h
new file mode 100644
index 00000000000..8ef6db76d5c
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/simint.h
@@ -0,0 +1,31 @@
1/*
2 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 */
17#ifndef _MIPS_SIMINT_H
18#define _MIPS_SIMINT_H
19
20#include <irq.h>
21
22#define SIM_INT_BASE 0
23#define MIPSCPU_INT_MB0 2
24#define MIPS_CPU_TIMER_IRQ 7
25
26
27#define MSC01E_INT_BASE 64
28
29#define MSC01E_INT_CPUCTR 11
30
31#endif
diff --git a/arch/mips/include/asm/mman.h b/arch/mips/include/asm/mman.h
new file mode 100644
index 00000000000..785b4ea4ec3
--- /dev/null
+++ b/arch/mips/include/asm/mman.h
@@ -0,0 +1,86 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995, 1999, 2002 by Ralf Baechle
7 */
8#ifndef _ASM_MMAN_H
9#define _ASM_MMAN_H
10
11/*
12 * Protections are chosen from these bits, OR'd together. The
13 * implementation does not necessarily support PROT_EXEC or PROT_WRITE
14 * without PROT_READ. The only guarantees are that no writing will be
15 * allowed without PROT_WRITE and no access will be allowed for PROT_NONE.
16 */
17#define PROT_NONE 0x00 /* page can not be accessed */
18#define PROT_READ 0x01 /* page can be read */
19#define PROT_WRITE 0x02 /* page can be written */
20#define PROT_EXEC 0x04 /* page can be executed */
21/* 0x08 reserved for PROT_EXEC_NOFLUSH */
22#define PROT_SEM 0x10 /* page may be used for atomic ops */
23#define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
24#define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
25
26/*
27 * Flags for mmap
28 */
29#define MAP_SHARED 0x001 /* Share changes */
30#define MAP_PRIVATE 0x002 /* Changes are private */
31#define MAP_TYPE 0x00f /* Mask for type of mapping */
32#define MAP_FIXED 0x010 /* Interpret addr exactly */
33
34/* not used by linux, but here to make sure we don't clash with ABI defines */
35#define MAP_RENAME 0x020 /* Assign page to file */
36#define MAP_AUTOGROW 0x040 /* File may grow by writing */
37#define MAP_LOCAL 0x080 /* Copy on fork/sproc */
38#define MAP_AUTORSRV 0x100 /* Logical swap reserved on demand */
39
40/* These are linux-specific */
41#define MAP_NORESERVE 0x0400 /* don't check for reservations */
42#define MAP_ANONYMOUS 0x0800 /* don't use a file */
43#define MAP_GROWSDOWN 0x1000 /* stack-like segment */
44#define MAP_DENYWRITE 0x2000 /* ETXTBSY */
45#define MAP_EXECUTABLE 0x4000 /* mark it as an executable */
46#define MAP_LOCKED 0x8000 /* pages are locked */
47#define MAP_POPULATE 0x10000 /* populate (prefault) pagetables */
48#define MAP_NONBLOCK 0x20000 /* do not block on IO */
49#define MAP_STACK 0x40000 /* give out an address that is best suited for process/thread stacks */
50#define MAP_HUGETLB 0x80000 /* create a huge page mapping */
51
52/*
53 * Flags for msync
54 */
55#define MS_ASYNC 0x0001 /* sync memory asynchronously */
56#define MS_INVALIDATE 0x0002 /* invalidate mappings & caches */
57#define MS_SYNC 0x0004 /* synchronous memory sync */
58
59/*
60 * Flags for mlockall
61 */
62#define MCL_CURRENT 1 /* lock all current mappings */
63#define MCL_FUTURE 2 /* lock all future mappings */
64
65#define MADV_NORMAL 0 /* no further special treatment */
66#define MADV_RANDOM 1 /* expect random page references */
67#define MADV_SEQUENTIAL 2 /* expect sequential page references */
68#define MADV_WILLNEED 3 /* will need these pages */
69#define MADV_DONTNEED 4 /* don't need these pages */
70
71/* common parameters: try to keep these consistent across architectures */
72#define MADV_REMOVE 9 /* remove these pages & resources */
73#define MADV_DONTFORK 10 /* don't inherit across fork */
74#define MADV_DOFORK 11 /* do inherit across fork */
75
76#define MADV_MERGEABLE 12 /* KSM may merge identical pages */
77#define MADV_UNMERGEABLE 13 /* KSM may not merge identical pages */
78#define MADV_HWPOISON 100 /* poison a page for testing */
79
80#define MADV_HUGEPAGE 14 /* Worth backing with hugepages */
81#define MADV_NOHUGEPAGE 15 /* Not worth backing with hugepages */
82
83/* compatibility flags */
84#define MAP_FILE 0
85
86#endif /* _ASM_MMAN_H */
diff --git a/arch/mips/include/asm/msgbuf.h b/arch/mips/include/asm/msgbuf.h
new file mode 100644
index 00000000000..0d6c7f14de3
--- /dev/null
+++ b/arch/mips/include/asm/msgbuf.h
@@ -0,0 +1,47 @@
1#ifndef _ASM_MSGBUF_H
2#define _ASM_MSGBUF_H
3
4
5/*
6 * The msqid64_ds structure for the MIPS architecture.
7 * Note extra padding because this structure is passed back and forth
8 * between kernel and user space.
9 *
10 * Pad space is left for:
11 * - extension of time_t to 64-bit on 32-bitsystem to solve the y2038 problem
12 * - 2 miscellaneous unsigned long values
13 */
14
15struct msqid64_ds {
16 struct ipc64_perm msg_perm;
17#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
18 unsigned long __unused1;
19#endif
20 __kernel_time_t msg_stime; /* last msgsnd time */
21#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
22 unsigned long __unused1;
23#endif
24#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
25 unsigned long __unused2;
26#endif
27 __kernel_time_t msg_rtime; /* last msgrcv time */
28#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
29 unsigned long __unused2;
30#endif
31#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
32 unsigned long __unused3;
33#endif
34 __kernel_time_t msg_ctime; /* last change time */
35#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
36 unsigned long __unused3;
37#endif
38 unsigned long msg_cbytes; /* current number of bytes on queue */
39 unsigned long msg_qnum; /* number of messages in queue */
40 unsigned long msg_qbytes; /* max number of bytes on queue */
41 __kernel_pid_t msg_lspid; /* pid of last msgsnd */
42 __kernel_pid_t msg_lrpid; /* last receive pid */
43 unsigned long __unused4;
44 unsigned long __unused5;
45};
46
47#endif /* _ASM_MSGBUF_H */
diff --git a/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h b/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
new file mode 100644
index 00000000000..d553f8e88df
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
@@ -0,0 +1,1365 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_PCIEEP_DEFS_H__
29#define __CVMX_PCIEEP_DEFS_H__
30
31#define CVMX_PCIEEP_CFG000 \
32 (0x0000000000000000ull)
33#define CVMX_PCIEEP_CFG001 \
34 (0x0000000000000004ull)
35#define CVMX_PCIEEP_CFG002 \
36 (0x0000000000000008ull)
37#define CVMX_PCIEEP_CFG003 \
38 (0x000000000000000Cull)
39#define CVMX_PCIEEP_CFG004 \
40 (0x0000000000000010ull)
41#define CVMX_PCIEEP_CFG004_MASK \
42 (0x0000000080000010ull)
43#define CVMX_PCIEEP_CFG005 \
44 (0x0000000000000014ull)
45#define CVMX_PCIEEP_CFG005_MASK \
46 (0x0000000080000014ull)
47#define CVMX_PCIEEP_CFG006 \
48 (0x0000000000000018ull)
49#define CVMX_PCIEEP_CFG006_MASK \
50 (0x0000000080000018ull)
51#define CVMX_PCIEEP_CFG007 \
52 (0x000000000000001Cull)
53#define CVMX_PCIEEP_CFG007_MASK \
54 (0x000000008000001Cull)
55#define CVMX_PCIEEP_CFG008 \
56 (0x0000000000000020ull)
57#define CVMX_PCIEEP_CFG008_MASK \
58 (0x0000000080000020ull)
59#define CVMX_PCIEEP_CFG009 \
60 (0x0000000000000024ull)
61#define CVMX_PCIEEP_CFG009_MASK \
62 (0x0000000080000024ull)
63#define CVMX_PCIEEP_CFG010 \
64 (0x0000000000000028ull)
65#define CVMX_PCIEEP_CFG011 \
66 (0x000000000000002Cull)
67#define CVMX_PCIEEP_CFG012 \
68 (0x0000000000000030ull)
69#define CVMX_PCIEEP_CFG012_MASK \
70 (0x0000000080000030ull)
71#define CVMX_PCIEEP_CFG013 \
72 (0x0000000000000034ull)
73#define CVMX_PCIEEP_CFG015 \
74 (0x000000000000003Cull)
75#define CVMX_PCIEEP_CFG016 \
76 (0x0000000000000040ull)
77#define CVMX_PCIEEP_CFG017 \
78 (0x0000000000000044ull)
79#define CVMX_PCIEEP_CFG020 \
80 (0x0000000000000050ull)
81#define CVMX_PCIEEP_CFG021 \
82 (0x0000000000000054ull)
83#define CVMX_PCIEEP_CFG022 \
84 (0x0000000000000058ull)
85#define CVMX_PCIEEP_CFG023 \
86 (0x000000000000005Cull)
87#define CVMX_PCIEEP_CFG028 \
88 (0x0000000000000070ull)
89#define CVMX_PCIEEP_CFG029 \
90 (0x0000000000000074ull)
91#define CVMX_PCIEEP_CFG030 \
92 (0x0000000000000078ull)
93#define CVMX_PCIEEP_CFG031 \
94 (0x000000000000007Cull)
95#define CVMX_PCIEEP_CFG032 \
96 (0x0000000000000080ull)
97#define CVMX_PCIEEP_CFG033 \
98 (0x0000000000000084ull)
99#define CVMX_PCIEEP_CFG034 \
100 (0x0000000000000088ull)
101#define CVMX_PCIEEP_CFG037 \
102 (0x0000000000000094ull)
103#define CVMX_PCIEEP_CFG038 \
104 (0x0000000000000098ull)
105#define CVMX_PCIEEP_CFG039 \
106 (0x000000000000009Cull)
107#define CVMX_PCIEEP_CFG040 \
108 (0x00000000000000A0ull)
109#define CVMX_PCIEEP_CFG041 \
110 (0x00000000000000A4ull)
111#define CVMX_PCIEEP_CFG042 \
112 (0x00000000000000A8ull)
113#define CVMX_PCIEEP_CFG064 \
114 (0x0000000000000100ull)
115#define CVMX_PCIEEP_CFG065 \
116 (0x0000000000000104ull)
117#define CVMX_PCIEEP_CFG066 \
118 (0x0000000000000108ull)
119#define CVMX_PCIEEP_CFG067 \
120 (0x000000000000010Cull)
121#define CVMX_PCIEEP_CFG068 \
122 (0x0000000000000110ull)
123#define CVMX_PCIEEP_CFG069 \
124 (0x0000000000000114ull)
125#define CVMX_PCIEEP_CFG070 \
126 (0x0000000000000118ull)
127#define CVMX_PCIEEP_CFG071 \
128 (0x000000000000011Cull)
129#define CVMX_PCIEEP_CFG072 \
130 (0x0000000000000120ull)
131#define CVMX_PCIEEP_CFG073 \
132 (0x0000000000000124ull)
133#define CVMX_PCIEEP_CFG074 \
134 (0x0000000000000128ull)
135#define CVMX_PCIEEP_CFG448 \
136 (0x0000000000000700ull)
137#define CVMX_PCIEEP_CFG449 \
138 (0x0000000000000704ull)
139#define CVMX_PCIEEP_CFG450 \
140 (0x0000000000000708ull)
141#define CVMX_PCIEEP_CFG451 \
142 (0x000000000000070Cull)
143#define CVMX_PCIEEP_CFG452 \
144 (0x0000000000000710ull)
145#define CVMX_PCIEEP_CFG453 \
146 (0x0000000000000714ull)
147#define CVMX_PCIEEP_CFG454 \
148 (0x0000000000000718ull)
149#define CVMX_PCIEEP_CFG455 \
150 (0x000000000000071Cull)
151#define CVMX_PCIEEP_CFG456 \
152 (0x0000000000000720ull)
153#define CVMX_PCIEEP_CFG458 \
154 (0x0000000000000728ull)
155#define CVMX_PCIEEP_CFG459 \
156 (0x000000000000072Cull)
157#define CVMX_PCIEEP_CFG460 \
158 (0x0000000000000730ull)
159#define CVMX_PCIEEP_CFG461 \
160 (0x0000000000000734ull)
161#define CVMX_PCIEEP_CFG462 \
162 (0x0000000000000738ull)
163#define CVMX_PCIEEP_CFG463 \
164 (0x000000000000073Cull)
165#define CVMX_PCIEEP_CFG464 \
166 (0x0000000000000740ull)
167#define CVMX_PCIEEP_CFG465 \
168 (0x0000000000000744ull)
169#define CVMX_PCIEEP_CFG466 \
170 (0x0000000000000748ull)
171#define CVMX_PCIEEP_CFG467 \
172 (0x000000000000074Cull)
173#define CVMX_PCIEEP_CFG468 \
174 (0x0000000000000750ull)
175#define CVMX_PCIEEP_CFG490 \
176 (0x00000000000007A8ull)
177#define CVMX_PCIEEP_CFG491 \
178 (0x00000000000007ACull)
179#define CVMX_PCIEEP_CFG492 \
180 (0x00000000000007B0ull)
181#define CVMX_PCIEEP_CFG516 \
182 (0x0000000000000810ull)
183#define CVMX_PCIEEP_CFG517 \
184 (0x0000000000000814ull)
185
186union cvmx_pcieep_cfg000 {
187 uint32_t u32;
188 struct cvmx_pcieep_cfg000_s {
189 uint32_t devid:16;
190 uint32_t vendid:16;
191 } s;
192 struct cvmx_pcieep_cfg000_s cn52xx;
193 struct cvmx_pcieep_cfg000_s cn52xxp1;
194 struct cvmx_pcieep_cfg000_s cn56xx;
195 struct cvmx_pcieep_cfg000_s cn56xxp1;
196};
197
198union cvmx_pcieep_cfg001 {
199 uint32_t u32;
200 struct cvmx_pcieep_cfg001_s {
201 uint32_t dpe:1;
202 uint32_t sse:1;
203 uint32_t rma:1;
204 uint32_t rta:1;
205 uint32_t sta:1;
206 uint32_t devt:2;
207 uint32_t mdpe:1;
208 uint32_t fbb:1;
209 uint32_t reserved_22_22:1;
210 uint32_t m66:1;
211 uint32_t cl:1;
212 uint32_t i_stat:1;
213 uint32_t reserved_11_18:8;
214 uint32_t i_dis:1;
215 uint32_t fbbe:1;
216 uint32_t see:1;
217 uint32_t ids_wcc:1;
218 uint32_t per:1;
219 uint32_t vps:1;
220 uint32_t mwice:1;
221 uint32_t scse:1;
222 uint32_t me:1;
223 uint32_t msae:1;
224 uint32_t isae:1;
225 } s;
226 struct cvmx_pcieep_cfg001_s cn52xx;
227 struct cvmx_pcieep_cfg001_s cn52xxp1;
228 struct cvmx_pcieep_cfg001_s cn56xx;
229 struct cvmx_pcieep_cfg001_s cn56xxp1;
230};
231
232union cvmx_pcieep_cfg002 {
233 uint32_t u32;
234 struct cvmx_pcieep_cfg002_s {
235 uint32_t bcc:8;
236 uint32_t sc:8;
237 uint32_t pi:8;
238 uint32_t rid:8;
239 } s;
240 struct cvmx_pcieep_cfg002_s cn52xx;
241 struct cvmx_pcieep_cfg002_s cn52xxp1;
242 struct cvmx_pcieep_cfg002_s cn56xx;
243 struct cvmx_pcieep_cfg002_s cn56xxp1;
244};
245
246union cvmx_pcieep_cfg003 {
247 uint32_t u32;
248 struct cvmx_pcieep_cfg003_s {
249 uint32_t bist:8;
250 uint32_t mfd:1;
251 uint32_t chf:7;
252 uint32_t lt:8;
253 uint32_t cls:8;
254 } s;
255 struct cvmx_pcieep_cfg003_s cn52xx;
256 struct cvmx_pcieep_cfg003_s cn52xxp1;
257 struct cvmx_pcieep_cfg003_s cn56xx;
258 struct cvmx_pcieep_cfg003_s cn56xxp1;
259};
260
261union cvmx_pcieep_cfg004 {
262 uint32_t u32;
263 struct cvmx_pcieep_cfg004_s {
264 uint32_t lbab:18;
265 uint32_t reserved_4_13:10;
266 uint32_t pf:1;
267 uint32_t typ:2;
268 uint32_t mspc:1;
269 } s;
270 struct cvmx_pcieep_cfg004_s cn52xx;
271 struct cvmx_pcieep_cfg004_s cn52xxp1;
272 struct cvmx_pcieep_cfg004_s cn56xx;
273 struct cvmx_pcieep_cfg004_s cn56xxp1;
274};
275
276union cvmx_pcieep_cfg004_mask {
277 uint32_t u32;
278 struct cvmx_pcieep_cfg004_mask_s {
279 uint32_t lmask:31;
280 uint32_t enb:1;
281 } s;
282 struct cvmx_pcieep_cfg004_mask_s cn52xx;
283 struct cvmx_pcieep_cfg004_mask_s cn52xxp1;
284 struct cvmx_pcieep_cfg004_mask_s cn56xx;
285 struct cvmx_pcieep_cfg004_mask_s cn56xxp1;
286};
287
288union cvmx_pcieep_cfg005 {
289 uint32_t u32;
290 struct cvmx_pcieep_cfg005_s {
291 uint32_t ubab:32;
292 } s;
293 struct cvmx_pcieep_cfg005_s cn52xx;
294 struct cvmx_pcieep_cfg005_s cn52xxp1;
295 struct cvmx_pcieep_cfg005_s cn56xx;
296 struct cvmx_pcieep_cfg005_s cn56xxp1;
297};
298
299union cvmx_pcieep_cfg005_mask {
300 uint32_t u32;
301 struct cvmx_pcieep_cfg005_mask_s {
302 uint32_t umask:32;
303 } s;
304 struct cvmx_pcieep_cfg005_mask_s cn52xx;
305 struct cvmx_pcieep_cfg005_mask_s cn52xxp1;
306 struct cvmx_pcieep_cfg005_mask_s cn56xx;
307 struct cvmx_pcieep_cfg005_mask_s cn56xxp1;
308};
309
310union cvmx_pcieep_cfg006 {
311 uint32_t u32;
312 struct cvmx_pcieep_cfg006_s {
313 uint32_t lbab:6;
314 uint32_t reserved_4_25:22;
315 uint32_t pf:1;
316 uint32_t typ:2;
317 uint32_t mspc:1;
318 } s;
319 struct cvmx_pcieep_cfg006_s cn52xx;
320 struct cvmx_pcieep_cfg006_s cn52xxp1;
321 struct cvmx_pcieep_cfg006_s cn56xx;
322 struct cvmx_pcieep_cfg006_s cn56xxp1;
323};
324
325union cvmx_pcieep_cfg006_mask {
326 uint32_t u32;
327 struct cvmx_pcieep_cfg006_mask_s {
328 uint32_t lmask:31;
329 uint32_t enb:1;
330 } s;
331 struct cvmx_pcieep_cfg006_mask_s cn52xx;
332 struct cvmx_pcieep_cfg006_mask_s cn52xxp1;
333 struct cvmx_pcieep_cfg006_mask_s cn56xx;
334 struct cvmx_pcieep_cfg006_mask_s cn56xxp1;
335};
336
337union cvmx_pcieep_cfg007 {
338 uint32_t u32;
339 struct cvmx_pcieep_cfg007_s {
340 uint32_t ubab:32;
341 } s;
342 struct cvmx_pcieep_cfg007_s cn52xx;
343 struct cvmx_pcieep_cfg007_s cn52xxp1;
344 struct cvmx_pcieep_cfg007_s cn56xx;
345 struct cvmx_pcieep_cfg007_s cn56xxp1;
346};
347
348union cvmx_pcieep_cfg007_mask {
349 uint32_t u32;
350 struct cvmx_pcieep_cfg007_mask_s {
351 uint32_t umask:32;
352 } s;
353 struct cvmx_pcieep_cfg007_mask_s cn52xx;
354 struct cvmx_pcieep_cfg007_mask_s cn52xxp1;
355 struct cvmx_pcieep_cfg007_mask_s cn56xx;
356 struct cvmx_pcieep_cfg007_mask_s cn56xxp1;
357};
358
359union cvmx_pcieep_cfg008 {
360 uint32_t u32;
361 struct cvmx_pcieep_cfg008_s {
362 uint32_t reserved_4_31:28;
363 uint32_t pf:1;
364 uint32_t typ:2;
365 uint32_t mspc:1;
366 } s;
367 struct cvmx_pcieep_cfg008_s cn52xx;
368 struct cvmx_pcieep_cfg008_s cn52xxp1;
369 struct cvmx_pcieep_cfg008_s cn56xx;
370 struct cvmx_pcieep_cfg008_s cn56xxp1;
371};
372
373union cvmx_pcieep_cfg008_mask {
374 uint32_t u32;
375 struct cvmx_pcieep_cfg008_mask_s {
376 uint32_t lmask:31;
377 uint32_t enb:1;
378 } s;
379 struct cvmx_pcieep_cfg008_mask_s cn52xx;
380 struct cvmx_pcieep_cfg008_mask_s cn52xxp1;
381 struct cvmx_pcieep_cfg008_mask_s cn56xx;
382 struct cvmx_pcieep_cfg008_mask_s cn56xxp1;
383};
384
385union cvmx_pcieep_cfg009 {
386 uint32_t u32;
387 struct cvmx_pcieep_cfg009_s {
388 uint32_t ubab:25;
389 uint32_t reserved_0_6:7;
390 } s;
391 struct cvmx_pcieep_cfg009_s cn52xx;
392 struct cvmx_pcieep_cfg009_s cn52xxp1;
393 struct cvmx_pcieep_cfg009_s cn56xx;
394 struct cvmx_pcieep_cfg009_s cn56xxp1;
395};
396
397union cvmx_pcieep_cfg009_mask {
398 uint32_t u32;
399 struct cvmx_pcieep_cfg009_mask_s {
400 uint32_t umask:32;
401 } s;
402 struct cvmx_pcieep_cfg009_mask_s cn52xx;
403 struct cvmx_pcieep_cfg009_mask_s cn52xxp1;
404 struct cvmx_pcieep_cfg009_mask_s cn56xx;
405 struct cvmx_pcieep_cfg009_mask_s cn56xxp1;
406};
407
408union cvmx_pcieep_cfg010 {
409 uint32_t u32;
410 struct cvmx_pcieep_cfg010_s {
411 uint32_t cisp:32;
412 } s;
413 struct cvmx_pcieep_cfg010_s cn52xx;
414 struct cvmx_pcieep_cfg010_s cn52xxp1;
415 struct cvmx_pcieep_cfg010_s cn56xx;
416 struct cvmx_pcieep_cfg010_s cn56xxp1;
417};
418
419union cvmx_pcieep_cfg011 {
420 uint32_t u32;
421 struct cvmx_pcieep_cfg011_s {
422 uint32_t ssid:16;
423 uint32_t ssvid:16;
424 } s;
425 struct cvmx_pcieep_cfg011_s cn52xx;
426 struct cvmx_pcieep_cfg011_s cn52xxp1;
427 struct cvmx_pcieep_cfg011_s cn56xx;
428 struct cvmx_pcieep_cfg011_s cn56xxp1;
429};
430
431union cvmx_pcieep_cfg012 {
432 uint32_t u32;
433 struct cvmx_pcieep_cfg012_s {
434 uint32_t eraddr:16;
435 uint32_t reserved_1_15:15;
436 uint32_t er_en:1;
437 } s;
438 struct cvmx_pcieep_cfg012_s cn52xx;
439 struct cvmx_pcieep_cfg012_s cn52xxp1;
440 struct cvmx_pcieep_cfg012_s cn56xx;
441 struct cvmx_pcieep_cfg012_s cn56xxp1;
442};
443
444union cvmx_pcieep_cfg012_mask {
445 uint32_t u32;
446 struct cvmx_pcieep_cfg012_mask_s {
447 uint32_t mask:31;
448 uint32_t enb:1;
449 } s;
450 struct cvmx_pcieep_cfg012_mask_s cn52xx;
451 struct cvmx_pcieep_cfg012_mask_s cn52xxp1;
452 struct cvmx_pcieep_cfg012_mask_s cn56xx;
453 struct cvmx_pcieep_cfg012_mask_s cn56xxp1;
454};
455
456union cvmx_pcieep_cfg013 {
457 uint32_t u32;
458 struct cvmx_pcieep_cfg013_s {
459 uint32_t reserved_8_31:24;
460 uint32_t cp:8;
461 } s;
462 struct cvmx_pcieep_cfg013_s cn52xx;
463 struct cvmx_pcieep_cfg013_s cn52xxp1;
464 struct cvmx_pcieep_cfg013_s cn56xx;
465 struct cvmx_pcieep_cfg013_s cn56xxp1;
466};
467
468union cvmx_pcieep_cfg015 {
469 uint32_t u32;
470 struct cvmx_pcieep_cfg015_s {
471 uint32_t ml:8;
472 uint32_t mg:8;
473 uint32_t inta:8;
474 uint32_t il:8;
475 } s;
476 struct cvmx_pcieep_cfg015_s cn52xx;
477 struct cvmx_pcieep_cfg015_s cn52xxp1;
478 struct cvmx_pcieep_cfg015_s cn56xx;
479 struct cvmx_pcieep_cfg015_s cn56xxp1;
480};
481
482union cvmx_pcieep_cfg016 {
483 uint32_t u32;
484 struct cvmx_pcieep_cfg016_s {
485 uint32_t pmes:5;
486 uint32_t d2s:1;
487 uint32_t d1s:1;
488 uint32_t auxc:3;
489 uint32_t dsi:1;
490 uint32_t reserved_20_20:1;
491 uint32_t pme_clock:1;
492 uint32_t pmsv:3;
493 uint32_t ncp:8;
494 uint32_t pmcid:8;
495 } s;
496 struct cvmx_pcieep_cfg016_s cn52xx;
497 struct cvmx_pcieep_cfg016_s cn52xxp1;
498 struct cvmx_pcieep_cfg016_s cn56xx;
499 struct cvmx_pcieep_cfg016_s cn56xxp1;
500};
501
502union cvmx_pcieep_cfg017 {
503 uint32_t u32;
504 struct cvmx_pcieep_cfg017_s {
505 uint32_t pmdia:8;
506 uint32_t bpccee:1;
507 uint32_t bd3h:1;
508 uint32_t reserved_16_21:6;
509 uint32_t pmess:1;
510 uint32_t pmedsia:2;
511 uint32_t pmds:4;
512 uint32_t pmeens:1;
513 uint32_t reserved_4_7:4;
514 uint32_t nsr:1;
515 uint32_t reserved_2_2:1;
516 uint32_t ps:2;
517 } s;
518 struct cvmx_pcieep_cfg017_s cn52xx;
519 struct cvmx_pcieep_cfg017_s cn52xxp1;
520 struct cvmx_pcieep_cfg017_s cn56xx;
521 struct cvmx_pcieep_cfg017_s cn56xxp1;
522};
523
524union cvmx_pcieep_cfg020 {
525 uint32_t u32;
526 struct cvmx_pcieep_cfg020_s {
527 uint32_t reserved_24_31:8;
528 uint32_t m64:1;
529 uint32_t mme:3;
530 uint32_t mmc:3;
531 uint32_t msien:1;
532 uint32_t ncp:8;
533 uint32_t msicid:8;
534 } s;
535 struct cvmx_pcieep_cfg020_s cn52xx;
536 struct cvmx_pcieep_cfg020_s cn52xxp1;
537 struct cvmx_pcieep_cfg020_s cn56xx;
538 struct cvmx_pcieep_cfg020_s cn56xxp1;
539};
540
541union cvmx_pcieep_cfg021 {
542 uint32_t u32;
543 struct cvmx_pcieep_cfg021_s {
544 uint32_t lmsi:30;
545 uint32_t reserved_0_1:2;
546 } s;
547 struct cvmx_pcieep_cfg021_s cn52xx;
548 struct cvmx_pcieep_cfg021_s cn52xxp1;
549 struct cvmx_pcieep_cfg021_s cn56xx;
550 struct cvmx_pcieep_cfg021_s cn56xxp1;
551};
552
553union cvmx_pcieep_cfg022 {
554 uint32_t u32;
555 struct cvmx_pcieep_cfg022_s {
556 uint32_t umsi:32;
557 } s;
558 struct cvmx_pcieep_cfg022_s cn52xx;
559 struct cvmx_pcieep_cfg022_s cn52xxp1;
560 struct cvmx_pcieep_cfg022_s cn56xx;
561 struct cvmx_pcieep_cfg022_s cn56xxp1;
562};
563
564union cvmx_pcieep_cfg023 {
565 uint32_t u32;
566 struct cvmx_pcieep_cfg023_s {
567 uint32_t reserved_16_31:16;
568 uint32_t msimd:16;
569 } s;
570 struct cvmx_pcieep_cfg023_s cn52xx;
571 struct cvmx_pcieep_cfg023_s cn52xxp1;
572 struct cvmx_pcieep_cfg023_s cn56xx;
573 struct cvmx_pcieep_cfg023_s cn56xxp1;
574};
575
576union cvmx_pcieep_cfg028 {
577 uint32_t u32;
578 struct cvmx_pcieep_cfg028_s {
579 uint32_t reserved_30_31:2;
580 uint32_t imn:5;
581 uint32_t si:1;
582 uint32_t dpt:4;
583 uint32_t pciecv:4;
584 uint32_t ncp:8;
585 uint32_t pcieid:8;
586 } s;
587 struct cvmx_pcieep_cfg028_s cn52xx;
588 struct cvmx_pcieep_cfg028_s cn52xxp1;
589 struct cvmx_pcieep_cfg028_s cn56xx;
590 struct cvmx_pcieep_cfg028_s cn56xxp1;
591};
592
593union cvmx_pcieep_cfg029 {
594 uint32_t u32;
595 struct cvmx_pcieep_cfg029_s {
596 uint32_t reserved_28_31:4;
597 uint32_t cspls:2;
598 uint32_t csplv:8;
599 uint32_t reserved_16_17:2;
600 uint32_t rber:1;
601 uint32_t reserved_12_14:3;
602 uint32_t el1al:3;
603 uint32_t el0al:3;
604 uint32_t etfs:1;
605 uint32_t pfs:2;
606 uint32_t mpss:3;
607 } s;
608 struct cvmx_pcieep_cfg029_s cn52xx;
609 struct cvmx_pcieep_cfg029_s cn52xxp1;
610 struct cvmx_pcieep_cfg029_s cn56xx;
611 struct cvmx_pcieep_cfg029_s cn56xxp1;
612};
613
614union cvmx_pcieep_cfg030 {
615 uint32_t u32;
616 struct cvmx_pcieep_cfg030_s {
617 uint32_t reserved_22_31:10;
618 uint32_t tp:1;
619 uint32_t ap_d:1;
620 uint32_t ur_d:1;
621 uint32_t fe_d:1;
622 uint32_t nfe_d:1;
623 uint32_t ce_d:1;
624 uint32_t reserved_15_15:1;
625 uint32_t mrrs:3;
626 uint32_t ns_en:1;
627 uint32_t ap_en:1;
628 uint32_t pf_en:1;
629 uint32_t etf_en:1;
630 uint32_t mps:3;
631 uint32_t ro_en:1;
632 uint32_t ur_en:1;
633 uint32_t fe_en:1;
634 uint32_t nfe_en:1;
635 uint32_t ce_en:1;
636 } s;
637 struct cvmx_pcieep_cfg030_s cn52xx;
638 struct cvmx_pcieep_cfg030_s cn52xxp1;
639 struct cvmx_pcieep_cfg030_s cn56xx;
640 struct cvmx_pcieep_cfg030_s cn56xxp1;
641};
642
643union cvmx_pcieep_cfg031 {
644 uint32_t u32;
645 struct cvmx_pcieep_cfg031_s {
646 uint32_t pnum:8;
647 uint32_t reserved_22_23:2;
648 uint32_t lbnc:1;
649 uint32_t dllarc:1;
650 uint32_t sderc:1;
651 uint32_t cpm:1;
652 uint32_t l1el:3;
653 uint32_t l0el:3;
654 uint32_t aslpms:2;
655 uint32_t mlw:6;
656 uint32_t mls:4;
657 } s;
658 struct cvmx_pcieep_cfg031_s cn52xx;
659 struct cvmx_pcieep_cfg031_s cn52xxp1;
660 struct cvmx_pcieep_cfg031_s cn56xx;
661 struct cvmx_pcieep_cfg031_s cn56xxp1;
662};
663
664union cvmx_pcieep_cfg032 {
665 uint32_t u32;
666 struct cvmx_pcieep_cfg032_s {
667 uint32_t reserved_30_31:2;
668 uint32_t dlla:1;
669 uint32_t scc:1;
670 uint32_t lt:1;
671 uint32_t reserved_26_26:1;
672 uint32_t nlw:6;
673 uint32_t ls:4;
674 uint32_t reserved_10_15:6;
675 uint32_t hawd:1;
676 uint32_t ecpm:1;
677 uint32_t es:1;
678 uint32_t ccc:1;
679 uint32_t rl:1;
680 uint32_t ld:1;
681 uint32_t rcb:1;
682 uint32_t reserved_2_2:1;
683 uint32_t aslpc:2;
684 } s;
685 struct cvmx_pcieep_cfg032_s cn52xx;
686 struct cvmx_pcieep_cfg032_s cn52xxp1;
687 struct cvmx_pcieep_cfg032_s cn56xx;
688 struct cvmx_pcieep_cfg032_s cn56xxp1;
689};
690
691union cvmx_pcieep_cfg033 {
692 uint32_t u32;
693 struct cvmx_pcieep_cfg033_s {
694 uint32_t ps_num:13;
695 uint32_t nccs:1;
696 uint32_t emip:1;
697 uint32_t sp_ls:2;
698 uint32_t sp_lv:8;
699 uint32_t hp_c:1;
700 uint32_t hp_s:1;
701 uint32_t pip:1;
702 uint32_t aip:1;
703 uint32_t mrlsp:1;
704 uint32_t pcp:1;
705 uint32_t abp:1;
706 } s;
707 struct cvmx_pcieep_cfg033_s cn52xx;
708 struct cvmx_pcieep_cfg033_s cn52xxp1;
709 struct cvmx_pcieep_cfg033_s cn56xx;
710 struct cvmx_pcieep_cfg033_s cn56xxp1;
711};
712
713union cvmx_pcieep_cfg034 {
714 uint32_t u32;
715 struct cvmx_pcieep_cfg034_s {
716 uint32_t reserved_25_31:7;
717 uint32_t dlls_c:1;
718 uint32_t emis:1;
719 uint32_t pds:1;
720 uint32_t mrlss:1;
721 uint32_t ccint_d:1;
722 uint32_t pd_c:1;
723 uint32_t mrls_c:1;
724 uint32_t pf_d:1;
725 uint32_t abp_d:1;
726 uint32_t reserved_13_15:3;
727 uint32_t dlls_en:1;
728 uint32_t emic:1;
729 uint32_t pcc:1;
730 uint32_t pic:2;
731 uint32_t aic:2;
732 uint32_t hpint_en:1;
733 uint32_t ccint_en:1;
734 uint32_t pd_en:1;
735 uint32_t mrls_en:1;
736 uint32_t pf_en:1;
737 uint32_t abp_en:1;
738 } s;
739 struct cvmx_pcieep_cfg034_s cn52xx;
740 struct cvmx_pcieep_cfg034_s cn52xxp1;
741 struct cvmx_pcieep_cfg034_s cn56xx;
742 struct cvmx_pcieep_cfg034_s cn56xxp1;
743};
744
745union cvmx_pcieep_cfg037 {
746 uint32_t u32;
747 struct cvmx_pcieep_cfg037_s {
748 uint32_t reserved_5_31:27;
749 uint32_t ctds:1;
750 uint32_t ctrs:4;
751 } s;
752 struct cvmx_pcieep_cfg037_s cn52xx;
753 struct cvmx_pcieep_cfg037_s cn52xxp1;
754 struct cvmx_pcieep_cfg037_s cn56xx;
755 struct cvmx_pcieep_cfg037_s cn56xxp1;
756};
757
758union cvmx_pcieep_cfg038 {
759 uint32_t u32;
760 struct cvmx_pcieep_cfg038_s {
761 uint32_t reserved_5_31:27;
762 uint32_t ctd:1;
763 uint32_t ctv:4;
764 } s;
765 struct cvmx_pcieep_cfg038_s cn52xx;
766 struct cvmx_pcieep_cfg038_s cn52xxp1;
767 struct cvmx_pcieep_cfg038_s cn56xx;
768 struct cvmx_pcieep_cfg038_s cn56xxp1;
769};
770
771union cvmx_pcieep_cfg039 {
772 uint32_t u32;
773 struct cvmx_pcieep_cfg039_s {
774 uint32_t reserved_0_31:32;
775 } s;
776 struct cvmx_pcieep_cfg039_s cn52xx;
777 struct cvmx_pcieep_cfg039_s cn52xxp1;
778 struct cvmx_pcieep_cfg039_s cn56xx;
779 struct cvmx_pcieep_cfg039_s cn56xxp1;
780};
781
782union cvmx_pcieep_cfg040 {
783 uint32_t u32;
784 struct cvmx_pcieep_cfg040_s {
785 uint32_t reserved_0_31:32;
786 } s;
787 struct cvmx_pcieep_cfg040_s cn52xx;
788 struct cvmx_pcieep_cfg040_s cn52xxp1;
789 struct cvmx_pcieep_cfg040_s cn56xx;
790 struct cvmx_pcieep_cfg040_s cn56xxp1;
791};
792
793union cvmx_pcieep_cfg041 {
794 uint32_t u32;
795 struct cvmx_pcieep_cfg041_s {
796 uint32_t reserved_0_31:32;
797 } s;
798 struct cvmx_pcieep_cfg041_s cn52xx;
799 struct cvmx_pcieep_cfg041_s cn52xxp1;
800 struct cvmx_pcieep_cfg041_s cn56xx;
801 struct cvmx_pcieep_cfg041_s cn56xxp1;
802};
803
804union cvmx_pcieep_cfg042 {
805 uint32_t u32;
806 struct cvmx_pcieep_cfg042_s {
807 uint32_t reserved_0_31:32;
808 } s;
809 struct cvmx_pcieep_cfg042_s cn52xx;
810 struct cvmx_pcieep_cfg042_s cn52xxp1;
811 struct cvmx_pcieep_cfg042_s cn56xx;
812 struct cvmx_pcieep_cfg042_s cn56xxp1;
813};
814
815union cvmx_pcieep_cfg064 {
816 uint32_t u32;
817 struct cvmx_pcieep_cfg064_s {
818 uint32_t nco:12;
819 uint32_t cv:4;
820 uint32_t pcieec:16;
821 } s;
822 struct cvmx_pcieep_cfg064_s cn52xx;
823 struct cvmx_pcieep_cfg064_s cn52xxp1;
824 struct cvmx_pcieep_cfg064_s cn56xx;
825 struct cvmx_pcieep_cfg064_s cn56xxp1;
826};
827
828union cvmx_pcieep_cfg065 {
829 uint32_t u32;
830 struct cvmx_pcieep_cfg065_s {
831 uint32_t reserved_21_31:11;
832 uint32_t ures:1;
833 uint32_t ecrces:1;
834 uint32_t mtlps:1;
835 uint32_t ros:1;
836 uint32_t ucs:1;
837 uint32_t cas:1;
838 uint32_t cts:1;
839 uint32_t fcpes:1;
840 uint32_t ptlps:1;
841 uint32_t reserved_6_11:6;
842 uint32_t sdes:1;
843 uint32_t dlpes:1;
844 uint32_t reserved_0_3:4;
845 } s;
846 struct cvmx_pcieep_cfg065_s cn52xx;
847 struct cvmx_pcieep_cfg065_s cn52xxp1;
848 struct cvmx_pcieep_cfg065_s cn56xx;
849 struct cvmx_pcieep_cfg065_s cn56xxp1;
850};
851
852union cvmx_pcieep_cfg066 {
853 uint32_t u32;
854 struct cvmx_pcieep_cfg066_s {
855 uint32_t reserved_21_31:11;
856 uint32_t urem:1;
857 uint32_t ecrcem:1;
858 uint32_t mtlpm:1;
859 uint32_t rom:1;
860 uint32_t ucm:1;
861 uint32_t cam:1;
862 uint32_t ctm:1;
863 uint32_t fcpem:1;
864 uint32_t ptlpm:1;
865 uint32_t reserved_6_11:6;
866 uint32_t sdem:1;
867 uint32_t dlpem:1;
868 uint32_t reserved_0_3:4;
869 } s;
870 struct cvmx_pcieep_cfg066_s cn52xx;
871 struct cvmx_pcieep_cfg066_s cn52xxp1;
872 struct cvmx_pcieep_cfg066_s cn56xx;
873 struct cvmx_pcieep_cfg066_s cn56xxp1;
874};
875
876union cvmx_pcieep_cfg067 {
877 uint32_t u32;
878 struct cvmx_pcieep_cfg067_s {
879 uint32_t reserved_21_31:11;
880 uint32_t ures:1;
881 uint32_t ecrces:1;
882 uint32_t mtlps:1;
883 uint32_t ros:1;
884 uint32_t ucs:1;
885 uint32_t cas:1;
886 uint32_t cts:1;
887 uint32_t fcpes:1;
888 uint32_t ptlps:1;
889 uint32_t reserved_6_11:6;
890 uint32_t sdes:1;
891 uint32_t dlpes:1;
892 uint32_t reserved_0_3:4;
893 } s;
894 struct cvmx_pcieep_cfg067_s cn52xx;
895 struct cvmx_pcieep_cfg067_s cn52xxp1;
896 struct cvmx_pcieep_cfg067_s cn56xx;
897 struct cvmx_pcieep_cfg067_s cn56xxp1;
898};
899
900union cvmx_pcieep_cfg068 {
901 uint32_t u32;
902 struct cvmx_pcieep_cfg068_s {
903 uint32_t reserved_14_31:18;
904 uint32_t anfes:1;
905 uint32_t rtts:1;
906 uint32_t reserved_9_11:3;
907 uint32_t rnrs:1;
908 uint32_t bdllps:1;
909 uint32_t btlps:1;
910 uint32_t reserved_1_5:5;
911 uint32_t res:1;
912 } s;
913 struct cvmx_pcieep_cfg068_s cn52xx;
914 struct cvmx_pcieep_cfg068_s cn52xxp1;
915 struct cvmx_pcieep_cfg068_s cn56xx;
916 struct cvmx_pcieep_cfg068_s cn56xxp1;
917};
918
919union cvmx_pcieep_cfg069 {
920 uint32_t u32;
921 struct cvmx_pcieep_cfg069_s {
922 uint32_t reserved_14_31:18;
923 uint32_t anfem:1;
924 uint32_t rttm:1;
925 uint32_t reserved_9_11:3;
926 uint32_t rnrm:1;
927 uint32_t bdllpm:1;
928 uint32_t btlpm:1;
929 uint32_t reserved_1_5:5;
930 uint32_t rem:1;
931 } s;
932 struct cvmx_pcieep_cfg069_s cn52xx;
933 struct cvmx_pcieep_cfg069_s cn52xxp1;
934 struct cvmx_pcieep_cfg069_s cn56xx;
935 struct cvmx_pcieep_cfg069_s cn56xxp1;
936};
937
938union cvmx_pcieep_cfg070 {
939 uint32_t u32;
940 struct cvmx_pcieep_cfg070_s {
941 uint32_t reserved_9_31:23;
942 uint32_t ce:1;
943 uint32_t cc:1;
944 uint32_t ge:1;
945 uint32_t gc:1;
946 uint32_t fep:5;
947 } s;
948 struct cvmx_pcieep_cfg070_s cn52xx;
949 struct cvmx_pcieep_cfg070_s cn52xxp1;
950 struct cvmx_pcieep_cfg070_s cn56xx;
951 struct cvmx_pcieep_cfg070_s cn56xxp1;
952};
953
954union cvmx_pcieep_cfg071 {
955 uint32_t u32;
956 struct cvmx_pcieep_cfg071_s {
957 uint32_t dword1:32;
958 } s;
959 struct cvmx_pcieep_cfg071_s cn52xx;
960 struct cvmx_pcieep_cfg071_s cn52xxp1;
961 struct cvmx_pcieep_cfg071_s cn56xx;
962 struct cvmx_pcieep_cfg071_s cn56xxp1;
963};
964
965union cvmx_pcieep_cfg072 {
966 uint32_t u32;
967 struct cvmx_pcieep_cfg072_s {
968 uint32_t dword2:32;
969 } s;
970 struct cvmx_pcieep_cfg072_s cn52xx;
971 struct cvmx_pcieep_cfg072_s cn52xxp1;
972 struct cvmx_pcieep_cfg072_s cn56xx;
973 struct cvmx_pcieep_cfg072_s cn56xxp1;
974};
975
976union cvmx_pcieep_cfg073 {
977 uint32_t u32;
978 struct cvmx_pcieep_cfg073_s {
979 uint32_t dword3:32;
980 } s;
981 struct cvmx_pcieep_cfg073_s cn52xx;
982 struct cvmx_pcieep_cfg073_s cn52xxp1;
983 struct cvmx_pcieep_cfg073_s cn56xx;
984 struct cvmx_pcieep_cfg073_s cn56xxp1;
985};
986
987union cvmx_pcieep_cfg074 {
988 uint32_t u32;
989 struct cvmx_pcieep_cfg074_s {
990 uint32_t dword4:32;
991 } s;
992 struct cvmx_pcieep_cfg074_s cn52xx;
993 struct cvmx_pcieep_cfg074_s cn52xxp1;
994 struct cvmx_pcieep_cfg074_s cn56xx;
995 struct cvmx_pcieep_cfg074_s cn56xxp1;
996};
997
998union cvmx_pcieep_cfg448 {
999 uint32_t u32;
1000 struct cvmx_pcieep_cfg448_s {
1001 uint32_t rtl:16;
1002 uint32_t rtltl:16;
1003 } s;
1004 struct cvmx_pcieep_cfg448_s cn52xx;
1005 struct cvmx_pcieep_cfg448_s cn52xxp1;
1006 struct cvmx_pcieep_cfg448_s cn56xx;
1007 struct cvmx_pcieep_cfg448_s cn56xxp1;
1008};
1009
1010union cvmx_pcieep_cfg449 {
1011 uint32_t u32;
1012 struct cvmx_pcieep_cfg449_s {
1013 uint32_t omr:32;
1014 } s;
1015 struct cvmx_pcieep_cfg449_s cn52xx;
1016 struct cvmx_pcieep_cfg449_s cn52xxp1;
1017 struct cvmx_pcieep_cfg449_s cn56xx;
1018 struct cvmx_pcieep_cfg449_s cn56xxp1;
1019};
1020
1021union cvmx_pcieep_cfg450 {
1022 uint32_t u32;
1023 struct cvmx_pcieep_cfg450_s {
1024 uint32_t lpec:8;
1025 uint32_t reserved_22_23:2;
1026 uint32_t link_state:6;
1027 uint32_t force_link:1;
1028 uint32_t reserved_8_14:7;
1029 uint32_t link_num:8;
1030 } s;
1031 struct cvmx_pcieep_cfg450_s cn52xx;
1032 struct cvmx_pcieep_cfg450_s cn52xxp1;
1033 struct cvmx_pcieep_cfg450_s cn56xx;
1034 struct cvmx_pcieep_cfg450_s cn56xxp1;
1035};
1036
1037union cvmx_pcieep_cfg451 {
1038 uint32_t u32;
1039 struct cvmx_pcieep_cfg451_s {
1040 uint32_t reserved_30_31:2;
1041 uint32_t l1el:3;
1042 uint32_t l0el:3;
1043 uint32_t n_fts_cc:8;
1044 uint32_t n_fts:8;
1045 uint32_t ack_freq:8;
1046 } s;
1047 struct cvmx_pcieep_cfg451_s cn52xx;
1048 struct cvmx_pcieep_cfg451_s cn52xxp1;
1049 struct cvmx_pcieep_cfg451_s cn56xx;
1050 struct cvmx_pcieep_cfg451_s cn56xxp1;
1051};
1052
1053union cvmx_pcieep_cfg452 {
1054 uint32_t u32;
1055 struct cvmx_pcieep_cfg452_s {
1056 uint32_t reserved_26_31:6;
1057 uint32_t eccrc:1;
1058 uint32_t reserved_22_24:3;
1059 uint32_t lme:6;
1060 uint32_t reserved_8_15:8;
1061 uint32_t flm:1;
1062 uint32_t reserved_6_6:1;
1063 uint32_t dllle:1;
1064 uint32_t reserved_4_4:1;
1065 uint32_t ra:1;
1066 uint32_t le:1;
1067 uint32_t sd:1;
1068 uint32_t omr:1;
1069 } s;
1070 struct cvmx_pcieep_cfg452_s cn52xx;
1071 struct cvmx_pcieep_cfg452_s cn52xxp1;
1072 struct cvmx_pcieep_cfg452_s cn56xx;
1073 struct cvmx_pcieep_cfg452_s cn56xxp1;
1074};
1075
1076union cvmx_pcieep_cfg453 {
1077 uint32_t u32;
1078 struct cvmx_pcieep_cfg453_s {
1079 uint32_t dlld:1;
1080 uint32_t reserved_26_30:5;
1081 uint32_t ack_nak:1;
1082 uint32_t fcd:1;
1083 uint32_t ilst:24;
1084 } s;
1085 struct cvmx_pcieep_cfg453_s cn52xx;
1086 struct cvmx_pcieep_cfg453_s cn52xxp1;
1087 struct cvmx_pcieep_cfg453_s cn56xx;
1088 struct cvmx_pcieep_cfg453_s cn56xxp1;
1089};
1090
1091union cvmx_pcieep_cfg454 {
1092 uint32_t u32;
1093 struct cvmx_pcieep_cfg454_s {
1094 uint32_t reserved_29_31:3;
1095 uint32_t tmfcwt:5;
1096 uint32_t tmanlt:5;
1097 uint32_t tmrt:5;
1098 uint32_t reserved_11_13:3;
1099 uint32_t nskps:3;
1100 uint32_t reserved_4_7:4;
1101 uint32_t ntss:4;
1102 } s;
1103 struct cvmx_pcieep_cfg454_s cn52xx;
1104 struct cvmx_pcieep_cfg454_s cn52xxp1;
1105 struct cvmx_pcieep_cfg454_s cn56xx;
1106 struct cvmx_pcieep_cfg454_s cn56xxp1;
1107};
1108
1109union cvmx_pcieep_cfg455 {
1110 uint32_t u32;
1111 struct cvmx_pcieep_cfg455_s {
1112 uint32_t m_cfg0_filt:1;
1113 uint32_t m_io_filt:1;
1114 uint32_t msg_ctrl:1;
1115 uint32_t m_cpl_ecrc_filt:1;
1116 uint32_t m_ecrc_filt:1;
1117 uint32_t m_cpl_len_err:1;
1118 uint32_t m_cpl_attr_err:1;
1119 uint32_t m_cpl_tc_err:1;
1120 uint32_t m_cpl_fun_err:1;
1121 uint32_t m_cpl_rid_err:1;
1122 uint32_t m_cpl_tag_err:1;
1123 uint32_t m_lk_filt:1;
1124 uint32_t m_cfg1_filt:1;
1125 uint32_t m_bar_match:1;
1126 uint32_t m_pois_filt:1;
1127 uint32_t m_fun:1;
1128 uint32_t dfcwt:1;
1129 uint32_t reserved_11_14:4;
1130 uint32_t skpiv:11;
1131 } s;
1132 struct cvmx_pcieep_cfg455_s cn52xx;
1133 struct cvmx_pcieep_cfg455_s cn52xxp1;
1134 struct cvmx_pcieep_cfg455_s cn56xx;
1135 struct cvmx_pcieep_cfg455_s cn56xxp1;
1136};
1137
1138union cvmx_pcieep_cfg456 {
1139 uint32_t u32;
1140 struct cvmx_pcieep_cfg456_s {
1141 uint32_t reserved_2_31:30;
1142 uint32_t m_vend1_drp:1;
1143 uint32_t m_vend0_drp:1;
1144 } s;
1145 struct cvmx_pcieep_cfg456_s cn52xx;
1146 struct cvmx_pcieep_cfg456_s cn52xxp1;
1147 struct cvmx_pcieep_cfg456_s cn56xx;
1148 struct cvmx_pcieep_cfg456_s cn56xxp1;
1149};
1150
1151union cvmx_pcieep_cfg458 {
1152 uint32_t u32;
1153 struct cvmx_pcieep_cfg458_s {
1154 uint32_t dbg_info_l32:32;
1155 } s;
1156 struct cvmx_pcieep_cfg458_s cn52xx;
1157 struct cvmx_pcieep_cfg458_s cn52xxp1;
1158 struct cvmx_pcieep_cfg458_s cn56xx;
1159 struct cvmx_pcieep_cfg458_s cn56xxp1;
1160};
1161
1162union cvmx_pcieep_cfg459 {
1163 uint32_t u32;
1164 struct cvmx_pcieep_cfg459_s {
1165 uint32_t dbg_info_u32:32;
1166 } s;
1167 struct cvmx_pcieep_cfg459_s cn52xx;
1168 struct cvmx_pcieep_cfg459_s cn52xxp1;
1169 struct cvmx_pcieep_cfg459_s cn56xx;
1170 struct cvmx_pcieep_cfg459_s cn56xxp1;
1171};
1172
1173union cvmx_pcieep_cfg460 {
1174 uint32_t u32;
1175 struct cvmx_pcieep_cfg460_s {
1176 uint32_t reserved_20_31:12;
1177 uint32_t tphfcc:8;
1178 uint32_t tpdfcc:12;
1179 } s;
1180 struct cvmx_pcieep_cfg460_s cn52xx;
1181 struct cvmx_pcieep_cfg460_s cn52xxp1;
1182 struct cvmx_pcieep_cfg460_s cn56xx;
1183 struct cvmx_pcieep_cfg460_s cn56xxp1;
1184};
1185
1186union cvmx_pcieep_cfg461 {
1187 uint32_t u32;
1188 struct cvmx_pcieep_cfg461_s {
1189 uint32_t reserved_20_31:12;
1190 uint32_t tchfcc:8;
1191 uint32_t tcdfcc:12;
1192 } s;
1193 struct cvmx_pcieep_cfg461_s cn52xx;
1194 struct cvmx_pcieep_cfg461_s cn52xxp1;
1195 struct cvmx_pcieep_cfg461_s cn56xx;
1196 struct cvmx_pcieep_cfg461_s cn56xxp1;
1197};
1198
1199union cvmx_pcieep_cfg462 {
1200 uint32_t u32;
1201 struct cvmx_pcieep_cfg462_s {
1202 uint32_t reserved_20_31:12;
1203 uint32_t tchfcc:8;
1204 uint32_t tcdfcc:12;
1205 } s;
1206 struct cvmx_pcieep_cfg462_s cn52xx;
1207 struct cvmx_pcieep_cfg462_s cn52xxp1;
1208 struct cvmx_pcieep_cfg462_s cn56xx;
1209 struct cvmx_pcieep_cfg462_s cn56xxp1;
1210};
1211
1212union cvmx_pcieep_cfg463 {
1213 uint32_t u32;
1214 struct cvmx_pcieep_cfg463_s {
1215 uint32_t reserved_3_31:29;
1216 uint32_t rqne:1;
1217 uint32_t trbne:1;
1218 uint32_t rtlpfccnr:1;
1219 } s;
1220 struct cvmx_pcieep_cfg463_s cn52xx;
1221 struct cvmx_pcieep_cfg463_s cn52xxp1;
1222 struct cvmx_pcieep_cfg463_s cn56xx;
1223 struct cvmx_pcieep_cfg463_s cn56xxp1;
1224};
1225
1226union cvmx_pcieep_cfg464 {
1227 uint32_t u32;
1228 struct cvmx_pcieep_cfg464_s {
1229 uint32_t wrr_vc3:8;
1230 uint32_t wrr_vc2:8;
1231 uint32_t wrr_vc1:8;
1232 uint32_t wrr_vc0:8;
1233 } s;
1234 struct cvmx_pcieep_cfg464_s cn52xx;
1235 struct cvmx_pcieep_cfg464_s cn52xxp1;
1236 struct cvmx_pcieep_cfg464_s cn56xx;
1237 struct cvmx_pcieep_cfg464_s cn56xxp1;
1238};
1239
1240union cvmx_pcieep_cfg465 {
1241 uint32_t u32;
1242 struct cvmx_pcieep_cfg465_s {
1243 uint32_t wrr_vc7:8;
1244 uint32_t wrr_vc6:8;
1245 uint32_t wrr_vc5:8;
1246 uint32_t wrr_vc4:8;
1247 } s;
1248 struct cvmx_pcieep_cfg465_s cn52xx;
1249 struct cvmx_pcieep_cfg465_s cn52xxp1;
1250 struct cvmx_pcieep_cfg465_s cn56xx;
1251 struct cvmx_pcieep_cfg465_s cn56xxp1;
1252};
1253
1254union cvmx_pcieep_cfg466 {
1255 uint32_t u32;
1256 struct cvmx_pcieep_cfg466_s {
1257 uint32_t rx_queue_order:1;
1258 uint32_t type_ordering:1;
1259 uint32_t reserved_24_29:6;
1260 uint32_t queue_mode:3;
1261 uint32_t reserved_20_20:1;
1262 uint32_t header_credits:8;
1263 uint32_t data_credits:12;
1264 } s;
1265 struct cvmx_pcieep_cfg466_s cn52xx;
1266 struct cvmx_pcieep_cfg466_s cn52xxp1;
1267 struct cvmx_pcieep_cfg466_s cn56xx;
1268 struct cvmx_pcieep_cfg466_s cn56xxp1;
1269};
1270
1271union cvmx_pcieep_cfg467 {
1272 uint32_t u32;
1273 struct cvmx_pcieep_cfg467_s {
1274 uint32_t reserved_24_31:8;
1275 uint32_t queue_mode:3;
1276 uint32_t reserved_20_20:1;
1277 uint32_t header_credits:8;
1278 uint32_t data_credits:12;
1279 } s;
1280 struct cvmx_pcieep_cfg467_s cn52xx;
1281 struct cvmx_pcieep_cfg467_s cn52xxp1;
1282 struct cvmx_pcieep_cfg467_s cn56xx;
1283 struct cvmx_pcieep_cfg467_s cn56xxp1;
1284};
1285
1286union cvmx_pcieep_cfg468 {
1287 uint32_t u32;
1288 struct cvmx_pcieep_cfg468_s {
1289 uint32_t reserved_24_31:8;
1290 uint32_t queue_mode:3;
1291 uint32_t reserved_20_20:1;
1292 uint32_t header_credits:8;
1293 uint32_t data_credits:12;
1294 } s;
1295 struct cvmx_pcieep_cfg468_s cn52xx;
1296 struct cvmx_pcieep_cfg468_s cn52xxp1;
1297 struct cvmx_pcieep_cfg468_s cn56xx;
1298 struct cvmx_pcieep_cfg468_s cn56xxp1;
1299};
1300
1301union cvmx_pcieep_cfg490 {
1302 uint32_t u32;
1303 struct cvmx_pcieep_cfg490_s {
1304 uint32_t reserved_26_31:6;
1305 uint32_t header_depth:10;
1306 uint32_t reserved_14_15:2;
1307 uint32_t data_depth:14;
1308 } s;
1309 struct cvmx_pcieep_cfg490_s cn52xx;
1310 struct cvmx_pcieep_cfg490_s cn52xxp1;
1311 struct cvmx_pcieep_cfg490_s cn56xx;
1312 struct cvmx_pcieep_cfg490_s cn56xxp1;
1313};
1314
1315union cvmx_pcieep_cfg491 {
1316 uint32_t u32;
1317 struct cvmx_pcieep_cfg491_s {
1318 uint32_t reserved_26_31:6;
1319 uint32_t header_depth:10;
1320 uint32_t reserved_14_15:2;
1321 uint32_t data_depth:14;
1322 } s;
1323 struct cvmx_pcieep_cfg491_s cn52xx;
1324 struct cvmx_pcieep_cfg491_s cn52xxp1;
1325 struct cvmx_pcieep_cfg491_s cn56xx;
1326 struct cvmx_pcieep_cfg491_s cn56xxp1;
1327};
1328
1329union cvmx_pcieep_cfg492 {
1330 uint32_t u32;
1331 struct cvmx_pcieep_cfg492_s {
1332 uint32_t reserved_26_31:6;
1333 uint32_t header_depth:10;
1334 uint32_t reserved_14_15:2;
1335 uint32_t data_depth:14;
1336 } s;
1337 struct cvmx_pcieep_cfg492_s cn52xx;
1338 struct cvmx_pcieep_cfg492_s cn52xxp1;
1339 struct cvmx_pcieep_cfg492_s cn56xx;
1340 struct cvmx_pcieep_cfg492_s cn56xxp1;
1341};
1342
1343union cvmx_pcieep_cfg516 {
1344 uint32_t u32;
1345 struct cvmx_pcieep_cfg516_s {
1346 uint32_t phy_stat:32;
1347 } s;
1348 struct cvmx_pcieep_cfg516_s cn52xx;
1349 struct cvmx_pcieep_cfg516_s cn52xxp1;
1350 struct cvmx_pcieep_cfg516_s cn56xx;
1351 struct cvmx_pcieep_cfg516_s cn56xxp1;
1352};
1353
1354union cvmx_pcieep_cfg517 {
1355 uint32_t u32;
1356 struct cvmx_pcieep_cfg517_s {
1357 uint32_t phy_ctrl:32;
1358 } s;
1359 struct cvmx_pcieep_cfg517_s cn52xx;
1360 struct cvmx_pcieep_cfg517_s cn52xxp1;
1361 struct cvmx_pcieep_cfg517_s cn56xx;
1362 struct cvmx_pcieep_cfg517_s cn56xxp1;
1363};
1364
1365#endif
diff --git a/arch/mips/include/asm/param.h b/arch/mips/include/asm/param.h
new file mode 100644
index 00000000000..da3920fce9a
--- /dev/null
+++ b/arch/mips/include/asm/param.h
@@ -0,0 +1,16 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright 1994 - 2000, 2002 Ralf Baechle (ralf@gnu.org)
7 * Copyright 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_PARAM_H
10#define _ASM_PARAM_H
11
12#define EXEC_PAGESIZE 65536
13
14#include <asm-generic/param.h>
15
16#endif /* _ASM_PARAM_H */
diff --git a/arch/mips/include/asm/poll.h b/arch/mips/include/asm/poll.h
new file mode 100644
index 00000000000..47b95208043
--- /dev/null
+++ b/arch/mips/include/asm/poll.h
@@ -0,0 +1,9 @@
1#ifndef __ASM_POLL_H
2#define __ASM_POLL_H
3
4#define POLLWRNORM POLLOUT
5#define POLLWRBAND 0x0100
6
7#include <asm-generic/poll.h>
8
9#endif /* __ASM_POLL_H */
diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h
new file mode 100644
index 00000000000..c200102c858
--- /dev/null
+++ b/arch/mips/include/asm/posix_types.h
@@ -0,0 +1,144 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996, 97, 98, 99, 2000 by Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_POSIX_TYPES_H
10#define _ASM_POSIX_TYPES_H
11
12#include <asm/sgidefs.h>
13
14/*
15 * This file is generally used by user-level software, so you need to
16 * be a little careful about namespace pollution etc. Also, we cannot
17 * assume GCC is being used.
18 */
19
20typedef unsigned long __kernel_ino_t;
21typedef unsigned int __kernel_mode_t;
22#if (_MIPS_SZLONG == 32)
23typedef unsigned long __kernel_nlink_t;
24#endif
25#if (_MIPS_SZLONG == 64)
26typedef unsigned int __kernel_nlink_t;
27#endif
28typedef long __kernel_off_t;
29typedef int __kernel_pid_t;
30typedef int __kernel_ipc_pid_t;
31typedef unsigned int __kernel_uid_t;
32typedef unsigned int __kernel_gid_t;
33#if (_MIPS_SZLONG == 32)
34typedef unsigned int __kernel_size_t;
35typedef int __kernel_ssize_t;
36typedef int __kernel_ptrdiff_t;
37#endif
38#if (_MIPS_SZLONG == 64)
39typedef unsigned long __kernel_size_t;
40typedef long __kernel_ssize_t;
41typedef long __kernel_ptrdiff_t;
42#endif
43typedef long __kernel_time_t;
44typedef long __kernel_suseconds_t;
45typedef long __kernel_clock_t;
46typedef int __kernel_timer_t;
47typedef int __kernel_clockid_t;
48typedef long __kernel_daddr_t;
49typedef char * __kernel_caddr_t;
50
51typedef unsigned short __kernel_uid16_t;
52typedef unsigned short __kernel_gid16_t;
53typedef unsigned int __kernel_uid32_t;
54typedef unsigned int __kernel_gid32_t;
55typedef __kernel_uid_t __kernel_old_uid_t;
56typedef __kernel_gid_t __kernel_old_gid_t;
57typedef unsigned int __kernel_old_dev_t;
58
59#ifdef __GNUC__
60typedef long long __kernel_loff_t;
61#endif
62
63typedef struct {
64#if (_MIPS_SZLONG == 32)
65 long val[2];
66#endif
67#if (_MIPS_SZLONG == 64)
68 int val[2];
69#endif
70} __kernel_fsid_t;
71
72#if defined(__KERNEL__)
73
74#undef __FD_SET
75static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
76{
77 unsigned long __tmp = __fd / __NFDBITS;
78 unsigned long __rem = __fd % __NFDBITS;
79 __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
80}
81
82#undef __FD_CLR
83static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
84{
85 unsigned long __tmp = __fd / __NFDBITS;
86 unsigned long __rem = __fd % __NFDBITS;
87 __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
88}
89
90#undef __FD_ISSET
91static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
92{
93 unsigned long __tmp = __fd / __NFDBITS;
94 unsigned long __rem = __fd % __NFDBITS;
95 return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
96}
97
98/*
99 * This will unroll the loop for the normal constant case (8 ints,
100 * for a 256-bit fd_set)
101 */
102#undef __FD_ZERO
103static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
104{
105 unsigned long *__tmp = __p->fds_bits;
106 int __i;
107
108 if (__builtin_constant_p(__FDSET_LONGS)) {
109 switch (__FDSET_LONGS) {
110 case 16:
111 __tmp[ 0] = 0; __tmp[ 1] = 0;
112 __tmp[ 2] = 0; __tmp[ 3] = 0;
113 __tmp[ 4] = 0; __tmp[ 5] = 0;
114 __tmp[ 6] = 0; __tmp[ 7] = 0;
115 __tmp[ 8] = 0; __tmp[ 9] = 0;
116 __tmp[10] = 0; __tmp[11] = 0;
117 __tmp[12] = 0; __tmp[13] = 0;
118 __tmp[14] = 0; __tmp[15] = 0;
119 return;
120
121 case 8:
122 __tmp[ 0] = 0; __tmp[ 1] = 0;
123 __tmp[ 2] = 0; __tmp[ 3] = 0;
124 __tmp[ 4] = 0; __tmp[ 5] = 0;
125 __tmp[ 6] = 0; __tmp[ 7] = 0;
126 return;
127
128 case 4:
129 __tmp[ 0] = 0; __tmp[ 1] = 0;
130 __tmp[ 2] = 0; __tmp[ 3] = 0;
131 return;
132 }
133 }
134 __i = __FDSET_LONGS;
135 while (__i) {
136 __i--;
137 *__tmp = 0;
138 __tmp++;
139 }
140}
141
142#endif /* defined(__KERNEL__) */
143
144#endif /* _ASM_POSIX_TYPES_H */
diff --git a/arch/mips/include/asm/resource.h b/arch/mips/include/asm/resource.h
new file mode 100644
index 00000000000..87cb3085269
--- /dev/null
+++ b/arch/mips/include/asm/resource.h
@@ -0,0 +1,35 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995, 96, 98, 99, 2000 by Ralf Baechle
7 * Copyright (C) 1999 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_RESOURCE_H
10#define _ASM_RESOURCE_H
11
12
13/*
14 * These five resource limit IDs have a MIPS/Linux-specific ordering,
15 * the rest comes from the generic header:
16 */
17#define RLIMIT_NOFILE 5 /* max number of open files */
18#define RLIMIT_AS 6 /* address space limit */
19#define RLIMIT_RSS 7 /* max resident set size */
20#define RLIMIT_NPROC 8 /* max number of processes */
21#define RLIMIT_MEMLOCK 9 /* max locked-in-memory address space */
22
23/*
24 * SuS says limits have to be unsigned.
25 * Which makes a ton more sense anyway,
26 * but we keep the old value on MIPS32,
27 * for compatibility:
28 */
29#ifdef CONFIG_32BIT
30# define RLIM_INFINITY 0x7fffffffUL
31#endif
32
33#include <asm-generic/resource.h>
34
35#endif /* _ASM_RESOURCE_H */
diff --git a/arch/mips/include/asm/sembuf.h b/arch/mips/include/asm/sembuf.h
new file mode 100644
index 00000000000..7281a4decaa
--- /dev/null
+++ b/arch/mips/include/asm/sembuf.h
@@ -0,0 +1,22 @@
1#ifndef _ASM_SEMBUF_H
2#define _ASM_SEMBUF_H
3
4/*
5 * The semid64_ds structure for the MIPS architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 2 miscellaneous 64-bit values
11 */
12
13struct semid64_ds {
14 struct ipc64_perm sem_perm; /* permissions .. see ipc.h */
15 __kernel_time_t sem_otime; /* last semop time */
16 __kernel_time_t sem_ctime; /* last change time */
17 unsigned long sem_nsems; /* no. of semaphores in array */
18 unsigned long __unused1;
19 unsigned long __unused2;
20};
21
22#endif /* _ASM_SEMBUF_H */
diff --git a/arch/mips/include/asm/sgidefs.h b/arch/mips/include/asm/sgidefs.h
new file mode 100644
index 00000000000..876442fcfb3
--- /dev/null
+++ b/arch/mips/include/asm/sgidefs.h
@@ -0,0 +1,44 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996, 1999, 2001 Ralf Baechle
7 * Copyright (C) 1999 Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 */
10#ifndef __ASM_SGIDEFS_H
11#define __ASM_SGIDEFS_H
12
13/*
14 * Using a Linux compiler for building Linux seems logic but not to
15 * everybody.
16 */
17#ifndef __linux__
18#error Use a Linux compiler or give up.
19#endif
20
21/*
22 * Definitions for the ISA levels
23 *
24 * With the introduction of MIPS32 / MIPS64 instruction sets definitions
25 * MIPS ISAs are no longer subsets of each other. Therefore comparisons
26 * on these symbols except with == may result in unexpected results and
27 * are forbidden!
28 */
29#define _MIPS_ISA_MIPS1 1
30#define _MIPS_ISA_MIPS2 2
31#define _MIPS_ISA_MIPS3 3
32#define _MIPS_ISA_MIPS4 4
33#define _MIPS_ISA_MIPS5 5
34#define _MIPS_ISA_MIPS32 6
35#define _MIPS_ISA_MIPS64 7
36
37/*
38 * Subprogram calling convention
39 */
40#define _MIPS_SIM_ABI32 1
41#define _MIPS_SIM_NABI32 2
42#define _MIPS_SIM_ABI64 3
43
44#endif /* __ASM_SGIDEFS_H */
diff --git a/arch/mips/include/asm/shmbuf.h b/arch/mips/include/asm/shmbuf.h
new file mode 100644
index 00000000000..f994438277b
--- /dev/null
+++ b/arch/mips/include/asm/shmbuf.h
@@ -0,0 +1,38 @@
1#ifndef _ASM_SHMBUF_H
2#define _ASM_SHMBUF_H
3
4/*
5 * The shmid64_ds structure for the MIPS architecture.
6 * Note extra padding because this structure is passed back and forth
7 * between kernel and user space.
8 *
9 * Pad space is left for:
10 * - 2 miscellaneous 32-bit rsp. 64-bit values
11 */
12
13struct shmid64_ds {
14 struct ipc64_perm shm_perm; /* operation perms */
15 size_t shm_segsz; /* size of segment (bytes) */
16 __kernel_time_t shm_atime; /* last attach time */
17 __kernel_time_t shm_dtime; /* last detach time */
18 __kernel_time_t shm_ctime; /* last change time */
19 __kernel_pid_t shm_cpid; /* pid of creator */
20 __kernel_pid_t shm_lpid; /* pid of last operator */
21 unsigned long shm_nattch; /* no. of current attaches */
22 unsigned long __unused1;
23 unsigned long __unused2;
24};
25
26struct shminfo64 {
27 unsigned long shmmax;
28 unsigned long shmmin;
29 unsigned long shmmni;
30 unsigned long shmseg;
31 unsigned long shmall;
32 unsigned long __unused1;
33 unsigned long __unused2;
34 unsigned long __unused3;
35 unsigned long __unused4;
36};
37
38#endif /* _ASM_SHMBUF_H */
diff --git a/arch/mips/include/asm/smvp.h b/arch/mips/include/asm/smvp.h
new file mode 100644
index 00000000000..0d0e80a39e8
--- /dev/null
+++ b/arch/mips/include/asm/smvp.h
@@ -0,0 +1,19 @@
1#ifndef _ASM_SMVP_H
2#define _ASM_SMVP_H
3
4/*
5 * Definitions for SMVP multitasking on MIPS MT cores
6 */
7struct task_struct;
8
9extern void smvp_smp_setup(void);
10extern void smvp_smp_finish(void);
11extern void smvp_boot_secondary(int cpu, struct task_struct *t);
12extern void smvp_init_secondary(void);
13extern void smvp_smp_finish(void);
14extern void smvp_cpus_done(void);
15extern void smvp_prepare_cpus(unsigned int max_cpus);
16
17/* This is platform specific */
18extern void smvp_send_ipi(int cpu, unsigned int action);
19#endif /* _ASM_SMVP_H */
diff --git a/arch/mips/include/asm/sockios.h b/arch/mips/include/asm/sockios.h
new file mode 100644
index 00000000000..ed1a5f78d22
--- /dev/null
+++ b/arch/mips/include/asm/sockios.h
@@ -0,0 +1,26 @@
1/*
2 * Socket-level I/O control calls.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995 by Ralf Baechle
9 */
10#ifndef _ASM_SOCKIOS_H
11#define _ASM_SOCKIOS_H
12
13#include <asm/ioctl.h>
14
15/* Socket-level I/O control calls. */
16#define FIOGETOWN _IOR('f', 123, int)
17#define FIOSETOWN _IOW('f', 124, int)
18
19#define SIOCATMARK _IOR('s', 7, int)
20#define SIOCSPGRP _IOW('s', 8, pid_t)
21#define SIOCGPGRP _IOR('s', 9, pid_t)
22
23#define SIOCGSTAMP 0x8906 /* Get stamp (timeval) */
24#define SIOCGSTAMPNS 0x8907 /* Get stamp (timespec) */
25
26#endif /* _ASM_SOCKIOS_H */
diff --git a/arch/mips/include/asm/stat.h b/arch/mips/include/asm/stat.h
new file mode 100644
index 00000000000..6e00f751ab6
--- /dev/null
+++ b/arch/mips/include/asm/stat.h
@@ -0,0 +1,132 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995, 1999, 2000 Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 */
9#ifndef _ASM_STAT_H
10#define _ASM_STAT_H
11
12#include <linux/types.h>
13
14#include <asm/sgidefs.h>
15
16#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
17
18struct stat {
19 unsigned st_dev;
20 long st_pad1[3]; /* Reserved for network id */
21 ino_t st_ino;
22 mode_t st_mode;
23 nlink_t st_nlink;
24 uid_t st_uid;
25 gid_t st_gid;
26 unsigned st_rdev;
27 long st_pad2[2];
28 off_t st_size;
29 long st_pad3;
30 /*
31 * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
32 * but we don't have it under Linux.
33 */
34 time_t st_atime;
35 long st_atime_nsec;
36 time_t st_mtime;
37 long st_mtime_nsec;
38 time_t st_ctime;
39 long st_ctime_nsec;
40 long st_blksize;
41 long st_blocks;
42 long st_pad4[14];
43};
44
45/*
46 * This matches struct stat64 in glibc2.1, hence the absolutely insane
47 * amounts of padding around dev_t's. The memory layout is the same as of
48 * struct stat of the 64-bit kernel.
49 */
50
51struct stat64 {
52 unsigned long st_dev;
53 unsigned long st_pad0[3]; /* Reserved for st_dev expansion */
54
55 unsigned long long st_ino;
56
57 mode_t st_mode;
58 nlink_t st_nlink;
59
60 uid_t st_uid;
61 gid_t st_gid;
62
63 unsigned long st_rdev;
64 unsigned long st_pad1[3]; /* Reserved for st_rdev expansion */
65
66 long long st_size;
67
68 /*
69 * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
70 * but we don't have it under Linux.
71 */
72 time_t st_atime;
73 unsigned long st_atime_nsec; /* Reserved for st_atime expansion */
74
75 time_t st_mtime;
76 unsigned long st_mtime_nsec; /* Reserved for st_mtime expansion */
77
78 time_t st_ctime;
79 unsigned long st_ctime_nsec; /* Reserved for st_ctime expansion */
80
81 unsigned long st_blksize;
82 unsigned long st_pad2;
83
84 long long st_blocks;
85};
86
87#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
88
89#if _MIPS_SIM == _MIPS_SIM_ABI64
90
91/* The memory layout is the same as of struct stat64 of the 32-bit kernel. */
92struct stat {
93 unsigned int st_dev;
94 unsigned int st_pad0[3]; /* Reserved for st_dev expansion */
95
96 unsigned long st_ino;
97
98 mode_t st_mode;
99 nlink_t st_nlink;
100
101 uid_t st_uid;
102 gid_t st_gid;
103
104 unsigned int st_rdev;
105 unsigned int st_pad1[3]; /* Reserved for st_rdev expansion */
106
107 off_t st_size;
108
109 /*
110 * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
111 * but we don't have it under Linux.
112 */
113 unsigned int st_atime;
114 unsigned int st_atime_nsec;
115
116 unsigned int st_mtime;
117 unsigned int st_mtime_nsec;
118
119 unsigned int st_ctime;
120 unsigned int st_ctime_nsec;
121
122 unsigned int st_blksize;
123 unsigned int st_pad2;
124
125 unsigned long st_blocks;
126};
127
128#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
129
130#define STAT_HAVE_NSEC 1
131
132#endif /* _ASM_STAT_H */
diff --git a/arch/mips/include/asm/statfs.h b/arch/mips/include/asm/statfs.h
new file mode 100644
index 00000000000..0f805c7a42a
--- /dev/null
+++ b/arch/mips/include/asm/statfs.h
@@ -0,0 +1,100 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995, 1999 by Ralf Baechle
7 */
8#ifndef _ASM_STATFS_H
9#define _ASM_STATFS_H
10
11#include <linux/posix_types.h>
12#include <asm/sgidefs.h>
13
14#ifndef __KERNEL_STRICT_NAMES
15
16#include <linux/types.h>
17
18typedef __kernel_fsid_t fsid_t;
19
20#endif
21
22struct statfs {
23 long f_type;
24#define f_fstyp f_type
25 long f_bsize;
26 long f_frsize; /* Fragment size - unsupported */
27 long f_blocks;
28 long f_bfree;
29 long f_files;
30 long f_ffree;
31 long f_bavail;
32
33 /* Linux specials */
34 __kernel_fsid_t f_fsid;
35 long f_namelen;
36 long f_flags;
37 long f_spare[5];
38};
39
40#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
41
42/*
43 * Unlike the traditional version the LFAPI version has none of the ABI junk
44 */
45struct statfs64 {
46 __u32 f_type;
47 __u32 f_bsize;
48 __u32 f_frsize; /* Fragment size - unsupported */
49 __u32 __pad;
50 __u64 f_blocks;
51 __u64 f_bfree;
52 __u64 f_files;
53 __u64 f_ffree;
54 __u64 f_bavail;
55 __kernel_fsid_t f_fsid;
56 __u32 f_namelen;
57 __u32 f_flags;
58 __u32 f_spare[5];
59};
60
61#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
62
63#if _MIPS_SIM == _MIPS_SIM_ABI64
64
65struct statfs64 { /* Same as struct statfs */
66 long f_type;
67 long f_bsize;
68 long f_frsize; /* Fragment size - unsupported */
69 long f_blocks;
70 long f_bfree;
71 long f_files;
72 long f_ffree;
73 long f_bavail;
74
75 /* Linux specials */
76 __kernel_fsid_t f_fsid;
77 long f_namelen;
78 long f_flags;
79 long f_spare[5];
80};
81
82struct compat_statfs64 {
83 __u32 f_type;
84 __u32 f_bsize;
85 __u32 f_frsize; /* Fragment size - unsupported */
86 __u32 __pad;
87 __u64 f_blocks;
88 __u64 f_bfree;
89 __u64 f_files;
90 __u64 f_ffree;
91 __u64 f_bavail;
92 __kernel_fsid_t f_fsid;
93 __u32 f_namelen;
94 __u32 f_flags;
95 __u32 f_spare[5];
96};
97
98#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
99
100#endif /* _ASM_STATFS_H */
diff --git a/arch/mips/include/asm/swab.h b/arch/mips/include/asm/swab.h
new file mode 100644
index 00000000000..97c2f81b4b4
--- /dev/null
+++ b/arch/mips/include/asm/swab.h
@@ -0,0 +1,59 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996, 99, 2003 by Ralf Baechle
7 */
8#ifndef _ASM_SWAB_H
9#define _ASM_SWAB_H
10
11#include <linux/compiler.h>
12#include <linux/types.h>
13
14#define __SWAB_64_THRU_32__
15
16#ifdef CONFIG_CPU_MIPSR2
17
18static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
19{
20 __asm__(
21 " wsbh %0, %1 \n"
22 : "=r" (x)
23 : "r" (x));
24
25 return x;
26}
27#define __arch_swab16 __arch_swab16
28
29static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
30{
31 __asm__(
32 " wsbh %0, %1 \n"
33 " rotr %0, %0, 16 \n"
34 : "=r" (x)
35 : "r" (x));
36
37 return x;
38}
39#define __arch_swab32 __arch_swab32
40
41/*
42 * Having already checked for CONFIG_CPU_MIPSR2, enable the
43 * optimized version for 64-bit kernel on r2 CPUs.
44 */
45#ifdef CONFIG_64BIT
46static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
47{
48 __asm__(
49 " dsbh %0, %1\n"
50 " dshd %0, %0"
51 : "=r" (x)
52 : "r" (x));
53
54 return x;
55}
56#define __arch_swab64 __arch_swab64
57#endif /* CONFIG_64BIT */
58#endif /* CONFIG_CPU_MIPSR2 */
59#endif /* _ASM_SWAB_H */
diff --git a/arch/mips/include/asm/sysmips.h b/arch/mips/include/asm/sysmips.h
new file mode 100644
index 00000000000..4f47b7d6a5f
--- /dev/null
+++ b/arch/mips/include/asm/sysmips.h
@@ -0,0 +1,25 @@
1/*
2 * Definitions for the MIPS sysmips(2) call
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995 by Ralf Baechle
9 */
10#ifndef _ASM_SYSMIPS_H
11#define _ASM_SYSMIPS_H
12
13/*
14 * Commands for the sysmips(2) call
15 *
16 * sysmips(2) is deprecated - though some existing software uses it.
17 * We only support the following commands.
18 */
19#define SETNAME 1 /* set hostname */
20#define FLUSH_CACHE 3 /* writeback and invalidate caches */
21#define MIPS_FIXADE 7 /* control address error fixing */
22#define MIPS_RDNVRAM 10 /* read NVRAM */
23#define MIPS_ATOMIC_SET 2001 /* atomically set variable */
24
25#endif /* _ASM_SYSMIPS_H */
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
new file mode 100644
index 00000000000..6018c80ce37
--- /dev/null
+++ b/arch/mips/include/asm/system.h
@@ -0,0 +1,235 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
7 * Copyright (C) 1996 by Paul M. Antoine
8 * Copyright (C) 1999 Silicon Graphics
9 * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000 MIPS Technologies, Inc.
11 */
12#ifndef _ASM_SYSTEM_H
13#define _ASM_SYSTEM_H
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/irqflags.h>
18
19#include <asm/addrspace.h>
20#include <asm/barrier.h>
21#include <asm/cmpxchg.h>
22#include <asm/cpu-features.h>
23#include <asm/dsp.h>
24#include <asm/watch.h>
25#include <asm/war.h>
26
27
28/*
29 * switch_to(n) should switch tasks to task nr n, first
30 * checking that n isn't the current task, in which case it does nothing.
31 */
32extern asmlinkage void *resume(void *last, void *next, void *next_ti);
33
34struct task_struct;
35
36extern unsigned int ll_bit;
37extern struct task_struct *ll_task;
38
39#ifdef CONFIG_MIPS_MT_FPAFF
40
41/*
42 * Handle the scheduler resume end of FPU affinity management. We do this
43 * inline to try to keep the overhead down. If we have been forced to run on
44 * a "CPU" with an FPU because of a previous high level of FP computation,
45 * but did not actually use the FPU during the most recent time-slice (CU1
46 * isn't set), we undo the restriction on cpus_allowed.
47 *
48 * We're not calling set_cpus_allowed() here, because we have no need to
49 * force prompt migration - we're already switching the current CPU to a
50 * different thread.
51 */
52
53#define __mips_mt_fpaff_switch_to(prev) \
54do { \
55 struct thread_info *__prev_ti = task_thread_info(prev); \
56 \
57 if (cpu_has_fpu && \
58 test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) && \
59 (!(KSTK_STATUS(prev) & ST0_CU1))) { \
60 clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND); \
61 prev->cpus_allowed = prev->thread.user_cpus_allowed; \
62 } \
63 next->thread.emulated_fp = 0; \
64} while(0)
65
66#else
67#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
68#endif
69
70#define __clear_software_ll_bit() \
71do { \
72 if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc) \
73 ll_bit = 0; \
74} while (0)
75
76#define switch_to(prev, next, last) \
77do { \
78 __mips_mt_fpaff_switch_to(prev); \
79 if (cpu_has_dsp) \
80 __save_dsp(prev); \
81 __clear_software_ll_bit(); \
82 (last) = resume(prev, next, task_thread_info(next)); \
83} while (0)
84
85#define finish_arch_switch(prev) \
86do { \
87 if (cpu_has_dsp) \
88 __restore_dsp(current); \
89 if (cpu_has_userlocal) \
90 write_c0_userlocal(current_thread_info()->tp_value); \
91 __restore_watch(); \
92} while (0)
93
94static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
95{
96 __u32 retval;
97
98 smp_mb__before_llsc();
99
100 if (kernel_uses_llsc && R10000_LLSC_WAR) {
101 unsigned long dummy;
102
103 __asm__ __volatile__(
104 " .set mips3 \n"
105 "1: ll %0, %3 # xchg_u32 \n"
106 " .set mips0 \n"
107 " move %2, %z4 \n"
108 " .set mips3 \n"
109 " sc %2, %1 \n"
110 " beqzl %2, 1b \n"
111 " .set mips0 \n"
112 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
113 : "R" (*m), "Jr" (val)
114 : "memory");
115 } else if (kernel_uses_llsc) {
116 unsigned long dummy;
117
118 do {
119 __asm__ __volatile__(
120 " .set mips3 \n"
121 " ll %0, %3 # xchg_u32 \n"
122 " .set mips0 \n"
123 " move %2, %z4 \n"
124 " .set mips3 \n"
125 " sc %2, %1 \n"
126 " .set mips0 \n"
127 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
128 : "R" (*m), "Jr" (val)
129 : "memory");
130 } while (unlikely(!dummy));
131 } else {
132 unsigned long flags;
133
134 raw_local_irq_save(flags);
135 retval = *m;
136 *m = val;
137 raw_local_irq_restore(flags); /* implies memory barrier */
138 }
139
140 smp_llsc_mb();
141
142 return retval;
143}
144
145#ifdef CONFIG_64BIT
146static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
147{
148 __u64 retval;
149
150 smp_mb__before_llsc();
151
152 if (kernel_uses_llsc && R10000_LLSC_WAR) {
153 unsigned long dummy;
154
155 __asm__ __volatile__(
156 " .set mips3 \n"
157 "1: lld %0, %3 # xchg_u64 \n"
158 " move %2, %z4 \n"
159 " scd %2, %1 \n"
160 " beqzl %2, 1b \n"
161 " .set mips0 \n"
162 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
163 : "R" (*m), "Jr" (val)
164 : "memory");
165 } else if (kernel_uses_llsc) {
166 unsigned long dummy;
167
168 do {
169 __asm__ __volatile__(
170 " .set mips3 \n"
171 " lld %0, %3 # xchg_u64 \n"
172 " move %2, %z4 \n"
173 " scd %2, %1 \n"
174 " .set mips0 \n"
175 : "=&r" (retval), "=m" (*m), "=&r" (dummy)
176 : "R" (*m), "Jr" (val)
177 : "memory");
178 } while (unlikely(!dummy));
179 } else {
180 unsigned long flags;
181
182 raw_local_irq_save(flags);
183 retval = *m;
184 *m = val;
185 raw_local_irq_restore(flags); /* implies memory barrier */
186 }
187
188 smp_llsc_mb();
189
190 return retval;
191}
192#else
193extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
194#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
195#endif
196
197static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
198{
199 switch (size) {
200 case 4:
201 return __xchg_u32(ptr, x);
202 case 8:
203 return __xchg_u64(ptr, x);
204 }
205
206 return x;
207}
208
209#define xchg(ptr, x) \
210({ \
211 BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc); \
212 \
213 ((__typeof__(*(ptr))) \
214 __xchg((unsigned long)(x), (ptr), sizeof(*(ptr)))); \
215})
216
217extern void set_handler(unsigned long offset, void *addr, unsigned long len);
218extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
219
220typedef void (*vi_handler_t)(void);
221extern void *set_vi_handler(int n, vi_handler_t addr);
222
223extern void *set_except_vector(int n, void *addr);
224extern unsigned long ebase;
225extern void per_cpu_trap_init(void);
226
227/*
228 * See include/asm-ia64/system.h; prevents deadlock on SMP
229 * systems.
230 */
231#define __ARCH_WANT_UNLOCKED_CTXSW
232
233extern unsigned long arch_align_stack(unsigned long sp);
234
235#endif /* _ASM_SYSTEM_H */
diff --git a/arch/mips/include/asm/termbits.h b/arch/mips/include/asm/termbits.h
new file mode 100644
index 00000000000..76630b396fa
--- /dev/null
+++ b/arch/mips/include/asm/termbits.h
@@ -0,0 +1,227 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1995, 96, 99, 2001, 06 Ralf Baechle
7 * Copyright (C) 1999 Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 */
10#ifndef _ASM_TERMBITS_H
11#define _ASM_TERMBITS_H
12
13#include <linux/posix_types.h>
14
15typedef unsigned char cc_t;
16typedef unsigned int speed_t;
17typedef unsigned int tcflag_t;
18
19/*
20 * The ABI says nothing about NCC but seems to use NCCS as
21 * replacement for it in struct termio
22 */
23#define NCCS 23
24struct termios {
25 tcflag_t c_iflag; /* input mode flags */
26 tcflag_t c_oflag; /* output mode flags */
27 tcflag_t c_cflag; /* control mode flags */
28 tcflag_t c_lflag; /* local mode flags */
29 cc_t c_line; /* line discipline */
30 cc_t c_cc[NCCS]; /* control characters */
31};
32
33struct termios2 {
34 tcflag_t c_iflag; /* input mode flags */
35 tcflag_t c_oflag; /* output mode flags */
36 tcflag_t c_cflag; /* control mode flags */
37 tcflag_t c_lflag; /* local mode flags */
38 cc_t c_line; /* line discipline */
39 cc_t c_cc[NCCS]; /* control characters */
40 speed_t c_ispeed; /* input speed */
41 speed_t c_ospeed; /* output speed */
42};
43
44struct ktermios {
45 tcflag_t c_iflag; /* input mode flags */
46 tcflag_t c_oflag; /* output mode flags */
47 tcflag_t c_cflag; /* control mode flags */
48 tcflag_t c_lflag; /* local mode flags */
49 cc_t c_line; /* line discipline */
50 cc_t c_cc[NCCS]; /* control characters */
51 speed_t c_ispeed; /* input speed */
52 speed_t c_ospeed; /* output speed */
53};
54
55/* c_cc characters */
56#define VINTR 0 /* Interrupt character [ISIG]. */
57#define VQUIT 1 /* Quit character [ISIG]. */
58#define VERASE 2 /* Erase character [ICANON]. */
59#define VKILL 3 /* Kill-line character [ICANON]. */
60#define VMIN 4 /* Minimum number of bytes read at once [!ICANON]. */
61#define VTIME 5 /* Time-out value (tenths of a second) [!ICANON]. */
62#define VEOL2 6 /* Second EOL character [ICANON]. */
63#define VSWTC 7 /* ??? */
64#define VSWTCH VSWTC
65#define VSTART 8 /* Start (X-ON) character [IXON, IXOFF]. */
66#define VSTOP 9 /* Stop (X-OFF) character [IXON, IXOFF]. */
67#define VSUSP 10 /* Suspend character [ISIG]. */
68#if 0
69/*
70 * VDSUSP is not supported
71 */
72#define VDSUSP 11 /* Delayed suspend character [ISIG]. */
73#endif
74#define VREPRINT 12 /* Reprint-line character [ICANON]. */
75#define VDISCARD 13 /* Discard character [IEXTEN]. */
76#define VWERASE 14 /* Word-erase character [ICANON]. */
77#define VLNEXT 15 /* Literal-next character [IEXTEN]. */
78#define VEOF 16 /* End-of-file character [ICANON]. */
79#define VEOL 17 /* End-of-line character [ICANON]. */
80
81/* c_iflag bits */
82#define IGNBRK 0000001 /* Ignore break condition. */
83#define BRKINT 0000002 /* Signal interrupt on break. */
84#define IGNPAR 0000004 /* Ignore characters with parity errors. */
85#define PARMRK 0000010 /* Mark parity and framing errors. */
86#define INPCK 0000020 /* Enable input parity check. */
87#define ISTRIP 0000040 /* Strip 8th bit off characters. */
88#define INLCR 0000100 /* Map NL to CR on input. */
89#define IGNCR 0000200 /* Ignore CR. */
90#define ICRNL 0000400 /* Map CR to NL on input. */
91#define IUCLC 0001000 /* Map upper case to lower case on input. */
92#define IXON 0002000 /* Enable start/stop output control. */
93#define IXANY 0004000 /* Any character will restart after stop. */
94#define IXOFF 0010000 /* Enable start/stop input control. */
95#define IMAXBEL 0020000 /* Ring bell when input queue is full. */
96#define IUTF8 0040000 /* Input is UTF-8 */
97
98/* c_oflag bits */
99#define OPOST 0000001 /* Perform output processing. */
100#define OLCUC 0000002 /* Map lower case to upper case on output. */
101#define ONLCR 0000004 /* Map NL to CR-NL on output. */
102#define OCRNL 0000010
103#define ONOCR 0000020
104#define ONLRET 0000040
105#define OFILL 0000100
106#define OFDEL 0000200
107#define NLDLY 0000400
108#define NL0 0000000
109#define NL1 0000400
110#define CRDLY 0003000
111#define CR0 0000000
112#define CR1 0001000
113#define CR2 0002000
114#define CR3 0003000
115#define TABDLY 0014000
116#define TAB0 0000000
117#define TAB1 0004000
118#define TAB2 0010000
119#define TAB3 0014000
120#define XTABS 0014000
121#define BSDLY 0020000
122#define BS0 0000000
123#define BS1 0020000
124#define VTDLY 0040000
125#define VT0 0000000
126#define VT1 0040000
127#define FFDLY 0100000
128#define FF0 0000000
129#define FF1 0100000
130/*
131#define PAGEOUT ???
132#define WRAP ???
133 */
134
135/* c_cflag bit meaning */
136#define CBAUD 0010017
137#define B0 0000000 /* hang up */
138#define B50 0000001
139#define B75 0000002
140#define B110 0000003
141#define B134 0000004
142#define B150 0000005
143#define B200 0000006
144#define B300 0000007
145#define B600 0000010
146#define B1200 0000011
147#define B1800 0000012
148#define B2400 0000013
149#define B4800 0000014
150#define B9600 0000015
151#define B19200 0000016
152#define B38400 0000017
153#define EXTA B19200
154#define EXTB B38400
155#define CSIZE 0000060 /* Number of bits per byte (mask). */
156#define CS5 0000000 /* 5 bits per byte. */
157#define CS6 0000020 /* 6 bits per byte. */
158#define CS7 0000040 /* 7 bits per byte. */
159#define CS8 0000060 /* 8 bits per byte. */
160#define CSTOPB 0000100 /* Two stop bits instead of one. */
161#define CREAD 0000200 /* Enable receiver. */
162#define PARENB 0000400 /* Parity enable. */
163#define PARODD 0001000 /* Odd parity instead of even. */
164#define HUPCL 0002000 /* Hang up on last close. */
165#define CLOCAL 0004000 /* Ignore modem status lines. */
166#define CBAUDEX 0010000
167#define BOTHER 0010000
168#define B57600 0010001
169#define B115200 0010002
170#define B230400 0010003
171#define B460800 0010004
172#define B500000 0010005
173#define B576000 0010006
174#define B921600 0010007
175#define B1000000 0010010
176#define B1152000 0010011
177#define B1500000 0010012
178#define B2000000 0010013
179#define B2500000 0010014
180#define B3000000 0010015
181#define B3500000 0010016
182#define B4000000 0010017
183#define CIBAUD 002003600000 /* input baud rate */
184#define CMSPAR 010000000000 /* mark or space (stick) parity */
185#define CRTSCTS 020000000000 /* flow control */
186
187#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
188
189/* c_lflag bits */
190#define ISIG 0000001 /* Enable signals. */
191#define ICANON 0000002 /* Do erase and kill processing. */
192#define XCASE 0000004
193#define ECHO 0000010 /* Enable echo. */
194#define ECHOE 0000020 /* Visual erase for ERASE. */
195#define ECHOK 0000040 /* Echo NL after KILL. */
196#define ECHONL 0000100 /* Echo NL even if ECHO is off. */
197#define NOFLSH 0000200 /* Disable flush after interrupt. */
198#define IEXTEN 0000400 /* Enable DISCARD and LNEXT. */
199#define ECHOCTL 0001000 /* Echo control characters as ^X. */
200#define ECHOPRT 0002000 /* Hardcopy visual erase. */
201#define ECHOKE 0004000 /* Visual erase for KILL. */
202#define FLUSHO 0020000
203#define PENDIN 0040000 /* Retype pending input (state). */
204#define TOSTOP 0100000 /* Send SIGTTOU for background output. */
205#define ITOSTOP TOSTOP
206#define EXTPROC 0200000 /* External processing on pty */
207
208/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
209#define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
210
211/* tcflow() and TCXONC use these */
212#define TCOOFF 0 /* Suspend output. */
213#define TCOON 1 /* Restart suspended output. */
214#define TCIOFF 2 /* Send a STOP character. */
215#define TCION 3 /* Send a START character. */
216
217/* tcflush() and TCFLSH use these */
218#define TCIFLUSH 0 /* Discard data received but not yet read. */
219#define TCOFLUSH 1 /* Discard data written but not yet sent. */
220#define TCIOFLUSH 2 /* Discard all pending data. */
221
222/* tcsetattr uses these */
223#define TCSANOW TCSETS /* Change immediately. */
224#define TCSADRAIN TCSETSW /* Change when pending output is written. */
225#define TCSAFLUSH TCSETSF /* Flush pending input before changing. */
226
227#endif /* _ASM_TERMBITS_H */
diff --git a/arch/mips/include/asm/titan_dep.h b/arch/mips/include/asm/titan_dep.h
new file mode 100644
index 00000000000..fee1908c65d
--- /dev/null
+++ b/arch/mips/include/asm/titan_dep.h
@@ -0,0 +1,231 @@
1/*
2 * Copyright 2003 PMC-Sierra
3 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
4 *
5 * Board specific definititions for the PMC-Sierra Yosemite
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef __TITAN_DEP_H__
14#define __TITAN_DEP_H__
15
16#include <asm/addrspace.h> /* for KSEG1ADDR() */
17#include <asm/byteorder.h> /* for cpu_to_le32() */
18
19#define TITAN_READ(ofs) \
20 (*(volatile u32 *)(ocd_base+(ofs)))
21#define TITAN_READ_16(ofs) \
22 (*(volatile u16 *)(ocd_base+(ofs)))
23#define TITAN_READ_8(ofs) \
24 (*(volatile u8 *)(ocd_base+(ofs)))
25
26#define TITAN_WRITE(ofs, data) \
27 do { *(volatile u32 *)(ocd_base+(ofs)) = (data); } while (0)
28#define TITAN_WRITE_16(ofs, data) \
29 do { *(volatile u16 *)(ocd_base+(ofs)) = (data); } while (0)
30#define TITAN_WRITE_8(ofs, data) \
31 do { *(volatile u8 *)(ocd_base+(ofs)) = (data); } while (0)
32
33/*
34 * PCI specific defines
35 */
36#define TITAN_PCI_0_CONFIG_ADDRESS 0x780
37#define TITAN_PCI_0_CONFIG_DATA 0x784
38
39/*
40 * HT specific defines
41 */
42#define RM9000x2_HTLINK_REG 0xbb000644
43#define RM9000x2_BASE_ADDR 0xbb000000
44
45#define OCD_BASE 0xfb000000UL
46#define OCD_SIZE 0x3000UL
47
48extern unsigned long ocd_base;
49
50/*
51 * OCD Registers
52 */
53#define RM9000x2_OCD_LKB5 0x0128 /* Ethernet */
54#define RM9000x2_OCD_LKM5 0x012c
55
56#define RM9000x2_OCD_LKB7 0x0138 /* HT Region 0 */
57#define RM9000x2_OCD_LKM7 0x013c
58#define RM9000x2_OCD_LKB8 0x0140 /* HT Region 1 */
59#define RM9000x2_OCD_LKM8 0x0144
60
61#define RM9000x2_OCD_LKB9 0x0148 /* Local Bus */
62#define RM9000x2_OCD_LKM9 0x014c
63#define RM9000x2_OCD_LKB10 0x0150
64#define RM9000x2_OCD_LKM10 0x0154
65#define RM9000x2_OCD_LKB11 0x0158
66#define RM9000x2_OCD_LKM11 0x015c
67#define RM9000x2_OCD_LKB12 0x0160
68#define RM9000x2_OCD_LKM12 0x0164
69
70#define RM9000x2_OCD_LKB13 0x0168 /* Scratch RAM */
71#define RM9000x2_OCD_LKM13 0x016c
72
73#define RM9000x2_OCD_LPD0 0x0200 /* Local Bus */
74#define RM9000x2_OCD_LPD1 0x0210
75#define RM9000x2_OCD_LPD2 0x0220
76#define RM9000x2_OCD_LPD3 0x0230
77
78#define RM9000x2_OCD_HTDVID 0x0600 /* HT Device Header */
79#define RM9000x2_OCD_HTSC 0x0604
80#define RM9000x2_OCD_HTCCR 0x0608
81#define RM9000x2_OCD_HTBHL 0x060c
82#define RM9000x2_OCD_HTBAR0 0x0610
83#define RM9000x2_OCD_HTBAR1 0x0614
84#define RM9000x2_OCD_HTBAR2 0x0618
85#define RM9000x2_OCD_HTBAR3 0x061c
86#define RM9000x2_OCD_HTBAR4 0x0620
87#define RM9000x2_OCD_HTBAR5 0x0624
88#define RM9000x2_OCD_HTCBCPT 0x0628
89#define RM9000x2_OCD_HTSDVID 0x062c
90#define RM9000x2_OCD_HTXRA 0x0630
91#define RM9000x2_OCD_HTCAP1 0x0634
92#define RM9000x2_OCD_HTIL 0x063c
93
94#define RM9000x2_OCD_HTLCC 0x0640 /* HT Capability Block */
95#define RM9000x2_OCD_HTLINK 0x0644
96#define RM9000x2_OCD_HTFQREV 0x0648
97
98#define RM9000x2_OCD_HTERCTL 0x0668 /* HT Controller */
99#define RM9000x2_OCD_HTRXDB 0x066c
100#define RM9000x2_OCD_HTIMPED 0x0670
101#define RM9000x2_OCD_HTSWIMP 0x0674
102#define RM9000x2_OCD_HTCAL 0x0678
103
104#define RM9000x2_OCD_HTBAA30 0x0680
105#define RM9000x2_OCD_HTBAA54 0x0684
106#define RM9000x2_OCD_HTMASK0 0x0688
107#define RM9000x2_OCD_HTMASK1 0x068c
108#define RM9000x2_OCD_HTMASK2 0x0690
109#define RM9000x2_OCD_HTMASK3 0x0694
110#define RM9000x2_OCD_HTMASK4 0x0698
111#define RM9000x2_OCD_HTMASK5 0x069c
112
113#define RM9000x2_OCD_HTIFCTL 0x06a0
114#define RM9000x2_OCD_HTPLL 0x06a4
115
116#define RM9000x2_OCD_HTSRI 0x06b0
117#define RM9000x2_OCD_HTRXNUM 0x06b4
118#define RM9000x2_OCD_HTTXNUM 0x06b8
119
120#define RM9000x2_OCD_HTTXCNT 0x06c8
121
122#define RM9000x2_OCD_HTERROR 0x06d8
123#define RM9000x2_OCD_HTRCRCE 0x06dc
124#define RM9000x2_OCD_HTEOI 0x06e0
125
126#define RM9000x2_OCD_CRCR 0x06f0
127
128#define RM9000x2_OCD_HTCFGA 0x06f8
129#define RM9000x2_OCD_HTCFGD 0x06fc
130
131#define RM9000x2_OCD_INTMSG 0x0a00
132
133#define RM9000x2_OCD_INTPIN0 0x0a40
134#define RM9000x2_OCD_INTPIN1 0x0a44
135#define RM9000x2_OCD_INTPIN2 0x0a48
136#define RM9000x2_OCD_INTPIN3 0x0a4c
137#define RM9000x2_OCD_INTPIN4 0x0a50
138#define RM9000x2_OCD_INTPIN5 0x0a54
139#define RM9000x2_OCD_INTPIN6 0x0a58
140#define RM9000x2_OCD_INTPIN7 0x0a5c
141#define RM9000x2_OCD_SEM 0x0a60
142#define RM9000x2_OCD_SEMSET 0x0a64
143#define RM9000x2_OCD_SEMCLR 0x0a68
144
145#define RM9000x2_OCD_TKT 0x0a70
146#define RM9000x2_OCD_TKTINC 0x0a74
147
148#define RM9000x2_OCD_NMICONFIG 0x0ac0 /* Interrupts */
149#define RM9000x2_OCD_INTP0PRI 0x1a80
150#define RM9000x2_OCD_INTP1PRI 0x1a80
151#define RM9000x2_OCD_INTP0STATUS0 0x1b00
152#define RM9000x2_OCD_INTP0MASK0 0x1b04
153#define RM9000x2_OCD_INTP0SET0 0x1b08
154#define RM9000x2_OCD_INTP0CLEAR0 0x1b0c
155#define RM9000x2_OCD_INTP0STATUS1 0x1b10
156#define RM9000x2_OCD_INTP0MASK1 0x1b14
157#define RM9000x2_OCD_INTP0SET1 0x1b18
158#define RM9000x2_OCD_INTP0CLEAR1 0x1b1c
159#define RM9000x2_OCD_INTP0STATUS2 0x1b20
160#define RM9000x2_OCD_INTP0MASK2 0x1b24
161#define RM9000x2_OCD_INTP0SET2 0x1b28
162#define RM9000x2_OCD_INTP0CLEAR2 0x1b2c
163#define RM9000x2_OCD_INTP0STATUS3 0x1b30
164#define RM9000x2_OCD_INTP0MASK3 0x1b34
165#define RM9000x2_OCD_INTP0SET3 0x1b38
166#define RM9000x2_OCD_INTP0CLEAR3 0x1b3c
167#define RM9000x2_OCD_INTP0STATUS4 0x1b40
168#define RM9000x2_OCD_INTP0MASK4 0x1b44
169#define RM9000x2_OCD_INTP0SET4 0x1b48
170#define RM9000x2_OCD_INTP0CLEAR4 0x1b4c
171#define RM9000x2_OCD_INTP0STATUS5 0x1b50
172#define RM9000x2_OCD_INTP0MASK5 0x1b54
173#define RM9000x2_OCD_INTP0SET5 0x1b58
174#define RM9000x2_OCD_INTP0CLEAR5 0x1b5c
175#define RM9000x2_OCD_INTP0STATUS6 0x1b60
176#define RM9000x2_OCD_INTP0MASK6 0x1b64
177#define RM9000x2_OCD_INTP0SET6 0x1b68
178#define RM9000x2_OCD_INTP0CLEAR6 0x1b6c
179#define RM9000x2_OCD_INTP0STATUS7 0x1b70
180#define RM9000x2_OCD_INTP0MASK7 0x1b74
181#define RM9000x2_OCD_INTP0SET7 0x1b78
182#define RM9000x2_OCD_INTP0CLEAR7 0x1b7c
183#define RM9000x2_OCD_INTP1STATUS0 0x2b00
184#define RM9000x2_OCD_INTP1MASK0 0x2b04
185#define RM9000x2_OCD_INTP1SET0 0x2b08
186#define RM9000x2_OCD_INTP1CLEAR0 0x2b0c
187#define RM9000x2_OCD_INTP1STATUS1 0x2b10
188#define RM9000x2_OCD_INTP1MASK1 0x2b14
189#define RM9000x2_OCD_INTP1SET1 0x2b18
190#define RM9000x2_OCD_INTP1CLEAR1 0x2b1c
191#define RM9000x2_OCD_INTP1STATUS2 0x2b20
192#define RM9000x2_OCD_INTP1MASK2 0x2b24
193#define RM9000x2_OCD_INTP1SET2 0x2b28
194#define RM9000x2_OCD_INTP1CLEAR2 0x2b2c
195#define RM9000x2_OCD_INTP1STATUS3 0x2b30
196#define RM9000x2_OCD_INTP1MASK3 0x2b34
197#define RM9000x2_OCD_INTP1SET3 0x2b38
198#define RM9000x2_OCD_INTP1CLEAR3 0x2b3c
199#define RM9000x2_OCD_INTP1STATUS4 0x2b40
200#define RM9000x2_OCD_INTP1MASK4 0x2b44
201#define RM9000x2_OCD_INTP1SET4 0x2b48
202#define RM9000x2_OCD_INTP1CLEAR4 0x2b4c
203#define RM9000x2_OCD_INTP1STATUS5 0x2b50
204#define RM9000x2_OCD_INTP1MASK5 0x2b54
205#define RM9000x2_OCD_INTP1SET5 0x2b58
206#define RM9000x2_OCD_INTP1CLEAR5 0x2b5c
207#define RM9000x2_OCD_INTP1STATUS6 0x2b60
208#define RM9000x2_OCD_INTP1MASK6 0x2b64
209#define RM9000x2_OCD_INTP1SET6 0x2b68
210#define RM9000x2_OCD_INTP1CLEAR6 0x2b6c
211#define RM9000x2_OCD_INTP1STATUS7 0x2b70
212#define RM9000x2_OCD_INTP1MASK7 0x2b74
213#define RM9000x2_OCD_INTP1SET7 0x2b78
214#define RM9000x2_OCD_INTP1CLEAR7 0x2b7c
215
216#define OCD_READ(reg) (*(volatile unsigned int *)(ocd_base + (reg)))
217#define OCD_WRITE(reg, val) \
218 do { *(volatile unsigned int *)(ocd_base + (reg)) = (val); } while (0)
219
220/*
221 * Hypertransport specific macros
222 */
223#define RM9K_WRITE(ofs, data) *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs) = data
224#define RM9K_WRITE_8(ofs, data) *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) = data
225#define RM9K_WRITE_16(ofs, data) *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) = data
226
227#define RM9K_READ(ofs, val) *(val) = *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs)
228#define RM9K_READ_8(ofs, val) *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs)
229#define RM9K_READ_16(ofs, val) *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs)
230
231#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 04:00:14 -0500