Added missing tegra files.HEADmaster

153 files changed, 16270 insertions, 0 deletions

diff --git a/arch/mips/alchemy/common/gpiolib-au1000.c b/arch/mips/alchemy/common/gpiolib-au1000.c
new file mode 100644
index 00000000000..c8e1a94d4a9
--- /dev/null
+++ b/arch/mips/alchemy/common/gpiolib-au1000.c
@@ -0,0 +1,126 @@
+/*
+ *  Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli <florian@openwrt.org>
+ *      GPIOLIB support for Au1000, Au1500, Au1100, Au1550 and Au12x0.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *  Notes :
+ *      au1000 SoC have only one GPIO block : GPIO1
+ *      Au1100, Au15x0, Au12x0 have a second one : GPIO2
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/gpio.h>
+
+static int gpio2_get(struct gpio_chip *chip, unsigned offset)
+{
+        return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE);
+}
+
+static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value);
+}
+
+static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE);
+}
+
+static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset,
+                                  int value)
+{
+        return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE,
+                                                value);
+}
+
+static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE);
+}
+
+
+static int gpio1_get(struct gpio_chip *chip, unsigned offset)
+{
+        return alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE);
+}
+
+static void gpio1_set(struct gpio_chip *chip,
+                                unsigned offset, int value)
+{
+        alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value);
+}
+
+static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+        return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE);
+}
+
+static int gpio1_direction_output(struct gpio_chip *chip,
+                                        unsigned offset, int value)
+{
+        return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE,
+                                             value);
+}
+
+static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+        return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE);
+}
+
+struct gpio_chip alchemy_gpio_chip[] = {
+        [0] = {
+                .label                  = "alchemy-gpio1",
+                .direction_input        = gpio1_direction_input,
+                .direction_output       = gpio1_direction_output,
+                .get                    = gpio1_get,
+                .set                    = gpio1_set,
+                .to_irq                 = gpio1_to_irq,
+                .base                   = ALCHEMY_GPIO1_BASE,
+                .ngpio                  = ALCHEMY_GPIO1_NUM,
+        },
+        [1] = {
+                .label                  = "alchemy-gpio2",
+                .direction_input        = gpio2_direction_input,
+                .direction_output       = gpio2_direction_output,
+                .get                    = gpio2_get,
+                .set                    = gpio2_set,
+                .to_irq                 = gpio2_to_irq,
+                .base                   = ALCHEMY_GPIO2_BASE,
+                .ngpio                  = ALCHEMY_GPIO2_NUM,
+        },
+};
+
+static int __init alchemy_gpiolib_init(void)
+{
+        gpiochip_add(&alchemy_gpio_chip[0]);
+        if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000)
+                gpiochip_add(&alchemy_gpio_chip[1]);
+
+        return 0;
+}
+arch_initcall(alchemy_gpiolib_init);
diff --git a/arch/mips/alchemy/common/pci.c b/arch/mips/alchemy/common/pci.c
new file mode 100644
index 00000000000..7866cf50cf9
--- /dev/null
+++ b/arch/mips/alchemy/common/pci.c
@@ -0,0 +1,104 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *      Alchemy/AMD Au1x00 PCI support.
+ *
+ * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
+ *
+ *  Support for all devices (greater than 16) added by David Gathright.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/mach-au1x00/au1000.h>
+
+/* TBD */
+static struct resource pci_io_resource = {
+        .start  = PCI_IO_START,
+        .end    = PCI_IO_END,
+        .name   = "PCI IO space",
+        .flags  = IORESOURCE_IO
+};
+
+static struct resource pci_mem_resource = {
+        .start  = PCI_MEM_START,
+        .end    = PCI_MEM_END,
+        .name   = "PCI memory space",
+        .flags  = IORESOURCE_MEM
+};
+
+extern struct pci_ops au1x_pci_ops;
+
+static struct pci_controller au1x_controller = {
+        .pci_ops        = &au1x_pci_ops,
+        .io_resource    = &pci_io_resource,
+        .mem_resource   = &pci_mem_resource,
+};
+
+#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
+static unsigned long virt_io_addr;
+#endif
+
+static int __init au1x_pci_setup(void)
+{
+        extern void au1x_pci_cfg_init(void);
+
+#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
+        virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
+                        Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
+
+        if (!virt_io_addr) {
+                printk(KERN_ERR "Unable to ioremap pci space\n");
+                return 1;
+        }
+        au1x_controller.io_map_base = virt_io_addr;
+
+#ifdef CONFIG_DMA_NONCOHERENT
+        {
+                /*
+                 *  Set the NC bit in controller for Au1500 pre-AC silicon
+                 */
+                u32 prid = read_c0_prid();
+
+                if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
+                        au_writel((1 << 16) | au_readl(Au1500_PCI_CFG),
+                                  Au1500_PCI_CFG);
+                        printk(KERN_INFO "Non-coherent PCI accesses enabled\n");
+                }
+        }
+#endif
+
+        set_io_port_base(virt_io_addr);
+#endif
+
+        au1x_pci_cfg_init();
+
+        register_pci_controller(&au1x_controller);
+        return 0;
+}
+
+arch_initcall(au1x_pci_setup);
diff --git a/arch/mips/alchemy/devboards/db1200/Makefile b/arch/mips/alchemy/devboards/db1200/Makefile
new file mode 100644
index 00000000000..17840a5e273
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/Makefile
@@ -0,0 +1 @@
+obj-y += setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c
new file mode 100644
index 00000000000..fbb55935b99
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/platform.c
@@ -0,0 +1,567 @@
+/*
+ * DBAu1200 board platform device registration
+ *
+ * Copyright (C) 2008-2009 Manuel Lauss
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/leds.h>
+#include <linux/mmc/host.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <linux/smc91x.h>
+
+#include <asm/mach-au1x00/au1100_mmc.h>
+#include <asm/mach-au1x00/au1xxx_dbdma.h>
+#include <asm/mach-au1x00/au1550_spi.h>
+#include <asm/mach-db1x00/bcsr.h>
+#include <asm/mach-db1x00/db1200.h>
+
+#include "../platform.h"
+
+static struct mtd_partition db1200_spiflash_parts[] = {
+        {
+                .name   = "DB1200 SPI flash",
+                .offset = 0,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+
+static struct flash_platform_data db1200_spiflash_data = {
+        .name           = "s25fl001",
+        .parts          = db1200_spiflash_parts,
+        .nr_parts       = ARRAY_SIZE(db1200_spiflash_parts),
+        .type           = "m25p10",
+};
+
+static struct spi_board_info db1200_spi_devs[] __initdata = {
+        {
+                /* TI TMP121AIDBVR temp sensor */
+                .modalias       = "tmp121",
+                .max_speed_hz   = 2000000,
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .mode           = 0,
+        },
+        {
+                /* Spansion S25FL001D0FMA SPI flash */
+                .modalias       = "m25p80",
+                .max_speed_hz   = 50000000,
+                .bus_num        = 0,
+                .chip_select    = 1,
+                .mode           = 0,
+                .platform_data  = &db1200_spiflash_data,
+        },
+};
+
+static struct i2c_board_info db1200_i2c_devs[] __initdata = {
+        {
+                /* AT24C04-10 I2C eeprom */
+                I2C_BOARD_INFO("24c04", 0x52),
+        },
+        {
+                /* Philips NE1619 temp/voltage sensor (adm1025 drv) */
+                I2C_BOARD_INFO("ne1619", 0x2d),
+        },
+        {
+                /* I2S audio codec WM8731 */
+                I2C_BOARD_INFO("wm8731", 0x1b),
+        },
+};
+
+/**********************************************************************/
+
+static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
+                                 unsigned int ctrl)
+{
+        struct nand_chip *this = mtd->priv;
+        unsigned long ioaddr = (unsigned long)this->IO_ADDR_W;
+
+        ioaddr &= 0xffffff00;
+
+        if (ctrl & NAND_CLE) {
+                ioaddr += MEM_STNAND_CMD;
+        } else if (ctrl & NAND_ALE) {
+                ioaddr += MEM_STNAND_ADDR;
+        } else {
+                /* assume we want to r/w real data  by default */
+                ioaddr += MEM_STNAND_DATA;
+        }
+        this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr;
+        if (cmd != NAND_CMD_NONE) {
+                __raw_writeb(cmd, this->IO_ADDR_W);
+                wmb();
+        }
+}
+
+static int au1200_nand_device_ready(struct mtd_info *mtd)
+{
+        return __raw_readl((void __iomem *)MEM_STSTAT) & 1;
+}
+
+static const char *db1200_part_probes[] = { "cmdlinepart", NULL };
+
+static struct mtd_partition db1200_nand_parts[] = {
+        {
+                .name   = "NAND FS 0",
+                .offset = 0,
+                .size   = 8 * 1024 * 1024,
+        },
+        {
+                .name   = "NAND FS 1",
+                .offset = MTDPART_OFS_APPEND,
+                .size   = MTDPART_SIZ_FULL
+        },
+};
+
+struct platform_nand_data db1200_nand_platdata = {
+        .chip = {
+                .nr_chips       = 1,
+                .chip_offset    = 0,
+                .nr_partitions  = ARRAY_SIZE(db1200_nand_parts),
+                .partitions     = db1200_nand_parts,
+                .chip_delay     = 20,
+                .part_probe_types = db1200_part_probes,
+        },
+        .ctrl = {
+                .dev_ready      = au1200_nand_device_ready,
+                .cmd_ctrl       = au1200_nand_cmd_ctrl,
+        },
+};
+
+static struct resource db1200_nand_res[] = {
+        [0] = {
+                .start  = DB1200_NAND_PHYS_ADDR,
+                .end    = DB1200_NAND_PHYS_ADDR + 0xff,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device db1200_nand_dev = {
+        .name           = "gen_nand",
+        .num_resources  = ARRAY_SIZE(db1200_nand_res),
+        .resource       = db1200_nand_res,
+        .id             = -1,
+        .dev            = {
+                .platform_data = &db1200_nand_platdata,
+        }
+};
+
+/**********************************************************************/
+
+static struct smc91x_platdata db1200_eth_data = {
+        .flags  = SMC91X_NOWAIT | SMC91X_USE_16BIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
+static struct resource db1200_eth_res[] = {
+        [0] = {
+                .start  = DB1200_ETH_PHYS_ADDR,
+                .end    = DB1200_ETH_PHYS_ADDR + 0xf,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DB1200_ETH_INT,
+                .end    = DB1200_ETH_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device db1200_eth_dev = {
+        .dev    = {
+                .platform_data  = &db1200_eth_data,
+        },
+        .name           = "smc91x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(db1200_eth_res),
+        .resource       = db1200_eth_res,
+};
+
+/**********************************************************************/
+
+static struct resource db1200_ide_res[] = {
+        [0] = {
+                .start  = DB1200_IDE_PHYS_ADDR,
+                .end    = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = DB1200_IDE_INT,
+                .end    = DB1200_IDE_INT,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static u64 ide_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device db1200_ide_dev = {
+        .name           = "au1200-ide",
+        .id             = 0,
+        .dev = {
+                .dma_mask               = &ide_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(db1200_ide_res),
+        .resource       = db1200_ide_res,
+};
+
+/**********************************************************************/
+
+static struct platform_device db1200_rtc_dev = {
+        .name   = "rtc-au1xxx",
+        .id     = -1,
+};
+
+/**********************************************************************/
+
+/* SD carddetects:  they're supposed to be edge-triggered, but ack
+ * doesn't seem to work (CPLD Rev 2).  Instead, the screaming one
+ * is disabled and its counterpart enabled.  The 500ms timeout is
+ * because the carddetect isn't debounced in hardware.
+ */
+static irqreturn_t db1200_mmc_cd(int irq, void *ptr)
+{
+        void(*mmc_cd)(struct mmc_host *, unsigned long);
+
+        if (irq == DB1200_SD0_INSERT_INT) {
+                disable_irq_nosync(DB1200_SD0_INSERT_INT);
+                enable_irq(DB1200_SD0_EJECT_INT);
+        } else {
+                disable_irq_nosync(DB1200_SD0_EJECT_INT);
+                enable_irq(DB1200_SD0_INSERT_INT);
+        }
+
+        /* link against CONFIG_MMC=m */
+        mmc_cd = symbol_get(mmc_detect_change);
+        if (mmc_cd) {
+                mmc_cd(ptr, msecs_to_jiffies(500));
+                symbol_put(mmc_detect_change);
+        }
+
+        return IRQ_HANDLED;
+}
+
+static int db1200_mmc_cd_setup(void *mmc_host, int en)
+{
+        int ret;
+
+        if (en) {
+                ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd,
+                                  IRQF_DISABLED, "sd_insert", mmc_host);
+                if (ret)
+                        goto out;
+
+                ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd,
+                                  IRQF_DISABLED, "sd_eject", mmc_host);
+                if (ret) {
+                        free_irq(DB1200_SD0_INSERT_INT, mmc_host);
+                        goto out;
+                }
+
+                if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT)
+                        enable_irq(DB1200_SD0_EJECT_INT);
+                else
+                        enable_irq(DB1200_SD0_INSERT_INT);
+
+        } else {
+                free_irq(DB1200_SD0_INSERT_INT, mmc_host);
+                free_irq(DB1200_SD0_EJECT_INT, mmc_host);
+        }
+        ret = 0;
+out:
+        return ret;
+}
+
+static void db1200_mmc_set_power(void *mmc_host, int state)
+{
+        if (state) {
+                bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
+                msleep(400);    /* stabilization time */
+        } else
+                bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
+}
+
+static int db1200_mmc_card_readonly(void *mmc_host)
+{
+        return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
+}
+
+static int db1200_mmc_card_inserted(void *mmc_host)
+{
+        return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
+}
+
+static void db1200_mmcled_set(struct led_classdev *led,
+                              enum led_brightness brightness)
+{
+        if (brightness != LED_OFF)
+                bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
+        else
+                bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
+}
+
+static struct led_classdev db1200_mmc_led = {
+        .brightness_set = db1200_mmcled_set,
+};
+
+/* needed by arch/mips/alchemy/common/platform.c */
+struct au1xmmc_platform_data au1xmmc_platdata[] = {
+        [0] = {
+                .cd_setup       = db1200_mmc_cd_setup,
+                .set_power      = db1200_mmc_set_power,
+                .card_inserted  = db1200_mmc_card_inserted,
+                .card_readonly  = db1200_mmc_card_readonly,
+                .led            = &db1200_mmc_led,
+        },
+};
+
+/**********************************************************************/
+
+static struct resource au1200_psc0_res[] = {
+        [0] = {
+                .start  = PSC0_PHYS_ADDR,
+                .end    = PSC0_PHYS_ADDR + 0x000fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1200_PSC0_INT,
+                .end    = AU1200_PSC0_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = DSCR_CMD0_PSC0_TX,
+                .end    = DSCR_CMD0_PSC0_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = DSCR_CMD0_PSC0_RX,
+                .end    = DSCR_CMD0_PSC0_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device db1200_i2c_dev = {
+        .name           = "au1xpsc_smbus",
+        .id             = 0,    /* bus number */
+        .num_resources  = ARRAY_SIZE(au1200_psc0_res),
+        .resource       = au1200_psc0_res,
+};
+
+static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol)
+{
+        if (cs)
+                bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL);
+        else
+                bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0);
+}
+
+static struct au1550_spi_info db1200_spi_platdata = {
+        .mainclk_hz     = 50000000,     /* PSC0 clock */
+        .num_chipselect = 2,
+        .activate_cs    = db1200_spi_cs_en,
+};
+
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device db1200_spi_dev = {
+        .dev    = {
+                .dma_mask               = &spi_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                .platform_data          = &db1200_spi_platdata,
+        },
+        .name           = "au1550-spi",
+        .id             = 0,    /* bus number */
+        .num_resources  = ARRAY_SIZE(au1200_psc0_res),
+        .resource       = au1200_psc0_res,
+};
+
+static struct resource au1200_psc1_res[] = {
+        [0] = {
+                .start  = PSC1_PHYS_ADDR,
+                .end    = PSC1_PHYS_ADDR + 0x000fffff,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AU1200_PSC1_INT,
+                .end    = AU1200_PSC1_INT,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = DSCR_CMD0_PSC1_TX,
+                .end    = DSCR_CMD0_PSC1_TX,
+                .flags  = IORESOURCE_DMA,
+        },
+        [3] = {
+                .start  = DSCR_CMD0_PSC1_RX,
+                .end    = DSCR_CMD0_PSC1_RX,
+                .flags  = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device db1200_audio_dev = {
+        /* name assigned later based on switch setting */
+        .id             = 1,    /* PSC ID */
+        .num_resources  = ARRAY_SIZE(au1200_psc1_res),
+        .resource       = au1200_psc1_res,
+};
+
+static struct platform_device db1200_stac_dev = {
+        .name           = "ac97-codec",
+        .id             = 1,    /* on PSC1 */
+};
+
+static struct platform_device *db1200_devs[] __initdata = {
+        NULL,           /* PSC0, selected by S6.8 */
+        &db1200_ide_dev,
+        &db1200_eth_dev,
+        &db1200_rtc_dev,
+        &db1200_nand_dev,
+        &db1200_audio_dev,
+        &db1200_stac_dev,
+};
+
+static int __init db1200_dev_init(void)
+{
+        unsigned long pfc;
+        unsigned short sw;
+        int swapped;
+
+        i2c_register_board_info(0, db1200_i2c_devs,
+                                ARRAY_SIZE(db1200_i2c_devs));
+        spi_register_board_info(db1200_spi_devs,
+                                ARRAY_SIZE(db1200_i2c_devs));
+
+        /* SWITCHES:    S6.8 I2C/SPI selector  (OFF=I2C  ON=SPI)
+         *              S6.7 AC97/I2S selector (OFF=AC97 ON=I2S)
+         */
+
+        /* NOTE: GPIO215 controls OTG VBUS supply.  In SPI mode however
+         * this pin is claimed by PSC0 (unused though, but pinmux doesn't
+         * allow to free it without crippling the SPI interface).
+         * As a result, in SPI mode, OTG simply won't work (PSC0 uses
+         * it as an input pin which is pulled high on the boards).
+         */
+        pfc = __raw_readl((void __iomem *)SYS_PINFUNC) & ~SYS_PINFUNC_P0A;
+
+        /* switch off OTG VBUS supply */
+        gpio_request(215, "otg-vbus");
+        gpio_direction_output(215, 1);
+
+        printk(KERN_INFO "DB1200 device configuration:\n");
+
+        sw = bcsr_read(BCSR_SWITCHES);
+        if (sw & BCSR_SWITCHES_DIP_8) {
+                db1200_devs[0] = &db1200_i2c_dev;
+                bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
+
+                pfc |= (2 << 17);       /* GPIO2 block owns GPIO215 */
+
+                printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n");
+                printk(KERN_INFO "   OTG port VBUS supply available!\n");
+        } else {
+                db1200_devs[0] = &db1200_spi_dev;
+                bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX);
+
+                pfc |= (1 << 17);       /* PSC0 owns GPIO215 */
+
+                printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n");
+                printk(KERN_INFO "   OTG port VBUS supply disabled\n");
+        }
+        __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
+        wmb();
+
+        /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S!
+         * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S
+         */
+        sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7;
+        if (sw == BCSR_SWITCHES_DIP_8) {
+                bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX);
+                db1200_audio_dev.name = "au1xpsc_i2s";
+                printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n");
+        } else {
+                bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0);
+                db1200_audio_dev.name = "au1xpsc_ac97";
+                printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n");
+        }
+
+        /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */
+        __raw_writel(PSC_SEL_CLK_SERCLK,
+                (void __iomem *)KSEG1ADDR(PSC1_PHYS_ADDR) + PSC_SEL_OFFSET);
+        wmb();
+
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                                    DB1200_PC0_INT,
+                                    DB1200_PC0_INSERT_INT,
+                                    /*DB1200_PC0_STSCHG_INT*/0,
+                                    DB1200_PC0_EJECT_INT,
+                                    0);
+
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x004000000,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
+                                    DB1200_PC1_INT,
+                                    DB1200_PC1_INSERT_INT,
+                                    /*DB1200_PC1_STSCHG_INT*/0,
+                                    DB1200_PC1_EJECT_INT,
+                                    1);
+
+        swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
+        db1x_register_norflash(64 << 20, 2, swapped);
+
+        return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs));
+}
+device_initcall(db1200_dev_init);
+
+/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */
+int board_au1200fb_panel(void)
+{
+        return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
+}
+
+int board_au1200fb_panel_init(void)
+{
+        /* Apply power */
+        bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
+                                BCSR_BOARD_LCDBL);
+        return 0;
+}
+
+int board_au1200fb_panel_shutdown(void)
+{
+        /* Remove power */
+        bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
+                             BCSR_BOARD_LCDBL, 0);
+        return 0;
+}
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
new file mode 100644
index 00000000000..4a8980027ec
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1200/setup.c
@@ -0,0 +1,81 @@
+/*
+ * Alchemy/AMD/RMI DB1200 board setup.
+ *
+ * Licensed under the terms outlined in the file COPYING in the root of
+ * this source archive.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-db1x00/bcsr.h>
+#include <asm/mach-db1x00/db1200.h>
+
+const char *get_system_type(void)
+{
+        return "Alchemy Db1200";
+}
+
+void __init board_setup(void)
+{
+        unsigned long freq0, clksrc, div, pfc;
+        unsigned short whoami;
+
+        bcsr_init(DB1200_BCSR_PHYS_ADDR,
+                  DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
+
+        whoami = bcsr_read(BCSR_WHOAMI);
+        printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"
+                "  Board-ID %d  Daughtercard ID %d\n",
+                (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
+
+        /* SMBus/SPI on PSC0, Audio on PSC1 */
+        pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
+        pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
+        pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
+        pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
+        __raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
+        wmb();
+
+        /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
+         * CPU clock; all other clock generators off/unused.
+         */
+        div = (get_au1x00_speed() + 25000000) / 50000000;
+        if (div & 1)
+                div++;
+        div = ((div >> 1) - 1) & 0xff;
+
+        freq0 = div << SYS_FC_FRDIV0_BIT;
+        __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
+        wmb();
+        freq0 |= SYS_FC_FE0;    /* enable F0 */
+        __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
+        wmb();
+
+        /* psc0_intclk comes 1:1 from F0 */
+        clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
+        __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
+        wmb();
+}
+
+static int __init db1200_arch_init(void)
+{
+        /* GPIO7 is low-level triggered CPLD cascade */
+        irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
+        bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
+
+        /* insert/eject pairs: one of both is always screaming.  To avoid
+         * issues they must not be automatically enabled when initially
+         * requested.
+         */
+        irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
+        return 0;
+}
+arch_initcall(db1200_arch_init);
diff --git a/arch/mips/alchemy/devboards/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile
new file mode 100644
index 00000000000..613c0c0c8be
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1x00/Makefile
@@ -0,0 +1,8 @@
+#
+#  Copyright 2000, 2008 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc. <source@mvista.com>
+#
+# Makefile for the Alchemy Semiconductor DBAu1xx0 boards.
+#
+
+obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
new file mode 100644
index 00000000000..5c956fe8760
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -0,0 +1,255 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      Alchemy Db1x00 board setup.
+ *
+ * Copyright 2000, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/pm.h>
+
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1xxx_eth.h>
+#include <asm/mach-db1x00/db1x00.h>
+#include <asm/mach-db1x00/bcsr.h>
+#include <asm/reboot.h>
+
+#include <prom.h>
+
+#ifdef CONFIG_MIPS_DB1500
+char irq_tab_alchemy[][5] __initdata = {
+        [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - HPT371   */
+        [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
+};
+
+#endif
+
+
+#ifdef CONFIG_MIPS_DB1550
+char irq_tab_alchemy[][5] __initdata = {
+        [11] = { -1, AU1550_PCI_INTC, 0xff, 0xff, 0xff }, /* IDSEL 11 - on-board HPT371 */
+        [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left) */
+        [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
+};
+#endif
+
+
+#ifdef CONFIG_MIPS_BOSPORUS
+char irq_tab_alchemy[][5] __initdata = {
+        [11] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 11 - miniPCI  */
+        [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741   */
+        [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */
+};
+
+/*
+ * Micrel/Kendin 5 port switch attached to MAC0,
+ * MAC0 is associated with PHY address 5 (== WAN port)
+ * MAC1 is not associated with any PHY, since it's connected directly
+ * to the switch.
+ * no interrupts are used
+ */
+static struct au1000_eth_platform_data eth0_pdata = {
+        .phy_static_config      = 1,
+        .phy_addr               = 5,
+};
+
+static void bosporus_power_off(void)
+{
+        while (1)
+                asm volatile (".set mips3 ; wait ; .set mips0");
+}
+
+const char *get_system_type(void)
+{
+        return "Alchemy Bosporus Gateway Reference";
+}
+#endif
+
+
+#ifdef CONFIG_MIPS_MIRAGE
+char irq_tab_alchemy[][5] __initdata = {
+        [11] = { -1, AU1500_PCI_INTD, 0xff, 0xff, 0xff }, /* IDSEL 11 - SMI VGX */
+        [12] = { -1, 0xff, 0xff, AU1500_PCI_INTC, 0xff }, /* IDSEL 12 - PNX1300 */
+        [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 13 - miniPCI */
+};
+
+static void mirage_power_off(void)
+{
+        alchemy_gpio_direction_output(210, 1);
+}
+
+const char *get_system_type(void)
+{
+        return "Alchemy Mirage";
+}
+#endif
+
+
+#if defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
+static void mips_softreset(void)
+{
+        asm volatile ("jr\t%0" : : "r"(0xbfc00000));
+}
+
+#else
+
+const char *get_system_type(void)
+{
+        return "Alchemy Db1x00";
+}
+#endif
+
+
+void __init board_setup(void)
+{
+        unsigned long bcsr1, bcsr2;
+
+        bcsr1 = DB1000_BCSR_PHYS_ADDR;
+        bcsr2 = DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS;
+
+#ifdef CONFIG_MIPS_DB1000
+        printk(KERN_INFO "AMD Alchemy Au1000/Db1000 Board\n");
+#endif
+#ifdef CONFIG_MIPS_DB1500
+        printk(KERN_INFO "AMD Alchemy Au1500/Db1500 Board\n");
+#endif
+#ifdef CONFIG_MIPS_DB1100
+        printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n");
+#endif
+#ifdef CONFIG_MIPS_BOSPORUS
+        au1xxx_override_eth_cfg(0, &eth0_pdata);
+
+        printk(KERN_INFO "AMD Alchemy Bosporus Board\n");
+#endif
+#ifdef CONFIG_MIPS_MIRAGE
+        printk(KERN_INFO "AMD Alchemy Mirage Board\n");
+#endif
+#ifdef CONFIG_MIPS_DB1550
+        printk(KERN_INFO "AMD Alchemy Au1550/Db1550 Board\n");
+
+        bcsr1 = DB1550_BCSR_PHYS_ADDR;
+        bcsr2 = DB1550_BCSR_PHYS_ADDR + DB1550_BCSR_HEXLED_OFS;
+#endif
+
+        /* initialize board register space */
+        bcsr_init(bcsr1, bcsr2);
+
+        /* Not valid for Au1550 */
+#if defined(CONFIG_IRDA) && \
+   (defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100))
+        {
+                u32 pin_func;
+
+                /* Set IRFIRSEL instead of GPIO15 */
+                pin_func = au_readl(SYS_PINFUNC) | SYS_PF_IRF;
+                au_writel(pin_func, SYS_PINFUNC);
+                /* Power off until the driver is in use */
+                bcsr_mod(BCSR_RESETS, BCSR_RESETS_IRDA_MODE_MASK,
+                         BCSR_RESETS_IRDA_MODE_OFF);
+        }
+#endif
+        bcsr_write(BCSR_PCMCIA, 0);     /* turn off PCMCIA power */
+
+        /* Enable GPIO[31:0] inputs */
+        alchemy_gpio1_input_enable();
+
+#ifdef CONFIG_MIPS_MIRAGE
+        {
+                u32 pin_func;
+
+                /* GPIO[20] is output */
+                alchemy_gpio_direction_output(20, 0);
+
+                /* Set GPIO[210:208] instead of SSI_0 */
+                pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0;
+
+                /* Set GPIO[215:211] for LEDs */
+                pin_func |= 5 << 2;
+
+                /* Set GPIO[214:213] for more LEDs */
+                pin_func |= 5 << 12;
+
+                /* Set GPIO[207:200] instead of PCMCIA/LCD */
+                pin_func |= SYS_PF_LCD | SYS_PF_PC;
+                au_writel(pin_func, SYS_PINFUNC);
+
+                /*
+                 * Enable speaker amplifier.  This should
+                 * be part of the audio driver.
+                 */
+                alchemy_gpio_direction_output(209, 1);
+
+                pm_power_off = mirage_power_off;
+                _machine_halt = mirage_power_off;
+                _machine_restart = (void(*)(char *))mips_softreset;
+        }
+#endif
+
+#ifdef CONFIG_MIPS_BOSPORUS
+        pm_power_off = bosporus_power_off;
+        _machine_halt = bosporus_power_off;
+        _machine_restart = (void(*)(char *))mips_softreset;
+#endif
+        au_sync();
+}
+
+static int __init db1x00_init_irq(void)
+{
+#if defined(CONFIG_MIPS_MIRAGE)
+        irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
+#elif defined(CONFIG_MIPS_DB1550)
+        irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);  /* CD0# */
+        irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);  /* CD1# */
+        irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW);  /* CARD0# */
+        irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW);  /* CARD1# */
+        irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+        irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
+#elif defined(CONFIG_MIPS_DB1500)
+        irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
+        irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
+        irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
+        irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
+        irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+        irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
+#elif defined(CONFIG_MIPS_DB1100)
+        irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
+        irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
+        irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
+        irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
+        irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+        irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
+#elif defined(CONFIG_MIPS_DB1000)
+        irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
+        irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
+        irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
+        irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
+        irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+        irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
+#endif
+        return 0;
+}
+arch_initcall(db1x00_init_irq);
diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c
new file mode 100644
index 00000000000..978d5ab3d67
--- /dev/null
+++ b/arch/mips/alchemy/devboards/db1x00/platform.c
@@ -0,0 +1,118 @@
+/*
+ * DBAu1xxx board platform device registration
+ *
+ * Copyright (C) 2009 Manuel Lauss
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-db1x00/bcsr.h>
+#include "../platform.h"
+
+/* DB1xxx PCMCIA interrupt sources:
+ * CD0/1        GPIO0/3
+ * STSCHG0/1    GPIO1/4
+ * CARD0/1      GPIO2/5
+ * Db1550:      0/1, 21/22, 3/5
+ */
+
+#define DB1XXX_HAS_PCMCIA
+#define F_SWAPPED (bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1000_SWAPBOOT)
+
+#if defined(CONFIG_MIPS_DB1000)
+#define DB1XXX_PCMCIA_CD0       AU1000_GPIO0_INT
+#define DB1XXX_PCMCIA_STSCHG0   AU1000_GPIO1_INT
+#define DB1XXX_PCMCIA_CARD0     AU1000_GPIO2_INT
+#define DB1XXX_PCMCIA_CD1       AU1000_GPIO3_INT
+#define DB1XXX_PCMCIA_STSCHG1   AU1000_GPIO4_INT
+#define DB1XXX_PCMCIA_CARD1     AU1000_GPIO5_INT
+#define BOARD_FLASH_SIZE        0x02000000 /* 32MB */
+#define BOARD_FLASH_WIDTH       4 /* 32-bits */
+#elif defined(CONFIG_MIPS_DB1100)
+#define DB1XXX_PCMCIA_CD0       AU1100_GPIO0_INT
+#define DB1XXX_PCMCIA_STSCHG0   AU1100_GPIO1_INT
+#define DB1XXX_PCMCIA_CARD0     AU1100_GPIO2_INT
+#define DB1XXX_PCMCIA_CD1       AU1100_GPIO3_INT
+#define DB1XXX_PCMCIA_STSCHG1   AU1100_GPIO4_INT
+#define DB1XXX_PCMCIA_CARD1     AU1100_GPIO5_INT
+#define BOARD_FLASH_SIZE        0x02000000 /* 32MB */
+#define BOARD_FLASH_WIDTH       4 /* 32-bits */
+#elif defined(CONFIG_MIPS_DB1500)
+#define DB1XXX_PCMCIA_CD0       AU1500_GPIO0_INT
+#define DB1XXX_PCMCIA_STSCHG0   AU1500_GPIO1_INT
+#define DB1XXX_PCMCIA_CARD0     AU1500_GPIO2_INT
+#define DB1XXX_PCMCIA_CD1       AU1500_GPIO3_INT
+#define DB1XXX_PCMCIA_STSCHG1   AU1500_GPIO4_INT
+#define DB1XXX_PCMCIA_CARD1     AU1500_GPIO5_INT
+#define BOARD_FLASH_SIZE        0x02000000 /* 32MB */
+#define BOARD_FLASH_WIDTH       4 /* 32-bits */
+#elif defined(CONFIG_MIPS_DB1550)
+#define DB1XXX_PCMCIA_CD0       AU1550_GPIO0_INT
+#define DB1XXX_PCMCIA_STSCHG0   AU1550_GPIO21_INT
+#define DB1XXX_PCMCIA_CARD0     AU1550_GPIO3_INT
+#define DB1XXX_PCMCIA_CD1       AU1550_GPIO1_INT
+#define DB1XXX_PCMCIA_STSCHG1   AU1550_GPIO22_INT
+#define DB1XXX_PCMCIA_CARD1     AU1550_GPIO5_INT
+#define BOARD_FLASH_SIZE        0x08000000 /* 128MB */
+#define BOARD_FLASH_WIDTH       4 /* 32-bits */
+#else
+/* other board: no PCMCIA */
+#undef DB1XXX_HAS_PCMCIA
+#undef F_SWAPPED
+#define F_SWAPPED 0
+#if defined(CONFIG_MIPS_BOSPORUS)
+#define BOARD_FLASH_SIZE        0x01000000 /* 16MB */
+#define BOARD_FLASH_WIDTH       2 /* 16-bits */
+#elif defined(CONFIG_MIPS_MIRAGE)
+#define BOARD_FLASH_SIZE        0x04000000 /* 64MB */
+#define BOARD_FLASH_WIDTH       4 /* 32-bits */
+#endif
+#endif
+
+static int __init db1xxx_dev_init(void)
+{
+#ifdef DB1XXX_HAS_PCMCIA
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                                    DB1XXX_PCMCIA_CARD0,
+                                    DB1XXX_PCMCIA_CD0,
+                                    /*DB1XXX_PCMCIA_STSCHG0*/0,
+                                    0,
+                                    0);
+
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x004000000,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x004400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x004000000,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x004400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x004000000,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x004010000 - 1,
+                                    DB1XXX_PCMCIA_CARD1,
+                                    DB1XXX_PCMCIA_CD1,
+                                    /*DB1XXX_PCMCIA_STSCHG1*/0,
+                                    0,
+                                    1);
+#endif
+        db1x_register_norflash(BOARD_FLASH_SIZE, BOARD_FLASH_WIDTH, F_SWAPPED);
+        return 0;
+}
+device_initcall(db1xxx_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1000/Makefile b/arch/mips/alchemy/devboards/pb1000/Makefile
new file mode 100644
index 00000000000..97c6615ba2b
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1000/Makefile
@@ -0,0 +1,8 @@
+#
+#  Copyright 2000, 2008 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc. <source@mvista.com>
+#
+# Makefile for the Alchemy Semiconductor Pb1000 board.
+#
+
+obj-y := board_setup.o
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
new file mode 100644
index 00000000000..e64fdcbf75d
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright 2000, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/pm.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-pb1x00/pb1000.h>
+#include <asm/reboot.h>
+#include <prom.h>
+
+#include "../platform.h"
+
+const char *get_system_type(void)
+{
+        return "Alchemy Pb1000";
+}
+
+static void board_reset(char *c)
+{
+        asm volatile ("jr %0" : : "r" (0xbfc00000));
+}
+
+static void board_power_off(void)
+{
+        while (1)
+                asm volatile (
+                "       .set    mips32                                  \n"
+                "       wait                                            \n"
+                "       .set    mips0                                   \n");
+}
+
+void __init board_setup(void)
+{
+        u32 pin_func, static_cfg0;
+        u32 sys_freqctrl, sys_clksrc;
+        u32 prid = read_c0_prid();
+
+        sys_freqctrl = 0;
+        sys_clksrc = 0;
+
+        /* Set AUX clock to 12 MHz * 8 = 96 MHz */
+        au_writel(8, SYS_AUXPLL);
+        alchemy_gpio1_input_enable();
+        udelay(100);
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+        /* Zero and disable FREQ2 */
+        sys_freqctrl = au_readl(SYS_FREQCTRL0);
+        sys_freqctrl &= ~0xFFF00000;
+        au_writel(sys_freqctrl, SYS_FREQCTRL0);
+
+        /* Zero and disable USBH/USBD clocks */
+        sys_clksrc = au_readl(SYS_CLKSRC);
+        sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
+                        SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
+        au_writel(sys_clksrc, SYS_CLKSRC);
+
+        sys_freqctrl = au_readl(SYS_FREQCTRL0);
+        sys_freqctrl &= ~0xFFF00000;
+
+        sys_clksrc = au_readl(SYS_CLKSRC);
+        sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
+                        SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
+
+        switch (prid & 0x000000FF) {
+        case 0x00: /* DA */
+        case 0x01: /* HA */
+        case 0x02: /* HB */
+                /* CPU core freq to 48 MHz to slow it way down... */
+                au_writel(4, SYS_CPUPLL);
+
+                /*
+                 * Setup 48 MHz FREQ2 from CPUPLL for USB Host
+                 * FRDIV2 = 3 -> div by 8 of 384 MHz -> 48 MHz
+                 */
+                sys_freqctrl |= (3 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2;
+                au_writel(sys_freqctrl, SYS_FREQCTRL0);
+
+                /* CPU core freq to 384 MHz */
+                au_writel(0x20, SYS_CPUPLL);
+
+                printk(KERN_INFO "Au1000: 48 MHz OHCI workaround enabled\n");
+                break;
+
+        default: /* HC and newer */
+                /* FREQ2 = aux / 2 = 48 MHz */
+                sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
+                                 SYS_FC_FE2 | SYS_FC_FS2;
+                au_writel(sys_freqctrl, SYS_FREQCTRL0);
+                break;
+        }
+
+        /*
+         * Route 48 MHz FREQ2 into USB Host and/or Device
+         */
+        sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
+        au_writel(sys_clksrc, SYS_CLKSRC);
+
+        /* Configure pins GPIO[14:9] as GPIO */
+        pin_func = au_readl(SYS_PINFUNC) & ~(SYS_PF_UR3 | SYS_PF_USB);
+
+        /* 2nd USB port is USB host */
+        pin_func |= SYS_PF_USB;
+
+        au_writel(pin_func, SYS_PINFUNC);
+
+        alchemy_gpio_direction_input(11);
+        alchemy_gpio_direction_input(13);
+        alchemy_gpio_direction_output(4, 0);
+        alchemy_gpio_direction_output(5, 0);
+#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
+
+        /* Make GPIO 15 an input (for interrupt line) */
+        pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_IRF;
+        /* We don't need I2S, so make it available for GPIO[31:29] */
+        pin_func |= SYS_PF_I2S;
+        au_writel(pin_func, SYS_PINFUNC);
+
+        alchemy_gpio_direction_input(15);
+
+        static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00;
+        au_writel(static_cfg0, MEM_STCFG0);
+
+        /* configure RCE2* for LCD */
+        au_writel(0x00000004, MEM_STCFG2);
+
+        /* MEM_STTIME2 */
+        au_writel(0x09000000, MEM_STTIME2);
+
+        /* Set 32-bit base address decoding for RCE2* */
+        au_writel(0x10003ff0, MEM_STADDR2);
+
+        /*
+         * PCI CPLD setup
+         * Expand CE0 to cover PCI
+         */
+        au_writel(0x11803e40, MEM_STADDR1);
+
+        /* Burst visibility on */
+        au_writel(au_readl(MEM_STCFG0) | 0x1000, MEM_STCFG0);
+
+        au_writel(0x83, MEM_STCFG1);         /* ewait enabled, flash timing */
+        au_writel(0x33030a10, MEM_STTIME1);  /* slower timing for FPGA */
+
+        /* Setup the static bus controller */
+        au_writel(0x00000002, MEM_STCFG3);  /* type = PCMCIA */
+        au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
+        au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
+
+        /*
+         * Enable Au1000 BCLK switching - note: sed1356 must not use
+         * its BCLK (Au1000 LCLK) for any timings
+         */
+        switch (prid & 0x000000FF) {
+        case 0x00: /* DA */
+        case 0x01: /* HA */
+        case 0x02: /* HB */
+                break;
+        default:  /* HC and newer */
+                /*
+                 * Enable sys bus clock divider when IDLE state or no bus
+                 * activity.
+                 */
+                au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
+                break;
+        }
+
+        pm_power_off = board_power_off;
+        _machine_halt = board_power_off;
+        _machine_restart = board_reset;
+}
+
+static int __init pb1000_init_irq(void)
+{
+        irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
+        return 0;
+}
+arch_initcall(pb1000_init_irq);
+
+static int __init pb1000_device_init(void)
+{
+        return db1x_register_norflash(8 * 1024 * 1024, 4, 0);
+}
+device_initcall(pb1000_device_init);
diff --git a/arch/mips/alchemy/devboards/pb1100/Makefile b/arch/mips/alchemy/devboards/pb1100/Makefile
new file mode 100644
index 00000000000..7e3756c83fe
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1100/Makefile
@@ -0,0 +1,8 @@
+#
+#  Copyright 2000, 2001, 2008 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc. <source@mvista.com>
+#
+# Makefile for the Alchemy Semiconductor Pb1100 board.
+#
+
+obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c
new file mode 100644
index 00000000000..d108fd573aa
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2002, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-db1x00/bcsr.h>
+
+#include <prom.h>
+
+
+const char *get_system_type(void)
+{
+        return "Alchemy Pb1100";
+}
+
+void __init board_setup(void)
+{
+        volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;
+
+        bcsr_init(DB1000_BCSR_PHYS_ADDR,
+                  DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
+
+        /* Set AUX clock to 12 MHz * 8 = 96 MHz */
+        au_writel(8, SYS_AUXPLL);
+        alchemy_gpio1_input_enable();
+        udelay(100);
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+        {
+                u32 pin_func, sys_freqctrl, sys_clksrc;
+
+                /* Configure pins GPIO[14:9] as GPIO */
+                pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
+
+                /* Zero and disable FREQ2 */
+                sys_freqctrl = au_readl(SYS_FREQCTRL0);
+                sys_freqctrl &= ~0xFFF00000;
+                au_writel(sys_freqctrl, SYS_FREQCTRL0);
+
+                /* Zero and disable USBH/USBD/IrDA clock */
+                sys_clksrc = au_readl(SYS_CLKSRC);
+                sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
+                au_writel(sys_clksrc, SYS_CLKSRC);
+
+                sys_freqctrl = au_readl(SYS_FREQCTRL0);
+                sys_freqctrl &= ~0xFFF00000;
+
+                sys_clksrc = au_readl(SYS_CLKSRC);
+                sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
+
+                /* FREQ2 = aux / 2 = 48 MHz */
+                sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
+                                SYS_FC_FE2 | SYS_FC_FS2;
+                au_writel(sys_freqctrl, SYS_FREQCTRL0);
+
+                /*
+                 * Route 48 MHz FREQ2 into USBH/USBD/IrDA
+                 */
+                sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MIR_BIT;
+                au_writel(sys_clksrc, SYS_CLKSRC);
+
+                /* Setup the static bus controller */
+                au_writel(0x00000002, MEM_STCFG3);  /* type = PCMCIA */
+                au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
+                au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
+
+                /*
+                 * Get USB Functionality pin state (device vs host drive pins).
+                 */
+                pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
+                /* 2nd USB port is USB host. */
+                pin_func |= SYS_PF_USB;
+                au_writel(pin_func, SYS_PINFUNC);
+        }
+#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
+
+        /* Enable sys bus clock divider when IDLE state or no bus activity. */
+        au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
+
+        /* Enable the RTC if not already enabled. */
+        if (!(readb(base + 0x28) & 0x20)) {
+                writeb(readb(base + 0x28) | 0x20, base + 0x28);
+                au_sync();
+        }
+        /* Put the clock in BCD mode. */
+        if (readb(base + 0x2C) & 0x4) { /* reg B */
+                writeb(readb(base + 0x2c) & ~0x4, base + 0x2c);
+                au_sync();
+        }
+}
+
+static int __init pb1100_init_irq(void)
+{
+        irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
+        irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
+        irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
+        irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
+
+        return 0;
+}
+arch_initcall(pb1100_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c
new file mode 100644
index 00000000000..2c8dc29759f
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1100/platform.c
@@ -0,0 +1,50 @@
+/*
+ * Pb1100 board platform device registration
+ *
+ * Copyright (C) 2009 Manuel Lauss
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-db1x00/bcsr.h>
+
+#include "../platform.h"
+
+static int __init pb1100_dev_init(void)
+{
+        int swapped;
+
+        /* PCMCIA. single socket, identical to Pb1500 */
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                                    AU1100_GPIO11_INT,   /* card */
+                                    AU1100_GPIO9_INT,    /* insert */
+                                    /*AU1100_GPIO10_INT*/0, /* stschg */
+                                    0,                   /* eject */
+                                    0);                  /* id */
+
+        swapped = bcsr_read(BCSR_STATUS) &  BCSR_STATUS_DB1000_SWAPBOOT;
+        db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
+
+        return 0;
+}
+device_initcall(pb1100_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1200/Makefile b/arch/mips/alchemy/devboards/pb1200/Makefile
new file mode 100644
index 00000000000..18c1bd53e4c
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1200/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards.
+#
+
+obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c
new file mode 100644
index 00000000000..6d06b07c238
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c
@@ -0,0 +1,174 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      Alchemy Pb1200/Db1200 board setup.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/sched.h>
+
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-db1x00/bcsr.h>
+
+#ifdef CONFIG_MIPS_PB1200
+#include <asm/mach-pb1x00/pb1200.h>
+#endif
+
+#ifdef CONFIG_MIPS_DB1200
+#include <asm/mach-db1x00/db1200.h>
+#define PB1200_INT_BEGIN DB1200_INT_BEGIN
+#define PB1200_INT_END DB1200_INT_END
+#endif
+
+#include <prom.h>
+
+const char *get_system_type(void)
+{
+        return "Alchemy Pb1200";
+}
+
+void __init board_setup(void)
+{
+        printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
+        bcsr_init(PB1200_BCSR_PHYS_ADDR,
+                  PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
+
+#if 0
+        {
+                u32 pin_func;
+
+                /*
+                 * Enable PSC1 SYNC for AC97.  Normaly done in audio driver,
+                 * but it is board specific code, so put it here.
+                 */
+                pin_func = au_readl(SYS_PINFUNC);
+                au_sync();
+                pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
+                au_writel(pin_func, SYS_PINFUNC);
+
+                au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */
+                au_sync();
+        }
+#endif
+
+#if defined(CONFIG_I2C_AU1550)
+        {
+                u32 freq0, clksrc;
+                u32 pin_func;
+
+                /* Select SMBus in CPLD */
+                bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
+
+                pin_func = au_readl(SYS_PINFUNC);
+                au_sync();
+                pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
+                /* Set GPIOs correctly */
+                pin_func |= 2 << 17;
+                au_writel(pin_func, SYS_PINFUNC);
+                au_sync();
+
+                /* The I2C driver depends on 50 MHz clock */
+                freq0 = au_readl(SYS_FREQCTRL0);
+                au_sync();
+                freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
+                freq0 |= 3 << SYS_FC_FRDIV1_BIT;
+                /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */
+                au_writel(freq0, SYS_FREQCTRL0);
+                au_sync();
+                freq0 |= SYS_FC_FE1;
+                au_writel(freq0, SYS_FREQCTRL0);
+                au_sync();
+
+                clksrc = au_readl(SYS_CLKSRC);
+                au_sync();
+                clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK);
+                /* Bit 22 is EXTCLK0 for PSC0 */
+                clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT;
+                au_writel(clksrc, SYS_CLKSRC);
+                au_sync();
+        }
+#endif
+
+        /*
+         * The Pb1200 development board uses external MUX for PSC0 to
+         * support SMB/SPI. bcsr_resets bit 12: 0=SMB 1=SPI
+         */
+#ifdef CONFIG_I2C_AU1550
+        bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0);
+#endif
+        au_sync();
+}
+
+static int __init pb1200_init_irq(void)
+{
+        /* We have a problem with CPLD rev 3. */
+        if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n");
+                printk(KERN_ERR "updated to latest revision. This software will\n");
+                printk(KERN_ERR "not work on anything less than CPLD rev 4.\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                printk(KERN_ERR "WARNING!!!\n");
+                panic("Game over.  Your score is 0.");
+        }
+
+        irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
+        bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
+
+        return 0;
+}
+arch_initcall(pb1200_init_irq);
+
+
+int board_au1200fb_panel(void)
+{
+        return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f;
+}
+
+int board_au1200fb_panel_init(void)
+{
+        /* Apply power */
+        bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
+                                BCSR_BOARD_LCDBL);
+        /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */
+        return 0;
+}
+
+int board_au1200fb_panel_shutdown(void)
+{
+        /* Remove power */
+        bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
+                             BCSR_BOARD_LCDBL, 0);
+        /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */
+        return 0;
+}
diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
new file mode 100644
index 00000000000..3ef2dceeb79
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
@@ -0,0 +1,203 @@
+/*
+ * Pb1200/DBAu1200 board platform device registration
+ *
+ * Copyright (C) 2008 MontaVista Software Inc. <source@mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/init.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/smc91x.h>
+
+#include <asm/mach-au1x00/au1xxx.h>
+#include <asm/mach-au1x00/au1100_mmc.h>
+#include <asm/mach-db1x00/bcsr.h>
+
+#include "../platform.h"
+
+static int mmc_activity;
+
+static void pb1200mmc0_set_power(void *mmc_host, int state)
+{
+        if (state)
+                bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR);
+        else
+                bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0);
+
+        msleep(1);
+}
+
+static int pb1200mmc0_card_readonly(void *mmc_host)
+{
+        return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0;
+}
+
+static int pb1200mmc0_card_inserted(void *mmc_host)
+{
+        return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0;
+}
+
+static void pb1200_mmcled_set(struct led_classdev *led,
+                        enum led_brightness brightness)
+{
+        if (brightness != LED_OFF) {
+                if (++mmc_activity == 1)
+                        bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0);
+        } else {
+                if (--mmc_activity == 0)
+                        bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0);
+        }
+}
+
+static struct led_classdev pb1200mmc_led = {
+        .brightness_set = pb1200_mmcled_set,
+};
+
+static void pb1200mmc1_set_power(void *mmc_host, int state)
+{
+        if (state)
+                bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD1PWR);
+        else
+                bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD1PWR, 0);
+
+        msleep(1);
+}
+
+static int pb1200mmc1_card_readonly(void *mmc_host)
+{
+        return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD1WP) ? 1 : 0;
+}
+
+static int pb1200mmc1_card_inserted(void *mmc_host)
+{
+        return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
+}
+
+const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
+        [0] = {
+                .set_power      = pb1200mmc0_set_power,
+                .card_inserted  = pb1200mmc0_card_inserted,
+                .card_readonly  = pb1200mmc0_card_readonly,
+                .cd_setup       = NULL,         /* use poll-timer in driver */
+                .led            = &pb1200mmc_led,
+        },
+        [1] = {
+                .set_power      = pb1200mmc1_set_power,
+                .card_inserted  = pb1200mmc1_card_inserted,
+                .card_readonly  = pb1200mmc1_card_readonly,
+                .cd_setup       = NULL,         /* use poll-timer in driver */
+                .led            = &pb1200mmc_led,
+        },
+};
+
+static struct resource ide_resources[] = {
+        [0] = {
+                .start  = IDE_PHYS_ADDR,
+                .end    = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start  = IDE_INT,
+                .end    = IDE_INT,
+                .flags  = IORESOURCE_IRQ
+        }
+};
+
+static u64 ide_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device ide_device = {
+        .name           = "au1200-ide",
+        .id             = 0,
+        .dev = {
+                .dma_mask               = &ide_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(ide_resources),
+        .resource       = ide_resources
+};
+
+static struct smc91x_platdata smc_data = {
+        .flags  = SMC91X_NOWAIT | SMC91X_USE_16BIT,
+        .leda   = RPC_LED_100_10,
+        .ledb   = RPC_LED_TX_RX,
+};
+
+static struct resource smc91c111_resources[] = {
+        [0] = {
+                .name   = "smc91x-regs",
+                .start  = SMC91C111_PHYS_ADDR,
+                .end    = SMC91C111_PHYS_ADDR + 0xf,
+                .flags  = IORESOURCE_MEM
+        },
+        [1] = {
+                .start  = SMC91C111_INT,
+                .end    = SMC91C111_INT,
+                .flags  = IORESOURCE_IRQ
+        },
+};
+
+static struct platform_device smc91c111_device = {
+        .dev    = {
+                .platform_data  = &smc_data,
+        },
+        .name           = "smc91x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smc91c111_resources),
+        .resource       = smc91c111_resources
+};
+
+static struct platform_device *board_platform_devices[] __initdata = {
+        &ide_device,
+        &smc91c111_device
+};
+
+static int __init board_register_devices(void)
+{
+        int swapped;
+
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                                    PB1200_PC0_INT,
+                                    PB1200_PC0_INSERT_INT,
+                                    /*PB1200_PC0_STSCHG_INT*/0,
+                                    PB1200_PC0_EJECT_INT,
+                                    0);
+
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x008000000,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x008400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x008000000,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x008010000 - 1,
+                                    PB1200_PC1_INT,
+                                    PB1200_PC1_INSERT_INT,
+                                    /*PB1200_PC1_STSCHG_INT*/0,
+                                    PB1200_PC1_EJECT_INT,
+                                    1);
+
+        swapped = bcsr_read(BCSR_STATUS) &  BCSR_STATUS_DB1200_SWAPBOOT;
+        db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
+
+        return platform_add_devices(board_platform_devices,
+                                    ARRAY_SIZE(board_platform_devices));
+}
+device_initcall(board_register_devices);
diff --git a/arch/mips/alchemy/devboards/pb1500/Makefile b/arch/mips/alchemy/devboards/pb1500/Makefile
new file mode 100644
index 00000000000..e83b151b5b6
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1500/Makefile
@@ -0,0 +1,8 @@
+#
+#  Copyright 2000, 2001, 2008 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc. <source@mvista.com>
+#
+# Makefile for the Alchemy Semiconductor Pb1500 board.
+#
+
+obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
new file mode 100644
index 00000000000..3b4fa320696
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2000, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-db1x00/bcsr.h>
+
+#include <prom.h>
+
+
+char irq_tab_alchemy[][5] __initdata = {
+        [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff },   /* IDSEL 12 - HPT370        */
+        [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD },   /* IDSEL 13 - PCI slot */
+};
+
+
+const char *get_system_type(void)
+{
+        return "Alchemy Pb1500";
+}
+
+void __init board_setup(void)
+{
+        u32 pin_func;
+        u32 sys_freqctrl, sys_clksrc;
+
+        bcsr_init(DB1000_BCSR_PHYS_ADDR,
+                  DB1000_BCSR_PHYS_ADDR + DB1000_BCSR_HEXLED_OFS);
+
+        sys_clksrc = sys_freqctrl = pin_func = 0;
+        /* Set AUX clock to 12 MHz * 8 = 96 MHz */
+        au_writel(8, SYS_AUXPLL);
+        alchemy_gpio1_input_enable();
+        udelay(100);
+
+        /* GPIO201 is input for PCMCIA card detect */
+        /* GPIO203 is input for PCMCIA interrupt request */
+        alchemy_gpio_direction_input(201);
+        alchemy_gpio_direction_input(203);
+
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+
+        /* Zero and disable FREQ2 */
+        sys_freqctrl = au_readl(SYS_FREQCTRL0);
+        sys_freqctrl &= ~0xFFF00000;
+        au_writel(sys_freqctrl, SYS_FREQCTRL0);
+
+        /* zero and disable USBH/USBD clocks */
+        sys_clksrc = au_readl(SYS_CLKSRC);
+        sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
+                        SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
+        au_writel(sys_clksrc, SYS_CLKSRC);
+
+        sys_freqctrl = au_readl(SYS_FREQCTRL0);
+        sys_freqctrl &= ~0xFFF00000;
+
+        sys_clksrc = au_readl(SYS_CLKSRC);
+        sys_clksrc &= ~(SYS_CS_CUD | SYS_CS_DUD | SYS_CS_MUD_MASK |
+                        SYS_CS_CUH | SYS_CS_DUH | SYS_CS_MUH_MASK);
+
+        /* FREQ2 = aux/2 = 48 MHz */
+        sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) | SYS_FC_FE2 | SYS_FC_FS2;
+        au_writel(sys_freqctrl, SYS_FREQCTRL0);
+
+        /*
+         * Route 48MHz FREQ2 into USB Host and/or Device
+         */
+        sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MUH_BIT;
+        au_writel(sys_clksrc, SYS_CLKSRC);
+
+        pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
+        /* 2nd USB port is USB host */
+        pin_func |= SYS_PF_USB;
+        au_writel(pin_func, SYS_PINFUNC);
+#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
+
+#ifdef CONFIG_PCI
+        /* Setup PCI bus controller */
+        au_writel(0, Au1500_PCI_CMEM);
+        au_writel(0x00003fff, Au1500_CFG_BASE);
+#if defined(__MIPSEB__)
+        au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
+#else
+        au_writel(0xf, Au1500_PCI_CFG);
+#endif
+        au_writel(0xf0000000, Au1500_PCI_MWMASK_DEV);
+        au_writel(0, Au1500_PCI_MWBASE_REV_CCL);
+        au_writel(0x02a00356, Au1500_PCI_STATCMD);
+        au_writel(0x00003c04, Au1500_PCI_HDRTYPE);
+        au_writel(0x00000008, Au1500_PCI_MBAR);
+        au_sync();
+#endif
+
+        /* Enable sys bus clock divider when IDLE state or no bus activity. */
+        au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
+
+        /* Enable the RTC if not already enabled */
+        if (!(au_readl(0xac000028) & 0x20)) {
+                printk(KERN_INFO "enabling clock ...\n");
+                au_writel((au_readl(0xac000028) | 0x20), 0xac000028);
+        }
+        /* Put the clock in BCD mode */
+        if (au_readl(0xac00002c) & 0x4) { /* reg B */
+                au_writel(au_readl(0xac00002c) & ~0x4, 0xac00002c);
+                au_sync();
+        }
+}
+
+static int __init pb1500_init_irq(void)
+{
+        irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW);   /* CD0# */
+        irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW);  /* CARD0 */
+        irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW);  /* STSCHG0# */
+        irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
+        irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
+
+        return 0;
+}
+arch_initcall(pb1500_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c
new file mode 100644
index 00000000000..d443bc7aa76
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1500/platform.c
@@ -0,0 +1,49 @@
+/*
+ * Pb1500 board platform device registration
+ *
+ * Copyright (C) 2009 Manuel Lauss
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-db1x00/bcsr.h>
+
+#include "../platform.h"
+
+static int __init pb1500_dev_init(void)
+{
+        int swapped;
+
+        /* PCMCIA. single socket, identical to Pb1500 */
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                                    AU1500_GPIO11_INT,   /* card */
+                                    AU1500_GPIO9_INT,    /* insert */
+                                    /*AU1500_GPIO10_INT*/0, /* stschg */
+                                    0,                   /* eject */
+                                    0);                  /* id */
+
+        swapped = bcsr_read(BCSR_STATUS) &  BCSR_STATUS_DB1000_SWAPBOOT;
+        db1x_register_norflash(64 * 1024 * 1024, 4, swapped);
+
+        return 0;
+}
+device_initcall(pb1500_dev_init);
diff --git a/arch/mips/alchemy/devboards/pb1550/Makefile b/arch/mips/alchemy/devboards/pb1550/Makefile
new file mode 100644
index 00000000000..9661b6ec5dd
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1550/Makefile
@@ -0,0 +1,8 @@
+#
+#  Copyright 2000, 2008 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc. <source@mvista.com>
+#
+# Makefile for the Alchemy Semiconductor Pb1550 board.
+#
+
+obj-y := board_setup.o platform.o
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
new file mode 100644
index 00000000000..b790213848b
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c
@@ -0,0 +1,86 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      Alchemy Pb1550 board setup.
+ *
+ * Copyright 2000, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/interrupt.h>
+
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-pb1x00/pb1550.h>
+#include <asm/mach-db1x00/bcsr.h>
+#include <asm/mach-au1x00/gpio.h>
+
+#include <prom.h>
+
+
+char irq_tab_alchemy[][5] __initdata = {
+        [12] = { -1, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD, AU1550_PCI_INTA }, /* IDSEL 12 - PCI slot 2 (left)  */
+        [13] = { -1, AU1550_PCI_INTA, AU1550_PCI_INTB, AU1550_PCI_INTC, AU1550_PCI_INTD }, /* IDSEL 13 - PCI slot 1 (right) */
+};
+
+const char *get_system_type(void)
+{
+        return "Alchemy Pb1550";
+}
+
+void __init board_setup(void)
+{
+        u32 pin_func;
+
+        bcsr_init(PB1550_BCSR_PHYS_ADDR,
+                  PB1550_BCSR_PHYS_ADDR + PB1550_BCSR_HEXLED_OFS);
+
+        alchemy_gpio2_enable();
+
+        /*
+         * Enable PSC1 SYNC for AC'97.  Normaly done in audio driver,
+         * but it is board specific code, so put it here.
+         */
+        pin_func = au_readl(SYS_PINFUNC);
+        au_sync();
+        pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
+        au_writel(pin_func, SYS_PINFUNC);
+
+        bcsr_write(BCSR_PCMCIA, 0);     /* turn off PCMCIA power */
+
+        printk(KERN_INFO "AMD Alchemy Pb1550 Board\n");
+}
+
+static int __init pb1550_init_irq(void)
+{
+        irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
+
+        /* enable both PCMCIA card irqs in the shared line */
+        alchemy_gpio2_enable_int(201);
+        alchemy_gpio2_enable_int(202);
+
+        return 0;
+}
+arch_initcall(pb1550_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c
new file mode 100644
index 00000000000..d7150d0f49c
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pb1550/platform.c
@@ -0,0 +1,69 @@
+/*
+ * Pb1550 board platform device registration
+ *
+ * Copyright (C) 2009 Manuel Lauss
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-pb1x00/pb1550.h>
+#include <asm/mach-db1x00/bcsr.h>
+
+#include "../platform.h"
+
+static int __init pb1550_dev_init(void)
+{
+        int swapped;
+
+        /* Pb1550, like all others, also has statuschange irqs; however they're
+        * wired up on one of the Au1550's shared GPIO201_205 line, which also
+        * services the PCMCIA card interrupts.  So we ignore statuschange and
+        * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia
+        * drivers are used to shared irqs and b) statuschange isn't really use-
+        * ful anyway.
+        */
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x000400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x000010000 - 1,
+                                    AU1550_GPIO201_205_INT,
+                                    AU1550_GPIO0_INT,
+                                    0,
+                                    0,
+                                    0);
+
+        db1x_register_pcmcia_socket(PCMCIA_ATTR_PHYS_ADDR + 0x008000000,
+                                    PCMCIA_ATTR_PHYS_ADDR + 0x008400000 - 1,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x008000000,
+                                    PCMCIA_MEM_PHYS_ADDR  + 0x008400000 - 1,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x008000000,
+                                    PCMCIA_IO_PHYS_ADDR   + 0x008010000 - 1,
+                                    AU1550_GPIO201_205_INT,
+                                    AU1550_GPIO1_INT,
+                                    0,
+                                    0,
+                                    1);
+
+        swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_PB1550_SWAPBOOT;
+        db1x_register_norflash(128 * 1024 * 1024, 4, swapped);
+
+        return 0;
+}
+device_initcall(pb1550_dev_init);
diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c
new file mode 100644
index 00000000000..e5306b56da6
--- /dev/null
+++ b/arch/mips/alchemy/devboards/prom.c
@@ -0,0 +1,66 @@
+/*
+ * Common code used by all Alchemy develboards.
+ *
+ * Extracted from files which had this to say:
+ *
+ * Copyright 2000, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <asm/bootinfo.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <prom.h>
+
+#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_DB1000) || \
+    defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \
+    defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) || \
+    defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
+#define ALCHEMY_BOARD_DEFAULT_MEMSIZE   0x04000000
+
+#else   /* Au1550/Au1200-based develboards */
+#define ALCHEMY_BOARD_DEFAULT_MEMSIZE   0x08000000
+#endif
+
+void __init prom_init(void)
+{
+        unsigned char *memsize_str;
+        unsigned long memsize;
+
+        prom_argc = (int)fw_arg0;
+        prom_argv = (char **)fw_arg1;
+        prom_envp = (char **)fw_arg2;
+
+        prom_init_cmdline();
+        memsize_str = prom_getenv("memsize");
+        if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
+                memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE;
+
+        add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+void prom_putchar(unsigned char c)
+{
+        alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
+}
diff --git a/arch/mips/alchemy/gpr/Makefile b/arch/mips/alchemy/gpr/Makefile
new file mode 100644
index 00000000000..cb73fe256dc
--- /dev/null
+++ b/arch/mips/alchemy/gpr/Makefile
@@ -0,0 +1,8 @@
+#
+#  Copyright 2003 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc. <source@mvista.com>
+#
+# Makefile for Trapeze ITS GPR board.
+#
+
+obj-y += board_setup.o init.o platform.o
diff --git a/arch/mips/alchemy/gpr/board_setup.c b/arch/mips/alchemy/gpr/board_setup.c
new file mode 100644
index 00000000000..5f8f0691ed2
--- /dev/null
+++ b/arch/mips/alchemy/gpr/board_setup.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
+ *
+ * Copyright 2000-2003, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+
+#include <asm/reboot.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#include <prom.h>
+
+char irq_tab_alchemy[][5] __initdata = {
+        [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff },
+};
+
+static void gpr_reset(char *c)
+{
+        /* switch System-LED to orange (red# and green# on) */
+        alchemy_gpio_direction_output(4, 0);
+        alchemy_gpio_direction_output(5, 0);
+
+        /* trigger watchdog to reset board in 200ms */
+        printk(KERN_EMERG "Triggering watchdog soft reset...\n");
+        raw_local_irq_disable();
+        alchemy_gpio_direction_output(1, 0);
+        udelay(1);
+        alchemy_gpio_set_value(1, 1);
+        while (1)
+                cpu_wait();
+}
+
+static void gpr_power_off(void)
+{
+        while (1)
+                cpu_wait();
+}
+
+void __init board_setup(void)
+{
+        printk(KERN_INFO "Trapeze ITS GPR board\n");
+
+        pm_power_off = gpr_power_off;
+        _machine_halt = gpr_power_off;
+        _machine_restart = gpr_reset;
+
+        /* Enable UART1/3 */
+        alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
+        alchemy_uart_enable(AU1000_UART1_PHYS_ADDR);
+
+        /* Take away Reset of UMTS-card */
+        alchemy_gpio_direction_output(215, 1);
+
+#ifdef CONFIG_PCI
+#if defined(__MIPSEB__)
+        au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
+#else
+        au_writel(0xf, Au1500_PCI_CFG);
+#endif
+#endif
+}
diff --git a/arch/mips/alchemy/gpr/init.c b/arch/mips/alchemy/gpr/init.c
new file mode 100644
index 00000000000..229aafae680
--- /dev/null
+++ b/arch/mips/alchemy/gpr/init.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2010 Wolfgang Grandegger <wg@denx.de>
+ *
+ * Copyright 2003, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <asm/bootinfo.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#include <prom.h>
+
+const char *get_system_type(void)
+{
+        return "GPR";
+}
+
+void __init prom_init(void)
+{
+        unsigned char *memsize_str;
+        unsigned long memsize;
+
+        prom_argc = fw_arg0;
+        prom_argv = (char **)fw_arg1;
+        prom_envp = (char **)fw_arg2;
+
+        prom_init_cmdline();
+
+        memsize_str = prom_getenv("memsize");
+        if (!memsize_str)
+                memsize = 0x04000000;
+        else
+                strict_strtoul(memsize_str, 0, &memsize);
+        add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+void prom_putchar(unsigned char c)
+{
+        alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
+}
diff --git a/arch/mips/alchemy/gpr/platform.c b/arch/mips/alchemy/gpr/platform.c
new file mode 100644
index 00000000000..14b46629cfc
--- /dev/null
+++ b/arch/mips/alchemy/gpr/platform.c
@@ -0,0 +1,183 @@
+/*
+ * GPR board platform device registration
+ *
+ * Copyright (C) 2010 Wolfgang Grandegger <wg@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/i2c-gpio.h>
+
+#include <asm/mach-au1x00/au1000.h>
+
+/*
+ * Watchdog
+ */
+static struct resource gpr_wdt_resource[] = {
+        [0] = {
+                .start  = 1,
+                .end    = 1,
+                .name   = "gpr-adm6320-wdt",
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device gpr_wdt_device = {
+        .name = "adm6320-wdt",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(gpr_wdt_resource),
+        .resource = gpr_wdt_resource,
+};
+
+/*
+ * FLASH
+ *
+ * 0x00000000-0x00200000 : "kernel"
+ * 0x00200000-0x00a00000 : "rootfs"
+ * 0x01d00000-0x01f00000 : "config"
+ * 0x01c00000-0x01d00000 : "yamon"
+ * 0x01d00000-0x01d40000 : "yamon env vars"
+ * 0x00000000-0x00a00000 : "kernel+rootfs"
+ */
+static struct mtd_partition gpr_mtd_partitions[] = {
+        {
+                .name   = "kernel",
+                .size   = 0x00200000,
+                .offset = 0,
+        },
+        {
+                .name   = "rootfs",
+                .size   = 0x00800000,
+                .offset = MTDPART_OFS_APPEND,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        {
+                .name   = "config",
+                .size   = 0x00200000,
+                .offset = 0x01d00000,
+        },
+        {
+                .name   = "yamon",
+                .size   = 0x00100000,
+                .offset = 0x01c00000,
+        },
+        {
+                .name   = "yamon env vars",
+                .size   = 0x00040000,
+                .offset = MTDPART_OFS_APPEND,
+        },
+        {
+                .name   = "kernel+rootfs",
+                .size   = 0x00a00000,
+                .offset = 0,
+        },
+};
+
+static struct physmap_flash_data gpr_flash_data = {
+        .width          = 4,
+        .nr_parts       = ARRAY_SIZE(gpr_mtd_partitions),
+        .parts          = gpr_mtd_partitions,
+};
+
+static struct resource gpr_mtd_resource = {
+        .start  = 0x1e000000,
+        .end    = 0x1fffffff,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device gpr_mtd_device = {
+        .name           = "physmap-flash",
+        .dev            = {
+                .platform_data  = &gpr_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &gpr_mtd_resource,
+};
+
+/*
+ * LEDs
+ */
+static struct gpio_led gpr_gpio_leds[] = {
+        {       /* green */
+                .name                   = "gpr:green",
+                .gpio                   = 4,
+                .active_low             = 1,
+        },
+        {       /* red */
+                .name                   = "gpr:red",
+                .gpio                   = 5,
+                .active_low             = 1,
+        }
+};
+
+static struct gpio_led_platform_data gpr_led_data = {
+        .num_leds = ARRAY_SIZE(gpr_gpio_leds),
+        .leds = gpr_gpio_leds,
+};
+
+static struct platform_device gpr_led_devices = {
+        .name = "leds-gpio",
+        .id = -1,
+        .dev = {
+                .platform_data = &gpr_led_data,
+        }
+};
+
+/*
+ * I2C
+ */
+static struct i2c_gpio_platform_data gpr_i2c_data = {
+        .sda_pin                = 209,
+        .sda_is_open_drain      = 1,
+        .scl_pin                = 210,
+        .scl_is_open_drain      = 1,
+        .udelay                 = 2,            /* ~100 kHz */
+        .timeout                = HZ,
+ };
+
+static struct platform_device gpr_i2c_device = {
+        .name                   = "i2c-gpio",
+        .id                     = -1,
+        .dev.platform_data      = &gpr_i2c_data,
+};
+
+static struct i2c_board_info gpr_i2c_info[] __initdata = {
+        {
+                I2C_BOARD_INFO("lm83", 0x18),
+                .type = "lm83"
+        }
+};
+
+static struct platform_device *gpr_devices[] __initdata = {
+        &gpr_wdt_device,
+        &gpr_mtd_device,
+        &gpr_i2c_device,
+        &gpr_led_devices,
+};
+
+static int __init gpr_dev_init(void)
+{
+        i2c_register_board_info(0, gpr_i2c_info, ARRAY_SIZE(gpr_i2c_info));
+
+        return platform_add_devices(gpr_devices, ARRAY_SIZE(gpr_devices));
+}
+device_initcall(gpr_dev_init);
diff --git a/arch/mips/alchemy/mtx-1/Makefile b/arch/mips/alchemy/mtx-1/Makefile
new file mode 100644
index 00000000000..81b540ceaf8
--- /dev/null
+++ b/arch/mips/alchemy/mtx-1/Makefile
@@ -0,0 +1,9 @@
+#
+#  Copyright 2003 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc. <source@mvista.com>
+#       Bruno Randolf <bruno.randolf@4g-systems.biz>
+#
+# Makefile for 4G Systems MTX-1 board.
+#
+
+obj-y += init.o board_setup.o platform.o
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
new file mode 100644
index 00000000000..3ae984cf98c
--- /dev/null
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -0,0 +1,134 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      4G Systems MTX-1 board setup.
+ *
+ * Copyright 2003, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *         Bruno Randolf <bruno.randolf@4g-systems.biz>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/pm.h>
+
+#include <asm/reboot.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#include <prom.h>
+
+char irq_tab_alchemy[][5] __initdata = {
+        [0] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 00 - AdapterA-Slot0 (top) */
+        [1] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 01 - AdapterA-Slot1 (bottom) */
+        [2] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 02 - AdapterB-Slot0 (top) */
+        [3] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 03 - AdapterB-Slot1 (bottom) */
+        [4] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, 0xff, 0xff }, /* IDSEL 04 - AdapterC-Slot0 (top) */
+        [5] = { -1, AU1500_PCI_INTB, AU1500_PCI_INTA, 0xff, 0xff }, /* IDSEL 05 - AdapterC-Slot1 (bottom) */
+        [6] = { -1, AU1500_PCI_INTC, AU1500_PCI_INTD, 0xff, 0xff }, /* IDSEL 06 - AdapterD-Slot0 (top) */
+        [7] = { -1, AU1500_PCI_INTD, AU1500_PCI_INTC, 0xff, 0xff }, /* IDSEL 07 - AdapterD-Slot1 (bottom) */
+};
+
+extern int (*board_pci_idsel)(unsigned int devsel, int assert);
+int mtx1_pci_idsel(unsigned int devsel, int assert);
+
+static void mtx1_reset(char *c)
+{
+        /* Jump to the reset vector */
+        __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
+}
+
+static void mtx1_power_off(void)
+{
+        while (1)
+                asm volatile (
+                "       .set    mips32                                  \n"
+                "       wait                                            \n"
+                "       .set    mips0                                   \n");
+}
+
+void __init board_setup(void)
+{
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+        /* Enable USB power switch */
+        alchemy_gpio_direction_output(204, 0);
+#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
+
+#ifdef CONFIG_PCI
+#if defined(__MIPSEB__)
+        au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
+#else
+        au_writel(0xf, Au1500_PCI_CFG);
+#endif
+        board_pci_idsel = mtx1_pci_idsel;
+#endif
+
+        /* Initialize sys_pinfunc */
+        au_writel(SYS_PF_NI2, SYS_PINFUNC);
+
+        /* Initialize GPIO */
+        au_writel(~0, KSEG1ADDR(AU1000_SYS_PHYS_ADDR) + SYS_TRIOUTCLR);
+        alchemy_gpio_direction_output(0, 0);    /* Disable M66EN (PCI 66MHz) */
+        alchemy_gpio_direction_output(3, 1);    /* Disable PCI CLKRUN# */
+        alchemy_gpio_direction_output(1, 1);    /* Enable EXT_IO3 */
+        alchemy_gpio_direction_output(5, 0);    /* Disable eth PHY TX_ER */
+
+        /* Enable LED and set it to green */
+        alchemy_gpio_direction_output(211, 1);  /* green on */
+        alchemy_gpio_direction_output(212, 0);  /* red off */
+
+        pm_power_off = mtx1_power_off;
+        _machine_halt = mtx1_power_off;
+        _machine_restart = mtx1_reset;
+
+        printk(KERN_INFO "4G Systems MTX-1 Board\n");
+}
+
+int
+mtx1_pci_idsel(unsigned int devsel, int assert)
+{
+        /* This function is only necessary to support a proprietary Cardbus
+         * adapter on the mtx-1 "singleboard" variant. It triggers a custom
+         * logic chip connected to EXT_IO3 (GPIO1) to suppress IDSEL signals.
+         */
+        if (assert && devsel != 0)
+                /* Suppress signal to Cardbus */
+                alchemy_gpio_set_value(1, 0);   /* set EXT_IO3 OFF */
+        else
+                alchemy_gpio_set_value(1, 1);   /* set EXT_IO3 ON */
+
+        udelay(1);
+        return 1;
+}
+
+static int __init mtx1_init_irq(void)
+{
+        irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
+        irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
+
+        return 0;
+}
+arch_initcall(mtx1_init_irq);
diff --git a/arch/mips/alchemy/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c
new file mode 100644
index 00000000000..2e81cc7f342
--- /dev/null
+++ b/arch/mips/alchemy/mtx-1/init.c
@@ -0,0 +1,66 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *      4G Systems MTX-1 board setup
+ *
+ * Copyright 2003, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *         Bruno Randolf <bruno.randolf@4g-systems.biz>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/bootinfo.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#include <prom.h>
+
+const char *get_system_type(void)
+{
+        return "MTX-1";
+}
+
+void __init prom_init(void)
+{
+        unsigned char *memsize_str;
+        unsigned long memsize;
+
+        prom_argc = fw_arg0;
+        prom_argv = (char **)fw_arg1;
+        prom_envp = (char **)fw_arg2;
+
+        prom_init_cmdline();
+
+        memsize_str = prom_getenv("memsize");
+        if (!memsize_str)
+                memsize = 0x04000000;
+        else
+                strict_strtoul(memsize_str, 0, &memsize);
+        add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+void prom_putchar(unsigned char c)
+{
+        alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
+}
diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c
new file mode 100644
index 00000000000..55628e390fd
--- /dev/null
+++ b/arch/mips/alchemy/mtx-1/platform.c
@@ -0,0 +1,168 @@
+/*
+ * MTX-1 platform devices registration
+ *
+ * Copyright (C) 2007-2009, Florian Fainelli <florian@openwrt.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <mtd/mtd-abi.h>
+
+#include <asm/mach-au1x00/au1xxx_eth.h>
+
+static struct gpio_keys_button mtx1_gpio_button[] = {
+        {
+                .gpio = 207,
+                .code = BTN_0,
+                .desc = "System button",
+        }
+};
+
+static struct gpio_keys_platform_data mtx1_buttons_data = {
+        .buttons = mtx1_gpio_button,
+        .nbuttons = ARRAY_SIZE(mtx1_gpio_button),
+};
+
+static struct platform_device mtx1_button = {
+        .name = "gpio-keys",
+        .id = -1,
+        .dev = {
+                .platform_data = &mtx1_buttons_data,
+        }
+};
+
+static struct resource mtx1_wdt_res[] = {
+        [0] = {
+                .start  = 215,
+                .end    = 215,
+                .name   = "mtx1-wdt-gpio",
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+
+static struct platform_device mtx1_wdt = {
+        .name = "mtx1-wdt",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mtx1_wdt_res),
+        .resource = mtx1_wdt_res,
+};
+
+static struct gpio_led default_leds[] = {
+        {
+                .name   = "mtx1:green",
+                .gpio = 211,
+        }, {
+                .name = "mtx1:red",
+                .gpio = 212,
+        },
+};
+
+static struct gpio_led_platform_data mtx1_led_data = {
+        .num_leds = ARRAY_SIZE(default_leds),
+        .leds = default_leds,
+};
+
+static struct platform_device mtx1_gpio_leds = {
+        .name = "leds-gpio",
+        .id = -1,
+        .dev = {
+                .platform_data = &mtx1_led_data,
+        }
+};
+
+static struct mtd_partition mtx1_mtd_partitions[] = {
+        {
+                .name   = "filesystem",
+                .size   = 0x01C00000,
+                .offset = 0,
+        },
+        {
+                .name   = "yamon",
+                .size   = 0x00100000,
+                .offset = MTDPART_OFS_APPEND,
+                .mask_flags = MTD_WRITEABLE,
+        },
+        {
+                .name   = "kernel",
+                .size   = 0x002c0000,
+                .offset = MTDPART_OFS_APPEND,
+        },
+        {
+                .name   = "yamon env",
+                .size   = 0x00040000,
+                .offset = MTDPART_OFS_APPEND,
+        },
+};
+
+static struct physmap_flash_data mtx1_flash_data = {
+        .width          = 4,
+        .nr_parts       = 4,
+        .parts          = mtx1_mtd_partitions,
+};
+
+static struct resource mtx1_mtd_resource = {
+        .start  = 0x1e000000,
+        .end    = 0x1fffffff,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device mtx1_mtd = {
+        .name           = "physmap-flash",
+        .dev            = {
+                .platform_data  = &mtx1_flash_data,
+        },
+        .num_resources  = 1,
+        .resource       = &mtx1_mtd_resource,
+};
+
+static struct __initdata platform_device * mtx1_devs[] = {
+        &mtx1_gpio_leds,
+        &mtx1_wdt,
+        &mtx1_button,
+        &mtx1_mtd,
+};
+
+static struct au1000_eth_platform_data mtx1_au1000_eth0_pdata = {
+        .phy_search_highest_addr        = 1,
+        .phy1_search_mac0               = 1,
+};
+
+static int __init mtx1_register_devices(void)
+{
+        int rc;
+
+        au1xxx_override_eth_cfg(0, &mtx1_au1000_eth0_pdata);
+
+        rc = gpio_request(mtx1_gpio_button[0].gpio,
+                                        mtx1_gpio_button[0].desc);
+        if (rc < 0) {
+                printk(KERN_INFO "mtx1: failed to request %d\n",
+                                        mtx1_gpio_button[0].gpio);
+                goto out;
+        }
+        gpio_direction_input(mtx1_gpio_button[0].gpio);
+out:
+        return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs));
+}
+
+arch_initcall(mtx1_register_devices);
diff --git a/arch/mips/alchemy/xxs1500/Makefile b/arch/mips/alchemy/xxs1500/Makefile
new file mode 100644
index 00000000000..91defcf4f33
--- /dev/null
+++ b/arch/mips/alchemy/xxs1500/Makefile
@@ -0,0 +1,8 @@
+#
+#  Copyright 2003 MontaVista Software Inc.
+#  Author: MontaVista Software, Inc. <source@mvista.com>
+#
+# Makefile for MyCable XXS1500 board.
+#
+
+obj-y += init.o board_setup.o platform.o
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
new file mode 100644
index 00000000000..81e57fad07a
--- /dev/null
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2000-2003, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+
+#include <asm/reboot.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#include <prom.h>
+
+static void xxs1500_reset(char *c)
+{
+        /* Jump to the reset vector */
+        __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
+}
+
+static void xxs1500_power_off(void)
+{
+        while (1)
+                asm volatile (
+                "       .set    mips32                                  \n"
+                "       wait                                            \n"
+                "       .set    mips0                                   \n");
+}
+
+void __init board_setup(void)
+{
+        u32 pin_func;
+
+        pm_power_off = xxs1500_power_off;
+        _machine_halt = xxs1500_power_off;
+        _machine_restart = xxs1500_reset;
+
+        alchemy_gpio1_input_enable();
+        alchemy_gpio2_enable();
+
+        /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
+        pin_func  = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
+        pin_func |= SYS_PF_UR3;
+        au_writel(pin_func, SYS_PINFUNC);
+
+        /* Enable UART */
+        alchemy_uart_enable(AU1000_UART3_PHYS_ADDR);
+        /* Enable DTR (MCR bit 0) = USB power up */
+        __raw_writel(1, (void __iomem *)KSEG1ADDR(AU1000_UART3_PHYS_ADDR + 0x18));
+        wmb();
+
+#ifdef CONFIG_PCI
+#if defined(__MIPSEB__)
+        au_writel(0xf | (2 << 6) | (1 << 4), Au1500_PCI_CFG);
+#else
+        au_writel(0xf, Au1500_PCI_CFG);
+#endif
+#endif
+}
+
+static int __init xxs1500_init_irq(void)
+{
+        irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
+        irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
+
+        irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
+        irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
+
+        return 0;
+}
+arch_initcall(xxs1500_init_irq);
diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c
new file mode 100644
index 00000000000..0ee02cfa989
--- /dev/null
+++ b/arch/mips/alchemy/xxs1500/init.c
@@ -0,0 +1,63 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *      XXS1500 board setup
+ *
+ * Copyright 2003, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+
+#include <asm/bootinfo.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#include <prom.h>
+
+const char *get_system_type(void)
+{
+        return "XXS1500";
+}
+
+void __init prom_init(void)
+{
+        unsigned char *memsize_str;
+        unsigned long memsize;
+
+        prom_argc = fw_arg0;
+        prom_argv = (char **)fw_arg1;
+        prom_envp = (char **)fw_arg2;
+
+        prom_init_cmdline();
+
+        memsize_str = prom_getenv("memsize");
+        if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
+                memsize = 0x04000000;
+
+        add_memory_region(0, memsize, BOOT_MEM_RAM);
+}
+
+void prom_putchar(unsigned char c)
+{
+        alchemy_uart_putchar(AU1000_UART0_PHYS_ADDR, c);
+}
diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c
new file mode 100644
index 00000000000..e87c45cde61
--- /dev/null
+++ b/arch/mips/alchemy/xxs1500/platform.c
@@ -0,0 +1,63 @@
+/*
+ * XXS1500 board platform device registration
+ *
+ * Copyright (C) 2009 Manuel Lauss
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-au1x00/au1000.h>
+
+static struct resource xxs1500_pcmcia_res[] = {
+        {
+                .name   = "pcmcia-io",
+                .flags  = IORESOURCE_MEM,
+                .start  = PCMCIA_IO_PHYS_ADDR,
+                .end    = PCMCIA_IO_PHYS_ADDR + 0x000400000 - 1,
+        },
+        {
+                .name   = "pcmcia-attr",
+                .flags  = IORESOURCE_MEM,
+                .start  = PCMCIA_ATTR_PHYS_ADDR,
+                .end    = PCMCIA_ATTR_PHYS_ADDR + 0x000400000 - 1,
+        },
+        {
+                .name   = "pcmcia-mem",
+                .flags  = IORESOURCE_MEM,
+                .start  = PCMCIA_MEM_PHYS_ADDR,
+                .end    = PCMCIA_MEM_PHYS_ADDR + 0x000400000 - 1,
+        },
+};
+
+static struct platform_device xxs1500_pcmcia_dev = {
+        .name           = "xxs1500_pcmcia",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(xxs1500_pcmcia_res),
+        .resource       = xxs1500_pcmcia_res,
+};
+
+static struct platform_device *xxs1500_devs[] __initdata = {
+        &xxs1500_pcmcia_dev,
+};
+
+static int __init xxs1500_dev_init(void)
+{
+        return platform_add_devices(xxs1500_devs,
+                                    ARRAY_SIZE(xxs1500_devs));
+}
+device_initcall(xxs1500_dev_init);
diff --git a/arch/mips/ath79/dev-ar913x-wmac.c b/arch/mips/ath79/dev-ar913x-wmac.c
new file mode 100644
index 00000000000..48f425a5ba2
--- /dev/null
+++ b/arch/mips/ath79/dev-ar913x-wmac.c
@@ -0,0 +1,60 @@
+/*
+ *  Atheros AR913X SoC built-in WMAC device support
+ *
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/ath9k_platform.h>
+
+#include <asm/mach-ath79/ath79.h>
+#include <asm/mach-ath79/ar71xx_regs.h>
+#include "dev-ar913x-wmac.h"
+
+static struct ath9k_platform_data ar913x_wmac_data;
+
+static struct resource ar913x_wmac_resources[] = {
+        {
+                .start  = AR913X_WMAC_BASE,
+                .end    = AR913X_WMAC_BASE + AR913X_WMAC_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = ATH79_CPU_IRQ_IP2,
+                .end    = ATH79_CPU_IRQ_IP2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device ar913x_wmac_device = {
+        .name           = "ath9k",
+        .id             = -1,
+        .resource       = ar913x_wmac_resources,
+        .num_resources  = ARRAY_SIZE(ar913x_wmac_resources),
+        .dev = {
+                .platform_data = &ar913x_wmac_data,
+        },
+};
+
+void __init ath79_register_ar913x_wmac(u8 *cal_data)
+{
+        if (cal_data)
+                memcpy(ar913x_wmac_data.eeprom_data, cal_data,
+                       sizeof(ar913x_wmac_data.eeprom_data));
+
+        /* reset the WMAC */
+        ath79_device_reset_set(AR913X_RESET_AMBA2WMAC);
+        mdelay(10);
+
+        ath79_device_reset_clear(AR913X_RESET_AMBA2WMAC);
+        mdelay(10);
+
+        platform_device_register(&ar913x_wmac_device);
+}
diff --git a/arch/mips/ath79/dev-ar913x-wmac.h b/arch/mips/ath79/dev-ar913x-wmac.h
new file mode 100644
index 00000000000..579d562bbda
--- /dev/null
+++ b/arch/mips/ath79/dev-ar913x-wmac.h
@@ -0,0 +1,17 @@
+/*
+ *  Atheros AR913X SoC built-in WMAC device support
+ *
+ *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
+ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
+#ifndef _ATH79_DEV_AR913X_WMAC_H
+#define _ATH79_DEV_AR913X_WMAC_H
+
+void ath79_register_ar913x_wmac(u8 *cal_data);
+
+#endif /* _ATH79_DEV_AR913X_WMAC_H */
diff --git a/arch/mips/bcm47xx/gpio.c b/arch/mips/bcm47xx/gpio.c
new file mode 100644
index 00000000000..e4a5ee9c972
--- /dev/null
+++ b/arch/mips/bcm47xx/gpio.c
@@ -0,0 +1,61 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
+ */
+
+#include <linux/ssb/ssb.h>
+#include <linux/ssb/ssb_driver_chipcommon.h>
+#include <linux/ssb/ssb_driver_extif.h>
+#include <asm/mach-bcm47xx/bcm47xx.h>
+#include <asm/mach-bcm47xx/gpio.h>
+
+#if (BCM47XX_CHIPCO_GPIO_LINES > BCM47XX_EXTIF_GPIO_LINES)
+static DECLARE_BITMAP(gpio_in_use, BCM47XX_CHIPCO_GPIO_LINES);
+#else
+static DECLARE_BITMAP(gpio_in_use, BCM47XX_EXTIF_GPIO_LINES);
+#endif
+
+int gpio_request(unsigned gpio, const char *tag)
+{
+        if (ssb_chipco_available(&ssb_bcm47xx.chipco) &&
+            ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
+                return -EINVAL;
+
+        if (ssb_extif_available(&ssb_bcm47xx.extif) &&
+            ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES))
+                return -EINVAL;
+
+        if (test_and_set_bit(gpio, gpio_in_use))
+                return -EBUSY;
+
+        return 0;
+}
+EXPORT_SYMBOL(gpio_request);
+
+void gpio_free(unsigned gpio)
+{
+        if (ssb_chipco_available(&ssb_bcm47xx.chipco) &&
+            ((unsigned)gpio >= BCM47XX_CHIPCO_GPIO_LINES))
+                return;
+
+        if (ssb_extif_available(&ssb_bcm47xx.extif) &&
+            ((unsigned)gpio >= BCM47XX_EXTIF_GPIO_LINES))
+                return;
+
+        clear_bit(gpio, gpio_in_use);
+}
+EXPORT_SYMBOL(gpio_free);
+
+int gpio_to_irq(unsigned gpio)
+{
+        if (ssb_chipco_available(&ssb_bcm47xx.chipco))
+                return ssb_mips_irq(ssb_bcm47xx.chipco.dev) + 2;
+        else if (ssb_extif_available(&ssb_bcm47xx.extif))
+                return ssb_mips_irq(ssb_bcm47xx.extif.dev) + 2;
+        else
+                return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(gpio_to_irq);
diff --git a/arch/mips/configs/cavium-octeon_defconfig b/arch/mips/configs/cavium-octeon_defconfig
new file mode 100644
index 00000000000..75165dfa60c
--- /dev/null
+++ b/arch/mips/configs/cavium-octeon_defconfig
@@ -0,0 +1,93 @@
+CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y
+CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SMP=y
+CONFIG_PREEMPT=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EXPERT=y
+# CONFIG_PCSPKR_PLATFORM is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_MIPS32_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_FW_LOADER is not set
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_MISC_DEVICES is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+# CONFIG_USB_SUPPORT is not set
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_EARLY_PRINTK is not set
+CONFIG_SECURITY=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig
new file mode 100644
index 00000000000..c6b49938ee8
--- /dev/null
+++ b/arch/mips/configs/db1100_defconfig
@@ -0,0 +1,122 @@
+CONFIG_MIPS_ALCHEMY=y
+CONFIG_MIPS_DB1100=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_100=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCALVERSION="-db1100"
+CONFIG_KERNEL_LZMA=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_TINY_RCU=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_EXPERT=y
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
+# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_PCCARD=y
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
+CONFIG_PM=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_BLK_DEV is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_IDE=y
+CONFIG_IDE_TASK_IOCTL=y
+CONFIG_NETDEVICES=y
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MIPS_AU1X00_ENET=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+CONFIG_FB=y
+CONFIG_FB_AU1100=y
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x16=y
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AU1XXX=y
+CONFIG_EXT2_FS=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_ZBOOT=y
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITYFS=y
diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
new file mode 100644
index 00000000000..1f69249b839
--- /dev/null
+++ b/arch/mips/configs/db1200_defconfig
@@ -0,0 +1,170 @@
+CONFIG_MIPS_ALCHEMY=y
+CONFIG_MIPS_DB1200=y
+CONFIG_KSM=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_100=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCALVERSION="-db1200"
+CONFIG_KERNEL_LZMA=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_TINY_RCU=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_EXPERT=y
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
+# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_PCCARD=y
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_UB=y
+# CONFIG_MISC_DEVICES is not set
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDECS=y
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_IDE_TASK_IOCTL=y
+# CONFIG_IDE_PROC_FS is not set
+CONFIG_BLK_DEV_IDE_AU1XXX=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMC91X=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_AU1550=y
+CONFIG_SPI=y
+CONFIG_SPI_AU1550=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_SENSORS_ADM1025=y
+CONFIG_SENSORS_LM70=y
+CONFIG_FB=y
+CONFIG_FB_AU1200=y
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x16=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_MIPS is not set
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AU1XPSC=y
+CONFIG_SND_SOC_DB1200=y
+CONFIG_HIDRAW=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_AU1X=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AU1XXX=y
+CONFIG_EXT2_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_VFAT_FS=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_UTF8=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS0,115200"
+CONFIG_DEBUG_ZBOOT=y
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITYFS=y
diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig
new file mode 100644
index 00000000000..b6e21c7cb6b
--- /dev/null
+++ b/arch/mips/configs/db1500_defconfig
@@ -0,0 +1,128 @@
+CONFIG_MIPS_ALCHEMY=y
+CONFIG_MIPS_DB1500=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_100=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCALVERSION="-db1500"
+CONFIG_KERNEL_LZMA=y
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_EXPERT=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_PCI=y
+CONFIG_PCCARD=y
+# CONFIG_CARDBUS is not set
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
+CONFIG_PM=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MISC_DEVICES is not set
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDECS=y
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
+CONFIG_BLK_DEV_HPT366=y
+CONFIG_NETDEVICES=y
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MIPS_AU1X00_ENET=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_VGA_ARB is not set
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AU1XXX=y
+CONFIG_EXT2_FS=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_UTF8=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_ZBOOT=y
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITYFS=y
diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig
new file mode 100644
index 00000000000..798a553c9e8
--- /dev/null
+++ b/arch/mips/configs/db1550_defconfig
@@ -0,0 +1,157 @@
+CONFIG_MIPS_ALCHEMY=y
+CONFIG_MIPS_DB1550=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_100=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCALVERSION="-db1550"
+CONFIG_KERNEL_LZMA=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_TINY_RCU=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_EXPERT=y
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
+# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_PCI=y
+CONFIG_PCCARD=y
+# CONFIG_CARDBUS is not set
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
+CONFIG_PM=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_AU1550=y
+CONFIG_BLK_DEV_UB=y
+# CONFIG_MISC_DEVICES is not set
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDECS=y
+CONFIG_BLK_DEV_IDECD=y
+# CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS is not set
+CONFIG_IDE_TASK_IOCTL=y
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
+CONFIG_BLK_DEV_HPT366=y
+CONFIG_NETDEVICES=y
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MIPS_AU1X00_ENET=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_AU1550=y
+CONFIG_SPI=y
+CONFIG_SPI_AU1550=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_ARB is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_HRTIMER=y
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_PCI is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_MIPS is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AU1XPSC=y
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AU1XXX=y
+CONFIG_EXT2_FS=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+# CONFIG_JFFS2_FS_POSIX_ACL is not set
+# CONFIG_JFFS2_FS_SECURITY is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_UTF8=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_ZBOOT=y
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITYFS=y
diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig
new file mode 100644
index 00000000000..b5ad7387bbb
--- /dev/null
+++ b/arch/mips/configs/mipssim_defconfig
@@ -0,0 +1,64 @@
+CONFIG_MIPS_SIM=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_HZ_100=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EXPERT=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_STANDALONE is not set
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NBD=y
+# CONFIG_MISC_DEVICES is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MIPS_SIM_NET=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_DNOTIFY is not set
+CONFIG_TMPFS=y
+CONFIG_ROMFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="nfsroot=192.168.192.169:/u1/mipsel,timeo=20 ip=dhcp"
+# CONFIG_CRC32 is not set
diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig
new file mode 100644
index 00000000000..75eb1b1f316
--- /dev/null
+++ b/arch/mips/configs/pb1100_defconfig
@@ -0,0 +1,124 @@
+CONFIG_MIPS_ALCHEMY=y
+CONFIG_MIPS_PB1100=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_100=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCALVERSION="-pb1100"
+CONFIG_KERNEL_LZMA=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_TINY_RCU=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_EXPERT=y
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
+# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_PCCARD=y
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
+CONFIG_PM=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_UB=y
+# CONFIG_MISC_DEVICES is not set
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDECS=y
+CONFIG_IDE_TASK_IOCTL=y
+# CONFIG_IDE_PROC_FS is not set
+CONFIG_NETDEVICES=y
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MIPS_AU1X00_ENET=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_HIDRAW=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AU1XXX=y
+CONFIG_EXT2_FS=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+# CONFIG_JFFS2_FS_POSIX_ACL is not set
+# CONFIG_JFFS2_FS_SECURITY is not set
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_ZBOOT=y
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITYFS=y
diff --git a/arch/mips/configs/pb1200_defconfig b/arch/mips/configs/pb1200_defconfig
new file mode 100644
index 00000000000..dcbe2704e5e
--- /dev/null
+++ b/arch/mips/configs/pb1200_defconfig
@@ -0,0 +1,170 @@
+CONFIG_MIPS_ALCHEMY=y
+CONFIG_MIPS_PB1200=y
+CONFIG_KSM=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_100=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCALVERSION="-pb1200"
+CONFIG_KERNEL_LZMA=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_TINY_RCU=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_EXPERT=y
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
+# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_PCCARD=y
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_UB=y
+# CONFIG_MISC_DEVICES is not set
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDECS=y
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_IDE_TASK_IOCTL=y
+# CONFIG_IDE_PROC_FS is not set
+CONFIG_BLK_DEV_IDE_AU1XXX=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMC91X=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_AU1550=y
+CONFIG_SPI=y
+CONFIG_SPI_AU1550=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_SENSORS_ADM1025=y
+CONFIG_SENSORS_LM70=y
+CONFIG_FB=y
+CONFIG_FB_AU1200=y
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x16=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_MIPS is not set
+# CONFIG_SND_USB is not set
+# CONFIG_SND_PCMCIA is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AU1XPSC=y
+CONFIG_SND_SOC_DB1200=y
+CONFIG_HIDRAW=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_AU1X=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AU1XXX=y
+CONFIG_EXT2_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_VFAT_FS=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_UTF8=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS0,115200"
+CONFIG_DEBUG_ZBOOT=y
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITYFS=y
diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig
new file mode 100644
index 00000000000..fa00487146f
--- /dev/null
+++ b/arch/mips/configs/pb1500_defconfig
@@ -0,0 +1,141 @@
+CONFIG_MIPS_ALCHEMY=y
+CONFIG_MIPS_PB1500=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_100=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCALVERSION="-pb1500"
+CONFIG_KERNEL_LZMA=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_TINY_RCU=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_EXPERT=y
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
+# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_PCI=y
+CONFIG_PCCARD=y
+# CONFIG_CARDBUS is not set
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
+CONFIG_PM=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_UB=y
+# CONFIG_MISC_DEVICES is not set
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDECS=y
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_IDE_TASK_IOCTL=y
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
+CONFIG_BLK_DEV_HPT366=y
+CONFIG_NETDEVICES=y
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MIPS_AU1X00_ENET=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+# CONFIG_VGA_ARB is not set
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+CONFIG_FB_S1D13XXX=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_OTG_WHITELIST=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AU1XXX=y
+CONFIG_EXT2_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_VFAT_FS=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_UTF8=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_ZBOOT=y
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITYFS=y
diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig
new file mode 100644
index 00000000000..e83d6497e8b
--- /dev/null
+++ b/arch/mips/configs/pb1550_defconfig
@@ -0,0 +1,145 @@
+CONFIG_MIPS_ALCHEMY=y
+CONFIG_MIPS_PB1550=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_100=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCALVERSION="-pb1550"
+CONFIG_KERNEL_LZMA=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_TINY_RCU=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_EXPERT=y
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_KALLSYMS is not set
+# CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_PCI=y
+CONFIG_PCCARD=y
+# CONFIG_CARDBUS is not set
+CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y
+CONFIG_PM=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_AU1550=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_UB=y
+# CONFIG_MISC_DEVICES is not set
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDECS=y
+CONFIG_BLK_DEV_IDECD=y
+# CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS is not set
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
+CONFIG_BLK_DEV_HPT366=y
+CONFIG_NETDEVICES=y
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MIPS_AU1X00_ENET=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_AU1550=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_ARB is not set
+CONFIG_HIDRAW=y
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DYNAMIC_MINORS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AU1XXX=y
+CONFIG_EXT2_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_VFAT_FS=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RUBIN=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_UTF8=y
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_ZBOOT=y
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITYFS=y
diff --git a/arch/mips/configs/pnx8335-stb225_defconfig b/arch/mips/configs/pnx8335-stb225_defconfig
new file mode 100644
index 00000000000..f2925769dfa
--- /dev/null
+++ b/arch/mips/configs/pnx8335-stb225_defconfig
@@ -0,0 +1,98 @@
+CONFIG_NXP_STB225=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_128=y
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_EXPERT=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_PM=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_INET_AH=y
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_LE_BYTE_SWAP=y
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_MISC_DEVICES is not set
+CONFIG_BLK_DEV_SD=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=m
+CONFIG_INPUT_EVBUG=m
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_VT_CONSOLE is not set
+CONFIG_SERIAL_PNX8XXX=y
+CONFIG_SERIAL_PNX8XXX_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_HWMON is not set
+CONFIG_FB=y
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_SOUND=m
+CONFIG_SND=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+CONFIG_EXT2_FS=m
+# CONFIG_DNOTIFY is not set
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V3=y
+CONFIG_NLS=y
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_UTF8=m
+CONFIG_SYSCTL_SYSCALL_CHECK=y
diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig
new file mode 100644
index 00000000000..1d1f2067f3e
--- /dev/null
+++ b/arch/mips/configs/pnx8550-jbs_defconfig
@@ -0,0 +1,98 @@
+CONFIG_PNX8550_JBS=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EXPERT=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_PCI=y
+CONFIG_PM=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_TCP_MD5SIG=y
+# CONFIG_IPV6 is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_SGI_IOC4=m
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDECD=m
+CONFIG_IDE_GENERIC=y
+CONFIG_BLK_DEV_OFFBOARD=y
+CONFIG_BLK_DEV_GENERIC=y
+CONFIG_BLK_DEV_HPT366=y
+CONFIG_BLK_DEV_IT8213=m
+CONFIG_BLK_DEV_TC86C001=m
+CONFIG_SCSI=y
+CONFIG_SCSI_TGT=m
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_FC_ATTRS=y
+CONFIG_ISCSI_TCP=m
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_NET_PCI=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+CONFIG_8139TOO_TUNE_TWISTER=y
+CONFIG_8139TOO_8129=y
+CONFIG_CHELSIO_T3=m
+CONFIG_NETXEN_NIC=m
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIAL_PNX8XXX=y
+CONFIG_SERIAL_PNX8XXX_CONSOLE=y
+CONFIG_HW_RANDOM=y
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_HID is not set
+# CONFIG_USB_HID is not set
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_ISD200=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_EXT2_FS=y
+# CONFIG_DNOTIFY is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_DLM=m
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SLAB=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRC_CCITT=m
diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig
new file mode 100644
index 00000000000..15c66a571f9
--- /dev/null
+++ b/arch/mips/configs/pnx8550-stb810_defconfig
@@ -0,0 +1,92 @@
+CONFIG_PNX8550_STB810=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EXPERT=y
+# CONFIG_SYSCTL_SYSCALL is not set
+# CONFIG_HOTPLUG is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_PCI=y
+CONFIG_PM=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IPV6 is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDECD=m
+CONFIG_IDE_GENERIC=y
+CONFIG_BLK_DEV_OFFBOARD=y
+CONFIG_BLK_DEV_GENERIC=y
+CONFIG_BLK_DEV_HPT366=y
+CONFIG_BLK_DEV_IT8213=m
+CONFIG_BLK_DEV_TC86C001=m
+CONFIG_SCSI=y
+CONFIG_SCSI_TGT=m
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_ISCSI_TCP=m
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_NET_PCI=y
+CONFIG_NATSEMI=y
+CONFIG_CHELSIO_T3=m
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO_I8042 is not set
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_LIBPS2=y
+CONFIG_HW_RANDOM=y
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_HID is not set
+# CONFIG_USB_HID is not set
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_ISD200=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_EXT2_FS=y
+# CONFIG_DNOTIFY is not set
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_DLM=m
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_HEADERS_CHECK=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SLAB=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="console=ttyS1,38400n8 root=/dev/nfs ip=bootp"
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRC_CCITT=m
diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig
new file mode 100644
index 00000000000..5b0463ef938
--- /dev/null
+++ b/arch/mips/configs/sb1250-swarm_defconfig
@@ -0,0 +1,125 @@
+CONFIG_SIBYTE_SWARM=y
+CONFIG_CPU_SB1_PASS_2_2=y
+CONFIG_64BIT=y
+CONFIG_SMP=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_CGROUPS=y
+CONFIG_CPUSETS=y
+# CONFIG_PROC_PID_CPUSET is not set
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_EXPERT=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_PCI=y
+CONFIG_MIPS32_COMPAT=y
+CONFIG_MIPS32_O32=y
+CONFIG_PM=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=m
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_TCP_MD5SIG=y
+# CONFIG_IPV6 is not set
+CONFIG_NETWORK_SECMARK=y
+CONFIG_CFG80211=m
+CONFIG_MAC80211=m
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_RC_DEFAULT_PID=y
+CONFIG_RFKILL=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_FW_LOADER=m
+CONFIG_CONNECTOR=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=9220
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_ATA_OVER_ETH=m
+CONFIG_SGI_IOC4=m
+CONFIG_IDE=y
+CONFIG_BLK_DEV_IDECD=y
+CONFIG_BLK_DEV_IDETAPE=y
+CONFIG_RAID_ATTRS=m
+CONFIG_NETDEVICES=y
+CONFIG_MACVLAN=m
+CONFIG_BROADCOM_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_SB1250_MAC=y
+# CONFIG_INPUT is not set
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_RAW=m
+# CONFIG_VT is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_FUSE_FS=m
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_DLM=m
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SALSA20=m
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_LZO=m
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC16=m
diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig
new file mode 100644
index 00000000000..f72d305a3f0
--- /dev/null
+++ b/arch/mips/configs/yosemite_defconfig
@@ -0,0 +1,94 @@
+CONFIG_PMC_YOSEMITE=y
+CONFIG_HIGHMEM=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_HZ_1000=y
+CONFIG_SYSVIPC=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_RELAY=y
+CONFIG_EXPERT=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_PCI=y
+CONFIG_PM=y
+CONFIG_NET=y
+CONFIG_PACKET=m
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=m
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_TUNNEL=m
+CONFIG_NETWORK_SECMARK=y
+CONFIG_FW_LOADER=m
+CONFIG_CONNECTOR=m
+CONFIG_CDROM_PKTCDVD=m
+CONFIG_ATA_OVER_ETH=m
+CONFIG_SGI_IOC4=m
+CONFIG_RAID_ATTRS=m
+CONFIG_NETDEVICES=y
+CONFIG_PHYLIB=m
+CONFIG_MARVELL_PHY=m
+CONFIG_DAVICOM_PHY=m
+CONFIG_QSEMI_PHY=m
+CONFIG_LXT_PHY=m
+CONFIG_CICADA_PHY=m
+CONFIG_VITESSE_PHY=m
+CONFIG_SMSC_PHY=m
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_QLA3XXX=m
+CONFIG_CHELSIO_T3=m
+CONFIG_NETXEN_NIC=m
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_HWMON is not set
+CONFIG_FUSE_FS=m
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRC16=m
+CONFIG_CRC32=m
+CONFIG_LIBCRC32C=m
diff --git a/arch/mips/include/asm/auxvec.h b/arch/mips/include/asm/auxvec.h
new file mode 100644
index 00000000000..7cf7f2d2194
--- /dev/null
+++ b/arch/mips/include/asm/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef _ASM_AUXVEC_H
+#define _ASM_AUXVEC_H
+
+#endif /* _ASM_AUXVEC_H */
diff --git a/arch/mips/include/asm/bitsperlong.h b/arch/mips/include/asm/bitsperlong.h
new file mode 100644
index 00000000000..3e4c10a8e78
--- /dev/null
+++ b/arch/mips/include/asm/bitsperlong.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_MIPS_BITSPERLONG_H
+#define __ASM_MIPS_BITSPERLONG_H
+
+#define __BITS_PER_LONG _MIPS_SZLONG
+
+#include <asm-generic/bitsperlong.h>
+
+#endif /* __ASM_MIPS_BITSPERLONG_H */
diff --git a/arch/mips/include/asm/byteorder.h b/arch/mips/include/asm/byteorder.h
new file mode 100644
index 00000000000..9579051ff1c
--- /dev/null
+++ b/arch/mips/include/asm/byteorder.h
@@ -0,0 +1,19 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 99, 2003 by Ralf Baechle
+ */
+#ifndef _ASM_BYTEORDER_H
+#define _ASM_BYTEORDER_H
+
+#if defined(__MIPSEB__)
+#include <linux/byteorder/big_endian.h>
+#elif defined(__MIPSEL__)
+#include <linux/byteorder/little_endian.h>
+#else
+# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
+#endif
+
+#endif /* _ASM_BYTEORDER_H */
diff --git a/arch/mips/include/asm/cachectl.h b/arch/mips/include/asm/cachectl.h
new file mode 100644
index 00000000000..f3ce721861d
--- /dev/null
+++ b/arch/mips/include/asm/cachectl.h
@@ -0,0 +1,26 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
+ */
+#ifndef _ASM_CACHECTL
+#define _ASM_CACHECTL
+
+/*
+ * Options for cacheflush system call
+ */
+#define ICACHE  (1<<0)          /* flush instruction cache        */
+#define DCACHE  (1<<1)          /* writeback and flush data cache */
+#define BCACHE  (ICACHE|DCACHE) /* flush both caches              */
+
+/*
+ * Caching modes for the cachectl(2) call
+ *
+ * cachectl(2) is currently not supported and returns ENOSYS.
+ */
+#define CACHEABLE       0       /* make pages cacheable */
+#define UNCACHEABLE     1       /* make pages uncacheable */
+
+#endif  /* _ASM_CACHECTL */
diff --git a/arch/mips/include/asm/fcntl.h b/arch/mips/include/asm/fcntl.h
new file mode 100644
index 00000000000..75eddedcfc3
--- /dev/null
+++ b/arch/mips/include/asm/fcntl.h
@@ -0,0 +1,77 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle
+ */
+#ifndef _ASM_FCNTL_H
+#define _ASM_FCNTL_H
+
+
+#define O_APPEND        0x0008
+#define O_DSYNC         0x0010  /* used to be O_SYNC, see below */
+#define O_NONBLOCK      0x0080
+#define O_CREAT         0x0100  /* not fcntl */
+#define O_TRUNC         0x0200  /* not fcntl */
+#define O_EXCL          0x0400  /* not fcntl */
+#define O_NOCTTY        0x0800  /* not fcntl */
+#define FASYNC          0x1000  /* fcntl, for BSD compatibility */
+#define O_LARGEFILE     0x2000  /* allow large file opens */
+/*
+ * Before Linux 2.6.33 only O_DSYNC semantics were implemented, but using
+ * the O_SYNC flag.  We continue to use the existing numerical value
+ * for O_DSYNC semantics now, but using the correct symbolic name for it.
+ * This new value is used to request true Posix O_SYNC semantics.  It is
+ * defined in this strange way to make sure applications compiled against
+ * new headers get at least O_DSYNC semantics on older kernels.
+ *
+ * This has the nice side-effect that we can simply test for O_DSYNC
+ * wherever we do not care if O_DSYNC or O_SYNC is used.
+ *
+ * Note: __O_SYNC must never be used directly.
+ */
+#define __O_SYNC        0x4000
+#define O_SYNC          (__O_SYNC|O_DSYNC)
+#define O_DIRECT        0x8000  /* direct disk access hint */
+
+#define F_GETLK         14
+#define F_SETLK         6
+#define F_SETLKW        7
+
+#define F_SETOWN        24      /*  for sockets. */
+#define F_GETOWN        23      /*  for sockets. */
+
+#ifndef __mips64
+#define F_GETLK64       33      /*  using 'struct flock64' */
+#define F_SETLK64       34
+#define F_SETLKW64      35
+#endif
+
+/*
+ * The flavours of struct flock.  "struct flock" is the ABI compliant
+ * variant.  Finally struct flock64 is the LFS variant of struct flock.  As
+ * a historic accident and inconsistence with the ABI definition it doesn't
+ * contain all the same fields as struct flock.
+ */
+
+#ifdef CONFIG_32BIT
+#include <linux/types.h>
+
+struct flock {
+        short   l_type;
+        short   l_whence;
+        off_t   l_start;
+        off_t   l_len;
+        long    l_sysid;
+        __kernel_pid_t l_pid;
+        long    pad[4];
+};
+
+#define HAVE_ARCH_STRUCT_FLOCK
+
+#endif /* CONFIG_32BIT */
+
+#include <asm-generic/fcntl.h>
+
+#endif /* _ASM_FCNTL_H */
diff --git a/arch/mips/include/asm/ioctl.h b/arch/mips/include/asm/ioctl.h
new file mode 100644
index 00000000000..c515a1a4c47
--- /dev/null
+++ b/arch/mips/include/asm/ioctl.h
@@ -0,0 +1,27 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2009 Wind River Systems
+ * Written by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_IOCTL_H
+#define __ASM_IOCTL_H
+
+#define _IOC_SIZEBITS   13
+#define _IOC_DIRBITS    3
+
+/*
+ * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
+ * And this turns out useful to catch old ioctl numbers in header
+ * files for us.
+ */
+#define _IOC_NONE       1U
+#define _IOC_READ       2U
+#define _IOC_WRITE      4U
+
+#include <asm-generic/ioctl.h>
+
+#endif /* __ASM_IOCTL_H */
diff --git a/arch/mips/include/asm/ioctls.h b/arch/mips/include/asm/ioctls.h
new file mode 100644
index 00000000000..92403c3d600
--- /dev/null
+++ b/arch/mips/include/asm/ioctls.h
@@ -0,0 +1,110 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1996, 2001 Ralf Baechle
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef __ASM_IOCTLS_H
+#define __ASM_IOCTLS_H
+
+#include <asm/ioctl.h>
+
+#define TCGETA          0x5401
+#define TCSETA          0x5402  /* Clashes with SNDCTL_TMR_START sound ioctl */
+#define TCSETAW         0x5403
+#define TCSETAF         0x5404
+
+#define TCSBRK          0x5405
+#define TCXONC          0x5406
+#define TCFLSH          0x5407
+
+#define TCGETS          0x540d
+#define TCSETS          0x540e
+#define TCSETSW         0x540f
+#define TCSETSF         0x5410
+
+#define TIOCEXCL        0x740d          /* set exclusive use of tty */
+#define TIOCNXCL        0x740e          /* reset exclusive use of tty */
+#define TIOCOUTQ        0x7472          /* output queue size */
+#define TIOCSTI         0x5472          /* simulate terminal input */
+#define TIOCMGET        0x741d          /* get all modem bits */
+#define TIOCMBIS        0x741b          /* bis modem bits */
+#define TIOCMBIC        0x741c          /* bic modem bits */
+#define TIOCMSET        0x741a          /* set all modem bits */
+#define TIOCPKT         0x5470          /* pty: set/clear packet mode */
+#define  TIOCPKT_DATA           0x00    /* data packet */
+#define  TIOCPKT_FLUSHREAD      0x01    /* flush packet */
+#define  TIOCPKT_FLUSHWRITE     0x02    /* flush packet */
+#define  TIOCPKT_STOP           0x04    /* stop output */
+#define  TIOCPKT_START          0x08    /* start output */
+#define  TIOCPKT_NOSTOP         0x10    /* no more ^S, ^Q */
+#define  TIOCPKT_DOSTOP         0x20    /* now do ^S ^Q */
+#define  TIOCPKT_IOCTL          0x40    /* state change of pty driver */
+#define TIOCSWINSZ      _IOW('t', 103, struct winsize)  /* set window size */
+#define TIOCGWINSZ      _IOR('t', 104, struct winsize)  /* get window size */
+#define TIOCNOTTY       0x5471          /* void tty association */
+#define TIOCSETD        0x7401
+#define TIOCGETD        0x7400
+
+#define FIOCLEX         0x6601
+#define FIONCLEX        0x6602
+#define FIOASYNC        0x667d
+#define FIONBIO         0x667e
+#define FIOQSIZE        0x667f
+
+#define TIOCGLTC        0x7474                  /* get special local chars */
+#define TIOCSLTC        0x7475                  /* set special local chars */
+#define TIOCSPGRP       _IOW('t', 118, int)     /* set pgrp of tty */
+#define TIOCGPGRP       _IOR('t', 119, int)     /* get pgrp of tty */
+#define TIOCCONS        _IOW('t', 120, int)     /* become virtual console */
+
+#define FIONREAD        0x467f
+#define TIOCINQ         FIONREAD
+
+#define TIOCGETP        0x7408
+#define TIOCSETP        0x7409
+#define TIOCSETN        0x740a                  /* TIOCSETP wo flush */
+
+/* #define TIOCSETA     _IOW('t', 20, struct termios) set termios struct */
+/* #define TIOCSETAW    _IOW('t', 21, struct termios) drain output, set */
+/* #define TIOCSETAF    _IOW('t', 22, struct termios) drn out, fls in, set */
+/* #define TIOCGETD     _IOR('t', 26, int)      get line discipline */
+/* #define TIOCSETD     _IOW('t', 27, int)      set line discipline */
+                                                /* 127-124 compat */
+
+#define TIOCSBRK        0x5427  /* BSD compatibility */
+#define TIOCCBRK        0x5428  /* BSD compatibility */
+#define TIOCGSID        0x7416  /* Return the session ID of FD */
+#define TCGETS2         _IOR('T', 0x2A, struct termios2)
+#define TCSETS2         _IOW('T', 0x2B, struct termios2)
+#define TCSETSW2        _IOW('T', 0x2C, struct termios2)
+#define TCSETSF2        _IOW('T', 0x2D, struct termios2)
+#define TIOCGPTN        _IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
+#define TIOCSPTLCK      _IOW('T', 0x31, int)  /* Lock/unlock Pty */
+#define TIOCGDEV        _IOR('T', 0x32, unsigned int) /* Get primary device node of /dev/console */
+#define TIOCSIG         _IOW('T', 0x36, int)  /* Generate signal on Pty slave */
+#define TIOCVHANGUP     0x5437
+
+/* I hope the range from 0x5480 on is free ... */
+#define TIOCSCTTY       0x5480          /* become controlling tty */
+#define TIOCGSOFTCAR    0x5481
+#define TIOCSSOFTCAR    0x5482
+#define TIOCLINUX       0x5483
+#define TIOCGSERIAL     0x5484
+#define TIOCSSERIAL     0x5485
+#define TCSBRKP         0x5486  /* Needed for POSIX tcsendbreak() */
+#define TIOCSERCONFIG   0x5488
+#define TIOCSERGWILD    0x5489
+#define TIOCSERSWILD    0x548a
+#define TIOCGLCKTRMIOS  0x548b
+#define TIOCSLCKTRMIOS  0x548c
+#define TIOCSERGSTRUCT  0x548d /* For debugging only */
+#define TIOCSERGETLSR   0x548e /* Get line status register */
+#define TIOCSERGETMULTI 0x548f /* Get multiport config  */
+#define TIOCSERSETMULTI 0x5490 /* Set multiport config */
+#define TIOCMIWAIT      0x5491 /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT     0x5492 /* read serial port inline interrupt counts */
+
+#endif /* __ASM_IOCTLS_H */
diff --git a/arch/mips/include/asm/ipcbuf.h b/arch/mips/include/asm/ipcbuf.h
new file mode 100644
index 00000000000..d47d08f264e
--- /dev/null
+++ b/arch/mips/include/asm/ipcbuf.h
@@ -0,0 +1,28 @@
+#ifndef _ASM_IPCBUF_H
+#define _ASM_IPCBUF_H
+
+/*
+ * The ipc64_perm structure for alpha architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit seq
+ * - 2 miscellaneous 64-bit values
+ */
+
+struct ipc64_perm
+{
+        __kernel_key_t  key;
+        __kernel_uid_t  uid;
+        __kernel_gid_t  gid;
+        __kernel_uid_t  cuid;
+        __kernel_gid_t  cgid;
+        __kernel_mode_t mode;
+        unsigned short  seq;
+        unsigned short  __pad1;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+};
+
+#endif /* _ASM_IPCBUF_H */
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx.h b/arch/mips/include/asm/mach-au1x00/au1xxx.h
new file mode 100644
index 00000000000..1b3655090ed
--- /dev/null
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx.h
@@ -0,0 +1,43 @@
+/*
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _AU1XXX_H_
+#define _AU1XXX_H_
+
+#include <asm/mach-au1x00/au1000.h>
+
+#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
+    defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
+#include <asm/mach-db1x00/db1x00.h>
+
+#elif defined(CONFIG_MIPS_PB1550)
+#include <asm/mach-pb1x00/pb1550.h>
+
+#elif defined(CONFIG_MIPS_PB1200)
+#include <asm/mach-pb1x00/pb1200.h>
+
+#elif defined(CONFIG_MIPS_DB1200)
+#include <asm/mach-db1x00/db1200.h>
+
+#endif
+
+#endif /* _AU1XXX_H_ */
diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h
new file mode 100644
index 00000000000..a919dac525a
--- /dev/null
+++ b/arch/mips/include/asm/mach-db1x00/db1x00.h
@@ -0,0 +1,79 @@
+/*
+ * AMD Alchemy DBAu1x00 Reference Boards
+ *
+ * Copyright 2001, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_DB1X00_H
+#define __ASM_DB1X00_H
+
+#include <asm/mach-au1x00/au1xxx_psc.h>
+
+#ifdef CONFIG_MIPS_DB1550
+
+#define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN      DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC3_TX
+#define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC3_RX
+
+#define SPI_PSC_BASE            PSC0_BASE_ADDR
+#define AC97_PSC_BASE           PSC1_BASE_ADDR
+#define SMBUS_PSC_BASE          PSC2_BASE_ADDR
+#define I2S_PSC_BASE            PSC3_BASE_ADDR
+
+#define NAND_PHYS_ADDR          0x20000000
+
+#endif
+
+/*
+ * NAND defines
+ *
+ * Timing values as described in databook, * ns value stripped of the
+ * lower 2 bits.
+ * These defines are here rather than an Au1550 generic file because
+ * the parts chosen on another board may be different and may require
+ * different timings.
+ */
+#define NAND_T_H                (18 >> 2)
+#define NAND_T_PUL              (30 >> 2)
+#define NAND_T_SU               (30 >> 2)
+#define NAND_T_WH               (30 >> 2)
+
+/* Bitfield shift amounts */
+#define NAND_T_H_SHIFT          0
+#define NAND_T_PUL_SHIFT        4
+#define NAND_T_SU_SHIFT         8
+#define NAND_T_WH_SHIFT         12
+
+#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
+                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
+                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
+                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
+#define NAND_CS         1
+
+/* Should be done by YAMON */
+#define NAND_STCFG      0x00400005 /* 8-bit NAND */
+#define NAND_STTIME     0x00007774 /* valid for 396 MHz SD=2 only */
+#define NAND_STADDR     0x12000FFF /* physical address 0x20000000 */
+
+#endif /* __ASM_DB1X00_H */
diff --git a/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h b/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h
new file mode 100644
index 00000000000..27aaaa5d925
--- /dev/null
+++ b/arch/mips/include/asm/mach-mipssim/cpu-feature-overrides.h
@@ -0,0 +1,67 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Chris Dearman
+ */
+#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
+
+
+/*
+ * CPU feature overrides for MIPS boards
+ */
+#ifdef CONFIG_CPU_MIPS32
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+#define cpu_has_fpu             0
+/* #define cpu_has_32fpr        ? */
+#define cpu_has_counter         1
+/* #define cpu_has_watch        ? */
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */
+/* #define cpu_has_prefetch     ? */
+#define cpu_has_mcheck          1
+/* #define cpu_has_ejtag        ? */
+#define cpu_has_llsc            1
+/* #define cpu_has_vtag_icache  ? */
+/* #define cpu_has_dc_aliases   ? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_clo_clz         1
+#define cpu_has_nofpuex         0
+/* #define cpu_has_64bits       ? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_inclusive_pcaches ? */
+#endif
+
+#ifdef CONFIG_CPU_MIPS64
+#define cpu_has_tlb             1
+#define cpu_has_4kex            1
+#define cpu_has_4k_cache        1
+/* #define cpu_has_fpu          ? */
+/* #define cpu_has_32fpr        ? */
+#define cpu_has_counter         1
+/* #define cpu_has_watch        ? */
+#define cpu_has_divec           1
+#define cpu_has_vce             0
+/* #define cpu_has_cache_cdex_p ? */
+/* #define cpu_has_cache_cdex_s ? */
+/* #define cpu_has_prefetch     ? */
+#define cpu_has_mcheck          1
+/* #define cpu_has_ejtag        ? */
+#define cpu_has_llsc            1
+/* #define cpu_has_vtag_icache  ? */
+/* #define cpu_has_dc_aliases   ? */
+/* #define cpu_has_ic_fills_f_dc ? */
+#define cpu_has_clo_clz         1
+#define cpu_has_nofpuex         0
+/* #define cpu_has_64bits       ? */
+/* #define cpu_has_64bit_zero_reg ? */
+/* #define cpu_has_inclusive_pcaches ? */
+#endif
+
+#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-mipssim/war.h b/arch/mips/include/asm/mach-mipssim/war.h
new file mode 100644
index 00000000000..c8a74a3515e
--- /dev/null
+++ b/arch/mips/include/asm/mach-mipssim/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H
+#define __ASM_MIPS_MACH_MIPSSIM_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             0
+#define ICACHE_REFILLS_WORKAROUND_WAR   0
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
new file mode 100644
index 00000000000..622c58710e5
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/mc146818rtc.h
@@ -0,0 +1,34 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1998, 2001, 03 by Ralf Baechle
+ *
+ * RTC routines for PC style attached Dallas chip.
+ */
+#ifndef __ASM_MACH_AU1XX_MC146818RTC_H
+#define __ASM_MACH_AU1XX_MC146818RTC_H
+
+#include <asm/io.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#define RTC_PORT(x)     (0x0c000000 + (x))
+#define RTC_IRQ         8
+#define PB1500_RTC_ADDR 0x0c000000
+
+static inline unsigned char CMOS_READ(unsigned long offset)
+{
+        offset <<= 2;
+        return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff);
+}
+
+static inline void CMOS_WRITE(unsigned char data, unsigned long offset)
+{
+        offset <<= 2;
+        au_writel(data, offset + PB1500_RTC_ADDR);
+}
+
+#define RTC_ALWAYS_BCD  1
+
+#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1000.h b/arch/mips/include/asm/mach-pb1x00/pb1000.h
new file mode 100644
index 00000000000..65059255dc1
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1000.h
@@ -0,0 +1,87 @@
+/*
+ * Alchemy Semi Pb1000 Reference Board
+ *
+ * Copyright 2001, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1000_H
+#define __ASM_PB1000_H
+
+/* PCMCIA PB1000 specific defines */
+#define PCMCIA_MAX_SOCK  1
+#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
+
+#define PB1000_PCR              0xBE000000
+#  define PCR_SLOT_0_VPP0       (1 << 0)
+#  define PCR_SLOT_0_VPP1       (1 << 1)
+#  define PCR_SLOT_0_VCC0       (1 << 2)
+#  define PCR_SLOT_0_VCC1       (1 << 3)
+#  define PCR_SLOT_0_RST        (1 << 4)
+#  define PCR_SLOT_1_VPP0       (1 << 8)
+#  define PCR_SLOT_1_VPP1       (1 << 9)
+#  define PCR_SLOT_1_VCC0       (1 << 10)
+#  define PCR_SLOT_1_VCC1       (1 << 11)
+#  define PCR_SLOT_1_RST        (1 << 12)
+
+#define PB1000_MDR              0xBE000004
+#  define MDR_PI                (1 << 5)        /* PCMCIA int latch  */
+#  define MDR_EPI               (1 << 14)       /* enable PCMCIA int */
+#  define MDR_CPI               (1 << 15)       /* clear  PCMCIA int  */
+
+#define PB1000_ACR1             0xBE000008
+#  define ACR1_SLOT_0_CD1       (1 << 0)        /* card detect 1        */
+#  define ACR1_SLOT_0_CD2       (1 << 1)        /* card detect 2        */
+#  define ACR1_SLOT_0_READY     (1 << 2)        /* ready                */
+#  define ACR1_SLOT_0_STATUS    (1 << 3)        /* status change        */
+#  define ACR1_SLOT_0_VS1       (1 << 4)        /* voltage sense 1      */
+#  define ACR1_SLOT_0_VS2       (1 << 5)        /* voltage sense 2      */
+#  define ACR1_SLOT_0_INPACK    (1 << 6)        /* inpack pin status    */
+#  define ACR1_SLOT_1_CD1       (1 << 8)        /* card detect 1        */
+#  define ACR1_SLOT_1_CD2       (1 << 9)        /* card detect 2        */
+#  define ACR1_SLOT_1_READY     (1 << 10)       /* ready                */
+#  define ACR1_SLOT_1_STATUS    (1 << 11)       /* status change        */
+#  define ACR1_SLOT_1_VS1       (1 << 12)       /* voltage sense 1      */
+#  define ACR1_SLOT_1_VS2       (1 << 13)       /* voltage sense 2      */
+#  define ACR1_SLOT_1_INPACK    (1 << 14)       /* inpack pin status    */
+
+#define CPLD_AUX0               0xBE00000C
+#define CPLD_AUX1               0xBE000010
+#define CPLD_AUX2               0xBE000014
+
+/* Voltage levels */
+
+/* VPPEN1 - VPPEN0 */
+#define VPP_GND ((0 << 1) | (0 << 0))
+#define VPP_5V  ((1 << 1) | (0 << 0))
+#define VPP_3V  ((0 << 1) | (1 << 0))
+#define VPP_12V ((0 << 1) | (1 << 0))
+#define VPP_HIZ ((1 << 1) | (1 << 0))
+
+/* VCCEN1 - VCCEN0 */
+#define VCC_3V  ((0 << 1) | (1 << 0))
+#define VCC_5V  ((1 << 1) | (0 << 0))
+#define VCC_HIZ ((0 << 1) | (0 << 0))
+
+/* VPP/VCC */
+#define SET_VCC_VPP(VCC, VPP, SLOT) \
+        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
+#endif /* __ASM_PB1000_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h
new file mode 100644
index 00000000000..fce4332ebb7
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h
@@ -0,0 +1,141 @@
+/*
+ * AMD Alchemy Pb1200 Reference Board
+ * Board Registers defines.
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1200_H
+#define __ASM_PB1200_H
+
+#include <linux/types.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1xxx_psc.h>
+
+#define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN      DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC1_TX
+#define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC1_RX
+
+/*
+ * SPI and SMB are muxed on the Pb1200 board.
+ * Refer to board documentation.
+ */
+#define SPI_PSC_BASE            PSC0_BASE_ADDR
+#define SMBUS_PSC_BASE          PSC0_BASE_ADDR
+/*
+ * AC97 and I2S are muxed on the Pb1200 board.
+ * Refer to board documentation.
+ */
+#define AC97_PSC_BASE       PSC1_BASE_ADDR
+#define I2S_PSC_BASE    PSC1_BASE_ADDR
+
+
+#define BCSR_SYSTEM_VDDI        0x001F
+#define BCSR_SYSTEM_POWEROFF    0x4000
+#define BCSR_SYSTEM_RESET       0x8000
+
+/* Bit positions for the different interrupt sources */
+#define BCSR_INT_IDE            0x0001
+#define BCSR_INT_ETH            0x0002
+#define BCSR_INT_PC0            0x0004
+#define BCSR_INT_PC0STSCHG      0x0008
+#define BCSR_INT_PC1            0x0010
+#define BCSR_INT_PC1STSCHG      0x0020
+#define BCSR_INT_DC             0x0040
+#define BCSR_INT_FLASHBUSY      0x0080
+#define BCSR_INT_PC0INSERT      0x0100
+#define BCSR_INT_PC0EJECT       0x0200
+#define BCSR_INT_PC1INSERT      0x0400
+#define BCSR_INT_PC1EJECT       0x0800
+#define BCSR_INT_SD0INSERT      0x1000
+#define BCSR_INT_SD0EJECT       0x2000
+#define BCSR_INT_SD1INSERT      0x4000
+#define BCSR_INT_SD1EJECT       0x8000
+
+#define SMC91C111_PHYS_ADDR     0x0D000300
+#define SMC91C111_INT           PB1200_ETH_INT
+
+#define IDE_PHYS_ADDR           0x0C800000
+#define IDE_REG_SHIFT           5
+#define IDE_PHYS_LEN            (16 << IDE_REG_SHIFT)
+#define IDE_INT                 PB1200_IDE_INT
+#define IDE_DDMA_REQ            DSCR_CMD0_DMA_REQ1
+#define IDE_RQSIZE              128
+
+#define NAND_PHYS_ADDR  0x1C000000
+
+/*
+ * Timing values as described in databook, * ns value stripped of
+ * lower 2 bits.
+ * These defines are here rather than an Au1200 generic file because
+ * the parts chosen on another board may be different and may require
+ * different timings.
+ */
+#define NAND_T_H                (18 >> 2)
+#define NAND_T_PUL              (30 >> 2)
+#define NAND_T_SU               (30 >> 2)
+#define NAND_T_WH               (30 >> 2)
+
+/* Bitfield shift amounts */
+#define NAND_T_H_SHIFT          0
+#define NAND_T_PUL_SHIFT        4
+#define NAND_T_SU_SHIFT         8
+#define NAND_T_WH_SHIFT         12
+
+#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
+                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
+                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
+                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
+
+/*
+ * External Interrupts for Pb1200 as of 8/6/2004.
+ * Bit positions in the CPLD registers can be calculated by taking
+ * the interrupt define and subtracting the PB1200_INT_BEGIN value.
+ *
+ *   Example: IDE bis pos is  = 64 - 64
+ *            ETH bit pos is  = 65 - 64
+ */
+enum external_pb1200_ints {
+        PB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,
+
+        PB1200_IDE_INT          = PB1200_INT_BEGIN,
+        PB1200_ETH_INT,
+        PB1200_PC0_INT,
+        PB1200_PC0_STSCHG_INT,
+        PB1200_PC1_INT,
+        PB1200_PC1_STSCHG_INT,
+        PB1200_DC_INT,
+        PB1200_FLASHBUSY_INT,
+        PB1200_PC0_INSERT_INT,
+        PB1200_PC0_EJECT_INT,
+        PB1200_PC1_INSERT_INT,
+        PB1200_PC1_EJECT_INT,
+        PB1200_SD0_INSERT_INT,
+        PB1200_SD0_EJECT_INT,
+        PB1200_SD1_INSERT_INT,
+        PB1200_SD1_EJECT_INT,
+
+        PB1200_INT_END          = PB1200_INT_BEGIN + 15
+};
+
+/* NAND chip select */
+#define NAND_CS 1
+
+#endif /* __ASM_PB1200_H */
diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h
new file mode 100644
index 00000000000..f835c88e959
--- /dev/null
+++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h
@@ -0,0 +1,73 @@
+/*
+ * AMD Alchemy Semi PB1550 Reference Board
+ * Board Registers defines.
+ *
+ * Copyright 2004 Embedded Edge LLC.
+ * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * ########################################################################
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ *
+ */
+#ifndef __ASM_PB1550_H
+#define __ASM_PB1550_H
+
+#include <linux/types.h>
+#include <asm/mach-au1x00/au1xxx_psc.h>
+
+#define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
+#define DBDMA_AC97_RX_CHAN      DSCR_CMD0_PSC1_RX
+#define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC3_TX
+#define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC3_RX
+
+#define SPI_PSC_BASE            PSC0_BASE_ADDR
+#define AC97_PSC_BASE           PSC1_BASE_ADDR
+#define SMBUS_PSC_BASE          PSC2_BASE_ADDR
+#define I2S_PSC_BASE            PSC3_BASE_ADDR
+
+/*
+ * Timing values as described in databook, * ns value stripped of
+ * lower 2 bits.
+ * These defines are here rather than an SOC1550 generic file because
+ * the parts chosen on another board may be different and may require
+ * different timings.
+ */
+#define NAND_T_H                (18 >> 2)
+#define NAND_T_PUL              (30 >> 2)
+#define NAND_T_SU               (30 >> 2)
+#define NAND_T_WH               (30 >> 2)
+
+/* Bitfield shift amounts */
+#define NAND_T_H_SHIFT          0
+#define NAND_T_PUL_SHIFT        4
+#define NAND_T_SU_SHIFT         8
+#define NAND_T_WH_SHIFT         12
+
+#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
+                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
+                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
+                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
+
+#define NAND_CS 1
+
+/* Should be done by YAMON */
+#define NAND_STCFG      0x00400005 /* 8-bit NAND */
+#define NAND_STTIME     0x00007774 /* valid for 396 MHz SD=2 only */
+#define NAND_STADDR     0x12000FFF /* physical address 0x20000000 */
+
+#endif /* __ASM_PB1550_H */
diff --git a/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h b/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h
new file mode 100644
index 00000000000..470e5e9e10d
--- /dev/null
+++ b/arch/mips/include/asm/mach-yosemite/cpu-feature-overrides.h
@@ -0,0 +1,47 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
+ */
+#ifndef __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
+
+/*
+ * Momentum Jaguar ATX always has the RM9000 processor.
+ */
+#define cpu_has_watch           1
+#define cpu_has_mips16          0
+#define cpu_has_divec           0
+#define cpu_has_vce             0
+#define cpu_has_cache_cdex_p    0
+#define cpu_has_cache_cdex_s    0
+#define cpu_has_prefetch        1
+#define cpu_has_mcheck          0
+#define cpu_has_ejtag           0
+
+#define cpu_has_llsc            1
+#define cpu_has_vtag_icache     0
+#define cpu_has_dc_aliases      0
+#define cpu_has_ic_fills_f_dc   0
+#define cpu_has_dsp             0
+#define cpu_has_mipsmt          0
+#define cpu_has_userlocal       0
+#define cpu_icache_snoops_remote_store  0
+
+#define cpu_has_nofpuex         0
+#define cpu_has_64bits          1
+
+#define cpu_has_inclusive_pcaches       0
+
+#define cpu_dcache_line_size()  32
+#define cpu_icache_line_size()  32
+#define cpu_scache_line_size()  32
+
+#define cpu_has_mips32r1        0
+#define cpu_has_mips32r2        0
+#define cpu_has_mips64r1        0
+#define cpu_has_mips64r2        0
+
+#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-yosemite/war.h b/arch/mips/include/asm/mach-yosemite/war.h
new file mode 100644
index 00000000000..e5c6d53efc8
--- /dev/null
+++ b/arch/mips/include/asm/mach-yosemite/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H
+#define __ASM_MIPS_MACH_YOSEMITE_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR     0
+#define R4600_V1_HIT_CACHEOP_WAR        0
+#define R4600_V2_HIT_CACHEOP_WAR        0
+#define R5432_CP0_INTERRUPT_WAR         0
+#define BCM1250_M3_WAR                  0
+#define SIBYTE_1956_WAR                 0
+#define MIPS4K_ICACHE_REFILL_WAR        0
+#define MIPS_CACHE_SYNC_WAR             0
+#define TX49XX_ICACHE_INDEX_INV_WAR     0
+#define RM9000_CDEX_SMP_WAR             1
+#define ICACHE_REFILLS_WORKAROUND_WAR   1
+#define R10000_LLSC_WAR                 0
+#define MIPS34K_MISSED_ITLB_WAR         0
+
+#endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */
diff --git a/arch/mips/include/asm/mips-boards/simint.h b/arch/mips/include/asm/mips-boards/simint.h
new file mode 100644
index 00000000000..8ef6db76d5c
--- /dev/null
+++ b/arch/mips/include/asm/mips-boards/simint.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#ifndef _MIPS_SIMINT_H
+#define _MIPS_SIMINT_H
+
+#include <irq.h>
+
+#define SIM_INT_BASE            0
+#define MIPSCPU_INT_MB0         2
+#define MIPS_CPU_TIMER_IRQ      7
+
+
+#define MSC01E_INT_BASE         64
+
+#define MSC01E_INT_CPUCTR       11
+
+#endif
diff --git a/arch/mips/include/asm/mman.h b/arch/mips/include/asm/mman.h
new file mode 100644
index 00000000000..785b4ea4ec3
--- /dev/null
+++ b/arch/mips/include/asm/mman.h
@@ -0,0 +1,86 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999, 2002 by Ralf Baechle
+ */
+#ifndef _ASM_MMAN_H
+#define _ASM_MMAN_H
+
+/*
+ * Protections are chosen from these bits, OR'd together.  The
+ * implementation does not necessarily support PROT_EXEC or PROT_WRITE
+ * without PROT_READ.  The only guarantees are that no writing will be
+ * allowed without PROT_WRITE and no access will be allowed for PROT_NONE.
+ */
+#define PROT_NONE       0x00            /* page can not be accessed */
+#define PROT_READ       0x01            /* page can be read */
+#define PROT_WRITE      0x02            /* page can be written */
+#define PROT_EXEC       0x04            /* page can be executed */
+/*                      0x08               reserved for PROT_EXEC_NOFLUSH */
+#define PROT_SEM        0x10            /* page may be used for atomic ops */
+#define PROT_GROWSDOWN  0x01000000      /* mprotect flag: extend change to start of growsdown vma */
+#define PROT_GROWSUP    0x02000000      /* mprotect flag: extend change to end of growsup vma */
+
+/*
+ * Flags for mmap
+ */
+#define MAP_SHARED      0x001           /* Share changes */
+#define MAP_PRIVATE     0x002           /* Changes are private */
+#define MAP_TYPE        0x00f           /* Mask for type of mapping */
+#define MAP_FIXED       0x010           /* Interpret addr exactly */
+
+/* not used by linux, but here to make sure we don't clash with ABI defines */
+#define MAP_RENAME      0x020           /* Assign page to file */
+#define MAP_AUTOGROW    0x040           /* File may grow by writing */
+#define MAP_LOCAL       0x080           /* Copy on fork/sproc */
+#define MAP_AUTORSRV    0x100           /* Logical swap reserved on demand */
+
+/* These are linux-specific */
+#define MAP_NORESERVE   0x0400          /* don't check for reservations */
+#define MAP_ANONYMOUS   0x0800          /* don't use a file */
+#define MAP_GROWSDOWN   0x1000          /* stack-like segment */
+#define MAP_DENYWRITE   0x2000          /* ETXTBSY */
+#define MAP_EXECUTABLE  0x4000          /* mark it as an executable */
+#define MAP_LOCKED      0x8000          /* pages are locked */
+#define MAP_POPULATE    0x10000         /* populate (prefault) pagetables */
+#define MAP_NONBLOCK    0x20000         /* do not block on IO */
+#define MAP_STACK       0x40000         /* give out an address that is best suited for process/thread stacks */
+#define MAP_HUGETLB     0x80000         /* create a huge page mapping */
+
+/*
+ * Flags for msync
+ */
+#define MS_ASYNC        0x0001          /* sync memory asynchronously */
+#define MS_INVALIDATE   0x0002          /* invalidate mappings & caches */
+#define MS_SYNC         0x0004          /* synchronous memory sync */
+
+/*
+ * Flags for mlockall
+ */
+#define MCL_CURRENT     1               /* lock all current mappings */
+#define MCL_FUTURE      2               /* lock all future mappings */
+
+#define MADV_NORMAL     0               /* no further special treatment */
+#define MADV_RANDOM     1               /* expect random page references */
+#define MADV_SEQUENTIAL 2               /* expect sequential page references */
+#define MADV_WILLNEED   3               /* will need these pages */
+#define MADV_DONTNEED   4               /* don't need these pages */
+
+/* common parameters: try to keep these consistent across architectures */
+#define MADV_REMOVE     9               /* remove these pages & resources */
+#define MADV_DONTFORK   10              /* don't inherit across fork */
+#define MADV_DOFORK     11              /* do inherit across fork */
+
+#define MADV_MERGEABLE   12             /* KSM may merge identical pages */
+#define MADV_UNMERGEABLE 13             /* KSM may not merge identical pages */
+#define MADV_HWPOISON    100            /* poison a page for testing */
+
+#define MADV_HUGEPAGE   14              /* Worth backing with hugepages */
+#define MADV_NOHUGEPAGE 15              /* Not worth backing with hugepages */
+
+/* compatibility flags */
+#define MAP_FILE        0
+
+#endif /* _ASM_MMAN_H */
diff --git a/arch/mips/include/asm/msgbuf.h b/arch/mips/include/asm/msgbuf.h
new file mode 100644
index 00000000000..0d6c7f14de3
--- /dev/null
+++ b/arch/mips/include/asm/msgbuf.h
@@ -0,0 +1,47 @@
+#ifndef _ASM_MSGBUF_H
+#define _ASM_MSGBUF_H
+
+
+/*
+ * The msqid64_ds structure for the MIPS architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - extension of time_t to 64-bit on 32-bitsystem to solve the y2038 problem
+ * - 2 miscellaneous unsigned long values
+ */
+
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused1;
+#endif
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused1;
+#endif
+#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused2;
+#endif
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused2;
+#endif
+#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused3;
+#endif
+        __kernel_time_t msg_ctime;      /* last change time */
+#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
+        unsigned long   __unused3;
+#endif
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+#endif /* _ASM_MSGBUF_H */
diff --git a/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h b/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
new file mode 100644
index 00000000000..d553f8e88df
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pcieep-defs.h
@@ -0,0 +1,1365 @@
+/***********************license start***************
+ * Author: Cavium Networks
+ *
+ * Contact: support@caviumnetworks.com
+ * This file is part of the OCTEON SDK
+ *
+ * Copyright (c) 2003-2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ *
+ * This file is distributed in the hope that it will be useful, but
+ * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
+ * NONINFRINGEMENT.  See the GNU General Public License for more
+ * details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this file; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ * or visit http://www.gnu.org/licenses/.
+ *
+ * This file may also be available under a different license from Cavium.
+ * Contact Cavium Networks for more information
+ ***********************license end**************************************/
+
+#ifndef __CVMX_PCIEEP_DEFS_H__
+#define __CVMX_PCIEEP_DEFS_H__
+
+#define CVMX_PCIEEP_CFG000 \
+         (0x0000000000000000ull)
+#define CVMX_PCIEEP_CFG001 \
+         (0x0000000000000004ull)
+#define CVMX_PCIEEP_CFG002 \
+         (0x0000000000000008ull)
+#define CVMX_PCIEEP_CFG003 \
+         (0x000000000000000Cull)
+#define CVMX_PCIEEP_CFG004 \
+         (0x0000000000000010ull)
+#define CVMX_PCIEEP_CFG004_MASK \
+         (0x0000000080000010ull)
+#define CVMX_PCIEEP_CFG005 \
+         (0x0000000000000014ull)
+#define CVMX_PCIEEP_CFG005_MASK \
+         (0x0000000080000014ull)
+#define CVMX_PCIEEP_CFG006 \
+         (0x0000000000000018ull)
+#define CVMX_PCIEEP_CFG006_MASK \
+         (0x0000000080000018ull)
+#define CVMX_PCIEEP_CFG007 \
+         (0x000000000000001Cull)
+#define CVMX_PCIEEP_CFG007_MASK \
+         (0x000000008000001Cull)
+#define CVMX_PCIEEP_CFG008 \
+         (0x0000000000000020ull)
+#define CVMX_PCIEEP_CFG008_MASK \
+         (0x0000000080000020ull)
+#define CVMX_PCIEEP_CFG009 \
+         (0x0000000000000024ull)
+#define CVMX_PCIEEP_CFG009_MASK \
+         (0x0000000080000024ull)
+#define CVMX_PCIEEP_CFG010 \
+         (0x0000000000000028ull)
+#define CVMX_PCIEEP_CFG011 \
+         (0x000000000000002Cull)
+#define CVMX_PCIEEP_CFG012 \
+         (0x0000000000000030ull)
+#define CVMX_PCIEEP_CFG012_MASK \
+         (0x0000000080000030ull)
+#define CVMX_PCIEEP_CFG013 \
+         (0x0000000000000034ull)
+#define CVMX_PCIEEP_CFG015 \
+         (0x000000000000003Cull)
+#define CVMX_PCIEEP_CFG016 \
+         (0x0000000000000040ull)
+#define CVMX_PCIEEP_CFG017 \
+         (0x0000000000000044ull)
+#define CVMX_PCIEEP_CFG020 \
+         (0x0000000000000050ull)
+#define CVMX_PCIEEP_CFG021 \
+         (0x0000000000000054ull)
+#define CVMX_PCIEEP_CFG022 \
+         (0x0000000000000058ull)
+#define CVMX_PCIEEP_CFG023 \
+         (0x000000000000005Cull)
+#define CVMX_PCIEEP_CFG028 \
+         (0x0000000000000070ull)
+#define CVMX_PCIEEP_CFG029 \
+         (0x0000000000000074ull)
+#define CVMX_PCIEEP_CFG030 \
+         (0x0000000000000078ull)
+#define CVMX_PCIEEP_CFG031 \
+         (0x000000000000007Cull)
+#define CVMX_PCIEEP_CFG032 \
+         (0x0000000000000080ull)
+#define CVMX_PCIEEP_CFG033 \
+         (0x0000000000000084ull)
+#define CVMX_PCIEEP_CFG034 \
+         (0x0000000000000088ull)
+#define CVMX_PCIEEP_CFG037 \
+         (0x0000000000000094ull)
+#define CVMX_PCIEEP_CFG038 \
+         (0x0000000000000098ull)
+#define CVMX_PCIEEP_CFG039 \
+         (0x000000000000009Cull)
+#define CVMX_PCIEEP_CFG040 \
+         (0x00000000000000A0ull)
+#define CVMX_PCIEEP_CFG041 \
+         (0x00000000000000A4ull)
+#define CVMX_PCIEEP_CFG042 \
+         (0x00000000000000A8ull)
+#define CVMX_PCIEEP_CFG064 \
+         (0x0000000000000100ull)
+#define CVMX_PCIEEP_CFG065 \
+         (0x0000000000000104ull)
+#define CVMX_PCIEEP_CFG066 \
+         (0x0000000000000108ull)
+#define CVMX_PCIEEP_CFG067 \
+         (0x000000000000010Cull)
+#define CVMX_PCIEEP_CFG068 \
+         (0x0000000000000110ull)
+#define CVMX_PCIEEP_CFG069 \
+         (0x0000000000000114ull)
+#define CVMX_PCIEEP_CFG070 \
+         (0x0000000000000118ull)
+#define CVMX_PCIEEP_CFG071 \
+         (0x000000000000011Cull)
+#define CVMX_PCIEEP_CFG072 \
+         (0x0000000000000120ull)
+#define CVMX_PCIEEP_CFG073 \
+         (0x0000000000000124ull)
+#define CVMX_PCIEEP_CFG074 \
+         (0x0000000000000128ull)
+#define CVMX_PCIEEP_CFG448 \
+         (0x0000000000000700ull)
+#define CVMX_PCIEEP_CFG449 \
+         (0x0000000000000704ull)
+#define CVMX_PCIEEP_CFG450 \
+         (0x0000000000000708ull)
+#define CVMX_PCIEEP_CFG451 \
+         (0x000000000000070Cull)
+#define CVMX_PCIEEP_CFG452 \
+         (0x0000000000000710ull)
+#define CVMX_PCIEEP_CFG453 \
+         (0x0000000000000714ull)
+#define CVMX_PCIEEP_CFG454 \
+         (0x0000000000000718ull)
+#define CVMX_PCIEEP_CFG455 \
+         (0x000000000000071Cull)
+#define CVMX_PCIEEP_CFG456 \
+         (0x0000000000000720ull)
+#define CVMX_PCIEEP_CFG458 \
+         (0x0000000000000728ull)
+#define CVMX_PCIEEP_CFG459 \
+         (0x000000000000072Cull)
+#define CVMX_PCIEEP_CFG460 \
+         (0x0000000000000730ull)
+#define CVMX_PCIEEP_CFG461 \
+         (0x0000000000000734ull)
+#define CVMX_PCIEEP_CFG462 \
+         (0x0000000000000738ull)
+#define CVMX_PCIEEP_CFG463 \
+         (0x000000000000073Cull)
+#define CVMX_PCIEEP_CFG464 \
+         (0x0000000000000740ull)
+#define CVMX_PCIEEP_CFG465 \
+         (0x0000000000000744ull)
+#define CVMX_PCIEEP_CFG466 \
+         (0x0000000000000748ull)
+#define CVMX_PCIEEP_CFG467 \
+         (0x000000000000074Cull)
+#define CVMX_PCIEEP_CFG468 \
+         (0x0000000000000750ull)
+#define CVMX_PCIEEP_CFG490 \
+         (0x00000000000007A8ull)
+#define CVMX_PCIEEP_CFG491 \
+         (0x00000000000007ACull)
+#define CVMX_PCIEEP_CFG492 \
+         (0x00000000000007B0ull)
+#define CVMX_PCIEEP_CFG516 \
+         (0x0000000000000810ull)
+#define CVMX_PCIEEP_CFG517 \
+         (0x0000000000000814ull)
+
+union cvmx_pcieep_cfg000 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg000_s {
+                uint32_t devid:16;
+                uint32_t vendid:16;
+        } s;
+        struct cvmx_pcieep_cfg000_s cn52xx;
+        struct cvmx_pcieep_cfg000_s cn52xxp1;
+        struct cvmx_pcieep_cfg000_s cn56xx;
+        struct cvmx_pcieep_cfg000_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg001 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg001_s {
+                uint32_t dpe:1;
+                uint32_t sse:1;
+                uint32_t rma:1;
+                uint32_t rta:1;
+                uint32_t sta:1;
+                uint32_t devt:2;
+                uint32_t mdpe:1;
+                uint32_t fbb:1;
+                uint32_t reserved_22_22:1;
+                uint32_t m66:1;
+                uint32_t cl:1;
+                uint32_t i_stat:1;
+                uint32_t reserved_11_18:8;
+                uint32_t i_dis:1;
+                uint32_t fbbe:1;
+                uint32_t see:1;
+                uint32_t ids_wcc:1;
+                uint32_t per:1;
+                uint32_t vps:1;
+                uint32_t mwice:1;
+                uint32_t scse:1;
+                uint32_t me:1;
+                uint32_t msae:1;
+                uint32_t isae:1;
+        } s;
+        struct cvmx_pcieep_cfg001_s cn52xx;
+        struct cvmx_pcieep_cfg001_s cn52xxp1;
+        struct cvmx_pcieep_cfg001_s cn56xx;
+        struct cvmx_pcieep_cfg001_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg002 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg002_s {
+                uint32_t bcc:8;
+                uint32_t sc:8;
+                uint32_t pi:8;
+                uint32_t rid:8;
+        } s;
+        struct cvmx_pcieep_cfg002_s cn52xx;
+        struct cvmx_pcieep_cfg002_s cn52xxp1;
+        struct cvmx_pcieep_cfg002_s cn56xx;
+        struct cvmx_pcieep_cfg002_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg003 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg003_s {
+                uint32_t bist:8;
+                uint32_t mfd:1;
+                uint32_t chf:7;
+                uint32_t lt:8;
+                uint32_t cls:8;
+        } s;
+        struct cvmx_pcieep_cfg003_s cn52xx;
+        struct cvmx_pcieep_cfg003_s cn52xxp1;
+        struct cvmx_pcieep_cfg003_s cn56xx;
+        struct cvmx_pcieep_cfg003_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg004 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg004_s {
+                uint32_t lbab:18;
+                uint32_t reserved_4_13:10;
+                uint32_t pf:1;
+                uint32_t typ:2;
+                uint32_t mspc:1;
+        } s;
+        struct cvmx_pcieep_cfg004_s cn52xx;
+        struct cvmx_pcieep_cfg004_s cn52xxp1;
+        struct cvmx_pcieep_cfg004_s cn56xx;
+        struct cvmx_pcieep_cfg004_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg004_mask {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg004_mask_s {
+                uint32_t lmask:31;
+                uint32_t enb:1;
+        } s;
+        struct cvmx_pcieep_cfg004_mask_s cn52xx;
+        struct cvmx_pcieep_cfg004_mask_s cn52xxp1;
+        struct cvmx_pcieep_cfg004_mask_s cn56xx;
+        struct cvmx_pcieep_cfg004_mask_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg005 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg005_s {
+                uint32_t ubab:32;
+        } s;
+        struct cvmx_pcieep_cfg005_s cn52xx;
+        struct cvmx_pcieep_cfg005_s cn52xxp1;
+        struct cvmx_pcieep_cfg005_s cn56xx;
+        struct cvmx_pcieep_cfg005_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg005_mask {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg005_mask_s {
+                uint32_t umask:32;
+        } s;
+        struct cvmx_pcieep_cfg005_mask_s cn52xx;
+        struct cvmx_pcieep_cfg005_mask_s cn52xxp1;
+        struct cvmx_pcieep_cfg005_mask_s cn56xx;
+        struct cvmx_pcieep_cfg005_mask_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg006 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg006_s {
+                uint32_t lbab:6;
+                uint32_t reserved_4_25:22;
+                uint32_t pf:1;
+                uint32_t typ:2;
+                uint32_t mspc:1;
+        } s;
+        struct cvmx_pcieep_cfg006_s cn52xx;
+        struct cvmx_pcieep_cfg006_s cn52xxp1;
+        struct cvmx_pcieep_cfg006_s cn56xx;
+        struct cvmx_pcieep_cfg006_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg006_mask {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg006_mask_s {
+                uint32_t lmask:31;
+                uint32_t enb:1;
+        } s;
+        struct cvmx_pcieep_cfg006_mask_s cn52xx;
+        struct cvmx_pcieep_cfg006_mask_s cn52xxp1;
+        struct cvmx_pcieep_cfg006_mask_s cn56xx;
+        struct cvmx_pcieep_cfg006_mask_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg007 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg007_s {
+                uint32_t ubab:32;
+        } s;
+        struct cvmx_pcieep_cfg007_s cn52xx;
+        struct cvmx_pcieep_cfg007_s cn52xxp1;
+        struct cvmx_pcieep_cfg007_s cn56xx;
+        struct cvmx_pcieep_cfg007_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg007_mask {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg007_mask_s {
+                uint32_t umask:32;
+        } s;
+        struct cvmx_pcieep_cfg007_mask_s cn52xx;
+        struct cvmx_pcieep_cfg007_mask_s cn52xxp1;
+        struct cvmx_pcieep_cfg007_mask_s cn56xx;
+        struct cvmx_pcieep_cfg007_mask_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg008 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg008_s {
+                uint32_t reserved_4_31:28;
+                uint32_t pf:1;
+                uint32_t typ:2;
+                uint32_t mspc:1;
+        } s;
+        struct cvmx_pcieep_cfg008_s cn52xx;
+        struct cvmx_pcieep_cfg008_s cn52xxp1;
+        struct cvmx_pcieep_cfg008_s cn56xx;
+        struct cvmx_pcieep_cfg008_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg008_mask {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg008_mask_s {
+                uint32_t lmask:31;
+                uint32_t enb:1;
+        } s;
+        struct cvmx_pcieep_cfg008_mask_s cn52xx;
+        struct cvmx_pcieep_cfg008_mask_s cn52xxp1;
+        struct cvmx_pcieep_cfg008_mask_s cn56xx;
+        struct cvmx_pcieep_cfg008_mask_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg009 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg009_s {
+                uint32_t ubab:25;
+                uint32_t reserved_0_6:7;
+        } s;
+        struct cvmx_pcieep_cfg009_s cn52xx;
+        struct cvmx_pcieep_cfg009_s cn52xxp1;
+        struct cvmx_pcieep_cfg009_s cn56xx;
+        struct cvmx_pcieep_cfg009_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg009_mask {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg009_mask_s {
+                uint32_t umask:32;
+        } s;
+        struct cvmx_pcieep_cfg009_mask_s cn52xx;
+        struct cvmx_pcieep_cfg009_mask_s cn52xxp1;
+        struct cvmx_pcieep_cfg009_mask_s cn56xx;
+        struct cvmx_pcieep_cfg009_mask_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg010 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg010_s {
+                uint32_t cisp:32;
+        } s;
+        struct cvmx_pcieep_cfg010_s cn52xx;
+        struct cvmx_pcieep_cfg010_s cn52xxp1;
+        struct cvmx_pcieep_cfg010_s cn56xx;
+        struct cvmx_pcieep_cfg010_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg011 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg011_s {
+                uint32_t ssid:16;
+                uint32_t ssvid:16;
+        } s;
+        struct cvmx_pcieep_cfg011_s cn52xx;
+        struct cvmx_pcieep_cfg011_s cn52xxp1;
+        struct cvmx_pcieep_cfg011_s cn56xx;
+        struct cvmx_pcieep_cfg011_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg012 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg012_s {
+                uint32_t eraddr:16;
+                uint32_t reserved_1_15:15;
+                uint32_t er_en:1;
+        } s;
+        struct cvmx_pcieep_cfg012_s cn52xx;
+        struct cvmx_pcieep_cfg012_s cn52xxp1;
+        struct cvmx_pcieep_cfg012_s cn56xx;
+        struct cvmx_pcieep_cfg012_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg012_mask {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg012_mask_s {
+                uint32_t mask:31;
+                uint32_t enb:1;
+        } s;
+        struct cvmx_pcieep_cfg012_mask_s cn52xx;
+        struct cvmx_pcieep_cfg012_mask_s cn52xxp1;
+        struct cvmx_pcieep_cfg012_mask_s cn56xx;
+        struct cvmx_pcieep_cfg012_mask_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg013 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg013_s {
+                uint32_t reserved_8_31:24;
+                uint32_t cp:8;
+        } s;
+        struct cvmx_pcieep_cfg013_s cn52xx;
+        struct cvmx_pcieep_cfg013_s cn52xxp1;
+        struct cvmx_pcieep_cfg013_s cn56xx;
+        struct cvmx_pcieep_cfg013_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg015 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg015_s {
+                uint32_t ml:8;
+                uint32_t mg:8;
+                uint32_t inta:8;
+                uint32_t il:8;
+        } s;
+        struct cvmx_pcieep_cfg015_s cn52xx;
+        struct cvmx_pcieep_cfg015_s cn52xxp1;
+        struct cvmx_pcieep_cfg015_s cn56xx;
+        struct cvmx_pcieep_cfg015_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg016 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg016_s {
+                uint32_t pmes:5;
+                uint32_t d2s:1;
+                uint32_t d1s:1;
+                uint32_t auxc:3;
+                uint32_t dsi:1;
+                uint32_t reserved_20_20:1;
+                uint32_t pme_clock:1;
+                uint32_t pmsv:3;
+                uint32_t ncp:8;
+                uint32_t pmcid:8;
+        } s;
+        struct cvmx_pcieep_cfg016_s cn52xx;
+        struct cvmx_pcieep_cfg016_s cn52xxp1;
+        struct cvmx_pcieep_cfg016_s cn56xx;
+        struct cvmx_pcieep_cfg016_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg017 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg017_s {
+                uint32_t pmdia:8;
+                uint32_t bpccee:1;
+                uint32_t bd3h:1;
+                uint32_t reserved_16_21:6;
+                uint32_t pmess:1;
+                uint32_t pmedsia:2;
+                uint32_t pmds:4;
+                uint32_t pmeens:1;
+                uint32_t reserved_4_7:4;
+                uint32_t nsr:1;
+                uint32_t reserved_2_2:1;
+                uint32_t ps:2;
+        } s;
+        struct cvmx_pcieep_cfg017_s cn52xx;
+        struct cvmx_pcieep_cfg017_s cn52xxp1;
+        struct cvmx_pcieep_cfg017_s cn56xx;
+        struct cvmx_pcieep_cfg017_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg020 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg020_s {
+                uint32_t reserved_24_31:8;
+                uint32_t m64:1;
+                uint32_t mme:3;
+                uint32_t mmc:3;
+                uint32_t msien:1;
+                uint32_t ncp:8;
+                uint32_t msicid:8;
+        } s;
+        struct cvmx_pcieep_cfg020_s cn52xx;
+        struct cvmx_pcieep_cfg020_s cn52xxp1;
+        struct cvmx_pcieep_cfg020_s cn56xx;
+        struct cvmx_pcieep_cfg020_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg021 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg021_s {
+                uint32_t lmsi:30;
+                uint32_t reserved_0_1:2;
+        } s;
+        struct cvmx_pcieep_cfg021_s cn52xx;
+        struct cvmx_pcieep_cfg021_s cn52xxp1;
+        struct cvmx_pcieep_cfg021_s cn56xx;
+        struct cvmx_pcieep_cfg021_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg022 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg022_s {
+                uint32_t umsi:32;
+        } s;
+        struct cvmx_pcieep_cfg022_s cn52xx;
+        struct cvmx_pcieep_cfg022_s cn52xxp1;
+        struct cvmx_pcieep_cfg022_s cn56xx;
+        struct cvmx_pcieep_cfg022_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg023 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg023_s {
+                uint32_t reserved_16_31:16;
+                uint32_t msimd:16;
+        } s;
+        struct cvmx_pcieep_cfg023_s cn52xx;
+        struct cvmx_pcieep_cfg023_s cn52xxp1;
+        struct cvmx_pcieep_cfg023_s cn56xx;
+        struct cvmx_pcieep_cfg023_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg028 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg028_s {
+                uint32_t reserved_30_31:2;
+                uint32_t imn:5;
+                uint32_t si:1;
+                uint32_t dpt:4;
+                uint32_t pciecv:4;
+                uint32_t ncp:8;
+                uint32_t pcieid:8;
+        } s;
+        struct cvmx_pcieep_cfg028_s cn52xx;
+        struct cvmx_pcieep_cfg028_s cn52xxp1;
+        struct cvmx_pcieep_cfg028_s cn56xx;
+        struct cvmx_pcieep_cfg028_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg029 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg029_s {
+                uint32_t reserved_28_31:4;
+                uint32_t cspls:2;
+                uint32_t csplv:8;
+                uint32_t reserved_16_17:2;
+                uint32_t rber:1;
+                uint32_t reserved_12_14:3;
+                uint32_t el1al:3;
+                uint32_t el0al:3;
+                uint32_t etfs:1;
+                uint32_t pfs:2;
+                uint32_t mpss:3;
+        } s;
+        struct cvmx_pcieep_cfg029_s cn52xx;
+        struct cvmx_pcieep_cfg029_s cn52xxp1;
+        struct cvmx_pcieep_cfg029_s cn56xx;
+        struct cvmx_pcieep_cfg029_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg030 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg030_s {
+                uint32_t reserved_22_31:10;
+                uint32_t tp:1;
+                uint32_t ap_d:1;
+                uint32_t ur_d:1;
+                uint32_t fe_d:1;
+                uint32_t nfe_d:1;
+                uint32_t ce_d:1;
+                uint32_t reserved_15_15:1;
+                uint32_t mrrs:3;
+                uint32_t ns_en:1;
+                uint32_t ap_en:1;
+                uint32_t pf_en:1;
+                uint32_t etf_en:1;
+                uint32_t mps:3;
+                uint32_t ro_en:1;
+                uint32_t ur_en:1;
+                uint32_t fe_en:1;
+                uint32_t nfe_en:1;
+                uint32_t ce_en:1;
+        } s;
+        struct cvmx_pcieep_cfg030_s cn52xx;
+        struct cvmx_pcieep_cfg030_s cn52xxp1;
+        struct cvmx_pcieep_cfg030_s cn56xx;
+        struct cvmx_pcieep_cfg030_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg031 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg031_s {
+                uint32_t pnum:8;
+                uint32_t reserved_22_23:2;
+                uint32_t lbnc:1;
+                uint32_t dllarc:1;
+                uint32_t sderc:1;
+                uint32_t cpm:1;
+                uint32_t l1el:3;
+                uint32_t l0el:3;
+                uint32_t aslpms:2;
+                uint32_t mlw:6;
+                uint32_t mls:4;
+        } s;
+        struct cvmx_pcieep_cfg031_s cn52xx;
+        struct cvmx_pcieep_cfg031_s cn52xxp1;
+        struct cvmx_pcieep_cfg031_s cn56xx;
+        struct cvmx_pcieep_cfg031_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg032 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg032_s {
+                uint32_t reserved_30_31:2;
+                uint32_t dlla:1;
+                uint32_t scc:1;
+                uint32_t lt:1;
+                uint32_t reserved_26_26:1;
+                uint32_t nlw:6;
+                uint32_t ls:4;
+                uint32_t reserved_10_15:6;
+                uint32_t hawd:1;
+                uint32_t ecpm:1;
+                uint32_t es:1;
+                uint32_t ccc:1;
+                uint32_t rl:1;
+                uint32_t ld:1;
+                uint32_t rcb:1;
+                uint32_t reserved_2_2:1;
+                uint32_t aslpc:2;
+        } s;
+        struct cvmx_pcieep_cfg032_s cn52xx;
+        struct cvmx_pcieep_cfg032_s cn52xxp1;
+        struct cvmx_pcieep_cfg032_s cn56xx;
+        struct cvmx_pcieep_cfg032_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg033 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg033_s {
+                uint32_t ps_num:13;
+                uint32_t nccs:1;
+                uint32_t emip:1;
+                uint32_t sp_ls:2;
+                uint32_t sp_lv:8;
+                uint32_t hp_c:1;
+                uint32_t hp_s:1;
+                uint32_t pip:1;
+                uint32_t aip:1;
+                uint32_t mrlsp:1;
+                uint32_t pcp:1;
+                uint32_t abp:1;
+        } s;
+        struct cvmx_pcieep_cfg033_s cn52xx;
+        struct cvmx_pcieep_cfg033_s cn52xxp1;
+        struct cvmx_pcieep_cfg033_s cn56xx;
+        struct cvmx_pcieep_cfg033_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg034 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg034_s {
+                uint32_t reserved_25_31:7;
+                uint32_t dlls_c:1;
+                uint32_t emis:1;
+                uint32_t pds:1;
+                uint32_t mrlss:1;
+                uint32_t ccint_d:1;
+                uint32_t pd_c:1;
+                uint32_t mrls_c:1;
+                uint32_t pf_d:1;
+                uint32_t abp_d:1;
+                uint32_t reserved_13_15:3;
+                uint32_t dlls_en:1;
+                uint32_t emic:1;
+                uint32_t pcc:1;
+                uint32_t pic:2;
+                uint32_t aic:2;
+                uint32_t hpint_en:1;
+                uint32_t ccint_en:1;
+                uint32_t pd_en:1;
+                uint32_t mrls_en:1;
+                uint32_t pf_en:1;
+                uint32_t abp_en:1;
+        } s;
+        struct cvmx_pcieep_cfg034_s cn52xx;
+        struct cvmx_pcieep_cfg034_s cn52xxp1;
+        struct cvmx_pcieep_cfg034_s cn56xx;
+        struct cvmx_pcieep_cfg034_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg037 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg037_s {
+                uint32_t reserved_5_31:27;
+                uint32_t ctds:1;
+                uint32_t ctrs:4;
+        } s;
+        struct cvmx_pcieep_cfg037_s cn52xx;
+        struct cvmx_pcieep_cfg037_s cn52xxp1;
+        struct cvmx_pcieep_cfg037_s cn56xx;
+        struct cvmx_pcieep_cfg037_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg038 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg038_s {
+                uint32_t reserved_5_31:27;
+                uint32_t ctd:1;
+                uint32_t ctv:4;
+        } s;
+        struct cvmx_pcieep_cfg038_s cn52xx;
+        struct cvmx_pcieep_cfg038_s cn52xxp1;
+        struct cvmx_pcieep_cfg038_s cn56xx;
+        struct cvmx_pcieep_cfg038_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg039 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg039_s {
+                uint32_t reserved_0_31:32;
+        } s;
+        struct cvmx_pcieep_cfg039_s cn52xx;
+        struct cvmx_pcieep_cfg039_s cn52xxp1;
+        struct cvmx_pcieep_cfg039_s cn56xx;
+        struct cvmx_pcieep_cfg039_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg040 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg040_s {
+                uint32_t reserved_0_31:32;
+        } s;
+        struct cvmx_pcieep_cfg040_s cn52xx;
+        struct cvmx_pcieep_cfg040_s cn52xxp1;
+        struct cvmx_pcieep_cfg040_s cn56xx;
+        struct cvmx_pcieep_cfg040_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg041 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg041_s {
+                uint32_t reserved_0_31:32;
+        } s;
+        struct cvmx_pcieep_cfg041_s cn52xx;
+        struct cvmx_pcieep_cfg041_s cn52xxp1;
+        struct cvmx_pcieep_cfg041_s cn56xx;
+        struct cvmx_pcieep_cfg041_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg042 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg042_s {
+                uint32_t reserved_0_31:32;
+        } s;
+        struct cvmx_pcieep_cfg042_s cn52xx;
+        struct cvmx_pcieep_cfg042_s cn52xxp1;
+        struct cvmx_pcieep_cfg042_s cn56xx;
+        struct cvmx_pcieep_cfg042_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg064 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg064_s {
+                uint32_t nco:12;
+                uint32_t cv:4;
+                uint32_t pcieec:16;
+        } s;
+        struct cvmx_pcieep_cfg064_s cn52xx;
+        struct cvmx_pcieep_cfg064_s cn52xxp1;
+        struct cvmx_pcieep_cfg064_s cn56xx;
+        struct cvmx_pcieep_cfg064_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg065 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg065_s {
+                uint32_t reserved_21_31:11;
+                uint32_t ures:1;
+                uint32_t ecrces:1;
+                uint32_t mtlps:1;
+                uint32_t ros:1;
+                uint32_t ucs:1;
+                uint32_t cas:1;
+                uint32_t cts:1;
+                uint32_t fcpes:1;
+                uint32_t ptlps:1;
+                uint32_t reserved_6_11:6;
+                uint32_t sdes:1;
+                uint32_t dlpes:1;
+                uint32_t reserved_0_3:4;
+        } s;
+        struct cvmx_pcieep_cfg065_s cn52xx;
+        struct cvmx_pcieep_cfg065_s cn52xxp1;
+        struct cvmx_pcieep_cfg065_s cn56xx;
+        struct cvmx_pcieep_cfg065_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg066 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg066_s {
+                uint32_t reserved_21_31:11;
+                uint32_t urem:1;
+                uint32_t ecrcem:1;
+                uint32_t mtlpm:1;
+                uint32_t rom:1;
+                uint32_t ucm:1;
+                uint32_t cam:1;
+                uint32_t ctm:1;
+                uint32_t fcpem:1;
+                uint32_t ptlpm:1;
+                uint32_t reserved_6_11:6;
+                uint32_t sdem:1;
+                uint32_t dlpem:1;
+                uint32_t reserved_0_3:4;
+        } s;
+        struct cvmx_pcieep_cfg066_s cn52xx;
+        struct cvmx_pcieep_cfg066_s cn52xxp1;
+        struct cvmx_pcieep_cfg066_s cn56xx;
+        struct cvmx_pcieep_cfg066_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg067 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg067_s {
+                uint32_t reserved_21_31:11;
+                uint32_t ures:1;
+                uint32_t ecrces:1;
+                uint32_t mtlps:1;
+                uint32_t ros:1;
+                uint32_t ucs:1;
+                uint32_t cas:1;
+                uint32_t cts:1;
+                uint32_t fcpes:1;
+                uint32_t ptlps:1;
+                uint32_t reserved_6_11:6;
+                uint32_t sdes:1;
+                uint32_t dlpes:1;
+                uint32_t reserved_0_3:4;
+        } s;
+        struct cvmx_pcieep_cfg067_s cn52xx;
+        struct cvmx_pcieep_cfg067_s cn52xxp1;
+        struct cvmx_pcieep_cfg067_s cn56xx;
+        struct cvmx_pcieep_cfg067_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg068 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg068_s {
+                uint32_t reserved_14_31:18;
+                uint32_t anfes:1;
+                uint32_t rtts:1;
+                uint32_t reserved_9_11:3;
+                uint32_t rnrs:1;
+                uint32_t bdllps:1;
+                uint32_t btlps:1;
+                uint32_t reserved_1_5:5;
+                uint32_t res:1;
+        } s;
+        struct cvmx_pcieep_cfg068_s cn52xx;
+        struct cvmx_pcieep_cfg068_s cn52xxp1;
+        struct cvmx_pcieep_cfg068_s cn56xx;
+        struct cvmx_pcieep_cfg068_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg069 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg069_s {
+                uint32_t reserved_14_31:18;
+                uint32_t anfem:1;
+                uint32_t rttm:1;
+                uint32_t reserved_9_11:3;
+                uint32_t rnrm:1;
+                uint32_t bdllpm:1;
+                uint32_t btlpm:1;
+                uint32_t reserved_1_5:5;
+                uint32_t rem:1;
+        } s;
+        struct cvmx_pcieep_cfg069_s cn52xx;
+        struct cvmx_pcieep_cfg069_s cn52xxp1;
+        struct cvmx_pcieep_cfg069_s cn56xx;
+        struct cvmx_pcieep_cfg069_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg070 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg070_s {
+                uint32_t reserved_9_31:23;
+                uint32_t ce:1;
+                uint32_t cc:1;
+                uint32_t ge:1;
+                uint32_t gc:1;
+                uint32_t fep:5;
+        } s;
+        struct cvmx_pcieep_cfg070_s cn52xx;
+        struct cvmx_pcieep_cfg070_s cn52xxp1;
+        struct cvmx_pcieep_cfg070_s cn56xx;
+        struct cvmx_pcieep_cfg070_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg071 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg071_s {
+                uint32_t dword1:32;
+        } s;
+        struct cvmx_pcieep_cfg071_s cn52xx;
+        struct cvmx_pcieep_cfg071_s cn52xxp1;
+        struct cvmx_pcieep_cfg071_s cn56xx;
+        struct cvmx_pcieep_cfg071_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg072 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg072_s {
+                uint32_t dword2:32;
+        } s;
+        struct cvmx_pcieep_cfg072_s cn52xx;
+        struct cvmx_pcieep_cfg072_s cn52xxp1;
+        struct cvmx_pcieep_cfg072_s cn56xx;
+        struct cvmx_pcieep_cfg072_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg073 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg073_s {
+                uint32_t dword3:32;
+        } s;
+        struct cvmx_pcieep_cfg073_s cn52xx;
+        struct cvmx_pcieep_cfg073_s cn52xxp1;
+        struct cvmx_pcieep_cfg073_s cn56xx;
+        struct cvmx_pcieep_cfg073_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg074 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg074_s {
+                uint32_t dword4:32;
+        } s;
+        struct cvmx_pcieep_cfg074_s cn52xx;
+        struct cvmx_pcieep_cfg074_s cn52xxp1;
+        struct cvmx_pcieep_cfg074_s cn56xx;
+        struct cvmx_pcieep_cfg074_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg448 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg448_s {
+                uint32_t rtl:16;
+                uint32_t rtltl:16;
+        } s;
+        struct cvmx_pcieep_cfg448_s cn52xx;
+        struct cvmx_pcieep_cfg448_s cn52xxp1;
+        struct cvmx_pcieep_cfg448_s cn56xx;
+        struct cvmx_pcieep_cfg448_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg449 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg449_s {
+                uint32_t omr:32;
+        } s;
+        struct cvmx_pcieep_cfg449_s cn52xx;
+        struct cvmx_pcieep_cfg449_s cn52xxp1;
+        struct cvmx_pcieep_cfg449_s cn56xx;
+        struct cvmx_pcieep_cfg449_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg450 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg450_s {
+                uint32_t lpec:8;
+                uint32_t reserved_22_23:2;
+                uint32_t link_state:6;
+                uint32_t force_link:1;
+                uint32_t reserved_8_14:7;
+                uint32_t link_num:8;
+        } s;
+        struct cvmx_pcieep_cfg450_s cn52xx;
+        struct cvmx_pcieep_cfg450_s cn52xxp1;
+        struct cvmx_pcieep_cfg450_s cn56xx;
+        struct cvmx_pcieep_cfg450_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg451 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg451_s {
+                uint32_t reserved_30_31:2;
+                uint32_t l1el:3;
+                uint32_t l0el:3;
+                uint32_t n_fts_cc:8;
+                uint32_t n_fts:8;
+                uint32_t ack_freq:8;
+        } s;
+        struct cvmx_pcieep_cfg451_s cn52xx;
+        struct cvmx_pcieep_cfg451_s cn52xxp1;
+        struct cvmx_pcieep_cfg451_s cn56xx;
+        struct cvmx_pcieep_cfg451_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg452 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg452_s {
+                uint32_t reserved_26_31:6;
+                uint32_t eccrc:1;
+                uint32_t reserved_22_24:3;
+                uint32_t lme:6;
+                uint32_t reserved_8_15:8;
+                uint32_t flm:1;
+                uint32_t reserved_6_6:1;
+                uint32_t dllle:1;
+                uint32_t reserved_4_4:1;
+                uint32_t ra:1;
+                uint32_t le:1;
+                uint32_t sd:1;
+                uint32_t omr:1;
+        } s;
+        struct cvmx_pcieep_cfg452_s cn52xx;
+        struct cvmx_pcieep_cfg452_s cn52xxp1;
+        struct cvmx_pcieep_cfg452_s cn56xx;
+        struct cvmx_pcieep_cfg452_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg453 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg453_s {
+                uint32_t dlld:1;
+                uint32_t reserved_26_30:5;
+                uint32_t ack_nak:1;
+                uint32_t fcd:1;
+                uint32_t ilst:24;
+        } s;
+        struct cvmx_pcieep_cfg453_s cn52xx;
+        struct cvmx_pcieep_cfg453_s cn52xxp1;
+        struct cvmx_pcieep_cfg453_s cn56xx;
+        struct cvmx_pcieep_cfg453_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg454 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg454_s {
+                uint32_t reserved_29_31:3;
+                uint32_t tmfcwt:5;
+                uint32_t tmanlt:5;
+                uint32_t tmrt:5;
+                uint32_t reserved_11_13:3;
+                uint32_t nskps:3;
+                uint32_t reserved_4_7:4;
+                uint32_t ntss:4;
+        } s;
+        struct cvmx_pcieep_cfg454_s cn52xx;
+        struct cvmx_pcieep_cfg454_s cn52xxp1;
+        struct cvmx_pcieep_cfg454_s cn56xx;
+        struct cvmx_pcieep_cfg454_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg455 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg455_s {
+                uint32_t m_cfg0_filt:1;
+                uint32_t m_io_filt:1;
+                uint32_t msg_ctrl:1;
+                uint32_t m_cpl_ecrc_filt:1;
+                uint32_t m_ecrc_filt:1;
+                uint32_t m_cpl_len_err:1;
+                uint32_t m_cpl_attr_err:1;
+                uint32_t m_cpl_tc_err:1;
+                uint32_t m_cpl_fun_err:1;
+                uint32_t m_cpl_rid_err:1;
+                uint32_t m_cpl_tag_err:1;
+                uint32_t m_lk_filt:1;
+                uint32_t m_cfg1_filt:1;
+                uint32_t m_bar_match:1;
+                uint32_t m_pois_filt:1;
+                uint32_t m_fun:1;
+                uint32_t dfcwt:1;
+                uint32_t reserved_11_14:4;
+                uint32_t skpiv:11;
+        } s;
+        struct cvmx_pcieep_cfg455_s cn52xx;
+        struct cvmx_pcieep_cfg455_s cn52xxp1;
+        struct cvmx_pcieep_cfg455_s cn56xx;
+        struct cvmx_pcieep_cfg455_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg456 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg456_s {
+                uint32_t reserved_2_31:30;
+                uint32_t m_vend1_drp:1;
+                uint32_t m_vend0_drp:1;
+        } s;
+        struct cvmx_pcieep_cfg456_s cn52xx;
+        struct cvmx_pcieep_cfg456_s cn52xxp1;
+        struct cvmx_pcieep_cfg456_s cn56xx;
+        struct cvmx_pcieep_cfg456_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg458 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg458_s {
+                uint32_t dbg_info_l32:32;
+        } s;
+        struct cvmx_pcieep_cfg458_s cn52xx;
+        struct cvmx_pcieep_cfg458_s cn52xxp1;
+        struct cvmx_pcieep_cfg458_s cn56xx;
+        struct cvmx_pcieep_cfg458_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg459 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg459_s {
+                uint32_t dbg_info_u32:32;
+        } s;
+        struct cvmx_pcieep_cfg459_s cn52xx;
+        struct cvmx_pcieep_cfg459_s cn52xxp1;
+        struct cvmx_pcieep_cfg459_s cn56xx;
+        struct cvmx_pcieep_cfg459_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg460 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg460_s {
+                uint32_t reserved_20_31:12;
+                uint32_t tphfcc:8;
+                uint32_t tpdfcc:12;
+        } s;
+        struct cvmx_pcieep_cfg460_s cn52xx;
+        struct cvmx_pcieep_cfg460_s cn52xxp1;
+        struct cvmx_pcieep_cfg460_s cn56xx;
+        struct cvmx_pcieep_cfg460_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg461 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg461_s {
+                uint32_t reserved_20_31:12;
+                uint32_t tchfcc:8;
+                uint32_t tcdfcc:12;
+        } s;
+        struct cvmx_pcieep_cfg461_s cn52xx;
+        struct cvmx_pcieep_cfg461_s cn52xxp1;
+        struct cvmx_pcieep_cfg461_s cn56xx;
+        struct cvmx_pcieep_cfg461_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg462 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg462_s {
+                uint32_t reserved_20_31:12;
+                uint32_t tchfcc:8;
+                uint32_t tcdfcc:12;
+        } s;
+        struct cvmx_pcieep_cfg462_s cn52xx;
+        struct cvmx_pcieep_cfg462_s cn52xxp1;
+        struct cvmx_pcieep_cfg462_s cn56xx;
+        struct cvmx_pcieep_cfg462_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg463 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg463_s {
+                uint32_t reserved_3_31:29;
+                uint32_t rqne:1;
+                uint32_t trbne:1;
+                uint32_t rtlpfccnr:1;
+        } s;
+        struct cvmx_pcieep_cfg463_s cn52xx;
+        struct cvmx_pcieep_cfg463_s cn52xxp1;
+        struct cvmx_pcieep_cfg463_s cn56xx;
+        struct cvmx_pcieep_cfg463_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg464 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg464_s {
+                uint32_t wrr_vc3:8;
+                uint32_t wrr_vc2:8;
+                uint32_t wrr_vc1:8;
+                uint32_t wrr_vc0:8;
+        } s;
+        struct cvmx_pcieep_cfg464_s cn52xx;
+        struct cvmx_pcieep_cfg464_s cn52xxp1;
+        struct cvmx_pcieep_cfg464_s cn56xx;
+        struct cvmx_pcieep_cfg464_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg465 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg465_s {
+                uint32_t wrr_vc7:8;
+                uint32_t wrr_vc6:8;
+                uint32_t wrr_vc5:8;
+                uint32_t wrr_vc4:8;
+        } s;
+        struct cvmx_pcieep_cfg465_s cn52xx;
+        struct cvmx_pcieep_cfg465_s cn52xxp1;
+        struct cvmx_pcieep_cfg465_s cn56xx;
+        struct cvmx_pcieep_cfg465_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg466 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg466_s {
+                uint32_t rx_queue_order:1;
+                uint32_t type_ordering:1;
+                uint32_t reserved_24_29:6;
+                uint32_t queue_mode:3;
+                uint32_t reserved_20_20:1;
+                uint32_t header_credits:8;
+                uint32_t data_credits:12;
+        } s;
+        struct cvmx_pcieep_cfg466_s cn52xx;
+        struct cvmx_pcieep_cfg466_s cn52xxp1;
+        struct cvmx_pcieep_cfg466_s cn56xx;
+        struct cvmx_pcieep_cfg466_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg467 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg467_s {
+                uint32_t reserved_24_31:8;
+                uint32_t queue_mode:3;
+                uint32_t reserved_20_20:1;
+                uint32_t header_credits:8;
+                uint32_t data_credits:12;
+        } s;
+        struct cvmx_pcieep_cfg467_s cn52xx;
+        struct cvmx_pcieep_cfg467_s cn52xxp1;
+        struct cvmx_pcieep_cfg467_s cn56xx;
+        struct cvmx_pcieep_cfg467_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg468 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg468_s {
+                uint32_t reserved_24_31:8;
+                uint32_t queue_mode:3;
+                uint32_t reserved_20_20:1;
+                uint32_t header_credits:8;
+                uint32_t data_credits:12;
+        } s;
+        struct cvmx_pcieep_cfg468_s cn52xx;
+        struct cvmx_pcieep_cfg468_s cn52xxp1;
+        struct cvmx_pcieep_cfg468_s cn56xx;
+        struct cvmx_pcieep_cfg468_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg490 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg490_s {
+                uint32_t reserved_26_31:6;
+                uint32_t header_depth:10;
+                uint32_t reserved_14_15:2;
+                uint32_t data_depth:14;
+        } s;
+        struct cvmx_pcieep_cfg490_s cn52xx;
+        struct cvmx_pcieep_cfg490_s cn52xxp1;
+        struct cvmx_pcieep_cfg490_s cn56xx;
+        struct cvmx_pcieep_cfg490_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg491 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg491_s {
+                uint32_t reserved_26_31:6;
+                uint32_t header_depth:10;
+                uint32_t reserved_14_15:2;
+                uint32_t data_depth:14;
+        } s;
+        struct cvmx_pcieep_cfg491_s cn52xx;
+        struct cvmx_pcieep_cfg491_s cn52xxp1;
+        struct cvmx_pcieep_cfg491_s cn56xx;
+        struct cvmx_pcieep_cfg491_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg492 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg492_s {
+                uint32_t reserved_26_31:6;
+                uint32_t header_depth:10;
+                uint32_t reserved_14_15:2;
+                uint32_t data_depth:14;
+        } s;
+        struct cvmx_pcieep_cfg492_s cn52xx;
+        struct cvmx_pcieep_cfg492_s cn52xxp1;
+        struct cvmx_pcieep_cfg492_s cn56xx;
+        struct cvmx_pcieep_cfg492_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg516 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg516_s {
+                uint32_t phy_stat:32;
+        } s;
+        struct cvmx_pcieep_cfg516_s cn52xx;
+        struct cvmx_pcieep_cfg516_s cn52xxp1;
+        struct cvmx_pcieep_cfg516_s cn56xx;
+        struct cvmx_pcieep_cfg516_s cn56xxp1;
+};
+
+union cvmx_pcieep_cfg517 {
+        uint32_t u32;
+        struct cvmx_pcieep_cfg517_s {
+                uint32_t phy_ctrl:32;
+        } s;
+        struct cvmx_pcieep_cfg517_s cn52xx;
+        struct cvmx_pcieep_cfg517_s cn52xxp1;
+        struct cvmx_pcieep_cfg517_s cn56xx;
+        struct cvmx_pcieep_cfg517_s cn56xxp1;
+};
+
+#endif
diff --git a/arch/mips/include/asm/param.h b/arch/mips/include/asm/param.h
new file mode 100644
index 00000000000..da3920fce9a
--- /dev/null
+++ b/arch/mips/include/asm/param.h
@@ -0,0 +1,16 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright 1994 - 2000, 2002 Ralf Baechle (ralf@gnu.org)
+ * Copyright 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_PARAM_H
+#define _ASM_PARAM_H
+
+#define EXEC_PAGESIZE   65536
+
+#include <asm-generic/param.h>
+
+#endif /* _ASM_PARAM_H */
diff --git a/arch/mips/include/asm/poll.h b/arch/mips/include/asm/poll.h
new file mode 100644
index 00000000000..47b95208043
--- /dev/null
+++ b/arch/mips/include/asm/poll.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_POLL_H
+#define __ASM_POLL_H
+
+#define POLLWRNORM      POLLOUT
+#define POLLWRBAND      0x0100
+
+#include <asm-generic/poll.h>
+
+#endif /* __ASM_POLL_H */
diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h
new file mode 100644
index 00000000000..c200102c858
--- /dev/null
+++ b/arch/mips/include/asm/posix_types.h
@@ -0,0 +1,144 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 97, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_POSIX_TYPES_H
+#define _ASM_POSIX_TYPES_H
+
+#include <asm/sgidefs.h>
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long   __kernel_ino_t;
+typedef unsigned int    __kernel_mode_t;
+#if (_MIPS_SZLONG == 32)
+typedef unsigned long   __kernel_nlink_t;
+#endif
+#if (_MIPS_SZLONG == 64)
+typedef unsigned int    __kernel_nlink_t;
+#endif
+typedef long            __kernel_off_t;
+typedef int             __kernel_pid_t;
+typedef int             __kernel_ipc_pid_t;
+typedef unsigned int    __kernel_uid_t;
+typedef unsigned int    __kernel_gid_t;
+#if (_MIPS_SZLONG == 32)
+typedef unsigned int    __kernel_size_t;
+typedef int             __kernel_ssize_t;
+typedef int             __kernel_ptrdiff_t;
+#endif
+#if (_MIPS_SZLONG == 64)
+typedef unsigned long   __kernel_size_t;
+typedef long            __kernel_ssize_t;
+typedef long            __kernel_ptrdiff_t;
+#endif
+typedef long            __kernel_time_t;
+typedef long            __kernel_suseconds_t;
+typedef long            __kernel_clock_t;
+typedef int             __kernel_timer_t;
+typedef int             __kernel_clockid_t;
+typedef long            __kernel_daddr_t;
+typedef char *          __kernel_caddr_t;
+
+typedef unsigned short  __kernel_uid16_t;
+typedef unsigned short  __kernel_gid16_t;
+typedef unsigned int    __kernel_uid32_t;
+typedef unsigned int    __kernel_gid32_t;
+typedef __kernel_uid_t  __kernel_old_uid_t;
+typedef __kernel_gid_t  __kernel_old_gid_t;
+typedef unsigned int    __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long      __kernel_loff_t;
+#endif
+
+typedef struct {
+#if (_MIPS_SZLONG == 32)
+        long    val[2];
+#endif
+#if (_MIPS_SZLONG == 64)
+        int     val[2];
+#endif
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__)
+
+#undef __FD_SET
+static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
+}
+
+#undef __FD_CLR
+static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
+}
+
+#undef __FD_ISSET
+static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
+{
+        unsigned long __tmp = __fd / __NFDBITS;
+        unsigned long __rem = __fd % __NFDBITS;
+        return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
+}
+
+/*
+ * This will unroll the loop for the normal constant case (8 ints,
+ * for a 256-bit fd_set)
+ */
+#undef __FD_ZERO
+static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
+{
+        unsigned long *__tmp = __p->fds_bits;
+        int __i;
+
+        if (__builtin_constant_p(__FDSET_LONGS)) {
+                switch (__FDSET_LONGS) {
+                case 16:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        __tmp[ 4] = 0; __tmp[ 5] = 0;
+                        __tmp[ 6] = 0; __tmp[ 7] = 0;
+                        __tmp[ 8] = 0; __tmp[ 9] = 0;
+                        __tmp[10] = 0; __tmp[11] = 0;
+                        __tmp[12] = 0; __tmp[13] = 0;
+                        __tmp[14] = 0; __tmp[15] = 0;
+                        return;
+
+                case 8:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        __tmp[ 4] = 0; __tmp[ 5] = 0;
+                        __tmp[ 6] = 0; __tmp[ 7] = 0;
+                        return;
+
+                case 4:
+                        __tmp[ 0] = 0; __tmp[ 1] = 0;
+                        __tmp[ 2] = 0; __tmp[ 3] = 0;
+                        return;
+                }
+        }
+        __i = __FDSET_LONGS;
+        while (__i) {
+                __i--;
+                *__tmp = 0;
+                __tmp++;
+        }
+}
+
+#endif /* defined(__KERNEL__) */
+
+#endif /* _ASM_POSIX_TYPES_H */
diff --git a/arch/mips/include/asm/resource.h b/arch/mips/include/asm/resource.h
new file mode 100644
index 00000000000..87cb3085269
--- /dev/null
+++ b/arch/mips/include/asm/resource.h
@@ -0,0 +1,35 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 98, 99, 2000 by Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_RESOURCE_H
+#define _ASM_RESOURCE_H
+
+
+/*
+ * These five resource limit IDs have a MIPS/Linux-specific ordering,
+ * the rest comes from the generic header:
+ */
+#define RLIMIT_NOFILE           5       /* max number of open files */
+#define RLIMIT_AS               6       /* address space limit */
+#define RLIMIT_RSS              7       /* max resident set size */
+#define RLIMIT_NPROC            8       /* max number of processes */
+#define RLIMIT_MEMLOCK          9       /* max locked-in-memory address space */
+
+/*
+ * SuS says limits have to be unsigned.
+ * Which makes a ton more sense anyway,
+ * but we keep the old value on MIPS32,
+ * for compatibility:
+ */
+#ifdef CONFIG_32BIT
+# define RLIM_INFINITY          0x7fffffffUL
+#endif
+
+#include <asm-generic/resource.h>
+
+#endif /* _ASM_RESOURCE_H */
diff --git a/arch/mips/include/asm/sembuf.h b/arch/mips/include/asm/sembuf.h
new file mode 100644
index 00000000000..7281a4decaa
--- /dev/null
+++ b/arch/mips/include/asm/sembuf.h
@@ -0,0 +1,22 @@
+#ifndef _ASM_SEMBUF_H
+#define _ASM_SEMBUF_H
+
+/*
+ * The semid64_ds structure for the MIPS architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 2 miscellaneous 64-bit values
+ */
+
+struct semid64_ds {
+        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
+        __kernel_time_t sem_otime;              /* last semop time */
+        __kernel_time_t sem_ctime;              /* last change time */
+        unsigned long   sem_nsems;              /* no. of semaphores in array */
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+};
+
+#endif /* _ASM_SEMBUF_H */
diff --git a/arch/mips/include/asm/sgidefs.h b/arch/mips/include/asm/sgidefs.h
new file mode 100644
index 00000000000..876442fcfb3
--- /dev/null
+++ b/arch/mips/include/asm/sgidefs.h
@@ -0,0 +1,44 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 1999, 2001 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef __ASM_SGIDEFS_H
+#define __ASM_SGIDEFS_H
+
+/*
+ * Using a Linux compiler for building Linux seems logic but not to
+ * everybody.
+ */
+#ifndef __linux__
+#error Use a Linux compiler or give up.
+#endif
+
+/*
+ * Definitions for the ISA levels
+ *
+ * With the introduction of MIPS32 / MIPS64 instruction sets definitions
+ * MIPS ISAs are no longer subsets of each other.  Therefore comparisons
+ * on these symbols except with == may result in unexpected results and
+ * are forbidden!
+ */
+#define _MIPS_ISA_MIPS1         1
+#define _MIPS_ISA_MIPS2         2
+#define _MIPS_ISA_MIPS3         3
+#define _MIPS_ISA_MIPS4         4
+#define _MIPS_ISA_MIPS5         5
+#define _MIPS_ISA_MIPS32        6
+#define _MIPS_ISA_MIPS64        7
+
+/*
+ * Subprogram calling convention
+ */
+#define _MIPS_SIM_ABI32         1
+#define _MIPS_SIM_NABI32        2
+#define _MIPS_SIM_ABI64         3
+
+#endif /* __ASM_SGIDEFS_H */
diff --git a/arch/mips/include/asm/shmbuf.h b/arch/mips/include/asm/shmbuf.h
new file mode 100644
index 00000000000..f994438277b
--- /dev/null
+++ b/arch/mips/include/asm/shmbuf.h
@@ -0,0 +1,38 @@
+#ifndef _ASM_SHMBUF_H
+#define _ASM_SHMBUF_H
+
+/*
+ * The shmid64_ds structure for the MIPS architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 2 miscellaneous 32-bit rsp. 64-bit values
+ */
+
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        __kernel_time_t         shm_atime;      /* last attach time */
+        __kernel_time_t         shm_dtime;      /* last detach time */
+        __kernel_time_t         shm_ctime;      /* last change time */
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused1;
+        unsigned long           __unused2;
+};
+
+struct shminfo64 {
+        unsigned long   shmmax;
+        unsigned long   shmmin;
+        unsigned long   shmmni;
+        unsigned long   shmseg;
+        unsigned long   shmall;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* _ASM_SHMBUF_H */
diff --git a/arch/mips/include/asm/smvp.h b/arch/mips/include/asm/smvp.h
new file mode 100644
index 00000000000..0d0e80a39e8
--- /dev/null
+++ b/arch/mips/include/asm/smvp.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_SMVP_H
+#define _ASM_SMVP_H
+
+/*
+ * Definitions for SMVP multitasking on MIPS MT cores
+ */
+struct task_struct;
+
+extern void smvp_smp_setup(void);
+extern void smvp_smp_finish(void);
+extern void smvp_boot_secondary(int cpu, struct task_struct *t);
+extern void smvp_init_secondary(void);
+extern void smvp_smp_finish(void);
+extern void smvp_cpus_done(void);
+extern void smvp_prepare_cpus(unsigned int max_cpus);
+
+/* This is platform specific */
+extern void smvp_send_ipi(int cpu, unsigned int action);
+#endif /*  _ASM_SMVP_H */
diff --git a/arch/mips/include/asm/sockios.h b/arch/mips/include/asm/sockios.h
new file mode 100644
index 00000000000..ed1a5f78d22
--- /dev/null
+++ b/arch/mips/include/asm/sockios.h
@@ -0,0 +1,26 @@
+/*
+ * Socket-level I/O control calls.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 by Ralf Baechle
+ */
+#ifndef _ASM_SOCKIOS_H
+#define _ASM_SOCKIOS_H
+
+#include <asm/ioctl.h>
+
+/* Socket-level I/O control calls. */
+#define FIOGETOWN       _IOR('f', 123, int)
+#define FIOSETOWN       _IOW('f', 124, int)
+
+#define SIOCATMARK      _IOR('s', 7, int)
+#define SIOCSPGRP       _IOW('s', 8, pid_t)
+#define SIOCGPGRP       _IOR('s', 9, pid_t)
+
+#define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
+#define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
+
+#endif /* _ASM_SOCKIOS_H */
diff --git a/arch/mips/include/asm/stat.h b/arch/mips/include/asm/stat.h
new file mode 100644
index 00000000000..6e00f751ab6
--- /dev/null
+++ b/arch/mips/include/asm/stat.h
@@ -0,0 +1,132 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999, 2000 Ralf Baechle
+ * Copyright (C) 2000 Silicon Graphics, Inc.
+ */
+#ifndef _ASM_STAT_H
+#define _ASM_STAT_H
+
+#include <linux/types.h>
+
+#include <asm/sgidefs.h>
+
+#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
+
+struct stat {
+        unsigned        st_dev;
+        long            st_pad1[3];             /* Reserved for network id */
+        ino_t           st_ino;
+        mode_t          st_mode;
+        nlink_t         st_nlink;
+        uid_t           st_uid;
+        gid_t           st_gid;
+        unsigned        st_rdev;
+        long            st_pad2[2];
+        off_t           st_size;
+        long            st_pad3;
+        /*
+         * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+         * but we don't have it under Linux.
+         */
+        time_t          st_atime;
+        long            st_atime_nsec;
+        time_t          st_mtime;
+        long            st_mtime_nsec;
+        time_t          st_ctime;
+        long            st_ctime_nsec;
+        long            st_blksize;
+        long            st_blocks;
+        long            st_pad4[14];
+};
+
+/*
+ * This matches struct stat64 in glibc2.1, hence the absolutely insane
+ * amounts of padding around dev_t's.  The memory layout is the same as of
+ * struct stat of the 64-bit kernel.
+ */
+
+struct stat64 {
+        unsigned long   st_dev;
+        unsigned long   st_pad0[3];     /* Reserved for st_dev expansion  */
+
+        unsigned long long      st_ino;
+
+        mode_t          st_mode;
+        nlink_t         st_nlink;
+
+        uid_t           st_uid;
+        gid_t           st_gid;
+
+        unsigned long   st_rdev;
+        unsigned long   st_pad1[3];     /* Reserved for st_rdev expansion  */
+
+        long long       st_size;
+
+        /*
+         * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+         * but we don't have it under Linux.
+         */
+        time_t          st_atime;
+        unsigned long   st_atime_nsec;  /* Reserved for st_atime expansion  */
+
+        time_t          st_mtime;
+        unsigned long   st_mtime_nsec;  /* Reserved for st_mtime expansion  */
+
+        time_t          st_ctime;
+        unsigned long   st_ctime_nsec;  /* Reserved for st_ctime expansion  */
+
+        unsigned long   st_blksize;
+        unsigned long   st_pad2;
+
+        long long       st_blocks;
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+
+/* The memory layout is the same as of struct stat64 of the 32-bit kernel.  */
+struct stat {
+        unsigned int            st_dev;
+        unsigned int            st_pad0[3]; /* Reserved for st_dev expansion */
+
+        unsigned long           st_ino;
+
+        mode_t                  st_mode;
+        nlink_t                 st_nlink;
+
+        uid_t                   st_uid;
+        gid_t                   st_gid;
+
+        unsigned int            st_rdev;
+        unsigned int            st_pad1[3]; /* Reserved for st_rdev expansion */
+
+        off_t                   st_size;
+
+        /*
+         * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
+         * but we don't have it under Linux.
+         */
+        unsigned int            st_atime;
+        unsigned int            st_atime_nsec;
+
+        unsigned int            st_mtime;
+        unsigned int            st_mtime_nsec;
+
+        unsigned int            st_ctime;
+        unsigned int            st_ctime_nsec;
+
+        unsigned int            st_blksize;
+        unsigned int            st_pad2;
+
+        unsigned long           st_blocks;
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
+
+#define STAT_HAVE_NSEC 1
+
+#endif /* _ASM_STAT_H */
diff --git a/arch/mips/include/asm/statfs.h b/arch/mips/include/asm/statfs.h
new file mode 100644
index 00000000000..0f805c7a42a
--- /dev/null
+++ b/arch/mips/include/asm/statfs.h
@@ -0,0 +1,100 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 1999 by Ralf Baechle
+ */
+#ifndef _ASM_STATFS_H
+#define _ASM_STATFS_H
+
+#include <linux/posix_types.h>
+#include <asm/sgidefs.h>
+
+#ifndef __KERNEL_STRICT_NAMES
+
+#include <linux/types.h>
+
+typedef __kernel_fsid_t        fsid_t;
+
+#endif
+
+struct statfs {
+        long            f_type;
+#define f_fstyp f_type
+        long            f_bsize;
+        long            f_frsize;       /* Fragment size - unsupported */
+        long            f_blocks;
+        long            f_bfree;
+        long            f_files;
+        long            f_ffree;
+        long            f_bavail;
+
+        /* Linux specials */
+        __kernel_fsid_t f_fsid;
+        long            f_namelen;
+        long            f_flags;
+        long            f_spare[5];
+};
+
+#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
+
+/*
+ * Unlike the traditional version the LFAPI version has none of the ABI junk
+ */
+struct statfs64 {
+        __u32   f_type;
+        __u32   f_bsize;
+        __u32   f_frsize;       /* Fragment size - unsupported */
+        __u32   __pad;
+        __u64   f_blocks;
+        __u64   f_bfree;
+        __u64   f_files;
+        __u64   f_ffree;
+        __u64   f_bavail;
+        __kernel_fsid_t f_fsid;
+        __u32   f_namelen;
+        __u32   f_flags;
+        __u32   f_spare[5];
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
+
+#if _MIPS_SIM == _MIPS_SIM_ABI64
+
+struct statfs64 {                       /* Same as struct statfs */
+        long            f_type;
+        long            f_bsize;
+        long            f_frsize;       /* Fragment size - unsupported */
+        long            f_blocks;
+        long            f_bfree;
+        long            f_files;
+        long            f_ffree;
+        long            f_bavail;
+
+        /* Linux specials */
+        __kernel_fsid_t f_fsid;
+        long            f_namelen;
+        long            f_flags;
+        long            f_spare[5];
+};
+
+struct compat_statfs64 {
+        __u32   f_type;
+        __u32   f_bsize;
+        __u32   f_frsize;       /* Fragment size - unsupported */
+        __u32   __pad;
+        __u64   f_blocks;
+        __u64   f_bfree;
+        __u64   f_files;
+        __u64   f_ffree;
+        __u64   f_bavail;
+        __kernel_fsid_t f_fsid;
+        __u32   f_namelen;
+        __u32   f_flags;
+        __u32   f_spare[5];
+};
+
+#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
+
+#endif /* _ASM_STATFS_H */
diff --git a/arch/mips/include/asm/swab.h b/arch/mips/include/asm/swab.h
new file mode 100644
index 00000000000..97c2f81b4b4
--- /dev/null
+++ b/arch/mips/include/asm/swab.h
@@ -0,0 +1,59 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1996, 99, 2003 by Ralf Baechle
+ */
+#ifndef _ASM_SWAB_H
+#define _ASM_SWAB_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+
+#define __SWAB_64_THRU_32__
+
+#ifdef CONFIG_CPU_MIPSR2
+
+static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
+{
+        __asm__(
+        "       wsbh    %0, %1                  \n"
+        : "=r" (x)
+        : "r" (x));
+
+        return x;
+}
+#define __arch_swab16 __arch_swab16
+
+static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
+{
+        __asm__(
+        "       wsbh    %0, %1                  \n"
+        "       rotr    %0, %0, 16              \n"
+        : "=r" (x)
+        : "r" (x));
+
+        return x;
+}
+#define __arch_swab32 __arch_swab32
+
+/*
+ * Having already checked for CONFIG_CPU_MIPSR2, enable the
+ * optimized version for 64-bit kernel on r2 CPUs.
+ */
+#ifdef CONFIG_64BIT
+static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
+{
+        __asm__(
+        "       dsbh    %0, %1\n"
+        "       dshd    %0, %0"
+        : "=r" (x)
+        : "r" (x));
+
+        return x;
+}
+#define __arch_swab64 __arch_swab64
+#endif /* CONFIG_64BIT */
+#endif /* CONFIG_CPU_MIPSR2 */
+#endif /* _ASM_SWAB_H */
diff --git a/arch/mips/include/asm/sysmips.h b/arch/mips/include/asm/sysmips.h
new file mode 100644
index 00000000000..4f47b7d6a5f
--- /dev/null
+++ b/arch/mips/include/asm/sysmips.h
@@ -0,0 +1,25 @@
+/*
+ * Definitions for the MIPS sysmips(2) call
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995 by Ralf Baechle
+ */
+#ifndef _ASM_SYSMIPS_H
+#define _ASM_SYSMIPS_H
+
+/*
+ * Commands for the sysmips(2) call
+ *
+ * sysmips(2) is deprecated - though some existing software uses it.
+ * We only support the following commands.
+ */
+#define SETNAME                    1    /* set hostname                  */
+#define FLUSH_CACHE                3    /* writeback and invalidate caches */
+#define MIPS_FIXADE                7    /* control address error fixing  */
+#define MIPS_RDNVRAM              10    /* read NVRAM */
+#define MIPS_ATOMIC_SET         2001    /* atomically set variable       */
+
+#endif /* _ASM_SYSMIPS_H */
diff --git a/arch/mips/include/asm/system.h b/arch/mips/include/asm/system.h
new file mode 100644
index 00000000000..6018c80ce37
--- /dev/null
+++ b/arch/mips/include/asm/system.h
@@ -0,0 +1,235 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
+ * Copyright (C) 1996 by Paul M. Antoine
+ * Copyright (C) 1999 Silicon Graphics
+ * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 2000 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_SYSTEM_H
+#define _ASM_SYSTEM_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/irqflags.h>
+
+#include <asm/addrspace.h>
+#include <asm/barrier.h>
+#include <asm/cmpxchg.h>
+#include <asm/cpu-features.h>
+#include <asm/dsp.h>
+#include <asm/watch.h>
+#include <asm/war.h>
+
+
+/*
+ * switch_to(n) should switch tasks to task nr n, first
+ * checking that n isn't the current task, in which case it does nothing.
+ */
+extern asmlinkage void *resume(void *last, void *next, void *next_ti);
+
+struct task_struct;
+
+extern unsigned int ll_bit;
+extern struct task_struct *ll_task;
+
+#ifdef CONFIG_MIPS_MT_FPAFF
+
+/*
+ * Handle the scheduler resume end of FPU affinity management.  We do this
+ * inline to try to keep the overhead down. If we have been forced to run on
+ * a "CPU" with an FPU because of a previous high level of FP computation,
+ * but did not actually use the FPU during the most recent time-slice (CU1
+ * isn't set), we undo the restriction on cpus_allowed.
+ *
+ * We're not calling set_cpus_allowed() here, because we have no need to
+ * force prompt migration - we're already switching the current CPU to a
+ * different thread.
+ */
+
+#define __mips_mt_fpaff_switch_to(prev)                                 \
+do {                                                                    \
+        struct thread_info *__prev_ti = task_thread_info(prev);         \
+                                                                        \
+        if (cpu_has_fpu &&                                              \
+            test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) &&             \
+            (!(KSTK_STATUS(prev) & ST0_CU1))) {                         \
+                clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND);          \
+                prev->cpus_allowed = prev->thread.user_cpus_allowed;    \
+        }                                                               \
+        next->thread.emulated_fp = 0;                                   \
+} while(0)
+
+#else
+#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
+#endif
+
+#define __clear_software_ll_bit()                                       \
+do {                                                                    \
+        if (!__builtin_constant_p(cpu_has_llsc) || !cpu_has_llsc)       \
+                ll_bit = 0;                                             \
+} while (0)
+
+#define switch_to(prev, next, last)                                     \
+do {                                                                    \
+        __mips_mt_fpaff_switch_to(prev);                                \
+        if (cpu_has_dsp)                                                \
+                __save_dsp(prev);                                       \
+        __clear_software_ll_bit();                                      \
+        (last) = resume(prev, next, task_thread_info(next));            \
+} while (0)
+
+#define finish_arch_switch(prev)                                        \
+do {                                                                    \
+        if (cpu_has_dsp)                                                \
+                __restore_dsp(current);                                 \
+        if (cpu_has_userlocal)                                          \
+                write_c0_userlocal(current_thread_info()->tp_value);    \
+        __restore_watch();                                              \
+} while (0)
+
+static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
+{
+        __u32 retval;
+
+        smp_mb__before_llsc();
+
+        if (kernel_uses_llsc && R10000_LLSC_WAR) {
+                unsigned long dummy;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     ll      %0, %3                  # xchg_u32      \n"
+                "       .set    mips0                                   \n"
+                "       move    %2, %z4                                 \n"
+                "       .set    mips3                                   \n"
+                "       sc      %2, %1                                  \n"
+                "       beqzl   %2, 1b                                  \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                : "R" (*m), "Jr" (val)
+                : "memory");
+        } else if (kernel_uses_llsc) {
+                unsigned long dummy;
+
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       ll      %0, %3          # xchg_u32      \n"
+                        "       .set    mips0                           \n"
+                        "       move    %2, %z4                         \n"
+                        "       .set    mips3                           \n"
+                        "       sc      %2, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                        : "R" (*m), "Jr" (val)
+                        : "memory");
+                } while (unlikely(!dummy));
+        } else {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                retval = *m;
+                *m = val;
+                raw_local_irq_restore(flags);   /* implies memory barrier  */
+        }
+
+        smp_llsc_mb();
+
+        return retval;
+}
+
+#ifdef CONFIG_64BIT
+static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
+{
+        __u64 retval;
+
+        smp_mb__before_llsc();
+
+        if (kernel_uses_llsc && R10000_LLSC_WAR) {
+                unsigned long dummy;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:     lld     %0, %3                  # xchg_u64      \n"
+                "       move    %2, %z4                                 \n"
+                "       scd     %2, %1                                  \n"
+                "       beqzl   %2, 1b                                  \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                : "R" (*m), "Jr" (val)
+                : "memory");
+        } else if (kernel_uses_llsc) {
+                unsigned long dummy;
+
+                do {
+                        __asm__ __volatile__(
+                        "       .set    mips3                           \n"
+                        "       lld     %0, %3          # xchg_u64      \n"
+                        "       move    %2, %z4                         \n"
+                        "       scd     %2, %1                          \n"
+                        "       .set    mips0                           \n"
+                        : "=&r" (retval), "=m" (*m), "=&r" (dummy)
+                        : "R" (*m), "Jr" (val)
+                        : "memory");
+                } while (unlikely(!dummy));
+        } else {
+                unsigned long flags;
+
+                raw_local_irq_save(flags);
+                retval = *m;
+                *m = val;
+                raw_local_irq_restore(flags);   /* implies memory barrier  */
+        }
+
+        smp_llsc_mb();
+
+        return retval;
+}
+#else
+extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
+#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
+#endif
+
+static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
+{
+        switch (size) {
+        case 4:
+                return __xchg_u32(ptr, x);
+        case 8:
+                return __xchg_u64(ptr, x);
+        }
+
+        return x;
+}
+
+#define xchg(ptr, x)                                                    \
+({                                                                      \
+        BUILD_BUG_ON(sizeof(*(ptr)) & ~0xc);                            \
+                                                                        \
+        ((__typeof__(*(ptr)))                                           \
+                __xchg((unsigned long)(x), (ptr), sizeof(*(ptr))));     \
+})
+
+extern void set_handler(unsigned long offset, void *addr, unsigned long len);
+extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
+
+typedef void (*vi_handler_t)(void);
+extern void *set_vi_handler(int n, vi_handler_t addr);
+
+extern void *set_except_vector(int n, void *addr);
+extern unsigned long ebase;
+extern void per_cpu_trap_init(void);
+
+/*
+ * See include/asm-ia64/system.h; prevents deadlock on SMP
+ * systems.
+ */
+#define __ARCH_WANT_UNLOCKED_CTXSW
+
+extern unsigned long arch_align_stack(unsigned long sp);
+
+#endif /* _ASM_SYSTEM_H */
diff --git a/arch/mips/include/asm/termbits.h b/arch/mips/include/asm/termbits.h
new file mode 100644
index 00000000000..76630b396fa
--- /dev/null
+++ b/arch/mips/include/asm/termbits.h
@@ -0,0 +1,227 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 1995, 96, 99, 2001, 06 Ralf Baechle
+ * Copyright (C) 1999 Silicon Graphics, Inc.
+ * Copyright (C) 2001 MIPS Technologies, Inc.
+ */
+#ifndef _ASM_TERMBITS_H
+#define _ASM_TERMBITS_H
+
+#include <linux/posix_types.h>
+
+typedef unsigned char cc_t;
+typedef unsigned int speed_t;
+typedef unsigned int tcflag_t;
+
+/*
+ * The ABI says nothing about NCC but seems to use NCCS as
+ * replacement for it in struct termio
+ */
+#define NCCS    23
+struct termios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+};
+
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+/* c_cc characters */
+#define VINTR            0              /* Interrupt character [ISIG].  */
+#define VQUIT            1              /* Quit character [ISIG].  */
+#define VERASE           2              /* Erase character [ICANON].  */
+#define VKILL            3              /* Kill-line character [ICANON].  */
+#define VMIN             4              /* Minimum number of bytes read at once [!ICANON].  */
+#define VTIME            5              /* Time-out value (tenths of a second) [!ICANON].  */
+#define VEOL2            6              /* Second EOL character [ICANON].  */
+#define VSWTC            7              /* ??? */
+#define VSWTCH          VSWTC
+#define VSTART           8              /* Start (X-ON) character [IXON, IXOFF].  */
+#define VSTOP            9              /* Stop (X-OFF) character [IXON, IXOFF].  */
+#define VSUSP           10              /* Suspend character [ISIG].  */
+#if 0
+/*
+ * VDSUSP is not supported
+ */
+#define VDSUSP          11              /* Delayed suspend character [ISIG].  */
+#endif
+#define VREPRINT        12              /* Reprint-line character [ICANON].  */
+#define VDISCARD        13              /* Discard character [IEXTEN].  */
+#define VWERASE         14              /* Word-erase character [ICANON].  */
+#define VLNEXT          15              /* Literal-next character [IEXTEN].  */
+#define VEOF            16              /* End-of-file character [ICANON].  */
+#define VEOL            17              /* End-of-line character [ICANON].  */
+
+/* c_iflag bits */
+#define IGNBRK  0000001         /* Ignore break condition.  */
+#define BRKINT  0000002         /* Signal interrupt on break.  */
+#define IGNPAR  0000004         /* Ignore characters with parity errors.  */
+#define PARMRK  0000010         /* Mark parity and framing errors.  */
+#define INPCK   0000020         /* Enable input parity check.  */
+#define ISTRIP  0000040         /* Strip 8th bit off characters.  */
+#define INLCR   0000100         /* Map NL to CR on input.  */
+#define IGNCR   0000200         /* Ignore CR.  */
+#define ICRNL   0000400         /* Map CR to NL on input.  */
+#define IUCLC   0001000         /* Map upper case to lower case on input.  */
+#define IXON    0002000         /* Enable start/stop output control.  */
+#define IXANY   0004000         /* Any character will restart after stop.  */
+#define IXOFF   0010000         /* Enable start/stop input control.  */
+#define IMAXBEL 0020000         /* Ring bell when input queue is full.  */
+#define IUTF8   0040000         /* Input is UTF-8 */
+
+/* c_oflag bits */
+#define OPOST   0000001         /* Perform output processing.  */
+#define OLCUC   0000002         /* Map lower case to upper case on output.  */
+#define ONLCR   0000004         /* Map NL to CR-NL on output.  */
+#define OCRNL   0000010
+#define ONOCR   0000020
+#define ONLRET  0000040
+#define OFILL   0000100
+#define OFDEL   0000200
+#define NLDLY   0000400
+#define   NL0   0000000
+#define   NL1   0000400
+#define CRDLY   0003000
+#define   CR0   0000000
+#define   CR1   0001000
+#define   CR2   0002000
+#define   CR3   0003000
+#define TABDLY  0014000
+#define   TAB0  0000000
+#define   TAB1  0004000
+#define   TAB2  0010000
+#define   TAB3  0014000
+#define   XTABS 0014000
+#define BSDLY   0020000
+#define   BS0   0000000
+#define   BS1   0020000
+#define VTDLY   0040000
+#define   VT0   0000000
+#define   VT1   0040000
+#define FFDLY   0100000
+#define   FF0   0000000
+#define   FF1   0100000
+/*
+#define PAGEOUT ???
+#define WRAP    ???
+ */
+
+/* c_cflag bit meaning */
+#define CBAUD   0010017
+#define  B0     0000000         /* hang up */
+#define  B50    0000001
+#define  B75    0000002
+#define  B110   0000003
+#define  B134   0000004
+#define  B150   0000005
+#define  B200   0000006
+#define  B300   0000007
+#define  B600   0000010
+#define  B1200  0000011
+#define  B1800  0000012
+#define  B2400  0000013
+#define  B4800  0000014
+#define  B9600  0000015
+#define  B19200 0000016
+#define  B38400 0000017
+#define EXTA B19200
+#define EXTB B38400
+#define CSIZE   0000060         /* Number of bits per byte (mask).  */
+#define   CS5   0000000         /* 5 bits per byte.  */
+#define   CS6   0000020         /* 6 bits per byte.  */
+#define   CS7   0000040         /* 7 bits per byte.  */
+#define   CS8   0000060         /* 8 bits per byte.  */
+#define CSTOPB  0000100         /* Two stop bits instead of one.  */
+#define CREAD   0000200         /* Enable receiver.  */
+#define PARENB  0000400         /* Parity enable.  */
+#define PARODD  0001000         /* Odd parity instead of even.  */
+#define HUPCL   0002000         /* Hang up on last close.  */
+#define CLOCAL  0004000         /* Ignore modem status lines.  */
+#define CBAUDEX 0010000
+#define    BOTHER 0010000
+#define    B57600 0010001
+#define   B115200 0010002
+#define   B230400 0010003
+#define   B460800 0010004
+#define   B500000 0010005
+#define   B576000 0010006
+#define   B921600 0010007
+#define  B1000000 0010010
+#define  B1152000 0010011
+#define  B1500000 0010012
+#define  B2000000 0010013
+#define  B2500000 0010014
+#define  B3000000 0010015
+#define  B3500000 0010016
+#define  B4000000 0010017
+#define CIBAUD    002003600000  /* input baud rate */
+#define CMSPAR    010000000000  /* mark or space (stick) parity */
+#define CRTSCTS   020000000000  /* flow control */
+
+#define IBSHIFT 16              /* Shift from CBAUD to CIBAUD */
+
+/* c_lflag bits */
+#define ISIG    0000001         /* Enable signals.  */
+#define ICANON  0000002         /* Do erase and kill processing.  */
+#define XCASE   0000004
+#define ECHO    0000010         /* Enable echo.  */
+#define ECHOE   0000020         /* Visual erase for ERASE.  */
+#define ECHOK   0000040         /* Echo NL after KILL.  */
+#define ECHONL  0000100         /* Echo NL even if ECHO is off.  */
+#define NOFLSH  0000200         /* Disable flush after interrupt.  */
+#define IEXTEN  0000400         /* Enable DISCARD and LNEXT.  */
+#define ECHOCTL 0001000         /* Echo control characters as ^X.  */
+#define ECHOPRT 0002000         /* Hardcopy visual erase.  */
+#define ECHOKE  0004000         /* Visual erase for KILL.  */
+#define FLUSHO  0020000
+#define PENDIN  0040000         /* Retype pending input (state).  */
+#define TOSTOP  0100000         /* Send SIGTTOU for background output.  */
+#define ITOSTOP TOSTOP
+#define EXTPROC 0200000         /* External processing on pty */
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
+
+/* tcflow() and TCXONC use these */
+#define TCOOFF          0       /* Suspend output.  */
+#define TCOON           1       /* Restart suspended output.  */
+#define TCIOFF          2       /* Send a STOP character.  */
+#define TCION           3       /* Send a START character.  */
+
+/* tcflush() and TCFLSH use these */
+#define TCIFLUSH        0       /* Discard data received but not yet read.  */
+#define TCOFLUSH        1       /* Discard data written but not yet sent.  */
+#define TCIOFLUSH       2       /* Discard all pending data.  */
+
+/* tcsetattr uses these */
+#define TCSANOW         TCSETS  /* Change immediately.  */
+#define TCSADRAIN       TCSETSW /* Change when pending output is written.  */
+#define TCSAFLUSH       TCSETSF /* Flush pending input before changing.  */
+
+#endif /* _ASM_TERMBITS_H */
diff --git a/arch/mips/include/asm/titan_dep.h b/arch/mips/include/asm/titan_dep.h
new file mode 100644
index 00000000000..fee1908c65d
--- /dev/null
+++ b/arch/mips/include/asm/titan_dep.h
@@ -0,0 +1,231 @@
+/*
+ * Copyright 2003 PMC-Sierra
+ * Author: Manish Lachwani (lachwani@pmc-sierra.com)
+ *
+ * Board specific definititions for the PMC-Sierra Yosemite
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __TITAN_DEP_H__
+#define __TITAN_DEP_H__
+
+#include <asm/addrspace.h>              /* for KSEG1ADDR() */
+#include <asm/byteorder.h>              /* for cpu_to_le32() */
+
+#define TITAN_READ(ofs)                                                 \
+        (*(volatile u32 *)(ocd_base+(ofs)))
+#define TITAN_READ_16(ofs)                                              \
+        (*(volatile u16 *)(ocd_base+(ofs)))
+#define TITAN_READ_8(ofs)                                               \
+        (*(volatile u8 *)(ocd_base+(ofs)))
+
+#define TITAN_WRITE(ofs, data)                                          \
+        do { *(volatile u32 *)(ocd_base+(ofs)) = (data); } while (0)
+#define TITAN_WRITE_16(ofs, data)                                       \
+        do { *(volatile u16 *)(ocd_base+(ofs)) = (data); } while (0)
+#define TITAN_WRITE_8(ofs, data)                                        \
+        do { *(volatile u8 *)(ocd_base+(ofs)) = (data); } while (0)
+
+/*
+ * PCI specific defines
+ */
+#define TITAN_PCI_0_CONFIG_ADDRESS      0x780
+#define TITAN_PCI_0_CONFIG_DATA         0x784
+
+/*
+ * HT specific defines
+ */
+#define RM9000x2_HTLINK_REG             0xbb000644
+#define RM9000x2_BASE_ADDR              0xbb000000
+
+#define OCD_BASE                        0xfb000000UL
+#define OCD_SIZE                        0x3000UL
+
+extern unsigned long ocd_base;
+
+/*
+ * OCD Registers
+ */
+#define RM9000x2_OCD_LKB5               0x0128          /* Ethernet */
+#define RM9000x2_OCD_LKM5               0x012c
+
+#define RM9000x2_OCD_LKB7               0x0138          /* HT Region 0 */
+#define RM9000x2_OCD_LKM7               0x013c
+#define RM9000x2_OCD_LKB8               0x0140          /* HT Region 1 */
+#define RM9000x2_OCD_LKM8               0x0144
+
+#define RM9000x2_OCD_LKB9               0x0148          /* Local Bus */
+#define RM9000x2_OCD_LKM9               0x014c
+#define RM9000x2_OCD_LKB10              0x0150
+#define RM9000x2_OCD_LKM10              0x0154
+#define RM9000x2_OCD_LKB11              0x0158
+#define RM9000x2_OCD_LKM11              0x015c
+#define RM9000x2_OCD_LKB12              0x0160
+#define RM9000x2_OCD_LKM12              0x0164
+
+#define RM9000x2_OCD_LKB13              0x0168          /* Scratch RAM */
+#define RM9000x2_OCD_LKM13              0x016c
+
+#define RM9000x2_OCD_LPD0               0x0200          /* Local Bus */
+#define RM9000x2_OCD_LPD1               0x0210
+#define RM9000x2_OCD_LPD2               0x0220
+#define RM9000x2_OCD_LPD3               0x0230
+
+#define RM9000x2_OCD_HTDVID             0x0600  /* HT Device Header */
+#define RM9000x2_OCD_HTSC               0x0604
+#define RM9000x2_OCD_HTCCR              0x0608
+#define RM9000x2_OCD_HTBHL              0x060c
+#define RM9000x2_OCD_HTBAR0             0x0610
+#define RM9000x2_OCD_HTBAR1             0x0614
+#define RM9000x2_OCD_HTBAR2             0x0618
+#define RM9000x2_OCD_HTBAR3             0x061c
+#define RM9000x2_OCD_HTBAR4             0x0620
+#define RM9000x2_OCD_HTBAR5             0x0624
+#define RM9000x2_OCD_HTCBCPT            0x0628
+#define RM9000x2_OCD_HTSDVID            0x062c
+#define RM9000x2_OCD_HTXRA              0x0630
+#define RM9000x2_OCD_HTCAP1             0x0634
+#define RM9000x2_OCD_HTIL               0x063c
+
+#define RM9000x2_OCD_HTLCC              0x0640  /* HT Capability Block */
+#define RM9000x2_OCD_HTLINK             0x0644
+#define RM9000x2_OCD_HTFQREV            0x0648
+
+#define RM9000x2_OCD_HTERCTL            0x0668  /* HT Controller */
+#define RM9000x2_OCD_HTRXDB             0x066c
+#define RM9000x2_OCD_HTIMPED            0x0670
+#define RM9000x2_OCD_HTSWIMP            0x0674
+#define RM9000x2_OCD_HTCAL              0x0678
+
+#define RM9000x2_OCD_HTBAA30            0x0680
+#define RM9000x2_OCD_HTBAA54            0x0684
+#define RM9000x2_OCD_HTMASK0            0x0688
+#define RM9000x2_OCD_HTMASK1            0x068c
+#define RM9000x2_OCD_HTMASK2            0x0690
+#define RM9000x2_OCD_HTMASK3            0x0694
+#define RM9000x2_OCD_HTMASK4            0x0698
+#define RM9000x2_OCD_HTMASK5            0x069c
+
+#define RM9000x2_OCD_HTIFCTL            0x06a0
+#define RM9000x2_OCD_HTPLL              0x06a4
+
+#define RM9000x2_OCD_HTSRI              0x06b0
+#define RM9000x2_OCD_HTRXNUM            0x06b4
+#define RM9000x2_OCD_HTTXNUM            0x06b8
+
+#define RM9000x2_OCD_HTTXCNT            0x06c8
+
+#define RM9000x2_OCD_HTERROR            0x06d8
+#define RM9000x2_OCD_HTRCRCE            0x06dc
+#define RM9000x2_OCD_HTEOI              0x06e0
+
+#define RM9000x2_OCD_CRCR               0x06f0
+
+#define RM9000x2_OCD_HTCFGA             0x06f8
+#define RM9000x2_OCD_HTCFGD             0x06fc
+
+#define RM9000x2_OCD_INTMSG             0x0a00
+
+#define RM9000x2_OCD_INTPIN0            0x0a40
+#define RM9000x2_OCD_INTPIN1            0x0a44
+#define RM9000x2_OCD_INTPIN2            0x0a48
+#define RM9000x2_OCD_INTPIN3            0x0a4c
+#define RM9000x2_OCD_INTPIN4            0x0a50
+#define RM9000x2_OCD_INTPIN5            0x0a54
+#define RM9000x2_OCD_INTPIN6            0x0a58
+#define RM9000x2_OCD_INTPIN7            0x0a5c
+#define RM9000x2_OCD_SEM                0x0a60
+#define RM9000x2_OCD_SEMSET             0x0a64
+#define RM9000x2_OCD_SEMCLR             0x0a68
+
+#define RM9000x2_OCD_TKT                0x0a70
+#define RM9000x2_OCD_TKTINC             0x0a74
+
+#define RM9000x2_OCD_NMICONFIG          0x0ac0          /* Interrupts */
+#define RM9000x2_OCD_INTP0PRI           0x1a80
+#define RM9000x2_OCD_INTP1PRI           0x1a80
+#define RM9000x2_OCD_INTP0STATUS0       0x1b00
+#define RM9000x2_OCD_INTP0MASK0         0x1b04
+#define RM9000x2_OCD_INTP0SET0          0x1b08
+#define RM9000x2_OCD_INTP0CLEAR0        0x1b0c
+#define RM9000x2_OCD_INTP0STATUS1       0x1b10
+#define RM9000x2_OCD_INTP0MASK1         0x1b14
+#define RM9000x2_OCD_INTP0SET1          0x1b18
+#define RM9000x2_OCD_INTP0CLEAR1        0x1b1c
+#define RM9000x2_OCD_INTP0STATUS2       0x1b20
+#define RM9000x2_OCD_INTP0MASK2         0x1b24
+#define RM9000x2_OCD_INTP0SET2          0x1b28
+#define RM9000x2_OCD_INTP0CLEAR2        0x1b2c
+#define RM9000x2_OCD_INTP0STATUS3       0x1b30
+#define RM9000x2_OCD_INTP0MASK3         0x1b34
+#define RM9000x2_OCD_INTP0SET3          0x1b38
+#define RM9000x2_OCD_INTP0CLEAR3        0x1b3c
+#define RM9000x2_OCD_INTP0STATUS4       0x1b40
+#define RM9000x2_OCD_INTP0MASK4         0x1b44
+#define RM9000x2_OCD_INTP0SET4          0x1b48
+#define RM9000x2_OCD_INTP0CLEAR4        0x1b4c
+#define RM9000x2_OCD_INTP0STATUS5       0x1b50
+#define RM9000x2_OCD_INTP0MASK5         0x1b54
+#define RM9000x2_OCD_INTP0SET5          0x1b58
+#define RM9000x2_OCD_INTP0CLEAR5        0x1b5c
+#define RM9000x2_OCD_INTP0STATUS6       0x1b60
+#define RM9000x2_OCD_INTP0MASK6         0x1b64
+#define RM9000x2_OCD_INTP0SET6          0x1b68
+#define RM9000x2_OCD_INTP0CLEAR6        0x1b6c
+#define RM9000x2_OCD_INTP0STATUS7       0x1b70
+#define RM9000x2_OCD_INTP0MASK7         0x1b74
+#define RM9000x2_OCD_INTP0SET7          0x1b78
+#define RM9000x2_OCD_INTP0CLEAR7        0x1b7c
+#define RM9000x2_OCD_INTP1STATUS0       0x2b00
+#define RM9000x2_OCD_INTP1MASK0         0x2b04
+#define RM9000x2_OCD_INTP1SET0          0x2b08
+#define RM9000x2_OCD_INTP1CLEAR0        0x2b0c
+#define RM9000x2_OCD_INTP1STATUS1       0x2b10
+#define RM9000x2_OCD_INTP1MASK1         0x2b14
+#define RM9000x2_OCD_INTP1SET1          0x2b18
+#define RM9000x2_OCD_INTP1CLEAR1        0x2b1c
+#define RM9000x2_OCD_INTP1STATUS2       0x2b20
+#define RM9000x2_OCD_INTP1MASK2         0x2b24
+#define RM9000x2_OCD_INTP1SET2          0x2b28
+#define RM9000x2_OCD_INTP1CLEAR2        0x2b2c
+#define RM9000x2_OCD_INTP1STATUS3       0x2b30
+#define RM9000x2_OCD_INTP1MASK3         0x2b34
+#define RM9000x2_OCD_INTP1SET3          0x2b38
+#define RM9000x2_OCD_INTP1CLEAR3        0x2b3c
+#define RM9000x2_OCD_INTP1STATUS4       0x2b40
+#define RM9000x2_OCD_INTP1MASK4         0x2b44
+#define RM9000x2_OCD_INTP1SET4          0x2b48
+#define RM9000x2_OCD_INTP1CLEAR4        0x2b4c
+#define RM9000x2_OCD_INTP1STATUS5       0x2b50
+#define RM9000x2_OCD_INTP1MASK5         0x2b54
+#define RM9000x2_OCD_INTP1SET5          0x2b58
+#define RM9000x2_OCD_INTP1CLEAR5        0x2b5c
+#define RM9000x2_OCD_INTP1STATUS6       0x2b60
+#define RM9000x2_OCD_INTP1MASK6         0x2b64
+#define RM9000x2_OCD_INTP1SET6          0x2b68
+#define RM9000x2_OCD_INTP1CLEAR6        0x2b6c
+#define RM9000x2_OCD_INTP1STATUS7       0x2b70
+#define RM9000x2_OCD_INTP1MASK7         0x2b74
+#define RM9000x2_OCD_INTP1SET7          0x2b78
+#define RM9000x2_OCD_INTP1CLEAR7        0x2b7c
+
+#define OCD_READ(reg)           (*(volatile unsigned int *)(ocd_base + (reg)))
+#define OCD_WRITE(reg, val)                                     \
+        do { *(volatile unsigned int *)(ocd_base + (reg)) = (val); } while (0)
+
+/*
+ * Hypertransport specific macros
+ */
+#define RM9K_WRITE(ofs, data)   *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs) = data
+#define RM9K_WRITE_8(ofs, data) *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) = data
+#define RM9K_WRITE_16(ofs, data) *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) = data
+
+#define RM9K_READ(ofs, val)     *(val) = *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs)
+#define RM9K_READ_8(ofs, val)   *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs)
+#define RM9K_READ_16(ofs, val)  *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs)
+
+#endif
diff --git a/arch/mips/jz4740/pwm.c b/arch/mips/jz4740/pwm.c
new file mode 100644
index 00000000000..a26a6faec9a
--- /dev/null
+++ b/arch/mips/jz4740/pwm.c
@@ -0,0 +1,177 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform PWM support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#include <linux/kernel.h>
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/pwm.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-jz4740/gpio.h>
+#include "timer.h"
+
+static struct clk *jz4740_pwm_clk;
+
+DEFINE_MUTEX(jz4740_pwm_mutex);
+
+struct pwm_device {
+        unsigned int id;
+        unsigned int gpio;
+        bool used;
+};
+
+static struct pwm_device jz4740_pwm_list[] = {
+        { 2, JZ_GPIO_PWM2, false },
+        { 3, JZ_GPIO_PWM3, false },
+        { 4, JZ_GPIO_PWM4, false },
+        { 5, JZ_GPIO_PWM5, false },
+        { 6, JZ_GPIO_PWM6, false },
+        { 7, JZ_GPIO_PWM7, false },
+};
+
+struct pwm_device *pwm_request(int id, const char *label)
+{
+        int ret = 0;
+        struct pwm_device *pwm;
+
+        if (id < 2 || id > 7 || !jz4740_pwm_clk)
+                return ERR_PTR(-ENODEV);
+
+        mutex_lock(&jz4740_pwm_mutex);
+
+        pwm = &jz4740_pwm_list[id - 2];
+        if (pwm->used)
+                ret = -EBUSY;
+        else
+                pwm->used = true;
+
+        mutex_unlock(&jz4740_pwm_mutex);
+
+        if (ret)
+                return ERR_PTR(ret);
+
+        ret = gpio_request(pwm->gpio, label);
+
+        if (ret) {
+                printk(KERN_ERR "Failed to request pwm gpio: %d\n", ret);
+                pwm->used = false;
+                return ERR_PTR(ret);
+        }
+
+        jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_PWM);
+
+        jz4740_timer_start(id);
+
+        return pwm;
+}
+
+void pwm_free(struct pwm_device *pwm)
+{
+        pwm_disable(pwm);
+        jz4740_timer_set_ctrl(pwm->id, 0);
+
+        jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_NONE);
+        gpio_free(pwm->gpio);
+
+        jz4740_timer_stop(pwm->id);
+
+        pwm->used = false;
+}
+
+int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
+{
+        unsigned long long tmp;
+        unsigned long period, duty;
+        unsigned int prescaler = 0;
+        unsigned int id = pwm->id;
+        uint16_t ctrl;
+        bool is_enabled;
+
+        if (duty_ns < 0 || duty_ns > period_ns)
+                return -EINVAL;
+
+        tmp = (unsigned long long)clk_get_rate(jz4740_pwm_clk) * period_ns;
+        do_div(tmp, 1000000000);
+        period = tmp;
+
+        while (period > 0xffff && prescaler < 6) {
+                period >>= 2;
+                ++prescaler;
+        }
+
+        if (prescaler == 6)
+                return -EINVAL;
+
+        tmp = (unsigned long long)period * duty_ns;
+        do_div(tmp, period_ns);
+        duty = period - tmp;
+
+        if (duty >= period)
+                duty = period - 1;
+
+        is_enabled = jz4740_timer_is_enabled(id);
+        if (is_enabled)
+                pwm_disable(pwm);
+
+        jz4740_timer_set_count(id, 0);
+        jz4740_timer_set_duty(id, duty);
+        jz4740_timer_set_period(id, period);
+
+        ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT |
+                JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN;
+
+        jz4740_timer_set_ctrl(id, ctrl);
+
+        if (is_enabled)
+                pwm_enable(pwm);
+
+        return 0;
+}
+
+int pwm_enable(struct pwm_device *pwm)
+{
+        uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id);
+
+        ctrl |= JZ_TIMER_CTRL_PWM_ENABLE;
+        jz4740_timer_set_ctrl(pwm->id, ctrl);
+        jz4740_timer_enable(pwm->id);
+
+        return 0;
+}
+
+void pwm_disable(struct pwm_device *pwm)
+{
+        uint32_t ctrl = jz4740_timer_get_ctrl(pwm->id);
+
+        ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE;
+        jz4740_timer_disable(pwm->id);
+        jz4740_timer_set_ctrl(pwm->id, ctrl);
+}
+
+static int __init jz4740_pwm_init(void)
+{
+        int ret = 0;
+
+        jz4740_pwm_clk = clk_get(NULL, "ext");
+
+        if (IS_ERR(jz4740_pwm_clk)) {
+                ret = PTR_ERR(jz4740_pwm_clk);
+                jz4740_pwm_clk = NULL;
+        }
+
+        return ret;
+}
+subsys_initcall(jz4740_pwm_init);
diff --git a/arch/mips/jz4740/timer.h b/arch/mips/jz4740/timer.h
new file mode 100644
index 00000000000..fca3994f2e6
--- /dev/null
+++ b/arch/mips/jz4740/timer.h
@@ -0,0 +1,136 @@
+/*
+ *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
+ *  JZ4740 platform timer support
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under  the terms of the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the License, or (at your
+ *  option) any later version.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+
+#ifndef __MIPS_JZ4740_TIMER_H__
+#define __MIPS_JZ4740_TIMER_H__
+
+#include <linux/module.h>
+#include <linux/io.h>
+
+#define JZ_REG_TIMER_STOP               0x0C
+#define JZ_REG_TIMER_STOP_SET           0x1C
+#define JZ_REG_TIMER_STOP_CLEAR         0x2C
+#define JZ_REG_TIMER_ENABLE             0x00
+#define JZ_REG_TIMER_ENABLE_SET         0x04
+#define JZ_REG_TIMER_ENABLE_CLEAR       0x08
+#define JZ_REG_TIMER_FLAG               0x10
+#define JZ_REG_TIMER_FLAG_SET           0x14
+#define JZ_REG_TIMER_FLAG_CLEAR         0x18
+#define JZ_REG_TIMER_MASK               0x20
+#define JZ_REG_TIMER_MASK_SET           0x24
+#define JZ_REG_TIMER_MASK_CLEAR         0x28
+
+#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x30)
+#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x34)
+#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x38)
+#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x3C)
+
+#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
+#define JZ_TIMER_IRQ_FULL(x) BIT(x)
+
+#define JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN      BIT(9)
+#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW            BIT(8)
+#define JZ_TIMER_CTRL_PWM_ENABLE                BIT(7)
+#define JZ_TIMER_CTRL_PRESCALE_MASK             0x1c
+#define JZ_TIMER_CTRL_PRESCALE_OFFSET           0x3
+#define JZ_TIMER_CTRL_PRESCALE_1                (0 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_4                (1 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_16               (2 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_64               (3 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_256              (4 << 3)
+#define JZ_TIMER_CTRL_PRESCALE_1024             (5 << 3)
+
+#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
+
+#define JZ_TIMER_CTRL_SRC_EXT           BIT(2)
+#define JZ_TIMER_CTRL_SRC_RTC           BIT(1)
+#define JZ_TIMER_CTRL_SRC_PCLK          BIT(0)
+
+extern void __iomem *jz4740_timer_base;
+void __init jz4740_timer_init(void);
+
+static inline void jz4740_timer_stop(unsigned int timer)
+{
+        writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
+}
+
+static inline void jz4740_timer_start(unsigned int timer)
+{
+        writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
+}
+
+static inline bool jz4740_timer_is_enabled(unsigned int timer)
+{
+        return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
+}
+
+static inline void jz4740_timer_enable(unsigned int timer)
+{
+        writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
+}
+
+static inline void jz4740_timer_disable(unsigned int timer)
+{
+        writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
+}
+
+
+static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
+{
+        writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
+}
+
+static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
+{
+        writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
+}
+
+static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
+{
+        writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
+}
+
+static inline uint16_t jz4740_timer_get_count(unsigned int timer)
+{
+        return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
+}
+
+static inline void jz4740_timer_ack_full(unsigned int timer)
+{
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
+}
+
+static inline void jz4740_timer_irq_full_enable(unsigned int timer)
+{
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
+}
+
+static inline void jz4740_timer_irq_full_disable(unsigned int timer)
+{
+        writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
+}
+
+static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
+{
+        writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
+}
+
+static inline uint16_t jz4740_timer_get_ctrl(unsigned int timer)
+{
+        return readw(jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
+}
+
+#endif
diff --git a/arch/mips/kernel/cpufreq/loongson2_clock.c b/arch/mips/kernel/cpufreq/loongson2_clock.c
new file mode 100644
index 00000000000..cefc6e259ba
--- /dev/null
+++ b/arch/mips/kernel/cpufreq/loongson2_clock.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2006 - 2008 Lemote Inc. & Insititute of Computing Technology
+ * Author: Yanhua, yanh@lemote.com
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/cpufreq.h>
+#include <linux/platform_device.h>
+
+#include <asm/clock.h>
+
+#include <loongson.h>
+
+static LIST_HEAD(clock_list);
+static DEFINE_SPINLOCK(clock_lock);
+static DEFINE_MUTEX(clock_list_sem);
+
+/* Minimum CLK support */
+enum {
+        DC_ZERO, DC_25PT = 2, DC_37PT, DC_50PT, DC_62PT, DC_75PT,
+        DC_87PT, DC_DISABLE, DC_RESV
+};
+
+struct cpufreq_frequency_table loongson2_clockmod_table[] = {
+        {DC_RESV, CPUFREQ_ENTRY_INVALID},
+        {DC_ZERO, CPUFREQ_ENTRY_INVALID},
+        {DC_25PT, 0},
+        {DC_37PT, 0},
+        {DC_50PT, 0},
+        {DC_62PT, 0},
+        {DC_75PT, 0},
+        {DC_87PT, 0},
+        {DC_DISABLE, 0},
+        {DC_RESV, CPUFREQ_TABLE_END},
+};
+EXPORT_SYMBOL_GPL(loongson2_clockmod_table);
+
+static struct clk cpu_clk = {
+        .name = "cpu_clk",
+        .flags = CLK_ALWAYS_ENABLED | CLK_RATE_PROPAGATES,
+        .rate = 800000000,
+};
+
+struct clk *clk_get(struct device *dev, const char *id)
+{
+        return &cpu_clk;
+}
+EXPORT_SYMBOL(clk_get);
+
+static void propagate_rate(struct clk *clk)
+{
+        struct clk *clkp;
+
+        list_for_each_entry(clkp, &clock_list, node) {
+                if (likely(clkp->parent != clk))
+                        continue;
+                if (likely(clkp->ops && clkp->ops->recalc))
+                        clkp->ops->recalc(clkp);
+                if (unlikely(clkp->flags & CLK_RATE_PROPAGATES))
+                        propagate_rate(clkp);
+        }
+}
+
+int clk_enable(struct clk *clk)
+{
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return (unsigned long)clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+void clk_put(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_put);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        return clk_set_rate_ex(clk, rate, 0);
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
+{
+        int ret = 0;
+        int regval;
+        int i;
+
+        if (likely(clk->ops && clk->ops->set_rate)) {
+                unsigned long flags;
+
+                spin_lock_irqsave(&clock_lock, flags);
+                ret = clk->ops->set_rate(clk, rate, algo_id);
+                spin_unlock_irqrestore(&clock_lock, flags);
+        }
+
+        if (unlikely(clk->flags & CLK_RATE_PROPAGATES))
+                propagate_rate(clk);
+
+        for (i = 0; loongson2_clockmod_table[i].frequency != CPUFREQ_TABLE_END;
+             i++) {
+                if (loongson2_clockmod_table[i].frequency ==
+                    CPUFREQ_ENTRY_INVALID)
+                        continue;
+                if (rate == loongson2_clockmod_table[i].frequency)
+                        break;
+        }
+        if (rate != loongson2_clockmod_table[i].frequency)
+                return -ENOTSUPP;
+
+        clk->rate = rate;
+
+        regval = LOONGSON_CHIPCFG0;
+        regval = (regval & ~0x7) | (loongson2_clockmod_table[i].index - 1);
+        LOONGSON_CHIPCFG0 = regval;
+
+        return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate_ex);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        if (likely(clk->ops && clk->ops->round_rate)) {
+                unsigned long flags, rounded;
+
+                spin_lock_irqsave(&clock_lock, flags);
+                rounded = clk->ops->round_rate(clk, rate);
+                spin_unlock_irqrestore(&clock_lock, flags);
+
+                return rounded;
+        }
+
+        return rate;
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+/*
+ * This is the simple version of Loongson-2 wait, Maybe we need do this in
+ * interrupt disabled content
+ */
+
+DEFINE_SPINLOCK(loongson2_wait_lock);
+void loongson2_cpu_wait(void)
+{
+        u32 cpu_freq;
+        unsigned long flags;
+
+        spin_lock_irqsave(&loongson2_wait_lock, flags);
+        cpu_freq = LOONGSON_CHIPCFG0;
+        LOONGSON_CHIPCFG0 &= ~0x7;      /* Put CPU into wait mode */
+        LOONGSON_CHIPCFG0 = cpu_freq;   /* Restore CPU state */
+        spin_unlock_irqrestore(&loongson2_wait_lock, flags);
+}
+EXPORT_SYMBOL_GPL(loongson2_cpu_wait);
+
+MODULE_AUTHOR("Yanhua <yanh@lemote.com>");
+MODULE_DESCRIPTION("cpufreq driver for Loongson 2F");
+MODULE_LICENSE("GPL");
diff --git a/arch/mips/kernel/init_task.c b/arch/mips/kernel/init_task.c
new file mode 100644
index 00000000000..6d6ca530589
--- /dev/null
+++ b/arch/mips/kernel/init_task.c
@@ -0,0 +1,35 @@
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/init_task.h>
+#include <linux/fs.h>
+#include <linux/mqueue.h>
+
+#include <asm/thread_info.h>
+#include <asm/uaccess.h>
+#include <asm/pgtable.h>
+
+static struct signal_struct init_signals = INIT_SIGNALS(init_signals);
+static struct sighand_struct init_sighand = INIT_SIGHAND(init_sighand);
+/*
+ * Initial thread structure.
+ *
+ * We need to make sure that this is 8192-byte aligned due to the
+ * way process stacks are handled. This is done by making sure
+ * the linker maps this in the .text segment right after head.S,
+ * and making head.S ensure the proper alignment.
+ *
+ * The things we do for performance..
+ */
+union thread_union init_thread_union __init_task_data
+        __attribute__((__aligned__(THREAD_SIZE))) =
+                { INIT_THREAD_INFO(init_task) };
+
+/*
+ * Initial task structure.
+ *
+ * All other task structs will be allocated on slabs in fork.c
+ */
+struct task_struct init_task = INIT_TASK(init_task);
+
+EXPORT_SYMBOL(init_task);
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
new file mode 100644
index 00000000000..38874a4b925
--- /dev/null
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2003 Ralf Baechle
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Handler for RM9000 extended interrupts.  These are a non-standard
+ * feature so we handle them separately from standard interrupts.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+
+static inline void unmask_rm9k_irq(struct irq_data *d)
+{
+        set_c0_intcontrol(0x1000 << (d->irq - RM9K_CPU_IRQ_BASE));
+}
+
+static inline void mask_rm9k_irq(struct irq_data *d)
+{
+        clear_c0_intcontrol(0x1000 << (d->irq - RM9K_CPU_IRQ_BASE));
+}
+
+static inline void rm9k_cpu_irq_enable(struct irq_data *d)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        unmask_rm9k_irq(d);
+        local_irq_restore(flags);
+}
+
+/*
+ * Performance counter interrupts are global on all processors.
+ */
+static void local_rm9k_perfcounter_irq_startup(void *args)
+{
+        rm9k_cpu_irq_enable(args);
+}
+
+static unsigned int rm9k_perfcounter_irq_startup(struct irq_data *d)
+{
+        on_each_cpu(local_rm9k_perfcounter_irq_startup, d, 1);
+
+        return 0;
+}
+
+static void local_rm9k_perfcounter_irq_shutdown(void *args)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        mask_rm9k_irq(args);
+        local_irq_restore(flags);
+}
+
+static void rm9k_perfcounter_irq_shutdown(struct irq_data *d)
+{
+        on_each_cpu(local_rm9k_perfcounter_irq_shutdown, d, 1);
+}
+
+static struct irq_chip rm9k_irq_controller = {
+        .name = "RM9000",
+        .irq_ack = mask_rm9k_irq,
+        .irq_mask = mask_rm9k_irq,
+        .irq_mask_ack = mask_rm9k_irq,
+        .irq_unmask = unmask_rm9k_irq,
+        .irq_eoi = unmask_rm9k_irq
+};
+
+static struct irq_chip rm9k_perfcounter_irq = {
+        .name = "RM9000",
+        .irq_startup = rm9k_perfcounter_irq_startup,
+        .irq_shutdown = rm9k_perfcounter_irq_shutdown,
+        .irq_ack = mask_rm9k_irq,
+        .irq_mask = mask_rm9k_irq,
+        .irq_mask_ack = mask_rm9k_irq,
+        .irq_unmask = unmask_rm9k_irq,
+};
+
+unsigned int rm9000_perfcount_irq;
+
+EXPORT_SYMBOL(rm9000_perfcount_irq);
+
+void __init rm9k_cpu_irq_init(void)
+{
+        int base = RM9K_CPU_IRQ_BASE;
+        int i;
+
+        clear_c0_intcontrol(0x0000f000);                /* Mask all */
+
+        for (i = base; i < base + 4; i++)
+                irq_set_chip_and_handler(i, &rm9k_irq_controller,
+                                         handle_level_irq);
+
+        rm9000_perfcount_irq = base + 1;
+        irq_set_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
+                                 handle_percpu_irq);
+}
diff --git a/arch/mips/kernel/kspd.c b/arch/mips/kernel/kspd.c
new file mode 100644
index 00000000000..29811f04339
--- /dev/null
+++ b/arch/mips/kernel/kspd.c
@@ -0,0 +1,423 @@
+/*
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/unistd.h>
+#include <linux/file.h>
+#include <linux/fdtable.h>
+#include <linux/fs.h>
+#include <linux/syscalls.h>
+#include <linux/workqueue.h>
+#include <linux/errno.h>
+#include <linux/list.h>
+
+#include <asm/vpe.h>
+#include <asm/rtlx.h>
+#include <asm/kspd.h>
+
+static struct workqueue_struct *workqueue;
+static struct work_struct work;
+
+extern unsigned long cpu_khz;
+
+struct mtsp_syscall {
+        int cmd;
+        unsigned char abi;
+        unsigned char size;
+};
+
+struct mtsp_syscall_ret {
+        int retval;
+        int errno;
+};
+
+struct mtsp_syscall_generic {
+        int arg0;
+        int arg1;
+        int arg2;
+        int arg3;
+        int arg4;
+        int arg5;
+        int arg6;
+};
+
+static struct list_head kspd_notifylist;
+static int sp_stopping;
+
+/* these should match with those in the SDE kit */
+#define MTSP_SYSCALL_BASE       0
+#define MTSP_SYSCALL_EXIT       (MTSP_SYSCALL_BASE + 0)
+#define MTSP_SYSCALL_OPEN       (MTSP_SYSCALL_BASE + 1)
+#define MTSP_SYSCALL_READ       (MTSP_SYSCALL_BASE + 2)
+#define MTSP_SYSCALL_WRITE      (MTSP_SYSCALL_BASE + 3)
+#define MTSP_SYSCALL_CLOSE      (MTSP_SYSCALL_BASE + 4)
+#define MTSP_SYSCALL_LSEEK32    (MTSP_SYSCALL_BASE + 5)
+#define MTSP_SYSCALL_ISATTY     (MTSP_SYSCALL_BASE + 6)
+#define MTSP_SYSCALL_GETTIME    (MTSP_SYSCALL_BASE + 7)
+#define MTSP_SYSCALL_PIPEFREQ   (MTSP_SYSCALL_BASE + 8)
+#define MTSP_SYSCALL_GETTOD     (MTSP_SYSCALL_BASE + 9)
+#define MTSP_SYSCALL_IOCTL     (MTSP_SYSCALL_BASE + 10)
+
+#define MTSP_O_RDONLY           0x0000
+#define MTSP_O_WRONLY           0x0001
+#define MTSP_O_RDWR             0x0002
+#define MTSP_O_NONBLOCK         0x0004
+#define MTSP_O_APPEND           0x0008
+#define MTSP_O_SHLOCK           0x0010
+#define MTSP_O_EXLOCK           0x0020
+#define MTSP_O_ASYNC            0x0040
+/* XXX: check which of these is actually O_SYNC vs O_DSYNC */
+#define MTSP_O_FSYNC            O_SYNC
+#define MTSP_O_NOFOLLOW         0x0100
+#define MTSP_O_SYNC             0x0080
+#define MTSP_O_CREAT            0x0200
+#define MTSP_O_TRUNC            0x0400
+#define MTSP_O_EXCL             0x0800
+#define MTSP_O_BINARY           0x8000
+
+extern int tclimit;
+
+struct apsp_table  {
+        int sp;
+        int ap;
+};
+
+/* we might want to do the mode flags too */
+struct apsp_table open_flags_table[] = {
+        { MTSP_O_RDWR, O_RDWR },
+        { MTSP_O_WRONLY, O_WRONLY },
+        { MTSP_O_CREAT, O_CREAT },
+        { MTSP_O_TRUNC, O_TRUNC },
+        { MTSP_O_NONBLOCK, O_NONBLOCK },
+        { MTSP_O_APPEND, O_APPEND },
+        { MTSP_O_NOFOLLOW, O_NOFOLLOW }
+};
+
+struct apsp_table syscall_command_table[] = {
+        { MTSP_SYSCALL_OPEN, __NR_open },
+        { MTSP_SYSCALL_CLOSE, __NR_close },
+        { MTSP_SYSCALL_READ, __NR_read },
+        { MTSP_SYSCALL_WRITE, __NR_write },
+        { MTSP_SYSCALL_LSEEK32, __NR_lseek },
+        { MTSP_SYSCALL_IOCTL, __NR_ioctl }
+};
+
+static int sp_syscall(int num, int arg0, int arg1, int arg2, int arg3)
+{
+        register long int _num  __asm__("$2") = num;
+        register long int _arg0  __asm__("$4") = arg0;
+        register long int _arg1  __asm__("$5") = arg1;
+        register long int _arg2  __asm__("$6") = arg2;
+        register long int _arg3  __asm__("$7") = arg3;
+
+        mm_segment_t old_fs;
+
+        old_fs = get_fs();
+        set_fs(KERNEL_DS);
+
+        __asm__ __volatile__ (
+        "       syscall                                 \n"
+        : "=r" (_num), "=r" (_arg3)
+        : "r" (_num), "r" (_arg0), "r" (_arg1), "r" (_arg2), "r" (_arg3));
+
+        set_fs(old_fs);
+
+        /* $a3 is error flag */
+        if (_arg3)
+                return -_num;
+
+        return _num;
+}
+
+static int translate_syscall_command(int cmd)
+{
+        int i;
+        int ret = -1;
+
+        for (i = 0; i < ARRAY_SIZE(syscall_command_table); i++) {
+                if ((cmd == syscall_command_table[i].sp))
+                        return syscall_command_table[i].ap;
+        }
+
+        return ret;
+}
+
+static unsigned int translate_open_flags(int flags)
+{
+        int i;
+        unsigned int ret = 0;
+
+        for (i = 0; i < ARRAY_SIZE(open_flags_table); i++) {
+                if( (flags & open_flags_table[i].sp) ) {
+                        ret |= open_flags_table[i].ap;
+                }
+        }
+
+        return ret;
+}
+
+
+static int sp_setfsuidgid(uid_t uid, gid_t gid)
+{
+        struct cred *new;
+
+        new = prepare_creds();
+        if (!new)
+                return -ENOMEM;
+
+        new->fsuid = uid;
+        new->fsgid = gid;
+
+        commit_creds(new);
+
+        return 0;
+}
+
+/*
+ * Expects a request to be on the sysio channel. Reads it.  Decides whether
+ * its a linux syscall and runs it, or whatever.  Puts the return code back
+ * into the request and sends the whole thing back.
+ */
+void sp_work_handle_request(void)
+{
+        struct mtsp_syscall sc;
+        struct mtsp_syscall_generic generic;
+        struct mtsp_syscall_ret ret;
+        struct kspd_notifications *n;
+        unsigned long written;
+        mm_segment_t old_fs;
+        struct timeval tv;
+        struct timezone tz;
+        int err, cmd;
+
+        char *vcwd;
+        int size;
+
+        ret.retval = -1;
+
+        old_fs = get_fs();
+        set_fs(KERNEL_DS);
+
+        if (!rtlx_read(RTLX_CHANNEL_SYSIO, &sc, sizeof(struct mtsp_syscall))) {
+                set_fs(old_fs);
+                printk(KERN_ERR "Expected request but nothing to read\n");
+                return;
+        }
+
+        size = sc.size;
+
+        if (size) {
+                if (!rtlx_read(RTLX_CHANNEL_SYSIO, &generic, size)) {
+                        set_fs(old_fs);
+                        printk(KERN_ERR "Expected request but nothing to read\n");
+                        return;
+                }
+        }
+
+        /* Run the syscall at the privilege of the user who loaded the
+           SP program */
+
+        if (vpe_getuid(tclimit)) {
+                err = sp_setfsuidgid(vpe_getuid(tclimit), vpe_getgid(tclimit));
+                if (!err)
+                        pr_err("Change of creds failed\n");
+        }
+
+        switch (sc.cmd) {
+        /* needs the flags argument translating from SDE kit to
+           linux */
+        case MTSP_SYSCALL_PIPEFREQ:
+                ret.retval = cpu_khz * 1000;
+                ret.errno = 0;
+                break;
+
+        case MTSP_SYSCALL_GETTOD:
+                memset(&tz, 0, sizeof(tz));
+                if ((ret.retval = sp_syscall(__NR_gettimeofday, (int)&tv,
+                                             (int)&tz, 0, 0)) == 0)
+                        ret.retval = tv.tv_sec;
+                break;
+
+        case MTSP_SYSCALL_EXIT:
+                list_for_each_entry(n, &kspd_notifylist, list)
+                        n->kspd_sp_exit(tclimit);
+                sp_stopping = 1;
+
+                printk(KERN_DEBUG "KSPD got exit syscall from SP exitcode %d\n",
+                       generic.arg0);
+                break;
+
+        case MTSP_SYSCALL_OPEN:
+                generic.arg1 = translate_open_flags(generic.arg1);
+
+                vcwd = vpe_getcwd(tclimit);
+
+                /* change to cwd of the process that loaded the SP program */
+                old_fs = get_fs();
+                set_fs(KERNEL_DS);
+                sys_chdir(vcwd);
+                set_fs(old_fs);
+
+                sc.cmd = __NR_open;
+
+                /* fall through */
+
+        default:
+                if ((sc.cmd >= __NR_Linux) &&
+                    (sc.cmd <= (__NR_Linux +  __NR_Linux_syscalls)) )
+                        cmd = sc.cmd;
+                else
+                        cmd = translate_syscall_command(sc.cmd);
+
+                if (cmd >= 0) {
+                        ret.retval = sp_syscall(cmd, generic.arg0, generic.arg1,
+                                                generic.arg2, generic.arg3);
+                } else
+                        printk(KERN_WARNING
+                               "KSPD: Unknown SP syscall number %d\n", sc.cmd);
+                break;
+        } /* switch */
+
+        if (vpe_getuid(tclimit)) {
+                err = sp_setfsuidgid(0, 0);
+                if (!err)
+                        pr_err("restoring old creds failed\n");
+        }
+
+        old_fs = get_fs();
+        set_fs(KERNEL_DS);
+        written = rtlx_write(RTLX_CHANNEL_SYSIO, &ret, sizeof(ret));
+        set_fs(old_fs);
+        if (written < sizeof(ret))
+                printk("KSPD: sp_work_handle_request failed to send to SP\n");
+}
+
+static void sp_cleanup(void)
+{
+        struct files_struct *files = current->files;
+        int i, j;
+        struct fdtable *fdt;
+
+        j = 0;
+
+        /*
+         * It is safe to dereference the fd table without RCU or
+         * ->file_lock
+         */
+        fdt = files_fdtable(files);
+        for (;;) {
+                unsigned long set;
+                i = j * __NFDBITS;
+                if (i >= fdt->max_fds)
+                        break;
+                set = fdt->open_fds->fds_bits[j++];
+                while (set) {
+                        if (set & 1) {
+                                struct file * file = xchg(&fdt->fd[i], NULL);
+                                if (file)
+                                        filp_close(file, files);
+                        }
+                        i++;
+                        set >>= 1;
+                }
+        }
+
+        /* Put daemon cwd back to root to avoid umount problems */
+        sys_chdir("/");
+}
+
+static int channel_open;
+
+/* the work handler */
+static void sp_work(struct work_struct *unused)
+{
+        if (!channel_open) {
+                if( rtlx_open(RTLX_CHANNEL_SYSIO, 1) != 0) {
+                        printk("KSPD: unable to open sp channel\n");
+                        sp_stopping = 1;
+                } else {
+                        channel_open++;
+                        printk(KERN_DEBUG "KSPD: SP channel opened\n");
+                }
+        } else {
+                /* wait for some data, allow it to sleep */
+                rtlx_read_poll(RTLX_CHANNEL_SYSIO, 1);
+
+                /* Check we haven't been woken because we are stopping */
+                if (!sp_stopping)
+                        sp_work_handle_request();
+        }
+
+        if (!sp_stopping)
+                queue_work(workqueue, &work);
+        else
+                sp_cleanup();
+}
+
+static void startwork(int vpe)
+{
+        sp_stopping = channel_open = 0;
+
+        if (workqueue == NULL) {
+                if ((workqueue = create_singlethread_workqueue("kspd")) == NULL) {
+                        printk(KERN_ERR "unable to start kspd\n");
+                        return;
+                }
+
+                INIT_WORK(&work, sp_work);
+        }
+
+        queue_work(workqueue, &work);
+}
+
+static void stopwork(int vpe)
+{
+        sp_stopping = 1;
+
+        printk(KERN_DEBUG "KSPD: SP stopping\n");
+}
+
+void kspd_notify(struct kspd_notifications *notify)
+{
+        list_add(&notify->list, &kspd_notifylist);
+}
+
+static struct vpe_notifications notify;
+static int kspd_module_init(void)
+{
+        INIT_LIST_HEAD(&kspd_notifylist);
+
+        notify.start = startwork;
+        notify.stop = stopwork;
+        vpe_notify(tclimit, &notify);
+
+        return 0;
+}
+
+static void kspd_module_exit(void)
+{
+
+}
+
+module_init(kspd_module_init);
+module_exit(kspd_module_exit);
+
+MODULE_DESCRIPTION("MIPS KSPD");
+MODULE_AUTHOR("Elizabeth Oldham, MIPS Technologies, Inc.");
+MODULE_LICENSE("GPL");
diff --git a/arch/mips/lantiq/devices.c b/arch/mips/lantiq/devices.c
new file mode 100644
index 00000000000..44a36771c81
--- /dev/null
+++ b/arch/mips/lantiq/devices.c
@@ -0,0 +1,120 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/reboot.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/etherdevice.h>
+#include <linux/time.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+
+#include <lantiq_soc.h>
+
+#include "devices.h"
+
+/* nor flash */
+static struct resource ltq_nor_resource = {
+        .name   = "nor",
+        .start  = LTQ_FLASH_START,
+        .end    = LTQ_FLASH_START + LTQ_FLASH_MAX - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device ltq_nor = {
+        .name           = "ltq_nor",
+        .resource       = &ltq_nor_resource,
+        .num_resources  = 1,
+};
+
+void __init ltq_register_nor(struct physmap_flash_data *data)
+{
+        ltq_nor.dev.platform_data = data;
+        platform_device_register(&ltq_nor);
+}
+
+/* watchdog */
+static struct resource ltq_wdt_resource = {
+        .name   = "watchdog",
+        .start  = LTQ_WDT_BASE_ADDR,
+        .end    = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+void __init ltq_register_wdt(void)
+{
+        platform_device_register_simple("ltq_wdt", 0, &ltq_wdt_resource, 1);
+}
+
+/* asc ports */
+static struct resource ltq_asc0_resources[] = {
+        {
+                .name   = "asc0",
+                .start  = LTQ_ASC0_BASE_ADDR,
+                .end    = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        IRQ_RES(tx, LTQ_ASC_TIR(0)),
+        IRQ_RES(rx, LTQ_ASC_RIR(0)),
+        IRQ_RES(err, LTQ_ASC_EIR(0)),
+};
+
+static struct resource ltq_asc1_resources[] = {
+        {
+                .name   = "asc1",
+                .start  = LTQ_ASC1_BASE_ADDR,
+                .end    = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        IRQ_RES(tx, LTQ_ASC_TIR(1)),
+        IRQ_RES(rx, LTQ_ASC_RIR(1)),
+        IRQ_RES(err, LTQ_ASC_EIR(1)),
+};
+
+void __init ltq_register_asc(int port)
+{
+        switch (port) {
+        case 0:
+                platform_device_register_simple("ltq_asc", 0,
+                        ltq_asc0_resources, ARRAY_SIZE(ltq_asc0_resources));
+                break;
+        case 1:
+                platform_device_register_simple("ltq_asc", 1,
+                        ltq_asc1_resources, ARRAY_SIZE(ltq_asc1_resources));
+                break;
+        default:
+                break;
+        }
+}
+
+#ifdef CONFIG_PCI
+/* pci */
+static struct platform_device ltq_pci = {
+        .name           = "ltq_pci",
+        .num_resources  = 0,
+};
+
+void __init ltq_register_pci(struct ltq_pci_data *data)
+{
+        ltq_pci.dev.platform_data = data;
+        platform_device_register(&ltq_pci);
+}
+#else
+void __init ltq_register_pci(struct ltq_pci_data *data)
+{
+        pr_err("kernel is compiled without PCI support\n");
+}
+#endif
diff --git a/arch/mips/lantiq/devices.h b/arch/mips/lantiq/devices.h
new file mode 100644
index 00000000000..2947bb19a52
--- /dev/null
+++ b/arch/mips/lantiq/devices.h
@@ -0,0 +1,23 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _LTQ_DEVICES_H__
+#define _LTQ_DEVICES_H__
+
+#include <lantiq_platform.h>
+#include <linux/mtd/physmap.h>
+
+#define IRQ_RES(resname, irq) \
+        {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ}
+
+extern void ltq_register_nor(struct physmap_flash_data *data);
+extern void ltq_register_wdt(void);
+extern void ltq_register_asc(int port);
+extern void ltq_register_pci(struct ltq_pci_data *data);
+
+#endif
diff --git a/arch/mips/lantiq/machtypes.h b/arch/mips/lantiq/machtypes.h
new file mode 100644
index 00000000000..7e01b8c484e
--- /dev/null
+++ b/arch/mips/lantiq/machtypes.h
@@ -0,0 +1,20 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _LANTIQ_MACH_H__
+#define _LANTIQ_MACH_H__
+
+#include <asm/mips_machine.h>
+
+enum lantiq_mach_type {
+        LTQ_MACH_GENERIC = 0,
+        LTQ_MACH_EASY50712,     /* Danube evaluation board */
+        LTQ_MACH_EASY50601,     /* Amazon SE evaluation board */
+};
+
+#endif
diff --git a/arch/mips/lantiq/setup.c b/arch/mips/lantiq/setup.c
new file mode 100644
index 00000000000..9b8af77ed0f
--- /dev/null
+++ b/arch/mips/lantiq/setup.c
@@ -0,0 +1,66 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <asm/bootinfo.h>
+
+#include <lantiq_soc.h>
+
+#include "machtypes.h"
+#include "devices.h"
+#include "prom.h"
+
+void __init plat_mem_setup(void)
+{
+        /* assume 16M as default incase uboot fails to pass proper ramsize */
+        unsigned long memsize = 16;
+        char **envp = (char **) KSEG1ADDR(fw_arg2);
+
+        ioport_resource.start = IOPORT_RESOURCE_START;
+        ioport_resource.end = IOPORT_RESOURCE_END;
+        iomem_resource.start = IOMEM_RESOURCE_START;
+        iomem_resource.end = IOMEM_RESOURCE_END;
+
+        set_io_port_base((unsigned long) KSEG1);
+
+        while (*envp) {
+                char *e = (char *)KSEG1ADDR(*envp);
+                if (!strncmp(e, "memsize=", 8)) {
+                        e += 8;
+                        if (strict_strtoul(e, 0, &memsize))
+                                pr_warn("bad memsize specified\n");
+                }
+                envp++;
+        }
+        memsize *= 1024 * 1024;
+        add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
+}
+
+static int __init
+lantiq_setup(void)
+{
+        ltq_soc_setup();
+        mips_machine_setup();
+        return 0;
+}
+
+arch_initcall(lantiq_setup);
+
+static void __init
+lantiq_generic_init(void)
+{
+        /* Nothing to do */
+}
+
+MIPS_MACHINE(LTQ_MACH_GENERIC,
+             "Generic",
+             "Generic Lantiq based board",
+             lantiq_generic_init);
diff --git a/arch/mips/lantiq/xway/Kconfig b/arch/mips/lantiq/xway/Kconfig
new file mode 100644
index 00000000000..2b857de3662
--- /dev/null
+++ b/arch/mips/lantiq/xway/Kconfig
@@ -0,0 +1,23 @@
+if SOC_XWAY
+
+menu "MIPS Machine"
+
+config LANTIQ_MACH_EASY50712
+        bool "Easy50712 - Danube"
+        default y
+
+endmenu
+
+endif
+
+if SOC_AMAZON_SE
+
+menu "MIPS Machine"
+
+config LANTIQ_MACH_EASY50601
+        bool "Easy50601 - Amazon SE"
+        default y
+
+endmenu
+
+endif
diff --git a/arch/mips/lantiq/xway/clk-ase.c b/arch/mips/lantiq/xway/clk-ase.c
new file mode 100644
index 00000000000..22d823acd53
--- /dev/null
+++ b/arch/mips/lantiq/xway/clk-ase.c
@@ -0,0 +1,48 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+
+#include <asm/time.h>
+#include <asm/irq.h>
+#include <asm/div64.h>
+
+#include <lantiq_soc.h>
+
+/* cgu registers */
+#define LTQ_CGU_SYS     0x0010
+
+unsigned int ltq_get_io_region_clock(void)
+{
+        return CLOCK_133M;
+}
+EXPORT_SYMBOL(ltq_get_io_region_clock);
+
+unsigned int ltq_get_fpi_bus_clock(int fpi)
+{
+        return CLOCK_133M;
+}
+EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
+
+unsigned int ltq_get_cpu_hz(void)
+{
+        if (ltq_cgu_r32(LTQ_CGU_SYS) & (1 << 5))
+                return CLOCK_266M;
+        else
+                return CLOCK_133M;
+}
+EXPORT_SYMBOL(ltq_get_cpu_hz);
+
+unsigned int ltq_get_fpi_hz(void)
+{
+        return CLOCK_133M;
+}
+EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/xway/clk-xway.c b/arch/mips/lantiq/xway/clk-xway.c
new file mode 100644
index 00000000000..ddd39593c58
--- /dev/null
+++ b/arch/mips/lantiq/xway/clk-xway.c
@@ -0,0 +1,223 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+
+#include <asm/time.h>
+#include <asm/irq.h>
+#include <asm/div64.h>
+
+#include <lantiq_soc.h>
+
+static unsigned int ltq_ram_clocks[] = {
+        CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
+#define DDR_HZ ltq_ram_clocks[ltq_cgu_r32(LTQ_CGU_SYS) & 0x3]
+
+#define BASIC_FREQUENCY_1       35328000
+#define BASIC_FREQUENCY_2       36000000
+#define BASIS_REQUENCY_USB      12000000
+
+#define GET_BITS(x, msb, lsb) \
+        (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
+
+#define LTQ_CGU_PLL0_CFG        0x0004
+#define LTQ_CGU_PLL1_CFG        0x0008
+#define LTQ_CGU_PLL2_CFG        0x000C
+#define LTQ_CGU_SYS             0x0010
+#define LTQ_CGU_UPDATE          0x0014
+#define LTQ_CGU_IF_CLK          0x0018
+#define LTQ_CGU_OSC_CON         0x001C
+#define LTQ_CGU_SMD             0x0020
+#define LTQ_CGU_CT1SR           0x0028
+#define LTQ_CGU_CT2SR           0x002C
+#define LTQ_CGU_PCMCR           0x0030
+#define LTQ_CGU_PCI_CR          0x0034
+#define LTQ_CGU_PD_PC           0x0038
+#define LTQ_CGU_FMR             0x003C
+
+#define CGU_PLL0_PHASE_DIVIDER_ENABLE   \
+        (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 31))
+#define CGU_PLL0_BYPASS                 \
+        (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 30))
+#define CGU_PLL0_CFG_DSMSEL             \
+        (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 28))
+#define CGU_PLL0_CFG_FRAC_EN            \
+        (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & (1 << 27))
+#define CGU_PLL1_SRC                    \
+        (ltq_cgu_r32(LTQ_CGU_PLL1_CFG) & (1 << 31))
+#define CGU_PLL2_PHASE_DIVIDER_ENABLE   \
+        (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & (1 << 20))
+#define CGU_SYS_FPI_SEL                 (1 << 6)
+#define CGU_SYS_DDR_SEL                 0x3
+#define CGU_PLL0_SRC                    (1 << 29)
+
+#define CGU_PLL0_CFG_PLLK       GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 26, 17)
+#define CGU_PLL0_CFG_PLLN       GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 12, 6)
+#define CGU_PLL0_CFG_PLLM       GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL0_CFG), 5, 2)
+#define CGU_PLL2_SRC            GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 18, 17)
+#define CGU_PLL2_CFG_INPUT_DIV  GET_BITS(ltq_cgu_r32(LTQ_CGU_PLL2_CFG), 16, 13)
+
+static unsigned int ltq_get_pll0_fdiv(void);
+
+static inline unsigned int get_input_clock(int pll)
+{
+        switch (pll) {
+        case 0:
+                if (ltq_cgu_r32(LTQ_CGU_PLL0_CFG) & CGU_PLL0_SRC)
+                        return BASIS_REQUENCY_USB;
+                else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
+                        return BASIC_FREQUENCY_1;
+                else
+                        return BASIC_FREQUENCY_2;
+        case 1:
+                if (CGU_PLL1_SRC)
+                        return BASIS_REQUENCY_USB;
+                else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
+                        return BASIC_FREQUENCY_1;
+                else
+                        return BASIC_FREQUENCY_2;
+        case 2:
+                switch (CGU_PLL2_SRC) {
+                case 0:
+                        return ltq_get_pll0_fdiv();
+                case 1:
+                        return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
+                                BASIC_FREQUENCY_1 :
+                                BASIC_FREQUENCY_2;
+                case 2:
+                        return BASIS_REQUENCY_USB;
+                }
+        default:
+                return 0;
+        }
+}
+
+static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
+{
+        u64 res, clock = get_input_clock(pll);
+
+        res = num * clock;
+        do_div(res, den);
+        return res;
+}
+
+static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
+        unsigned int K)
+{
+        unsigned int num = ((N + 1) << 10) + K;
+        unsigned int den = (M + 1) << 10;
+
+        return cal_dsm(pll, num, den);
+}
+
+static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
+        unsigned int K)
+{
+        unsigned int num = ((N + 1) << 11) + K + 512;
+        unsigned int den = (M + 1) << 11;
+
+        return cal_dsm(pll, num, den);
+}
+
+static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
+        unsigned int K)
+{
+        unsigned int num = K >= 512 ?
+                ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
+        unsigned int den = (M + 1) << 12;
+
+        return cal_dsm(pll, num, den);
+}
+
+static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
+        unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
+{
+        if (!dsmsel)
+                return mash_dsm(pll, M, N, K);
+        else if (!phase_div_en)
+                return mash_dsm(pll, M, N, K);
+        else
+                return ssff_dsm_2(pll, M, N, K);
+}
+
+static inline unsigned int ltq_get_pll0_fosc(void)
+{
+        if (CGU_PLL0_BYPASS)
+                return get_input_clock(0);
+        else
+                return !CGU_PLL0_CFG_FRAC_EN
+                        ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0,
+                                CGU_PLL0_CFG_DSMSEL,
+                                CGU_PLL0_PHASE_DIVIDER_ENABLE)
+                        : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN,
+                                CGU_PLL0_CFG_PLLK, CGU_PLL0_CFG_DSMSEL,
+                                CGU_PLL0_PHASE_DIVIDER_ENABLE);
+}
+
+static unsigned int ltq_get_pll0_fdiv(void)
+{
+        unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
+
+        return (ltq_get_pll0_fosc() + (div >> 1)) / div;
+}
+
+unsigned int ltq_get_io_region_clock(void)
+{
+        unsigned int ret = ltq_get_pll0_fosc();
+
+        switch (ltq_cgu_r32(LTQ_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
+        default:
+        case 0:
+                return (ret + 1) / 2;
+        case 1:
+                return (ret * 2 + 2) / 5;
+        case 2:
+                return (ret + 1) / 3;
+        case 3:
+                return (ret + 2) / 4;
+        }
+}
+EXPORT_SYMBOL(ltq_get_io_region_clock);
+
+unsigned int ltq_get_fpi_bus_clock(int fpi)
+{
+        unsigned int ret = ltq_get_io_region_clock();
+
+        if ((fpi == 2) && (ltq_cgu_r32(LTQ_CGU_SYS) & CGU_SYS_FPI_SEL))
+                ret >>= 1;
+        return ret;
+}
+EXPORT_SYMBOL(ltq_get_fpi_bus_clock);
+
+unsigned int ltq_get_cpu_hz(void)
+{
+        switch (ltq_cgu_r32(LTQ_CGU_SYS) & 0xc) {
+        case 0:
+                return CLOCK_333M;
+        case 4:
+                return DDR_HZ;
+        case 8:
+                return DDR_HZ << 1;
+        default:
+                return DDR_HZ >> 1;
+        }
+}
+EXPORT_SYMBOL(ltq_get_cpu_hz);
+
+unsigned int ltq_get_fpi_hz(void)
+{
+        unsigned int ddr_clock = DDR_HZ;
+
+        if (ltq_cgu_r32(LTQ_CGU_SYS) & 0x40)
+                return ddr_clock >> 1;
+        return ddr_clock;
+}
+EXPORT_SYMBOL(ltq_get_fpi_hz);
diff --git a/arch/mips/lantiq/xway/devices.c b/arch/mips/lantiq/xway/devices.c
new file mode 100644
index 00000000000..d0e32ab2ea0
--- /dev/null
+++ b/arch/mips/lantiq/xway/devices.c
@@ -0,0 +1,119 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/mtd/physmap.h>
+#include <linux/kernel.h>
+#include <linux/reboot.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <linux/etherdevice.h>
+#include <linux/time.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+
+#include <lantiq_soc.h>
+#include <lantiq_irq.h>
+#include <lantiq_platform.h>
+
+#include "devices.h"
+
+/* gpio */
+static struct resource ltq_gpio_resource[] = {
+        {
+                .name   = "gpio0",
+                .start  = LTQ_GPIO0_BASE_ADDR,
+                .end    = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "gpio1",
+                .start  = LTQ_GPIO1_BASE_ADDR,
+                .end    = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .name   = "gpio2",
+                .start  = LTQ_GPIO2_BASE_ADDR,
+                .end    = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+
+void __init ltq_register_gpio(void)
+{
+        platform_device_register_simple("ltq_gpio", 0,
+                &ltq_gpio_resource[0], 1);
+        platform_device_register_simple("ltq_gpio", 1,
+                &ltq_gpio_resource[1], 1);
+
+        /* AR9 and VR9 have an extra gpio block */
+        if (ltq_is_ar9() || ltq_is_vr9()) {
+                platform_device_register_simple("ltq_gpio", 2,
+                        &ltq_gpio_resource[2], 1);
+        }
+}
+
+/* serial to parallel conversion */
+static struct resource ltq_stp_resource = {
+        .name   = "stp",
+        .start  = LTQ_STP_BASE_ADDR,
+        .end    = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+void __init ltq_register_gpio_stp(void)
+{
+        platform_device_register_simple("ltq_stp", 0, &ltq_stp_resource, 1);
+}
+
+/* asc ports - amazon se has its own serial mapping */
+static struct resource ltq_ase_asc_resources[] = {
+        {
+                .name   = "asc0",
+                .start  = LTQ_ASC1_BASE_ADDR,
+                .end    = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        IRQ_RES(tx, LTQ_ASC_ASE_TIR),
+        IRQ_RES(rx, LTQ_ASC_ASE_RIR),
+        IRQ_RES(err, LTQ_ASC_ASE_EIR),
+};
+
+void __init ltq_register_ase_asc(void)
+{
+        platform_device_register_simple("ltq_asc", 0,
+                ltq_ase_asc_resources, ARRAY_SIZE(ltq_ase_asc_resources));
+}
+
+/* ethernet */
+static struct resource ltq_etop_resources = {
+        .name   = "etop",
+        .start  = LTQ_ETOP_BASE_ADDR,
+        .end    = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static struct platform_device ltq_etop = {
+        .name           = "ltq_etop",
+        .resource       = &ltq_etop_resources,
+        .num_resources  = 1,
+};
+
+void __init
+ltq_register_etop(struct ltq_eth_data *eth)
+{
+        if (eth) {
+                ltq_etop.dev.platform_data = eth;
+                platform_device_register(&ltq_etop);
+        }
+}
diff --git a/arch/mips/lantiq/xway/devices.h b/arch/mips/lantiq/xway/devices.h
new file mode 100644
index 00000000000..e90493471bc
--- /dev/null
+++ b/arch/mips/lantiq/xway/devices.h
@@ -0,0 +1,20 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#ifndef _LTQ_DEVICES_XWAY_H__
+#define _LTQ_DEVICES_XWAY_H__
+
+#include "../devices.h"
+#include <linux/phy.h>
+
+extern void ltq_register_gpio(void);
+extern void ltq_register_gpio_stp(void);
+extern void ltq_register_ase_asc(void);
+extern void ltq_register_etop(struct ltq_eth_data *eth);
+
+#endif
diff --git a/arch/mips/lantiq/xway/ebu.c b/arch/mips/lantiq/xway/ebu.c
new file mode 100644
index 00000000000..033b3184c7a
--- /dev/null
+++ b/arch/mips/lantiq/xway/ebu.c
@@ -0,0 +1,52 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  EBU - the external bus unit attaches PCI, NOR and NAND
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/ioport.h>
+
+#include <lantiq_soc.h>
+
+/* all access to the ebu must be locked */
+DEFINE_SPINLOCK(ebu_lock);
+EXPORT_SYMBOL_GPL(ebu_lock);
+
+static struct resource ltq_ebu_resource = {
+        .name   = "ebu",
+        .start  = LTQ_EBU_BASE_ADDR,
+        .end    = LTQ_EBU_BASE_ADDR + LTQ_EBU_SIZE - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+/* remapped base addr of the clock unit and external bus unit */
+void __iomem *ltq_ebu_membase;
+
+static int __init lantiq_ebu_init(void)
+{
+        /* insert and request the memory region */
+        if (insert_resource(&iomem_resource, &ltq_ebu_resource) < 0)
+                panic("Failed to insert ebu memory\n");
+
+        if (request_mem_region(ltq_ebu_resource.start,
+                        resource_size(&ltq_ebu_resource), "ebu") < 0)
+                panic("Failed to request ebu memory\n");
+
+        /* remap ebu register range */
+        ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start,
+                                resource_size(&ltq_ebu_resource));
+        if (!ltq_ebu_membase)
+                panic("Failed to remap ebu memory\n");
+
+        /* make sure to unprotect the memory region where flash is located */
+        ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0);
+        return 0;
+}
+
+postcore_initcall(lantiq_ebu_init);
diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
new file mode 100644
index 00000000000..a321451a545
--- /dev/null
+++ b/arch/mips/lantiq/xway/gpio.c
@@ -0,0 +1,195 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+
+#include <lantiq_soc.h>
+
+#define LTQ_GPIO_OUT            0x00
+#define LTQ_GPIO_IN             0x04
+#define LTQ_GPIO_DIR            0x08
+#define LTQ_GPIO_ALTSEL0        0x0C
+#define LTQ_GPIO_ALTSEL1        0x10
+#define LTQ_GPIO_OD             0x14
+
+#define PINS_PER_PORT           16
+#define MAX_PORTS               3
+
+#define ltq_gpio_getbit(m, r, p)        (!!(ltq_r32(m + r) & (1 << p)))
+#define ltq_gpio_setbit(m, r, p)        ltq_w32_mask(0, (1 << p), m + r)
+#define ltq_gpio_clearbit(m, r, p)      ltq_w32_mask((1 << p), 0, m + r)
+
+struct ltq_gpio {
+        void __iomem *membase;
+        struct gpio_chip chip;
+};
+
+static struct ltq_gpio ltq_gpio_port[MAX_PORTS];
+
+int gpio_to_irq(unsigned int gpio)
+{
+        return -EINVAL;
+}
+EXPORT_SYMBOL(gpio_to_irq);
+
+int irq_to_gpio(unsigned int gpio)
+{
+        return -EINVAL;
+}
+EXPORT_SYMBOL(irq_to_gpio);
+
+int ltq_gpio_request(unsigned int pin, unsigned int alt0,
+        unsigned int alt1, unsigned int dir, const char *name)
+{
+        int id = 0;
+
+        if (pin >= (MAX_PORTS * PINS_PER_PORT))
+                return -EINVAL;
+        if (gpio_request(pin, name)) {
+                pr_err("failed to setup lantiq gpio: %s\n", name);
+                return -EBUSY;
+        }
+        if (dir)
+                gpio_direction_output(pin, 1);
+        else
+                gpio_direction_input(pin);
+        while (pin >= PINS_PER_PORT) {
+                pin -= PINS_PER_PORT;
+                id++;
+        }
+        if (alt0)
+                ltq_gpio_setbit(ltq_gpio_port[id].membase,
+                        LTQ_GPIO_ALTSEL0, pin);
+        else
+                ltq_gpio_clearbit(ltq_gpio_port[id].membase,
+                        LTQ_GPIO_ALTSEL0, pin);
+        if (alt1)
+                ltq_gpio_setbit(ltq_gpio_port[id].membase,
+                        LTQ_GPIO_ALTSEL1, pin);
+        else
+                ltq_gpio_clearbit(ltq_gpio_port[id].membase,
+                        LTQ_GPIO_ALTSEL1, pin);
+        return 0;
+}
+EXPORT_SYMBOL(ltq_gpio_request);
+
+static void ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
+{
+        struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
+
+        if (value)
+                ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset);
+        else
+                ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset);
+}
+
+static int ltq_gpio_get(struct gpio_chip *chip, unsigned int offset)
+{
+        struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
+
+        return ltq_gpio_getbit(ltq_gpio->membase, LTQ_GPIO_IN, offset);
+}
+
+static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
+{
+        struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
+
+        ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
+        ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
+
+        return 0;
+}
+
+static int ltq_gpio_direction_output(struct gpio_chip *chip,
+        unsigned int offset, int value)
+{
+        struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
+
+        ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
+        ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
+        ltq_gpio_set(chip, offset, value);
+
+        return 0;
+}
+
+static int ltq_gpio_req(struct gpio_chip *chip, unsigned offset)
+{
+        struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
+
+        ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset);
+        ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset);
+        return 0;
+}
+
+static int ltq_gpio_probe(struct platform_device *pdev)
+{
+        struct resource *res;
+
+        if (pdev->id >= MAX_PORTS) {
+                dev_err(&pdev->dev, "invalid gpio port %d\n",
+                        pdev->id);
+                return -EINVAL;
+        }
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "failed to get memory for gpio port %d\n",
+                        pdev->id);
+                return -ENOENT;
+        }
+        res = devm_request_mem_region(&pdev->dev, res->start,
+                resource_size(res), dev_name(&pdev->dev));
+        if (!res) {
+                dev_err(&pdev->dev,
+                        "failed to request memory for gpio port %d\n",
+                        pdev->id);
+                return -EBUSY;
+        }
+        ltq_gpio_port[pdev->id].membase = devm_ioremap_nocache(&pdev->dev,
+                res->start, resource_size(res));
+        if (!ltq_gpio_port[pdev->id].membase) {
+                dev_err(&pdev->dev, "failed to remap memory for gpio port %d\n",
+                        pdev->id);
+                return -ENOMEM;
+        }
+        ltq_gpio_port[pdev->id].chip.label = "ltq_gpio";
+        ltq_gpio_port[pdev->id].chip.direction_input = ltq_gpio_direction_input;
+        ltq_gpio_port[pdev->id].chip.direction_output =
+                ltq_gpio_direction_output;
+        ltq_gpio_port[pdev->id].chip.get = ltq_gpio_get;
+        ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set;
+        ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req;
+        ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id;
+        ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT;
+        platform_set_drvdata(pdev, &ltq_gpio_port[pdev->id]);
+        return gpiochip_add(&ltq_gpio_port[pdev->id].chip);
+}
+
+static struct platform_driver
+ltq_gpio_driver = {
+        .probe = ltq_gpio_probe,
+        .driver = {
+                .name = "ltq_gpio",
+                .owner = THIS_MODULE,
+        },
+};
+
+int __init ltq_gpio_init(void)
+{
+        int ret = platform_driver_register(&ltq_gpio_driver);
+
+        if (ret)
+                pr_info("ltq_gpio : Error registering platfom driver!");
+        return ret;
+}
+
+postcore_initcall(ltq_gpio_init);
diff --git a/arch/mips/lantiq/xway/gpio_ebu.c b/arch/mips/lantiq/xway/gpio_ebu.c
new file mode 100644
index 00000000000..a479355abdb
--- /dev/null
+++ b/arch/mips/lantiq/xway/gpio_ebu.c
@@ -0,0 +1,126 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+
+#include <lantiq_soc.h>
+
+/*
+ * By attaching hardware latches to the EBU it is possible to create output
+ * only gpios. This driver configures a special memory address, which when
+ * written to outputs 16 bit to the latches.
+ */
+
+#define LTQ_EBU_BUSCON  0x1e7ff         /* 16 bit access, slowest timing */
+#define LTQ_EBU_WP      0x80000000      /* write protect bit */
+
+/* we keep a shadow value of the last value written to the ebu */
+static int ltq_ebu_gpio_shadow = 0x0;
+static void __iomem *ltq_ebu_gpio_membase;
+
+static void ltq_ebu_apply(void)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&ebu_lock, flags);
+        ltq_ebu_w32(LTQ_EBU_BUSCON, LTQ_EBU_BUSCON1);
+        *((__u16 *)ltq_ebu_gpio_membase) = ltq_ebu_gpio_shadow;
+        ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
+        spin_unlock_irqrestore(&ebu_lock, flags);
+}
+
+static void ltq_ebu_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        if (value)
+                ltq_ebu_gpio_shadow |= (1 << offset);
+        else
+                ltq_ebu_gpio_shadow &= ~(1 << offset);
+        ltq_ebu_apply();
+}
+
+static int ltq_ebu_direction_output(struct gpio_chip *chip, unsigned offset,
+        int value)
+{
+        ltq_ebu_set(chip, offset, value);
+
+        return 0;
+}
+
+static struct gpio_chip ltq_ebu_chip = {
+        .label = "ltq_ebu",
+        .direction_output = ltq_ebu_direction_output,
+        .set = ltq_ebu_set,
+        .base = 72,
+        .ngpio = 16,
+        .can_sleep = 1,
+        .owner = THIS_MODULE,
+};
+
+static int ltq_ebu_probe(struct platform_device *pdev)
+{
+        int ret = 0;
+        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+        if (!res) {
+                dev_err(&pdev->dev, "failed to get memory resource\n");
+                return -ENOENT;
+        }
+
+        res = devm_request_mem_region(&pdev->dev, res->start,
+                resource_size(res), dev_name(&pdev->dev));
+        if (!res) {
+                dev_err(&pdev->dev, "failed to request memory resource\n");
+                return -EBUSY;
+        }
+
+        ltq_ebu_gpio_membase = devm_ioremap_nocache(&pdev->dev, res->start,
+                resource_size(res));
+        if (!ltq_ebu_gpio_membase) {
+                dev_err(&pdev->dev, "Failed to ioremap mem region\n");
+                return -ENOMEM;
+        }
+
+        /* grab the default shadow value passed form the platform code */
+        ltq_ebu_gpio_shadow = (unsigned int) pdev->dev.platform_data;
+
+        /* tell the ebu controller which memory address we will be using */
+        ltq_ebu_w32(pdev->resource->start | 0x1, LTQ_EBU_ADDRSEL1);
+
+        /* write protect the region */
+        ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
+
+        ret = gpiochip_add(&ltq_ebu_chip);
+        if (!ret)
+                ltq_ebu_apply();
+        return ret;
+}
+
+static struct platform_driver ltq_ebu_driver = {
+        .probe = ltq_ebu_probe,
+        .driver = {
+                .name = "ltq_ebu",
+                .owner = THIS_MODULE,
+        },
+};
+
+static int __init ltq_ebu_init(void)
+{
+        int ret = platform_driver_register(&ltq_ebu_driver);
+
+        if (ret)
+                pr_info("ltq_ebu : Error registering platfom driver!");
+        return ret;
+}
+
+postcore_initcall(ltq_ebu_init);
diff --git a/arch/mips/lantiq/xway/gpio_stp.c b/arch/mips/lantiq/xway/gpio_stp.c
new file mode 100644
index 00000000000..67d59d69034
--- /dev/null
+++ b/arch/mips/lantiq/xway/gpio_stp.c
@@ -0,0 +1,157 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2007 John Crispin <blogic@openwrt.org>
+ *
+ */
+
+#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <lantiq_soc.h>
+
+#define LTQ_STP_CON0            0x00
+#define LTQ_STP_CON1            0x04
+#define LTQ_STP_CPU0            0x08
+#define LTQ_STP_CPU1            0x0C
+#define LTQ_STP_AR              0x10
+
+#define LTQ_STP_CON_SWU         (1 << 31)
+#define LTQ_STP_2HZ             0
+#define LTQ_STP_4HZ             (1 << 23)
+#define LTQ_STP_8HZ             (2 << 23)
+#define LTQ_STP_10HZ            (3 << 23)
+#define LTQ_STP_SPEED_MASK      (0xf << 23)
+#define LTQ_STP_UPD_FPI         (1 << 31)
+#define LTQ_STP_UPD_MASK        (3 << 30)
+#define LTQ_STP_ADSL_SRC        (3 << 24)
+
+#define LTQ_STP_GROUP0          (1 << 0)
+
+#define LTQ_STP_RISING          0
+#define LTQ_STP_FALLING         (1 << 26)
+#define LTQ_STP_EDGE_MASK       (1 << 26)
+
+#define ltq_stp_r32(reg)        __raw_readl(ltq_stp_membase + reg)
+#define ltq_stp_w32(val, reg)   __raw_writel(val, ltq_stp_membase + reg)
+#define ltq_stp_w32_mask(clear, set, reg) \
+                ltq_w32((ltq_r32(ltq_stp_membase + reg) & ~(clear)) | (set), \
+                ltq_stp_membase + (reg))
+
+static int ltq_stp_shadow = 0xffff;
+static void __iomem *ltq_stp_membase;
+
+static void ltq_stp_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+        if (value)
+                ltq_stp_shadow |= (1 << offset);
+        else
+                ltq_stp_shadow &= ~(1 << offset);
+        ltq_stp_w32(ltq_stp_shadow, LTQ_STP_CPU0);
+}
+
+static int ltq_stp_direction_output(struct gpio_chip *chip, unsigned offset,
+        int value)
+{
+        ltq_stp_set(chip, offset, value);
+
+        return 0;
+}
+
+static struct gpio_chip ltq_stp_chip = {
+        .label = "ltq_stp",
+        .direction_output = ltq_stp_direction_output,
+        .set = ltq_stp_set,
+        .base = 48,
+        .ngpio = 24,
+        .can_sleep = 1,
+        .owner = THIS_MODULE,
+};
+
+static int ltq_stp_hw_init(void)
+{
+        /* the 3 pins used to control the external stp */
+        ltq_gpio_request(4, 1, 0, 1, "stp-st");
+        ltq_gpio_request(5, 1, 0, 1, "stp-d");
+        ltq_gpio_request(6, 1, 0, 1, "stp-sh");
+
+        /* sane defaults */
+        ltq_stp_w32(0, LTQ_STP_AR);
+        ltq_stp_w32(0, LTQ_STP_CPU0);
+        ltq_stp_w32(0, LTQ_STP_CPU1);
+        ltq_stp_w32(LTQ_STP_CON_SWU, LTQ_STP_CON0);
+        ltq_stp_w32(0, LTQ_STP_CON1);
+
+        /* rising or falling edge */
+        ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0);
+
+        /* per default stp 15-0 are set */
+        ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1);
+
+        /* stp are update periodically by the FPI bus */
+        ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1);
+
+        /* set stp update speed */
+        ltq_stp_w32_mask(LTQ_STP_SPEED_MASK, LTQ_STP_8HZ, LTQ_STP_CON1);
+
+        /* tell the hardware that pin (led) 0 and 1 are controlled
+         *  by the dsl arc
+         */
+        ltq_stp_w32_mask(0, LTQ_STP_ADSL_SRC, LTQ_STP_CON0);
+
+        ltq_pmu_enable(PMU_LED);
+        return 0;
+}
+
+static int __devinit ltq_stp_probe(struct platform_device *pdev)
+{
+        struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        int ret = 0;
+
+        if (!res)
+                return -ENOENT;
+        res = devm_request_mem_region(&pdev->dev, res->start,
+                resource_size(res), dev_name(&pdev->dev));
+        if (!res) {
+                dev_err(&pdev->dev, "failed to request STP memory\n");
+                return -EBUSY;
+        }
+        ltq_stp_membase = devm_ioremap_nocache(&pdev->dev, res->start,
+                resource_size(res));
+        if (!ltq_stp_membase) {
+                dev_err(&pdev->dev, "failed to remap STP memory\n");
+                return -ENOMEM;
+        }
+        ret = gpiochip_add(&ltq_stp_chip);
+        if (!ret)
+                ret = ltq_stp_hw_init();
+
+        return ret;
+}
+
+static struct platform_driver ltq_stp_driver = {
+        .probe = ltq_stp_probe,
+        .driver = {
+                .name = "ltq_stp",
+                .owner = THIS_MODULE,
+        },
+};
+
+int __init ltq_stp_init(void)
+{
+        int ret = platform_driver_register(&ltq_stp_driver);
+
+        if (ret)
+                pr_info("ltq_stp: error registering platfom driver");
+        return ret;
+}
+
+postcore_initcall(ltq_stp_init);
diff --git a/arch/mips/lantiq/xway/mach-easy50601.c b/arch/mips/lantiq/xway/mach-easy50601.c
new file mode 100644
index 00000000000..d5aaf637ab1
--- /dev/null
+++ b/arch/mips/lantiq/xway/mach-easy50601.c
@@ -0,0 +1,57 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/input.h>
+
+#include <lantiq.h>
+
+#include "../machtypes.h"
+#include "devices.h"
+
+static struct mtd_partition easy50601_partitions[] = {
+        {
+                .name   = "uboot",
+                .offset = 0x0,
+                .size   = 0x10000,
+        },
+        {
+                .name   = "uboot_env",
+                .offset = 0x10000,
+                .size   = 0x10000,
+        },
+        {
+                .name   = "linux",
+                .offset = 0x20000,
+                .size   = 0xE0000,
+        },
+        {
+                .name   = "rootfs",
+                .offset = 0x100000,
+                .size   = 0x300000,
+        },
+};
+
+static struct physmap_flash_data easy50601_flash_data = {
+        .nr_parts       = ARRAY_SIZE(easy50601_partitions),
+        .parts          = easy50601_partitions,
+};
+
+static void __init easy50601_init(void)
+{
+        ltq_register_nor(&easy50601_flash_data);
+}
+
+MIPS_MACHINE(LTQ_MACH_EASY50601,
+                        "EASY50601",
+                        "EASY50601 Eval Board",
+                        easy50601_init);
diff --git a/arch/mips/lantiq/xway/mach-easy50712.c b/arch/mips/lantiq/xway/mach-easy50712.c
new file mode 100644
index 00000000000..ea5027b3239
--- /dev/null
+++ b/arch/mips/lantiq/xway/mach-easy50712.c
@@ -0,0 +1,74 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/physmap.h>
+#include <linux/input.h>
+#include <linux/phy.h>
+
+#include <lantiq_soc.h>
+#include <irq.h>
+
+#include "../machtypes.h"
+#include "devices.h"
+
+static struct mtd_partition easy50712_partitions[] = {
+        {
+                .name   = "uboot",
+                .offset = 0x0,
+                .size   = 0x10000,
+        },
+        {
+                .name   = "uboot_env",
+                .offset = 0x10000,
+                .size   = 0x10000,
+        },
+        {
+                .name   = "linux",
+                .offset = 0x20000,
+                .size   = 0xe0000,
+        },
+        {
+                .name   = "rootfs",
+                .offset = 0x100000,
+                .size   = 0x300000,
+        },
+};
+
+static struct physmap_flash_data easy50712_flash_data = {
+        .nr_parts       = ARRAY_SIZE(easy50712_partitions),
+        .parts          = easy50712_partitions,
+};
+
+static struct ltq_pci_data ltq_pci_data = {
+        .clock  = PCI_CLOCK_INT,
+        .gpio   = PCI_GNT1 | PCI_REQ1,
+        .irq    = {
+                [14] = INT_NUM_IM0_IRL0 + 22,
+        },
+};
+
+static struct ltq_eth_data ltq_eth_data = {
+        .mii_mode = PHY_INTERFACE_MODE_MII,
+};
+
+static void __init easy50712_init(void)
+{
+        ltq_register_gpio_stp();
+        ltq_register_nor(&easy50712_flash_data);
+        ltq_register_pci(&ltq_pci_data);
+        ltq_register_etop(&ltq_eth_data);
+}
+
+MIPS_MACHINE(LTQ_MACH_EASY50712,
+             "EASY50712",
+             "EASY50712 Eval Board",
+              easy50712_init);
diff --git a/arch/mips/lantiq/xway/pmu.c b/arch/mips/lantiq/xway/pmu.c
new file mode 100644
index 00000000000..39f0d2641cb
--- /dev/null
+++ b/arch/mips/lantiq/xway/pmu.c
@@ -0,0 +1,69 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/ioport.h>
+
+#include <lantiq_soc.h>
+
+/* PMU - the power management unit allows us to turn part of the core
+ * on and off
+ */
+
+/* the enable / disable registers */
+#define LTQ_PMU_PWDCR   0x1C
+#define LTQ_PMU_PWDSR   0x20
+
+#define ltq_pmu_w32(x, y)       ltq_w32((x), ltq_pmu_membase + (y))
+#define ltq_pmu_r32(x)          ltq_r32(ltq_pmu_membase + (x))
+
+static struct resource ltq_pmu_resource = {
+        .name   = "pmu",
+        .start  = LTQ_PMU_BASE_ADDR,
+        .end    = LTQ_PMU_BASE_ADDR + LTQ_PMU_SIZE - 1,
+        .flags  = IORESOURCE_MEM,
+};
+
+static void __iomem *ltq_pmu_membase;
+
+void ltq_pmu_enable(unsigned int module)
+{
+        int err = 1000000;
+
+        ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR);
+        do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module));
+
+        if (!err)
+                panic("activating PMU module failed!\n");
+}
+EXPORT_SYMBOL(ltq_pmu_enable);
+
+void ltq_pmu_disable(unsigned int module)
+{
+        ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR);
+}
+EXPORT_SYMBOL(ltq_pmu_disable);
+
+int __init ltq_pmu_init(void)
+{
+        if (insert_resource(&iomem_resource, &ltq_pmu_resource) < 0)
+                panic("Failed to insert pmu memory\n");
+
+        if (request_mem_region(ltq_pmu_resource.start,
+                        resource_size(&ltq_pmu_resource), "pmu") < 0)
+                panic("Failed to request pmu memory\n");
+
+        ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start,
+                                resource_size(&ltq_pmu_resource));
+        if (!ltq_pmu_membase)
+                panic("Failed to remap pmu memory\n");
+        return 0;
+}
+
+core_initcall(ltq_pmu_init);
diff --git a/arch/mips/lantiq/xway/prom-ase.c b/arch/mips/lantiq/xway/prom-ase.c
new file mode 100644
index 00000000000..abe49f4db57
--- /dev/null
+++ b/arch/mips/lantiq/xway/prom-ase.c
@@ -0,0 +1,39 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <asm/bootinfo.h>
+#include <asm/time.h>
+
+#include <lantiq_soc.h>
+
+#include "../prom.h"
+
+#define SOC_AMAZON_SE   "Amazon_SE"
+
+#define PART_SHIFT      12
+#define PART_MASK       0x0FFFFFFF
+#define REV_SHIFT       28
+#define REV_MASK        0xF0000000
+
+void __init ltq_soc_detect(struct ltq_soc_info *i)
+{
+        i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
+        i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
+        switch (i->partnum) {
+        case SOC_ID_AMAZON_SE:
+                i->name = SOC_AMAZON_SE;
+                i->type = SOC_TYPE_AMAZON_SE;
+                break;
+
+        default:
+                unreachable();
+                break;
+        }
+}
diff --git a/arch/mips/lantiq/xway/prom-xway.c b/arch/mips/lantiq/xway/prom-xway.c
new file mode 100644
index 00000000000..1686692ac24
--- /dev/null
+++ b/arch/mips/lantiq/xway/prom-xway.c
@@ -0,0 +1,54 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <asm/bootinfo.h>
+#include <asm/time.h>
+
+#include <lantiq_soc.h>
+
+#include "../prom.h"
+
+#define SOC_DANUBE      "Danube"
+#define SOC_TWINPASS    "Twinpass"
+#define SOC_AR9         "AR9"
+
+#define PART_SHIFT      12
+#define PART_MASK       0x0FFFFFFF
+#define REV_SHIFT       28
+#define REV_MASK        0xF0000000
+
+void __init ltq_soc_detect(struct ltq_soc_info *i)
+{
+        i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT;
+        i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT;
+        switch (i->partnum) {
+        case SOC_ID_DANUBE1:
+        case SOC_ID_DANUBE2:
+                i->name = SOC_DANUBE;
+                i->type = SOC_TYPE_DANUBE;
+                break;
+
+        case SOC_ID_TWINPASS:
+                i->name = SOC_TWINPASS;
+                i->type = SOC_TYPE_DANUBE;
+                break;
+
+        case SOC_ID_ARX188:
+        case SOC_ID_ARX168:
+        case SOC_ID_ARX182:
+                i->name = SOC_AR9;
+                i->type = SOC_TYPE_AR9;
+                break;
+
+        default:
+                unreachable();
+                break;
+        }
+}
diff --git a/arch/mips/lantiq/xway/setup-ase.c b/arch/mips/lantiq/xway/setup-ase.c
new file mode 100644
index 00000000000..f6f326798a3
--- /dev/null
+++ b/arch/mips/lantiq/xway/setup-ase.c
@@ -0,0 +1,19 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ */
+
+#include <lantiq_soc.h>
+
+#include "../prom.h"
+#include "devices.h"
+
+void __init ltq_soc_setup(void)
+{
+        ltq_register_ase_asc();
+        ltq_register_gpio();
+        ltq_register_wdt();
+}
diff --git a/arch/mips/lantiq/xway/setup-xway.c b/arch/mips/lantiq/xway/setup-xway.c
new file mode 100644
index 00000000000..c292f643a85
--- /dev/null
+++ b/arch/mips/lantiq/xway/setup-xway.c
@@ -0,0 +1,20 @@
+/*
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ *
+ *  Copyright (C) 2011 John Crispin <blogic@openwrt.org>
+ */
+
+#include <lantiq_soc.h>
+
+#include "../prom.h"
+#include "devices.h"
+
+void __init ltq_soc_setup(void)
+{
+        ltq_register_asc(0);
+        ltq_register_asc(1);
+        ltq_register_gpio();
+        ltq_register_wdt();
+}
diff --git a/arch/mips/lib/memcpy-inatomic.S b/arch/mips/lib/memcpy-inatomic.S
new file mode 100644
index 00000000000..68853a038d3
--- /dev/null
+++ b/arch/mips/lib/memcpy-inatomic.S
@@ -0,0 +1,451 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Unified implementation of memcpy, memmove and the __copy_user backend.
+ *
+ * Copyright (C) 1998, 99, 2000, 01, 2002 Ralf Baechle (ralf@gnu.org)
+ * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc.
+ * Copyright (C) 2002 Broadcom, Inc.
+ *   memcpy/copy_user author: Mark Vandevoorde
+ * Copyright (C) 2007  Maciej W. Rozycki
+ *
+ * Mnemonic names for arguments to memcpy/__copy_user
+ */
+
+/*
+ * Hack to resolve longstanding prefetch issue
+ *
+ * Prefetching may be fatal on some systems if we're prefetching beyond the
+ * end of memory on some systems.  It's also a seriously bad idea on non
+ * dma-coherent systems.
+ */
+#ifdef CONFIG_DMA_NONCOHERENT
+#undef CONFIG_CPU_HAS_PREFETCH
+#endif
+#ifdef CONFIG_MIPS_MALTA
+#undef CONFIG_CPU_HAS_PREFETCH
+#endif
+
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/regdef.h>
+
+#define dst a0
+#define src a1
+#define len a2
+
+/*
+ * Spec
+ *
+ * memcpy copies len bytes from src to dst and sets v0 to dst.
+ * It assumes that
+ *   - src and dst don't overlap
+ *   - src is readable
+ *   - dst is writable
+ * memcpy uses the standard calling convention
+ *
+ * __copy_user copies up to len bytes from src to dst and sets a2 (len) to
+ * the number of uncopied bytes due to an exception caused by a read or write.
+ * __copy_user assumes that src and dst don't overlap, and that the call is
+ * implementing one of the following:
+ *   copy_to_user
+ *     - src is readable  (no exceptions when reading src)
+ *   copy_from_user
+ *     - dst is writable  (no exceptions when writing dst)
+ * __copy_user uses a non-standard calling convention; see
+ * include/asm-mips/uaccess.h
+ *
+ * When an exception happens on a load, the handler must
+ # ensure that all of the destination buffer is overwritten to prevent
+ * leaking information to user mode programs.
+ */
+
+/*
+ * Implementation
+ */
+
+/*
+ * The exception handler for loads requires that:
+ *  1- AT contain the address of the byte just past the end of the source
+ *     of the copy,
+ *  2- src_entry <= src < AT, and
+ *  3- (dst - src) == (dst_entry - src_entry),
+ * The _entry suffix denotes values when __copy_user was called.
+ *
+ * (1) is set up up by uaccess.h and maintained by not writing AT in copy_user
+ * (2) is met by incrementing src by the number of bytes copied
+ * (3) is met by not doing loads between a pair of increments of dst and src
+ *
+ * The exception handlers for stores adjust len (if necessary) and return.
+ * These handlers do not need to overwrite any data.
+ *
+ * For __rmemcpy and memmove an exception is always a kernel bug, therefore
+ * they're not protected.
+ */
+
+#define EXC(inst_reg,addr,handler)              \
+9:      inst_reg, addr;                         \
+        .section __ex_table,"a";                \
+        PTR     9b, handler;                    \
+        .previous
+
+/*
+ * Only on the 64-bit kernel we can made use of 64-bit registers.
+ */
+#ifdef CONFIG_64BIT
+#define USE_DOUBLE
+#endif
+
+#ifdef USE_DOUBLE
+
+#define LOAD   ld
+#define LOADL  ldl
+#define LOADR  ldr
+#define STOREL sdl
+#define STORER sdr
+#define STORE  sd
+#define ADD    daddu
+#define SUB    dsubu
+#define SRL    dsrl
+#define SRA    dsra
+#define SLL    dsll
+#define SLLV   dsllv
+#define SRLV   dsrlv
+#define NBYTES 8
+#define LOG_NBYTES 3
+
+/*
+ * As we are sharing code base with the mips32 tree (which use the o32 ABI
+ * register definitions). We need to redefine the register definitions from
+ * the n64 ABI register naming to the o32 ABI register naming.
+ */
+#undef t0
+#undef t1
+#undef t2
+#undef t3
+#define t0      $8
+#define t1      $9
+#define t2      $10
+#define t3      $11
+#define t4      $12
+#define t5      $13
+#define t6      $14
+#define t7      $15
+
+#else
+
+#define LOAD   lw
+#define LOADL  lwl
+#define LOADR  lwr
+#define STOREL swl
+#define STORER swr
+#define STORE  sw
+#define ADD    addu
+#define SUB    subu
+#define SRL    srl
+#define SLL    sll
+#define SRA    sra
+#define SLLV   sllv
+#define SRLV   srlv
+#define NBYTES 4
+#define LOG_NBYTES 2
+
+#endif /* USE_DOUBLE */
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+#define LDFIRST LOADR
+#define LDREST  LOADL
+#define STFIRST STORER
+#define STREST  STOREL
+#define SHIFT_DISCARD SLLV
+#else
+#define LDFIRST LOADL
+#define LDREST  LOADR
+#define STFIRST STOREL
+#define STREST  STORER
+#define SHIFT_DISCARD SRLV
+#endif
+
+#define FIRST(unit) ((unit)*NBYTES)
+#define REST(unit)  (FIRST(unit)+NBYTES-1)
+#define UNIT(unit)  FIRST(unit)
+
+#define ADDRMASK (NBYTES-1)
+
+        .text
+        .set    noreorder
+#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
+        .set    noat
+#else
+        .set    at=v1
+#endif
+
+/*
+ * A combined memcpy/__copy_user
+ * __copy_user sets len to 0 for success; else to an upper bound of
+ * the number of uncopied bytes.
+ * memcpy sets v0 to dst.
+ */
+        .align  5
+LEAF(__copy_user_inatomic)
+        /*
+         * Note: dst & src may be unaligned, len may be 0
+         * Temps
+         */
+#define rem t8
+
+        /*
+         * The "issue break"s below are very approximate.
+         * Issue delays for dcache fills will perturb the schedule, as will
+         * load queue full replay traps, etc.
+         *
+         * If len < NBYTES use byte operations.
+         */
+        PREF(   0, 0(src) )
+        PREF(   1, 0(dst) )
+        sltu    t2, len, NBYTES
+        and     t1, dst, ADDRMASK
+        PREF(   0, 1*32(src) )
+        PREF(   1, 1*32(dst) )
+        bnez    t2, .Lcopy_bytes_checklen
+         and    t0, src, ADDRMASK
+        PREF(   0, 2*32(src) )
+        PREF(   1, 2*32(dst) )
+        bnez    t1, .Ldst_unaligned
+         nop
+        bnez    t0, .Lsrc_unaligned_dst_aligned
+        /*
+         * use delay slot for fall-through
+         * src and dst are aligned; need to compute rem
+         */
+.Lboth_aligned:
+         SRL    t0, len, LOG_NBYTES+3           # +3 for 8 units/iter
+        beqz    t0, .Lcleanup_both_aligned      # len < 8*NBYTES
+         and    rem, len, (8*NBYTES-1)          # rem = len % (8*NBYTES)
+        PREF(   0, 3*32(src) )
+        PREF(   1, 3*32(dst) )
+        .align  4
+1:
+EXC(    LOAD    t0, UNIT(0)(src),       .Ll_exc)
+EXC(    LOAD    t1, UNIT(1)(src),       .Ll_exc_copy)
+EXC(    LOAD    t2, UNIT(2)(src),       .Ll_exc_copy)
+EXC(    LOAD    t3, UNIT(3)(src),       .Ll_exc_copy)
+        SUB     len, len, 8*NBYTES
+EXC(    LOAD    t4, UNIT(4)(src),       .Ll_exc_copy)
+EXC(    LOAD    t7, UNIT(5)(src),       .Ll_exc_copy)
+        STORE   t0, UNIT(0)(dst)
+        STORE   t1, UNIT(1)(dst)
+EXC(    LOAD    t0, UNIT(6)(src),       .Ll_exc_copy)
+EXC(    LOAD    t1, UNIT(7)(src),       .Ll_exc_copy)
+        ADD     src, src, 8*NBYTES
+        ADD     dst, dst, 8*NBYTES
+        STORE   t2, UNIT(-6)(dst)
+        STORE   t3, UNIT(-5)(dst)
+        STORE   t4, UNIT(-4)(dst)
+        STORE   t7, UNIT(-3)(dst)
+        STORE   t0, UNIT(-2)(dst)
+        STORE   t1, UNIT(-1)(dst)
+        PREF(   0, 8*32(src) )
+        PREF(   1, 8*32(dst) )
+        bne     len, rem, 1b
+         nop
+
+        /*
+         * len == rem == the number of bytes left to copy < 8*NBYTES
+         */
+.Lcleanup_both_aligned:
+        beqz    len, .Ldone
+         sltu   t0, len, 4*NBYTES
+        bnez    t0, .Lless_than_4units
+         and    rem, len, (NBYTES-1)    # rem = len % NBYTES
+        /*
+         * len >= 4*NBYTES
+         */
+EXC(    LOAD    t0, UNIT(0)(src),       .Ll_exc)
+EXC(    LOAD    t1, UNIT(1)(src),       .Ll_exc_copy)
+EXC(    LOAD    t2, UNIT(2)(src),       .Ll_exc_copy)
+EXC(    LOAD    t3, UNIT(3)(src),       .Ll_exc_copy)
+        SUB     len, len, 4*NBYTES
+        ADD     src, src, 4*NBYTES
+        STORE   t0, UNIT(0)(dst)
+        STORE   t1, UNIT(1)(dst)
+        STORE   t2, UNIT(2)(dst)
+        STORE   t3, UNIT(3)(dst)
+        .set    reorder                         /* DADDI_WAR */
+        ADD     dst, dst, 4*NBYTES
+        beqz    len, .Ldone
+        .set    noreorder
+.Lless_than_4units:
+        /*
+         * rem = len % NBYTES
+         */
+        beq     rem, len, .Lcopy_bytes
+         nop
+1:
+EXC(    LOAD    t0, 0(src),             .Ll_exc)
+        ADD     src, src, NBYTES
+        SUB     len, len, NBYTES
+        STORE   t0, 0(dst)
+        .set    reorder                         /* DADDI_WAR */
+        ADD     dst, dst, NBYTES
+        bne     rem, len, 1b
+        .set    noreorder
+
+        /*
+         * src and dst are aligned, need to copy rem bytes (rem < NBYTES)
+         * A loop would do only a byte at a time with possible branch
+         * mispredicts.  Can't do an explicit LOAD dst,mask,or,STORE
+         * because can't assume read-access to dst.  Instead, use
+         * STREST dst, which doesn't require read access to dst.
+         *
+         * This code should perform better than a simple loop on modern,
+         * wide-issue mips processors because the code has fewer branches and
+         * more instruction-level parallelism.
+         */
+#define bits t2
+        beqz    len, .Ldone
+         ADD    t1, dst, len    # t1 is just past last byte of dst
+        li      bits, 8*NBYTES
+        SLL     rem, len, 3     # rem = number of bits to keep
+EXC(    LOAD    t0, 0(src),             .Ll_exc)
+        SUB     bits, bits, rem # bits = number of bits to discard
+        SHIFT_DISCARD t0, t0, bits
+        STREST  t0, -1(t1)
+        jr      ra
+         move   len, zero
+.Ldst_unaligned:
+        /*
+         * dst is unaligned
+         * t0 = src & ADDRMASK
+         * t1 = dst & ADDRMASK; T1 > 0
+         * len >= NBYTES
+         *
+         * Copy enough bytes to align dst
+         * Set match = (src and dst have same alignment)
+         */
+#define match rem
+EXC(    LDFIRST t3, FIRST(0)(src),      .Ll_exc)
+        ADD     t2, zero, NBYTES
+EXC(    LDREST  t3, REST(0)(src),       .Ll_exc_copy)
+        SUB     t2, t2, t1      # t2 = number of bytes copied
+        xor     match, t0, t1
+        STFIRST t3, FIRST(0)(dst)
+        beq     len, t2, .Ldone
+         SUB    len, len, t2
+        ADD     dst, dst, t2
+        beqz    match, .Lboth_aligned
+         ADD    src, src, t2
+
+.Lsrc_unaligned_dst_aligned:
+        SRL     t0, len, LOG_NBYTES+2    # +2 for 4 units/iter
+        PREF(   0, 3*32(src) )
+        beqz    t0, .Lcleanup_src_unaligned
+         and    rem, len, (4*NBYTES-1)   # rem = len % 4*NBYTES
+        PREF(   1, 3*32(dst) )
+1:
+/*
+ * Avoid consecutive LD*'s to the same register since some mips
+ * implementations can't issue them in the same cycle.
+ * It's OK to load FIRST(N+1) before REST(N) because the two addresses
+ * are to the same unit (unless src is aligned, but it's not).
+ */
+EXC(    LDFIRST t0, FIRST(0)(src),      .Ll_exc)
+EXC(    LDFIRST t1, FIRST(1)(src),      .Ll_exc_copy)
+        SUB     len, len, 4*NBYTES
+EXC(    LDREST  t0, REST(0)(src),       .Ll_exc_copy)
+EXC(    LDREST  t1, REST(1)(src),       .Ll_exc_copy)
+EXC(    LDFIRST t2, FIRST(2)(src),      .Ll_exc_copy)
+EXC(    LDFIRST t3, FIRST(3)(src),      .Ll_exc_copy)
+EXC(    LDREST  t2, REST(2)(src),       .Ll_exc_copy)
+EXC(    LDREST  t3, REST(3)(src),       .Ll_exc_copy)
+        PREF(   0, 9*32(src) )          # 0 is PREF_LOAD  (not streamed)
+        ADD     src, src, 4*NBYTES
+#ifdef CONFIG_CPU_SB1
+        nop                             # improves slotting
+#endif
+        STORE   t0, UNIT(0)(dst)
+        STORE   t1, UNIT(1)(dst)
+        STORE   t2, UNIT(2)(dst)
+        STORE   t3, UNIT(3)(dst)
+        PREF(   1, 9*32(dst) )          # 1 is PREF_STORE (not streamed)
+        .set    reorder                         /* DADDI_WAR */
+        ADD     dst, dst, 4*NBYTES
+        bne     len, rem, 1b
+        .set    noreorder
+
+.Lcleanup_src_unaligned:
+        beqz    len, .Ldone
+         and    rem, len, NBYTES-1  # rem = len % NBYTES
+        beq     rem, len, .Lcopy_bytes
+         nop
+1:
+EXC(    LDFIRST t0, FIRST(0)(src),      .Ll_exc)
+EXC(    LDREST  t0, REST(0)(src),       .Ll_exc_copy)
+        ADD     src, src, NBYTES
+        SUB     len, len, NBYTES
+        STORE   t0, 0(dst)
+        .set    reorder                         /* DADDI_WAR */
+        ADD     dst, dst, NBYTES
+        bne     len, rem, 1b
+        .set    noreorder
+
+.Lcopy_bytes_checklen:
+        beqz    len, .Ldone
+         nop
+.Lcopy_bytes:
+        /* 0 < len < NBYTES  */
+#define COPY_BYTE(N)                    \
+EXC(    lb      t0, N(src), .Ll_exc);   \
+        SUB     len, len, 1;            \
+        beqz    len, .Ldone;            \
+         sb     t0, N(dst)
+
+        COPY_BYTE(0)
+        COPY_BYTE(1)
+#ifdef USE_DOUBLE
+        COPY_BYTE(2)
+        COPY_BYTE(3)
+        COPY_BYTE(4)
+        COPY_BYTE(5)
+#endif
+EXC(    lb      t0, NBYTES-2(src), .Ll_exc)
+        SUB     len, len, 1
+        jr      ra
+         sb     t0, NBYTES-2(dst)
+.Ldone:
+        jr      ra
+         nop
+        END(__copy_user_inatomic)
+
+.Ll_exc_copy:
+        /*
+         * Copy bytes from src until faulting load address (or until a
+         * lb faults)
+         *
+         * When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28)
+         * may be more than a byte beyond the last address.
+         * Hence, the lb below may get an exception.
+         *
+         * Assumes src < THREAD_BUADDR($28)
+         */
+        LOAD    t0, TI_TASK($28)
+         nop
+        LOAD    t0, THREAD_BUADDR(t0)
+1:
+EXC(    lb      t1, 0(src),     .Ll_exc)
+        ADD     src, src, 1
+        sb      t1, 0(dst)      # can't fault -- we're copy_from_user
+        .set    reorder                         /* DADDI_WAR */
+        ADD     dst, dst, 1
+        bne     src, t0, 1b
+        .set    noreorder
+.Ll_exc:
+        LOAD    t0, TI_TASK($28)
+         nop
+        LOAD    t0, THREAD_BUADDR(t0)   # t0 is just past last good address
+         nop
+        SUB     len, AT, t0             # len number of uncopied bytes
+        jr      ra
+         nop
diff --git a/arch/mips/mipssim/Makefile b/arch/mips/mipssim/Makefile
new file mode 100644
index 00000000000..01410a3f172
--- /dev/null
+++ b/arch/mips/mipssim/Makefile
@@ -0,0 +1,23 @@
+#
+# Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+# Copyright (C) 2007 MIPS Technologies, Inc.
+#   written by Ralf Baechle (ralf@linux-mips.org)
+#
+# This program is free software; you can distribute it and/or modify it
+# under the terms of the GNU General Public License (Version 2) as
+# published by the Free Software Foundation.
+#
+# This program is distributed in the hope it will be useful, but WITHOUT
+# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+# FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+# for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+#
+
+obj-y := sim_platform.o sim_setup.o sim_mem.o sim_time.o sim_int.o
+
+obj-$(CONFIG_EARLY_PRINTK) += sim_console.o
+obj-$(CONFIG_MIPS_MT_SMTC) += sim_smtc.o
diff --git a/arch/mips/mipssim/Platform b/arch/mips/mipssim/Platform
new file mode 100644
index 00000000000..3df60b8a12e
--- /dev/null
+++ b/arch/mips/mipssim/Platform
@@ -0,0 +1,6 @@
+#
+# MIPS SIM
+#
+platform-$(CONFIG_MIPS_SIM)     += mipssim/
+cflags-$(CONFIG_MIPS_SIM)       += -I$(srctree)/arch/mips/include/asm/mach-mipssim
+load-$(CONFIG_MIPS_SIM)         += 0x80100000
diff --git a/arch/mips/mipssim/sim_console.c b/arch/mips/mipssim/sim_console.c
new file mode 100644
index 00000000000..a2f41672cd5
--- /dev/null
+++ b/arch/mips/mipssim/sim_console.c
@@ -0,0 +1,40 @@
+/*
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
+ * Copyright (C) 2007 MIPS Technologies, Inc.
+ *   written by Ralf Baechle
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/serial_reg.h>
+
+static inline unsigned int serial_in(int offset)
+{
+        return inb(0x3f8 + offset);
+}
+
+static inline void serial_out(int offset, int value)
+{
+        outb(value, 0x3f8 + offset);
+}
+
+void __init prom_putchar(char c)
+{
+        while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
+                ;
+
+        serial_out(UART_TX, c);
+}
diff --git a/arch/mips/mipssim/sim_int.c b/arch/mips/mipssim/sim_int.c
new file mode 100644
index 00000000000..5c779be6f08
--- /dev/null
+++ b/arch/mips/mipssim/sim_int.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (C) 1999, 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/kernel_stat.h>
+#include <asm/mips-boards/simint.h>
+#include <asm/irq_cpu.h>
+
+static inline int clz(unsigned long x)
+{
+        __asm__(
+        "       .set    push                                    \n"
+        "       .set    mips32                                  \n"
+        "       clz     %0, %1                                  \n"
+        "       .set    pop                                     \n"
+        : "=r" (x)
+        : "r" (x));
+
+        return x;
+}
+
+/*
+ * Version of ffs that only looks at bits 12..15.
+ */
+static inline unsigned int irq_ffs(unsigned int pending)
+{
+#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
+        return -clz(pending) + 31 - CAUSEB_IP;
+#else
+        unsigned int a0 = 7;
+        unsigned int t0;
+
+        t0 = s0 & 0xf000;
+        t0 = t0 < 1;
+        t0 = t0 << 2;
+        a0 = a0 - t0;
+        s0 = s0 << t0;
+
+        t0 = s0 & 0xc000;
+        t0 = t0 < 1;
+        t0 = t0 << 1;
+        a0 = a0 - t0;
+        s0 = s0 << t0;
+
+        t0 = s0 & 0x8000;
+        t0 = t0 < 1;
+        /* t0 = t0 << 2; */
+        a0 = a0 - t0;
+        /* s0 = s0 << t0; */
+
+        return a0;
+#endif
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+        unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
+        int irq;
+
+        irq = irq_ffs(pending);
+
+        if (irq > 0)
+                do_IRQ(MIPS_CPU_IRQ_BASE + irq);
+        else
+                spurious_interrupt();
+}
+
+void __init arch_init_irq(void)
+{
+        mips_cpu_irq_init();
+}
diff --git a/arch/mips/mipssim/sim_mem.c b/arch/mips/mipssim/sim_mem.c
new file mode 100644
index 00000000000..953d836a771
--- /dev/null
+++ b/arch/mips/mipssim/sim_mem.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/bootmem.h>
+#include <linux/pfn.h>
+
+#include <asm/bootinfo.h>
+#include <asm/page.h>
+#include <asm/sections.h>
+
+#include <asm/mips-boards/prom.h>
+
+/*#define DEBUG*/
+
+enum simmem_memtypes {
+        simmem_reserved = 0,
+        simmem_free,
+};
+struct prom_pmemblock mdesc[PROM_MAX_PMEMBLOCKS];
+
+#ifdef DEBUG
+static char *mtypes[3] = {
+        "SIM reserved memory",
+        "SIM free memory",
+};
+#endif
+
+struct prom_pmemblock * __init prom_getmdesc(void)
+{
+        unsigned int memsize;
+
+        memsize = 0x02000000;
+        pr_info("Setting default memory size 0x%08x\n", memsize);
+
+        memset(mdesc, 0, sizeof(mdesc));
+
+        mdesc[0].type = simmem_reserved;
+        mdesc[0].base = 0x00000000;
+        mdesc[0].size = 0x00001000;
+
+        mdesc[1].type = simmem_free;
+        mdesc[1].base = 0x00001000;
+        mdesc[1].size = 0x000ff000;
+
+        mdesc[2].type = simmem_reserved;
+        mdesc[2].base = 0x00100000;
+        mdesc[2].size = CPHYSADDR(PFN_ALIGN(&_end)) - mdesc[2].base;
+
+        mdesc[3].type = simmem_free;
+        mdesc[3].base = CPHYSADDR(PFN_ALIGN(&_end));
+        mdesc[3].size = memsize - mdesc[3].base;
+
+        return &mdesc[0];
+}
+
+static int __init prom_memtype_classify(unsigned int type)
+{
+        switch (type) {
+        case simmem_free:
+                return BOOT_MEM_RAM;
+        case simmem_reserved:
+        default:
+                return BOOT_MEM_RESERVED;
+        }
+}
+
+void __init prom_meminit(void)
+{
+        struct prom_pmemblock *p;
+
+        p = prom_getmdesc();
+
+        while (p->size) {
+                long type;
+                unsigned long base, size;
+
+                type = prom_memtype_classify(p->type);
+                base = p->base;
+                size = p->size;
+
+                add_memory_region(base, size, type);
+                p++;
+        }
+}
+
+void __init prom_free_prom_memory(void)
+{
+        int i;
+        unsigned long addr;
+
+        for (i = 0; i < boot_mem_map.nr_map; i++) {
+                if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA)
+                        continue;
+
+                addr = boot_mem_map.map[i].addr;
+                free_init_pages("prom memory",
+                                addr, addr + boot_mem_map.map[i].size);
+        }
+}
diff --git a/arch/mips/mipssim/sim_platform.c b/arch/mips/mipssim/sim_platform.c
new file mode 100644
index 00000000000..53210a8c5de
--- /dev/null
+++ b/arch/mips/mipssim/sim_platform.c
@@ -0,0 +1,35 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 by Ralf Baechle (ralf@linux-mips.org)
+ */
+#include <linux/init.h>
+#include <linux/if_ether.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+static char mipsnet_string[] = "mipsnet";
+
+static struct platform_device eth1_device = {
+        .name           = mipsnet_string,
+        .id             = 0,
+};
+
+/*
+ * Create a platform device for the GPI port that receives the
+ * image data from the embedded camera.
+ */
+static int __init mipsnet_devinit(void)
+{
+        int err;
+
+        err = platform_device_register(&eth1_device);
+        if (err)
+                printk(KERN_ERR "%s: registration failed\n", mipsnet_string);
+
+        return err;
+}
+
+device_initcall(mipsnet_devinit);
diff --git a/arch/mips/mipssim/sim_setup.c b/arch/mips/mipssim/sim_setup.c
new file mode 100644
index 00000000000..256e0cdaa49
--- /dev/null
+++ b/arch/mips/mipssim/sim_setup.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/ioport.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/mips-boards/generic.h>
+#include <asm/mips-boards/prom.h>
+#include <asm/time.h>
+#include <asm/mips-boards/sim.h>
+#include <asm/mips-boards/simint.h>
+#include <asm/smp-ops.h>
+
+
+static void __init serial_init(void);
+unsigned int _isbonito;
+
+const char *get_system_type(void)
+{
+        return "MIPSsim";
+}
+
+void __init plat_mem_setup(void)
+{
+        set_io_port_base(0xbfd00000);
+
+        serial_init();
+}
+
+extern struct plat_smp_ops ssmtc_smp_ops;
+
+void __init prom_init(void)
+{
+        set_io_port_base(0xbfd00000);
+
+        prom_meminit();
+
+        if (cpu_has_mipsmt) {
+                if (!register_vsmp_smp_ops())
+                        return;
+
+#ifdef CONFIG_MIPS_MT_SMTC
+                register_smp_ops(&ssmtc_smp_ops);
+                        return;
+#endif
+        }
+
+        register_up_smp_ops();
+}
+
+static void __init serial_init(void)
+{
+#ifdef CONFIG_SERIAL_8250
+        struct uart_port s;
+
+        memset(&s, 0, sizeof(s));
+
+        s.iobase = 0x3f8;
+
+        /* hardware int 4 - the serial int, is CPU int 6
+         but poll for now */
+        s.irq =  0;
+        s.uartclk = 1843200;
+        s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
+        s.iotype = UPIO_PORT;
+        s.regshift = 0;
+        s.timeout = 4;
+
+        if (early_serial_setup(&s) != 0) {
+                printk(KERN_ERR "Serial setup failed!\n");
+        }
+
+#endif
+}
diff --git a/arch/mips/mipssim/sim_smtc.c b/arch/mips/mipssim/sim_smtc.c
new file mode 100644
index 00000000000..915063991f6
--- /dev/null
+++ b/arch/mips/mipssim/sim_smtc.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ */
+/*
+ * Simulator Platform-specific hooks for SMTC operation
+ */
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/cpumask.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+
+#include <linux/atomic.h>
+#include <asm/cpu.h>
+#include <asm/processor.h>
+#include <asm/smtc.h>
+#include <asm/system.h>
+#include <asm/mmu_context.h>
+#include <asm/smtc_ipi.h>
+
+/* VPE/SMP Prototype implements platform interfaces directly */
+
+/*
+ * Cause the specified action to be performed on a targeted "CPU"
+ */
+
+static void ssmtc_send_ipi_single(int cpu, unsigned int action)
+{
+        smtc_send_ipi(cpu, LINUX_SMP_IPI, action);
+        /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */
+}
+
+static inline void ssmtc_send_ipi_mask(const struct cpumask *mask,
+                                       unsigned int action)
+{
+        unsigned int i;
+
+        for_each_cpu(i, mask)
+                ssmtc_send_ipi_single(i, action);
+}
+
+/*
+ * Post-config but pre-boot cleanup entry point
+ */
+static void __cpuinit ssmtc_init_secondary(void)
+{
+        smtc_init_secondary();
+}
+
+/*
+ * SMP initialization finalization entry point
+ */
+static void __cpuinit ssmtc_smp_finish(void)
+{
+        smtc_smp_finish();
+}
+
+/*
+ * Hook for after all CPUs are online
+ */
+static void ssmtc_cpus_done(void)
+{
+}
+
+/*
+ * Platform "CPU" startup hook
+ */
+static void __cpuinit ssmtc_boot_secondary(int cpu, struct task_struct *idle)
+{
+        smtc_boot_secondary(cpu, idle);
+}
+
+static void __init ssmtc_smp_setup(void)
+{
+        if (read_c0_config3() & (1 << 2))
+                mipsmt_build_cpu_map(0);
+}
+
+/*
+ * Platform SMP pre-initialization
+ */
+static void ssmtc_prepare_cpus(unsigned int max_cpus)
+{
+        /*
+         * As noted above, we can assume a single CPU for now
+         * but it may be multithreaded.
+         */
+
+        if (read_c0_config3() & (1 << 2)) {
+                mipsmt_prepare_cpus();
+        }
+}
+
+struct plat_smp_ops ssmtc_smp_ops = {
+        .send_ipi_single        = ssmtc_send_ipi_single,
+        .send_ipi_mask          = ssmtc_send_ipi_mask,
+        .init_secondary         = ssmtc_init_secondary,
+        .smp_finish             = ssmtc_smp_finish,
+        .cpus_done              = ssmtc_cpus_done,
+        .boot_secondary         = ssmtc_boot_secondary,
+        .smp_setup              = ssmtc_smp_setup,
+        .prepare_cpus           = ssmtc_prepare_cpus,
+};
diff --git a/arch/mips/mipssim/sim_time.c b/arch/mips/mipssim/sim_time.c
new file mode 100644
index 00000000000..5492c42f765
--- /dev/null
+++ b/arch/mips/mipssim/sim_time.c
@@ -0,0 +1,116 @@
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/mc146818rtc.h>
+#include <linux/smp.h>
+#include <linux/timex.h>
+
+#include <asm/hardirq.h>
+#include <asm/div64.h>
+#include <asm/cpu.h>
+#include <asm/time.h>
+#include <asm/irq.h>
+#include <asm/mc146818-time.h>
+#include <asm/msc01_ic.h>
+
+#include <asm/mips-boards/generic.h>
+#include <asm/mips-boards/prom.h>
+#include <asm/mips-boards/simint.h>
+
+
+unsigned long cpu_khz;
+
+/*
+ * Estimate CPU frequency.  Sets mips_hpt_frequency as a side-effect
+ */
+static unsigned int __init estimate_cpu_frequency(void)
+{
+        unsigned int prid = read_c0_prid() & 0xffff00;
+        unsigned int count;
+
+#if 1
+        /*
+         * hardwire the board frequency to 12MHz.
+         */
+
+        if ((prid == (PRID_COMP_MIPS | PRID_IMP_20KC)) ||
+            (prid == (PRID_COMP_MIPS | PRID_IMP_25KF)))
+                count = 12000000;
+        else
+                count =  6000000;
+#else
+        unsigned int flags;
+
+        local_irq_save(flags);
+
+        /* Start counter exactly on falling edge of update flag */
+        while (CMOS_READ(RTC_REG_A) & RTC_UIP);
+        while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
+
+        /* Start r4k counter. */
+        write_c0_count(0);
+
+        /* Read counter exactly on falling edge of update flag */
+        while (CMOS_READ(RTC_REG_A) & RTC_UIP);
+        while (!(CMOS_READ(RTC_REG_A) & RTC_UIP));
+
+        count = read_c0_count();
+
+        /* restore interrupts */
+        local_irq_restore(flags);
+#endif
+
+        mips_hpt_frequency = count;
+
+        if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
+            (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
+                count *= 2;
+
+        count += 5000;    /* round */
+        count -= count%10000;
+
+        return count;
+}
+
+static int mips_cpu_timer_irq;
+
+static void mips_timer_dispatch(void)
+{
+        do_IRQ(mips_cpu_timer_irq);
+}
+
+
+unsigned __cpuinit get_c0_compare_int(void)
+{
+#ifdef MSC01E_INT_BASE
+        if (cpu_has_veic) {
+                set_vi_handler(MSC01E_INT_CPUCTR, mips_timer_dispatch);
+                mips_cpu_timer_irq = MSC01E_INT_BASE + MSC01E_INT_CPUCTR;
+
+                return mips_cpu_timer_irq;
+        }
+#endif
+        if (cpu_has_vint)
+                set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
+        mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
+
+        return mips_cpu_timer_irq;
+}
+
+void __init plat_time_init(void)
+{
+        unsigned int est_freq;
+
+        /* Set Data mode - binary. */
+        CMOS_WRITE(CMOS_READ(RTC_CONTROL) | RTC_DM_BINARY, RTC_CONTROL);
+
+        est_freq = estimate_cpu_frequency();
+
+        printk(KERN_INFO "CPU frequency %d.%02d MHz\n", est_freq / 1000000,
+               (est_freq % 1000000) * 100 / 1000000);
+
+        cpu_khz = est_freq / 1000;
+}
diff --git a/arch/mips/netlogic/xlr/irq.c b/arch/mips/netlogic/xlr/irq.c
new file mode 100644
index 00000000000..521bb7377eb
--- /dev/null
+++ b/arch/mips/netlogic/xlr/irq.c
@@ -0,0 +1,300 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/linkage.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+
+#include <asm/mipsregs.h>
+
+#include <asm/netlogic/xlr/iomap.h>
+#include <asm/netlogic/xlr/pic.h>
+#include <asm/netlogic/xlr/xlr.h>
+
+#include <asm/netlogic/interrupt.h>
+#include <asm/netlogic/mips-extns.h>
+
+static u64 nlm_irq_mask;
+static DEFINE_SPINLOCK(nlm_pic_lock);
+
+static void xlr_pic_enable(struct irq_data *d)
+{
+        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
+        unsigned long flags;
+        nlm_reg_t reg;
+        int irq = d->irq;
+
+        WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
+
+        spin_lock_irqsave(&nlm_pic_lock, flags);
+        reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
+        netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
+                          reg | (1 << 6) | (1 << 30) | (1 << 31));
+        spin_unlock_irqrestore(&nlm_pic_lock, flags);
+}
+
+static void xlr_pic_mask(struct irq_data *d)
+{
+        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
+        unsigned long flags;
+        nlm_reg_t reg;
+        int irq = d->irq;
+
+        WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
+
+        spin_lock_irqsave(&nlm_pic_lock, flags);
+        reg = netlogic_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
+        netlogic_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE,
+                          reg | (1 << 6) | (1 << 30) | (0 << 31));
+        spin_unlock_irqrestore(&nlm_pic_lock, flags);
+}
+
+#ifdef CONFIG_PCI
+/* Extra ACK needed for XLR on chip PCI controller */
+static void xlr_pci_ack(struct irq_data *d)
+{
+        nlm_reg_t *pci_mmio = netlogic_io_mmio(NETLOGIC_IO_PCIX_OFFSET);
+
+        netlogic_read_reg(pci_mmio, (0x140 >> 2));
+}
+
+/* Extra ACK needed for XLS on chip PCIe controller */
+static void xls_pcie_ack(struct irq_data *d)
+{
+        nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
+
+        switch (d->irq) {
+        case PIC_PCIE_LINK0_IRQ:
+                netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_LINK1_IRQ:
+                netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_LINK2_IRQ:
+                netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_LINK3_IRQ:
+                netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
+                break;
+        }
+}
+
+/* For XLS B silicon, the 3,4 PCI interrupts are different */
+static void xls_pcie_ack_b(struct irq_data *d)
+{
+        nlm_reg_t *pcie_mmio_le = netlogic_io_mmio(NETLOGIC_IO_PCIE_1_OFFSET);
+
+        switch (d->irq) {
+        case PIC_PCIE_LINK0_IRQ:
+                netlogic_write_reg(pcie_mmio_le, (0x90 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_LINK1_IRQ:
+                netlogic_write_reg(pcie_mmio_le, (0x94 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_XLSB0_LINK2_IRQ:
+                netlogic_write_reg(pcie_mmio_le, (0x190 >> 2), 0xffffffff);
+                break;
+        case PIC_PCIE_XLSB0_LINK3_IRQ:
+                netlogic_write_reg(pcie_mmio_le, (0x194 >> 2), 0xffffffff);
+                break;
+        }
+}
+#endif
+
+static void xlr_pic_ack(struct irq_data *d)
+{
+        unsigned long flags;
+        nlm_reg_t *mmio;
+        int irq = d->irq;
+        void *hd = irq_data_get_irq_handler_data(d);
+
+        WARN(!PIC_IRQ_IS_IRT(irq), "Bad irq %d", irq);
+
+        if (hd) {
+                void (*extra_ack)(void *) = hd;
+                extra_ack(d);
+        }
+        mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
+        spin_lock_irqsave(&nlm_pic_lock, flags);
+        netlogic_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
+        spin_unlock_irqrestore(&nlm_pic_lock, flags);
+}
+
+/*
+ * This chip definition handles interrupts routed thru the XLR
+ * hardware PIC, currently IRQs 8-39 are mapped to hardware intr
+ * 0-31 wired the XLR PIC
+ */
+static struct irq_chip xlr_pic = {
+        .name           = "XLR-PIC",
+        .irq_enable     = xlr_pic_enable,
+        .irq_mask       = xlr_pic_mask,
+        .irq_ack        = xlr_pic_ack,
+};
+
+static void rsvd_irq_handler(struct irq_data *d)
+{
+        WARN(d->irq >= PIC_IRQ_BASE, "Bad irq %d", d->irq);
+}
+
+/*
+ * Chip definition for CPU originated interrupts(timer, msg) and
+ * IPIs
+ */
+struct irq_chip nlm_cpu_intr = {
+        .name           = "XLR-CPU-INTR",
+        .irq_enable     = rsvd_irq_handler,
+        .irq_mask       = rsvd_irq_handler,
+        .irq_ack        = rsvd_irq_handler,
+};
+
+void __init init_xlr_irqs(void)
+{
+        nlm_reg_t *mmio = netlogic_io_mmio(NETLOGIC_IO_PIC_OFFSET);
+        uint32_t thread_mask = 1;
+        int level, i;
+
+        pr_info("Interrupt thread mask [%x]\n", thread_mask);
+        for (i = 0; i < PIC_NUM_IRTS; i++) {
+                level = PIC_IRQ_IS_EDGE_TRIGGERED(i);
+
+                /* Bind all PIC irqs to boot cpu */
+                netlogic_write_reg(mmio, PIC_IRT_0_BASE + i, thread_mask);
+
+                /*
+                 * Use local scheduling and high polarity for all IRTs
+                 * Invalidate all IRTs, by default
+                 */
+                netlogic_write_reg(mmio, PIC_IRT_1_BASE + i,
+                                (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i));
+        }
+
+        /* Make all IRQs as level triggered by default */
+        for (i = 0; i < NR_IRQS; i++) {
+                if (PIC_IRQ_IS_IRT(i))
+                        irq_set_chip_and_handler(i, &xlr_pic, handle_level_irq);
+                else
+                        irq_set_chip_and_handler(i, &nlm_cpu_intr,
+                                                handle_percpu_irq);
+        }
+#ifdef CONFIG_SMP
+        irq_set_chip_and_handler(IRQ_IPI_SMP_FUNCTION, &nlm_cpu_intr,
+                         nlm_smp_function_ipi_handler);
+        irq_set_chip_and_handler(IRQ_IPI_SMP_RESCHEDULE, &nlm_cpu_intr,
+                         nlm_smp_resched_ipi_handler);
+        nlm_irq_mask |=
+            ((1ULL << IRQ_IPI_SMP_FUNCTION) | (1ULL << IRQ_IPI_SMP_RESCHEDULE));
+#endif
+
+#ifdef CONFIG_PCI
+        /*
+         * For PCI interrupts, we need to ack the PIC controller too, overload
+         * irq handler data to do this
+         */
+        if (nlm_chip_is_xls()) {
+                if (nlm_chip_is_xls_b()) {
+                        irq_set_handler_data(PIC_PCIE_LINK0_IRQ,
+                                                        xls_pcie_ack_b);
+                        irq_set_handler_data(PIC_PCIE_LINK1_IRQ,
+                                                        xls_pcie_ack_b);
+                        irq_set_handler_data(PIC_PCIE_XLSB0_LINK2_IRQ,
+                                                        xls_pcie_ack_b);
+                        irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ,
+                                                        xls_pcie_ack_b);
+                } else {
+                        irq_set_handler_data(PIC_PCIE_LINK0_IRQ, xls_pcie_ack);
+                        irq_set_handler_data(PIC_PCIE_LINK1_IRQ, xls_pcie_ack);
+                        irq_set_handler_data(PIC_PCIE_LINK2_IRQ, xls_pcie_ack);
+                        irq_set_handler_data(PIC_PCIE_LINK3_IRQ, xls_pcie_ack);
+                }
+        } else {
+                /* XLR PCI controller ACK */
+                irq_set_handler_data(PIC_PCIE_XLSB0_LINK3_IRQ, xlr_pci_ack);
+        }
+#endif
+        /* unmask all PIC related interrupts. If no handler is installed by the
+         * drivers, it'll just ack the interrupt and return
+         */
+        for (i = PIC_IRT_FIRST_IRQ; i <= PIC_IRT_LAST_IRQ; i++)
+                nlm_irq_mask |= (1ULL << i);
+
+        nlm_irq_mask |= (1ULL << IRQ_TIMER);
+}
+
+void __init arch_init_irq(void)
+{
+        /* Initialize the irq descriptors */
+        init_xlr_irqs();
+        write_c0_eimr(nlm_irq_mask);
+}
+
+void __cpuinit nlm_smp_irq_init(void)
+{
+        /* set interrupt mask for non-zero cpus */
+        write_c0_eimr(nlm_irq_mask);
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+        uint64_t eirr;
+        int i;
+
+        eirr = read_c0_eirr() & read_c0_eimr();
+        if (!eirr)
+                return;
+
+        /* no need of EIRR here, writing compare clears interrupt */
+        if (eirr & (1 << IRQ_TIMER)) {
+                do_IRQ(IRQ_TIMER);
+                return;
+        }
+
+        /* use dcltz: optimize below code */
+        for (i = 63; i != -1; i--) {
+                if (eirr & (1ULL << i))
+                        break;
+        }
+        if (i == -1) {
+                pr_err("no interrupt !!\n");
+                return;
+        }
+
+        /* Ack eirr */
+        write_c0_eirr(1ULL << i);
+
+        do_IRQ(i);
+}
diff --git a/arch/mips/netlogic/xlr/smp.c b/arch/mips/netlogic/xlr/smp.c
new file mode 100644
index 00000000000..d842bce5c94
--- /dev/null
+++ b/arch/mips/netlogic/xlr/smp.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/irq.h>
+
+#include <asm/mmu_context.h>
+
+#include <asm/netlogic/interrupt.h>
+#include <asm/netlogic/mips-extns.h>
+
+#include <asm/netlogic/xlr/iomap.h>
+#include <asm/netlogic/xlr/pic.h>
+#include <asm/netlogic/xlr/xlr.h>
+
+void core_send_ipi(int logical_cpu, unsigned int action)
+{
+        int cpu = cpu_logical_map(logical_cpu);
+        u32 tid = cpu & 0x3;
+        u32 pid = (cpu >> 2) & 0x07;
+        u32 ipi = (tid << 16) | (pid << 20);
+
+        if (action & SMP_CALL_FUNCTION)
+                ipi |= IRQ_IPI_SMP_FUNCTION;
+        else if (action & SMP_RESCHEDULE_YOURSELF)
+                ipi |= IRQ_IPI_SMP_RESCHEDULE;
+        else
+                return;
+
+        pic_send_ipi(ipi);
+}
+
+void nlm_send_ipi_single(int cpu, unsigned int action)
+{
+        core_send_ipi(cpu, action);
+}
+
+void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
+{
+        int cpu;
+
+        for_each_cpu(cpu, mask) {
+                core_send_ipi(cpu, action);
+        }
+}
+
+/* IRQ_IPI_SMP_FUNCTION Handler */
+void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
+{
+        smp_call_function_interrupt();
+}
+
+/* IRQ_IPI_SMP_RESCHEDULE  handler */
+void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
+{
+        scheduler_ipi();
+}
+
+/*
+ * Called before going into mips code, early cpu init
+ */
+void nlm_early_init_secondary(void)
+{
+        write_c0_ebase((uint32_t)nlm_common_ebase);
+        /* TLB partition here later */
+}
+
+/*
+ * Code to run on secondary just after probing the CPU
+ */
+static void __cpuinit nlm_init_secondary(void)
+{
+        nlm_smp_irq_init();
+}
+
+void nlm_smp_finish(void)
+{
+#ifdef notyet
+        nlm_common_msgring_cpu_init();
+#endif
+        local_irq_enable();
+}
+
+void nlm_cpus_done(void)
+{
+}
+
+/*
+ * Boot all other cpus in the system, initialize them, and bring them into
+ * the boot function
+ */
+int nlm_cpu_unblock[NR_CPUS];
+int nlm_cpu_ready[NR_CPUS];
+unsigned long nlm_next_gp;
+unsigned long nlm_next_sp;
+cpumask_t phys_cpu_present_map;
+
+void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
+{
+        unsigned long gp = (unsigned long)task_thread_info(idle);
+        unsigned long sp = (unsigned long)__KSTK_TOS(idle);
+        int cpu = cpu_logical_map(logical_cpu);
+
+        nlm_next_sp = sp;
+        nlm_next_gp = gp;
+
+        /* barrier */
+        __sync();
+        nlm_cpu_unblock[cpu] = 1;
+}
+
+void __init nlm_smp_setup(void)
+{
+        unsigned int boot_cpu;
+        int num_cpus, i;
+
+        boot_cpu = hard_smp_processor_id();
+        cpus_clear(phys_cpu_present_map);
+
+        cpu_set(boot_cpu, phys_cpu_present_map);
+        __cpu_number_map[boot_cpu] = 0;
+        __cpu_logical_map[0] = boot_cpu;
+        cpu_set(0, cpu_possible_map);
+
+        num_cpus = 1;
+        for (i = 0; i < NR_CPUS; i++) {
+                if (nlm_cpu_ready[i]) {
+                        cpu_set(i, phys_cpu_present_map);
+                        __cpu_number_map[i] = num_cpus;
+                        __cpu_logical_map[num_cpus] = i;
+                        cpu_set(num_cpus, cpu_possible_map);
+                        ++num_cpus;
+                }
+        }
+
+        pr_info("Phys CPU present map: %lx, possible map %lx\n",
+                (unsigned long)phys_cpu_present_map.bits[0],
+                (unsigned long)cpu_possible_map.bits[0]);
+
+        pr_info("Detected %i Slave CPU(s)\n", num_cpus);
+}
+
+void nlm_prepare_cpus(unsigned int max_cpus)
+{
+}
+
+struct plat_smp_ops nlm_smp_ops = {
+        .send_ipi_single        = nlm_send_ipi_single,
+        .send_ipi_mask          = nlm_send_ipi_mask,
+        .init_secondary         = nlm_init_secondary,
+        .smp_finish             = nlm_smp_finish,
+        .cpus_done              = nlm_cpus_done,
+        .boot_secondary         = nlm_boot_secondary,
+        .smp_setup              = nlm_smp_setup,
+        .prepare_cpus           = nlm_prepare_cpus,
+};
+
+unsigned long secondary_entry_point;
+
+int nlm_wakeup_secondary_cpus(u32 wakeup_mask)
+{
+        unsigned int tid, pid, ipi, i, boot_cpu;
+        void *reset_vec;
+
+        secondary_entry_point = (unsigned long)prom_pre_boot_secondary_cpus;
+        reset_vec = (void *)CKSEG1ADDR(0x1fc00000);
+        memcpy(reset_vec, nlm_boot_smp_nmi, 0x80);
+        boot_cpu = hard_smp_processor_id();
+
+        for (i = 0; i < NR_CPUS; i++) {
+                if (i == boot_cpu)
+                        continue;
+                if (wakeup_mask & (1u << i)) {
+                        tid = i & 0x3;
+                        pid = (i >> 2) & 0x7;
+                        ipi = (tid << 16) | (pid << 20) | (1 << 8);
+                        pic_send_ipi(ipi);
+                }
+        }
+
+        return 0;
+}
diff --git a/arch/mips/netlogic/xlr/smpboot.S b/arch/mips/netlogic/xlr/smpboot.S
new file mode 100644
index 00000000000..b8e074402c9
--- /dev/null
+++ b/arch/mips/netlogic/xlr/smpboot.S
@@ -0,0 +1,94 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <asm/asm.h>
+#include <asm/asm-offsets.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+
+/* Don't jump to linux function from Bootloader stack. Change it
+ * here. Kernel might allocate bootloader memory before all the CPUs are
+ * brought up (eg: Inode cache region) and we better don't overwrite this
+ * memory
+ */
+NESTED(prom_pre_boot_secondary_cpus, 16, sp)
+        .set    mips64
+        mfc0    t0, $15, 1      # read ebase
+        andi    t0, 0x1f        # t0 has the processor_id()
+        sll     t0, 2           # offset in cpu array
+
+        PTR_LA  t1, nlm_cpu_ready # mark CPU ready
+        PTR_ADDU t1, t0
+        li      t2, 1
+        sw      t2, 0(t1)
+
+        PTR_LA  t1, nlm_cpu_unblock
+        PTR_ADDU t1, t0
+1:      lw      t2, 0(t1)       # wait till unblocked
+        beqz    t2, 1b
+        nop
+
+        PTR_LA  t1, nlm_next_sp
+        PTR_L   sp, 0(t1)
+        PTR_LA  t1, nlm_next_gp
+        PTR_L   gp, 0(t1)
+
+        PTR_LA  t0, nlm_early_init_secondary
+        jalr    t0
+        nop
+
+        PTR_LA  t0, smp_bootstrap
+        jr      t0
+        nop
+END(prom_pre_boot_secondary_cpus)
+
+NESTED(nlm_boot_smp_nmi, 0, sp)
+        .set push
+        .set noat
+        .set mips64
+        .set noreorder
+
+        /* Clear the  NMI and BEV bits */
+        MFC0    k0, CP0_STATUS
+        li      k1, 0xffb7ffff
+        and     k0, k0, k1
+        MTC0    k0, CP0_STATUS
+
+        PTR_LA  k1, secondary_entry_point
+        PTR_L   k0, 0(k1)
+        jr      k0
+        nop
+        .set pop
+END(nlm_boot_smp_nmi)
diff --git a/arch/mips/netlogic/xlr/time.c b/arch/mips/netlogic/xlr/time.c
new file mode 100644
index 00000000000..0d81b262593
--- /dev/null
+++ b/arch/mips/netlogic/xlr/time.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/init.h>
+
+#include <asm/time.h>
+#include <asm/netlogic/interrupt.h>
+#include <asm/netlogic/psb-bootinfo.h>
+
+unsigned int __cpuinit get_c0_compare_int(void)
+{
+        return IRQ_TIMER;
+}
+
+void __init plat_time_init(void)
+{
+        mips_hpt_frequency = nlm_prom_info.cpu_frequency;
+        pr_info("MIPS counter frequency [%ld]\n",
+                (unsigned long)mips_hpt_frequency);
+}
diff --git a/arch/mips/netlogic/xlr/xlr_console.c b/arch/mips/netlogic/xlr/xlr_console.c
new file mode 100644
index 00000000000..759df069220
--- /dev/null
+++ b/arch/mips/netlogic/xlr/xlr_console.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
+ * reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the NetLogic
+ * license below:
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <linux/types.h>
+#include <asm/netlogic/xlr/iomap.h>
+
+void prom_putchar(char c)
+{
+        nlm_reg_t *mmio;
+
+        mmio = netlogic_io_mmio(NETLOGIC_IO_UART_0_OFFSET);
+        while (netlogic_read_reg(mmio, 0x5) == 0)
+                ;
+        netlogic_write_reg(mmio, 0x0, c);
+}
diff --git a/arch/mips/nxp/pnx8550/common/pci.c b/arch/mips/nxp/pnx8550/common/pci.c
new file mode 100644
index 00000000000..98e86ddb86c
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/common/pci.c
@@ -0,0 +1,134 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ *
+ * Author: source@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <pci.h>
+#include <glb.h>
+#include <nand.h>
+
+static struct resource pci_io_resource = {
+        .start  = PNX8550_PCIIO + 0x1000,       /* reserve regacy I/O space */
+        .end    = PNX8550_PCIIO + PNX8550_PCIIO_SIZE,
+        .name   = "pci IO space",
+        .flags  = IORESOURCE_IO
+};
+
+static struct resource pci_mem_resource = {
+        .start  = PNX8550_PCIMEM,
+        .end    = PNX8550_PCIMEM + PNX8550_PCIMEM_SIZE - 1,
+        .name   = "pci memory space",
+        .flags  = IORESOURCE_MEM
+};
+
+extern struct pci_ops pnx8550_pci_ops;
+
+static struct pci_controller pnx8550_controller = {
+        .pci_ops        = &pnx8550_pci_ops,
+        .io_map_base    = PNX8550_PORT_BASE,
+        .io_resource    = &pci_io_resource,
+        .mem_resource   = &pci_mem_resource,
+};
+
+/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
+static inline unsigned long get_system_mem_size(void)
+{
+        /* Read IP2031_RANK0_ADDR_LO */
+        unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
+        /* Read IP2031_RANK1_ADDR_HI */
+        unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
+
+        return dram_r1_hi - dram_r0_lo + 1;
+}
+
+static int __init pnx8550_pci_setup(void)
+{
+        int pci_mem_code;
+        int mem_size = get_system_mem_size() >> 20;
+
+        /* Clear the Global 2 Register, PCI Inta Output Enable Registers
+           Bit 1:Enable DAC Powerdown
+          -> 0:DACs are enabled and are working normally
+             1:DACs are powerdown
+           Bit 0:Enable of PCI inta output
+          -> 0 = Disable PCI inta output
+             1 = Enable PCI inta output
+        */
+        PNX8550_GLB2_ENAB_INTA_O = 0;
+
+        /* Calc the PCI mem size code */
+        if (mem_size >= 128)
+                pci_mem_code = SIZE_128M;
+        else if (mem_size >= 64)
+                pci_mem_code = SIZE_64M;
+        else if (mem_size >= 32)
+                pci_mem_code = SIZE_32M;
+        else
+                pci_mem_code = SIZE_16M;
+
+        /* Set PCI_XIO registers */
+        outl(pci_mem_resource.start, PCI_BASE | PCI_BASE1_LO);
+        outl(pci_mem_resource.end + 1, PCI_BASE | PCI_BASE1_HI);
+        outl(pci_io_resource.start, PCI_BASE | PCI_BASE2_LO);
+        outl(pci_io_resource.end, PCI_BASE | PCI_BASE2_HI);
+
+        /* Send memory transaction via PCI_BASE2 */
+        outl(0x00000001, PCI_BASE | PCI_IO);
+
+        /* Unlock the setup register */
+        outl(0xca, PCI_BASE | PCI_UNLOCKREG);
+
+        /*
+         * BAR0 of PNX8550 (pci base 10) must be zero in order for ide
+         * to work, and in order for bus_to_baddr to work without any
+         * hacks.
+         */
+        outl(0x00000000, PCI_BASE | PCI_BASE10);
+
+        /*
+         *These two bars are set by default or the boot code.
+         * However, it's safer to set them here so we're not boot
+         * code dependent.
+         */
+        outl(0x1be00000, PCI_BASE | PCI_BASE14);  /* PNX MMIO */
+        outl(PNX8550_NAND_BASE_ADDR, PCI_BASE | PCI_BASE18);  /* XIO      */
+
+        outl(PCI_EN_TA |
+             PCI_EN_PCI2MMI |
+             PCI_EN_XIO |
+             PCI_SETUP_BASE18_SIZE(SIZE_32M) |
+             PCI_SETUP_BASE18_EN |
+             PCI_SETUP_BASE14_EN |
+             PCI_SETUP_BASE10_PREF |
+             PCI_SETUP_BASE10_SIZE(pci_mem_code) |
+             PCI_SETUP_CFGMANAGE_EN |
+             PCI_SETUP_PCIARB_EN,
+             PCI_BASE |
+             PCI_SETUP);        /* PCI_SETUP */
+        outl(0x00000000, PCI_BASE | PCI_CTRL);  /* PCI_CONTROL */
+
+        register_pci_controller(&pnx8550_controller);
+
+        return 0;
+}
+
+arch_initcall(pnx8550_pci_setup);
diff --git a/arch/mips/nxp/pnx8550/common/setup.c b/arch/mips/nxp/pnx8550/common/setup.c
new file mode 100644
index 00000000000..71adac32332
--- /dev/null
+++ b/arch/mips/nxp/pnx8550/common/setup.c
@@ -0,0 +1,143 @@
+/*
+ *
+ * 2.6 port, Embedded Alley Solutions, Inc
+ *
+ *  Based on Per Hallsmark, per.hallsmark@mvista.com
+ *
+ *  This program is free software; you can distribute it and/or modify it
+ *  under the terms of the GNU General Public License (Version 2) as
+ *  published by the Free Software Foundation.
+ *
+ *  This program is distributed in the hope it will be useful, but WITHOUT
+ *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ *  for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ */
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/serial_pnx8xxx.h>
+#include <linux/pm.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+#include <asm/pgtable.h>
+#include <asm/time.h>
+
+#include <glb.h>
+#include <int.h>
+#include <pci.h>
+#include <uart.h>
+#include <nand.h>
+
+extern void __init board_setup(void);
+extern void pnx8550_machine_restart(char *);
+extern void pnx8550_machine_halt(void);
+extern void pnx8550_machine_power_off(void);
+extern struct resource ioport_resource;
+extern struct resource iomem_resource;
+extern char *prom_getcmdline(void);
+
+struct resource standard_io_resources[] = {
+        {
+                .start  = 0x00,
+                .end    = 0x1f,
+                .name   = "dma1",
+                .flags  = IORESOURCE_BUSY
+        }, {
+                .start  = 0x40,
+                .end    = 0x5f,
+                .name   = "timer",
+                .flags  = IORESOURCE_BUSY
+        }, {
+                .start  = 0x80,
+                .end    = 0x8f,
+                .name   = "dma page reg",
+                .flags  = IORESOURCE_BUSY
+        }, {
+                .start  = 0xc0,
+                .end    = 0xdf,
+                .name   = "dma2",
+                .flags  = IORESOURCE_BUSY
+        },
+};
+
+#define STANDARD_IO_RESOURCES ARRAY_SIZE(standard_io_resources)
+
+extern struct resource pci_io_resource;
+extern struct resource pci_mem_resource;
+
+/* Return the total size of DRAM-memory, (RANK0 + RANK1) */
+unsigned long get_system_mem_size(void)
+{
+        /* Read IP2031_RANK0_ADDR_LO */
+        unsigned long dram_r0_lo = inl(PCI_BASE | 0x65010);
+        /* Read IP2031_RANK1_ADDR_HI */
+        unsigned long dram_r1_hi = inl(PCI_BASE | 0x65018);
+
+        return dram_r1_hi - dram_r0_lo + 1;
+}
+
+int pnx8550_console_port = -1;
+
+void __init plat_mem_setup(void)
+{
+        int i;
+        char* argptr;
+
+        board_setup();  /* board specific setup */
+
+        _machine_restart = pnx8550_machine_restart;
+        _machine_halt = pnx8550_machine_halt;
+        pm_power_off = pnx8550_machine_power_off;
+
+        /* Clear the Global 2 Register, PCI Inta Output Enable Registers
+           Bit 1:Enable DAC Powerdown
+          -> 0:DACs are enabled and are working normally
+             1:DACs are powerdown
+           Bit 0:Enable of PCI inta output
+          -> 0 = Disable PCI inta output
+             1 = Enable PCI inta output
+        */
+        PNX8550_GLB2_ENAB_INTA_O = 0;
+
+        /* IO/MEM resources. */
+        set_io_port_base(PNX8550_PORT_BASE);
+        ioport_resource.start = 0;
+        ioport_resource.end = ~0;
+        iomem_resource.start = 0;
+        iomem_resource.end = ~0;
+
+        /* Request I/O space for devices on this board */
+        for (i = 0; i < STANDARD_IO_RESOURCES; i++)
+                request_resource(&ioport_resource, standard_io_resources + i);
+
+        /* Place the Mode Control bit for GPIO pin 16 in primary function */
+        /* Pin 16 is used by UART1, UA1_TX                                */
+        outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) |
+                        (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT),
+                        PNX8550_GPIO_MC1);
+
+        argptr = prom_getcmdline();
+        if ((argptr = strstr(argptr, "console=ttyS")) != NULL) {
+                argptr += strlen("console=ttyS");
+                pnx8550_console_port = *argptr == '0' ? 0 : 1;
+
+                /* We must initialize the UART (console) before early printk */
+                /* Set LCR to 8-bit and BAUD to 38400 (no 5)                */
+                ip3106_lcr(UART_BASE, pnx8550_console_port) =
+                        PNX8XXX_UART_LCR_8BIT;
+                ip3106_baud(UART_BASE, pnx8550_console_port) = 5;
+        }
+}
diff --git a/arch/mips/oprofile/op_model_rm9000.c b/arch/mips/oprofile/op_model_rm9000.c
new file mode 100644
index 00000000000..3aa81384966
--- /dev/null
+++ b/arch/mips/oprofile/op_model_rm9000.c
@@ -0,0 +1,138 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 by Ralf Baechle
+ */
+#include <linux/init.h>
+#include <linux/oprofile.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+
+#include "op_impl.h"
+
+#define RM9K_COUNTER1_EVENT(event)      ((event) << 0)
+#define RM9K_COUNTER1_SUPERVISOR        (1ULL    <<  7)
+#define RM9K_COUNTER1_KERNEL            (1ULL    <<  8)
+#define RM9K_COUNTER1_USER              (1ULL    <<  9)
+#define RM9K_COUNTER1_ENABLE            (1ULL    << 10)
+#define RM9K_COUNTER1_OVERFLOW          (1ULL    << 15)
+
+#define RM9K_COUNTER2_EVENT(event)      ((event) << 16)
+#define RM9K_COUNTER2_SUPERVISOR        (1ULL    << 23)
+#define RM9K_COUNTER2_KERNEL            (1ULL    << 24)
+#define RM9K_COUNTER2_USER              (1ULL    << 25)
+#define RM9K_COUNTER2_ENABLE            (1ULL    << 26)
+#define RM9K_COUNTER2_OVERFLOW          (1ULL    << 31)
+
+extern unsigned int rm9000_perfcount_irq;
+
+static struct rm9k_register_config {
+        unsigned int control;
+        unsigned int reset_counter1;
+        unsigned int reset_counter2;
+} reg;
+
+/* Compute all of the registers in preparation for enabling profiling.  */
+
+static void rm9000_reg_setup(struct op_counter_config *ctr)
+{
+        unsigned int control = 0;
+
+        /* Compute the performance counter control word.  */
+        /* For now count kernel and user mode */
+        if (ctr[0].enabled)
+                control |= RM9K_COUNTER1_EVENT(ctr[0].event) |
+                           RM9K_COUNTER1_KERNEL |
+                           RM9K_COUNTER1_USER |
+                           RM9K_COUNTER1_ENABLE;
+        if (ctr[1].enabled)
+                control |= RM9K_COUNTER2_EVENT(ctr[1].event) |
+                           RM9K_COUNTER2_KERNEL |
+                           RM9K_COUNTER2_USER |
+                           RM9K_COUNTER2_ENABLE;
+        reg.control = control;
+
+        reg.reset_counter1 = 0x80000000 - ctr[0].count;
+        reg.reset_counter2 = 0x80000000 - ctr[1].count;
+}
+
+/* Program all of the registers in preparation for enabling profiling.  */
+
+static void rm9000_cpu_setup(void *args)
+{
+        uint64_t perfcount;
+
+        perfcount = ((uint64_t) reg.reset_counter2 << 32) | reg.reset_counter1;
+        write_c0_perfcount(perfcount);
+}
+
+static void rm9000_cpu_start(void *args)
+{
+        /* Start all counters on current CPU */
+        write_c0_perfcontrol(reg.control);
+}
+
+static void rm9000_cpu_stop(void *args)
+{
+        /* Stop all counters on current CPU */
+        write_c0_perfcontrol(0);
+}
+
+static irqreturn_t rm9000_perfcount_handler(int irq, void *dev_id)
+{
+        unsigned int control = read_c0_perfcontrol();
+        struct pt_regs *regs = get_irq_regs();
+        uint32_t counter1, counter2;
+        uint64_t counters;
+
+        /*
+         * RM9000 combines two 32-bit performance counters into a single
+         * 64-bit coprocessor zero register.  To avoid a race updating the
+         * registers we need to stop the counters while we're messing with
+         * them ...
+         */
+        write_c0_perfcontrol(0);
+
+        counters = read_c0_perfcount();
+        counter1 = counters;
+        counter2 = counters >> 32;
+
+        if (control & RM9K_COUNTER1_OVERFLOW) {
+                oprofile_add_sample(regs, 0);
+                counter1 = reg.reset_counter1;
+        }
+        if (control & RM9K_COUNTER2_OVERFLOW) {
+                oprofile_add_sample(regs, 1);
+                counter2 = reg.reset_counter2;
+        }
+
+        counters = ((uint64_t)counter2 << 32) | counter1;
+        write_c0_perfcount(counters);
+        write_c0_perfcontrol(reg.control);
+
+        return IRQ_HANDLED;
+}
+
+static int __init rm9000_init(void)
+{
+        return request_irq(rm9000_perfcount_irq, rm9000_perfcount_handler,
+                           0, "Perfcounter", NULL);
+}
+
+static void rm9000_exit(void)
+{
+        free_irq(rm9000_perfcount_irq, NULL);
+}
+
+struct op_mips_model op_model_rm9000_ops = {
+        .reg_setup      = rm9000_reg_setup,
+        .cpu_setup      = rm9000_cpu_setup,
+        .init           = rm9000_init,
+        .exit           = rm9000_exit,
+        .cpu_start      = rm9000_cpu_start,
+        .cpu_stop       = rm9000_cpu_stop,
+        .cpu_type       = "mips/rm9000",
+        .num_counters   = 2
+};
diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c
new file mode 100644
index 00000000000..e2ddfc49237
--- /dev/null
+++ b/arch/mips/pci/fixup-au1000.c
@@ -0,0 +1,43 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *      Board specific PCI fixups.
+ *
+ * Copyright 2001-2003, 2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/pci.h>
+#include <linux/init.h>
+
+extern char irq_tab_alchemy[][5];
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        return irq_tab_alchemy[slot][pin];
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        return 0;
+}
diff --git a/arch/mips/pci/fixup-yosemite.c b/arch/mips/pci/fixup-yosemite.c
new file mode 100644
index 00000000000..fdafb13a793
--- /dev/null
+++ b/arch/mips/pci/fixup-yosemite.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2003 PMC-Sierra
+ * Author: Manish Lachwani (lachwani@pmc-sierra.com)
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/pci.h>
+
+int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        if (pin == 0)
+                return -1;
+
+        return 3;                       /* Everything goes to one irq bit */
+}
+
+/* Do platform specific device initialization at pci_enable_device() time */
+int pcibios_plat_dev_init(struct pci_dev *dev)
+{
+        return 0;
+}
diff --git a/arch/mips/pci/ops-au1000.c b/arch/mips/pci/ops-au1000.c
new file mode 100644
index 00000000000..9a57c5ab91d
--- /dev/null
+++ b/arch/mips/pci/ops-au1000.c
@@ -0,0 +1,308 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ *      Alchemy/AMD Au1xx0 PCI support.
+ *
+ * Copyright 2001-2003, 2007-2008 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc. <source@mvista.com>
+ *
+ *  Support for all devices (greater than 16) added by David Gathright.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/vmalloc.h>
+
+#include <asm/mach-au1x00/au1000.h>
+
+#undef  DEBUG
+#ifdef  DEBUG
+#define DBG(x...) printk(KERN_DEBUG x)
+#else
+#define DBG(x...)
+#endif
+
+#define PCI_ACCESS_READ  0
+#define PCI_ACCESS_WRITE 1
+
+int (*board_pci_idsel)(unsigned int devsel, int assert);
+
+void mod_wired_entry(int entry, unsigned long entrylo0,
+                unsigned long entrylo1, unsigned long entryhi,
+                unsigned long pagemask)
+{
+        unsigned long old_pagemask;
+        unsigned long old_ctx;
+
+        /* Save old context and create impossible VPN2 value */
+        old_ctx = read_c0_entryhi() & 0xff;
+        old_pagemask = read_c0_pagemask();
+        write_c0_index(entry);
+        write_c0_pagemask(pagemask);
+        write_c0_entryhi(entryhi);
+        write_c0_entrylo0(entrylo0);
+        write_c0_entrylo1(entrylo1);
+        tlb_write_indexed();
+        write_c0_entryhi(old_ctx);
+        write_c0_pagemask(old_pagemask);
+}
+
+static struct vm_struct *pci_cfg_vm;
+static int pci_cfg_wired_entry;
+static unsigned long last_entryLo0, last_entryLo1;
+
+/*
+ * We can't ioremap the entire pci config space because it's too large.
+ * Nor can we call ioremap dynamically because some device drivers use
+ * the PCI config routines from within interrupt handlers and that
+ * becomes a problem in get_vm_area().  We use one wired TLB to handle
+ * all config accesses for all busses.
+ */
+void __init au1x_pci_cfg_init(void)
+{
+        /* Reserve a wired entry for PCI config accesses */
+        pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP);
+        if (!pci_cfg_vm)
+                panic(KERN_ERR "PCI unable to get vm area\n");
+        pci_cfg_wired_entry = read_c0_wired();
+        add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K);
+        last_entryLo0 = last_entryLo1 = 0xffffffff;
+}
+
+static int config_access(unsigned char access_type, struct pci_bus *bus,
+                         unsigned int dev_fn, unsigned char where, u32 *data)
+{
+#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
+        unsigned int device = PCI_SLOT(dev_fn);
+        unsigned int function = PCI_FUNC(dev_fn);
+        unsigned long offset, status;
+        unsigned long cfg_base;
+        unsigned long flags;
+        int error = PCIBIOS_SUCCESSFUL;
+        unsigned long entryLo0, entryLo1;
+
+        if (device > 19) {
+                *data = 0xffffffff;
+                return -1;
+        }
+
+        local_irq_save(flags);
+        au_writel(((0x2000 << 16) | (au_readl(Au1500_PCI_STATCMD) & 0xffff)),
+                        Au1500_PCI_STATCMD);
+        au_sync_udelay(1);
+
+        /*
+         * Allow board vendors to implement their own off-chip IDSEL.
+         * If it doesn't succeed, may as well bail out at this point.
+         */
+        if (board_pci_idsel && board_pci_idsel(device, 1) == 0) {
+                *data = 0xffffffff;
+                local_irq_restore(flags);
+                return -1;
+        }
+
+        /* Setup the config window */
+        if (bus->number == 0)
+                cfg_base = (1 << device) << 11;
+        else
+                cfg_base = 0x80000000 | (bus->number << 16) | (device << 11);
+
+        /* Setup the lower bits of the 36-bit address */
+        offset = (function << 8) | (where & ~0x3);
+        /* Pick up any address that falls below the page mask */
+        offset |= cfg_base & ~PAGE_MASK;
+
+        /* Page boundary */
+        cfg_base = cfg_base & PAGE_MASK;
+
+        /*
+         * To improve performance, if the current device is the same as
+         * the last device accessed, we don't touch the TLB.
+         */
+        entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7;
+        entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7;
+        if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) {
+                mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1,
+                                (unsigned long)pci_cfg_vm->addr, PM_4K);
+                last_entryLo0 = entryLo0;
+                last_entryLo1 = entryLo1;
+        }
+
+        if (access_type == PCI_ACCESS_WRITE)
+                au_writel(*data, (int)(pci_cfg_vm->addr + offset));
+        else
+                *data = au_readl((int)(pci_cfg_vm->addr + offset));
+
+        au_sync_udelay(2);
+
+        DBG("cfg_access %d bus->number %u dev %u at %x *data %x conf %lx\n",
+            access_type, bus->number, device, where, *data, offset);
+
+        /* Check master abort */
+        status = au_readl(Au1500_PCI_STATCMD);
+
+        if (status & (1 << 29)) {
+                *data = 0xffffffff;
+                error = -1;
+                DBG("Au1x Master Abort\n");
+        } else if ((status >> 28) & 0xf) {
+                DBG("PCI ERR detected: device %u, status %lx\n",
+                    device, (status >> 28) & 0xf);
+
+                /* Clear errors */
+                au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD);
+
+                *data = 0xffffffff;
+                error = -1;
+        }
+
+        /* Take away the IDSEL. */
+        if (board_pci_idsel)
+                (void)board_pci_idsel(device, 0);
+
+        local_irq_restore(flags);
+        return error;
+#endif
+}
+
+static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
+                            int where,  u8 *val)
+{
+        u32 data;
+        int ret;
+
+        ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+        if (where & 1)
+                data >>= 8;
+        if (where & 2)
+                data >>= 16;
+        *val = data & 0xff;
+        return ret;
+}
+
+static int read_config_word(struct pci_bus *bus, unsigned int devfn,
+                            int where, u16 *val)
+{
+        u32 data;
+        int ret;
+
+        ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
+        if (where & 2)
+                data >>= 16;
+        *val = data & 0xffff;
+        return ret;
+}
+
+static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
+                             int where, u32 *val)
+{
+        int ret;
+
+        ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
+        return ret;
+}
+
+static int write_config_byte(struct pci_bus *bus, unsigned int devfn,
+                             int where, u8 val)
+{
+        u32 data = 0;
+
+        if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+                return -1;
+
+        data = (data & ~(0xff << ((where & 3) << 3))) |
+               (val << ((where & 3) << 3));
+
+        if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+                return -1;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int write_config_word(struct pci_bus *bus, unsigned int devfn,
+                             int where, u16 val)
+{
+        u32 data = 0;
+
+        if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
+                return -1;
+
+        data = (data & ~(0xffff << ((where & 3) << 3))) |
+               (val << ((where & 3) << 3));
+
+        if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
+                return -1;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int write_config_dword(struct pci_bus *bus, unsigned int devfn,
+                              int where, u32 val)
+{
+        if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
+                return -1;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int config_read(struct pci_bus *bus, unsigned int devfn,
+                       int where, int size, u32 *val)
+{
+        switch (size) {
+        case 1: {
+                        u8 _val;
+                        int rc = read_config_byte(bus, devfn, where, &_val);
+
+                        *val = _val;
+                        return rc;
+                }
+        case 2: {
+                        u16 _val;
+                        int rc = read_config_word(bus, devfn, where, &_val);
+
+                        *val = _val;
+                        return rc;
+                }
+        default:
+                return read_config_dword(bus, devfn, where, val);
+        }
+}
+
+static int config_write(struct pci_bus *bus, unsigned int devfn,
+                        int where, int size, u32 val)
+{
+        switch (size) {
+        case 1:
+                return write_config_byte(bus, devfn, where, (u8) val);
+        case 2:
+                return write_config_word(bus, devfn, where, (u16) val);
+        default:
+                return write_config_dword(bus, devfn, where, val);
+        }
+}
+
+struct pci_ops au1x_pci_ops = {
+        config_read,
+        config_write
+};
diff --git a/arch/mips/pci/ops-titan-ht.c b/arch/mips/pci/ops-titan-ht.c
new file mode 100644
index 00000000000..57d54adc9e2
--- /dev/null
+++ b/arch/mips/pci/ops-titan-ht.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2003 PMC-Sierra
+ * Author: Manish Lachwani (lachwani@pmc-sierra.com)
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <asm/io.h>
+
+#include <asm/titan_dep.h>
+
+static int titan_ht_config_read_dword(struct pci_bus *bus, unsigned int devfn,
+        int offset, u32 *val)
+{
+        volatile uint32_t address;
+        int busno;
+
+        busno = bus->number;
+
+        address = (busno << 16) | (devfn << 8) | (offset & 0xfc) | 0x80000000;
+        if (busno != 0)
+                address |= 1;
+
+        /*
+         * RM9000 HT Errata: Issue back to back HT config
+         * transcations. Issue a BIU sync before and
+         * after the HT cycle
+         */
+
+        *(volatile int32_t *) 0xfb0000f0 |= 0x2;
+
+        udelay(30);
+
+        *(volatile int32_t *) 0xfb0006f8 = address;
+        *(val) = *(volatile int32_t *) 0xfb0006fc;
+
+        udelay(30);
+
+        * (volatile int32_t *) 0xfb0000f0 |= 0x2;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int titan_ht_config_read(struct pci_bus *bus, unsigned int devfn,
+        int offset, int size, u32 *val)
+{
+        uint32_t dword;
+
+        titan_ht_config_read_dword(bus, devfn, offset, &dword);
+
+        dword >>= ((offset & 3) << 3);
+        dword &= (0xffffffffU >> ((4 - size) << 8));
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static inline int titan_ht_config_write_dword(struct pci_bus *bus,
+        unsigned int devfn, int offset, u32 val)
+{
+        volatile uint32_t address;
+        int busno;
+
+        busno = bus->number;
+
+        address = (busno << 16) | (devfn << 8) | (offset & 0xfc) | 0x80000000;
+        if (busno != 0)
+                address |= 1;
+
+        *(volatile int32_t *) 0xfb0000f0 |= 0x2;
+
+        udelay(30);
+
+        *(volatile int32_t *) 0xfb0006f8 = address;
+        *(volatile int32_t *) 0xfb0006fc = val;
+
+        udelay(30);
+
+        *(volatile int32_t *) 0xfb0000f0 |= 0x2;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int titan_ht_config_write(struct pci_bus *bus, unsigned int devfn,
+        int offset, int size, u32 val)
+{
+        uint32_t val1, val2, mask;
+
+        titan_ht_config_read_dword(bus, devfn, offset, &val2);
+
+        val1 = val << ((offset & 3) << 3);
+        mask = ~(0xffffffffU >> ((4 - size) << 8));
+        val2 &= ~(mask << ((offset & 3) << 8));
+
+        titan_ht_config_write_dword(bus, devfn, offset, val1 | val2);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+struct pci_ops titan_ht_pci_ops = {
+        .read   = titan_ht_config_read,
+        .write  = titan_ht_config_write,
+};
diff --git a/arch/mips/pci/ops-titan.c b/arch/mips/pci/ops-titan.c
new file mode 100644
index 00000000000..ebf8fc40e9b
--- /dev/null
+++ b/arch/mips/pci/ops-titan.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2003 PMC-Sierra
+ * Author: Manish Lachwani (lachwani@pmc-sierra.com)
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+
+#include <asm/pci.h>
+#include <asm/io.h>
+#include <asm/rm9k-ocd.h>
+
+/*
+ * PCI specific defines
+ */
+#define TITAN_PCI_0_CONFIG_ADDRESS      0x780
+#define TITAN_PCI_0_CONFIG_DATA         0x784
+
+/*
+ * Titan PCI Config Read Byte
+ */
+static int titan_read_config(struct pci_bus *bus, unsigned int devfn, int reg,
+        int size, u32 * val)
+{
+        uint32_t address, tmp;
+        int dev, busno, func;
+
+        busno = bus->number;
+        dev = PCI_SLOT(devfn);
+        func = PCI_FUNC(devfn);
+
+        address = (busno << 16) | (dev << 11) | (func << 8) |
+                  (reg & 0xfc) | 0x80000000;
+
+
+        /* start the configuration cycle */
+        ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
+        tmp = ocd_readl(TITAN_PCI_0_CONFIG_DATA) >> ((reg & 3) << 3);
+
+        switch (size) {
+        case 1:
+                tmp &= 0xff;
+        case 2:
+                tmp &= 0xffff;
+        }
+        *val = tmp;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int titan_write_config(struct pci_bus *bus, unsigned int devfn, int reg,
+        int size, u32 val)
+{
+        uint32_t address;
+        int dev, busno, func;
+
+        busno = bus->number;
+        dev = PCI_SLOT(devfn);
+        func = PCI_FUNC(devfn);
+
+        address = (busno << 16) | (dev << 11) | (func << 8) |
+                (reg & 0xfc) | 0x80000000;
+
+        /* start the configuration cycle */
+        ocd_writel(address, TITAN_PCI_0_CONFIG_ADDRESS);
+
+        /* write the data */
+        switch (size) {
+        case 1:
+                ocd_writeb(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x3));
+                break;
+
+        case 2:
+                ocd_writew(val, TITAN_PCI_0_CONFIG_DATA + (~reg & 0x2));
+                break;
+
+        case 4:
+                ocd_writel(val, TITAN_PCI_0_CONFIG_DATA);
+                break;
+        }
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+/*
+ * Titan PCI structure
+ */
+struct pci_ops titan_pci_ops = {
+        titan_read_config,
+        titan_write_config,
+};
diff --git a/arch/mips/pci/pci-yosemite.c b/arch/mips/pci/pci-yosemite.c
new file mode 100644
index 00000000000..cf5e1a25cb7
--- /dev/null
+++ b/arch/mips/pci/pci-yosemite.c
@@ -0,0 +1,67 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <asm/titan_dep.h>
+
+extern struct pci_ops titan_pci_ops;
+
+static struct resource py_mem_resource = {
+        .start  = 0xe0000000UL,
+        .end    = 0xe3ffffffUL,
+        .name   = "Titan PCI MEM",
+        .flags  = IORESOURCE_MEM
+};
+
+/*
+ * PMON really reserves 16MB of I/O port space but that's stupid, nothing
+ * needs that much since allocations are limited to 256 bytes per device
+ * anyway.  So we just claim 64kB here.
+ */
+#define TITAN_IO_SIZE   0x0000ffffUL
+#define TITAN_IO_BASE   0xe8000000UL
+
+static struct resource py_io_resource = {
+        .start  = 0x00001000UL,
+        .end    = TITAN_IO_SIZE - 1,
+        .name   = "Titan IO MEM",
+        .flags  = IORESOURCE_IO,
+};
+
+static struct pci_controller py_controller = {
+        .pci_ops        = &titan_pci_ops,
+        .mem_resource   = &py_mem_resource,
+        .mem_offset     = 0x00000000UL,
+        .io_resource    = &py_io_resource,
+        .io_offset      = 0x00000000UL
+};
+
+static char ioremap_failed[] __initdata = "Could not ioremap I/O port range";
+
+static int __init pmc_yosemite_setup(void)
+{
+        unsigned long io_v_base;
+
+        io_v_base = (unsigned long) ioremap(TITAN_IO_BASE, TITAN_IO_SIZE);
+        if (!io_v_base)
+                panic(ioremap_failed);
+
+        set_io_port_base(io_v_base);
+        py_controller.io_map_base = io_v_base;
+        TITAN_WRITE(RM9000x2_OCD_LKM7, TITAN_READ(RM9000x2_OCD_LKM7) | 1);
+
+        ioport_resource.end = TITAN_IO_SIZE - 1;
+
+        register_pci_controller(&py_controller);
+
+        return 0;
+}
+
+arch_initcall(pmc_yosemite_setup);
diff --git a/arch/mips/pmc-sierra/yosemite/Makefile b/arch/mips/pmc-sierra/yosemite/Makefile
new file mode 100644
index 00000000000..02f5fb94ea2
--- /dev/null
+++ b/arch/mips/pmc-sierra/yosemite/Makefile
@@ -0,0 +1,9 @@
+#
+# Makefile for the PMC-Sierra Titan
+#
+
+obj-y    += irq.o prom.o py-console.o setup.o
+
+obj-$(CONFIG_SMP)               += smp.o
+
+ccflags-y := -Werror
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
new file mode 100644
index 00000000000..d6f8bdff8cb
--- /dev/null
+++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
@@ -0,0 +1,169 @@
+/*
+ *  Copyright (C) 2003 PMC-Sierra Inc.
+ *  Author: Manish Lachwani (lachwani@pmc-sierra.com)
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Description:
+ *
+ * This code reads the ATMEL 24CXX EEPROM. The PMC-Sierra Yosemite board uses the ATMEL
+ * 24C32/24C64 which uses two byte addressing as compared to 24C16. Note that this program
+ * uses the serial port like /dev/ttyS0, to communicate with the EEPROM. Hence, you are
+ * expected to have a connectivity from the EEPROM to the serial port. This program does
+ * __not__ communicate using the I2C protocol
+ */
+
+#include "atmel_read_eeprom.h"
+
+static void delay(int delay)
+{
+        while (delay--);
+}
+
+static void send_bit(unsigned char bit)
+{
+        scl_lo;
+        delay(TXX);
+        if (bit)
+                sda_hi;
+        else
+                sda_lo;
+
+        delay(TXX);
+        scl_hi;
+        delay(TXX);
+}
+
+static void send_ack(void)
+{
+        send_bit(0);
+}
+
+static void send_byte(unsigned char byte)
+{
+        int     i = 0;
+
+        for (i = 7; i >= 0; i--)
+                send_bit((byte >> i) & 0x01);
+}
+
+static void send_start(void)
+{
+        sda_hi;
+        delay(TXX);
+        scl_hi;
+        delay(TXX);
+        sda_lo;
+        delay(TXX);
+}
+
+static void send_stop(void)
+{
+        sda_lo;
+        delay(TXX);
+        scl_hi;
+        delay(TXX);
+        sda_hi;
+        delay(TXX);
+}
+
+static void do_idle(void)
+{
+        sda_hi;
+        scl_hi;
+        vcc_off;
+}
+
+static int recv_bit(void)
+{
+        int     status;
+
+        scl_lo;
+        delay(TXX);
+        sda_hi;
+        delay(TXX);
+        scl_hi;
+        delay(TXX);
+
+        return 1;
+}
+
+static unsigned char recv_byte(void) {
+        int i;
+        unsigned char byte=0;
+
+        for (i=7;i>=0;i--)
+                byte |= (recv_bit() << i);
+
+        return byte;
+}
+
+static int recv_ack(void)
+{
+        unsigned int    ack;
+
+        ack = (unsigned int)recv_bit();
+        scl_lo;
+
+        if (ack) {
+                do_idle();
+                printk(KERN_ERR "Error reading the Atmel 24C32/24C64 EEPROM\n");
+                return -1;
+        }
+
+        return ack;
+}
+
+/*
+ * This function does the actual read of the EEPROM. It needs the buffer into which the
+ * read data is copied, the size of the EEPROM being read and the buffer size
+ */
+int read_eeprom(char *buffer, int eeprom_size, int size)
+{
+        int     i = 0, err;
+
+        send_start();
+        send_byte(W_HEADER);
+        recv_ack();
+
+        /* EEPROM with size of more than 2K need two byte addressing */
+        if (eeprom_size > 2048) {
+                send_byte(0x00);
+                recv_ack();
+        }
+
+        send_start();
+        send_byte(R_HEADER);
+        err = recv_ack();
+        if (err == -1)
+                return err;
+
+        for (i = 0; i < size; i++) {
+                *buffer++ = recv_byte();
+                send_ack();
+        }
+
+        /* Note : We should do some check if the buffer contains correct information */
+
+        send_stop();
+}
diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
new file mode 100644
index 00000000000..d6c7ec469fa
--- /dev/null
+++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.h
@@ -0,0 +1,67 @@
+/*
+ *  arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c
+ *
+ *  Copyright (C) 2003 PMC-Sierra Inc.
+ *  Author: Manish Lachwani (lachwani@pmc-sierra.com)
+ *  Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Header file for atmel_read_eeprom.c
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <asm/pci.h>
+#include <asm/io.h>
+#include <linux/init.h>
+#include <asm/termios.h>
+#include <asm/ioctls.h>
+#include <linux/ioctl.h>
+#include <linux/fcntl.h>
+
+#define DEFAULT_PORT    "/dev/ttyS0"    /* Port to open */
+#define TXX             0               /* Dummy loop for spinning */
+
+#define BLOCK_SEL       0x00
+#define SLAVE_ADDR      0xa0
+#define READ_BIT        0x01
+#define WRITE_BIT       0x00
+#define R_HEADER        SLAVE_ADDR + BLOCK_SEL + READ_BIT
+#define W_HEADER        SLAVE_ADDR + BLOCK_SEL + WRITE_BIT
+
+/*
+ * Clock, Voltages and Data
+ */
+#define vcc_off         (ioctl(fd, TIOCSBRK, 0))
+#define vcc_on          (ioctl(fd, TIOCCBRK, 0))
+#define sda_hi          (ioctl(fd, TIOCMBIS, &dtr))
+#define sda_lo          (ioctl(fd, TIOCMBIC, &dtr))
+#define scl_lo          (ioctl(fd, TIOCMBIC, &rts))
+#define scl_hi          (ioctl(fd, TIOCMBIS, &rts))
+
+const char rts = TIOCM_RTS;
+const char dtr = TIOCM_DTR;
+int fd;
diff --git a/arch/mips/pmc-sierra/yosemite/ht-irq.c b/arch/mips/pmc-sierra/yosemite/ht-irq.c
new file mode 100644
index 00000000000..86b98e98fb4
--- /dev/null
+++ b/arch/mips/pmc-sierra/yosemite/ht-irq.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2003 PMC-Sierra
+ * Author: Manish Lachwani (lachwani@pmc-sierra.com)
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <asm/pci.h>
+
+/*
+ * HT Bus fixup for the Titan
+ * XXX IRQ values need to change based on the board layout
+ */
+void __init titan_ht_pcibios_fixup_bus(struct pci_bus *bus)
+{
+        struct pci_bus *current_bus = bus;
+        struct pci_dev *devices;
+        struct list_head *devices_link;
+
+        list_for_each(devices_link, &(current_bus->devices)) {
+                devices = pci_dev_b(devices_link);
+                if (devices == NULL)
+                        continue;
+        }
+
+        /*
+         * PLX and SPKT related changes go here
+         */
+}
diff --git a/arch/mips/pmc-sierra/yosemite/ht.c b/arch/mips/pmc-sierra/yosemite/ht.c
new file mode 100644
index 00000000000..63be40e470d
--- /dev/null
+++ b/arch/mips/pmc-sierra/yosemite/ht.c
@@ -0,0 +1,415 @@
+/*
+ * Copyright 2003 PMC-Sierra
+ * Author: Manish Lachwani (lachwani@pmc-sierra.com)
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <asm/pci.h>
+#include <asm/io.h>
+
+#include <linux/init.h>
+#include <asm/titan_dep.h>
+
+#ifdef CONFIG_HYPERTRANSPORT
+
+
+/*
+ * This function check if the Hypertransport Link Initialization completed. If
+ * it did, then proceed further with scanning bus #2
+ */
+static __inline__ int check_titan_htlink(void)
+{
+        u32 val;
+
+        val = *(volatile uint32_t *)(RM9000x2_HTLINK_REG);
+        if (val & 0x00000020)
+                /* HT Link Initialization completed */
+                return 1;
+        else
+                return 0;
+}
+
+static int titan_ht_config_read_dword(struct pci_dev *device,
+                                             int offset, u32* val)
+{
+        int dev, bus, func;
+        uint32_t address_reg, data_reg;
+        uint32_t address;
+
+        bus = device->bus->number;
+        dev = PCI_SLOT(device->devfn);
+        func = PCI_FUNC(device->devfn);
+
+        /* XXX Need to change the Bus # */
+        if (bus > 2)
+                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
+                                                        0x80000000 | 0x1;
+        else
+                address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
+
+        address_reg = RM9000x2_OCD_HTCFGA;
+        data_reg =  RM9000x2_OCD_HTCFGD;
+
+        RM9K_WRITE(address_reg, address);
+        RM9K_READ(data_reg, val);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int titan_ht_config_read_word(struct pci_dev *device,
+                                             int offset, u16* val)
+{
+        int dev, bus, func;
+        uint32_t address_reg, data_reg;
+        uint32_t address;
+
+        bus = device->bus->number;
+        dev = PCI_SLOT(device->devfn);
+        func = PCI_FUNC(device->devfn);
+
+        /* XXX Need to change the Bus # */
+        if (bus > 2)
+                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
+                                                0x80000000 | 0x1;
+        else
+                address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
+
+        address_reg = RM9000x2_OCD_HTCFGA;
+        data_reg =  RM9000x2_OCD_HTCFGD;
+
+        if ((offset & 0x3) == 0)
+                offset = 0x2;
+        else
+                offset = 0x0;
+
+        RM9K_WRITE(address_reg, address);
+        RM9K_READ_16(data_reg + offset, val);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+
+u32 longswap(unsigned long l)
+{
+        unsigned char b1, b2, b3, b4;
+
+        b1 = l&255;
+        b2 = (l>>8)&255;
+        b3 = (l>>16)&255;
+        b4 = (l>>24)&255;
+
+        return ((b1<<24) + (b2<<16) + (b3<<8) + b4);
+}
+
+
+static int titan_ht_config_read_byte(struct pci_dev *device,
+                                             int offset, u8* val)
+{
+        int dev, bus, func;
+        uint32_t address_reg, data_reg;
+        uint32_t address;
+        int offset1;
+
+        bus = device->bus->number;
+        dev = PCI_SLOT(device->devfn);
+        func = PCI_FUNC(device->devfn);
+
+        /* XXX Need to change the Bus # */
+        if (bus > 2)
+                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
+                                                        0x80000000 | 0x1;
+        else
+                address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
+
+        address_reg = RM9000x2_OCD_HTCFGA;
+        data_reg =  RM9000x2_OCD_HTCFGD;
+
+        RM9K_WRITE(address_reg, address);
+
+        if ((offset & 0x3) == 0) {
+                offset1 = 0x3;
+        }
+        if ((offset & 0x3) == 1) {
+                offset1 = 0x2;
+        }
+        if ((offset & 0x3) == 2) {
+                offset1 = 0x1;
+        }
+        if ((offset & 0x3) == 3) {
+                offset1 = 0x0;
+        }
+        RM9K_READ_8(data_reg + offset1, val);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int titan_ht_config_write_dword(struct pci_dev *device,
+                                             int offset, u8 val)
+{
+        int dev, bus, func;
+        uint32_t address_reg, data_reg;
+        uint32_t address;
+
+        bus = device->bus->number;
+        dev = PCI_SLOT(device->devfn);
+        func = PCI_FUNC(device->devfn);
+
+        /* XXX Need to change the Bus # */
+        if (bus > 2)
+                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
+                                                        0x80000000 | 0x1;
+        else
+              address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
+
+        address_reg = RM9000x2_OCD_HTCFGA;
+        data_reg =  RM9000x2_OCD_HTCFGD;
+
+        RM9K_WRITE(address_reg, address);
+        RM9K_WRITE(data_reg, val);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int titan_ht_config_write_word(struct pci_dev *device,
+                                             int offset, u8 val)
+{
+        int dev, bus, func;
+        uint32_t address_reg, data_reg;
+        uint32_t address;
+
+        bus = device->bus->number;
+        dev = PCI_SLOT(device->devfn);
+        func = PCI_FUNC(device->devfn);
+
+        /* XXX Need to change the Bus # */
+        if (bus > 2)
+                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
+                                0x80000000 | 0x1;
+        else
+                address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
+
+        address_reg = RM9000x2_OCD_HTCFGA;
+        data_reg =  RM9000x2_OCD_HTCFGD;
+
+        if ((offset & 0x3) == 0)
+                offset = 0x2;
+        else
+                offset = 0x0;
+
+        RM9K_WRITE(address_reg, address);
+        RM9K_WRITE_16(data_reg + offset, val);
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int titan_ht_config_write_byte(struct pci_dev *device,
+                                             int offset, u8 val)
+{
+        int dev, bus, func;
+        uint32_t address_reg, data_reg;
+        uint32_t address;
+        int offset1;
+
+        bus = device->bus->number;
+        dev = PCI_SLOT(device->devfn);
+        func = PCI_FUNC(device->devfn);
+
+        /* XXX Need to change the Bus # */
+        if (bus > 2)
+                address = (bus << 16) | (dev << 11) | (func << 8) | (offset & 0xfc) |
+                                0x80000000 | 0x1;
+        else
+                address = (dev << 11) | (func << 8) | (offset & 0xfc) | 0x80000000;
+
+        address_reg = RM9000x2_OCD_HTCFGA;
+        data_reg =  RM9000x2_OCD_HTCFGD;
+
+        RM9K_WRITE(address_reg, address);
+
+        if ((offset & 0x3) == 0) {
+             offset1 = 0x3;
+        }
+        if ((offset & 0x3) == 1) {
+             offset1 = 0x2;
+        }
+        if ((offset & 0x3) == 2) {
+             offset1 = 0x1;
+        }
+        if ((offset & 0x3) == 3) {
+            offset1 = 0x0;
+        }
+
+        RM9K_WRITE_8(data_reg + offset1, val);
+        return PCIBIOS_SUCCESSFUL;
+}
+
+
+static void titan_pcibios_set_master(struct pci_dev *dev)
+{
+        u16 cmd;
+        int bus = dev->bus->number;
+
+        if (check_titan_htlink())
+            titan_ht_config_read_word(dev, PCI_COMMAND, &cmd);
+
+        cmd |= PCI_COMMAND_MASTER;
+
+        if (check_titan_htlink())
+            titan_ht_config_write_word(dev, PCI_COMMAND, cmd);
+}
+
+
+int pcibios_enable_resources(struct pci_dev *dev)
+{
+        u16 cmd, old_cmd;
+        u8 tmp1;
+        int idx;
+        struct resource *r;
+        int bus = dev->bus->number;
+
+        if (check_titan_htlink())
+            titan_ht_config_read_word(dev, PCI_COMMAND, &cmd);
+
+        old_cmd = cmd;
+        for (idx = 0; idx < 6; idx++) {
+                r = &dev->resource[idx];
+                if (!r->start && r->end) {
+                        printk(KERN_ERR
+                               "PCI: Device %s not available because of "
+                               "resource collisions\n", pci_name(dev));
+                        return -EINVAL;
+                }
+                if (r->flags & IORESOURCE_IO)
+                        cmd |= PCI_COMMAND_IO;
+                if (r->flags & IORESOURCE_MEM)
+                        cmd |= PCI_COMMAND_MEMORY;
+        }
+        if (cmd != old_cmd) {
+                if (check_titan_htlink())
+                   titan_ht_config_write_word(dev, PCI_COMMAND, cmd);
+        }
+
+        if (check_titan_htlink())
+                titan_ht_config_read_byte(dev, PCI_CACHE_LINE_SIZE, &tmp1);
+
+        if (tmp1 != 8) {
+                printk(KERN_WARNING "PCI setting cache line size to 8 from "
+                       "%d\n", tmp1);
+        }
+
+        if (check_titan_htlink())
+                titan_ht_config_write_byte(dev, PCI_CACHE_LINE_SIZE, 8);
+
+        if (check_titan_htlink())
+                titan_ht_config_read_byte(dev, PCI_LATENCY_TIMER, &tmp1);
+
+        if (tmp1 < 32 || tmp1 == 0xff) {
+                printk(KERN_WARNING "PCI setting latency timer to 32 from %d\n",
+                       tmp1);
+        }
+
+        if (check_titan_htlink())
+                titan_ht_config_write_byte(dev, PCI_LATENCY_TIMER, 32);
+
+        return 0;
+}
+
+
+int pcibios_enable_device(struct pci_dev *dev, int mask)
+{
+        return pcibios_enable_resources(dev);
+}
+
+resource_size_t pcibios_align_resource(void *data, const struct resource *res,
+                                resource_size_t size, resource_size_t align)
+{
+        struct pci_dev *dev = data;
+        resource_size_t start = res->start;
+
+        if (res->flags & IORESOURCE_IO) {
+                /* We need to avoid collisions with `mirrored' VGA ports
+                   and other strange ISA hardware, so we always want the
+                   addresses kilobyte aligned.  */
+                if (size > 0x100) {
+                        printk(KERN_ERR "PCI: I/O Region %s/%d too large"
+                               " (%ld bytes)\n", pci_name(dev),
+                                dev->resource - res, size);
+                }
+
+                start = (start + 1024 - 1) & ~(1024 - 1);
+        }
+
+        return start;
+}
+
+struct pci_ops titan_pci_ops = {
+        titan_ht_config_read_byte,
+        titan_ht_config_read_word,
+        titan_ht_config_read_dword,
+        titan_ht_config_write_byte,
+        titan_ht_config_write_word,
+        titan_ht_config_write_dword
+};
+
+void __init pcibios_fixup_bus(struct pci_bus *c)
+{
+        titan_ht_pcibios_fixup_bus(c);
+}
+
+void __init pcibios_init(void)
+{
+
+        /* Reset PCI I/O and PCI MEM values */
+        /* XXX Need to add the proper values here */
+        ioport_resource.start = 0xe0000000;
+        ioport_resource.end   = 0xe0000000 + 0x20000000 - 1;
+        iomem_resource.start  = 0xc0000000;
+        iomem_resource.end    = 0xc0000000 + 0x20000000 - 1;
+
+        /* XXX Need to add bus values */
+        pci_scan_bus(2, &titan_pci_ops, NULL);
+        pci_scan_bus(3, &titan_pci_ops, NULL);
+}
+
+/*
+ * for parsing "pci=" kernel boot arguments.
+ */
+char *pcibios_setup(char *str)
+{
+        printk(KERN_INFO "rr: pcibios_setup\n");
+        /* Nothing to do for now.  */
+
+        return str;
+}
+
+unsigned __init int pcibios_assign_all_busses(void)
+{
+        /* We want to use the PCI bus detection done by PMON */
+        return 0;
+}
+
+#endif /* CONFIG_HYPERTRANSPORT */
diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c
new file mode 100644
index 00000000000..25bbbf428be
--- /dev/null
+++ b/arch/mips/pmc-sierra/yosemite/irq.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (C) 2003 PMC-Sierra Inc.
+ * Author: Manish Lachwani (lachwani@pmc-sierra.com)
+ *
+ * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Second level Interrupt handlers for the PMC-Sierra Titan/Yosemite board
+ */
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/timex.h>
+#include <linux/random.h>
+#include <linux/bitops.h>
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/irq_cpu.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/titan_dep.h>
+
+/* Hypertransport specific */
+#define IRQ_ACK_BITS            0x00000000      /* Ack bits */
+
+#define HYPERTRANSPORT_INTA     0x78            /* INTA# */
+#define HYPERTRANSPORT_INTB     0x79            /* INTB# */
+#define HYPERTRANSPORT_INTC     0x7a            /* INTC# */
+#define HYPERTRANSPORT_INTD     0x7b            /* INTD# */
+
+extern void titan_mailbox_irq(void);
+
+#ifdef CONFIG_HYPERTRANSPORT
+/*
+ * Handle hypertransport & SMP interrupts. The interrupt lines are scarce.
+ * For interprocessor interrupts, the best thing to do is to use the INTMSG
+ * register. We use the same external interrupt line, i.e. INTB3 and monitor
+ * another status bit
+ */
+static void ll_ht_smp_irq_handler(int irq)
+{
+        u32 status = OCD_READ(RM9000x2_OCD_INTP0STATUS4);
+
+        /* Ack all the bits that correspond to the interrupt sources */
+        if (status != 0)
+                OCD_WRITE(RM9000x2_OCD_INTP0STATUS4, IRQ_ACK_BITS);
+
+        status = OCD_READ(RM9000x2_OCD_INTP1STATUS4);
+        if (status != 0)
+                OCD_WRITE(RM9000x2_OCD_INTP1STATUS4, IRQ_ACK_BITS);
+
+#ifdef CONFIG_HT_LEVEL_TRIGGER
+        /*
+         * Level Trigger Mode only. Send the HT EOI message back to the source.
+         */
+        switch (status) {
+        case 0x1000000:
+                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA);
+                break;
+        case 0x2000000:
+                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB);
+                break;
+        case 0x4000000:
+                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC);
+                break;
+        case 0x8000000:
+                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD);
+                break;
+        case 0x0000001:
+                /* PLX */
+                OCD_WRITE(RM9000x2_OCD_HTEOI, 0x20);
+                OCD_WRITE(IRQ_CLEAR_REG, IRQ_ACK_BITS);
+                break;
+        case 0xf000000:
+                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA);
+                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB);
+                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC);
+                OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD);
+                break;
+        }
+#endif /* CONFIG_HT_LEVEL_TRIGGER */
+
+        do_IRQ(irq);
+}
+#endif
+
+asmlinkage void plat_irq_dispatch(void)
+{
+        unsigned int cause = read_c0_cause();
+        unsigned int status = read_c0_status();
+        unsigned int pending = cause & status;
+
+        if (pending & STATUSF_IP7) {
+                do_IRQ(7);
+        } else if (pending & STATUSF_IP2) {
+#ifdef CONFIG_HYPERTRANSPORT
+                ll_ht_smp_irq_handler(2);
+#else
+                do_IRQ(2);
+#endif
+        } else if (pending & STATUSF_IP3) {
+                do_IRQ(3);
+        } else if (pending & STATUSF_IP4) {
+                do_IRQ(4);
+        } else if (pending & STATUSF_IP5) {
+#ifdef CONFIG_SMP
+                titan_mailbox_irq();
+#else
+                do_IRQ(5);
+#endif
+        } else if (pending & STATUSF_IP6) {
+                do_IRQ(4);
+        }
+}
+
+/*
+ * Initialize the next level interrupt handler
+ */
+void __init arch_init_irq(void)
+{
+        clear_c0_status(ST0_IM);
+
+        mips_cpu_irq_init();
+        rm7k_cpu_irq_init();
+        rm9k_cpu_irq_init();
+}
diff --git a/arch/mips/pmc-sierra/yosemite/prom.c b/arch/mips/pmc-sierra/yosemite/prom.c
new file mode 100644
index 00000000000..cf4c868715a
--- /dev/null
+++ b/arch/mips/pmc-sierra/yosemite/prom.c
@@ -0,0 +1,143 @@
+/*
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * Copyright (C) 2003, 2004 PMC-Sierra Inc.
+ * Author: Manish Lachwani (lachwani@pmc-sierra.com)
+ * Copyright (C) 2004 Ralf Baechle
+ */
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/smp.h>
+
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/smp-ops.h>
+#include <asm/system.h>
+#include <asm/bootinfo.h>
+#include <asm/pmon.h>
+
+#ifdef CONFIG_SMP
+extern void prom_grab_secondary(void);
+#else
+#define prom_grab_secondary() do { } while (0)
+#endif
+
+#include "setup.h"
+
+struct callvectors *debug_vectors;
+
+extern unsigned long yosemite_base;
+extern unsigned long cpu_clock_freq;
+
+const char *get_system_type(void)
+{
+        return "PMC-Sierra Yosemite";
+}
+
+static void prom_cpu0_exit(void *arg)
+{
+        void *nvram = (void *) YOSEMITE_RTC_BASE;
+
+        /* Ask the NVRAM/RTC/watchdog chip to assert reset in 1/16 second */
+        writeb(0x84, nvram + 0xff7);
+
+        /* wait for the watchdog to go off */
+        mdelay(100 + (1000 / 16));
+
+        /* if the watchdog fails for some reason, let people know */
+        printk(KERN_NOTICE "Watchdog reset failed\n");
+}
+
+/*
+ * Reset the NVRAM over the local bus
+ */
+static void prom_exit(void)
+{
+#ifdef CONFIG_SMP
+        if (smp_processor_id())
+                /* CPU 1 */
+                smp_call_function(prom_cpu0_exit, NULL, 1);
+#endif
+        prom_cpu0_exit(NULL);
+}
+
+/*
+ * Halt the system
+ */
+static void prom_halt(void)
+{
+        printk(KERN_NOTICE "\n** You can safely turn off the power\n");
+        while (1)
+                __asm__(".set\tmips3\n\t" "wait\n\t" ".set\tmips0");
+}
+
+extern struct plat_smp_ops yos_smp_ops;
+
+/*
+ * Init routine which accepts the variables from PMON
+ */
+void __init prom_init(void)
+{
+        int argc = fw_arg0;
+        char **arg = (char **) fw_arg1;
+        char **env = (char **) fw_arg2;
+        struct callvectors *cv = (struct callvectors *) fw_arg3;
+        int i = 0;
+
+        /* Callbacks for halt, restart */
+        _machine_restart = (void (*)(char *)) prom_exit;
+        _machine_halt = prom_halt;
+        pm_power_off = prom_halt;
+
+        debug_vectors = cv;
+        arcs_cmdline[0] = '\0';
+
+        /* Get the boot parameters */
+        for (i = 1; i < argc; i++) {
+                if (strlen(arcs_cmdline) + strlen(arg[i] + 1) >=
+                    sizeof(arcs_cmdline))
+                        break;
+
+                strcat(arcs_cmdline, arg[i]);
+                strcat(arcs_cmdline, " ");
+        }
+
+#ifdef CONFIG_SERIAL_8250_CONSOLE
+        if ((strstr(arcs_cmdline, "console=ttyS")) == NULL)
+                strcat(arcs_cmdline, "console=ttyS0,115200");
+#endif
+
+        while (*env) {
+                if (strncmp("ocd_base", *env, strlen("ocd_base")) == 0)
+                        yosemite_base =
+                            simple_strtol(*env + strlen("ocd_base="), NULL,
+                                          16);
+
+                if (strncmp("cpuclock", *env, strlen("cpuclock")) == 0)
+                        cpu_clock_freq =
+                            simple_strtol(*env + strlen("cpuclock="), NULL,
+                                          10);
+
+                env++;
+        }
+
+        prom_grab_secondary();
+
+        register_smp_ops(&yos_smp_ops);
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
+
+void __init prom_fixup_mem_map(unsigned long start, unsigned long end)
+{
+}
diff --git a/arch/mips/pmc-sierra/yosemite/py-console.c b/arch/mips/pmc-sierra/yosemite/py-console.c
new file mode 100644
index 00000000000..434d7b1a8c6
--- /dev/null
+++ b/arch/mips/pmc-sierra/yosemite/py-console.c
@@ -0,0 +1,117 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2001, 2002, 2004 Ralf Baechle
+ */
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/kdev_t.h>
+#include <linux/major.h>
+#include <linux/termios.h>
+#include <linux/sched.h>
+#include <linux/tty.h>
+
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <asm/serial.h>
+#include <asm/io.h>
+
+/* SUPERIO uart register map */
+struct yo_uartregs {
+        union {
+                volatile u8     rbr;    /* read only, DLAB == 0 */
+                volatile u8     thr;    /* write only, DLAB == 0 */
+                volatile u8     dll;    /* DLAB == 1 */
+        } u1;
+        union {
+                volatile u8     ier;    /* DLAB == 0 */
+                volatile u8     dlm;    /* DLAB == 1 */
+        } u2;
+        union {
+                volatile u8     iir;    /* read only */
+                volatile u8     fcr;    /* write only */
+        } u3;
+        volatile u8     iu_lcr;
+        volatile u8     iu_mcr;
+        volatile u8     iu_lsr;
+        volatile u8     iu_msr;
+        volatile u8     iu_scr;
+} yo_uregs_t;
+
+#define iu_rbr u1.rbr
+#define iu_thr u1.thr
+#define iu_dll u1.dll
+#define iu_ier u2.ier
+#define iu_dlm u2.dlm
+#define iu_iir u3.iir
+#define iu_fcr u3.fcr
+
+#define ssnop()         __asm__ __volatile__("sll       $0, $0, 1\n");
+#define ssnop_4()       do { ssnop(); ssnop(); ssnop(); ssnop(); } while (0)
+
+#define IO_BASE_64      0x9000000000000000ULL
+
+static unsigned char readb_outer_space(unsigned long long phys)
+{
+        unsigned long long vaddr = IO_BASE_64 | phys;
+        unsigned char res;
+        unsigned int sr;
+
+        sr = read_c0_status();
+        write_c0_status((sr | ST0_KX) & ~ ST0_IE);
+        ssnop_4();
+
+        __asm__ __volatile__ (
+        "       .set    mips3           \n"
+        "       .set    push            \n"
+        "       .set    noreorder       \n"
+        "       .set    nomacro         \n"
+        "       ld      %0, %1          \n"
+        "       .set    pop             \n"
+        "       lbu     %0, (%0)        \n"
+        "       .set    mips0           \n"
+        : "=r" (res)
+        : "R" (vaddr));
+
+        write_c0_status(sr);
+        ssnop_4();
+
+        return res;
+}
+
+static void writeb_outer_space(unsigned long long phys, unsigned char c)
+{
+        unsigned long long vaddr = IO_BASE_64 | phys;
+        unsigned long tmp;
+        unsigned int sr;
+
+        sr = read_c0_status();
+        write_c0_status((sr | ST0_KX) & ~ ST0_IE);
+        ssnop_4();
+
+        __asm__ __volatile__ (
+        "       .set    mips3           \n"
+        "       .set    push            \n"
+        "       .set    noreorder       \n"
+        "       .set    nomacro         \n"
+        "       ld      %0, %1          \n"
+        "       .set    pop             \n"
+        "       sb      %2, (%0)        \n"
+        "       .set    mips0           \n"
+        : "=&r" (tmp)
+        : "R" (vaddr), "r" (c));
+
+        write_c0_status(sr);
+        ssnop_4();
+}
+
+void prom_putchar(char c)
+{
+        unsigned long lsr = 0xfd000008ULL + offsetof(struct yo_uartregs, iu_lsr);
+        unsigned long thr = 0xfd000008ULL + offsetof(struct yo_uartregs, iu_thr);
+
+        while ((readb_outer_space(lsr) & 0x20) == 0);
+        writeb_outer_space(thr, c);
+}
diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c
new file mode 100644
index 00000000000..3498ac9c35a
--- /dev/null
+++ b/arch/mips/pmc-sierra/yosemite/setup.c
@@ -0,0 +1,223 @@
+/*
+ *  Copyright (C) 2003 PMC-Sierra Inc.
+ *  Author: Manish Lachwani (lachwani@pmc-sierra.com)
+ *
+ * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
+ *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
+ *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
+ *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
+ *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *  You should have received a copy of the  GNU General Public License along
+ *  with this program; if not, write  to the Free Software Foundation, Inc.,
+ *  675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/bcd.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/mm.h>
+#include <linux/bootmem.h>
+#include <linux/swap.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/timex.h>
+#include <linux/termios.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+
+#include <asm/time.h>
+#include <asm/bootinfo.h>
+#include <asm/page.h>
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/serial.h>
+#include <asm/titan_dep.h>
+#include <asm/m48t37.h>
+
+#include "setup.h"
+
+unsigned char titan_ge_mac_addr_base[6] = {
+        // 0x00, 0x03, 0xcc, 0x1d, 0x22, 0x00
+        0x00, 0xe0, 0x04, 0x00, 0x00, 0x21
+};
+
+unsigned long cpu_clock_freq;
+unsigned long yosemite_base;
+
+static struct m48t37_rtc *m48t37_base;
+
+void __init bus_error_init(void)
+{
+        /* Do nothing */
+}
+
+
+void read_persistent_clock(struct timespec *ts)
+{
+        unsigned int year, month, day, hour, min, sec;
+        unsigned long flags;
+
+        spin_lock_irqsave(&rtc_lock, flags);
+        /* Stop the update to the time */
+        m48t37_base->control = 0x40;
+
+        year = bcd2bin(m48t37_base->year);
+        year += bcd2bin(m48t37_base->century) * 100;
+
+        month = bcd2bin(m48t37_base->month);
+        day = bcd2bin(m48t37_base->date);
+        hour = bcd2bin(m48t37_base->hour);
+        min = bcd2bin(m48t37_base->min);
+        sec = bcd2bin(m48t37_base->sec);
+
+        /* Start the update to the time again */
+        m48t37_base->control = 0x00;
+        spin_unlock_irqrestore(&rtc_lock, flags);
+
+        ts->tv_sec = mktime(year, month, day, hour, min, sec);
+        ts->tv_nsec = 0;
+}
+
+int rtc_mips_set_time(unsigned long tim)
+{
+        struct rtc_time tm;
+        unsigned long flags;
+
+        /*
+         * Convert to a more useful format -- note months count from 0
+         * and years from 1900
+         */
+        rtc_time_to_tm(tim, &tm);
+        tm.tm_year += 1900;
+        tm.tm_mon += 1;
+
+        spin_lock_irqsave(&rtc_lock, flags);
+        /* enable writing */
+        m48t37_base->control = 0x80;
+
+        /* year */
+        m48t37_base->year = bin2bcd(tm.tm_year % 100);
+        m48t37_base->century = bin2bcd(tm.tm_year / 100);
+
+        /* month */
+        m48t37_base->month = bin2bcd(tm.tm_mon);
+
+        /* day */
+        m48t37_base->date = bin2bcd(tm.tm_mday);
+
+        /* hour/min/sec */
+        m48t37_base->hour = bin2bcd(tm.tm_hour);
+        m48t37_base->min = bin2bcd(tm.tm_min);
+        m48t37_base->sec = bin2bcd(tm.tm_sec);
+
+        /* day of week -- not really used, but let's keep it up-to-date */
+        m48t37_base->day = bin2bcd(tm.tm_wday + 1);
+
+        /* disable writing */
+        m48t37_base->control = 0x00;
+        spin_unlock_irqrestore(&rtc_lock, flags);
+
+        return 0;
+}
+
+void __init plat_time_init(void)
+{
+        mips_hpt_frequency = cpu_clock_freq / 2;
+mips_hpt_frequency = 33000000 * 3 * 5;
+}
+
+unsigned long ocd_base;
+
+EXPORT_SYMBOL(ocd_base);
+
+/*
+ * Common setup before any secondaries are started
+ */
+
+#define TITAN_UART_CLK          3686400
+#define TITAN_SERIAL_BASE_BAUD  (TITAN_UART_CLK / 16)
+#define TITAN_SERIAL_IRQ        4
+#define TITAN_SERIAL_BASE       0xfd000008UL
+
+static void __init py_map_ocd(void)
+{
+        ocd_base = (unsigned long) ioremap(OCD_BASE, OCD_SIZE);
+        if (!ocd_base)
+                panic("Mapping OCD failed - game over.  Your score is 0.");
+
+        /* Kludge for PMON bug ... */
+        OCD_WRITE(0x0710, 0x0ffff029);
+}
+
+static void __init py_uart_setup(void)
+{
+#ifdef CONFIG_SERIAL_8250
+        struct uart_port up;
+
+        /*
+         * Register to interrupt zero because we share the interrupt with
+         * the serial driver which we don't properly support yet.
+         */
+        memset(&up, 0, sizeof(up));
+        up.membase      = (unsigned char *) ioremap(TITAN_SERIAL_BASE, 8);
+        up.irq          = TITAN_SERIAL_IRQ;
+        up.uartclk      = TITAN_UART_CLK;
+        up.regshift     = 0;
+        up.iotype       = UPIO_MEM;
+        up.flags        = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
+        up.line         = 0;
+
+        if (early_serial_setup(&up))
+                printk(KERN_ERR "Early serial init of port 0 failed\n");
+#endif /* CONFIG_SERIAL_8250 */
+}
+
+static void __init py_rtc_setup(void)
+{
+        m48t37_base = ioremap(YOSEMITE_RTC_BASE, YOSEMITE_RTC_SIZE);
+        if (!m48t37_base)
+                printk(KERN_ERR "Mapping the RTC failed\n");
+}
+
+/* Not only time init but that's what the hook it's called through is named */
+static void __init py_late_time_init(void)
+{
+        py_map_ocd();
+        py_uart_setup();
+        py_rtc_setup();
+}
+
+void __init plat_mem_setup(void)
+{
+        late_time_init = py_late_time_init;
+
+        /* Add memory regions */
+        add_memory_region(0x00000000, 0x10000000, BOOT_MEM_RAM);
+
+#if 0 /* XXX Crash ...  */
+        OCD_WRITE(RM9000x2_OCD_HTSC,
+                  OCD_READ(RM9000x2_OCD_HTSC) | HYPERTRANSPORT_ENABLE);
+
+        /* Set the BAR. Shifted mode */
+        OCD_WRITE(RM9000x2_OCD_HTBAR0, HYPERTRANSPORT_BAR0_ADDR);
+        OCD_WRITE(RM9000x2_OCD_HTMASK0, HYPERTRANSPORT_SIZE0);
+#endif
+}
diff --git a/arch/mips/pmc-sierra/yosemite/setup.h b/arch/mips/pmc-sierra/yosemite/setup.h
new file mode 100644
index 00000000000..1a01abfc7d3
--- /dev/null
+++ b/arch/mips/pmc-sierra/yosemite/setup.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2003, 04 PMC-Sierra
+ * Author: Manish Lachwani (lachwani@pmc-sierra.com)
+ * Copyright 2004 Ralf Baechle <ralf@linux-mips.org>
+ *
+ * Board specific definititions for the PMC-Sierra Yosemite
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+#ifndef __SETUP_H__
+#define __SETUP_H__
+
+/* M48T37 RTC + NVRAM */
+#define YOSEMITE_RTC_BASE               0xfc800000
+#define YOSEMITE_RTC_SIZE               0x00800000
+
+#define HYPERTRANSPORT_BAR0_ADDR        0x00000006
+#define HYPERTRANSPORT_SIZE0            0x0fffffff
+#define HYPERTRANSPORT_BAR0_ATTR        0x00002000
+
+#define HYPERTRANSPORT_ENABLE           0x6
+
+/*
+ * EEPROM Size
+ */
+#define TITAN_ATMEL_24C32_SIZE          32768
+#define TITAN_ATMEL_24C64_SIZE          65536
+
+#endif /* __SETUP_H__ */
diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c
new file mode 100644
index 00000000000..2608752898c
--- /dev/null
+++ b/arch/mips/pmc-sierra/yosemite/smp.c
@@ -0,0 +1,185 @@
+#include <linux/linkage.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+
+#include <asm/pmon.h>
+#include <asm/titan_dep.h>
+#include <asm/time.h>
+
+#define LAUNCHSTACK_SIZE 256
+
+static __cpuinitdata arch_spinlock_t launch_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+
+static unsigned long secondary_sp __cpuinitdata;
+static unsigned long secondary_gp __cpuinitdata;
+
+static unsigned char launchstack[LAUNCHSTACK_SIZE] __initdata
+        __attribute__((aligned(2 * sizeof(long))));
+
+static void __init prom_smp_bootstrap(void)
+{
+        local_irq_disable();
+
+        while (arch_spin_is_locked(&launch_lock));
+
+        __asm__ __volatile__(
+        "       move    $sp, %0         \n"
+        "       move    $gp, %1         \n"
+        "       j       smp_bootstrap   \n"
+        :
+        : "r" (secondary_sp), "r" (secondary_gp));
+}
+
+/*
+ * PMON is a fragile beast.  It'll blow up once the mappings it's littering
+ * right into the middle of KSEG3 are blown away so we have to grab the slave
+ * core early and keep it in a waiting loop.
+ */
+void __init prom_grab_secondary(void)
+{
+        arch_spin_lock(&launch_lock);
+
+        pmon_cpustart(1, &prom_smp_bootstrap,
+                      launchstack + LAUNCHSTACK_SIZE, 0);
+}
+
+void titan_mailbox_irq(void)
+{
+        int cpu = smp_processor_id();
+        unsigned long status;
+
+        switch (cpu) {
+        case 0:
+                status = OCD_READ(RM9000x2_OCD_INTP0STATUS3);
+                OCD_WRITE(RM9000x2_OCD_INTP0CLEAR3, status);
+
+                if (status & 0x2)
+                        smp_call_function_interrupt();
+                if (status & 0x4)
+                        scheduler_ipi();
+                break;
+
+        case 1:
+                status = OCD_READ(RM9000x2_OCD_INTP1STATUS3);
+                OCD_WRITE(RM9000x2_OCD_INTP1CLEAR3, status);
+
+                if (status & 0x2)
+                        smp_call_function_interrupt();
+                if (status & 0x4)
+                        scheduler_ipi();
+                break;
+        }
+}
+
+/*
+ * Send inter-processor interrupt
+ */
+static void yos_send_ipi_single(int cpu, unsigned int action)
+{
+        /*
+         * Generate an INTMSG so that it can be sent over to the
+         * destination CPU. The INTMSG will put the STATUS bits
+         * based on the action desired. An alternative strategy
+         * is to write to the Interrupt Set register, read the
+         * Interrupt Status register and clear the Interrupt
+         * Clear register. The latter is preffered.
+         */
+        switch (action) {
+        case SMP_RESCHEDULE_YOURSELF:
+                if (cpu == 1)
+                        OCD_WRITE(RM9000x2_OCD_INTP1SET3, 4);
+                else
+                        OCD_WRITE(RM9000x2_OCD_INTP0SET3, 4);
+                break;
+
+        case SMP_CALL_FUNCTION:
+                if (cpu == 1)
+                        OCD_WRITE(RM9000x2_OCD_INTP1SET3, 2);
+                else
+                        OCD_WRITE(RM9000x2_OCD_INTP0SET3, 2);
+                break;
+        }
+}
+
+static void yos_send_ipi_mask(const struct cpumask *mask, unsigned int action)
+{
+        unsigned int i;
+
+        for_each_cpu(i, mask)
+                yos_send_ipi_single(i, action);
+}
+
+/*
+ *  After we've done initial boot, this function is called to allow the
+ *  board code to clean up state, if needed
+ */
+static void __cpuinit yos_init_secondary(void)
+{
+        set_c0_status(ST0_CO | ST0_IE | ST0_IM);
+}
+
+static void __cpuinit yos_smp_finish(void)
+{
+}
+
+/* Hook for after all CPUs are online */
+static void yos_cpus_done(void)
+{
+}
+
+/*
+ * Firmware CPU startup hook
+ * Complicated by PMON's weird interface which tries to minimic the UNIX fork.
+ * It launches the next * available CPU and copies some information on the
+ * stack so the first thing we do is throw away that stuff and load useful
+ * values into the registers ...
+ */
+static void __cpuinit yos_boot_secondary(int cpu, struct task_struct *idle)
+{
+        unsigned long gp = (unsigned long) task_thread_info(idle);
+        unsigned long sp = __KSTK_TOS(idle);
+
+        secondary_sp = sp;
+        secondary_gp = gp;
+
+        arch_spin_unlock(&launch_lock);
+}
+
+/*
+ * Detect available CPUs, populate cpu_possible_map before smp_init
+ *
+ * We don't want to start the secondary CPU yet nor do we have a nice probing
+ * feature in PMON so we just assume presence of the secondary core.
+ */
+static void __init yos_smp_setup(void)
+{
+        int i;
+
+        cpus_clear(cpu_possible_map);
+
+        for (i = 0; i < 2; i++) {
+                cpu_set(i, cpu_possible_map);
+                __cpu_number_map[i]     = i;
+                __cpu_logical_map[i]    = i;
+        }
+}
+
+static void __init yos_prepare_cpus(unsigned int max_cpus)
+{
+        /*
+         * Be paranoid.  Enable the IPI only if we're really about to go SMP.
+         */
+        if (cpus_weight(cpu_possible_map))
+                set_c0_status(STATUSF_IP5);
+}
+
+struct plat_smp_ops yos_smp_ops = {
+        .send_ipi_single        = yos_send_ipi_single,
+        .send_ipi_mask          = yos_send_ipi_mask,
+        .init_secondary         = yos_init_secondary,
+        .smp_finish             = yos_smp_finish,
+        .cpus_done              = yos_cpus_done,
+        .boot_secondary         = yos_boot_secondary,
+        .smp_setup              = yos_smp_setup,
+        .prepare_cpus           = yos_prepare_cpus,
+};
diff --git a/arch/mips/powertv/asic/Kconfig b/arch/mips/powertv/asic/Kconfig
new file mode 100644
index 00000000000..2016bfe94d6
--- /dev/null
+++ b/arch/mips/powertv/asic/Kconfig
@@ -0,0 +1,28 @@
+config MIN_RUNTIME_RESOURCES
+        bool "Support for minimum runtime resources"
+        default n
+        depends on POWERTV
+        help
+          Enables support for minimizing the number of (SA asic) runtime
+          resources that are preallocated by the kernel.
+
+config MIN_RUNTIME_DOCSIS
+        bool "Support for minimum DOCSIS resource"
+        default y
+        depends on MIN_RUNTIME_RESOURCES
+        help
+          Enables support for the preallocated DOCSIS resource.
+
+config MIN_RUNTIME_PMEM
+        bool "Support for minimum PMEM resource"
+        default y
+        depends on MIN_RUNTIME_RESOURCES
+        help
+          Enables support for the preallocated Memory resource.
+
+config MIN_RUNTIME_TFTP
+        bool "Support for minimum TFTP resource"
+        default y
+        depends on MIN_RUNTIME_RESOURCES
+        help
+          Enables support for the preallocated TFTP resource.