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authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
commit8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch)
treea8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /arch/arm/mach-sa1100/include/mach
parent406089d01562f1e2bf9f089fd7637009ebaad589 (diff)
Patched in Tegra support.
Diffstat (limited to 'arch/arm/mach-sa1100/include/mach')
-rw-r--r--arch/arm/mach-sa1100/include/mach/SA-1100.h245
-rw-r--r--arch/arm/mach-sa1100/include/mach/assabet.h15
-rw-r--r--arch/arm/mach-sa1100/include/mach/cerf.h15
-rw-r--r--arch/arm/mach-sa1100/include/mach/collie.h3
-rw-r--r--arch/arm/mach-sa1100/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-sa1100/include/mach/entry-macro.S6
-rw-r--r--arch/arm/mach-sa1100/include/mach/gpio.h8
-rw-r--r--arch/arm/mach-sa1100/include/mach/hardware.h6
-rw-r--r--arch/arm/mach-sa1100/include/mach/irqs.h27
-rw-r--r--arch/arm/mach-sa1100/include/mach/nanoengine.h12
-rw-r--r--arch/arm/mach-sa1100/include/mach/neponset.h52
-rw-r--r--arch/arm/mach-sa1100/include/mach/shannon.h14
-rw-r--r--arch/arm/mach-sa1100/include/mach/simpad.h106
-rw-r--r--arch/arm/mach-sa1100/include/mach/uncompress.h2
14 files changed, 377 insertions, 136 deletions
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index 0ac6cc08a19..bae8296f5db 100644
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -830,14 +830,14 @@
830 * (read/write). 830 * (read/write).
831 */ 831 */
832 832
833#define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */ 833#define OSMR0 __REG(0x90000000) /* OS timer Match Reg. 0 */
834#define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */ 834#define OSMR1 __REG(0x90000004) /* OS timer Match Reg. 1 */
835#define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */ 835#define OSMR2 __REG(0x90000008) /* OS timer Match Reg. 2 */
836#define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */ 836#define OSMR3 __REG(0x9000000c) /* OS timer Match Reg. 3 */
837#define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */ 837#define OSCR __REG(0x90000010) /* OS timer Counter Reg. */
838#define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */ 838#define OSSR __REG(0x90000014 ) /* OS timer Status Reg. */
839#define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */ 839#define OWER __REG(0x90000018 ) /* OS timer Watch-dog Enable Reg. */
840#define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */ 840#define OIER __REG(0x9000001C ) /* OS timer Interrupt Enable Reg. */
841 841
842#define OSSR_M(Nb) /* Match detected [0..3] */ \ 842#define OSSR_M(Nb) /* Match detected [0..3] */ \
843 (0x00000001 << (Nb)) 843 (0x00000001 << (Nb))
@@ -1590,9 +1590,224 @@
1590 1590
1591/* 1591/*
1592 * Direct Memory Access (DMA) control registers 1592 * Direct Memory Access (DMA) control registers
1593 *
1594 * Registers
1595 * DDAR0 Direct Memory Access (DMA) Device Address Register
1596 * channel 0 (read/write).
1597 * DCSR0 Direct Memory Access (DMA) Control and Status
1598 * Register channel 0 (read/write).
1599 * DBSA0 Direct Memory Access (DMA) Buffer Start address
1600 * register A channel 0 (read/write).
1601 * DBTA0 Direct Memory Access (DMA) Buffer Transfer count
1602 * register A channel 0 (read/write).
1603 * DBSB0 Direct Memory Access (DMA) Buffer Start address
1604 * register B channel 0 (read/write).
1605 * DBTB0 Direct Memory Access (DMA) Buffer Transfer count
1606 * register B channel 0 (read/write).
1607 *
1608 * DDAR1 Direct Memory Access (DMA) Device Address Register
1609 * channel 1 (read/write).
1610 * DCSR1 Direct Memory Access (DMA) Control and Status
1611 * Register channel 1 (read/write).
1612 * DBSA1 Direct Memory Access (DMA) Buffer Start address
1613 * register A channel 1 (read/write).
1614 * DBTA1 Direct Memory Access (DMA) Buffer Transfer count
1615 * register A channel 1 (read/write).
1616 * DBSB1 Direct Memory Access (DMA) Buffer Start address
1617 * register B channel 1 (read/write).
1618 * DBTB1 Direct Memory Access (DMA) Buffer Transfer count
1619 * register B channel 1 (read/write).
1620 *
1621 * DDAR2 Direct Memory Access (DMA) Device Address Register
1622 * channel 2 (read/write).
1623 * DCSR2 Direct Memory Access (DMA) Control and Status
1624 * Register channel 2 (read/write).
1625 * DBSA2 Direct Memory Access (DMA) Buffer Start address
1626 * register A channel 2 (read/write).
1627 * DBTA2 Direct Memory Access (DMA) Buffer Transfer count
1628 * register A channel 2 (read/write).
1629 * DBSB2 Direct Memory Access (DMA) Buffer Start address
1630 * register B channel 2 (read/write).
1631 * DBTB2 Direct Memory Access (DMA) Buffer Transfer count
1632 * register B channel 2 (read/write).
1633 *
1634 * DDAR3 Direct Memory Access (DMA) Device Address Register
1635 * channel 3 (read/write).
1636 * DCSR3 Direct Memory Access (DMA) Control and Status
1637 * Register channel 3 (read/write).
1638 * DBSA3 Direct Memory Access (DMA) Buffer Start address
1639 * register A channel 3 (read/write).
1640 * DBTA3 Direct Memory Access (DMA) Buffer Transfer count
1641 * register A channel 3 (read/write).
1642 * DBSB3 Direct Memory Access (DMA) Buffer Start address
1643 * register B channel 3 (read/write).
1644 * DBTB3 Direct Memory Access (DMA) Buffer Transfer count
1645 * register B channel 3 (read/write).
1646 *
1647 * DDAR4 Direct Memory Access (DMA) Device Address Register
1648 * channel 4 (read/write).
1649 * DCSR4 Direct Memory Access (DMA) Control and Status
1650 * Register channel 4 (read/write).
1651 * DBSA4 Direct Memory Access (DMA) Buffer Start address
1652 * register A channel 4 (read/write).
1653 * DBTA4 Direct Memory Access (DMA) Buffer Transfer count
1654 * register A channel 4 (read/write).
1655 * DBSB4 Direct Memory Access (DMA) Buffer Start address
1656 * register B channel 4 (read/write).
1657 * DBTB4 Direct Memory Access (DMA) Buffer Transfer count
1658 * register B channel 4 (read/write).
1659 *
1660 * DDAR5 Direct Memory Access (DMA) Device Address Register
1661 * channel 5 (read/write).
1662 * DCSR5 Direct Memory Access (DMA) Control and Status
1663 * Register channel 5 (read/write).
1664 * DBSA5 Direct Memory Access (DMA) Buffer Start address
1665 * register A channel 5 (read/write).
1666 * DBTA5 Direct Memory Access (DMA) Buffer Transfer count
1667 * register A channel 5 (read/write).
1668 * DBSB5 Direct Memory Access (DMA) Buffer Start address
1669 * register B channel 5 (read/write).
1670 * DBTB5 Direct Memory Access (DMA) Buffer Transfer count
1671 * register B channel 5 (read/write).
1593 */ 1672 */
1594#define DMA_SIZE (6 * 0x20) 1673
1595#define DMA_PHYS 0xb0000000 1674#define DMASp 0x00000020 /* DMA control reg. Space [byte] */
1675
1676#define DDAR(Nb) __REG(0xB0000000 + (Nb)*DMASp) /* DMA Device Address Reg. channel [0..5] */
1677#define SetDCSR(Nb) __REG(0xB0000004 + (Nb)*DMASp) /* Set DMA Control & Status Reg. channel [0..5] (write) */
1678#define ClrDCSR(Nb) __REG(0xB0000008 + (Nb)*DMASp) /* Clear DMA Control & Status Reg. channel [0..5] (write) */
1679#define RdDCSR(Nb) __REG(0xB000000C + (Nb)*DMASp) /* Read DMA Control & Status Reg. channel [0..5] (read) */
1680#define DBSA(Nb) __REG(0xB0000010 + (Nb)*DMASp) /* DMA Buffer Start address reg. A channel [0..5] */
1681#define DBTA(Nb) __REG(0xB0000014 + (Nb)*DMASp) /* DMA Buffer Transfer count reg. A channel [0..5] */
1682#define DBSB(Nb) __REG(0xB0000018 + (Nb)*DMASp) /* DMA Buffer Start address reg. B channel [0..5] */
1683#define DBTB(Nb) __REG(0xB000001C + (Nb)*DMASp) /* DMA Buffer Transfer count reg. B channel [0..5] */
1684
1685#define DDAR_RW 0x00000001 /* device data Read/Write */
1686#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */
1687 /* (memory -> device) */
1688#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */
1689 /* (device -> memory) */
1690#define DDAR_E 0x00000002 /* big/little Endian device */
1691#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */
1692#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */
1693#define DDAR_BS 0x00000004 /* device Burst Size */
1694#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */
1695#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */
1696#define DDAR_DW 0x00000008 /* device Data Width */
1697#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */
1698#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */
1699#define DDAR_DS Fld (4, 4) /* Device Select */
1700#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \
1701 (0x0 << FShft (DDAR_DS))
1702#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \
1703 (0x1 << FShft (DDAR_DS))
1704#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \
1705 (0x2 << FShft (DDAR_DS))
1706#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \
1707 (0x3 << FShft (DDAR_DS))
1708#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \
1709 (0x4 << FShft (DDAR_DS))
1710#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \
1711 (0x5 << FShft (DDAR_DS))
1712#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \
1713 (0x6 << FShft (DDAR_DS))
1714#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \
1715 (0x7 << FShft (DDAR_DS))
1716#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \
1717 (0x8 << FShft (DDAR_DS))
1718#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \
1719 (0x9 << FShft (DDAR_DS))
1720#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \
1721 /* (audio) */ \
1722 (0xA << FShft (DDAR_DS))
1723#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \
1724 /* (audio) */ \
1725 (0xB << FShft (DDAR_DS))
1726#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \
1727 /* (telecom) */ \
1728 (0xC << FShft (DDAR_DS))
1729#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \
1730 /* (telecom) */ \
1731 (0xD << FShft (DDAR_DS))
1732#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \
1733 (0xE << FShft (DDAR_DS))
1734#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \
1735 (0xF << FShft (DDAR_DS))
1736#define DDAR_DA Fld (24, 8) /* Device Address */
1737#define DDAR_DevAdd(Add) /* Device Address */ \
1738 (((Add) & 0xF0000000) | \
1739 (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
1740#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \
1741 (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
1742 DDAR_Ser0UDCTr + DDAR_DevAdd (__PREG(Ser0UDCDR)))
1743#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \
1744 (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
1745 DDAR_Ser0UDCRc + DDAR_DevAdd (__PREG(Ser0UDCDR)))
1746#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \
1747 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1748 DDAR_Ser1UARTTr + DDAR_DevAdd (__PREG(Ser1UTDR)))
1749#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \
1750 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1751 DDAR_Ser1UARTRc + DDAR_DevAdd (__PREG(Ser1UTDR)))
1752#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \
1753 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1754 DDAR_Ser1SDLCTr + DDAR_DevAdd (__PREG(Ser1SDDR)))
1755#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \
1756 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1757 DDAR_Ser1SDLCRc + DDAR_DevAdd (__PREG(Ser1SDDR)))
1758#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \
1759 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1760 DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2UTDR)))
1761#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \
1762 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1763 DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2UTDR)))
1764#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \
1765 (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
1766 DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2HSDR)))
1767#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \
1768 (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
1769 DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2HSDR)))
1770#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \
1771 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1772 DDAR_Ser3UARTTr + DDAR_DevAdd (__PREG(Ser3UTDR)))
1773#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \
1774 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1775 DDAR_Ser3UARTRc + DDAR_DevAdd (__PREG(Ser3UTDR)))
1776#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \
1777 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
1778 DDAR_Ser4MCP0Tr + DDAR_DevAdd (__PREG(Ser4MCDR0)))
1779#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \
1780 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
1781 DDAR_Ser4MCP0Rc + DDAR_DevAdd (__PREG(Ser4MCDR0)))
1782#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \
1783 /* (telecom) */ \
1784 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
1785 DDAR_Ser4MCP1Tr + DDAR_DevAdd (__PREG(Ser4MCDR1)))
1786#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \
1787 /* (telecom) */ \
1788 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
1789 DDAR_Ser4MCP1Rc + DDAR_DevAdd (__PREG(Ser4MCDR1)))
1790#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \
1791 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
1792 DDAR_Ser4SSPTr + DDAR_DevAdd (__PREG(Ser4SSDR)))
1793#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \
1794 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
1795 DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR)))
1796
1797#define DCSR_RUN 0x00000001 /* DMA running */
1798#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */
1799#define DCSR_ERROR 0x00000004 /* DMA ERROR */
1800#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */
1801#define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */
1802#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */
1803#define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */
1804#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */
1805#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */
1806#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */
1807
1808#define DBT_TC Fld (13, 0) /* Transfer Count */
1809#define DBTA_TCA DBT_TC /* Transfer Count buffer A */
1810#define DBTB_TCB DBT_TC /* Transfer Count buffer B */
1596 1811
1597 1812
1598/* 1813/*
@@ -1688,6 +1903,16 @@
1688#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ 1903#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
1689 /* (Alternative) */ 1904 /* (Alternative) */
1690 1905
1906#define LCCR0 __REG(0xB0100000) /* LCD Control Reg. 0 */
1907#define LCSR __REG(0xB0100004) /* LCD Status Reg. */
1908#define DBAR1 __REG(0xB0100010) /* LCD DMA Base Address Reg. channel 1 */
1909#define DCAR1 __REG(0xB0100014) /* LCD DMA Current Address Reg. channel 1 */
1910#define DBAR2 __REG(0xB0100018) /* LCD DMA Base Address Reg. channel 2 */
1911#define DCAR2 __REG(0xB010001C) /* LCD DMA Current Address Reg. channel 2 */
1912#define LCCR1 __REG(0xB0100020) /* LCD Control Reg. 1 */
1913#define LCCR2 __REG(0xB0100024) /* LCD Control Reg. 2 */
1914#define LCCR3 __REG(0xB0100028) /* LCD Control Reg. 3 */
1915
1691#define LCCR0_LEN 0x00000001 /* LCD ENable */ 1916#define LCCR0_LEN 0x00000001 /* LCD ENable */
1692#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ 1917#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
1693#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ 1918#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h
index 307391488c2..28c2cf50c25 100644
--- a/arch/arm/mach-sa1100/include/mach/assabet.h
+++ b/arch/arm/mach-sa1100/include/mach/assabet.h
@@ -85,18 +85,21 @@ extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
85#define ASSABET_BSR_RAD_RI (1 << 31) 85#define ASSABET_BSR_RAD_RI (1 << 31)
86 86
87 87
88/* GPIOs (bitmasks) for which the generic definition doesn't say much */ 88/* GPIOs for which the generic definition doesn't say much */
89#define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */ 89#define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */
90#define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */ 90#define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */
91#define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */ 91#define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */
92#define ASSABET_GPIO_CF_IRQ GPIO_GPIO (21) /* CF IRQ */
93#define ASSABET_GPIO_CF_CD GPIO_GPIO (22) /* CF CD */
94#define ASSABET_GPIO_CF_BVD2 GPIO_GPIO (24) /* CF BVD */
92#define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */ 95#define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */
96#define ASSABET_GPIO_CF_BVD1 GPIO_GPIO (25) /* CF BVD */
93#define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */ 97#define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */
94#define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */ 98#define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */
95 99
96/* These are gpiolib GPIO numbers, not bitmasks */ 100#define ASSABET_IRQ_GPIO_CF_IRQ IRQ_GPIO21
97#define ASSABET_GPIO_CF_IRQ 21 /* CF IRQ */ 101#define ASSABET_IRQ_GPIO_CF_CD IRQ_GPIO22
98#define ASSABET_GPIO_CF_CD 22 /* CF CD */ 102#define ASSABET_IRQ_GPIO_CF_BVD2 IRQ_GPIO24
99#define ASSABET_GPIO_CF_BVD2 24 /* CF BVD / IOSPKR */ 103#define ASSABET_IRQ_GPIO_CF_BVD1 IRQ_GPIO25
100#define ASSABET_GPIO_CF_BVD1 25 /* CF BVD / IOSTSCHG */
101 104
102#endif 105#endif
diff --git a/arch/arm/mach-sa1100/include/mach/cerf.h b/arch/arm/mach-sa1100/include/mach/cerf.h
index 88fd9c006ce..c3ac3d0f946 100644
--- a/arch/arm/mach-sa1100/include/mach/cerf.h
+++ b/arch/arm/mach-sa1100/include/mach/cerf.h
@@ -14,10 +14,15 @@
14#define CERF_ETH_IO 0xf0000000 14#define CERF_ETH_IO 0xf0000000
15#define CERF_ETH_IRQ IRQ_GPIO26 15#define CERF_ETH_IRQ IRQ_GPIO26
16 16
17#define CERF_GPIO_CF_BVD2 19 17#define CERF_GPIO_CF_BVD2 GPIO_GPIO (19)
18#define CERF_GPIO_CF_BVD1 20 18#define CERF_GPIO_CF_BVD1 GPIO_GPIO (20)
19#define CERF_GPIO_CF_RESET 21 19#define CERF_GPIO_CF_RESET GPIO_GPIO (21)
20#define CERF_GPIO_CF_IRQ 22 20#define CERF_GPIO_CF_IRQ GPIO_GPIO (22)
21#define CERF_GPIO_CF_CD 23 21#define CERF_GPIO_CF_CD GPIO_GPIO (23)
22
23#define CERF_IRQ_GPIO_CF_BVD2 IRQ_GPIO19
24#define CERF_IRQ_GPIO_CF_BVD1 IRQ_GPIO20
25#define CERF_IRQ_GPIO_CF_IRQ IRQ_GPIO22
26#define CERF_IRQ_GPIO_CF_CD IRQ_GPIO23
22 27
23#endif // _INCLUDE_CERF_H_ 28#endif // _INCLUDE_CERF_H_
diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h
index f33679d2d3e..52acda7061b 100644
--- a/arch/arm/mach-sa1100/include/mach/collie.h
+++ b/arch/arm/mach-sa1100/include/mach/collie.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/mach-sa1100/include/mach/collie.h 2 * arch/arm/mach-sa1100/include/mach/collie.h
3 * 3 *
4 * This file contains the hardware specific definitions for Collie 4 * This file contains the hardware specific definitions for Assabet
5 * Only include this file from SA1100-specific files. 5 * Only include this file from SA1100-specific files.
6 * 6 *
7 * ChangeLog: 7 * ChangeLog:
@@ -13,7 +13,6 @@
13#ifndef __ASM_ARCH_COLLIE_H 13#ifndef __ASM_ARCH_COLLIE_H
14#define __ASM_ARCH_COLLIE_H 14#define __ASM_ARCH_COLLIE_H
15 15
16extern void locomolcd_power(int on);
17 16
18#define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1) 17#define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1)
19#define COLLIE_GPIO_CHARGE_ON (COLLIE_SCOOP_GPIO_BASE + 0) 18#define COLLIE_GPIO_CHARGE_ON (COLLIE_SCOOP_GPIO_BASE + 0)
diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/mach-sa1100/include/mach/debug-macro.S
index 530772d937a..0cd0fc9635b 100644
--- a/arch/arm/mach-sa1100/include/mach/debug-macro.S
+++ b/arch/arm/mach-sa1100/include/mach/debug-macro.S
@@ -12,7 +12,7 @@
12*/ 12*/
13#include <mach/hardware.h> 13#include <mach/hardware.h>
14 14
15 .macro addruart, rp, rv, tmp 15 .macro addruart, rp, rv
16 mrc p15, 0, \rp, c1, c0 16 mrc p15, 0, \rp, c1, c0
17 tst \rp, #1 @ MMU enabled? 17 tst \rp, #1 @ MMU enabled?
18 moveq \rp, #0x80000000 @ physical base address 18 moveq \rp, #0x80000000 @ physical base address
diff --git a/arch/arm/mach-sa1100/include/mach/entry-macro.S b/arch/arm/mach-sa1100/include/mach/entry-macro.S
index 8cf7630bf02..6aa13c46c5d 100644
--- a/arch/arm/mach-sa1100/include/mach/entry-macro.S
+++ b/arch/arm/mach-sa1100/include/mach/entry-macro.S
@@ -8,11 +8,17 @@
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10 10
11 .macro disable_fiq
12 .endm
13
11 .macro get_irqnr_preamble, base, tmp 14 .macro get_irqnr_preamble, base, tmp
12 mov \base, #0xfa000000 @ ICIP = 0xfa050000 15 mov \base, #0xfa000000 @ ICIP = 0xfa050000
13 add \base, \base, #0x00050000 16 add \base, \base, #0x00050000
14 .endm 17 .endm
15 18
19 .macro arch_ret_to_user, tmp1, tmp2
20 .endm
21
16 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
17 ldr \irqstat, [\base] @ get irqs 23 ldr \irqstat, [\base] @ get irqs
18 ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004 24 ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004
diff --git a/arch/arm/mach-sa1100/include/mach/gpio.h b/arch/arm/mach-sa1100/include/mach/gpio.h
index 6a9eecf3137..7befc104e9a 100644
--- a/arch/arm/mach-sa1100/include/mach/gpio.h
+++ b/arch/arm/mach-sa1100/include/mach/gpio.h
@@ -24,13 +24,10 @@
24#ifndef __ASM_ARCH_SA1100_GPIO_H 24#ifndef __ASM_ARCH_SA1100_GPIO_H
25#define __ASM_ARCH_SA1100_GPIO_H 25#define __ASM_ARCH_SA1100_GPIO_H
26 26
27#include <linux/io.h>
28#include <mach/hardware.h> 27#include <mach/hardware.h>
29#include <asm/irq.h> 28#include <asm/irq.h>
30#include <asm-generic/gpio.h> 29#include <asm-generic/gpio.h>
31 30
32#define __ARM_GPIOLIB_COMPLEX
33
34static inline int gpio_get_value(unsigned gpio) 31static inline int gpio_get_value(unsigned gpio)
35{ 32{
36 if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) 33 if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
@@ -52,4 +49,9 @@ static inline void gpio_set_value(unsigned gpio, int value)
52 49
53#define gpio_cansleep __gpio_cansleep 50#define gpio_cansleep __gpio_cansleep
54 51
52#define gpio_to_irq(gpio) ((gpio < 11) ? (IRQ_GPIO0 + gpio) : \
53 (IRQ_GPIO11 - 11 + gpio))
54#define irq_to_gpio(irq) ((irq < IRQ_GPIO11_27) ? (irq - IRQ_GPIO0) : \
55 (irq - IRQ_GPIO11 + 11))
56
55#endif 57#endif
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index cbedd75a9d6..99f5856d8de 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -32,7 +32,7 @@
32#define PIO_START 0x80000000 /* physical start of IO space */ 32#define PIO_START 0x80000000 /* physical start of IO space */
33 33
34#define io_p2v( x ) \ 34#define io_p2v( x ) \
35 IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE ) 35 ( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
36#define io_v2p( x ) \ 36#define io_v2p( x ) \
37 ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START ) 37 ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
38 38
@@ -47,8 +47,6 @@
47#define CPU_SA1110_ID (0x6901b110) 47#define CPU_SA1110_ID (0x6901b110)
48#define CPU_SA1110_MASK (0xfffffff0) 48#define CPU_SA1110_MASK (0xfffffff0)
49 49
50#define __MREG(x) IOMEM(io_p2v(x))
51
52#ifndef __ASSEMBLY__ 50#ifndef __ASSEMBLY__
53 51
54#include <asm/cputype.h> 52#include <asm/cputype.h>
@@ -58,7 +56,7 @@
58#define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID) 56#define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID)
59#define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID) 57#define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID)
60 58
61# define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x))) 59# define __REG(x) (*((volatile unsigned long *)io_p2v(x)))
62# define __PREG(x) (io_v2p((unsigned long)&(x))) 60# define __PREG(x) (io_v2p((unsigned long)&(x)))
63 61
64static inline unsigned long get_clock_tick_rate(void) 62static inline unsigned long get_clock_tick_rate(void)
diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h
index 3790298b714..d18f21abef8 100644
--- a/arch/arm/mach-sa1100/include/mach/irqs.h
+++ b/arch/arm/mach-sa1100/include/mach/irqs.h
@@ -71,19 +71,22 @@
71/* 71/*
72 * Figure out the MAX IRQ number. 72 * Figure out the MAX IRQ number.
73 * 73 *
74 * Neponset, SA1111 and UCB1x00 are sparse IRQ aware, so can dynamically 74 * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
75 * allocate their IRQs above NR_IRQS. 75 * If we have an LoCoMo, the max IRQ is IRQ_BOARD_START + 4
76 * 76 * Otherwise, we have the standard IRQs only.
77 * LoCoMo has 4 additional IRQs, but is not sparse IRQ aware, and so has
78 * to be included in the NR_IRQS calculation.
79 */ 77 */
80#ifdef CONFIG_SHARP_LOCOMO 78#ifdef CONFIG_SA1111
81#define NR_IRQS_LOCOMO 4 79#define NR_IRQS (IRQ_BOARD_END + 55)
80#elif defined(CONFIG_SHARP_LOCOMO)
81#define NR_IRQS (IRQ_BOARD_START + 4)
82#else 82#else
83#define NR_IRQS_LOCOMO 0 83#define NR_IRQS (IRQ_BOARD_START)
84#endif 84#endif
85 85
86#ifndef NR_IRQS 86/*
87#define NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO) 87 * Board specific IRQs. Define them here.
88#endif 88 * Do not surround them with ifdefs.
89#define SA1100_NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO) 89 */
90#define IRQ_NEPONSET_SMC9196 (IRQ_BOARD_START + 0)
91#define IRQ_NEPONSET_USAR (IRQ_BOARD_START + 1)
92#define IRQ_NEPONSET_SA1111 (IRQ_BOARD_START + 2)
diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h
index 5ebd469a31f..14f8382d066 100644
--- a/arch/arm/mach-sa1100/include/mach/nanoengine.h
+++ b/arch/arm/mach-sa1100/include/mach/nanoengine.h
@@ -16,12 +16,12 @@
16 16
17#include <mach/irqs.h> 17#include <mach/irqs.h>
18 18
19#define GPIO_PC_READY0 11 /* ready for socket 0 (active high)*/ 19#define GPIO_PC_READY0 GPIO_GPIO(11) /* ready for socket 0 (active high)*/
20#define GPIO_PC_READY1 12 /* ready for socket 1 (active high) */ 20#define GPIO_PC_READY1 GPIO_GPIO(12) /* ready for socket 1 (active high) */
21#define GPIO_PC_CD0 13 /* detect for socket 0 (active low) */ 21#define GPIO_PC_CD0 GPIO_GPIO(13) /* detect for socket 0 (active low) */
22#define GPIO_PC_CD1 14 /* detect for socket 1 (active low) */ 22#define GPIO_PC_CD1 GPIO_GPIO(14) /* detect for socket 1 (active low) */
23#define GPIO_PC_RESET0 15 /* reset socket 0 */ 23#define GPIO_PC_RESET0 GPIO_GPIO(15) /* reset socket 0 */
24#define GPIO_PC_RESET1 16 /* reset socket 1 */ 24#define GPIO_PC_RESET1 GPIO_GPIO(16) /* reset socket 1 */
25 25
26#define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0 26#define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0
27#define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11 27#define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11
diff --git a/arch/arm/mach-sa1100/include/mach/neponset.h b/arch/arm/mach-sa1100/include/mach/neponset.h
index 5516a52a329..ffe2bc45eed 100644
--- a/arch/arm/mach-sa1100/include/mach/neponset.h
+++ b/arch/arm/mach-sa1100/include/mach/neponset.h
@@ -15,6 +15,54 @@
15/* 15/*
16 * Neponset definitions: 16 * Neponset definitions:
17 */ 17 */
18
19#define NEPONSET_CPLD_BASE (0x10000000)
20#define Nep_p2v( x ) ((x) - NEPONSET_CPLD_BASE + 0xf3000000)
21#define Nep_v2p( x ) ((x) - 0xf3000000 + NEPONSET_CPLD_BASE)
22
23#define _IRR 0x10000024 /* Interrupt Reason Register */
24#define _AUD_CTL 0x100000c0 /* Audio controls (RW) */
25#define _MDM_CTL_0 0x100000b0 /* Modem control 0 (RW) */
26#define _MDM_CTL_1 0x100000b4 /* Modem control 1 (RW) */
27#define _NCR_0 0x100000a0 /* Control Register (RW) */
28#define _KP_X_OUT 0x10000090 /* Keypad row write (RW) */
29#define _KP_Y_IN 0x10000080 /* Keypad column read (RO) */
30#define _SWPK 0x10000020 /* Switch pack (RO) */
31#define _WHOAMI 0x10000000 /* System ID Register (RO) */
32
33#define _LEDS 0x10000010 /* LEDs [31:0] (WO) */
34
35#define IRR (*((volatile u_char *) Nep_p2v(_IRR)))
36#define AUD_CTL (*((volatile u_char *) Nep_p2v(_AUD_CTL)))
37#define MDM_CTL_0 (*((volatile u_char *) Nep_p2v(_MDM_CTL_0)))
38#define MDM_CTL_1 (*((volatile u_char *) Nep_p2v(_MDM_CTL_1)))
39#define NCR_0 (*((volatile u_char *) Nep_p2v(_NCR_0)))
40#define KP_X_OUT (*((volatile u_char *) Nep_p2v(_KP_X_OUT)))
41#define KP_Y_IN (*((volatile u_char *) Nep_p2v(_KP_Y_IN)))
42#define SWPK (*((volatile u_char *) Nep_p2v(_SWPK)))
43#define WHOAMI (*((volatile u_char *) Nep_p2v(_WHOAMI)))
44
45#define LEDS (*((volatile Word *) Nep_p2v(_LEDS)))
46
47#define IRR_ETHERNET (1<<0)
48#define IRR_USAR (1<<1)
49#define IRR_SA1111 (1<<2)
50
51#define AUD_SEL_1341 (1<<0)
52#define AUD_MUTE_1341 (1<<1)
53
54#define MDM_CTL0_RTS1 (1 << 0)
55#define MDM_CTL0_DTR1 (1 << 1)
56#define MDM_CTL0_RTS2 (1 << 2)
57#define MDM_CTL0_DTR2 (1 << 3)
58
59#define MDM_CTL1_CTS1 (1 << 0)
60#define MDM_CTL1_DSR1 (1 << 1)
61#define MDM_CTL1_DCD1 (1 << 2)
62#define MDM_CTL1_CTS2 (1 << 3)
63#define MDM_CTL1_DSR2 (1 << 4)
64#define MDM_CTL1_DCD2 (1 << 5)
65
18#define NCR_GP01_OFF (1<<0) 66#define NCR_GP01_OFF (1<<0)
19#define NCR_TP_PWR_EN (1<<1) 67#define NCR_TP_PWR_EN (1<<1)
20#define NCR_MS_PWR_EN (1<<2) 68#define NCR_MS_PWR_EN (1<<2)
@@ -23,8 +71,4 @@
23#define NCR_A0VPP (1<<5) 71#define NCR_A0VPP (1<<5)
24#define NCR_A1VPP (1<<6) 72#define NCR_A1VPP (1<<6)
25 73
26void neponset_ncr_frob(unsigned int, unsigned int);
27#define neponset_ncr_set(v) neponset_ncr_frob(0, v)
28#define neponset_ncr_clear(v) neponset_ncr_frob(v, 0)
29
30#endif 74#endif
diff --git a/arch/arm/mach-sa1100/include/mach/shannon.h b/arch/arm/mach-sa1100/include/mach/shannon.h
index fff39e02b49..ec27d6e1214 100644
--- a/arch/arm/mach-sa1100/include/mach/shannon.h
+++ b/arch/arm/mach-sa1100/include/mach/shannon.h
@@ -21,12 +21,16 @@
21#define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */ 21#define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */
22#define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */ 22#define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */
23#define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */ 23#define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */
24#define SHANNON_GPIO_DISP_EN 22 /* out */ 24#define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */
25/* XXX GPIO 23 unaccounted for */ 25/* XXX GPIO 23 unaccounted for */
26#define SHANNON_GPIO_EJECT_0 24 /* in */ 26#define SHANNON_GPIO_EJECT_0 GPIO_GPIO (24) /* in */
27#define SHANNON_GPIO_EJECT_1 25 /* in */ 27#define SHANNON_IRQ_GPIO_EJECT_0 IRQ_GPIO24
28#define SHANNON_GPIO_RDY_0 26 /* in */ 28#define SHANNON_GPIO_EJECT_1 GPIO_GPIO (25) /* in */
29#define SHANNON_GPIO_RDY_1 27 /* in */ 29#define SHANNON_IRQ_GPIO_EJECT_1 IRQ_GPIO25
30#define SHANNON_GPIO_RDY_0 GPIO_GPIO (26) /* in */
31#define SHANNON_IRQ_GPIO_RDY_0 IRQ_GPIO26
32#define SHANNON_GPIO_RDY_1 GPIO_GPIO (27) /* in */
33#define SHANNON_IRQ_GPIO_RDY_1 IRQ_GPIO27
30 34
31/* MCP UCB codec GPIO pins... */ 35/* MCP UCB codec GPIO pins... */
32 36
diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h
index ac2ea767215..9296c4513ce 100644
--- a/arch/arm/mach-sa1100/include/mach/simpad.h
+++ b/arch/arm/mach-sa1100/include/mach/simpad.h
@@ -39,87 +39,41 @@
39 39
40 40
41/*--- PCMCIA ---*/ 41/*--- PCMCIA ---*/
42#define GPIO_CF_CD 24 42#define GPIO_CF_CD GPIO_GPIO24
43#define GPIO_CF_IRQ 1 43#define GPIO_CF_IRQ GPIO_GPIO1
44#define IRQ_GPIO_CF_IRQ IRQ_GPIO1
45#define IRQ_GPIO_CF_CD IRQ_GPIO24
44 46
45/*--- SmartCard ---*/ 47/*--- SmartCard ---*/
46#define GPIO_SMART_CARD GPIO_GPIO10 48#define GPIO_SMART_CARD GPIO_GPIO10
47#define IRQ_GPIO_SMARD_CARD IRQ_GPIO10 49#define IRQ_GPIO_SMARD_CARD IRQ_GPIO10
48 50
49/*--- ucb1x00 GPIO ---*/ 51// CS3 Latch is write only, a shadow is necessary
50#define SIMPAD_UCB1X00_GPIO_BASE (GPIO_MAX + 1) 52
51#define SIMPAD_UCB1X00_GPIO_PROG1 (SIMPAD_UCB1X00_GPIO_BASE) 53#define CS3BUSTYPE unsigned volatile long
52#define SIMPAD_UCB1X00_GPIO_PROG2 (SIMPAD_UCB1X00_GPIO_BASE + 1) 54#define CS3_BASE 0xf1000000
53#define SIMPAD_UCB1X00_GPIO_UP (SIMPAD_UCB1X00_GPIO_BASE + 2) 55
54#define SIMPAD_UCB1X00_GPIO_DOWN (SIMPAD_UCB1X00_GPIO_BASE + 3) 56#define VCC_5V_EN 0x0001 // For 5V PCMCIA
55#define SIMPAD_UCB1X00_GPIO_LEFT (SIMPAD_UCB1X00_GPIO_BASE + 4) 57#define VCC_3V_EN 0x0002 // FOR 3.3V PCMCIA
56#define SIMPAD_UCB1X00_GPIO_RIGHT (SIMPAD_UCB1X00_GPIO_BASE + 5) 58#define EN1 0x0004 // This is only for EPROM's
57#define SIMPAD_UCB1X00_GPIO_6 (SIMPAD_UCB1X00_GPIO_BASE + 6) 59#define EN0 0x0008 // Both should be enable for 3.3V or 5V
58#define SIMPAD_UCB1X00_GPIO_7 (SIMPAD_UCB1X00_GPIO_BASE + 7) 60#define DISPLAY_ON 0x0010
59#define SIMPAD_UCB1X00_GPIO_HEADSET (SIMPAD_UCB1X00_GPIO_BASE + 8) 61#define PCMCIA_BUFF_DIS 0x0020
60#define SIMPAD_UCB1X00_GPIO_SPEAKER (SIMPAD_UCB1X00_GPIO_BASE + 9) 62#define MQ_RESET 0x0040
61 63#define PCMCIA_RESET 0x0080
62/*--- CS3 Latch ---*/ 64#define DECT_POWER_ON 0x0100
63#define SIMPAD_CS3_GPIO_BASE (GPIO_MAX + 11) 65#define IRDA_SD 0x0200 // Shutdown for powersave
64#define SIMPAD_CS3_VCC_5V_EN (SIMPAD_CS3_GPIO_BASE) 66#define RS232_ON 0x0400
65#define SIMPAD_CS3_VCC_3V_EN (SIMPAD_CS3_GPIO_BASE + 1) 67#define SD_MEDIAQ 0x0800 // Shutdown for powersave
66#define SIMPAD_CS3_EN1 (SIMPAD_CS3_GPIO_BASE + 2) 68#define LED2_ON 0x1000
67#define SIMPAD_CS3_EN0 (SIMPAD_CS3_GPIO_BASE + 3) 69#define IRDA_MODE 0x2000 // Fast/Slow IrDA mode
68#define SIMPAD_CS3_DISPLAY_ON (SIMPAD_CS3_GPIO_BASE + 4) 70#define ENABLE_5V 0x4000 // Enable 5V circuit
69#define SIMPAD_CS3_PCMCIA_BUFF_DIS (SIMPAD_CS3_GPIO_BASE + 5) 71#define RESET_SIMCARD 0x8000
70#define SIMPAD_CS3_MQ_RESET (SIMPAD_CS3_GPIO_BASE + 6) 72
71#define SIMPAD_CS3_PCMCIA_RESET (SIMPAD_CS3_GPIO_BASE + 7) 73#define RS232_ENABLE 0x0440
72#define SIMPAD_CS3_DECT_POWER_ON (SIMPAD_CS3_GPIO_BASE + 8) 74#define PCMCIAMASK 0x402f
73#define SIMPAD_CS3_IRDA_SD (SIMPAD_CS3_GPIO_BASE + 9) 75
74#define SIMPAD_CS3_RS232_ON (SIMPAD_CS3_GPIO_BASE + 10) 76
75#define SIMPAD_CS3_SD_MEDIAQ (SIMPAD_CS3_GPIO_BASE + 11)
76#define SIMPAD_CS3_LED2_ON (SIMPAD_CS3_GPIO_BASE + 12)
77#define SIMPAD_CS3_IRDA_MODE (SIMPAD_CS3_GPIO_BASE + 13)
78#define SIMPAD_CS3_ENABLE_5V (SIMPAD_CS3_GPIO_BASE + 14)
79#define SIMPAD_CS3_RESET_SIMCARD (SIMPAD_CS3_GPIO_BASE + 15)
80
81#define SIMPAD_CS3_PCMCIA_BVD1 (SIMPAD_CS3_GPIO_BASE + 16)
82#define SIMPAD_CS3_PCMCIA_BVD2 (SIMPAD_CS3_GPIO_BASE + 17)
83#define SIMPAD_CS3_PCMCIA_VS1 (SIMPAD_CS3_GPIO_BASE + 18)
84#define SIMPAD_CS3_PCMCIA_VS2 (SIMPAD_CS3_GPIO_BASE + 19)
85#define SIMPAD_CS3_LOCK_IND (SIMPAD_CS3_GPIO_BASE + 20)
86#define SIMPAD_CS3_CHARGING_STATE (SIMPAD_CS3_GPIO_BASE + 21)
87#define SIMPAD_CS3_PCMCIA_SHORT (SIMPAD_CS3_GPIO_BASE + 22)
88#define SIMPAD_CS3_GPIO_23 (SIMPAD_CS3_GPIO_BASE + 23)
89
90#define CS3_BASE IOMEM(0xf1000000)
91
92long simpad_get_cs3_ro(void);
93long simpad_get_cs3_shadow(void);
94void simpad_set_cs3_bit(int value);
95void simpad_clear_cs3_bit(int value);
96
97#define VCC_5V_EN 0x0001 /* For 5V PCMCIA */
98#define VCC_3V_EN 0x0002 /* FOR 3.3V PCMCIA */
99#define EN1 0x0004 /* This is only for EPROM's */
100#define EN0 0x0008 /* Both should be enable for 3.3V or 5V */
101#define DISPLAY_ON 0x0010
102#define PCMCIA_BUFF_DIS 0x0020
103#define MQ_RESET 0x0040
104#define PCMCIA_RESET 0x0080
105#define DECT_POWER_ON 0x0100
106#define IRDA_SD 0x0200 /* Shutdown for powersave */
107#define RS232_ON 0x0400
108#define SD_MEDIAQ 0x0800 /* Shutdown for powersave */
109#define LED2_ON 0x1000
110#define IRDA_MODE 0x2000 /* Fast/Slow IrDA mode */
111#define ENABLE_5V 0x4000 /* Enable 5V circuit */
112#define RESET_SIMCARD 0x8000
113
114#define PCMCIA_BVD1 0x01
115#define PCMCIA_BVD2 0x02
116#define PCMCIA_VS1 0x04
117#define PCMCIA_VS2 0x08
118#define LOCK_IND 0x10
119#define CHARGING_STATE 0x20
120#define PCMCIA_SHORT 0x40
121
122/*--- Battery ---*/
123struct simpad_battery { 77struct simpad_battery {
124 unsigned char ac_status; /* line connected yes/no */ 78 unsigned char ac_status; /* line connected yes/no */
125 unsigned char status; /* battery loading yes/no */ 79 unsigned char status; /* battery loading yes/no */
diff --git a/arch/arm/mach-sa1100/include/mach/uncompress.h b/arch/arm/mach-sa1100/include/mach/uncompress.h
index 5cf71da60e4..6cb39ddde65 100644
--- a/arch/arm/mach-sa1100/include/mach/uncompress.h
+++ b/arch/arm/mach-sa1100/include/mach/uncompress.h
@@ -8,8 +8,6 @@
8 8
9#include "hardware.h" 9#include "hardware.h"
10 10
11#define IOMEM(x) (x)
12
13/* 11/*
14 * The following code assumes the serial port has already been 12 * The following code assumes the serial port has already been
15 * initialized by the bootloader. We search for the first enabled 13 * initialized by the bootloader. We search for the first enabled
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 07:18:39 -0400