aboutsummaryrefslogtreecommitdiffstats
path: root/arch/arm/mach-sa1100
diff options
context:
space:
mode:
authorJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
committerJonathan Herman <hermanjl@cs.unc.edu>2013-01-17 16:15:55 -0500
commit8dea78da5cee153b8af9c07a2745f6c55057fe12 (patch)
treea8f4d49d63b1ecc92f2fddceba0655b2472c5bd9 /arch/arm/mach-sa1100
parent406089d01562f1e2bf9f089fd7637009ebaad589 (diff)
Patched in Tegra support.
Diffstat (limited to 'arch/arm/mach-sa1100')
-rw-r--r--arch/arm/mach-sa1100/Kconfig12
-rw-r--r--arch/arm/mach-sa1100/Makefile12
-rw-r--r--arch/arm/mach-sa1100/Makefile.boot7
-rw-r--r--arch/arm/mach-sa1100/assabet.c296
-rw-r--r--arch/arm/mach-sa1100/badge4.c78
-rw-r--r--arch/arm/mach-sa1100/cerf.c65
-rw-r--r--arch/arm/mach-sa1100/clock.c82
-rw-r--r--arch/arm/mach-sa1100/collie.c69
-rw-r--r--arch/arm/mach-sa1100/cpu-sa1100.c3
-rw-r--r--arch/arm/mach-sa1100/cpu-sa1110.c1
-rw-r--r--arch/arm/mach-sa1100/generic.c178
-rw-r--r--arch/arm/mach-sa1100/generic.h15
-rw-r--r--arch/arm/mach-sa1100/h3100.c29
-rw-r--r--arch/arm/mach-sa1100/h3600.c38
-rw-r--r--arch/arm/mach-sa1100/h3xxx.c15
-rw-r--r--arch/arm/mach-sa1100/hackkit.c49
-rw-r--r--arch/arm/mach-sa1100/include/mach/SA-1100.h245
-rw-r--r--arch/arm/mach-sa1100/include/mach/assabet.h15
-rw-r--r--arch/arm/mach-sa1100/include/mach/cerf.h15
-rw-r--r--arch/arm/mach-sa1100/include/mach/collie.h3
-rw-r--r--arch/arm/mach-sa1100/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-sa1100/include/mach/entry-macro.S6
-rw-r--r--arch/arm/mach-sa1100/include/mach/gpio.h8
-rw-r--r--arch/arm/mach-sa1100/include/mach/hardware.h6
-rw-r--r--arch/arm/mach-sa1100/include/mach/irqs.h27
-rw-r--r--arch/arm/mach-sa1100/include/mach/nanoengine.h12
-rw-r--r--arch/arm/mach-sa1100/include/mach/neponset.h52
-rw-r--r--arch/arm/mach-sa1100/include/mach/shannon.h14
-rw-r--r--arch/arm/mach-sa1100/include/mach/simpad.h106
-rw-r--r--arch/arm/mach-sa1100/include/mach/uncompress.h2
-rw-r--r--arch/arm/mach-sa1100/irq.c9
-rw-r--r--arch/arm/mach-sa1100/jornada720.c53
-rw-r--r--arch/arm/mach-sa1100/jornada720_ssp.c5
-rw-r--r--arch/arm/mach-sa1100/lart.c116
-rw-r--r--arch/arm/mach-sa1100/nanoengine.c20
-rw-r--r--arch/arm/mach-sa1100/neponset.c554
-rw-r--r--arch/arm/mach-sa1100/pci-nanoengine.c27
-rw-r--r--arch/arm/mach-sa1100/pleb.c29
-rw-r--r--arch/arm/mach-sa1100/pm.c8
-rw-r--r--arch/arm/mach-sa1100/shannon.c35
-rw-r--r--arch/arm/mach-sa1100/simpad.c243
-rw-r--r--arch/arm/mach-sa1100/sleep.S41
-rw-r--r--arch/arm/mach-sa1100/ssp.c2
-rw-r--r--arch/arm/mach-sa1100/time.c75
44 files changed, 1119 insertions, 1560 deletions
diff --git a/arch/arm/mach-sa1100/Kconfig b/arch/arm/mach-sa1100/Kconfig
index ca14dbdcfb2..42625e4d949 100644
--- a/arch/arm/mach-sa1100/Kconfig
+++ b/arch/arm/mach-sa1100/Kconfig
@@ -49,15 +49,15 @@ config SA1100_COLLIE
49 bool "Sharp Zaurus SL5500" 49 bool "Sharp Zaurus SL5500"
50 # FIXME: select CPU_FREQ_SA11x0 50 # FIXME: select CPU_FREQ_SA11x0
51 select SHARP_LOCOMO 51 select SHARP_LOCOMO
52 select SHARP_PARAM
53 select SHARP_SCOOP 52 select SHARP_SCOOP
53 select SHARP_PARAM
54 help 54 help
55 Say Y here to support the Sharp Zaurus SL5500 PDAs. 55 Say Y here to support the Sharp Zaurus SL5500 PDAs.
56 56
57config SA1100_H3100 57config SA1100_H3100
58 bool "Compaq iPAQ H3100" 58 bool "Compaq iPAQ H3100"
59 select CPU_FREQ_SA1110
60 select HTC_EGPIO 59 select HTC_EGPIO
60 select CPU_FREQ_SA1110
61 help 61 help
62 Say Y here if you intend to run this kernel on the Compaq iPAQ 62 Say Y here if you intend to run this kernel on the Compaq iPAQ
63 H3100 handheld computer. Information about this machine and the 63 H3100 handheld computer. Information about this machine and the
@@ -67,8 +67,8 @@ config SA1100_H3100
67 67
68config SA1100_H3600 68config SA1100_H3600
69 bool "Compaq iPAQ H3600/H3700" 69 bool "Compaq iPAQ H3600/H3700"
70 select CPU_FREQ_SA1110
71 select HTC_EGPIO 70 select HTC_EGPIO
71 select CPU_FREQ_SA1110
72 help 72 help
73 Say Y here if you intend to run this kernel on the Compaq iPAQ 73 Say Y here if you intend to run this kernel on the Compaq iPAQ
74 H3600 handheld computer. Information about this machine and the 74 H3600 handheld computer. Information about this machine and the
@@ -78,16 +78,16 @@ config SA1100_H3600
78 78
79config SA1100_BADGE4 79config SA1100_BADGE4
80 bool "HP Labs BadgePAD 4" 80 bool "HP Labs BadgePAD 4"
81 select CPU_FREQ_SA1100
82 select SA1111 81 select SA1111
82 select CPU_FREQ_SA1100
83 help 83 help
84 Say Y here if you want to build a kernel for the HP Laboratories 84 Say Y here if you want to build a kernel for the HP Laboratories
85 BadgePAD 4. 85 BadgePAD 4.
86 86
87config SA1100_JORNADA720 87config SA1100_JORNADA720
88 bool "HP Jornada 720" 88 bool "HP Jornada 720"
89 # FIXME: select CPU_FREQ_SA11x0
90 select SA1111 89 select SA1111
90 # FIXME: select CPU_FREQ_SA11x0
91 help 91 help
92 Say Y here if you want to build a kernel for the HP Jornada 720 92 Say Y here if you want to build a kernel for the HP Jornada 720
93 handheld computer. See 93 handheld computer. See
@@ -95,8 +95,8 @@ config SA1100_JORNADA720
95 95
96config SA1100_JORNADA720_SSP 96config SA1100_JORNADA720_SSP
97 bool "HP Jornada 720 Extended SSP driver" 97 bool "HP Jornada 720 Extended SSP driver"
98 depends on SA1100_JORNADA720
99 select SA1100_SSP 98 select SA1100_SSP
99 depends on SA1100_JORNADA720
100 help 100 help
101 Say Y here if you have a HP Jornada 7xx handheld computer and you 101 Say Y here if you have a HP Jornada 7xx handheld computer and you
102 want to access devices connected to the MCU. Those include the 102 want to access devices connected to the MCU. Those include the
diff --git a/arch/arm/mach-sa1100/Makefile b/arch/arm/mach-sa1100/Makefile
index 1aed9e70465..41252d22e65 100644
--- a/arch/arm/mach-sa1100/Makefile
+++ b/arch/arm/mach-sa1100/Makefile
@@ -3,21 +3,25 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := clock.o generic.o irq.o time.o #nmi-oopser.o 6obj-y := clock.o generic.o gpio.o irq.o dma.o time.o #nmi-oopser.o
7obj-m := 7obj-m :=
8obj-n := 8obj-n :=
9obj- := 9obj- :=
10led-y := leds.o
10 11
11obj-$(CONFIG_CPU_FREQ_SA1100) += cpu-sa1100.o 12obj-$(CONFIG_CPU_FREQ_SA1100) += cpu-sa1100.o
12obj-$(CONFIG_CPU_FREQ_SA1110) += cpu-sa1110.o 13obj-$(CONFIG_CPU_FREQ_SA1110) += cpu-sa1110.o
13 14
14# Specific board support 15# Specific board support
15obj-$(CONFIG_SA1100_ASSABET) += assabet.o 16obj-$(CONFIG_SA1100_ASSABET) += assabet.o
17led-$(CONFIG_SA1100_ASSABET) += leds-assabet.o
16obj-$(CONFIG_ASSABET_NEPONSET) += neponset.o 18obj-$(CONFIG_ASSABET_NEPONSET) += neponset.o
17 19
18obj-$(CONFIG_SA1100_BADGE4) += badge4.o 20obj-$(CONFIG_SA1100_BADGE4) += badge4.o
21led-$(CONFIG_SA1100_BADGE4) += leds-badge4.o
19 22
20obj-$(CONFIG_SA1100_CERF) += cerf.o 23obj-$(CONFIG_SA1100_CERF) += cerf.o
24led-$(CONFIG_SA1100_CERF) += leds-cerf.o
21 25
22obj-$(CONFIG_SA1100_COLLIE) += collie.o 26obj-$(CONFIG_SA1100_COLLIE) += collie.o
23 27
@@ -25,11 +29,13 @@ obj-$(CONFIG_SA1100_H3100) += h3100.o h3xxx.o
25obj-$(CONFIG_SA1100_H3600) += h3600.o h3xxx.o 29obj-$(CONFIG_SA1100_H3600) += h3600.o h3xxx.o
26 30
27obj-$(CONFIG_SA1100_HACKKIT) += hackkit.o 31obj-$(CONFIG_SA1100_HACKKIT) += hackkit.o
32led-$(CONFIG_SA1100_HACKKIT) += leds-hackkit.o
28 33
29obj-$(CONFIG_SA1100_JORNADA720) += jornada720.o 34obj-$(CONFIG_SA1100_JORNADA720) += jornada720.o
30obj-$(CONFIG_SA1100_JORNADA720_SSP) += jornada720_ssp.o 35obj-$(CONFIG_SA1100_JORNADA720_SSP) += jornada720_ssp.o
31 36
32obj-$(CONFIG_SA1100_LART) += lart.o 37obj-$(CONFIG_SA1100_LART) += lart.o
38led-$(CONFIG_SA1100_LART) += leds-lart.o
33 39
34obj-$(CONFIG_SA1100_NANOENGINE) += nanoengine.o 40obj-$(CONFIG_SA1100_NANOENGINE) += nanoengine.o
35obj-$(CONFIG_PCI_NANOENGINE) += pci-nanoengine.o 41obj-$(CONFIG_PCI_NANOENGINE) += pci-nanoengine.o
@@ -39,6 +45,10 @@ obj-$(CONFIG_SA1100_PLEB) += pleb.o
39obj-$(CONFIG_SA1100_SHANNON) += shannon.o 45obj-$(CONFIG_SA1100_SHANNON) += shannon.o
40 46
41obj-$(CONFIG_SA1100_SIMPAD) += simpad.o 47obj-$(CONFIG_SA1100_SIMPAD) += simpad.o
48led-$(CONFIG_SA1100_SIMPAD) += leds-simpad.o
49
50# LEDs support
51obj-$(CONFIG_LEDS) += $(led-y)
42 52
43# Miscellaneous functions 53# Miscellaneous functions
44obj-$(CONFIG_PM) += pm.o sleep.o 54obj-$(CONFIG_PM) += pm.o sleep.o
diff --git a/arch/arm/mach-sa1100/Makefile.boot b/arch/arm/mach-sa1100/Makefile.boot
index f7951aa0456..a56ad0417cf 100644
--- a/arch/arm/mach-sa1100/Makefile.boot
+++ b/arch/arm/mach-sa1100/Makefile.boot
@@ -1,7 +1,6 @@
1ifeq ($(CONFIG_SA1111),y) 1 zreladdr-y := 0xc0008000
2 zreladdr-y += 0xc0208000 2ifeq ($(CONFIG_ARCH_SA1100),y)
3else 3 zreladdr-$(CONFIG_SA1111) := 0xc0208000
4 zreladdr-y += 0xc0008000
5endif 4endif
6params_phys-y := 0xc0000100 5params_phys-y := 0xc0000100
7initrd_phys-y := 0xc0800000 6initrd_phys-y := 0xc0800000
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index 9a23739f702..26257df19b6 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -14,20 +14,15 @@
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/errno.h> 15#include <linux/errno.h>
16#include <linux/ioport.h> 16#include <linux/ioport.h>
17#include <linux/platform_data/sa11x0-serial.h>
18#include <linux/serial_core.h> 17#include <linux/serial_core.h>
19#include <linux/mfd/ucb1x00.h>
20#include <linux/mtd/mtd.h> 18#include <linux/mtd/mtd.h>
21#include <linux/mtd/partitions.h> 19#include <linux/mtd/partitions.h>
22#include <linux/delay.h> 20#include <linux/delay.h>
23#include <linux/mm.h> 21#include <linux/mm.h>
24#include <linux/leds.h>
25#include <linux/slab.h>
26
27#include <video/sa1100fb.h>
28 22
29#include <mach/hardware.h> 23#include <mach/hardware.h>
30#include <asm/mach-types.h> 24#include <asm/mach-types.h>
25#include <asm/irq.h>
31#include <asm/setup.h> 26#include <asm/setup.h>
32#include <asm/page.h> 27#include <asm/page.h>
33#include <asm/pgtable-hwdef.h> 28#include <asm/pgtable-hwdef.h>
@@ -38,20 +33,20 @@
38#include <asm/mach/flash.h> 33#include <asm/mach/flash.h>
39#include <asm/mach/irda.h> 34#include <asm/mach/irda.h>
40#include <asm/mach/map.h> 35#include <asm/mach/map.h>
36#include <asm/mach/serial_sa1100.h>
41#include <mach/assabet.h> 37#include <mach/assabet.h>
42#include <linux/platform_data/mfd-mcp-sa11x0.h> 38#include <mach/mcp.h>
43#include <mach/irqs.h>
44 39
45#include "generic.h" 40#include "generic.h"
46 41
47#define ASSABET_BCR_DB1110 \ 42#define ASSABET_BCR_DB1110 \
48 (ASSABET_BCR_SPK_OFF | \ 43 (ASSABET_BCR_SPK_OFF | ASSABET_BCR_QMUTE | \
49 ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \ 44 ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
50 ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \ 45 ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
51 ASSABET_BCR_IRDA_MD0) 46 ASSABET_BCR_IRDA_MD0)
52 47
53#define ASSABET_BCR_DB1111 \ 48#define ASSABET_BCR_DB1111 \
54 (ASSABET_BCR_SPK_OFF | \ 49 (ASSABET_BCR_SPK_OFF | ASSABET_BCR_QMUTE | \
55 ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \ 50 ASSABET_BCR_LED_GREEN | ASSABET_BCR_LED_RED | \
56 ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \ 51 ASSABET_BCR_RS232EN | ASSABET_BCR_LCD_12RGB | \
57 ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \ 52 ASSABET_BCR_CF_BUS_OFF | ASSABET_BCR_STEREO_LB | \
@@ -74,10 +69,31 @@ void ASSABET_BCR_frob(unsigned int mask, unsigned int val)
74 69
75EXPORT_SYMBOL(ASSABET_BCR_frob); 70EXPORT_SYMBOL(ASSABET_BCR_frob);
76 71
77static void assabet_ucb1x00_reset(enum ucb1x00_reset state) 72static void assabet_backlight_power(int on)
78{ 73{
79 if (state == UCB_RST_PROBE) 74#ifndef ASSABET_PAL_VIDEO
80 ASSABET_BCR_set(ASSABET_BCR_CODEC_RST); 75 if (on)
76 ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON);
77 else
78#endif
79 ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
80}
81
82/*
83 * Turn on/off the backlight. When turning the backlight on,
84 * we wait 500us after turning it on so we don't cause the
85 * supplies to droop when we enable the LCD controller (and
86 * cause a hard reset.)
87 */
88static void assabet_lcd_power(int on)
89{
90#ifndef ASSABET_PAL_VIDEO
91 if (on) {
92 ASSABET_BCR_set(ASSABET_BCR_LCD_ON);
93 udelay(500);
94 } else
95#endif
96 ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
81} 97}
82 98
83 99
@@ -136,8 +152,15 @@ static struct flash_platform_data assabet_flash_data = {
136}; 152};
137 153
138static struct resource assabet_flash_resources[] = { 154static struct resource assabet_flash_resources[] = {
139 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M), 155 {
140 DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M), 156 .start = SA1100_CS0_PHYS,
157 .end = SA1100_CS0_PHYS + SZ_32M - 1,
158 .flags = IORESOURCE_MEM,
159 }, {
160 .start = SA1100_CS1_PHYS,
161 .end = SA1100_CS1_PHYS + SZ_32M - 1,
162 .flags = IORESOURCE_MEM,
163 }
141}; 164};
142 165
143 166
@@ -176,126 +199,18 @@ static struct irda_platform_data assabet_irda_data = {
176 .set_speed = assabet_irda_set_speed, 199 .set_speed = assabet_irda_set_speed,
177}; 200};
178 201
179static struct ucb1x00_plat_data assabet_ucb1x00_data = {
180 .reset = assabet_ucb1x00_reset,
181 .gpio_base = -1,
182};
183
184static struct mcp_plat_data assabet_mcp_data = { 202static struct mcp_plat_data assabet_mcp_data = {
185 .mccr0 = MCCR0_ADM, 203 .mccr0 = MCCR0_ADM,
186 .sclk_rate = 11981000, 204 .sclk_rate = 11981000,
187 .codec_pdata = &assabet_ucb1x00_data,
188}; 205};
189 206
190static void assabet_lcd_set_visual(u32 visual)
191{
192 u_int is_true_color = visual == FB_VISUAL_TRUECOLOR;
193
194 if (machine_is_assabet()) {
195#if 1 // phase 4 or newer Assabet's
196 if (is_true_color)
197 ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
198 else
199 ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
200#else
201 // older Assabet's
202 if (is_true_color)
203 ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
204 else
205 ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
206#endif
207 }
208}
209
210#ifndef ASSABET_PAL_VIDEO
211static void assabet_lcd_backlight_power(int on)
212{
213 if (on)
214 ASSABET_BCR_set(ASSABET_BCR_LIGHT_ON);
215 else
216 ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
217}
218
219/*
220 * Turn on/off the backlight. When turning the backlight on, we wait
221 * 500us after turning it on so we don't cause the supplies to droop
222 * when we enable the LCD controller (and cause a hard reset.)
223 */
224static void assabet_lcd_power(int on)
225{
226 if (on) {
227 ASSABET_BCR_set(ASSABET_BCR_LCD_ON);
228 udelay(500);
229 } else
230 ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
231}
232
233/*
234 * The assabet uses a sharp LQ039Q2DS54 LCD module. It is actually
235 * takes an RGB666 signal, but we provide it with an RGB565 signal
236 * instead (def_rgb_16).
237 */
238static struct sa1100fb_mach_info lq039q2ds54_info = {
239 .pixclock = 171521, .bpp = 16,
240 .xres = 320, .yres = 240,
241
242 .hsync_len = 5, .vsync_len = 1,
243 .left_margin = 61, .upper_margin = 3,
244 .right_margin = 9, .lower_margin = 0,
245
246 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
247
248 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
249 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
250
251 .backlight_power = assabet_lcd_backlight_power,
252 .lcd_power = assabet_lcd_power,
253 .set_visual = assabet_lcd_set_visual,
254};
255#else
256static void assabet_pal_backlight_power(int on)
257{
258 ASSABET_BCR_clear(ASSABET_BCR_LIGHT_ON);
259}
260
261static void assabet_pal_power(int on)
262{
263 ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
264}
265
266static struct sa1100fb_mach_info pal_info = {
267 .pixclock = 67797, .bpp = 16,
268 .xres = 640, .yres = 512,
269
270 .hsync_len = 64, .vsync_len = 6,
271 .left_margin = 125, .upper_margin = 70,
272 .right_margin = 115, .lower_margin = 36,
273
274 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
275 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
276
277 .backlight_power = assabet_pal_backlight_power,
278 .lcd_power = assabet_pal_power,
279 .set_visual = assabet_lcd_set_visual,
280};
281#endif
282
283#ifdef CONFIG_ASSABET_NEPONSET
284static struct resource neponset_resources[] = {
285 DEFINE_RES_MEM(0x10000000, 0x08000000),
286 DEFINE_RES_MEM(0x18000000, 0x04000000),
287 DEFINE_RES_MEM(0x40000000, SZ_8K),
288 DEFINE_RES_IRQ(IRQ_GPIO25),
289};
290#endif
291
292static void __init assabet_init(void) 207static void __init assabet_init(void)
293{ 208{
294 /* 209 /*
295 * Ensure that the power supply is in "high power" mode. 210 * Ensure that the power supply is in "high power" mode.
296 */ 211 */
297 GPSR = GPIO_GPIO16;
298 GPDR |= GPIO_GPIO16; 212 GPDR |= GPIO_GPIO16;
213 GPSR = GPIO_GPIO16;
299 214
300 /* 215 /*
301 * Ensure that these pins are set as outputs and are driving 216 * Ensure that these pins are set as outputs and are driving
@@ -303,16 +218,8 @@ static void __init assabet_init(void)
303 * the WS latch in the CPLD, and we don't float causing 218 * the WS latch in the CPLD, and we don't float causing
304 * excessive power drain. --rmk 219 * excessive power drain. --rmk
305 */ 220 */
306 GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
307 GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM; 221 GPDR |= GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
308 222 GPCR = GPIO_SSP_TXD | GPIO_SSP_SCLK | GPIO_SSP_SFRM;
309 /*
310 * Also set GPIO27 as an output; this is used to clock UART3
311 * via the FPGA and as otherwise has no pullups or pulldowns,
312 * so stop it floating.
313 */
314 GPCR = GPIO_GPIO27;
315 GPDR |= GPIO_GPIO27;
316 223
317 /* 224 /*
318 * Set up registers for sleep mode. 225 * Set up registers for sleep mode.
@@ -324,7 +231,8 @@ static void __init assabet_init(void)
324 PPDR |= PPC_TXD3 | PPC_TXD1; 231 PPDR |= PPC_TXD3 | PPC_TXD1;
325 PPSR |= PPC_TXD3 | PPC_TXD1; 232 PPSR |= PPC_TXD3 | PPC_TXD1;
326 233
327 sa11x0_ppc_configure_mcp(); 234 sa1100fb_lcd_power = assabet_lcd_power;
235 sa1100fb_backlight_power = assabet_backlight_power;
328 236
329 if (machine_has_neponset()) { 237 if (machine_has_neponset()) {
330 /* 238 /*
@@ -338,17 +246,9 @@ static void __init assabet_init(void)
338#ifndef CONFIG_ASSABET_NEPONSET 246#ifndef CONFIG_ASSABET_NEPONSET
339 printk( "Warning: Neponset detected but full support " 247 printk( "Warning: Neponset detected but full support "
340 "hasn't been configured in the kernel\n" ); 248 "hasn't been configured in the kernel\n" );
341#else
342 platform_device_register_simple("neponset", 0,
343 neponset_resources, ARRAY_SIZE(neponset_resources));
344#endif 249#endif
345 } 250 }
346 251
347#ifndef ASSABET_PAL_VIDEO
348 sa11x0_register_lcd(&lq039q2ds54_info);
349#else
350 sa11x0_register_lcd(&pal_video);
351#endif
352 sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources, 252 sa11x0_register_mtd(&assabet_flash_data, assabet_flash_resources,
353 ARRAY_SIZE(assabet_flash_resources)); 253 ARRAY_SIZE(assabet_flash_resources));
354 sa11x0_register_irda(&assabet_irda_data); 254 sa11x0_register_irda(&assabet_irda_data);
@@ -364,11 +264,11 @@ static void __init assabet_init(void)
364static void __init map_sa1100_gpio_regs( void ) 264static void __init map_sa1100_gpio_regs( void )
365{ 265{
366 unsigned long phys = __PREG(GPLR) & PMD_MASK; 266 unsigned long phys = __PREG(GPLR) & PMD_MASK;
367 unsigned long virt = (unsigned long)io_p2v(phys); 267 unsigned long virt = io_p2v(phys);
368 int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO); 268 int prot = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_DOMAIN(DOMAIN_IO);
369 pmd_t *pmd; 269 pmd_t *pmd;
370 270
371 pmd = pmd_offset(pud_offset(pgd_offset_k(virt), virt), virt); 271 pmd = pmd_offset(pgd_offset_k(virt), virt);
372 *pmd = __pmd(phys | prot); 272 *pmd = __pmd(phys | prot);
373 flush_pmd_entry(pmd); 273 flush_pmd_entry(pmd);
374} 274}
@@ -388,7 +288,7 @@ static void __init map_sa1100_gpio_regs( void )
388 */ 288 */
389static void __init get_assabet_scr(void) 289static void __init get_assabet_scr(void)
390{ 290{
391 unsigned long uninitialized_var(scr), i; 291 unsigned long scr, i;
392 292
393 GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */ 293 GPDR |= 0x3fc; /* Configure GPIO 9:2 as outputs */
394 GPSR = 0x3fc; /* Write 0xFF to GPIO 9:2 */ 294 GPSR = 0x3fc; /* Write 0xFF to GPIO 9:2 */
@@ -401,7 +301,8 @@ static void __init get_assabet_scr(void)
401} 301}
402 302
403static void __init 303static void __init
404fixup_assabet(struct tag *tags, char **cmdline, struct meminfo *mi) 304fixup_assabet(struct machine_desc *desc, struct tag *tags,
305 char **cmdline, struct meminfo *mi)
405{ 306{
406 /* This must be done before any call to machine_has_neponset() */ 307 /* This must be done before any call to machine_has_neponset() */
407 map_sa1100_gpio_regs(); 308 map_sa1100_gpio_regs();
@@ -512,8 +413,21 @@ static void __init assabet_map_io(void)
512 */ 413 */
513 Ser1SDCR0 |= SDCR0_SUS; 414 Ser1SDCR0 |= SDCR0_SUS;
514 415
515 if (!machine_has_neponset()) 416 if (machine_has_neponset()) {
417#ifdef CONFIG_ASSABET_NEPONSET
418 extern void neponset_map_io(void);
419
420 /*
421 * We map Neponset registers even if it isn't present since
422 * many drivers will try to probe their stuff (and fail).
423 * This is still more friendly than a kernel paging request
424 * crash.
425 */
426 neponset_map_io();
427#endif
428 } else {
516 sa1100_register_uart_fns(&assabet_port_fns); 429 sa1100_register_uart_fns(&assabet_port_fns);
430 }
517 431
518 /* 432 /*
519 * When Neponset is attached, the first UART should be 433 * When Neponset is attached, the first UART should be
@@ -531,101 +445,15 @@ static void __init assabet_map_io(void)
531 sa1100_register_uart(2, 3); 445 sa1100_register_uart(2, 3);
532} 446}
533 447
534/* LEDs */
535#if defined(CONFIG_NEW_LEDS) && defined(CONFIG_LEDS_CLASS)
536struct assabet_led {
537 struct led_classdev cdev;
538 u32 mask;
539};
540
541/*
542 * The triggers lines up below will only be used if the
543 * LED triggers are compiled in.
544 */
545static const struct {
546 const char *name;
547 const char *trigger;
548} assabet_leds[] = {
549 { "assabet:red", "cpu0",},
550 { "assabet:green", "heartbeat", },
551};
552
553/*
554 * The LED control in Assabet is reversed:
555 * - setting bit means turn off LED
556 * - clearing bit means turn on LED
557 */
558static void assabet_led_set(struct led_classdev *cdev,
559 enum led_brightness b)
560{
561 struct assabet_led *led = container_of(cdev,
562 struct assabet_led, cdev);
563
564 if (b != LED_OFF)
565 ASSABET_BCR_clear(led->mask);
566 else
567 ASSABET_BCR_set(led->mask);
568}
569
570static enum led_brightness assabet_led_get(struct led_classdev *cdev)
571{
572 struct assabet_led *led = container_of(cdev,
573 struct assabet_led, cdev);
574
575 return (ASSABET_BCR & led->mask) ? LED_OFF : LED_FULL;
576}
577
578static int __init assabet_leds_init(void)
579{
580 int i;
581
582 if (!machine_is_assabet())
583 return -ENODEV;
584
585 for (i = 0; i < ARRAY_SIZE(assabet_leds); i++) {
586 struct assabet_led *led;
587
588 led = kzalloc(sizeof(*led), GFP_KERNEL);
589 if (!led)
590 break;
591
592 led->cdev.name = assabet_leds[i].name;
593 led->cdev.brightness_set = assabet_led_set;
594 led->cdev.brightness_get = assabet_led_get;
595 led->cdev.default_trigger = assabet_leds[i].trigger;
596
597 if (!i)
598 led->mask = ASSABET_BCR_LED_RED;
599 else
600 led->mask = ASSABET_BCR_LED_GREEN;
601
602 if (led_classdev_register(NULL, &led->cdev) < 0) {
603 kfree(led);
604 break;
605 }
606 }
607
608 return 0;
609}
610
611/*
612 * Since we may have triggers on any subsystem, defer registration
613 * until after subsystem_init.
614 */
615fs_initcall(assabet_leds_init);
616#endif
617 448
618MACHINE_START(ASSABET, "Intel-Assabet") 449MACHINE_START(ASSABET, "Intel-Assabet")
619 .atag_offset = 0x100, 450 .boot_params = 0xc0000100,
620 .fixup = fixup_assabet, 451 .fixup = fixup_assabet,
621 .map_io = assabet_map_io, 452 .map_io = assabet_map_io,
622 .nr_irqs = SA1100_NR_IRQS,
623 .init_irq = sa1100_init_irq, 453 .init_irq = sa1100_init_irq,
624 .timer = &sa1100_timer, 454 .timer = &sa1100_timer,
625 .init_machine = assabet_init, 455 .init_machine = assabet_init,
626 .init_late = sa11x0_init_late,
627#ifdef CONFIG_SA1111 456#ifdef CONFIG_SA1111
628 .dma_zone_size = SZ_1M, 457 .dma_zone_size = SZ_1M,
629#endif 458#endif
630 .restart = sa11x0_restart,
631MACHINE_END 459MACHINE_END
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index b2dadf3ea3d..b4311b0a439 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -16,15 +16,12 @@
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/platform_data/sa11x0-serial.h>
20#include <linux/platform_device.h> 19#include <linux/platform_device.h>
21#include <linux/delay.h> 20#include <linux/delay.h>
22#include <linux/tty.h> 21#include <linux/tty.h>
23#include <linux/mtd/mtd.h> 22#include <linux/mtd/mtd.h>
24#include <linux/mtd/partitions.h> 23#include <linux/mtd/partitions.h>
25#include <linux/errno.h> 24#include <linux/errno.h>
26#include <linux/gpio.h>
27#include <linux/leds.h>
28 25
29#include <mach/hardware.h> 26#include <mach/hardware.h>
30#include <asm/mach-types.h> 27#include <asm/mach-types.h>
@@ -35,33 +32,27 @@
35#include <asm/mach/flash.h> 32#include <asm/mach/flash.h>
36#include <asm/mach/map.h> 33#include <asm/mach/map.h>
37#include <asm/hardware/sa1111.h> 34#include <asm/hardware/sa1111.h>
35#include <asm/mach/serial_sa1100.h>
38 36
39#include <mach/badge4.h> 37#include <mach/badge4.h>
40 38
41#include "generic.h" 39#include "generic.h"
42 40
43static struct resource sa1111_resources[] = { 41static struct resource sa1111_resources[] = {
44 [0] = DEFINE_RES_MEM(BADGE4_SA1111_BASE, 0x2000), 42 [0] = {
45 [1] = DEFINE_RES_IRQ(BADGE4_IRQ_GPIO_SA1111), 43 .start = BADGE4_SA1111_BASE,
44 .end = BADGE4_SA1111_BASE + 0x00001fff,
45 .flags = IORESOURCE_MEM,
46 },
47 [1] = {
48 .start = BADGE4_IRQ_GPIO_SA1111,
49 .end = BADGE4_IRQ_GPIO_SA1111,
50 .flags = IORESOURCE_IRQ,
51 },
46}; 52};
47 53
48static int badge4_sa1111_enable(void *data, unsigned devid)
49{
50 if (devid == SA1111_DEVID_USB)
51 badge4_set_5V(BADGE4_5V_USB, 1);
52 return 0;
53}
54
55static void badge4_sa1111_disable(void *data, unsigned devid)
56{
57 if (devid == SA1111_DEVID_USB)
58 badge4_set_5V(BADGE4_5V_USB, 0);
59}
60
61static struct sa1111_platform_data sa1111_info = { 54static struct sa1111_platform_data sa1111_info = {
62 .disable_devs = SA1111_DEVID_PS2_MSE, 55 .irq_base = IRQ_BOARD_END,
63 .enable = badge4_sa1111_enable,
64 .disable = badge4_sa1111_disable,
65}; 56};
66 57
67static u64 sa1111_dmamask = 0xffffffffUL; 58static u64 sa1111_dmamask = 0xffffffffUL;
@@ -78,36 +69,8 @@ static struct platform_device sa1111_device = {
78 .resource = sa1111_resources, 69 .resource = sa1111_resources,
79}; 70};
80 71
81/* LEDs */
82struct gpio_led badge4_gpio_leds[] = {
83 {
84 .name = "badge4:red",
85 .default_trigger = "heartbeat",
86 .gpio = 7,
87 },
88 {
89 .name = "badge4:green",
90 .default_trigger = "cpu0",
91 .gpio = 9,
92 },
93};
94
95static struct gpio_led_platform_data badge4_gpio_led_info = {
96 .leds = badge4_gpio_leds,
97 .num_leds = ARRAY_SIZE(badge4_gpio_leds),
98};
99
100static struct platform_device badge4_leds = {
101 .name = "leds-gpio",
102 .id = -1,
103 .dev = {
104 .platform_data = &badge4_gpio_led_info,
105 }
106};
107
108static struct platform_device *devices[] __initdata = { 72static struct platform_device *devices[] __initdata = {
109 &sa1111_device, 73 &sa1111_device,
110 &badge4_leds,
111}; 74};
112 75
113static int __init badge4_sa1111_init(void) 76static int __init badge4_sa1111_init(void)
@@ -158,8 +121,11 @@ static struct flash_platform_data badge4_flash_data = {
158 .nr_parts = ARRAY_SIZE(badge4_partitions), 121 .nr_parts = ARRAY_SIZE(badge4_partitions),
159}; 122};
160 123
161static struct resource badge4_flash_resource = 124static struct resource badge4_flash_resource = {
162 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_64M); 125 .start = SA1100_CS0_PHYS,
126 .end = SA1100_CS0_PHYS + SZ_64M - 1,
127 .flags = IORESOURCE_MEM,
128};
163 129
164static int five_v_on __initdata = 0; 130static int five_v_on __initdata = 0;
165 131
@@ -303,6 +269,11 @@ static struct map_desc badge4_io_desc[] __initdata = {
303 .pfn = __phys_to_pfn(0x10000000), 269 .pfn = __phys_to_pfn(0x10000000),
304 .length = 0x00100000, 270 .length = 0x00100000,
305 .type = MT_DEVICE 271 .type = MT_DEVICE
272 }, { /* SA-1111 */
273 .virtual = 0xf4000000,
274 .pfn = __phys_to_pfn(0x48000000),
275 .length = 0x00100000,
276 .type = MT_DEVICE
306 } 277 }
307}; 278};
308 279
@@ -331,14 +302,11 @@ static void __init badge4_map_io(void)
331} 302}
332 303
333MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4") 304MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4")
334 .atag_offset = 0x100, 305 .boot_params = 0xc0000100,
335 .map_io = badge4_map_io, 306 .map_io = badge4_map_io,
336 .nr_irqs = SA1100_NR_IRQS,
337 .init_irq = sa1100_init_irq, 307 .init_irq = sa1100_init_irq,
338 .init_late = sa11x0_init_late,
339 .timer = &sa1100_timer, 308 .timer = &sa1100_timer,
340#ifdef CONFIG_SA1111 309#ifdef CONFIG_SA1111
341 .dma_zone_size = SZ_1M, 310 .dma_zone_size = SZ_1M,
342#endif 311#endif
343 .restart = sa11x0_restart,
344MACHINE_END 312MACHINE_END
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index 304bca4a07c..7f3da4b11ec 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -13,14 +13,12 @@
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/tty.h> 15#include <linux/tty.h>
16#include <linux/platform_data/sa11x0-serial.h>
17#include <linux/platform_device.h> 16#include <linux/platform_device.h>
18#include <linux/irq.h> 17#include <linux/irq.h>
19#include <linux/mtd/mtd.h> 18#include <linux/mtd/mtd.h>
20#include <linux/mtd/partitions.h> 19#include <linux/mtd/partitions.h>
21#include <linux/gpio.h>
22#include <linux/leds.h>
23 20
21#include <asm/irq.h>
24#include <mach/hardware.h> 22#include <mach/hardware.h>
25#include <asm/setup.h> 23#include <asm/setup.h>
26 24
@@ -28,14 +26,18 @@
28#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
29#include <asm/mach/flash.h> 27#include <asm/mach/flash.h>
30#include <asm/mach/map.h> 28#include <asm/mach/map.h>
29#include <asm/mach/serial_sa1100.h>
31 30
32#include <mach/cerf.h> 31#include <mach/cerf.h>
33#include <linux/platform_data/mfd-mcp-sa11x0.h> 32#include <mach/mcp.h>
34#include <mach/irqs.h>
35#include "generic.h" 33#include "generic.h"
36 34
37static struct resource cerfuart2_resources[] = { 35static struct resource cerfuart2_resources[] = {
38 [0] = DEFINE_RES_MEM(0x80030000, SZ_64K), 36 [0] = {
37 .start = 0x80030000,
38 .end = 0x8003ffff,
39 .flags = IORESOURCE_MEM,
40 },
39}; 41};
40 42
41static struct platform_device cerfuart2_device = { 43static struct platform_device cerfuart2_device = {
@@ -45,48 +47,8 @@ static struct platform_device cerfuart2_device = {
45 .resource = cerfuart2_resources, 47 .resource = cerfuart2_resources,
46}; 48};
47 49
48/* LEDs */
49struct gpio_led cerf_gpio_leds[] = {
50 {
51 .name = "cerf:d0",
52 .default_trigger = "heartbeat",
53 .gpio = 0,
54 },
55 {
56 .name = "cerf:d1",
57 .default_trigger = "cpu0",
58 .gpio = 1,
59 },
60 {
61 .name = "cerf:d2",
62 .default_trigger = "default-on",
63 .gpio = 2,
64 },
65 {
66 .name = "cerf:d3",
67 .default_trigger = "default-on",
68 .gpio = 3,
69 },
70
71};
72
73static struct gpio_led_platform_data cerf_gpio_led_info = {
74 .leds = cerf_gpio_leds,
75 .num_leds = ARRAY_SIZE(cerf_gpio_leds),
76};
77
78static struct platform_device cerf_leds = {
79 .name = "leds-gpio",
80 .id = -1,
81 .dev = {
82 .platform_data = &cerf_gpio_led_info,
83 }
84};
85
86
87static struct platform_device *cerf_devices[] __initdata = { 50static struct platform_device *cerf_devices[] __initdata = {
88 &cerfuart2_device, 51 &cerfuart2_device,
89 &cerf_leds,
90}; 52};
91 53
92#ifdef CONFIG_SA1100_CERF_FLASH_32MB 54#ifdef CONFIG_SA1100_CERF_FLASH_32MB
@@ -125,8 +87,11 @@ static struct flash_platform_data cerf_flash_data = {
125 .nr_parts = ARRAY_SIZE(cerf_partitions), 87 .nr_parts = ARRAY_SIZE(cerf_partitions),
126}; 88};
127 89
128static struct resource cerf_flash_resource = 90static struct resource cerf_flash_resource = {
129 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); 91 .start = SA1100_CS0_PHYS,
92 .end = SA1100_CS0_PHYS + SZ_32M - 1,
93 .flags = IORESOURCE_MEM,
94};
130 95
131static void __init cerf_init_irq(void) 96static void __init cerf_init_irq(void)
132{ 97{
@@ -163,7 +128,6 @@ static struct mcp_plat_data cerf_mcp_data = {
163 128
164static void __init cerf_init(void) 129static void __init cerf_init(void)
165{ 130{
166 sa11x0_ppc_configure_mcp();
167 platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices)); 131 platform_add_devices(cerf_devices, ARRAY_SIZE(cerf_devices));
168 sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1); 132 sa11x0_register_mtd(&cerf_flash_data, &cerf_flash_resource, 1);
169 sa11x0_register_mcp(&cerf_mcp_data); 133 sa11x0_register_mcp(&cerf_mcp_data);
@@ -172,10 +136,7 @@ static void __init cerf_init(void)
172MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube") 136MACHINE_START(CERF, "Intrinsyc CerfBoard/CerfCube")
173 /* Maintainer: support@intrinsyc.com */ 137 /* Maintainer: support@intrinsyc.com */
174 .map_io = cerf_map_io, 138 .map_io = cerf_map_io,
175 .nr_irqs = SA1100_NR_IRQS,
176 .init_irq = cerf_init_irq, 139 .init_irq = cerf_init_irq,
177 .timer = &sa1100_timer, 140 .timer = &sa1100_timer,
178 .init_machine = cerf_init, 141 .init_machine = cerf_init,
179 .init_late = sa11x0_init_late,
180 .restart = sa11x0_restart,
181MACHINE_END 142MACHINE_END
diff --git a/arch/arm/mach-sa1100/clock.c b/arch/arm/mach-sa1100/clock.c
index 172ebd0ee0a..dab3c6347a8 100644
--- a/arch/arm/mach-sa1100/clock.c
+++ b/arch/arm/mach-sa1100/clock.c
@@ -11,29 +11,17 @@
11#include <linux/clk.h> 11#include <linux/clk.h>
12#include <linux/spinlock.h> 12#include <linux/spinlock.h>
13#include <linux/mutex.h> 13#include <linux/mutex.h>
14#include <linux/io.h>
15#include <linux/clkdev.h>
16 14
17#include <mach/hardware.h> 15#include <mach/hardware.h>
18 16
19struct clkops { 17/*
20 void (*enable)(struct clk *); 18 * Very simple clock implementation - we only have one clock to deal with.
21 void (*disable)(struct clk *); 19 */
22};
23
24struct clk { 20struct clk {
25 const struct clkops *ops;
26 unsigned int enabled; 21 unsigned int enabled;
27}; 22};
28 23
29#define DEFINE_CLK(_name, _ops) \ 24static void clk_gpio27_enable(void)
30struct clk clk_##_name = { \
31 .ops = _ops, \
32 }
33
34static DEFINE_SPINLOCK(clocks_lock);
35
36static void clk_gpio27_enable(struct clk *clk)
37{ 25{
38 /* 26 /*
39 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111: 27 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
@@ -44,24 +32,38 @@ static void clk_gpio27_enable(struct clk *clk)
44 TUCR = TUCR_3_6864MHz; 32 TUCR = TUCR_3_6864MHz;
45} 33}
46 34
47static void clk_gpio27_disable(struct clk *clk) 35static void clk_gpio27_disable(void)
48{ 36{
49 TUCR = 0; 37 TUCR = 0;
50 GPDR &= ~GPIO_32_768kHz; 38 GPDR &= ~GPIO_32_768kHz;
51 GAFR &= ~GPIO_32_768kHz; 39 GAFR &= ~GPIO_32_768kHz;
52} 40}
53 41
42static struct clk clk_gpio27;
43
44static DEFINE_SPINLOCK(clocks_lock);
45
46struct clk *clk_get(struct device *dev, const char *id)
47{
48 const char *devname = dev_name(dev);
49
50 return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27;
51}
52EXPORT_SYMBOL(clk_get);
53
54void clk_put(struct clk *clk)
55{
56}
57EXPORT_SYMBOL(clk_put);
58
54int clk_enable(struct clk *clk) 59int clk_enable(struct clk *clk)
55{ 60{
56 unsigned long flags; 61 unsigned long flags;
57 62
58 if (clk) { 63 spin_lock_irqsave(&clocks_lock, flags);
59 spin_lock_irqsave(&clocks_lock, flags); 64 if (clk->enabled++ == 0)
60 if (clk->enabled++ == 0) 65 clk_gpio27_enable();
61 clk->ops->enable(clk); 66 spin_unlock_irqrestore(&clocks_lock, flags);
62 spin_unlock_irqrestore(&clocks_lock, flags);
63 }
64
65 return 0; 67 return 0;
66} 68}
67EXPORT_SYMBOL(clk_enable); 69EXPORT_SYMBOL(clk_enable);
@@ -70,31 +72,17 @@ void clk_disable(struct clk *clk)
70{ 72{
71 unsigned long flags; 73 unsigned long flags;
72 74
73 if (clk) { 75 WARN_ON(clk->enabled == 0);
74 WARN_ON(clk->enabled == 0); 76
75 spin_lock_irqsave(&clocks_lock, flags); 77 spin_lock_irqsave(&clocks_lock, flags);
76 if (--clk->enabled == 0) 78 if (--clk->enabled == 0)
77 clk->ops->disable(clk); 79 clk_gpio27_disable();
78 spin_unlock_irqrestore(&clocks_lock, flags); 80 spin_unlock_irqrestore(&clocks_lock, flags);
79 }
80} 81}
81EXPORT_SYMBOL(clk_disable); 82EXPORT_SYMBOL(clk_disable);
82 83
83const struct clkops clk_gpio27_ops = { 84unsigned long clk_get_rate(struct clk *clk)
84 .enable = clk_gpio27_enable,
85 .disable = clk_gpio27_disable,
86};
87
88static DEFINE_CLK(gpio27, &clk_gpio27_ops);
89
90static struct clk_lookup sa11xx_clkregs[] = {
91 CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27),
92 CLKDEV_INIT("sa1100-rtc", NULL, NULL),
93};
94
95static int __init sa11xx_clk_init(void)
96{ 85{
97 clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs)); 86 return 3686400;
98 return 0;
99} 87}
100core_initcall(sa11xx_clk_init); 88EXPORT_SYMBOL(clk_get_rate);
diff --git a/arch/arm/mach-sa1100/collie.c b/arch/arm/mach-sa1100/collie.c
index 45f424f5fca..bd3e1bfdd6a 100644
--- a/arch/arm/mach-sa1100/collie.c
+++ b/arch/arm/mach-sa1100/collie.c
@@ -21,37 +21,37 @@
21#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <linux/tty.h> 22#include <linux/tty.h>
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/platform_data/sa11x0-serial.h>
25#include <linux/platform_device.h> 24#include <linux/platform_device.h>
26#include <linux/mfd/ucb1x00.h>
27#include <linux/mtd/mtd.h> 25#include <linux/mtd/mtd.h>
28#include <linux/mtd/partitions.h> 26#include <linux/mtd/partitions.h>
29#include <linux/timer.h> 27#include <linux/timer.h>
30#include <linux/gpio.h> 28#include <linux/gpio.h>
31#include <linux/pda_power.h> 29#include <linux/pda_power.h>
32 30
33#include <video/sa1100fb.h>
34
35#include <mach/hardware.h> 31#include <mach/hardware.h>
36#include <asm/mach-types.h> 32#include <asm/mach-types.h>
37#include <asm/page.h> 33#include <asm/irq.h>
38#include <asm/setup.h> 34#include <asm/setup.h>
39#include <mach/collie.h> 35#include <mach/collie.h>
40 36
41#include <asm/mach/arch.h> 37#include <asm/mach/arch.h>
42#include <asm/mach/flash.h> 38#include <asm/mach/flash.h>
43#include <asm/mach/map.h> 39#include <asm/mach/map.h>
40#include <asm/mach/serial_sa1100.h>
44 41
45#include <asm/hardware/scoop.h> 42#include <asm/hardware/scoop.h>
46#include <asm/mach/sharpsl_param.h> 43#include <asm/mach/sharpsl_param.h>
47#include <asm/hardware/locomo.h> 44#include <asm/hardware/locomo.h>
48#include <linux/platform_data/mfd-mcp-sa11x0.h> 45#include <mach/mcp.h>
49#include <mach/irqs.h>
50 46
51#include "generic.h" 47#include "generic.h"
52 48
53static struct resource collie_scoop_resources[] = { 49static struct resource collie_scoop_resources[] = {
54 [0] = DEFINE_RES_MEM(0x40800000, SZ_4K), 50 [0] = {
51 .start = 0x40800000,
52 .end = 0x40800fff,
53 .flags = IORESOURCE_MEM,
54 },
55}; 55};
56 56
57static struct scoop_config collie_scoop_setup = { 57static struct scoop_config collie_scoop_setup = {
@@ -84,14 +84,10 @@ static struct scoop_pcmcia_config collie_pcmcia_config = {
84 .num_devs = 1, 84 .num_devs = 1,
85}; 85};
86 86
87static struct ucb1x00_plat_data collie_ucb1x00_data = {
88 .gpio_base = COLLIE_TC35143_GPIO_BASE,
89};
90
91static struct mcp_plat_data collie_mcp_data = { 87static struct mcp_plat_data collie_mcp_data = {
92 .mccr0 = MCCR0_ADM | MCCR0_ExtClk, 88 .mccr0 = MCCR0_ADM | MCCR0_ExtClk,
93 .sclk_rate = 9216000, 89 .sclk_rate = 9216000,
94 .codec_pdata = &collie_ucb1x00_data, 90 .gpio_base = COLLIE_TC35143_GPIO_BASE,
95}; 91};
96 92
97/* 93/*
@@ -141,6 +137,8 @@ static struct pda_power_pdata collie_power_data = {
141static struct resource collie_power_resource[] = { 137static struct resource collie_power_resource[] = {
142 { 138 {
143 .name = "ac", 139 .name = "ac",
140 .start = gpio_to_irq(COLLIE_GPIO_AC_IN),
141 .end = gpio_to_irq(COLLIE_GPIO_AC_IN),
144 .flags = IORESOURCE_IRQ | 142 .flags = IORESOURCE_IRQ |
145 IORESOURCE_IRQ_HIGHEDGE | 143 IORESOURCE_IRQ_HIGHEDGE |
146 IORESOURCE_IRQ_LOWEDGE, 144 IORESOURCE_IRQ_LOWEDGE,
@@ -224,8 +222,16 @@ device_initcall(collie_uart_init);
224 222
225 223
226static struct resource locomo_resources[] = { 224static struct resource locomo_resources[] = {
227 [0] = DEFINE_RES_MEM(0x40000000, SZ_8K), 225 [0] = {
228 [1] = DEFINE_RES_IRQ(IRQ_GPIO25), 226 .start = 0x40000000,
227 .end = 0x40001fff,
228 .flags = IORESOURCE_MEM,
229 },
230 [1] = {
231 .start = IRQ_GPIO25,
232 .end = IRQ_GPIO25,
233 .flags = IORESOURCE_IRQ,
234 },
229}; 235};
230 236
231static struct locomo_platform_data locomo_info = { 237static struct locomo_platform_data locomo_info = {
@@ -298,25 +304,11 @@ static struct flash_platform_data collie_flash_data = {
298}; 304};
299 305
300static struct resource collie_flash_resources[] = { 306static struct resource collie_flash_resources[] = {
301 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M), 307 {
302}; 308 .start = SA1100_CS0_PHYS,
303 309 .end = SA1100_CS0_PHYS + SZ_32M - 1,
304static struct sa1100fb_mach_info collie_lcd_info = { 310 .flags = IORESOURCE_MEM,
305 .pixclock = 171521, .bpp = 16, 311 }
306 .xres = 320, .yres = 240,
307
308 .hsync_len = 5, .vsync_len = 1,
309 .left_margin = 11, .upper_margin = 2,
310 .right_margin = 30, .lower_margin = 0,
311
312 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
313
314 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
315 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
316
317#ifdef CONFIG_BACKLIGHT_LOCOMO
318 .lcd_power = locomolcd_power
319#endif
320}; 312};
321 313
322static void __init collie_init(void) 314static void __init collie_init(void)
@@ -348,11 +340,6 @@ static void __init collie_init(void)
348 340
349 GPSR |= _COLLIE_GPIO_UCB1x00_RESET; 341 GPSR |= _COLLIE_GPIO_UCB1x00_RESET;
350 342
351 collie_power_resource[0].start = gpio_to_irq(COLLIE_GPIO_AC_IN);
352 collie_power_resource[0].end = gpio_to_irq(COLLIE_GPIO_AC_IN);
353
354 sa11x0_ppc_configure_mcp();
355
356 343
357 platform_scoop_config = &collie_pcmcia_config; 344 platform_scoop_config = &collie_pcmcia_config;
358 345
@@ -361,7 +348,6 @@ static void __init collie_init(void)
361 printk(KERN_WARNING "collie: Unable to register LoCoMo device\n"); 348 printk(KERN_WARNING "collie: Unable to register LoCoMo device\n");
362 } 349 }
363 350
364 sa11x0_register_lcd(&collie_lcd_info);
365 sa11x0_register_mtd(&collie_flash_data, collie_flash_resources, 351 sa11x0_register_mtd(&collie_flash_data, collie_flash_resources,
366 ARRAY_SIZE(collie_flash_resources)); 352 ARRAY_SIZE(collie_flash_resources));
367 sa11x0_register_mcp(&collie_mcp_data); 353 sa11x0_register_mcp(&collie_mcp_data);
@@ -397,10 +383,7 @@ static void __init collie_map_io(void)
397 383
398MACHINE_START(COLLIE, "Sharp-Collie") 384MACHINE_START(COLLIE, "Sharp-Collie")
399 .map_io = collie_map_io, 385 .map_io = collie_map_io,
400 .nr_irqs = SA1100_NR_IRQS,
401 .init_irq = sa1100_init_irq, 386 .init_irq = sa1100_init_irq,
402 .timer = &sa1100_timer, 387 .timer = &sa1100_timer,
403 .init_machine = collie_init, 388 .init_machine = collie_init,
404 .init_late = sa11x0_init_late,
405 .restart = sa11x0_restart,
406MACHINE_END 389MACHINE_END
diff --git a/arch/arm/mach-sa1100/cpu-sa1100.c b/arch/arm/mach-sa1100/cpu-sa1100.c
index e8f4d1e1923..aaa8acf76b7 100644
--- a/arch/arm/mach-sa1100/cpu-sa1100.c
+++ b/arch/arm/mach-sa1100/cpu-sa1100.c
@@ -87,7 +87,6 @@
87#include <linux/types.h> 87#include <linux/types.h>
88#include <linux/init.h> 88#include <linux/init.h>
89#include <linux/cpufreq.h> 89#include <linux/cpufreq.h>
90#include <linux/io.h>
91 90
92#include <asm/cputype.h> 91#include <asm/cputype.h>
93 92
@@ -229,7 +228,7 @@ static int __init sa1100_cpu_init(struct cpufreq_policy *policy)
229 return 0; 228 return 0;
230} 229}
231 230
232static struct cpufreq_driver sa1100_driver __refdata = { 231static struct cpufreq_driver sa1100_driver = {
233 .flags = CPUFREQ_STICKY, 232 .flags = CPUFREQ_STICKY,
234 .verify = sa11x0_verify_speed, 233 .verify = sa11x0_verify_speed,
235 .target = sa1100_target, 234 .target = sa1100_target,
diff --git a/arch/arm/mach-sa1100/cpu-sa1110.c b/arch/arm/mach-sa1100/cpu-sa1110.c
index 48c45b0c92b..675bf8ef97e 100644
--- a/arch/arm/mach-sa1100/cpu-sa1110.c
+++ b/arch/arm/mach-sa1100/cpu-sa1110.c
@@ -19,7 +19,6 @@
19#include <linux/cpufreq.h> 19#include <linux/cpufreq.h>
20#include <linux/delay.h> 20#include <linux/delay.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/kernel.h> 22#include <linux/kernel.h>
24#include <linux/moduleparam.h> 23#include <linux/moduleparam.h>
25#include <linux/types.h> 24#include <linux/types.h>
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 9db3e98e8b8..e21f3470eec 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -9,27 +9,22 @@
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12#include <linux/gpio.h>
13#include <linux/module.h> 12#include <linux/module.h>
14#include <linux/kernel.h> 13#include <linux/kernel.h>
15#include <linux/init.h> 14#include <linux/init.h>
16#include <linux/delay.h> 15#include <linux/delay.h>
17#include <linux/dma-mapping.h>
18#include <linux/pm.h> 16#include <linux/pm.h>
19#include <linux/cpufreq.h> 17#include <linux/cpufreq.h>
20#include <linux/ioport.h> 18#include <linux/ioport.h>
21#include <linux/platform_device.h> 19#include <linux/platform_device.h>
22 20
23#include <video/sa1100fb.h>
24
25#include <asm/div64.h> 21#include <asm/div64.h>
22#include <mach/hardware.h>
23#include <asm/system.h>
26#include <asm/mach/map.h> 24#include <asm/mach/map.h>
27#include <asm/mach/flash.h> 25#include <asm/mach/flash.h>
28#include <asm/irq.h> 26#include <asm/irq.h>
29#include <asm/system_misc.h> 27#include <asm/gpio.h>
30
31#include <mach/hardware.h>
32#include <mach/irqs.h>
33 28
34#include "generic.h" 29#include "generic.h"
35 30
@@ -131,17 +126,6 @@ static void sa1100_power_off(void)
131 PMCR = PMCR_SF; 126 PMCR = PMCR_SF;
132} 127}
133 128
134void sa11x0_restart(char mode, const char *cmd)
135{
136 if (mode == 's') {
137 /* Jump into ROM at address 0 */
138 soft_restart(0);
139 } else {
140 /* Use on-chip reset capability */
141 RSRR = RSRR_SWR;
142 }
143}
144
145static void sa11x0_register_device(struct platform_device *dev, void *data) 129static void sa11x0_register_device(struct platform_device *dev, void *data)
146{ 130{
147 int err; 131 int err;
@@ -154,8 +138,16 @@ static void sa11x0_register_device(struct platform_device *dev, void *data)
154 138
155 139
156static struct resource sa11x0udc_resources[] = { 140static struct resource sa11x0udc_resources[] = {
157 [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K), 141 [0] = {
158 [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC), 142 .start = __PREG(Ser0UDCCR),
143 .end = __PREG(Ser0UDCCR) + 0xffff,
144 .flags = IORESOURCE_MEM,
145 },
146 [1] = {
147 .start = IRQ_Ser0UDC,
148 .end = IRQ_Ser0UDC,
149 .flags = IORESOURCE_IRQ,
150 },
159}; 151};
160 152
161static u64 sa11x0udc_dma_mask = 0xffffffffUL; 153static u64 sa11x0udc_dma_mask = 0xffffffffUL;
@@ -172,8 +164,16 @@ static struct platform_device sa11x0udc_device = {
172}; 164};
173 165
174static struct resource sa11x0uart1_resources[] = { 166static struct resource sa11x0uart1_resources[] = {
175 [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K), 167 [0] = {
176 [1] = DEFINE_RES_IRQ(IRQ_Ser1UART), 168 .start = __PREG(Ser1UTCR0),
169 .end = __PREG(Ser1UTCR0) + 0xffff,
170 .flags = IORESOURCE_MEM,
171 },
172 [1] = {
173 .start = IRQ_Ser1UART,
174 .end = IRQ_Ser1UART,
175 .flags = IORESOURCE_IRQ,
176 },
177}; 177};
178 178
179static struct platform_device sa11x0uart1_device = { 179static struct platform_device sa11x0uart1_device = {
@@ -184,8 +184,16 @@ static struct platform_device sa11x0uart1_device = {
184}; 184};
185 185
186static struct resource sa11x0uart3_resources[] = { 186static struct resource sa11x0uart3_resources[] = {
187 [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K), 187 [0] = {
188 [1] = DEFINE_RES_IRQ(IRQ_Ser3UART), 188 .start = __PREG(Ser3UTCR0),
189 .end = __PREG(Ser3UTCR0) + 0xffff,
190 .flags = IORESOURCE_MEM,
191 },
192 [1] = {
193 .start = IRQ_Ser3UART,
194 .end = IRQ_Ser3UART,
195 .flags = IORESOURCE_IRQ,
196 },
189}; 197};
190 198
191static struct platform_device sa11x0uart3_device = { 199static struct platform_device sa11x0uart3_device = {
@@ -196,9 +204,16 @@ static struct platform_device sa11x0uart3_device = {
196}; 204};
197 205
198static struct resource sa11x0mcp_resources[] = { 206static struct resource sa11x0mcp_resources[] = {
199 [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K), 207 [0] = {
200 [1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4), 208 .start = __PREG(Ser4MCCR0),
201 [2] = DEFINE_RES_IRQ(IRQ_Ser4MCP), 209 .end = __PREG(Ser4MCCR0) + 0xffff,
210 .flags = IORESOURCE_MEM,
211 },
212 [1] = {
213 .start = IRQ_Ser4MCP,
214 .end = IRQ_Ser4MCP,
215 .flags = IORESOURCE_IRQ,
216 },
202}; 217};
203 218
204static u64 sa11x0mcp_dma_mask = 0xffffffffUL; 219static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
@@ -214,24 +229,22 @@ static struct platform_device sa11x0mcp_device = {
214 .resource = sa11x0mcp_resources, 229 .resource = sa11x0mcp_resources,
215}; 230};
216 231
217void __init sa11x0_ppc_configure_mcp(void)
218{
219 /* Setup the PPC unit for the MCP */
220 PPDR &= ~PPC_RXD4;
221 PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
222 PSDR |= PPC_RXD4;
223 PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
224 PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
225}
226
227void sa11x0_register_mcp(struct mcp_plat_data *data) 232void sa11x0_register_mcp(struct mcp_plat_data *data)
228{ 233{
229 sa11x0_register_device(&sa11x0mcp_device, data); 234 sa11x0_register_device(&sa11x0mcp_device, data);
230} 235}
231 236
232static struct resource sa11x0ssp_resources[] = { 237static struct resource sa11x0ssp_resources[] = {
233 [0] = DEFINE_RES_MEM(0x80070000, SZ_64K), 238 [0] = {
234 [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP), 239 .start = 0x80070000,
240 .end = 0x8007ffff,
241 .flags = IORESOURCE_MEM,
242 },
243 [1] = {
244 .start = IRQ_Ser4SSP,
245 .end = IRQ_Ser4SSP,
246 .flags = IORESOURCE_IRQ,
247 },
235}; 248};
236 249
237static u64 sa11x0ssp_dma_mask = 0xffffffffUL; 250static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
@@ -248,8 +261,16 @@ static struct platform_device sa11x0ssp_device = {
248}; 261};
249 262
250static struct resource sa11x0fb_resources[] = { 263static struct resource sa11x0fb_resources[] = {
251 [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K), 264 [0] = {
252 [1] = DEFINE_RES_IRQ(IRQ_LCD), 265 .start = 0xb0100000,
266 .end = 0xb010ffff,
267 .flags = IORESOURCE_MEM,
268 },
269 [1] = {
270 .start = IRQ_LCD,
271 .end = IRQ_LCD,
272 .flags = IORESOURCE_IRQ,
273 },
253}; 274};
254 275
255static struct platform_device sa11x0fb_device = { 276static struct platform_device sa11x0fb_device = {
@@ -262,11 +283,6 @@ static struct platform_device sa11x0fb_device = {
262 .resource = sa11x0fb_resources, 283 .resource = sa11x0fb_resources,
263}; 284};
264 285
265void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
266{
267 sa11x0_register_device(&sa11x0fb_device, inf);
268}
269
270static struct platform_device sa11x0pcmcia_device = { 286static struct platform_device sa11x0pcmcia_device = {
271 .name = "sa11x0-pcmcia", 287 .name = "sa11x0-pcmcia",
272 .id = -1, 288 .id = -1,
@@ -287,10 +303,23 @@ void sa11x0_register_mtd(struct flash_platform_data *flash,
287} 303}
288 304
289static struct resource sa11x0ir_resources[] = { 305static struct resource sa11x0ir_resources[] = {
290 DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24), 306 {
291 DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c), 307 .start = __PREG(Ser2UTCR0),
292 DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04), 308 .end = __PREG(Ser2UTCR0) + 0x24 - 1,
293 DEFINE_RES_IRQ(IRQ_Ser2ICP), 309 .flags = IORESOURCE_MEM,
310 }, {
311 .start = __PREG(Ser2HSCR0),
312 .end = __PREG(Ser2HSCR0) + 0x1c - 1,
313 .flags = IORESOURCE_MEM,
314 }, {
315 .start = __PREG(Ser2HSCR2),
316 .end = __PREG(Ser2HSCR2) + 0x04 - 1,
317 .flags = IORESOURCE_MEM,
318 }, {
319 .start = IRQ_Ser2ICP,
320 .end = IRQ_Ser2ICP,
321 .flags = IORESOURCE_IRQ,
322 }
294}; 323};
295 324
296static struct platform_device sa11x0ir_device = { 325static struct platform_device sa11x0ir_device = {
@@ -305,40 +334,9 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
305 sa11x0_register_device(&sa11x0ir_device, irda); 334 sa11x0_register_device(&sa11x0ir_device, irda);
306} 335}
307 336
308static struct resource sa1100_rtc_resources[] = {
309 DEFINE_RES_MEM(0x90010000, 0x40),
310 DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
311 DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
312};
313
314static struct platform_device sa11x0rtc_device = { 337static struct platform_device sa11x0rtc_device = {
315 .name = "sa1100-rtc", 338 .name = "sa1100-rtc",
316 .id = -1, 339 .id = -1,
317 .num_resources = ARRAY_SIZE(sa1100_rtc_resources),
318 .resource = sa1100_rtc_resources,
319};
320
321static struct resource sa11x0dma_resources[] = {
322 DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
323 DEFINE_RES_IRQ(IRQ_DMA0),
324 DEFINE_RES_IRQ(IRQ_DMA1),
325 DEFINE_RES_IRQ(IRQ_DMA2),
326 DEFINE_RES_IRQ(IRQ_DMA3),
327 DEFINE_RES_IRQ(IRQ_DMA4),
328 DEFINE_RES_IRQ(IRQ_DMA5),
329};
330
331static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
332
333static struct platform_device sa11x0dma_device = {
334 .name = "sa11x0-dma",
335 .id = -1,
336 .dev = {
337 .dma_mask = &sa11x0dma_dma_mask,
338 .coherent_dma_mask = 0xffffffff,
339 },
340 .num_resources = ARRAY_SIZE(sa11x0dma_resources),
341 .resource = sa11x0dma_resources,
342}; 340};
343 341
344static struct platform_device *sa11x0_devices[] __initdata = { 342static struct platform_device *sa11x0_devices[] __initdata = {
@@ -347,8 +345,8 @@ static struct platform_device *sa11x0_devices[] __initdata = {
347 &sa11x0uart3_device, 345 &sa11x0uart3_device,
348 &sa11x0ssp_device, 346 &sa11x0ssp_device,
349 &sa11x0pcmcia_device, 347 &sa11x0pcmcia_device,
348 &sa11x0fb_device,
350 &sa11x0rtc_device, 349 &sa11x0rtc_device,
351 &sa11x0dma_device,
352}; 350};
353 351
354static int __init sa1100_init(void) 352static int __init sa1100_init(void)
@@ -359,10 +357,12 @@ static int __init sa1100_init(void)
359 357
360arch_initcall(sa1100_init); 358arch_initcall(sa1100_init);
361 359
362void __init sa11x0_init_late(void) 360void (*sa1100fb_backlight_power)(int on);
363{ 361void (*sa1100fb_lcd_power)(int on);
364 sa11x0_pm_init(); 362
365} 363EXPORT_SYMBOL(sa1100fb_backlight_power);
364EXPORT_SYMBOL(sa1100fb_lcd_power);
365
366 366
367/* 367/*
368 * Common I/O mapping: 368 * Common I/O mapping:
@@ -417,7 +417,7 @@ void __init sa1100_map_io(void)
417 * the MBGNT signal false to ensure the SA1111 doesn't own the 417 * the MBGNT signal false to ensure the SA1111 doesn't own the
418 * SDRAM bus. 418 * SDRAM bus.
419 */ 419 */
420void sa1110_mb_disable(void) 420void __init sa1110_mb_disable(void)
421{ 421{
422 unsigned long flags; 422 unsigned long flags;
423 423
@@ -436,7 +436,7 @@ void sa1110_mb_disable(void)
436 * If the system is going to use the SA-1111 DMA engines, set up 436 * If the system is going to use the SA-1111 DMA engines, set up
437 * the memory bus request/grant pins. 437 * the memory bus request/grant pins.
438 */ 438 */
439void sa1110_mb_enable(void) 439void __devinit sa1110_mb_enable(void)
440{ 440{
441 unsigned long flags; 441 unsigned long flags;
442 442
diff --git a/arch/arm/mach-sa1100/generic.h b/arch/arm/mach-sa1100/generic.h
index a5b7c13da3e..b7a9a601c2d 100644
--- a/arch/arm/mach-sa1100/generic.h
+++ b/arch/arm/mach-sa1100/generic.h
@@ -10,13 +10,14 @@ extern struct sys_timer sa1100_timer;
10extern void __init sa1100_map_io(void); 10extern void __init sa1100_map_io(void);
11extern void __init sa1100_init_irq(void); 11extern void __init sa1100_init_irq(void);
12extern void __init sa1100_init_gpio(void); 12extern void __init sa1100_init_gpio(void);
13extern void sa11x0_restart(char, const char *);
14extern void sa11x0_init_late(void);
15 13
16#define SET_BANK(__nr,__start,__size) \ 14#define SET_BANK(__nr,__start,__size) \
17 mi->bank[__nr].start = (__start), \ 15 mi->bank[__nr].start = (__start), \
18 mi->bank[__nr].size = (__size) 16 mi->bank[__nr].size = (__size)
19 17
18extern void (*sa1100fb_backlight_power)(int on);
19extern void (*sa1100fb_lcd_power)(int on);
20
20extern void sa1110_mb_enable(void); 21extern void sa1110_mb_enable(void);
21extern void sa1110_mb_disable(void); 22extern void sa1110_mb_disable(void);
22 23
@@ -37,14 +38,4 @@ struct irda_platform_data;
37void sa11x0_register_irda(struct irda_platform_data *irda); 38void sa11x0_register_irda(struct irda_platform_data *irda);
38 39
39struct mcp_plat_data; 40struct mcp_plat_data;
40void sa11x0_ppc_configure_mcp(void);
41void sa11x0_register_mcp(struct mcp_plat_data *data); 41void sa11x0_register_mcp(struct mcp_plat_data *data);
42
43struct sa1100fb_mach_info;
44void sa11x0_register_lcd(struct sa1100fb_mach_info *inf);
45
46#ifdef CONFIG_PM
47int sa11x0_pm_init(void);
48#else
49static inline int sa11x0_pm_init(void) { return 0; }
50#endif
diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c
index e1571eab08a..03d7376cf8a 100644
--- a/arch/arm/mach-sa1100/h3100.c
+++ b/arch/arm/mach-sa1100/h3100.c
@@ -14,14 +14,11 @@
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16 16
17#include <video/sa1100fb.h>
18
19#include <asm/mach-types.h> 17#include <asm/mach-types.h>
20#include <asm/mach/arch.h> 18#include <asm/mach/arch.h>
21#include <asm/mach/irda.h> 19#include <asm/mach/irda.h>
22 20
23#include <mach/h3xxx.h> 21#include <mach/h3xxx.h>
24#include <mach/irqs.h>
25 22
26#include "generic.h" 23#include "generic.h"
27 24
@@ -39,28 +36,13 @@ static void h3100_lcd_power(int enable)
39 } 36 }
40} 37}
41 38
42static struct sa1100fb_mach_info h3100_lcd_info = {
43 .pixclock = 406977, .bpp = 4,
44 .xres = 320, .yres = 240,
45
46 .hsync_len = 26, .vsync_len = 41,
47 .left_margin = 4, .upper_margin = 0,
48 .right_margin = 4, .lower_margin = 0,
49
50 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
51 .cmap_greyscale = 1,
52 .cmap_inverse = 1,
53
54 .lccr0 = LCCR0_Mono | LCCR0_4PixMono | LCCR0_Sngl | LCCR0_Pas,
55 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
56
57 .lcd_power = h3100_lcd_power,
58};
59 39
60static void __init h3100_map_io(void) 40static void __init h3100_map_io(void)
61{ 41{
62 h3xxx_map_io(); 42 h3xxx_map_io();
63 43
44 sa1100fb_lcd_power = h3100_lcd_power;
45
64 /* Older bootldrs put GPIO2-9 in alternate mode on the 46 /* Older bootldrs put GPIO2-9 in alternate mode on the
65 assumption that they are used for video */ 47 assumption that they are used for video */
66 GAFR &= ~0x000001fb; 48 GAFR &= ~0x000001fb;
@@ -98,19 +80,14 @@ static void __init h3100_mach_init(void)
98{ 80{
99 h3xxx_init_gpio(h3100_default_gpio, ARRAY_SIZE(h3100_default_gpio)); 81 h3xxx_init_gpio(h3100_default_gpio, ARRAY_SIZE(h3100_default_gpio));
100 h3xxx_mach_init(); 82 h3xxx_mach_init();
101
102 sa11x0_register_lcd(&h3100_lcd_info);
103 sa11x0_register_irda(&h3100_irda_data); 83 sa11x0_register_irda(&h3100_irda_data);
104} 84}
105 85
106MACHINE_START(H3100, "Compaq iPAQ H3100") 86MACHINE_START(H3100, "Compaq iPAQ H3100")
107 .atag_offset = 0x100, 87 .boot_params = 0xc0000100,
108 .map_io = h3100_map_io, 88 .map_io = h3100_map_io,
109 .nr_irqs = SA1100_NR_IRQS,
110 .init_irq = sa1100_init_irq, 89 .init_irq = sa1100_init_irq,
111 .timer = &sa1100_timer, 90 .timer = &sa1100_timer,
112 .init_machine = h3100_mach_init, 91 .init_machine = h3100_mach_init,
113 .init_late = sa11x0_init_late,
114 .restart = sa11x0_restart,
115MACHINE_END 92MACHINE_END
116 93
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index ba7a2901ab8..965f64a836f 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -14,14 +14,11 @@
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/gpio.h> 15#include <linux/gpio.h>
16 16
17#include <video/sa1100fb.h>
18
19#include <asm/mach-types.h> 17#include <asm/mach-types.h>
20#include <asm/mach/arch.h> 18#include <asm/mach/arch.h>
21#include <asm/mach/irda.h> 19#include <asm/mach/irda.h>
22 20
23#include <mach/h3xxx.h> 21#include <mach/h3xxx.h>
24#include <mach/irqs.h>
25 22
26#include "generic.h" 23#include "generic.h"
27 24
@@ -59,35 +56,11 @@ err2: gpio_free(H3XXX_EGPIO_LCD_ON);
59err1: return; 56err1: return;
60} 57}
61 58
62static const struct sa1100fb_rgb h3600_rgb_16 = {
63 .red = { .offset = 12, .length = 4, },
64 .green = { .offset = 7, .length = 4, },
65 .blue = { .offset = 1, .length = 4, },
66 .transp = { .offset = 0, .length = 0, },
67};
68
69static struct sa1100fb_mach_info h3600_lcd_info = {
70 .pixclock = 174757, .bpp = 16,
71 .xres = 320, .yres = 240,
72
73 .hsync_len = 3, .vsync_len = 3,
74 .left_margin = 12, .upper_margin = 10,
75 .right_margin = 17, .lower_margin = 1,
76
77 .cmap_static = 1,
78
79 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
80 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
81
82 .rgb[RGB_16] = &h3600_rgb_16,
83
84 .lcd_power = h3600_lcd_power,
85};
86
87
88static void __init h3600_map_io(void) 59static void __init h3600_map_io(void)
89{ 60{
90 h3xxx_map_io(); 61 h3xxx_map_io();
62
63 sa1100fb_lcd_power = h3600_lcd_power;
91} 64}
92 65
93/* 66/*
@@ -148,19 +121,14 @@ static void __init h3600_mach_init(void)
148{ 121{
149 h3xxx_init_gpio(h3600_default_gpio, ARRAY_SIZE(h3600_default_gpio)); 122 h3xxx_init_gpio(h3600_default_gpio, ARRAY_SIZE(h3600_default_gpio));
150 h3xxx_mach_init(); 123 h3xxx_mach_init();
151
152 sa11x0_register_lcd(&h3600_lcd_info);
153 sa11x0_register_irda(&h3600_irda_data); 124 sa11x0_register_irda(&h3600_irda_data);
154} 125}
155 126
156MACHINE_START(H3600, "Compaq iPAQ H3600") 127MACHINE_START(H3600, "Compaq iPAQ H3600")
157 .atag_offset = 0x100, 128 .boot_params = 0xc0000100,
158 .map_io = h3600_map_io, 129 .map_io = h3600_map_io,
159 .nr_irqs = SA1100_NR_IRQS,
160 .init_irq = sa1100_init_irq, 130 .init_irq = sa1100_init_irq,
161 .timer = &sa1100_timer, 131 .timer = &sa1100_timer,
162 .init_machine = h3600_mach_init, 132 .init_machine = h3600_mach_init,
163 .init_late = sa11x0_init_late,
164 .restart = sa11x0_restart,
165MACHINE_END 133MACHINE_END
166 134
diff --git a/arch/arm/mach-sa1100/h3xxx.c b/arch/arm/mach-sa1100/h3xxx.c
index f17e7382242..b0784c974c2 100644
--- a/arch/arm/mach-sa1100/h3xxx.c
+++ b/arch/arm/mach-sa1100/h3xxx.c
@@ -17,12 +17,12 @@
17#include <linux/mfd/htc-egpio.h> 17#include <linux/mfd/htc-egpio.h>
18#include <linux/mtd/mtd.h> 18#include <linux/mtd/mtd.h>
19#include <linux/mtd/partitions.h> 19#include <linux/mtd/partitions.h>
20#include <linux/platform_data/sa11x0-serial.h>
21#include <linux/platform_device.h> 20#include <linux/platform_device.h>
22#include <linux/serial_core.h> 21#include <linux/serial_core.h>
23 22
24#include <asm/mach/flash.h> 23#include <asm/mach/flash.h>
25#include <asm/mach/map.h> 24#include <asm/mach/map.h>
25#include <asm/mach/serial_sa1100.h>
26 26
27#include <mach/h3xxx.h> 27#include <mach/h3xxx.h>
28 28
@@ -109,8 +109,11 @@ static struct flash_platform_data h3xxx_flash_data = {
109 .nr_parts = ARRAY_SIZE(h3xxx_partitions), 109 .nr_parts = ARRAY_SIZE(h3xxx_partitions),
110}; 110};
111 111
112static struct resource h3xxx_flash_resource = 112static struct resource h3xxx_flash_resource = {
113 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); 113 .start = SA1100_CS0_PHYS,
114 .end = SA1100_CS0_PHYS + SZ_32M - 1,
115 .flags = IORESOURCE_MEM,
116};
114 117
115 118
116/* 119/*
@@ -183,7 +186,11 @@ static struct sa1100_port_fns h3xxx_port_fns __initdata = {
183 */ 186 */
184 187
185static struct resource egpio_resources[] = { 188static struct resource egpio_resources[] = {
186 [0] = DEFINE_RES_MEM(H3600_EGPIO_PHYS, 0x4), 189 [0] = {
190 .start = H3600_EGPIO_PHYS,
191 .end = H3600_EGPIO_PHYS + 0x4 - 1,
192 .flags = IORESOURCE_MEM,
193 },
187}; 194};
188 195
189static struct htc_egpio_chip egpio_chips[] = { 196static struct htc_egpio_chip egpio_chips[] = {
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index d005939c41f..db5e434a17d 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -18,27 +18,22 @@
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/errno.h> 19#include <linux/errno.h>
20#include <linux/cpufreq.h> 20#include <linux/cpufreq.h>
21#include <linux/platform_data/sa11x0-serial.h>
22#include <linux/serial_core.h> 21#include <linux/serial_core.h>
23#include <linux/mtd/mtd.h> 22#include <linux/mtd/mtd.h>
24#include <linux/mtd/partitions.h> 23#include <linux/mtd/partitions.h>
25#include <linux/tty.h>
26#include <linux/gpio.h>
27#include <linux/leds.h>
28#include <linux/platform_device.h>
29 24
25#include <mach/hardware.h>
30#include <asm/mach-types.h> 26#include <asm/mach-types.h>
31#include <asm/setup.h> 27#include <asm/setup.h>
32#include <asm/page.h> 28#include <asm/page.h>
33#include <asm/pgtable.h> 29#include <asm/pgtable.h>
30#include <asm/irq.h>
34 31
35#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
36#include <asm/mach/flash.h> 33#include <asm/mach/flash.h>
37#include <asm/mach/map.h> 34#include <asm/mach/map.h>
38#include <asm/mach/irq.h> 35#include <asm/mach/irq.h>
39 36#include <asm/mach/serial_sa1100.h>
40#include <mach/hardware.h>
41#include <mach/irqs.h>
42 37
43#include "generic.h" 38#include "generic.h"
44 39
@@ -184,40 +179,15 @@ static struct flash_platform_data hackkit_flash_data = {
184 .nr_parts = ARRAY_SIZE(hackkit_partitions), 179 .nr_parts = ARRAY_SIZE(hackkit_partitions),
185}; 180};
186 181
187static struct resource hackkit_flash_resource = 182static struct resource hackkit_flash_resource = {
188 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); 183 .start = SA1100_CS0_PHYS,
189 184 .end = SA1100_CS0_PHYS + SZ_32M,
190/* LEDs */ 185 .flags = IORESOURCE_MEM,
191struct gpio_led hackkit_gpio_leds[] = {
192 {
193 .name = "hackkit:red",
194 .default_trigger = "cpu0",
195 .gpio = 22,
196 },
197 {
198 .name = "hackkit:green",
199 .default_trigger = "heartbeat",
200 .gpio = 23,
201 },
202};
203
204static struct gpio_led_platform_data hackkit_gpio_led_info = {
205 .leds = hackkit_gpio_leds,
206 .num_leds = ARRAY_SIZE(hackkit_gpio_leds),
207};
208
209static struct platform_device hackkit_leds = {
210 .name = "leds-gpio",
211 .id = -1,
212 .dev = {
213 .platform_data = &hackkit_gpio_led_info,
214 }
215}; 186};
216 187
217static void __init hackkit_init(void) 188static void __init hackkit_init(void)
218{ 189{
219 sa11x0_register_mtd(&hackkit_flash_data, &hackkit_flash_resource, 1); 190 sa11x0_register_mtd(&hackkit_flash_data, &hackkit_flash_resource, 1);
220 platform_device_register(&hackkit_leds);
221} 191}
222 192
223/********************************************************************** 193/**********************************************************************
@@ -225,12 +195,9 @@ static void __init hackkit_init(void)
225 */ 195 */
226 196
227MACHINE_START(HACKKIT, "HackKit Cpu Board") 197MACHINE_START(HACKKIT, "HackKit Cpu Board")
228 .atag_offset = 0x100, 198 .boot_params = 0xc0000100,
229 .map_io = hackkit_map_io, 199 .map_io = hackkit_map_io,
230 .nr_irqs = SA1100_NR_IRQS,
231 .init_irq = sa1100_init_irq, 200 .init_irq = sa1100_init_irq,
232 .timer = &sa1100_timer, 201 .timer = &sa1100_timer,
233 .init_machine = hackkit_init, 202 .init_machine = hackkit_init,
234 .init_late = sa11x0_init_late,
235 .restart = sa11x0_restart,
236MACHINE_END 203MACHINE_END
diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index 0ac6cc08a19..bae8296f5db 100644
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -830,14 +830,14 @@
830 * (read/write). 830 * (read/write).
831 */ 831 */
832 832
833#define OSMR0 io_p2v(0x90000000) /* OS timer Match Reg. 0 */ 833#define OSMR0 __REG(0x90000000) /* OS timer Match Reg. 0 */
834#define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */ 834#define OSMR1 __REG(0x90000004) /* OS timer Match Reg. 1 */
835#define OSMR2 io_p2v(0x90000008) /* OS timer Match Reg. 2 */ 835#define OSMR2 __REG(0x90000008) /* OS timer Match Reg. 2 */
836#define OSMR3 io_p2v(0x9000000c) /* OS timer Match Reg. 3 */ 836#define OSMR3 __REG(0x9000000c) /* OS timer Match Reg. 3 */
837#define OSCR io_p2v(0x90000010) /* OS timer Counter Reg. */ 837#define OSCR __REG(0x90000010) /* OS timer Counter Reg. */
838#define OSSR io_p2v(0x90000014) /* OS timer Status Reg. */ 838#define OSSR __REG(0x90000014 ) /* OS timer Status Reg. */
839#define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */ 839#define OWER __REG(0x90000018 ) /* OS timer Watch-dog Enable Reg. */
840#define OIER io_p2v(0x9000001C) /* OS timer Interrupt Enable Reg. */ 840#define OIER __REG(0x9000001C ) /* OS timer Interrupt Enable Reg. */
841 841
842#define OSSR_M(Nb) /* Match detected [0..3] */ \ 842#define OSSR_M(Nb) /* Match detected [0..3] */ \
843 (0x00000001 << (Nb)) 843 (0x00000001 << (Nb))
@@ -1590,9 +1590,224 @@
1590 1590
1591/* 1591/*
1592 * Direct Memory Access (DMA) control registers 1592 * Direct Memory Access (DMA) control registers
1593 *
1594 * Registers
1595 * DDAR0 Direct Memory Access (DMA) Device Address Register
1596 * channel 0 (read/write).
1597 * DCSR0 Direct Memory Access (DMA) Control and Status
1598 * Register channel 0 (read/write).
1599 * DBSA0 Direct Memory Access (DMA) Buffer Start address
1600 * register A channel 0 (read/write).
1601 * DBTA0 Direct Memory Access (DMA) Buffer Transfer count
1602 * register A channel 0 (read/write).
1603 * DBSB0 Direct Memory Access (DMA) Buffer Start address
1604 * register B channel 0 (read/write).
1605 * DBTB0 Direct Memory Access (DMA) Buffer Transfer count
1606 * register B channel 0 (read/write).
1607 *
1608 * DDAR1 Direct Memory Access (DMA) Device Address Register
1609 * channel 1 (read/write).
1610 * DCSR1 Direct Memory Access (DMA) Control and Status
1611 * Register channel 1 (read/write).
1612 * DBSA1 Direct Memory Access (DMA) Buffer Start address
1613 * register A channel 1 (read/write).
1614 * DBTA1 Direct Memory Access (DMA) Buffer Transfer count
1615 * register A channel 1 (read/write).
1616 * DBSB1 Direct Memory Access (DMA) Buffer Start address
1617 * register B channel 1 (read/write).
1618 * DBTB1 Direct Memory Access (DMA) Buffer Transfer count
1619 * register B channel 1 (read/write).
1620 *
1621 * DDAR2 Direct Memory Access (DMA) Device Address Register
1622 * channel 2 (read/write).
1623 * DCSR2 Direct Memory Access (DMA) Control and Status
1624 * Register channel 2 (read/write).
1625 * DBSA2 Direct Memory Access (DMA) Buffer Start address
1626 * register A channel 2 (read/write).
1627 * DBTA2 Direct Memory Access (DMA) Buffer Transfer count
1628 * register A channel 2 (read/write).
1629 * DBSB2 Direct Memory Access (DMA) Buffer Start address
1630 * register B channel 2 (read/write).
1631 * DBTB2 Direct Memory Access (DMA) Buffer Transfer count
1632 * register B channel 2 (read/write).
1633 *
1634 * DDAR3 Direct Memory Access (DMA) Device Address Register
1635 * channel 3 (read/write).
1636 * DCSR3 Direct Memory Access (DMA) Control and Status
1637 * Register channel 3 (read/write).
1638 * DBSA3 Direct Memory Access (DMA) Buffer Start address
1639 * register A channel 3 (read/write).
1640 * DBTA3 Direct Memory Access (DMA) Buffer Transfer count
1641 * register A channel 3 (read/write).
1642 * DBSB3 Direct Memory Access (DMA) Buffer Start address
1643 * register B channel 3 (read/write).
1644 * DBTB3 Direct Memory Access (DMA) Buffer Transfer count
1645 * register B channel 3 (read/write).
1646 *
1647 * DDAR4 Direct Memory Access (DMA) Device Address Register
1648 * channel 4 (read/write).
1649 * DCSR4 Direct Memory Access (DMA) Control and Status
1650 * Register channel 4 (read/write).
1651 * DBSA4 Direct Memory Access (DMA) Buffer Start address
1652 * register A channel 4 (read/write).
1653 * DBTA4 Direct Memory Access (DMA) Buffer Transfer count
1654 * register A channel 4 (read/write).
1655 * DBSB4 Direct Memory Access (DMA) Buffer Start address
1656 * register B channel 4 (read/write).
1657 * DBTB4 Direct Memory Access (DMA) Buffer Transfer count
1658 * register B channel 4 (read/write).
1659 *
1660 * DDAR5 Direct Memory Access (DMA) Device Address Register
1661 * channel 5 (read/write).
1662 * DCSR5 Direct Memory Access (DMA) Control and Status
1663 * Register channel 5 (read/write).
1664 * DBSA5 Direct Memory Access (DMA) Buffer Start address
1665 * register A channel 5 (read/write).
1666 * DBTA5 Direct Memory Access (DMA) Buffer Transfer count
1667 * register A channel 5 (read/write).
1668 * DBSB5 Direct Memory Access (DMA) Buffer Start address
1669 * register B channel 5 (read/write).
1670 * DBTB5 Direct Memory Access (DMA) Buffer Transfer count
1671 * register B channel 5 (read/write).
1593 */ 1672 */
1594#define DMA_SIZE (6 * 0x20) 1673
1595#define DMA_PHYS 0xb0000000 1674#define DMASp 0x00000020 /* DMA control reg. Space [byte] */
1675
1676#define DDAR(Nb) __REG(0xB0000000 + (Nb)*DMASp) /* DMA Device Address Reg. channel [0..5] */
1677#define SetDCSR(Nb) __REG(0xB0000004 + (Nb)*DMASp) /* Set DMA Control & Status Reg. channel [0..5] (write) */
1678#define ClrDCSR(Nb) __REG(0xB0000008 + (Nb)*DMASp) /* Clear DMA Control & Status Reg. channel [0..5] (write) */
1679#define RdDCSR(Nb) __REG(0xB000000C + (Nb)*DMASp) /* Read DMA Control & Status Reg. channel [0..5] (read) */
1680#define DBSA(Nb) __REG(0xB0000010 + (Nb)*DMASp) /* DMA Buffer Start address reg. A channel [0..5] */
1681#define DBTA(Nb) __REG(0xB0000014 + (Nb)*DMASp) /* DMA Buffer Transfer count reg. A channel [0..5] */
1682#define DBSB(Nb) __REG(0xB0000018 + (Nb)*DMASp) /* DMA Buffer Start address reg. B channel [0..5] */
1683#define DBTB(Nb) __REG(0xB000001C + (Nb)*DMASp) /* DMA Buffer Transfer count reg. B channel [0..5] */
1684
1685#define DDAR_RW 0x00000001 /* device data Read/Write */
1686#define DDAR_DevWr (DDAR_RW*0) /* Device data Write */
1687 /* (memory -> device) */
1688#define DDAR_DevRd (DDAR_RW*1) /* Device data Read */
1689 /* (device -> memory) */
1690#define DDAR_E 0x00000002 /* big/little Endian device */
1691#define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */
1692#define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */
1693#define DDAR_BS 0x00000004 /* device Burst Size */
1694#define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */
1695#define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */
1696#define DDAR_DW 0x00000008 /* device Data Width */
1697#define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */
1698#define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */
1699#define DDAR_DS Fld (4, 4) /* Device Select */
1700#define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \
1701 (0x0 << FShft (DDAR_DS))
1702#define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \
1703 (0x1 << FShft (DDAR_DS))
1704#define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \
1705 (0x2 << FShft (DDAR_DS))
1706#define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \
1707 (0x3 << FShft (DDAR_DS))
1708#define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \
1709 (0x4 << FShft (DDAR_DS))
1710#define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \
1711 (0x5 << FShft (DDAR_DS))
1712#define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \
1713 (0x6 << FShft (DDAR_DS))
1714#define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \
1715 (0x7 << FShft (DDAR_DS))
1716#define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \
1717 (0x8 << FShft (DDAR_DS))
1718#define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \
1719 (0x9 << FShft (DDAR_DS))
1720#define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \
1721 /* (audio) */ \
1722 (0xA << FShft (DDAR_DS))
1723#define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \
1724 /* (audio) */ \
1725 (0xB << FShft (DDAR_DS))
1726#define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \
1727 /* (telecom) */ \
1728 (0xC << FShft (DDAR_DS))
1729#define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \
1730 /* (telecom) */ \
1731 (0xD << FShft (DDAR_DS))
1732#define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \
1733 (0xE << FShft (DDAR_DS))
1734#define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \
1735 (0xF << FShft (DDAR_DS))
1736#define DDAR_DA Fld (24, 8) /* Device Address */
1737#define DDAR_DevAdd(Add) /* Device Address */ \
1738 (((Add) & 0xF0000000) | \
1739 (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
1740#define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \
1741 (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
1742 DDAR_Ser0UDCTr + DDAR_DevAdd (__PREG(Ser0UDCDR)))
1743#define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \
1744 (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
1745 DDAR_Ser0UDCRc + DDAR_DevAdd (__PREG(Ser0UDCDR)))
1746#define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \
1747 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1748 DDAR_Ser1UARTTr + DDAR_DevAdd (__PREG(Ser1UTDR)))
1749#define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \
1750 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1751 DDAR_Ser1UARTRc + DDAR_DevAdd (__PREG(Ser1UTDR)))
1752#define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \
1753 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1754 DDAR_Ser1SDLCTr + DDAR_DevAdd (__PREG(Ser1SDDR)))
1755#define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \
1756 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1757 DDAR_Ser1SDLCRc + DDAR_DevAdd (__PREG(Ser1SDDR)))
1758#define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \
1759 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1760 DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2UTDR)))
1761#define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \
1762 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1763 DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2UTDR)))
1764#define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \
1765 (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
1766 DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2HSDR)))
1767#define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \
1768 (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
1769 DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2HSDR)))
1770#define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \
1771 (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
1772 DDAR_Ser3UARTTr + DDAR_DevAdd (__PREG(Ser3UTDR)))
1773#define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \
1774 (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
1775 DDAR_Ser3UARTRc + DDAR_DevAdd (__PREG(Ser3UTDR)))
1776#define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \
1777 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
1778 DDAR_Ser4MCP0Tr + DDAR_DevAdd (__PREG(Ser4MCDR0)))
1779#define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \
1780 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
1781 DDAR_Ser4MCP0Rc + DDAR_DevAdd (__PREG(Ser4MCDR0)))
1782#define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \
1783 /* (telecom) */ \
1784 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
1785 DDAR_Ser4MCP1Tr + DDAR_DevAdd (__PREG(Ser4MCDR1)))
1786#define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \
1787 /* (telecom) */ \
1788 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
1789 DDAR_Ser4MCP1Rc + DDAR_DevAdd (__PREG(Ser4MCDR1)))
1790#define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \
1791 (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
1792 DDAR_Ser4SSPTr + DDAR_DevAdd (__PREG(Ser4SSDR)))
1793#define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \
1794 (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
1795 DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR)))
1796
1797#define DCSR_RUN 0x00000001 /* DMA running */
1798#define DCSR_IE 0x00000002 /* DMA Interrupt Enable */
1799#define DCSR_ERROR 0x00000004 /* DMA ERROR */
1800#define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */
1801#define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */
1802#define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */
1803#define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */
1804#define DCSR_BIU 0x00000080 /* DMA Buffer In Use */
1805#define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */
1806#define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */
1807
1808#define DBT_TC Fld (13, 0) /* Transfer Count */
1809#define DBTA_TCA DBT_TC /* Transfer Count buffer A */
1810#define DBTB_TCB DBT_TC /* Transfer Count buffer B */
1596 1811
1597 1812
1598/* 1813/*
@@ -1688,6 +1903,16 @@
1688#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */ 1903#define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
1689 /* (Alternative) */ 1904 /* (Alternative) */
1690 1905
1906#define LCCR0 __REG(0xB0100000) /* LCD Control Reg. 0 */
1907#define LCSR __REG(0xB0100004) /* LCD Status Reg. */
1908#define DBAR1 __REG(0xB0100010) /* LCD DMA Base Address Reg. channel 1 */
1909#define DCAR1 __REG(0xB0100014) /* LCD DMA Current Address Reg. channel 1 */
1910#define DBAR2 __REG(0xB0100018) /* LCD DMA Base Address Reg. channel 2 */
1911#define DCAR2 __REG(0xB010001C) /* LCD DMA Current Address Reg. channel 2 */
1912#define LCCR1 __REG(0xB0100020) /* LCD Control Reg. 1 */
1913#define LCCR2 __REG(0xB0100024) /* LCD Control Reg. 2 */
1914#define LCCR3 __REG(0xB0100028) /* LCD Control Reg. 3 */
1915
1691#define LCCR0_LEN 0x00000001 /* LCD ENable */ 1916#define LCCR0_LEN 0x00000001 /* LCD ENable */
1692#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */ 1917#define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
1693#define LCCR0_Color (LCCR0_CMS*0) /* Color display */ 1918#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
diff --git a/arch/arm/mach-sa1100/include/mach/assabet.h b/arch/arm/mach-sa1100/include/mach/assabet.h
index 307391488c2..28c2cf50c25 100644
--- a/arch/arm/mach-sa1100/include/mach/assabet.h
+++ b/arch/arm/mach-sa1100/include/mach/assabet.h
@@ -85,18 +85,21 @@ extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
85#define ASSABET_BSR_RAD_RI (1 << 31) 85#define ASSABET_BSR_RAD_RI (1 << 31)
86 86
87 87
88/* GPIOs (bitmasks) for which the generic definition doesn't say much */ 88/* GPIOs for which the generic definition doesn't say much */
89#define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */ 89#define ASSABET_GPIO_RADIO_IRQ GPIO_GPIO (14) /* Radio interrupt request */
90#define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */ 90#define ASSABET_GPIO_PS_MODE_SYNC GPIO_GPIO (16) /* Power supply mode/sync */
91#define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */ 91#define ASSABET_GPIO_STEREO_64FS_CLK GPIO_GPIO (19) /* SSP UDA1341 clock input */
92#define ASSABET_GPIO_CF_IRQ GPIO_GPIO (21) /* CF IRQ */
93#define ASSABET_GPIO_CF_CD GPIO_GPIO (22) /* CF CD */
94#define ASSABET_GPIO_CF_BVD2 GPIO_GPIO (24) /* CF BVD */
92#define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */ 95#define ASSABET_GPIO_GFX_IRQ GPIO_GPIO (24) /* Graphics IRQ */
96#define ASSABET_GPIO_CF_BVD1 GPIO_GPIO (25) /* CF BVD */
93#define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */ 97#define ASSABET_GPIO_BATT_LOW GPIO_GPIO (26) /* Low battery */
94#define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */ 98#define ASSABET_GPIO_RCLK GPIO_GPIO (26) /* CCLK/2 */
95 99
96/* These are gpiolib GPIO numbers, not bitmasks */ 100#define ASSABET_IRQ_GPIO_CF_IRQ IRQ_GPIO21
97#define ASSABET_GPIO_CF_IRQ 21 /* CF IRQ */ 101#define ASSABET_IRQ_GPIO_CF_CD IRQ_GPIO22
98#define ASSABET_GPIO_CF_CD 22 /* CF CD */ 102#define ASSABET_IRQ_GPIO_CF_BVD2 IRQ_GPIO24
99#define ASSABET_GPIO_CF_BVD2 24 /* CF BVD / IOSPKR */ 103#define ASSABET_IRQ_GPIO_CF_BVD1 IRQ_GPIO25
100#define ASSABET_GPIO_CF_BVD1 25 /* CF BVD / IOSTSCHG */
101 104
102#endif 105#endif
diff --git a/arch/arm/mach-sa1100/include/mach/cerf.h b/arch/arm/mach-sa1100/include/mach/cerf.h
index 88fd9c006ce..c3ac3d0f946 100644
--- a/arch/arm/mach-sa1100/include/mach/cerf.h
+++ b/arch/arm/mach-sa1100/include/mach/cerf.h
@@ -14,10 +14,15 @@
14#define CERF_ETH_IO 0xf0000000 14#define CERF_ETH_IO 0xf0000000
15#define CERF_ETH_IRQ IRQ_GPIO26 15#define CERF_ETH_IRQ IRQ_GPIO26
16 16
17#define CERF_GPIO_CF_BVD2 19 17#define CERF_GPIO_CF_BVD2 GPIO_GPIO (19)
18#define CERF_GPIO_CF_BVD1 20 18#define CERF_GPIO_CF_BVD1 GPIO_GPIO (20)
19#define CERF_GPIO_CF_RESET 21 19#define CERF_GPIO_CF_RESET GPIO_GPIO (21)
20#define CERF_GPIO_CF_IRQ 22 20#define CERF_GPIO_CF_IRQ GPIO_GPIO (22)
21#define CERF_GPIO_CF_CD 23 21#define CERF_GPIO_CF_CD GPIO_GPIO (23)
22
23#define CERF_IRQ_GPIO_CF_BVD2 IRQ_GPIO19
24#define CERF_IRQ_GPIO_CF_BVD1 IRQ_GPIO20
25#define CERF_IRQ_GPIO_CF_IRQ IRQ_GPIO22
26#define CERF_IRQ_GPIO_CF_CD IRQ_GPIO23
22 27
23#endif // _INCLUDE_CERF_H_ 28#endif // _INCLUDE_CERF_H_
diff --git a/arch/arm/mach-sa1100/include/mach/collie.h b/arch/arm/mach-sa1100/include/mach/collie.h
index f33679d2d3e..52acda7061b 100644
--- a/arch/arm/mach-sa1100/include/mach/collie.h
+++ b/arch/arm/mach-sa1100/include/mach/collie.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * arch/arm/mach-sa1100/include/mach/collie.h 2 * arch/arm/mach-sa1100/include/mach/collie.h
3 * 3 *
4 * This file contains the hardware specific definitions for Collie 4 * This file contains the hardware specific definitions for Assabet
5 * Only include this file from SA1100-specific files. 5 * Only include this file from SA1100-specific files.
6 * 6 *
7 * ChangeLog: 7 * ChangeLog:
@@ -13,7 +13,6 @@
13#ifndef __ASM_ARCH_COLLIE_H 13#ifndef __ASM_ARCH_COLLIE_H
14#define __ASM_ARCH_COLLIE_H 14#define __ASM_ARCH_COLLIE_H
15 15
16extern void locomolcd_power(int on);
17 16
18#define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1) 17#define COLLIE_SCOOP_GPIO_BASE (GPIO_MAX + 1)
19#define COLLIE_GPIO_CHARGE_ON (COLLIE_SCOOP_GPIO_BASE + 0) 18#define COLLIE_GPIO_CHARGE_ON (COLLIE_SCOOP_GPIO_BASE + 0)
diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/mach-sa1100/include/mach/debug-macro.S
index 530772d937a..0cd0fc9635b 100644
--- a/arch/arm/mach-sa1100/include/mach/debug-macro.S
+++ b/arch/arm/mach-sa1100/include/mach/debug-macro.S
@@ -12,7 +12,7 @@
12*/ 12*/
13#include <mach/hardware.h> 13#include <mach/hardware.h>
14 14
15 .macro addruart, rp, rv, tmp 15 .macro addruart, rp, rv
16 mrc p15, 0, \rp, c1, c0 16 mrc p15, 0, \rp, c1, c0
17 tst \rp, #1 @ MMU enabled? 17 tst \rp, #1 @ MMU enabled?
18 moveq \rp, #0x80000000 @ physical base address 18 moveq \rp, #0x80000000 @ physical base address
diff --git a/arch/arm/mach-sa1100/include/mach/entry-macro.S b/arch/arm/mach-sa1100/include/mach/entry-macro.S
index 8cf7630bf02..6aa13c46c5d 100644
--- a/arch/arm/mach-sa1100/include/mach/entry-macro.S
+++ b/arch/arm/mach-sa1100/include/mach/entry-macro.S
@@ -8,11 +8,17 @@
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10 10
11 .macro disable_fiq
12 .endm
13
11 .macro get_irqnr_preamble, base, tmp 14 .macro get_irqnr_preamble, base, tmp
12 mov \base, #0xfa000000 @ ICIP = 0xfa050000 15 mov \base, #0xfa000000 @ ICIP = 0xfa050000
13 add \base, \base, #0x00050000 16 add \base, \base, #0x00050000
14 .endm 17 .endm
15 18
19 .macro arch_ret_to_user, tmp1, tmp2
20 .endm
21
16 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
17 ldr \irqstat, [\base] @ get irqs 23 ldr \irqstat, [\base] @ get irqs
18 ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004 24 ldr \irqnr, [\base, #4] @ ICMR = 0xfa050004
diff --git a/arch/arm/mach-sa1100/include/mach/gpio.h b/arch/arm/mach-sa1100/include/mach/gpio.h
index 6a9eecf3137..7befc104e9a 100644
--- a/arch/arm/mach-sa1100/include/mach/gpio.h
+++ b/arch/arm/mach-sa1100/include/mach/gpio.h
@@ -24,13 +24,10 @@
24#ifndef __ASM_ARCH_SA1100_GPIO_H 24#ifndef __ASM_ARCH_SA1100_GPIO_H
25#define __ASM_ARCH_SA1100_GPIO_H 25#define __ASM_ARCH_SA1100_GPIO_H
26 26
27#include <linux/io.h>
28#include <mach/hardware.h> 27#include <mach/hardware.h>
29#include <asm/irq.h> 28#include <asm/irq.h>
30#include <asm-generic/gpio.h> 29#include <asm-generic/gpio.h>
31 30
32#define __ARM_GPIOLIB_COMPLEX
33
34static inline int gpio_get_value(unsigned gpio) 31static inline int gpio_get_value(unsigned gpio)
35{ 32{
36 if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX)) 33 if (__builtin_constant_p(gpio) && (gpio <= GPIO_MAX))
@@ -52,4 +49,9 @@ static inline void gpio_set_value(unsigned gpio, int value)
52 49
53#define gpio_cansleep __gpio_cansleep 50#define gpio_cansleep __gpio_cansleep
54 51
52#define gpio_to_irq(gpio) ((gpio < 11) ? (IRQ_GPIO0 + gpio) : \
53 (IRQ_GPIO11 - 11 + gpio))
54#define irq_to_gpio(irq) ((irq < IRQ_GPIO11_27) ? (irq - IRQ_GPIO0) : \
55 (irq - IRQ_GPIO11 + 11))
56
55#endif 57#endif
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index cbedd75a9d6..99f5856d8de 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -32,7 +32,7 @@
32#define PIO_START 0x80000000 /* physical start of IO space */ 32#define PIO_START 0x80000000 /* physical start of IO space */
33 33
34#define io_p2v( x ) \ 34#define io_p2v( x ) \
35 IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE ) 35 ( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
36#define io_v2p( x ) \ 36#define io_v2p( x ) \
37 ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START ) 37 ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
38 38
@@ -47,8 +47,6 @@
47#define CPU_SA1110_ID (0x6901b110) 47#define CPU_SA1110_ID (0x6901b110)
48#define CPU_SA1110_MASK (0xfffffff0) 48#define CPU_SA1110_MASK (0xfffffff0)
49 49
50#define __MREG(x) IOMEM(io_p2v(x))
51
52#ifndef __ASSEMBLY__ 50#ifndef __ASSEMBLY__
53 51
54#include <asm/cputype.h> 52#include <asm/cputype.h>
@@ -58,7 +56,7 @@
58#define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID) 56#define cpu_is_sa1100() ((read_cpuid_id() & CPU_SA1100_MASK) == CPU_SA1100_ID)
59#define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID) 57#define cpu_is_sa1110() ((read_cpuid_id() & CPU_SA1110_MASK) == CPU_SA1110_ID)
60 58
61# define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x))) 59# define __REG(x) (*((volatile unsigned long *)io_p2v(x)))
62# define __PREG(x) (io_v2p((unsigned long)&(x))) 60# define __PREG(x) (io_v2p((unsigned long)&(x)))
63 61
64static inline unsigned long get_clock_tick_rate(void) 62static inline unsigned long get_clock_tick_rate(void)
diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h
index 3790298b714..d18f21abef8 100644
--- a/arch/arm/mach-sa1100/include/mach/irqs.h
+++ b/arch/arm/mach-sa1100/include/mach/irqs.h
@@ -71,19 +71,22 @@
71/* 71/*
72 * Figure out the MAX IRQ number. 72 * Figure out the MAX IRQ number.
73 * 73 *
74 * Neponset, SA1111 and UCB1x00 are sparse IRQ aware, so can dynamically 74 * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
75 * allocate their IRQs above NR_IRQS. 75 * If we have an LoCoMo, the max IRQ is IRQ_BOARD_START + 4
76 * 76 * Otherwise, we have the standard IRQs only.
77 * LoCoMo has 4 additional IRQs, but is not sparse IRQ aware, and so has
78 * to be included in the NR_IRQS calculation.
79 */ 77 */
80#ifdef CONFIG_SHARP_LOCOMO 78#ifdef CONFIG_SA1111
81#define NR_IRQS_LOCOMO 4 79#define NR_IRQS (IRQ_BOARD_END + 55)
80#elif defined(CONFIG_SHARP_LOCOMO)
81#define NR_IRQS (IRQ_BOARD_START + 4)
82#else 82#else
83#define NR_IRQS_LOCOMO 0 83#define NR_IRQS (IRQ_BOARD_START)
84#endif 84#endif
85 85
86#ifndef NR_IRQS 86/*
87#define NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO) 87 * Board specific IRQs. Define them here.
88#endif 88 * Do not surround them with ifdefs.
89#define SA1100_NR_IRQS (IRQ_BOARD_START + NR_IRQS_LOCOMO) 89 */
90#define IRQ_NEPONSET_SMC9196 (IRQ_BOARD_START + 0)
91#define IRQ_NEPONSET_USAR (IRQ_BOARD_START + 1)
92#define IRQ_NEPONSET_SA1111 (IRQ_BOARD_START + 2)
diff --git a/arch/arm/mach-sa1100/include/mach/nanoengine.h b/arch/arm/mach-sa1100/include/mach/nanoengine.h
index 5ebd469a31f..14f8382d066 100644
--- a/arch/arm/mach-sa1100/include/mach/nanoengine.h
+++ b/arch/arm/mach-sa1100/include/mach/nanoengine.h
@@ -16,12 +16,12 @@
16 16
17#include <mach/irqs.h> 17#include <mach/irqs.h>
18 18
19#define GPIO_PC_READY0 11 /* ready for socket 0 (active high)*/ 19#define GPIO_PC_READY0 GPIO_GPIO(11) /* ready for socket 0 (active high)*/
20#define GPIO_PC_READY1 12 /* ready for socket 1 (active high) */ 20#define GPIO_PC_READY1 GPIO_GPIO(12) /* ready for socket 1 (active high) */
21#define GPIO_PC_CD0 13 /* detect for socket 0 (active low) */ 21#define GPIO_PC_CD0 GPIO_GPIO(13) /* detect for socket 0 (active low) */
22#define GPIO_PC_CD1 14 /* detect for socket 1 (active low) */ 22#define GPIO_PC_CD1 GPIO_GPIO(14) /* detect for socket 1 (active low) */
23#define GPIO_PC_RESET0 15 /* reset socket 0 */ 23#define GPIO_PC_RESET0 GPIO_GPIO(15) /* reset socket 0 */
24#define GPIO_PC_RESET1 16 /* reset socket 1 */ 24#define GPIO_PC_RESET1 GPIO_GPIO(16) /* reset socket 1 */
25 25
26#define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0 26#define NANOENGINE_IRQ_GPIO_PCI IRQ_GPIO0
27#define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11 27#define NANOENGINE_IRQ_GPIO_PC_READY0 IRQ_GPIO11
diff --git a/arch/arm/mach-sa1100/include/mach/neponset.h b/arch/arm/mach-sa1100/include/mach/neponset.h
index 5516a52a329..ffe2bc45eed 100644
--- a/arch/arm/mach-sa1100/include/mach/neponset.h
+++ b/arch/arm/mach-sa1100/include/mach/neponset.h
@@ -15,6 +15,54 @@
15/* 15/*
16 * Neponset definitions: 16 * Neponset definitions:
17 */ 17 */
18
19#define NEPONSET_CPLD_BASE (0x10000000)
20#define Nep_p2v( x ) ((x) - NEPONSET_CPLD_BASE + 0xf3000000)
21#define Nep_v2p( x ) ((x) - 0xf3000000 + NEPONSET_CPLD_BASE)
22
23#define _IRR 0x10000024 /* Interrupt Reason Register */
24#define _AUD_CTL 0x100000c0 /* Audio controls (RW) */
25#define _MDM_CTL_0 0x100000b0 /* Modem control 0 (RW) */
26#define _MDM_CTL_1 0x100000b4 /* Modem control 1 (RW) */
27#define _NCR_0 0x100000a0 /* Control Register (RW) */
28#define _KP_X_OUT 0x10000090 /* Keypad row write (RW) */
29#define _KP_Y_IN 0x10000080 /* Keypad column read (RO) */
30#define _SWPK 0x10000020 /* Switch pack (RO) */
31#define _WHOAMI 0x10000000 /* System ID Register (RO) */
32
33#define _LEDS 0x10000010 /* LEDs [31:0] (WO) */
34
35#define IRR (*((volatile u_char *) Nep_p2v(_IRR)))
36#define AUD_CTL (*((volatile u_char *) Nep_p2v(_AUD_CTL)))
37#define MDM_CTL_0 (*((volatile u_char *) Nep_p2v(_MDM_CTL_0)))
38#define MDM_CTL_1 (*((volatile u_char *) Nep_p2v(_MDM_CTL_1)))
39#define NCR_0 (*((volatile u_char *) Nep_p2v(_NCR_0)))
40#define KP_X_OUT (*((volatile u_char *) Nep_p2v(_KP_X_OUT)))
41#define KP_Y_IN (*((volatile u_char *) Nep_p2v(_KP_Y_IN)))
42#define SWPK (*((volatile u_char *) Nep_p2v(_SWPK)))
43#define WHOAMI (*((volatile u_char *) Nep_p2v(_WHOAMI)))
44
45#define LEDS (*((volatile Word *) Nep_p2v(_LEDS)))
46
47#define IRR_ETHERNET (1<<0)
48#define IRR_USAR (1<<1)
49#define IRR_SA1111 (1<<2)
50
51#define AUD_SEL_1341 (1<<0)
52#define AUD_MUTE_1341 (1<<1)
53
54#define MDM_CTL0_RTS1 (1 << 0)
55#define MDM_CTL0_DTR1 (1 << 1)
56#define MDM_CTL0_RTS2 (1 << 2)
57#define MDM_CTL0_DTR2 (1 << 3)
58
59#define MDM_CTL1_CTS1 (1 << 0)
60#define MDM_CTL1_DSR1 (1 << 1)
61#define MDM_CTL1_DCD1 (1 << 2)
62#define MDM_CTL1_CTS2 (1 << 3)
63#define MDM_CTL1_DSR2 (1 << 4)
64#define MDM_CTL1_DCD2 (1 << 5)
65
18#define NCR_GP01_OFF (1<<0) 66#define NCR_GP01_OFF (1<<0)
19#define NCR_TP_PWR_EN (1<<1) 67#define NCR_TP_PWR_EN (1<<1)
20#define NCR_MS_PWR_EN (1<<2) 68#define NCR_MS_PWR_EN (1<<2)
@@ -23,8 +71,4 @@
23#define NCR_A0VPP (1<<5) 71#define NCR_A0VPP (1<<5)
24#define NCR_A1VPP (1<<6) 72#define NCR_A1VPP (1<<6)
25 73
26void neponset_ncr_frob(unsigned int, unsigned int);
27#define neponset_ncr_set(v) neponset_ncr_frob(0, v)
28#define neponset_ncr_clear(v) neponset_ncr_frob(v, 0)
29
30#endif 74#endif
diff --git a/arch/arm/mach-sa1100/include/mach/shannon.h b/arch/arm/mach-sa1100/include/mach/shannon.h
index fff39e02b49..ec27d6e1214 100644
--- a/arch/arm/mach-sa1100/include/mach/shannon.h
+++ b/arch/arm/mach-sa1100/include/mach/shannon.h
@@ -21,12 +21,16 @@
21#define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */ 21#define SHANNON_GPIO_U3_RTS GPIO_GPIO (19) /* ?? */
22#define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */ 22#define SHANNON_GPIO_U3_CTS GPIO_GPIO (20) /* ?? */
23#define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */ 23#define SHANNON_GPIO_SENSE_12V GPIO_GPIO (21) /* Input, 12v flash unprotect detected */
24#define SHANNON_GPIO_DISP_EN 22 /* out */ 24#define SHANNON_GPIO_DISP_EN GPIO_GPIO (22) /* out */
25/* XXX GPIO 23 unaccounted for */ 25/* XXX GPIO 23 unaccounted for */
26#define SHANNON_GPIO_EJECT_0 24 /* in */ 26#define SHANNON_GPIO_EJECT_0 GPIO_GPIO (24) /* in */
27#define SHANNON_GPIO_EJECT_1 25 /* in */ 27#define SHANNON_IRQ_GPIO_EJECT_0 IRQ_GPIO24
28#define SHANNON_GPIO_RDY_0 26 /* in */ 28#define SHANNON_GPIO_EJECT_1 GPIO_GPIO (25) /* in */
29#define SHANNON_GPIO_RDY_1 27 /* in */ 29#define SHANNON_IRQ_GPIO_EJECT_1 IRQ_GPIO25
30#define SHANNON_GPIO_RDY_0 GPIO_GPIO (26) /* in */
31#define SHANNON_IRQ_GPIO_RDY_0 IRQ_GPIO26
32#define SHANNON_GPIO_RDY_1 GPIO_GPIO (27) /* in */
33#define SHANNON_IRQ_GPIO_RDY_1 IRQ_GPIO27
30 34
31/* MCP UCB codec GPIO pins... */ 35/* MCP UCB codec GPIO pins... */
32 36
diff --git a/arch/arm/mach-sa1100/include/mach/simpad.h b/arch/arm/mach-sa1100/include/mach/simpad.h
index ac2ea767215..9296c4513ce 100644
--- a/arch/arm/mach-sa1100/include/mach/simpad.h
+++ b/arch/arm/mach-sa1100/include/mach/simpad.h
@@ -39,87 +39,41 @@
39 39
40 40
41/*--- PCMCIA ---*/ 41/*--- PCMCIA ---*/
42#define GPIO_CF_CD 24 42#define GPIO_CF_CD GPIO_GPIO24
43#define GPIO_CF_IRQ 1 43#define GPIO_CF_IRQ GPIO_GPIO1
44#define IRQ_GPIO_CF_IRQ IRQ_GPIO1
45#define IRQ_GPIO_CF_CD IRQ_GPIO24
44 46
45/*--- SmartCard ---*/ 47/*--- SmartCard ---*/
46#define GPIO_SMART_CARD GPIO_GPIO10 48#define GPIO_SMART_CARD GPIO_GPIO10
47#define IRQ_GPIO_SMARD_CARD IRQ_GPIO10 49#define IRQ_GPIO_SMARD_CARD IRQ_GPIO10
48 50
49/*--- ucb1x00 GPIO ---*/ 51// CS3 Latch is write only, a shadow is necessary
50#define SIMPAD_UCB1X00_GPIO_BASE (GPIO_MAX + 1) 52
51#define SIMPAD_UCB1X00_GPIO_PROG1 (SIMPAD_UCB1X00_GPIO_BASE) 53#define CS3BUSTYPE unsigned volatile long
52#define SIMPAD_UCB1X00_GPIO_PROG2 (SIMPAD_UCB1X00_GPIO_BASE + 1) 54#define CS3_BASE 0xf1000000
53#define SIMPAD_UCB1X00_GPIO_UP (SIMPAD_UCB1X00_GPIO_BASE + 2) 55
54#define SIMPAD_UCB1X00_GPIO_DOWN (SIMPAD_UCB1X00_GPIO_BASE + 3) 56#define VCC_5V_EN 0x0001 // For 5V PCMCIA
55#define SIMPAD_UCB1X00_GPIO_LEFT (SIMPAD_UCB1X00_GPIO_BASE + 4) 57#define VCC_3V_EN 0x0002 // FOR 3.3V PCMCIA
56#define SIMPAD_UCB1X00_GPIO_RIGHT (SIMPAD_UCB1X00_GPIO_BASE + 5) 58#define EN1 0x0004 // This is only for EPROM's
57#define SIMPAD_UCB1X00_GPIO_6 (SIMPAD_UCB1X00_GPIO_BASE + 6) 59#define EN0 0x0008 // Both should be enable for 3.3V or 5V
58#define SIMPAD_UCB1X00_GPIO_7 (SIMPAD_UCB1X00_GPIO_BASE + 7) 60#define DISPLAY_ON 0x0010
59#define SIMPAD_UCB1X00_GPIO_HEADSET (SIMPAD_UCB1X00_GPIO_BASE + 8) 61#define PCMCIA_BUFF_DIS 0x0020
60#define SIMPAD_UCB1X00_GPIO_SPEAKER (SIMPAD_UCB1X00_GPIO_BASE + 9) 62#define MQ_RESET 0x0040
61 63#define PCMCIA_RESET 0x0080
62/*--- CS3 Latch ---*/ 64#define DECT_POWER_ON 0x0100
63#define SIMPAD_CS3_GPIO_BASE (GPIO_MAX + 11) 65#define IRDA_SD 0x0200 // Shutdown for powersave
64#define SIMPAD_CS3_VCC_5V_EN (SIMPAD_CS3_GPIO_BASE) 66#define RS232_ON 0x0400
65#define SIMPAD_CS3_VCC_3V_EN (SIMPAD_CS3_GPIO_BASE + 1) 67#define SD_MEDIAQ 0x0800 // Shutdown for powersave
66#define SIMPAD_CS3_EN1 (SIMPAD_CS3_GPIO_BASE + 2) 68#define LED2_ON 0x1000
67#define SIMPAD_CS3_EN0 (SIMPAD_CS3_GPIO_BASE + 3) 69#define IRDA_MODE 0x2000 // Fast/Slow IrDA mode
68#define SIMPAD_CS3_DISPLAY_ON (SIMPAD_CS3_GPIO_BASE + 4) 70#define ENABLE_5V 0x4000 // Enable 5V circuit
69#define SIMPAD_CS3_PCMCIA_BUFF_DIS (SIMPAD_CS3_GPIO_BASE + 5) 71#define RESET_SIMCARD 0x8000
70#define SIMPAD_CS3_MQ_RESET (SIMPAD_CS3_GPIO_BASE + 6) 72
71#define SIMPAD_CS3_PCMCIA_RESET (SIMPAD_CS3_GPIO_BASE + 7) 73#define RS232_ENABLE 0x0440
72#define SIMPAD_CS3_DECT_POWER_ON (SIMPAD_CS3_GPIO_BASE + 8) 74#define PCMCIAMASK 0x402f
73#define SIMPAD_CS3_IRDA_SD (SIMPAD_CS3_GPIO_BASE + 9) 75
74#define SIMPAD_CS3_RS232_ON (SIMPAD_CS3_GPIO_BASE + 10) 76
75#define SIMPAD_CS3_SD_MEDIAQ (SIMPAD_CS3_GPIO_BASE + 11)
76#define SIMPAD_CS3_LED2_ON (SIMPAD_CS3_GPIO_BASE + 12)
77#define SIMPAD_CS3_IRDA_MODE (SIMPAD_CS3_GPIO_BASE + 13)
78#define SIMPAD_CS3_ENABLE_5V (SIMPAD_CS3_GPIO_BASE + 14)
79#define SIMPAD_CS3_RESET_SIMCARD (SIMPAD_CS3_GPIO_BASE + 15)
80
81#define SIMPAD_CS3_PCMCIA_BVD1 (SIMPAD_CS3_GPIO_BASE + 16)
82#define SIMPAD_CS3_PCMCIA_BVD2 (SIMPAD_CS3_GPIO_BASE + 17)
83#define SIMPAD_CS3_PCMCIA_VS1 (SIMPAD_CS3_GPIO_BASE + 18)
84#define SIMPAD_CS3_PCMCIA_VS2 (SIMPAD_CS3_GPIO_BASE + 19)
85#define SIMPAD_CS3_LOCK_IND (SIMPAD_CS3_GPIO_BASE + 20)
86#define SIMPAD_CS3_CHARGING_STATE (SIMPAD_CS3_GPIO_BASE + 21)
87#define SIMPAD_CS3_PCMCIA_SHORT (SIMPAD_CS3_GPIO_BASE + 22)
88#define SIMPAD_CS3_GPIO_23 (SIMPAD_CS3_GPIO_BASE + 23)
89
90#define CS3_BASE IOMEM(0xf1000000)
91
92long simpad_get_cs3_ro(void);
93long simpad_get_cs3_shadow(void);
94void simpad_set_cs3_bit(int value);
95void simpad_clear_cs3_bit(int value);
96
97#define VCC_5V_EN 0x0001 /* For 5V PCMCIA */
98#define VCC_3V_EN 0x0002 /* FOR 3.3V PCMCIA */
99#define EN1 0x0004 /* This is only for EPROM's */
100#define EN0 0x0008 /* Both should be enable for 3.3V or 5V */
101#define DISPLAY_ON 0x0010
102#define PCMCIA_BUFF_DIS 0x0020
103#define MQ_RESET 0x0040
104#define PCMCIA_RESET 0x0080
105#define DECT_POWER_ON 0x0100
106#define IRDA_SD 0x0200 /* Shutdown for powersave */
107#define RS232_ON 0x0400
108#define SD_MEDIAQ 0x0800 /* Shutdown for powersave */
109#define LED2_ON 0x1000
110#define IRDA_MODE 0x2000 /* Fast/Slow IrDA mode */
111#define ENABLE_5V 0x4000 /* Enable 5V circuit */
112#define RESET_SIMCARD 0x8000
113
114#define PCMCIA_BVD1 0x01
115#define PCMCIA_BVD2 0x02
116#define PCMCIA_VS1 0x04
117#define PCMCIA_VS2 0x08
118#define LOCK_IND 0x10
119#define CHARGING_STATE 0x20
120#define PCMCIA_SHORT 0x40
121
122/*--- Battery ---*/
123struct simpad_battery { 77struct simpad_battery {
124 unsigned char ac_status; /* line connected yes/no */ 78 unsigned char ac_status; /* line connected yes/no */
125 unsigned char status; /* battery loading yes/no */ 79 unsigned char status; /* battery loading yes/no */
diff --git a/arch/arm/mach-sa1100/include/mach/uncompress.h b/arch/arm/mach-sa1100/include/mach/uncompress.h
index 5cf71da60e4..6cb39ddde65 100644
--- a/arch/arm/mach-sa1100/include/mach/uncompress.h
+++ b/arch/arm/mach-sa1100/include/mach/uncompress.h
@@ -8,8 +8,6 @@
8 8
9#include "hardware.h" 9#include "hardware.h"
10 10
11#define IOMEM(x) (x)
12
13/* 11/*
14 * The following code assumes the serial port has already been 12 * The following code assumes the serial port has already been
15 * initialized by the bootloader. We search for the first enabled 13 * initialized by the bootloader. We search for the first enabled
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 2124f1fc2fb..dfbf824a69f 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -12,13 +12,11 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/irq.h> 15#include <linux/irq.h>
17#include <linux/ioport.h> 16#include <linux/ioport.h>
18#include <linux/syscore_ops.h> 17#include <linux/syscore_ops.h>
19 18
20#include <mach/hardware.h> 19#include <mach/hardware.h>
21#include <mach/irqs.h>
22#include <asm/mach/irq.h> 20#include <asm/mach/irq.h>
23 21
24#include "generic.h" 22#include "generic.h"
@@ -223,8 +221,11 @@ static struct irq_chip sa1100_normal_chip = {
223 .irq_set_wake = sa1100_set_wake, 221 .irq_set_wake = sa1100_set_wake,
224}; 222};
225 223
226static struct resource irq_resource = 224static struct resource irq_resource = {
227 DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs"); 225 .name = "irqs",
226 .start = 0x90050000,
227 .end = 0x9005ffff,
228};
228 229
229static struct sa1100irq_state { 230static struct sa1100irq_state {
230 unsigned int saved; 231 unsigned int saved;
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index 35cfc428b4d..176c066aec7 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -17,23 +17,21 @@
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/tty.h> 18#include <linux/tty.h>
19#include <linux/delay.h> 19#include <linux/delay.h>
20#include <linux/platform_data/sa11x0-serial.h>
21#include <linux/platform_device.h> 20#include <linux/platform_device.h>
22#include <linux/ioport.h> 21#include <linux/ioport.h>
23#include <linux/mtd/mtd.h> 22#include <linux/mtd/mtd.h>
24#include <linux/mtd/partitions.h> 23#include <linux/mtd/partitions.h>
25#include <video/s1d13xxxfb.h> 24#include <video/s1d13xxxfb.h>
26 25
26#include <mach/hardware.h>
27#include <asm/hardware/sa1111.h> 27#include <asm/hardware/sa1111.h>
28#include <asm/page.h> 28#include <asm/irq.h>
29#include <asm/mach-types.h> 29#include <asm/mach-types.h>
30#include <asm/setup.h> 30#include <asm/setup.h>
31#include <asm/mach/arch.h> 31#include <asm/mach/arch.h>
32#include <asm/mach/flash.h> 32#include <asm/mach/flash.h>
33#include <asm/mach/map.h> 33#include <asm/mach/map.h>
34 34#include <asm/mach/serial_sa1100.h>
35#include <mach/hardware.h>
36#include <mach/irqs.h>
37 35
38#include "generic.h" 36#include "generic.h"
39 37
@@ -47,7 +45,7 @@
47 45
48/* memory space (line 52 of HP's doc) */ 46/* memory space (line 52 of HP's doc) */
49#define SA1111REGSTART 0x40000000 47#define SA1111REGSTART 0x40000000
50#define SA1111REGLEN 0x00002000 48#define SA1111REGLEN 0x00001fff
51#define EPSONREGSTART 0x48000000 49#define EPSONREGSTART 0x48000000
52#define EPSONREGLEN 0x00100000 50#define EPSONREGLEN 0x00100000
53#define EPSONFBSTART 0x48200000 51#define EPSONFBSTART 0x48200000
@@ -175,8 +173,16 @@ static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
175}; 173};
176 174
177static struct resource s1d13xxxfb_resources[] = { 175static struct resource s1d13xxxfb_resources[] = {
178 [0] = DEFINE_RES_MEM(EPSONFBSTART, EPSONFBLEN), 176 [0] = {
179 [1] = DEFINE_RES_MEM(EPSONREGSTART, EPSONREGLEN), 177 .start = EPSONFBSTART,
178 .end = EPSONFBSTART + EPSONFBLEN,
179 .flags = IORESOURCE_MEM,
180 },
181 [1] = {
182 .start = EPSONREGSTART,
183 .end = EPSONREGSTART + EPSONREGLEN,
184 .flags = IORESOURCE_MEM,
185 }
180}; 186};
181 187
182static struct platform_device s1d13xxxfb_device = { 188static struct platform_device s1d13xxxfb_device = {
@@ -190,12 +196,20 @@ static struct platform_device s1d13xxxfb_device = {
190}; 196};
191 197
192static struct resource sa1111_resources[] = { 198static struct resource sa1111_resources[] = {
193 [0] = DEFINE_RES_MEM(SA1111REGSTART, SA1111REGLEN), 199 [0] = {
194 [1] = DEFINE_RES_IRQ(IRQ_GPIO1), 200 .start = SA1111REGSTART,
201 .end = SA1111REGSTART + SA1111REGLEN,
202 .flags = IORESOURCE_MEM,
203 },
204 [1] = {
205 .start = IRQ_GPIO1,
206 .end = IRQ_GPIO1,
207 .flags = IORESOURCE_IRQ,
208 },
195}; 209};
196 210
197static struct sa1111_platform_data sa1111_info = { 211static struct sa1111_platform_data sa1111_info = {
198 .disable_devs = SA1111_DEVID_PS2_MSE, 212 .irq_base = IRQ_BOARD_END,
199}; 213};
200 214
201static u64 sa1111_dmamask = 0xffffffffUL; 215static u64 sa1111_dmamask = 0xffffffffUL;
@@ -269,6 +283,11 @@ static struct map_desc jornada720_io_desc[] __initdata = {
269 .pfn = __phys_to_pfn(EPSONFBSTART), 283 .pfn = __phys_to_pfn(EPSONFBSTART),
270 .length = EPSONFBLEN, 284 .length = EPSONFBLEN,
271 .type = MT_DEVICE 285 .type = MT_DEVICE
286 }, { /* SA-1111 */
287 .virtual = 0xf4000000,
288 .pfn = __phys_to_pfn(SA1111REGSTART),
289 .length = SA1111REGLEN,
290 .type = MT_DEVICE
272 } 291 }
273}; 292};
274 293
@@ -332,8 +351,11 @@ static struct flash_platform_data jornada720_flash_data = {
332 .nr_parts = ARRAY_SIZE(jornada720_partitions), 351 .nr_parts = ARRAY_SIZE(jornada720_partitions),
333}; 352};
334 353
335static struct resource jornada720_flash_resource = 354static struct resource jornada720_flash_resource = {
336 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M); 355 .start = SA1100_CS0_PHYS,
356 .end = SA1100_CS0_PHYS + SZ_32M - 1,
357 .flags = IORESOURCE_MEM,
358};
337 359
338static void __init jornada720_mach_init(void) 360static void __init jornada720_mach_init(void)
339{ 361{
@@ -342,15 +364,12 @@ static void __init jornada720_mach_init(void)
342 364
343MACHINE_START(JORNADA720, "HP Jornada 720") 365MACHINE_START(JORNADA720, "HP Jornada 720")
344 /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */ 366 /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */
345 .atag_offset = 0x100, 367 .boot_params = 0xc0000100,
346 .map_io = jornada720_map_io, 368 .map_io = jornada720_map_io,
347 .nr_irqs = SA1100_NR_IRQS,
348 .init_irq = sa1100_init_irq, 369 .init_irq = sa1100_init_irq,
349 .timer = &sa1100_timer, 370 .timer = &sa1100_timer,
350 .init_machine = jornada720_mach_init, 371 .init_machine = jornada720_mach_init,
351 .init_late = sa11x0_init_late,
352#ifdef CONFIG_SA1111 372#ifdef CONFIG_SA1111
353 .dma_zone_size = SZ_1M, 373 .dma_zone_size = SZ_1M,
354#endif 374#endif
355 .restart = sa11x0_restart,
356MACHINE_END 375MACHINE_END
diff --git a/arch/arm/mach-sa1100/jornada720_ssp.c b/arch/arm/mach-sa1100/jornada720_ssp.c
index b143c465934..f50b00bd18a 100644
--- a/arch/arm/mach-sa1100/jornada720_ssp.c
+++ b/arch/arm/mach-sa1100/jornada720_ssp.c
@@ -18,7 +18,6 @@
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/sched.h> 20#include <linux/sched.h>
21#include <linux/io.h>
22 21
23#include <mach/hardware.h> 22#include <mach/hardware.h>
24#include <mach/jornada720.h> 23#include <mach/jornada720.h>
@@ -130,7 +129,7 @@ void jornada_ssp_end(void)
130}; 129};
131EXPORT_SYMBOL(jornada_ssp_end); 130EXPORT_SYMBOL(jornada_ssp_end);
132 131
133static int jornada_ssp_probe(struct platform_device *dev) 132static int __devinit jornada_ssp_probe(struct platform_device *dev)
134{ 133{
135 int ret; 134 int ret;
136 135
@@ -199,5 +198,3 @@ static int __init jornada_ssp_init(void)
199{ 198{
200 return platform_driver_register(&jornadassp_driver); 199 return platform_driver_register(&jornadassp_driver);
201} 200}
202
203module_init(jornada_ssp_init);
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index f69f78fc3dd..7b9556b5905 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -4,13 +4,7 @@
4 4
5#include <linux/init.h> 5#include <linux/init.h>
6#include <linux/kernel.h> 6#include <linux/kernel.h>
7#include <linux/platform_data/sa11x0-serial.h>
8#include <linux/tty.h> 7#include <linux/tty.h>
9#include <linux/gpio.h>
10#include <linux/leds.h>
11#include <linux/platform_device.h>
12
13#include <video/sa1100fb.h>
14 8
15#include <mach/hardware.h> 9#include <mach/hardware.h>
16#include <asm/setup.h> 10#include <asm/setup.h>
@@ -19,8 +13,8 @@
19 13
20#include <asm/mach/arch.h> 14#include <asm/mach/arch.h>
21#include <asm/mach/map.h> 15#include <asm/mach/map.h>
22#include <linux/platform_data/mfd-mcp-sa11x0.h> 16#include <asm/mach/serial_sa1100.h>
23#include <mach/irqs.h> 17#include <mach/mcp.h>
24 18
25#include "generic.h" 19#include "generic.h"
26 20
@@ -32,86 +26,8 @@ static struct mcp_plat_data lart_mcp_data = {
32 .sclk_rate = 11981000, 26 .sclk_rate = 11981000,
33}; 27};
34 28
35#ifdef LART_GREY_LCD
36static struct sa1100fb_mach_info lart_grey_info = {
37 .pixclock = 150000, .bpp = 4,
38 .xres = 320, .yres = 240,
39
40 .hsync_len = 1, .vsync_len = 1,
41 .left_margin = 4, .upper_margin = 0,
42 .right_margin = 2, .lower_margin = 0,
43
44 .cmap_greyscale = 1,
45 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
46
47 .lccr0 = LCCR0_Mono | LCCR0_Sngl | LCCR0_Pas | LCCR0_4PixMono,
48 .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
49};
50#endif
51#ifdef LART_COLOR_LCD
52static struct sa1100fb_mach_info lart_color_info = {
53 .pixclock = 150000, .bpp = 16,
54 .xres = 320, .yres = 240,
55
56 .hsync_len = 2, .vsync_len = 3,
57 .left_margin = 69, .upper_margin = 14,
58 .right_margin = 8, .lower_margin = 4,
59
60 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
61 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
62};
63#endif
64#ifdef LART_VIDEO_OUT
65static struct sa1100fb_mach_info lart_video_info = {
66 .pixclock = 39721, .bpp = 16,
67 .xres = 640, .yres = 480,
68
69 .hsync_len = 95, .vsync_len = 2,
70 .left_margin = 40, .upper_margin = 32,
71 .right_margin = 24, .lower_margin = 11,
72
73 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
74
75 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
76 .lccr3 = LCCR3_OutEnL | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
77};
78#endif
79
80#ifdef LART_KIT01_LCD
81static struct sa1100fb_mach_info lart_kit01_info = {
82 .pixclock = 63291, .bpp = 16,
83 .xres = 640, .yres = 480,
84
85 .hsync_len = 64, .vsync_len = 3,
86 .left_margin = 122, .upper_margin = 45,
87 .right_margin = 10, .lower_margin = 10,
88
89 .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
90 .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg
91};
92#endif
93
94static void __init lart_init(void) 29static void __init lart_init(void)
95{ 30{
96 struct sa1100fb_mach_info *inf = NULL;
97
98#ifdef LART_GREY_LCD
99 inf = &lart_grey_info;
100#endif
101#ifdef LART_COLOR_LCD
102 inf = &lart_color_info;
103#endif
104#ifdef LART_VIDEO_OUT
105 inf = &lart_video_info;
106#endif
107#ifdef LART_KIT01_LCD
108 inf = &lart_kit01_info;
109#endif
110
111 if (inf)
112 sa11x0_register_lcd(inf);
113
114 sa11x0_ppc_configure_mcp();
115 sa11x0_register_mcp(&lart_mcp_data); 31 sa11x0_register_mcp(&lart_mcp_data);
116} 32}
117 33
@@ -129,27 +45,6 @@ static struct map_desc lart_io_desc[] __initdata = {
129 } 45 }
130}; 46};
131 47
132/* LEDs */
133struct gpio_led lart_gpio_leds[] = {
134 {
135 .name = "lart:red",
136 .default_trigger = "cpu0",
137 .gpio = 23,
138 },
139};
140
141static struct gpio_led_platform_data lart_gpio_led_info = {
142 .leds = lart_gpio_leds,
143 .num_leds = ARRAY_SIZE(lart_gpio_leds),
144};
145
146static struct platform_device lart_leds = {
147 .name = "leds-gpio",
148 .id = -1,
149 .dev = {
150 .platform_data = &lart_gpio_led_info,
151 }
152};
153static void __init lart_map_io(void) 48static void __init lart_map_io(void)
154{ 49{
155 sa1100_map_io(); 50 sa1100_map_io();
@@ -163,17 +58,12 @@ static void __init lart_map_io(void)
163 GPDR |= GPIO_UART_TXD; 58 GPDR |= GPIO_UART_TXD;
164 GPDR &= ~GPIO_UART_RXD; 59 GPDR &= ~GPIO_UART_RXD;
165 PPAR |= PPAR_UPR; 60 PPAR |= PPAR_UPR;
166
167 platform_device_register(&lart_leds);
168} 61}
169 62
170MACHINE_START(LART, "LART") 63MACHINE_START(LART, "LART")
171 .atag_offset = 0x100, 64 .boot_params = 0xc0000100,
172 .map_io = lart_map_io, 65 .map_io = lart_map_io,
173 .nr_irqs = SA1100_NR_IRQS,
174 .init_irq = sa1100_init_irq, 66 .init_irq = sa1100_init_irq,
175 .init_machine = lart_init, 67 .init_machine = lart_init,
176 .init_late = sa11x0_init_late,
177 .timer = &sa1100_timer, 68 .timer = &sa1100_timer,
178 .restart = sa11x0_restart,
179MACHINE_END 69MACHINE_END
diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c
index 102e08f7b10..72087f0658b 100644
--- a/arch/arm/mach-sa1100/nanoengine.c
+++ b/arch/arm/mach-sa1100/nanoengine.c
@@ -13,22 +13,20 @@
13 13
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/platform_data/sa11x0-serial.h>
17#include <linux/mtd/mtd.h> 16#include <linux/mtd/mtd.h>
18#include <linux/mtd/partitions.h> 17#include <linux/mtd/partitions.h>
19#include <linux/root_dev.h> 18#include <linux/root_dev.h>
20 19
21#include <asm/mach-types.h> 20#include <asm/mach-types.h>
22#include <asm/setup.h> 21#include <asm/setup.h>
23#include <asm/page.h>
24 22
25#include <asm/mach/arch.h> 23#include <asm/mach/arch.h>
26#include <asm/mach/flash.h> 24#include <asm/mach/flash.h>
27#include <asm/mach/map.h> 25#include <asm/mach/map.h>
26#include <asm/mach/serial_sa1100.h>
28 27
29#include <mach/hardware.h> 28#include <mach/hardware.h>
30#include <mach/nanoengine.h> 29#include <mach/nanoengine.h>
31#include <mach/irqs.h>
32 30
33#include "generic.h" 31#include "generic.h"
34 32
@@ -59,8 +57,15 @@ static struct flash_platform_data nanoengine_flash_data = {
59}; 57};
60 58
61static struct resource nanoengine_flash_resources[] = { 59static struct resource nanoengine_flash_resources[] = {
62 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_32M), 60 {
63 DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_32M), 61 .start = SA1100_CS0_PHYS,
62 .end = SA1100_CS0_PHYS + SZ_32M - 1,
63 .flags = IORESOURCE_MEM,
64 }, {
65 .start = SA1100_CS1_PHYS,
66 .end = SA1100_CS1_PHYS + SZ_32M - 1,
67 .flags = IORESOURCE_MEM,
68 }
64}; 69};
65 70
66static struct map_desc nanoengine_io_desc[] __initdata = { 71static struct map_desc nanoengine_io_desc[] __initdata = {
@@ -106,12 +111,9 @@ static void __init nanoengine_init(void)
106} 111}
107 112
108MACHINE_START(NANOENGINE, "BSE nanoEngine") 113MACHINE_START(NANOENGINE, "BSE nanoEngine")
109 .atag_offset = 0x100, 114 .boot_params = 0xc0000000,
110 .map_io = nanoengine_map_io, 115 .map_io = nanoengine_map_io,
111 .nr_irqs = SA1100_NR_IRQS,
112 .init_irq = sa1100_init_irq, 116 .init_irq = sa1100_init_irq,
113 .timer = &sa1100_timer, 117 .timer = &sa1100_timer,
114 .init_machine = nanoengine_init, 118 .init_machine = nanoengine_init,
115 .init_late = sa11x0_init_late,
116 .restart = sa11x0_restart,
117MACHINE_END 119MACHINE_END
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index 400f8033204..b4fa53a1427 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -1,105 +1,89 @@
1/* 1/*
2 * linux/arch/arm/mach-sa1100/neponset.c 2 * linux/arch/arm/mach-sa1100/neponset.c
3 *
3 */ 4 */
4#include <linux/err.h> 5#include <linux/kernel.h>
5#include <linux/init.h> 6#include <linux/init.h>
7#include <linux/tty.h>
6#include <linux/ioport.h> 8#include <linux/ioport.h>
7#include <linux/irq.h>
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/platform_data/sa11x0-serial.h>
11#include <linux/platform_device.h>
12#include <linux/pm.h>
13#include <linux/serial_core.h> 9#include <linux/serial_core.h>
14#include <linux/slab.h> 10#include <linux/platform_device.h>
15 11
12#include <mach/hardware.h>
16#include <asm/mach-types.h> 13#include <asm/mach-types.h>
14#include <asm/irq.h>
17#include <asm/mach/map.h> 15#include <asm/mach/map.h>
16#include <asm/mach/irq.h>
17#include <asm/mach/serial_sa1100.h>
18#include <mach/assabet.h>
19#include <mach/neponset.h>
18#include <asm/hardware/sa1111.h> 20#include <asm/hardware/sa1111.h>
19#include <asm/sizes.h> 21#include <asm/sizes.h>
20 22
21#include <mach/hardware.h> 23/*
22#include <mach/assabet.h> 24 * Install handler for Neponset IRQ. Note that we have to loop here
23#include <mach/neponset.h> 25 * since the ETHERNET and USAR IRQs are level based, and we need to
24#include <mach/irqs.h> 26 * ensure that the IRQ signal is deasserted before returning. This
25 27 * is rather unfortunate.
26#define NEP_IRQ_SMC91X 0 28 */
27#define NEP_IRQ_USAR 1 29static void
28#define NEP_IRQ_SA1111 2 30neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
29#define NEP_IRQ_NR 3 31{
30 32 unsigned int irr;
31#define WHOAMI 0x00
32#define LEDS 0x10
33#define SWPK 0x20
34#define IRR 0x24
35#define KP_Y_IN 0x80
36#define KP_X_OUT 0x90
37#define NCR_0 0xa0
38#define MDM_CTL_0 0xb0
39#define MDM_CTL_1 0xb4
40#define AUD_CTL 0xc0
41
42#define IRR_ETHERNET (1 << 0)
43#define IRR_USAR (1 << 1)
44#define IRR_SA1111 (1 << 2)
45
46#define MDM_CTL0_RTS1 (1 << 0)
47#define MDM_CTL0_DTR1 (1 << 1)
48#define MDM_CTL0_RTS2 (1 << 2)
49#define MDM_CTL0_DTR2 (1 << 3)
50
51#define MDM_CTL1_CTS1 (1 << 0)
52#define MDM_CTL1_DSR1 (1 << 1)
53#define MDM_CTL1_DCD1 (1 << 2)
54#define MDM_CTL1_CTS2 (1 << 3)
55#define MDM_CTL1_DSR2 (1 << 4)
56#define MDM_CTL1_DCD2 (1 << 5)
57
58#define AUD_SEL_1341 (1 << 0)
59#define AUD_MUTE_1341 (1 << 1)
60 33
61extern void sa1110_mb_disable(void); 34 while (1) {
35 /*
36 * Acknowledge the parent IRQ.
37 */
38 desc->irq_data.chip->irq_ack(&desc->irq_data);
62 39
63struct neponset_drvdata { 40 /*
64 void __iomem *base; 41 * Read the interrupt reason register. Let's have all
65 struct platform_device *sa1111; 42 * active IRQ bits high. Note: there is a typo in the
66 struct platform_device *smc91x; 43 * Neponset user's guide for the SA1111 IRR level.
67 unsigned irq_base; 44 */
68#ifdef CONFIG_PM_SLEEP 45 irr = IRR ^ (IRR_ETHERNET | IRR_USAR);
69 u32 ncr0;
70 u32 mdm_ctl_0;
71#endif
72};
73 46
74static void __iomem *nep_base; 47 if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
48 break;
75 49
76void neponset_ncr_frob(unsigned int mask, unsigned int val) 50 /*
77{ 51 * Since there is no individual mask, we have to
78 void __iomem *base = nep_base; 52 * mask the parent IRQ. This is safe, since we'll
79 53 * recheck the register for any pending IRQs.
80 if (base) { 54 */
81 unsigned long flags; 55 if (irr & (IRR_ETHERNET | IRR_USAR)) {
82 unsigned v; 56 desc->irq_data.chip->irq_mask(&desc->irq_data);
83 57
84 local_irq_save(flags); 58 /*
85 v = readb_relaxed(base + NCR_0); 59 * Ack the interrupt now to prevent re-entering
86 writeb_relaxed((v & ~mask) | val, base + NCR_0); 60 * this neponset handler. Again, this is safe
87 local_irq_restore(flags); 61 * since we'll check the IRR register prior to
88 } else { 62 * leaving.
89 WARN(1, "nep_base unset\n"); 63 */
64 desc->irq_data.chip->irq_ack(&desc->irq_data);
65
66 if (irr & IRR_ETHERNET) {
67 generic_handle_irq(IRQ_NEPONSET_SMC9196);
68 }
69
70 if (irr & IRR_USAR) {
71 generic_handle_irq(IRQ_NEPONSET_USAR);
72 }
73
74 desc->irq_data.chip->irq_unmask(&desc->irq_data);
75 }
76
77 if (irr & IRR_SA1111) {
78 generic_handle_irq(IRQ_NEPONSET_SA1111);
79 }
90 } 80 }
91} 81}
92EXPORT_SYMBOL(neponset_ncr_frob);
93 82
94static void neponset_set_mctrl(struct uart_port *port, u_int mctrl) 83static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
95{ 84{
96 void __iomem *base = nep_base; 85 u_int mdm_ctl0 = MDM_CTL_0;
97 u_int mdm_ctl0;
98
99 if (!base)
100 return;
101 86
102 mdm_ctl0 = readb_relaxed(base + MDM_CTL_0);
103 if (port->mapbase == _Ser1UTCR0) { 87 if (port->mapbase == _Ser1UTCR0) {
104 if (mctrl & TIOCM_RTS) 88 if (mctrl & TIOCM_RTS)
105 mdm_ctl0 &= ~MDM_CTL0_RTS2; 89 mdm_ctl0 &= ~MDM_CTL0_RTS2;
@@ -122,19 +106,14 @@ static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
122 mdm_ctl0 |= MDM_CTL0_DTR1; 106 mdm_ctl0 |= MDM_CTL0_DTR1;
123 } 107 }
124 108
125 writeb_relaxed(mdm_ctl0, base + MDM_CTL_0); 109 MDM_CTL_0 = mdm_ctl0;
126} 110}
127 111
128static u_int neponset_get_mctrl(struct uart_port *port) 112static u_int neponset_get_mctrl(struct uart_port *port)
129{ 113{
130 void __iomem *base = nep_base;
131 u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR; 114 u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
132 u_int mdm_ctl1; 115 u_int mdm_ctl1 = MDM_CTL_1;
133
134 if (!base)
135 return ret;
136 116
137 mdm_ctl1 = readb_relaxed(base + MDM_CTL_1);
138 if (port->mapbase == _Ser1UTCR0) { 117 if (port->mapbase == _Ser1UTCR0) {
139 if (mdm_ctl1 & MDM_CTL1_DCD2) 118 if (mdm_ctl1 & MDM_CTL1_DCD2)
140 ret &= ~TIOCM_CD; 119 ret &= ~TIOCM_CD;
@@ -154,283 +133,214 @@ static u_int neponset_get_mctrl(struct uart_port *port)
154 return ret; 133 return ret;
155} 134}
156 135
157static struct sa1100_port_fns neponset_port_fns = { 136static struct sa1100_port_fns neponset_port_fns __devinitdata = {
158 .set_mctrl = neponset_set_mctrl, 137 .set_mctrl = neponset_set_mctrl,
159 .get_mctrl = neponset_get_mctrl, 138 .get_mctrl = neponset_get_mctrl,
160}; 139};
161 140
162/* 141static int __devinit neponset_probe(struct platform_device *dev)
163 * Install handler for Neponset IRQ. Note that we have to loop here
164 * since the ETHERNET and USAR IRQs are level based, and we need to
165 * ensure that the IRQ signal is deasserted before returning. This
166 * is rather unfortunate.
167 */
168static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
169{ 142{
170 struct neponset_drvdata *d = irq_desc_get_handler_data(desc); 143 sa1100_register_uart_fns(&neponset_port_fns);
171 unsigned int irr;
172
173 while (1) {
174 /*
175 * Acknowledge the parent IRQ.
176 */
177 desc->irq_data.chip->irq_ack(&desc->irq_data);
178
179 /*
180 * Read the interrupt reason register. Let's have all
181 * active IRQ bits high. Note: there is a typo in the
182 * Neponset user's guide for the SA1111 IRR level.
183 */
184 irr = readb_relaxed(d->base + IRR);
185 irr ^= IRR_ETHERNET | IRR_USAR;
186
187 if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
188 break;
189
190 /*
191 * Since there is no individual mask, we have to
192 * mask the parent IRQ. This is safe, since we'll
193 * recheck the register for any pending IRQs.
194 */
195 if (irr & (IRR_ETHERNET | IRR_USAR)) {
196 desc->irq_data.chip->irq_mask(&desc->irq_data);
197
198 /*
199 * Ack the interrupt now to prevent re-entering
200 * this neponset handler. Again, this is safe
201 * since we'll check the IRR register prior to
202 * leaving.
203 */
204 desc->irq_data.chip->irq_ack(&desc->irq_data);
205 144
206 if (irr & IRR_ETHERNET) 145 /*
207 generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X); 146 * Install handler for GPIO25.
147 */
148 irq_set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING);
149 irq_set_chained_handler(IRQ_GPIO25, neponset_irq_handler);
208 150
209 if (irr & IRR_USAR) 151 /*
210 generic_handle_irq(d->irq_base + NEP_IRQ_USAR); 152 * We would set IRQ_GPIO25 to be a wake-up IRQ, but
153 * unfortunately something on the Neponset activates
154 * this IRQ on sleep (ethernet?)
155 */
156#if 0
157 enable_irq_wake(IRQ_GPIO25);
158#endif
211 159
212 desc->irq_data.chip->irq_unmask(&desc->irq_data); 160 /*
213 } 161 * Setup other Neponset IRQs. SA1111 will be done by the
162 * generic SA1111 code.
163 */
164 irq_set_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
165 set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE);
166 irq_set_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
167 set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE);
214 168
215 if (irr & IRR_SA1111) 169 /*
216 generic_handle_irq(d->irq_base + NEP_IRQ_SA1111); 170 * Disable GPIO 0/1 drivers so the buttons work on the module.
217 } 171 */
218} 172 NCR_0 = NCR_GP01_OFF;
219 173
220/* Yes, we really do not have any kind of masking or unmasking */ 174 return 0;
221static void nochip_noop(struct irq_data *irq)
222{
223} 175}
224 176
225static struct irq_chip nochip = { 177#ifdef CONFIG_PM
226 .name = "neponset",
227 .irq_ack = nochip_noop,
228 .irq_mask = nochip_noop,
229 .irq_unmask = nochip_noop,
230};
231 178
232static struct sa1111_platform_data sa1111_info = { 179/*
233 .disable_devs = SA1111_DEVID_PS2_MSE, 180 * LDM power management.
234}; 181 */
182static unsigned int neponset_saved_state;
235 183
236static int neponset_probe(struct platform_device *dev) 184static int neponset_suspend(struct platform_device *dev, pm_message_t state)
237{ 185{
238 struct neponset_drvdata *d; 186 /*
239 struct resource *nep_res, *sa1111_res, *smc91x_res; 187 * Save state.
240 struct resource sa1111_resources[] = { 188 */
241 DEFINE_RES_MEM(0x40000000, SZ_8K), 189 neponset_saved_state = NCR_0;
242 { .flags = IORESOURCE_IRQ },
243 };
244 struct platform_device_info sa1111_devinfo = {
245 .parent = &dev->dev,
246 .name = "sa1111",
247 .id = 0,
248 .res = sa1111_resources,
249 .num_res = ARRAY_SIZE(sa1111_resources),
250 .data = &sa1111_info,
251 .size_data = sizeof(sa1111_info),
252 .dma_mask = 0xffffffffUL,
253 };
254 struct resource smc91x_resources[] = {
255 DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
256 0x02000000, "smc91x-regs"),
257 DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
258 0x02000000, "smc91x-attrib"),
259 { .flags = IORESOURCE_IRQ },
260 };
261 struct platform_device_info smc91x_devinfo = {
262 .parent = &dev->dev,
263 .name = "smc91x",
264 .id = 0,
265 .res = smc91x_resources,
266 .num_res = ARRAY_SIZE(smc91x_resources),
267 };
268 int ret, irq;
269
270 if (nep_base)
271 return -EBUSY;
272
273 irq = ret = platform_get_irq(dev, 0);
274 if (ret < 0)
275 goto err_alloc;
276
277 nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
278 smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
279 sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
280 if (!nep_res || !smc91x_res || !sa1111_res) {
281 ret = -ENXIO;
282 goto err_alloc;
283 }
284
285 d = kzalloc(sizeof(*d), GFP_KERNEL);
286 if (!d) {
287 ret = -ENOMEM;
288 goto err_alloc;
289 }
290
291 d->base = ioremap(nep_res->start, SZ_4K);
292 if (!d->base) {
293 ret = -ENOMEM;
294 goto err_ioremap;
295 }
296
297 if (readb_relaxed(d->base + WHOAMI) != 0x11) {
298 dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
299 readb_relaxed(d->base + WHOAMI));
300 ret = -ENODEV;
301 goto err_id;
302 }
303
304 ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
305 if (ret <= 0) {
306 dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
307 NEP_IRQ_NR, ret);
308 if (ret == 0)
309 ret = -ENOMEM;
310 goto err_irq_alloc;
311 }
312 190
313 d->irq_base = ret; 191 return 0;
192}
314 193
315 irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip, 194static int neponset_resume(struct platform_device *dev)
316 handle_simple_irq); 195{
317 set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE); 196 NCR_0 = neponset_saved_state;
318 irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
319 handle_simple_irq);
320 set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE);
321 irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
322 197
323 irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING); 198 return 0;
324 irq_set_handler_data(irq, d); 199}
325 irq_set_chained_handler(irq, neponset_irq_handler);
326 200
327 /* 201#else
328 * We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately 202#define neponset_suspend NULL
329 * something on the Neponset activates this IRQ on sleep (eth?) 203#define neponset_resume NULL
330 */
331#if 0
332 enable_irq_wake(irq);
333#endif 204#endif
334 205
335 dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n", 206static struct platform_driver neponset_device_driver = {
336 d->irq_base, d->irq_base + NEP_IRQ_NR - 1); 207 .probe = neponset_probe,
337 nep_base = d->base; 208 .suspend = neponset_suspend,
209 .resume = neponset_resume,
210 .driver = {
211 .name = "neponset",
212 },
213};
338 214
339 sa1100_register_uart_fns(&neponset_port_fns); 215static struct resource neponset_resources[] = {
216 [0] = {
217 .start = 0x10000000,
218 .end = 0x17ffffff,
219 .flags = IORESOURCE_MEM,
220 },
221};
340 222
341 /* Ensure that the memory bus request/grant signals are setup */ 223static struct platform_device neponset_device = {
342 sa1110_mb_disable(); 224 .name = "neponset",
225 .id = 0,
226 .num_resources = ARRAY_SIZE(neponset_resources),
227 .resource = neponset_resources,
228};
343 229
344 /* Disable GPIO 0/1 drivers so the buttons work on the Assabet */ 230static struct resource sa1111_resources[] = {
345 writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0); 231 [0] = {
232 .start = 0x40000000,
233 .end = 0x40001fff,
234 .flags = IORESOURCE_MEM,
235 },
236 [1] = {
237 .start = IRQ_NEPONSET_SA1111,
238 .end = IRQ_NEPONSET_SA1111,
239 .flags = IORESOURCE_IRQ,
240 },
241};
346 242
347 sa1111_resources[0].parent = sa1111_res; 243static struct sa1111_platform_data sa1111_info = {
348 sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111; 244 .irq_base = IRQ_BOARD_END,
349 sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111; 245};
350 d->sa1111 = platform_device_register_full(&sa1111_devinfo);
351 246
352 smc91x_resources[0].parent = smc91x_res; 247static u64 sa1111_dmamask = 0xffffffffUL;
353 smc91x_resources[1].parent = smc91x_res;
354 smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
355 smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
356 d->smc91x = platform_device_register_full(&smc91x_devinfo);
357 248
358 platform_set_drvdata(dev, d); 249static struct platform_device sa1111_device = {
250 .name = "sa1111",
251 .id = 0,
252 .dev = {
253 .dma_mask = &sa1111_dmamask,
254 .coherent_dma_mask = 0xffffffff,
255 .platform_data = &sa1111_info,
256 },
257 .num_resources = ARRAY_SIZE(sa1111_resources),
258 .resource = sa1111_resources,
259};
359 260
360 return 0; 261static struct resource smc91x_resources[] = {
262 [0] = {
263 .name = "smc91x-regs",
264 .start = SA1100_CS3_PHYS,
265 .end = SA1100_CS3_PHYS + 0x01ffffff,
266 .flags = IORESOURCE_MEM,
267 },
268 [1] = {
269 .start = IRQ_NEPONSET_SMC9196,
270 .end = IRQ_NEPONSET_SMC9196,
271 .flags = IORESOURCE_IRQ,
272 },
273 [2] = {
274 .name = "smc91x-attrib",
275 .start = SA1100_CS3_PHYS + 0x02000000,
276 .end = SA1100_CS3_PHYS + 0x03ffffff,
277 .flags = IORESOURCE_MEM,
278 },
279};
361 280
362 err_irq_alloc: 281static struct platform_device smc91x_device = {
363 err_id: 282 .name = "smc91x",
364 iounmap(d->base); 283 .id = 0,
365 err_ioremap: 284 .num_resources = ARRAY_SIZE(smc91x_resources),
366 kfree(d); 285 .resource = smc91x_resources,
367 err_alloc: 286};
368 return ret;
369}
370 287
371static int neponset_remove(struct platform_device *dev) 288static struct platform_device *devices[] __initdata = {
372{ 289 &neponset_device,
373 struct neponset_drvdata *d = platform_get_drvdata(dev); 290 &sa1111_device,
374 int irq = platform_get_irq(dev, 0); 291 &smc91x_device,
375 292};
376 if (!IS_ERR(d->sa1111))
377 platform_device_unregister(d->sa1111);
378 if (!IS_ERR(d->smc91x))
379 platform_device_unregister(d->smc91x);
380 irq_set_chained_handler(irq, NULL);
381 irq_free_descs(d->irq_base, NEP_IRQ_NR);
382 nep_base = NULL;
383 iounmap(d->base);
384 kfree(d);
385 293
386 return 0; 294extern void sa1110_mb_disable(void);
387}
388 295
389#ifdef CONFIG_PM_SLEEP 296static int __init neponset_init(void)
390static int neponset_suspend(struct device *dev)
391{ 297{
392 struct neponset_drvdata *d = dev_get_drvdata(dev); 298 platform_driver_register(&neponset_device_driver);
393 299
394 d->ncr0 = readb_relaxed(d->base + NCR_0); 300 /*
395 d->mdm_ctl_0 = readb_relaxed(d->base + MDM_CTL_0); 301 * The Neponset is only present on the Assabet machine type.
302 */
303 if (!machine_is_assabet())
304 return -ENODEV;
396 305
397 return 0; 306 /*
398} 307 * Ensure that the memory bus request/grant signals are setup,
308 * and the grant is held in its inactive state, whether or not
309 * we actually have a Neponset attached.
310 */
311 sa1110_mb_disable();
399 312
400static int neponset_resume(struct device *dev) 313 if (!machine_has_neponset()) {
401{ 314 printk(KERN_DEBUG "Neponset expansion board not present\n");
402 struct neponset_drvdata *d = dev_get_drvdata(dev); 315 return -ENODEV;
316 }
403 317
404 writeb_relaxed(d->ncr0, d->base + NCR_0); 318 if (WHOAMI != 0x11) {
405 writeb_relaxed(d->mdm_ctl_0, d->base + MDM_CTL_0); 319 printk(KERN_WARNING "Neponset board detected, but "
320 "wrong ID: %02x\n", WHOAMI);
321 return -ENODEV;
322 }
406 323
407 return 0; 324 return platform_add_devices(devices, ARRAY_SIZE(devices));
408} 325}
409 326
410static const struct dev_pm_ops neponset_pm_ops = { 327subsys_initcall(neponset_init);
411 .suspend_noirq = neponset_suspend,
412 .resume_noirq = neponset_resume,
413 .freeze_noirq = neponset_suspend,
414 .restore_noirq = neponset_resume,
415};
416#define PM_OPS &neponset_pm_ops
417#else
418#define PM_OPS NULL
419#endif
420 328
421static struct platform_driver neponset_device_driver = { 329static struct map_desc neponset_io_desc[] __initdata = {
422 .probe = neponset_probe, 330 { /* System Registers */
423 .remove = neponset_remove, 331 .virtual = 0xf3000000,
424 .driver = { 332 .pfn = __phys_to_pfn(0x10000000),
425 .name = "neponset", 333 .length = SZ_1M,
426 .owner = THIS_MODULE, 334 .type = MT_DEVICE
427 .pm = PM_OPS, 335 }, { /* SA-1111 */
428 }, 336 .virtual = 0xf4000000,
337 .pfn = __phys_to_pfn(0x40000000),
338 .length = SZ_1M,
339 .type = MT_DEVICE
340 }
429}; 341};
430 342
431static int __init neponset_init(void) 343void __init neponset_map_io(void)
432{ 344{
433 return platform_driver_register(&neponset_device_driver); 345 iotable_init(neponset_io_desc, ARRAY_SIZE(neponset_io_desc));
434} 346}
435
436subsys_initcall(neponset_init);
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
index ff02e2da99f..dd39fee5954 100644
--- a/arch/arm/mach-sa1100/pci-nanoengine.c
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -129,8 +129,17 @@ static int __init pci_nanoengine_map_irq(const struct pci_dev *dev, u8 slot,
129 return NANOENGINE_IRQ_GPIO_PCI; 129 return NANOENGINE_IRQ_GPIO_PCI;
130} 130}
131 131
132static struct resource pci_io_ports = 132struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys)
133 DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO"); 133{
134 return pci_scan_bus(sys->busnr, &pci_nano_ops, sys);
135}
136
137static struct resource pci_io_ports = {
138 .name = "PCI IO",
139 .start = 0x400,
140 .end = 0x7FF,
141 .flags = IORESOURCE_IO,
142};
134 143
135static struct resource pci_non_prefetchable_memory = { 144static struct resource pci_non_prefetchable_memory = {
136 .name = "PCI non-prefetchable", 145 .name = "PCI non-prefetchable",
@@ -217,7 +226,7 @@ static struct resource pci_prefetchable_memory = {
217 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH, 226 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
218}; 227};
219 228
220static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys) 229static int __init pci_nanoengine_setup_resources(struct resource **resource)
221{ 230{
222 if (request_resource(&ioport_resource, &pci_io_ports)) { 231 if (request_resource(&ioport_resource, &pci_io_ports)) {
223 printk(KERN_ERR "PCI: unable to allocate io port region\n"); 232 printk(KERN_ERR "PCI: unable to allocate io port region\n");
@@ -234,11 +243,9 @@ static int __init pci_nanoengine_setup_resources(struct pci_sys_data *sys)
234 printk(KERN_ERR "PCI: unable to allocate prefetchable\n"); 243 printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
235 return -EBUSY; 244 return -EBUSY;
236 } 245 }
237 pci_add_resource_offset(&sys->resources, &pci_io_ports, sys->io_offset); 246 resource[0] = &pci_io_ports;
238 pci_add_resource_offset(&sys->resources, 247 resource[1] = &pci_non_prefetchable_memory;
239 &pci_non_prefetchable_memory, sys->mem_offset); 248 resource[2] = &pci_prefetchable_memory;
240 pci_add_resource_offset(&sys->resources,
241 &pci_prefetchable_memory, sys->mem_offset);
242 249
243 return 1; 250 return 1;
244} 251}
@@ -253,7 +260,7 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
253 if (nr == 0) { 260 if (nr == 0) {
254 sys->mem_offset = NANO_PCI_MEM_RW_PHYS; 261 sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
255 sys->io_offset = 0x400; 262 sys->io_offset = 0x400;
256 ret = pci_nanoengine_setup_resources(sys); 263 ret = pci_nanoengine_setup_resources(sys->resource);
257 /* Enable alternate memory bus master mode, see 264 /* Enable alternate memory bus master mode, see
258 * "Intel StrongARM SA1110 Developer's Manual", 265 * "Intel StrongARM SA1110 Developer's Manual",
259 * section 10.8, "Alternate Memory Bus Master Mode". */ 266 * section 10.8, "Alternate Memory Bus Master Mode". */
@@ -268,7 +275,7 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
268static struct hw_pci nanoengine_pci __initdata = { 275static struct hw_pci nanoengine_pci __initdata = {
269 .map_irq = pci_nanoengine_map_irq, 276 .map_irq = pci_nanoengine_map_irq,
270 .nr_controllers = 1, 277 .nr_controllers = 1,
271 .ops = &pci_nano_ops, 278 .scan = pci_nanoengine_scan_bus,
272 .setup = pci_nanoengine_setup, 279 .setup = pci_nanoengine_setup,
273}; 280};
274 281
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c
index c51bb63f90f..65161f2bea2 100644
--- a/arch/arm/mach-sa1100/pleb.c
+++ b/arch/arm/mach-sa1100/pleb.c
@@ -6,7 +6,6 @@
6#include <linux/kernel.h> 6#include <linux/kernel.h>
7#include <linux/tty.h> 7#include <linux/tty.h>
8#include <linux/ioport.h> 8#include <linux/ioport.h>
9#include <linux/platform_data/sa11x0-serial.h>
10#include <linux/platform_device.h> 9#include <linux/platform_device.h>
11#include <linux/irq.h> 10#include <linux/irq.h>
12#include <linux/io.h> 11#include <linux/io.h>
@@ -19,6 +18,7 @@
19#include <asm/mach/arch.h> 18#include <asm/mach/arch.h>
20#include <asm/mach/map.h> 19#include <asm/mach/map.h>
21#include <asm/mach/flash.h> 20#include <asm/mach/flash.h>
21#include <asm/mach/serial_sa1100.h>
22#include <mach/irqs.h> 22#include <mach/irqs.h>
23 23
24#include "generic.h" 24#include "generic.h"
@@ -37,9 +37,17 @@
37#define IRQ_GPIO_ETH0_IRQ IRQ_GPIO21 37#define IRQ_GPIO_ETH0_IRQ IRQ_GPIO21
38 38
39static struct resource smc91x_resources[] = { 39static struct resource smc91x_resources[] = {
40 [0] = DEFINE_RES_MEM(PLEB_ETH0_P, 0x04000000), 40 [0] = {
41 .start = PLEB_ETH0_P,
42 .end = PLEB_ETH0_P | 0x03ffffff,
43 .flags = IORESOURCE_MEM,
44 },
41#if 0 /* Autoprobe instead, to get rising/falling edge characteristic right */ 45#if 0 /* Autoprobe instead, to get rising/falling edge characteristic right */
42 [1] = DEFINE_RES_IRQ(IRQ_GPIO_ETH0_IRQ), 46 [1] = {
47 .start = IRQ_GPIO_ETH0_IRQ,
48 .end = IRQ_GPIO_ETH0_IRQ,
49 .flags = IORESOURCE_IRQ,
50 },
43#endif 51#endif
44}; 52};
45 53
@@ -62,8 +70,16 @@ static struct platform_device *devices[] __initdata = {
62 * the two SA1100 lowest chip select outputs. 70 * the two SA1100 lowest chip select outputs.
63 */ 71 */
64static struct resource pleb_flash_resources[] = { 72static struct resource pleb_flash_resources[] = {
65 [0] = DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_8M), 73 [0] = {
66 [1] = DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_8M), 74 .start = SA1100_CS0_PHYS,
75 .end = SA1100_CS0_PHYS + SZ_8M - 1,
76 .flags = IORESOURCE_MEM,
77 },
78 [1] = {
79 .start = SA1100_CS1_PHYS,
80 .end = SA1100_CS1_PHYS + SZ_8M - 1,
81 .flags = IORESOURCE_MEM,
82 }
67}; 83};
68 84
69 85
@@ -131,10 +147,7 @@ static void __init pleb_map_io(void)
131 147
132MACHINE_START(PLEB, "PLEB") 148MACHINE_START(PLEB, "PLEB")
133 .map_io = pleb_map_io, 149 .map_io = pleb_map_io,
134 .nr_irqs = SA1100_NR_IRQS,
135 .init_irq = sa1100_init_irq, 150 .init_irq = sa1100_init_irq,
136 .timer = &sa1100_timer, 151 .timer = &sa1100_timer,
137 .init_machine = pleb_init, 152 .init_machine = pleb_init,
138 .init_late = sa11x0_init_late,
139 .restart = sa11x0_restart,
140MACHINE_END 153MACHINE_END
diff --git a/arch/arm/mach-sa1100/pm.c b/arch/arm/mach-sa1100/pm.c
index 6645d1e31f1..e4512cdb923 100644
--- a/arch/arm/mach-sa1100/pm.c
+++ b/arch/arm/mach-sa1100/pm.c
@@ -23,7 +23,6 @@
23 * Storage is local on the stack now. 23 * Storage is local on the stack now.
24 */ 24 */
25#include <linux/init.h> 25#include <linux/init.h>
26#include <linux/io.h>
27#include <linux/suspend.h> 26#include <linux/suspend.h>
28#include <linux/errno.h> 27#include <linux/errno.h>
29#include <linux/time.h> 28#include <linux/time.h>
@@ -31,6 +30,7 @@
31#include <mach/hardware.h> 30#include <mach/hardware.h>
32#include <asm/memory.h> 31#include <asm/memory.h>
33#include <asm/suspend.h> 32#include <asm/suspend.h>
33#include <asm/system.h>
34#include <asm/mach/time.h> 34#include <asm/mach/time.h>
35 35
36extern int sa1100_finish_suspend(unsigned long); 36extern int sa1100_finish_suspend(unsigned long);
@@ -78,6 +78,8 @@ static int sa11x0_pm_enter(suspend_state_t state)
78 /* go zzz */ 78 /* go zzz */
79 cpu_suspend(0, sa1100_finish_suspend); 79 cpu_suspend(0, sa1100_finish_suspend);
80 80
81 cpu_init();
82
81 /* 83 /*
82 * Ensure not to come back here if it wasn't intended 84 * Ensure not to come back here if it wasn't intended
83 */ 85 */
@@ -118,8 +120,10 @@ static const struct platform_suspend_ops sa11x0_pm_ops = {
118 .valid = suspend_valid_only_mem, 120 .valid = suspend_valid_only_mem,
119}; 121};
120 122
121int __init sa11x0_pm_init(void) 123static int __init sa11x0_pm_init(void)
122{ 124{
123 suspend_set_ops(&sa11x0_pm_ops); 125 suspend_set_ops(&sa11x0_pm_ops);
124 return 0; 126 return 0;
125} 127}
128
129late_initcall(sa11x0_pm_init);
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 6460d25fbb8..7917b240557 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -5,13 +5,10 @@
5#include <linux/init.h> 5#include <linux/init.h>
6#include <linux/device.h> 6#include <linux/device.h>
7#include <linux/kernel.h> 7#include <linux/kernel.h>
8#include <linux/platform_data/sa11x0-serial.h>
9#include <linux/tty.h> 8#include <linux/tty.h>
10#include <linux/mtd/mtd.h> 9#include <linux/mtd/mtd.h>
11#include <linux/mtd/partitions.h> 10#include <linux/mtd/partitions.h>
12 11
13#include <video/sa1100fb.h>
14
15#include <mach/hardware.h> 12#include <mach/hardware.h>
16#include <asm/mach-types.h> 13#include <asm/mach-types.h>
17#include <asm/setup.h> 14#include <asm/setup.h>
@@ -19,9 +16,9 @@
19#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
20#include <asm/mach/flash.h> 17#include <asm/mach/flash.h>
21#include <asm/mach/map.h> 18#include <asm/mach/map.h>
22#include <linux/platform_data/mfd-mcp-sa11x0.h> 19#include <asm/mach/serial_sa1100.h>
20#include <mach/mcp.h>
23#include <mach/shannon.h> 21#include <mach/shannon.h>
24#include <mach/irqs.h>
25 22
26#include "generic.h" 23#include "generic.h"
27 24
@@ -49,32 +46,19 @@ static struct flash_platform_data shannon_flash_data = {
49 .nr_parts = ARRAY_SIZE(shannon_partitions), 46 .nr_parts = ARRAY_SIZE(shannon_partitions),
50}; 47};
51 48
52static struct resource shannon_flash_resource = 49static struct resource shannon_flash_resource = {
53 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_4M); 50 .start = SA1100_CS0_PHYS,
51 .end = SA1100_CS0_PHYS + SZ_4M - 1,
52 .flags = IORESOURCE_MEM,
53};
54 54
55static struct mcp_plat_data shannon_mcp_data = { 55static struct mcp_plat_data shannon_mcp_data = {
56 .mccr0 = MCCR0_ADM, 56 .mccr0 = MCCR0_ADM,
57 .sclk_rate = 11981000, 57 .sclk_rate = 11981000,
58}; 58};
59 59
60static struct sa1100fb_mach_info shannon_lcd_info = {
61 .pixclock = 152500, .bpp = 8,
62 .xres = 640, .yres = 480,
63
64 .hsync_len = 4, .vsync_len = 3,
65 .left_margin = 2, .upper_margin = 0,
66 .right_margin = 1, .lower_margin = 0,
67
68 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
69
70 .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
71 .lccr3 = LCCR3_ACBsDiv(512),
72};
73
74static void __init shannon_init(void) 60static void __init shannon_init(void)
75{ 61{
76 sa11x0_ppc_configure_mcp();
77 sa11x0_register_lcd(&shannon_lcd_info);
78 sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1); 62 sa11x0_register_mtd(&shannon_flash_data, &shannon_flash_resource, 1);
79 sa11x0_register_mcp(&shannon_mcp_data); 63 sa11x0_register_mcp(&shannon_mcp_data);
80} 64}
@@ -98,12 +82,9 @@ static void __init shannon_map_io(void)
98} 82}
99 83
100MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)") 84MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)")
101 .atag_offset = 0x100, 85 .boot_params = 0xc0000100,
102 .map_io = shannon_map_io, 86 .map_io = shannon_map_io,
103 .nr_irqs = SA1100_NR_IRQS,
104 .init_irq = sa1100_init_irq, 87 .init_irq = sa1100_init_irq,
105 .timer = &sa1100_timer, 88 .timer = &sa1100_timer,
106 .init_machine = shannon_init, 89 .init_machine = shannon_init,
107 .init_late = sa11x0_init_late,
108 .restart = sa11x0_restart,
109MACHINE_END 90MACHINE_END
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 6d65f65fcb2..cfb76077bd2 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -7,16 +7,14 @@
7#include <linux/kernel.h> 7#include <linux/kernel.h>
8#include <linux/tty.h> 8#include <linux/tty.h>
9#include <linux/proc_fs.h> 9#include <linux/proc_fs.h>
10#include <linux/string.h> 10#include <linux/string.h>
11#include <linux/pm.h> 11#include <linux/pm.h>
12#include <linux/platform_data/sa11x0-serial.h>
13#include <linux/platform_device.h> 12#include <linux/platform_device.h>
14#include <linux/mfd/ucb1x00.h>
15#include <linux/mtd/mtd.h> 13#include <linux/mtd/mtd.h>
16#include <linux/mtd/partitions.h> 14#include <linux/mtd/partitions.h>
17#include <linux/io.h> 15#include <linux/io.h>
18#include <linux/gpio.h>
19 16
17#include <asm/irq.h>
20#include <mach/hardware.h> 18#include <mach/hardware.h>
21#include <asm/setup.h> 19#include <asm/setup.h>
22 20
@@ -24,98 +22,41 @@
24#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
25#include <asm/mach/flash.h> 23#include <asm/mach/flash.h>
26#include <asm/mach/map.h> 24#include <asm/mach/map.h>
27#include <linux/platform_data/mfd-mcp-sa11x0.h> 25#include <asm/mach/serial_sa1100.h>
26#include <mach/mcp.h>
28#include <mach/simpad.h> 27#include <mach/simpad.h>
29#include <mach/irqs.h>
30 28
31#include <linux/serial_core.h> 29#include <linux/serial_core.h>
32#include <linux/ioport.h> 30#include <linux/ioport.h>
33#include <linux/input.h>
34#include <linux/gpio_keys.h>
35#include <linux/leds.h>
36#include <linux/i2c-gpio.h>
37 31
38#include "generic.h" 32#include "generic.h"
39 33
40/* 34long cs3_shadow;
41 * CS3 support
42 */
43
44static long cs3_shadow;
45static spinlock_t cs3_lock;
46static struct gpio_chip cs3_gpio;
47
48long simpad_get_cs3_ro(void)
49{
50 return readl(CS3_BASE);
51}
52EXPORT_SYMBOL(simpad_get_cs3_ro);
53 35
54long simpad_get_cs3_shadow(void) 36long get_cs3_shadow(void)
55{ 37{
56 return cs3_shadow; 38 return cs3_shadow;
57} 39}
58EXPORT_SYMBOL(simpad_get_cs3_shadow);
59 40
60static void __simpad_write_cs3(void) 41void set_cs3(long value)
61{ 42{
62 writel(cs3_shadow, CS3_BASE); 43 *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow = value;
63} 44}
64 45
65void simpad_set_cs3_bit(int value) 46void set_cs3_bit(int value)
66{ 47{
67 unsigned long flags;
68
69 spin_lock_irqsave(&cs3_lock, flags);
70 cs3_shadow |= value; 48 cs3_shadow |= value;
71 __simpad_write_cs3(); 49 *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow;
72 spin_unlock_irqrestore(&cs3_lock, flags);
73} 50}
74EXPORT_SYMBOL(simpad_set_cs3_bit);
75 51
76void simpad_clear_cs3_bit(int value) 52void clear_cs3_bit(int value)
77{ 53{
78 unsigned long flags;
79
80 spin_lock_irqsave(&cs3_lock, flags);
81 cs3_shadow &= ~value; 54 cs3_shadow &= ~value;
82 __simpad_write_cs3(); 55 *(CS3BUSTYPE *)(CS3_BASE) = cs3_shadow;
83 spin_unlock_irqrestore(&cs3_lock, flags);
84} 56}
85EXPORT_SYMBOL(simpad_clear_cs3_bit);
86 57
87static void cs3_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 58EXPORT_SYMBOL(set_cs3_bit);
88{ 59EXPORT_SYMBOL(clear_cs3_bit);
89 if (offset > 15)
90 return;
91 if (value)
92 simpad_set_cs3_bit(1 << offset);
93 else
94 simpad_clear_cs3_bit(1 << offset);
95};
96
97static int cs3_gpio_get(struct gpio_chip *chip, unsigned offset)
98{
99 if (offset > 15)
100 return simpad_get_cs3_ro() & (1 << (offset - 16));
101 return simpad_get_cs3_shadow() & (1 << offset);
102};
103
104static int cs3_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
105{
106 if (offset > 15)
107 return 0;
108 return -EINVAL;
109};
110
111static int cs3_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
112 int value)
113{
114 if (offset > 15)
115 return -EINVAL;
116 cs3_gpio_set(chip, offset, value);
117 return 0;
118};
119 60
120static struct map_desc simpad_io_desc[] __initdata = { 61static struct map_desc simpad_io_desc[] __initdata = {
121 { /* MQ200 */ 62 { /* MQ200 */
@@ -123,9 +64,9 @@ static struct map_desc simpad_io_desc[] __initdata = {
123 .pfn = __phys_to_pfn(0x4b800000), 64 .pfn = __phys_to_pfn(0x4b800000),
124 .length = 0x00800000, 65 .length = 0x00800000,
125 .type = MT_DEVICE 66 .type = MT_DEVICE
126 }, { /* Simpad CS3 */ 67 }, { /* Paules CS3, write only */
127 .virtual = (unsigned long)CS3_BASE, 68 .virtual = 0xf1000000,
128 .pfn = __phys_to_pfn(SA1100_CS3_PHYS), 69 .pfn = __phys_to_pfn(0x18000000),
129 .length = 0x00100000, 70 .length = 0x00100000,
130 .type = MT_DEVICE 71 .type = MT_DEVICE
131 }, 72 },
@@ -137,12 +78,12 @@ static void simpad_uart_pm(struct uart_port *port, u_int state, u_int oldstate)
137 if (port->mapbase == (u_int)&Ser1UTCR0) { 78 if (port->mapbase == (u_int)&Ser1UTCR0) {
138 if (state) 79 if (state)
139 { 80 {
140 simpad_clear_cs3_bit(RS232_ON); 81 clear_cs3_bit(RS232_ON);
141 simpad_clear_cs3_bit(DECT_POWER_ON); 82 clear_cs3_bit(DECT_POWER_ON);
142 }else 83 }else
143 { 84 {
144 simpad_set_cs3_bit(RS232_ON); 85 set_cs3_bit(RS232_ON);
145 simpad_set_cs3_bit(DECT_POWER_ON); 86 set_cs3_bit(DECT_POWER_ON);
146 } 87 }
147 } 88 }
148} 89}
@@ -177,18 +118,20 @@ static struct flash_platform_data simpad_flash_data = {
177 118
178 119
179static struct resource simpad_flash_resources [] = { 120static struct resource simpad_flash_resources [] = {
180 DEFINE_RES_MEM(SA1100_CS0_PHYS, SZ_16M), 121 {
181 DEFINE_RES_MEM(SA1100_CS1_PHYS, SZ_16M), 122 .start = SA1100_CS0_PHYS,
182}; 123 .end = SA1100_CS0_PHYS + SZ_16M -1,
183 124 .flags = IORESOURCE_MEM,
184static struct ucb1x00_plat_data simpad_ucb1x00_data = { 125 }, {
185 .gpio_base = SIMPAD_UCB1X00_GPIO_BASE, 126 .start = SA1100_CS1_PHYS,
127 .end = SA1100_CS1_PHYS + SZ_16M -1,
128 .flags = IORESOURCE_MEM,
129 }
186}; 130};
187 131
188static struct mcp_plat_data simpad_mcp_data = { 132static struct mcp_plat_data simpad_mcp_data = {
189 .mccr0 = MCCR0_ADM, 133 .mccr0 = MCCR0_ADM,
190 .sclk_rate = 11981000, 134 .sclk_rate = 11981000,
191 .codec_pdata = &simpad_ucb1x00_data,
192}; 135};
193 136
194 137
@@ -199,10 +142,9 @@ static void __init simpad_map_io(void)
199 142
200 iotable_init(simpad_io_desc, ARRAY_SIZE(simpad_io_desc)); 143 iotable_init(simpad_io_desc, ARRAY_SIZE(simpad_io_desc));
201 144
202 /* Initialize CS3 */ 145 set_cs3_bit (EN1 | EN0 | LED2_ON | DISPLAY_ON | RS232_ON |
203 cs3_shadow = (EN1 | EN0 | LED2_ON | DISPLAY_ON | 146 ENABLE_5V | RESET_SIMCARD | DECT_POWER_ON);
204 RS232_ON | ENABLE_5V | RESET_SIMCARD | DECT_POWER_ON); 147
205 __simpad_write_cs3(); /* Spinlocks not yet initialized */
206 148
207 sa1100_register_uart_fns(&simpad_port_fns); 149 sa1100_register_uart_fns(&simpad_port_fns);
208 sa1100_register_uart(0, 3); /* serial interface */ 150 sa1100_register_uart(0, 3); /* serial interface */
@@ -228,14 +170,13 @@ static void __init simpad_map_io(void)
228 170
229static void simpad_power_off(void) 171static void simpad_power_off(void)
230{ 172{
231 local_irq_disable(); 173 local_irq_disable(); // was cli
232 cs3_shadow = SD_MEDIAQ; 174 set_cs3(0x800); /* only SD_MEDIAQ */
233 __simpad_write_cs3(); /* Bypass spinlock here */
234 175
235 /* disable internal oscillator, float CS lines */ 176 /* disable internal oscillator, float CS lines */
236 PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS); 177 PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
237 /* enable wake-up on GPIO0 */ 178 /* enable wake-up on GPIO0 (Assabet...) */
238 PWER = GFER = GRER = PWER_GPIO0; 179 PWER = GFER = GRER = 1;
239 /* 180 /*
240 * set scratchpad to zero, just in case it is used as a 181 * set scratchpad to zero, just in case it is used as a
241 * restart address by the bootloader. 182 * restart address by the bootloader.
@@ -251,91 +192,6 @@ static void simpad_power_off(void)
251 192
252} 193}
253 194
254/*
255 * gpio_keys
256*/
257
258static struct gpio_keys_button simpad_button_table[] = {
259 { KEY_POWER, IRQ_GPIO_POWER_BUTTON, 1, "power button" },
260};
261
262static struct gpio_keys_platform_data simpad_keys_data = {
263 .buttons = simpad_button_table,
264 .nbuttons = ARRAY_SIZE(simpad_button_table),
265};
266
267static struct platform_device simpad_keys = {
268 .name = "gpio-keys",
269 .dev = {
270 .platform_data = &simpad_keys_data,
271 },
272};
273
274static struct gpio_keys_button simpad_polled_button_table[] = {
275 { KEY_PROG1, SIMPAD_UCB1X00_GPIO_PROG1, 1, "prog1 button" },
276 { KEY_PROG2, SIMPAD_UCB1X00_GPIO_PROG2, 1, "prog2 button" },
277 { KEY_UP, SIMPAD_UCB1X00_GPIO_UP, 1, "up button" },
278 { KEY_DOWN, SIMPAD_UCB1X00_GPIO_DOWN, 1, "down button" },
279 { KEY_LEFT, SIMPAD_UCB1X00_GPIO_LEFT, 1, "left button" },
280 { KEY_RIGHT, SIMPAD_UCB1X00_GPIO_RIGHT, 1, "right button" },
281};
282
283static struct gpio_keys_platform_data simpad_polled_keys_data = {
284 .buttons = simpad_polled_button_table,
285 .nbuttons = ARRAY_SIZE(simpad_polled_button_table),
286 .poll_interval = 50,
287};
288
289static struct platform_device simpad_polled_keys = {
290 .name = "gpio-keys-polled",
291 .dev = {
292 .platform_data = &simpad_polled_keys_data,
293 },
294};
295
296/*
297 * GPIO LEDs
298 */
299
300static struct gpio_led simpad_leds[] = {
301 {
302 .name = "simpad:power",
303 .gpio = SIMPAD_CS3_LED2_ON,
304 .active_low = 0,
305 .default_trigger = "default-on",
306 },
307};
308
309static struct gpio_led_platform_data simpad_led_data = {
310 .num_leds = ARRAY_SIZE(simpad_leds),
311 .leds = simpad_leds,
312};
313
314static struct platform_device simpad_gpio_leds = {
315 .name = "leds-gpio",
316 .id = 0,
317 .dev = {
318 .platform_data = &simpad_led_data,
319 },
320};
321
322/*
323 * i2c
324 */
325static struct i2c_gpio_platform_data simpad_i2c_data = {
326 .sda_pin = GPIO_GPIO21,
327 .scl_pin = GPIO_GPIO25,
328 .udelay = 10,
329 .timeout = HZ,
330};
331
332static struct platform_device simpad_i2c = {
333 .name = "i2c-gpio",
334 .id = 0,
335 .dev = {
336 .platform_data = &simpad_i2c_data,
337 },
338};
339 195
340/* 196/*
341 * MediaQ Video Device 197 * MediaQ Video Device
@@ -346,11 +202,7 @@ static struct platform_device simpad_mq200fb = {
346}; 202};
347 203
348static struct platform_device *devices[] __initdata = { 204static struct platform_device *devices[] __initdata = {
349 &simpad_keys, 205 &simpad_mq200fb
350 &simpad_polled_keys,
351 &simpad_mq200fb,
352 &simpad_gpio_leds,
353 &simpad_i2c,
354}; 206};
355 207
356 208
@@ -359,22 +211,8 @@ static int __init simpad_init(void)
359{ 211{
360 int ret; 212 int ret;
361 213
362 spin_lock_init(&cs3_lock);
363
364 cs3_gpio.label = "simpad_cs3";
365 cs3_gpio.base = SIMPAD_CS3_GPIO_BASE;
366 cs3_gpio.ngpio = 24;
367 cs3_gpio.set = cs3_gpio_set;
368 cs3_gpio.get = cs3_gpio_get;
369 cs3_gpio.direction_input = cs3_gpio_direction_input;
370 cs3_gpio.direction_output = cs3_gpio_direction_output;
371 ret = gpiochip_add(&cs3_gpio);
372 if (ret)
373 printk(KERN_WARNING "simpad: Unable to register cs3 GPIO device");
374
375 pm_power_off = simpad_power_off; 214 pm_power_off = simpad_power_off;
376 215
377 sa11x0_ppc_configure_mcp();
378 sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources, 216 sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources,
379 ARRAY_SIZE(simpad_flash_resources)); 217 ARRAY_SIZE(simpad_flash_resources));
380 sa11x0_register_mcp(&simpad_mcp_data); 218 sa11x0_register_mcp(&simpad_mcp_data);
@@ -391,11 +229,8 @@ arch_initcall(simpad_init);
391 229
392MACHINE_START(SIMPAD, "Simpad") 230MACHINE_START(SIMPAD, "Simpad")
393 /* Maintainer: Holger Freyther */ 231 /* Maintainer: Holger Freyther */
394 .atag_offset = 0x100, 232 .boot_params = 0xc0000100,
395 .map_io = simpad_map_io, 233 .map_io = simpad_map_io,
396 .nr_irqs = SA1100_NR_IRQS,
397 .init_irq = sa1100_init_irq, 234 .init_irq = sa1100_init_irq,
398 .init_late = sa11x0_init_late,
399 .timer = &sa1100_timer, 235 .timer = &sa1100_timer,
400 .restart = sa11x0_restart,
401MACHINE_END 236MACHINE_END
diff --git a/arch/arm/mach-sa1100/sleep.S b/arch/arm/mach-sa1100/sleep.S
index 85863741ef8..e8223315b44 100644
--- a/arch/arm/mach-sa1100/sleep.S
+++ b/arch/arm/mach-sa1100/sleep.S
@@ -26,38 +26,29 @@
26 * 26 *
27 * Causes sa11x0 to enter sleep state 27 * Causes sa11x0 to enter sleep state
28 * 28 *
29 * Must be aligned to a cacheline.
30 */ 29 */
31 .balign 32 30
32ENTRY(sa1100_finish_suspend) 31ENTRY(sa1100_finish_suspend)
33 @ disable clock switching 32 @ disable clock switching
34 mcr p15, 0, r1, c15, c2, 2 33 mcr p15, 0, r1, c15, c2, 2
35 34
36 ldr r6, =MDREFR 35 @ Adjust memory timing before lowering CPU clock
37 ldr r4, [r6] 36 @ Clock speed adjustment without changing memory timing makes
38 orr r4, r4, #MDREFR_K1DB2 37 @ CPU hang in some cases
39 ldr r5, =PPCR 38 ldr r0, =MDREFR
40 39 ldr r1, [r0]
41 @ Pre-load __loop_udelay into the I-cache 40 orr r1, r1, #MDREFR_K1DB2
42 mov r0, #1 41 str r1, [r0]
43 bl __loop_udelay
44 mov r0, r0
45
46 @ The following must all exist in a single cache line to
47 @ avoid accessing memory until this sequence is complete,
48 @ otherwise we occasionally hang.
49
50 @ Adjust memory timing before lowering CPU clock
51 str r4, [r6]
52 42
53 @ delay 90us and set CPU PLL to lowest speed 43 @ delay 90us and set CPU PLL to lowest speed
54 @ fixes resume problem on high speed SA1110 44 @ fixes resume problem on high speed SA1110
55 mov r0, #90 45 mov r0, #90
56 bl __loop_udelay 46 bl __udelay
47 ldr r0, =PPCR
57 mov r1, #0 48 mov r1, #0
58 str r1, [r5] 49 str r1, [r0]
59 mov r0, #90 50 mov r0, #90
60 bl __loop_udelay 51 bl __udelay
61 52
62 /* 53 /*
63 * SA1110 SDRAM controller workaround. register values: 54 * SA1110 SDRAM controller workaround. register values:
@@ -94,10 +85,12 @@ ENTRY(sa1100_finish_suspend)
94 bic r5, r5, #FMsk(MSC_RT) 85 bic r5, r5, #FMsk(MSC_RT)
95 bic r5, r5, #FMsk(MSC_RT)<<16 86 bic r5, r5, #FMsk(MSC_RT)<<16
96 87
88 ldr r6, =MDREFR
89
97 ldr r7, [r6] 90 ldr r7, [r6]
98 bic r7, r7, #0x0000FF00 91bic r7, r7, #0x0000FF00
99 bic r7, r7, #0x000000F0 92bic r7, r7, #0x000000F0
100 orr r8, r7, #MDREFR_SLFRSH 93orr r8, r7, #MDREFR_SLFRSH
101 94
102 ldr r9, =MDCNFG 95 ldr r9, =MDCNFG
103 ldr r10, [r9] 96 ldr r10, [r9]
diff --git a/arch/arm/mach-sa1100/ssp.c b/arch/arm/mach-sa1100/ssp.c
index e22fca9ad5e..b20ff93b84a 100644
--- a/arch/arm/mach-sa1100/ssp.c
+++ b/arch/arm/mach-sa1100/ssp.c
@@ -19,8 +19,8 @@
19#include <linux/init.h> 19#include <linux/init.h>
20#include <linux/io.h> 20#include <linux/io.h>
21 21
22#include <asm/irq.h>
22#include <mach/hardware.h> 23#include <mach/hardware.h>
23#include <mach/irqs.h>
24#include <asm/hardware/ssp.h> 24#include <asm/hardware/ssp.h>
25 25
26#define TIMEOUT 100000 26#define TIMEOUT 100000
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 80702c9ecc7..fa6602491d5 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -12,17 +12,37 @@
12#include <linux/errno.h> 12#include <linux/errno.h>
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14#include <linux/irq.h> 14#include <linux/irq.h>
15#include <linux/sched.h> /* just for sched_clock() - funny that */
15#include <linux/timex.h> 16#include <linux/timex.h>
16#include <linux/clockchips.h> 17#include <linux/clockchips.h>
17 18
18#include <asm/mach/time.h> 19#include <asm/mach/time.h>
19#include <asm/sched_clock.h> 20#include <asm/sched_clock.h>
20#include <mach/hardware.h> 21#include <mach/hardware.h>
21#include <mach/irqs.h>
22 22
23static u32 notrace sa1100_read_sched_clock(void) 23/*
24 * This is the SA11x0 sched_clock implementation.
25 */
26static DEFINE_CLOCK_DATA(cd);
27
28/*
29 * Constants generated by clocks_calc_mult_shift(m, s, 3.6864MHz,
30 * NSEC_PER_SEC, 60).
31 * This gives a resolution of about 271ns and a wrap period of about 19min.
32 */
33#define SC_MULT 2275555556u
34#define SC_SHIFT 23
35
36unsigned long long notrace sched_clock(void)
37{
38 u32 cyc = OSCR;
39 return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
40}
41
42static void notrace sa1100_update_sched_clock(void)
24{ 43{
25 return readl_relaxed(OSCR); 44 u32 cyc = OSCR;
45 update_sched_clock(&cd, cyc, (u32)~0);
26} 46}
27 47
28#define MIN_OSCR_DELTA 2 48#define MIN_OSCR_DELTA 2
@@ -32,8 +52,8 @@ static irqreturn_t sa1100_ost0_interrupt(int irq, void *dev_id)
32 struct clock_event_device *c = dev_id; 52 struct clock_event_device *c = dev_id;
33 53
34 /* Disarm the compare/match, signal the event. */ 54 /* Disarm the compare/match, signal the event. */
35 writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER); 55 OIER &= ~OIER_E0;
36 writel_relaxed(OSSR_M0, OSSR); 56 OSSR = OSSR_M0;
37 c->event_handler(c); 57 c->event_handler(c);
38 58
39 return IRQ_HANDLED; 59 return IRQ_HANDLED;
@@ -44,10 +64,10 @@ sa1100_osmr0_set_next_event(unsigned long delta, struct clock_event_device *c)
44{ 64{
45 unsigned long next, oscr; 65 unsigned long next, oscr;
46 66
47 writel_relaxed(readl_relaxed(OIER) | OIER_E0, OIER); 67 OIER |= OIER_E0;
48 next = readl_relaxed(OSCR) + delta; 68 next = OSCR + delta;
49 writel_relaxed(next, OSMR0); 69 OSMR0 = next;
50 oscr = readl_relaxed(OSCR); 70 oscr = OSCR;
51 71
52 return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0; 72 return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
53} 73}
@@ -59,8 +79,8 @@ sa1100_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *c)
59 case CLOCK_EVT_MODE_ONESHOT: 79 case CLOCK_EVT_MODE_ONESHOT:
60 case CLOCK_EVT_MODE_UNUSED: 80 case CLOCK_EVT_MODE_UNUSED:
61 case CLOCK_EVT_MODE_SHUTDOWN: 81 case CLOCK_EVT_MODE_SHUTDOWN:
62 writel_relaxed(readl_relaxed(OIER) & ~OIER_E0, OIER); 82 OIER &= ~OIER_E0;
63 writel_relaxed(OSSR_M0, OSSR); 83 OSSR = OSSR_M0;
64 break; 84 break;
65 85
66 case CLOCK_EVT_MODE_RESUME: 86 case CLOCK_EVT_MODE_RESUME:
@@ -86,10 +106,11 @@ static struct irqaction sa1100_timer_irq = {
86 106
87static void __init sa1100_timer_init(void) 107static void __init sa1100_timer_init(void)
88{ 108{
89 writel_relaxed(0, OIER); 109 OIER = 0;
90 writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); 110 OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
91 111
92 setup_sched_clock(sa1100_read_sched_clock, 32, 3686400); 112 init_fixed_sched_clock(&cd, sa1100_update_sched_clock, 32,
113 3686400, SC_MULT, SC_SHIFT);
93 114
94 clockevents_calc_mult_shift(&ckevt_sa1100_osmr0, 3686400, 4); 115 clockevents_calc_mult_shift(&ckevt_sa1100_osmr0, 3686400, 4);
95 ckevt_sa1100_osmr0.max_delta_ns = 116 ckevt_sa1100_osmr0.max_delta_ns =
@@ -100,7 +121,7 @@ static void __init sa1100_timer_init(void)
100 121
101 setup_irq(IRQ_OST0, &sa1100_timer_irq); 122 setup_irq(IRQ_OST0, &sa1100_timer_irq);
102 123
103 clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32, 124 clocksource_mmio_init(&OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
104 clocksource_mmio_readl_up); 125 clocksource_mmio_readl_up);
105 clockevents_register_device(&ckevt_sa1100_osmr0); 126 clockevents_register_device(&ckevt_sa1100_osmr0);
106} 127}
@@ -110,26 +131,26 @@ unsigned long osmr[4], oier;
110 131
111static void sa1100_timer_suspend(void) 132static void sa1100_timer_suspend(void)
112{ 133{
113 osmr[0] = readl_relaxed(OSMR0); 134 osmr[0] = OSMR0;
114 osmr[1] = readl_relaxed(OSMR1); 135 osmr[1] = OSMR1;
115 osmr[2] = readl_relaxed(OSMR2); 136 osmr[2] = OSMR2;
116 osmr[3] = readl_relaxed(OSMR3); 137 osmr[3] = OSMR3;
117 oier = readl_relaxed(OIER); 138 oier = OIER;
118} 139}
119 140
120static void sa1100_timer_resume(void) 141static void sa1100_timer_resume(void)
121{ 142{
122 writel_relaxed(0x0f, OSSR); 143 OSSR = 0x0f;
123 writel_relaxed(osmr[0], OSMR0); 144 OSMR0 = osmr[0];
124 writel_relaxed(osmr[1], OSMR1); 145 OSMR1 = osmr[1];
125 writel_relaxed(osmr[2], OSMR2); 146 OSMR2 = osmr[2];
126 writel_relaxed(osmr[3], OSMR3); 147 OSMR3 = osmr[3];
127 writel_relaxed(oier, OIER); 148 OIER = oier;
128 149
129 /* 150 /*
130 * OSMR0 is the system timer: make sure OSCR is sufficiently behind 151 * OSMR0 is the system timer: make sure OSCR is sufficiently behind
131 */ 152 */
132 writel_relaxed(OSMR0 - LATCH, OSCR); 153 OSCR = OSMR0 - LATCH;
133} 154}
134#else 155#else
135#define sa1100_timer_suspend NULL 156#define sa1100_timer_suspend NULL
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 07:34:29 -0400