1 files changed, 235 insertions, 10 deletions

diff --git a/arch/arm/mach-sa1100/include/mach/SA-1100.h b/arch/arm/mach-sa1100/include/mach/SA-1100.h
index 0ac6cc08a19..bae8296f5db 100644
--- a/arch/arm/mach-sa1100/include/mach/SA-1100.h
+++ b/arch/arm/mach-sa1100/include/mach/SA-1100.h
@@ -830,14 +830,14 @@
  *                      (read/write).
  */
 
-#define OSMR0           io_p2v(0x90000000)  /* OS timer Match Reg. 0 */
-#define OSMR1           io_p2v(0x90000004)  /* OS timer Match Reg. 1 */
-#define OSMR2           io_p2v(0x90000008)  /* OS timer Match Reg. 2 */
-#define OSMR3           io_p2v(0x9000000c)  /* OS timer Match Reg. 3 */
-#define OSCR            io_p2v(0x90000010)  /* OS timer Counter Reg. */
-#define OSSR            io_p2v(0x90000014)  /* OS timer Status Reg. */
-#define OWER            io_p2v(0x90000018)  /* OS timer Watch-dog Enable Reg. */
-#define OIER            io_p2v(0x9000001C)  /* OS timer Interrupt Enable Reg. */
+#define OSMR0           __REG(0x90000000)  /* OS timer Match Reg. 0 */
+#define OSMR1           __REG(0x90000004)  /* OS timer Match Reg. 1 */
+#define OSMR2           __REG(0x90000008)  /* OS timer Match Reg. 2 */
+#define OSMR3           __REG(0x9000000c)  /* OS timer Match Reg. 3 */
+#define OSCR    __REG(0x90000010)  /* OS timer Counter Reg. */
+#define OSSR    __REG(0x90000014        )  /* OS timer Status Reg. */
+#define OWER    __REG(0x90000018        )  /* OS timer Watch-dog Enable Reg. */
+#define OIER    __REG(0x9000001C        )  /* OS timer Interrupt Enable Reg. */
 
 #define OSSR_M(Nb)                      /* Match detected [0..3]           */ \
                         (0x00000001 << (Nb))
@@ -1590,9 +1590,224 @@
 
 /*
  * Direct Memory Access (DMA) control registers
+ *
+ * Registers
+ *    DDAR0             Direct Memory Access (DMA) Device Address Register
+ *                      channel 0 (read/write).
+ *    DCSR0             Direct Memory Access (DMA) Control and Status
+ *                      Register channel 0 (read/write).
+ *    DBSA0             Direct Memory Access (DMA) Buffer Start address
+ *                      register A channel 0 (read/write).
+ *    DBTA0             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register A channel 0 (read/write).
+ *    DBSB0             Direct Memory Access (DMA) Buffer Start address
+ *                      register B channel 0 (read/write).
+ *    DBTB0             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register B channel 0 (read/write).
+ *
+ *    DDAR1             Direct Memory Access (DMA) Device Address Register
+ *                      channel 1 (read/write).
+ *    DCSR1             Direct Memory Access (DMA) Control and Status
+ *                      Register channel 1 (read/write).
+ *    DBSA1             Direct Memory Access (DMA) Buffer Start address
+ *                      register A channel 1 (read/write).
+ *    DBTA1             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register A channel 1 (read/write).
+ *    DBSB1             Direct Memory Access (DMA) Buffer Start address
+ *                      register B channel 1 (read/write).
+ *    DBTB1             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register B channel 1 (read/write).
+ *
+ *    DDAR2             Direct Memory Access (DMA) Device Address Register
+ *                      channel 2 (read/write).
+ *    DCSR2             Direct Memory Access (DMA) Control and Status
+ *                      Register channel 2 (read/write).
+ *    DBSA2             Direct Memory Access (DMA) Buffer Start address
+ *                      register A channel 2 (read/write).
+ *    DBTA2             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register A channel 2 (read/write).
+ *    DBSB2             Direct Memory Access (DMA) Buffer Start address
+ *                      register B channel 2 (read/write).
+ *    DBTB2             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register B channel 2 (read/write).
+ *
+ *    DDAR3             Direct Memory Access (DMA) Device Address Register
+ *                      channel 3 (read/write).
+ *    DCSR3             Direct Memory Access (DMA) Control and Status
+ *                      Register channel 3 (read/write).
+ *    DBSA3             Direct Memory Access (DMA) Buffer Start address
+ *                      register A channel 3 (read/write).
+ *    DBTA3             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register A channel 3 (read/write).
+ *    DBSB3             Direct Memory Access (DMA) Buffer Start address
+ *                      register B channel 3 (read/write).
+ *    DBTB3             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register B channel 3 (read/write).
+ *
+ *    DDAR4             Direct Memory Access (DMA) Device Address Register
+ *                      channel 4 (read/write).
+ *    DCSR4             Direct Memory Access (DMA) Control and Status
+ *                      Register channel 4 (read/write).
+ *    DBSA4             Direct Memory Access (DMA) Buffer Start address
+ *                      register A channel 4 (read/write).
+ *    DBTA4             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register A channel 4 (read/write).
+ *    DBSB4             Direct Memory Access (DMA) Buffer Start address
+ *                      register B channel 4 (read/write).
+ *    DBTB4             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register B channel 4 (read/write).
+ *
+ *    DDAR5             Direct Memory Access (DMA) Device Address Register
+ *                      channel 5 (read/write).
+ *    DCSR5             Direct Memory Access (DMA) Control and Status
+ *                      Register channel 5 (read/write).
+ *    DBSA5             Direct Memory Access (DMA) Buffer Start address
+ *                      register A channel 5 (read/write).
+ *    DBTA5             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register A channel 5 (read/write).
+ *    DBSB5             Direct Memory Access (DMA) Buffer Start address
+ *                      register B channel 5 (read/write).
+ *    DBTB5             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register B channel 5 (read/write).
  */
-#define DMA_SIZE        (6 * 0x20)
-#define DMA_PHYS        0xb0000000
+
+#define DMASp           0x00000020      /* DMA control reg. Space [byte]   */
+
+#define DDAR(Nb)        __REG(0xB0000000 + (Nb)*DMASp)  /* DMA Device Address Reg. channel [0..5] */
+#define SetDCSR(Nb)     __REG(0xB0000004 + (Nb)*DMASp)  /* Set DMA Control & Status Reg. channel [0..5] (write) */
+#define ClrDCSR(Nb)     __REG(0xB0000008 + (Nb)*DMASp)  /* Clear DMA Control & Status Reg. channel [0..5] (write) */
+#define RdDCSR(Nb)      __REG(0xB000000C + (Nb)*DMASp)  /* Read DMA Control & Status Reg. channel [0..5] (read) */
+#define DBSA(Nb)        __REG(0xB0000010 + (Nb)*DMASp)  /* DMA Buffer Start address reg. A channel [0..5] */
+#define DBTA(Nb)        __REG(0xB0000014 + (Nb)*DMASp)  /* DMA Buffer Transfer count reg. A channel [0..5] */
+#define DBSB(Nb)        __REG(0xB0000018 + (Nb)*DMASp)  /* DMA Buffer Start address reg. B channel [0..5] */
+#define DBTB(Nb)        __REG(0xB000001C + (Nb)*DMASp)  /* DMA Buffer Transfer count reg. B channel [0..5] */
+
+#define DDAR_RW         0x00000001      /* device data Read/Write          */
+#define DDAR_DevWr      (DDAR_RW*0)     /*  Device data Write              */
+                                        /*  (memory -> device)             */
+#define DDAR_DevRd      (DDAR_RW*1)     /*  Device data Read               */
+                                        /*  (device -> memory)             */
+#define DDAR_E          0x00000002      /* big/little Endian device        */
+#define DDAR_LtlEnd     (DDAR_E*0)      /*  Little Endian device           */
+#define DDAR_BigEnd     (DDAR_E*1)      /*  Big Endian device              */
+#define DDAR_BS         0x00000004      /* device Burst Size               */
+#define DDAR_Brst4      (DDAR_BS*0)     /*  Burst-of-4 device              */
+#define DDAR_Brst8      (DDAR_BS*1)     /*  Burst-of-8 device              */
+#define DDAR_DW         0x00000008      /* device Data Width               */
+#define DDAR_8BitDev    (DDAR_DW*0)     /*  8-Bit Device                   */
+#define DDAR_16BitDev   (DDAR_DW*1)     /*  16-Bit Device                  */
+#define DDAR_DS         Fld (4, 4)      /* Device Select                   */
+#define DDAR_Ser0UDCTr                  /*  Ser. port 0 UDC Transmit       */ \
+                        (0x0 << FShft (DDAR_DS))
+#define DDAR_Ser0UDCRc                  /*  Ser. port 0 UDC Receive        */ \
+                        (0x1 << FShft (DDAR_DS))
+#define DDAR_Ser1SDLCTr                 /*  Ser. port 1 SDLC Transmit      */ \
+                        (0x2 << FShft (DDAR_DS))
+#define DDAR_Ser1SDLCRc                 /*  Ser. port 1 SDLC Receive       */ \
+                        (0x3 << FShft (DDAR_DS))
+#define DDAR_Ser1UARTTr                 /*  Ser. port 1 UART Transmit      */ \
+                        (0x4 << FShft (DDAR_DS))
+#define DDAR_Ser1UARTRc                 /*  Ser. port 1 UART Receive       */ \
+                        (0x5 << FShft (DDAR_DS))
+#define DDAR_Ser2ICPTr                  /*  Ser. port 2 ICP Transmit       */ \
+                        (0x6 << FShft (DDAR_DS))
+#define DDAR_Ser2ICPRc                  /*  Ser. port 2 ICP Receive        */ \
+                        (0x7 << FShft (DDAR_DS))
+#define DDAR_Ser3UARTTr                 /*  Ser. port 3 UART Transmit      */ \
+                        (0x8 << FShft (DDAR_DS))
+#define DDAR_Ser3UARTRc                 /*  Ser. port 3 UART Receive       */ \
+                        (0x9 << FShft (DDAR_DS))
+#define DDAR_Ser4MCP0Tr                 /*  Ser. port 4 MCP 0 Transmit     */ \
+                                        /*  (audio)                        */ \
+                        (0xA << FShft (DDAR_DS))
+#define DDAR_Ser4MCP0Rc                 /*  Ser. port 4 MCP 0 Receive      */ \
+                                        /*  (audio)                        */ \
+                        (0xB << FShft (DDAR_DS))
+#define DDAR_Ser4MCP1Tr                 /*  Ser. port 4 MCP 1 Transmit     */ \
+                                        /*  (telecom)                      */ \
+                        (0xC << FShft (DDAR_DS))
+#define DDAR_Ser4MCP1Rc                 /*  Ser. port 4 MCP 1 Receive      */ \
+                                        /*  (telecom)                      */ \
+                        (0xD << FShft (DDAR_DS))
+#define DDAR_Ser4SSPTr                  /*  Ser. port 4 SSP Transmit       */ \
+                        (0xE << FShft (DDAR_DS))
+#define DDAR_Ser4SSPRc                  /*  Ser. port 4 SSP Receive        */ \
+                        (0xF << FShft (DDAR_DS))
+#define DDAR_DA         Fld (24, 8)     /* Device Address                  */
+#define DDAR_DevAdd(Add)                /*  Device Address                 */ \
+                        (((Add) & 0xF0000000) | \
+                         (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
+#define DDAR_Ser0UDCWr                  /* Ser. port 0 UDC Write           */ \
+                        (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
+                         DDAR_Ser0UDCTr + DDAR_DevAdd (__PREG(Ser0UDCDR)))
+#define DDAR_Ser0UDCRd                  /* Ser. port 0 UDC Read            */ \
+                        (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
+                         DDAR_Ser0UDCRc + DDAR_DevAdd (__PREG(Ser0UDCDR)))
+#define DDAR_Ser1UARTWr                 /* Ser. port 1 UART Write          */ \
+                        (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser1UARTTr + DDAR_DevAdd (__PREG(Ser1UTDR)))
+#define DDAR_Ser1UARTRd                 /* Ser. port 1 UART Read           */ \
+                        (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser1UARTRc + DDAR_DevAdd (__PREG(Ser1UTDR)))
+#define DDAR_Ser1SDLCWr                 /* Ser. port 1 SDLC Write          */ \
+                        (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser1SDLCTr + DDAR_DevAdd (__PREG(Ser1SDDR)))
+#define DDAR_Ser1SDLCRd                 /* Ser. port 1 SDLC Read           */ \
+                        (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser1SDLCRc + DDAR_DevAdd (__PREG(Ser1SDDR)))
+#define DDAR_Ser2UARTWr                 /* Ser. port 2 UART Write          */ \
+                        (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2UTDR)))
+#define DDAR_Ser2UARTRd                 /* Ser. port 2 UART Read           */ \
+                        (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2UTDR)))
+#define DDAR_Ser2HSSPWr                 /* Ser. port 2 HSSP Write          */ \
+                        (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
+                         DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2HSDR)))
+#define DDAR_Ser2HSSPRd                 /* Ser. port 2 HSSP Read           */ \
+                        (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
+                         DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2HSDR)))
+#define DDAR_Ser3UARTWr                 /* Ser. port 3 UART Write          */ \
+                        (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser3UARTTr + DDAR_DevAdd (__PREG(Ser3UTDR)))
+#define DDAR_Ser3UARTRd                 /* Ser. port 3 UART Read           */ \
+                        (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser3UARTRc + DDAR_DevAdd (__PREG(Ser3UTDR)))
+#define DDAR_Ser4MCP0Wr                 /* Ser. port 4 MCP 0 Write (audio) */ \
+                        (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
+                         DDAR_Ser4MCP0Tr + DDAR_DevAdd (__PREG(Ser4MCDR0)))
+#define DDAR_Ser4MCP0Rd                 /* Ser. port 4 MCP 0 Read (audio)  */ \
+                        (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
+                         DDAR_Ser4MCP0Rc + DDAR_DevAdd (__PREG(Ser4MCDR0)))
+#define DDAR_Ser4MCP1Wr                 /* Ser. port 4 MCP 1 Write         */ \
+                                        /* (telecom)                       */ \
+                        (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
+                         DDAR_Ser4MCP1Tr + DDAR_DevAdd (__PREG(Ser4MCDR1)))
+#define DDAR_Ser4MCP1Rd                 /* Ser. port 4 MCP 1 Read          */ \
+                                        /* (telecom)                       */ \
+                        (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
+                         DDAR_Ser4MCP1Rc + DDAR_DevAdd (__PREG(Ser4MCDR1)))
+#define DDAR_Ser4SSPWr                  /* Ser. port 4 SSP Write (16 bits) */ \
+                        (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
+                         DDAR_Ser4SSPTr + DDAR_DevAdd (__PREG(Ser4SSDR)))
+#define DDAR_Ser4SSPRd                  /* Ser. port 4 SSP Read (16 bits)  */ \
+                        (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
+                         DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR)))
+
+#define DCSR_RUN        0x00000001      /* DMA running                     */
+#define DCSR_IE         0x00000002      /* DMA Interrupt Enable            */
+#define DCSR_ERROR      0x00000004      /* DMA ERROR                       */
+#define DCSR_DONEA      0x00000008      /* DONE DMA transfer buffer A      */
+#define DCSR_STRTA      0x00000010      /* STaRTed DMA transfer buffer A   */
+#define DCSR_DONEB      0x00000020      /* DONE DMA transfer buffer B      */
+#define DCSR_STRTB      0x00000040      /* STaRTed DMA transfer buffer B   */
+#define DCSR_BIU        0x00000080      /* DMA Buffer In Use               */
+#define DCSR_BufA       (DCSR_BIU*0)    /*  DMA Buffer A in use            */
+#define DCSR_BufB       (DCSR_BIU*1)    /*  DMA Buffer B in use            */
+
+#define DBT_TC          Fld (13, 0)     /* Transfer Count                  */
+#define DBTA_TCA        DBT_TC          /* Transfer Count buffer A         */
+#define DBTB_TCB        DBT_TC          /* Transfer Count buffer B         */
 
 
 /*
@@ -1688,6 +1903,16 @@
 #define LCD_Int100_0A   0xF             /* LCD Intensity = 100.0% =  1     */
                                         /* (Alternative)                   */
 
+#define LCCR0           __REG(0xB0100000)  /* LCD Control Reg. 0 */
+#define LCSR            __REG(0xB0100004)  /* LCD Status Reg. */
+#define DBAR1           __REG(0xB0100010)  /* LCD DMA Base Address Reg. channel 1 */
+#define DCAR1           __REG(0xB0100014)  /* LCD DMA Current Address Reg. channel 1 */
+#define DBAR2           __REG(0xB0100018)  /* LCD DMA Base Address Reg.  channel 2 */
+#define DCAR2           __REG(0xB010001C)  /* LCD DMA Current Address Reg. channel 2 */
+#define LCCR1           __REG(0xB0100020)  /* LCD Control Reg. 1 */
+#define LCCR2           __REG(0xB0100024)  /* LCD Control Reg. 2 */
+#define LCCR3           __REG(0xB0100028)  /* LCD Control Reg. 3 */
+
 #define LCCR0_LEN       0x00000001      /* LCD ENable                      */
 #define LCCR0_CMS       0x00000002      /* Color/Monochrome display Select */
 #define LCCR0_Color     (LCCR0_CMS*0)   /*  Color display                  */