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-rw-r--r--drivers/gpu/pvr/Makefile12
-rw-r--r--drivers/gpu/pvr/bridged_pvr_bridge.c6912
-rw-r--r--drivers/gpu/pvr/bridged_pvr_bridge.h2
-rw-r--r--drivers/gpu/pvr/bridged_support.c6
-rw-r--r--drivers/gpu/pvr/bridged_support.h4
-rw-r--r--drivers/gpu/pvr/buffer_manager.c453
-rw-r--r--drivers/gpu/pvr/buffer_manager.h5
-rw-r--r--drivers/gpu/pvr/dbgdrvif.h113
-rw-r--r--drivers/gpu/pvr/device.h2
-rw-r--r--drivers/gpu/pvr/deviceclass.c119
-rw-r--r--drivers/gpu/pvr/devicemem.c211
-rw-r--r--drivers/gpu/pvr/handle.c292
-rw-r--r--drivers/gpu/pvr/handle.h25
-rw-r--r--drivers/gpu/pvr/hash.c34
-rw-r--r--drivers/gpu/pvr/hash.h7
-rw-r--r--drivers/gpu/pvr/img_types.h24
-rw-r--r--drivers/gpu/pvr/ioctldef.h98
-rw-r--r--drivers/gpu/pvr/mem.c10
-rw-r--r--drivers/gpu/pvr/mm.c8
-rw-r--r--drivers/gpu/pvr/mm.h6
-rw-r--r--drivers/gpu/pvr/mmap.c48
-rw-r--r--drivers/gpu/pvr/mmap.h17
-rw-r--r--drivers/gpu/pvr/module.c63
-rw-r--r--drivers/gpu/pvr/omap4/sysconfig.c255
-rw-r--r--drivers/gpu/pvr/omap4/sysconfig.h50
-rw-r--r--drivers/gpu/pvr/omap4/sysinfo.h23
-rw-r--r--drivers/gpu/pvr/omap4/syslocal.h65
-rw-r--r--drivers/gpu/pvr/omap4/sysutils.c21
-rw-r--r--drivers/gpu/pvr/omap4/sysutils_linux.c537
-rw-r--r--drivers/gpu/pvr/omap4/sysutils_linux_wqueue_compat.c198
-rw-r--r--drivers/gpu/pvr/osfunc.c179
-rw-r--r--drivers/gpu/pvr/osfunc.h40
-rw-r--r--drivers/gpu/pvr/pdump_common.c224
-rw-r--r--drivers/gpu/pvr/pdump_km.h14
-rw-r--r--drivers/gpu/pvr/pdumpdefs.h9
-rw-r--r--drivers/gpu/pvr/perproc.c10
-rw-r--r--drivers/gpu/pvr/perproc.h13
-rw-r--r--drivers/gpu/pvr/power.c21
-rw-r--r--drivers/gpu/pvr/private_data.h28
-rw-r--r--drivers/gpu/pvr/pvr_bridge.h655
-rw-r--r--drivers/gpu/pvr/pvr_bridge_k.c161
-rw-r--r--drivers/gpu/pvr/pvr_bridge_km.h20
-rw-r--r--drivers/gpu/pvr/pvr_debug.h1
-rw-r--r--drivers/gpu/pvr/pvrmmap.h8
-rw-r--r--drivers/gpu/pvr/pvrsrv.c62
-rw-r--r--drivers/gpu/pvr/pvrsrv_errors.h2
-rw-r--r--drivers/gpu/pvr/pvrversion.h8
-rw-r--r--drivers/gpu/pvr/queue.c146
-rw-r--r--drivers/gpu/pvr/queue.h3
-rw-r--r--drivers/gpu/pvr/ra.c2
-rw-r--r--drivers/gpu/pvr/resman.c17
-rw-r--r--drivers/gpu/pvr/resman.h3
-rw-r--r--drivers/gpu/pvr/services.h268
-rw-r--r--drivers/gpu/pvr/servicesext.h232
-rw-r--r--drivers/gpu/pvr/servicesint.h117
-rw-r--r--drivers/gpu/pvr/sgx/bridged_sgx_bridge.c1041
-rw-r--r--drivers/gpu/pvr/sgx/mmu.c806
-rw-r--r--drivers/gpu/pvr/sgx/mmu.h8
-rw-r--r--drivers/gpu/pvr/sgx/pb.c8
-rw-r--r--drivers/gpu/pvr/sgx/sgx_bridge_km.h28
-rw-r--r--drivers/gpu/pvr/sgx/sgxconfig.h147
-rw-r--r--drivers/gpu/pvr/sgx/sgxinfokm.h201
-rw-r--r--drivers/gpu/pvr/sgx/sgxinit.c441
-rw-r--r--drivers/gpu/pvr/sgx/sgxkick.c46
-rw-r--r--drivers/gpu/pvr/sgx/sgxpower.c15
-rw-r--r--drivers/gpu/pvr/sgx/sgxreset.c430
-rw-r--r--drivers/gpu/pvr/sgx/sgxtransfer.c120
-rw-r--r--drivers/gpu/pvr/sgx/sgxutils.c301
-rw-r--r--drivers/gpu/pvr/sgx/sgxutils.h19
-rw-r--r--drivers/gpu/pvr/sgx531defs.h544
-rw-r--r--drivers/gpu/pvr/sgx535defs.h650
-rw-r--r--drivers/gpu/pvr/sgx543_v1.164defs.h1284
-rw-r--r--drivers/gpu/pvr/sgx543defs.h400
-rw-r--r--drivers/gpu/pvr/sgx544defs.h1351
-rw-r--r--drivers/gpu/pvr/sgx_bridge.h189
-rw-r--r--drivers/gpu/pvr/sgx_mkif_km.h63
-rw-r--r--drivers/gpu/pvr/sgx_options.h58
-rw-r--r--drivers/gpu/pvr/sgxapi_km.h64
-rw-r--r--drivers/gpu/pvr/sgxdefs.h16
-rw-r--r--drivers/gpu/pvr/sgxerrata.h154
-rw-r--r--drivers/gpu/pvr/sgxfeaturedefs.h90
-rw-r--r--drivers/gpu/pvr/sgxinfo.h196
-rw-r--r--drivers/gpu/pvr/sgxmmu.h19
-rw-r--r--drivers/gpu/pvr/sgxmpdefs.h30
-rw-r--r--drivers/gpu/pvr/syscommon.h52
-rw-r--r--drivers/gpu/pvr/ttrace.h184
-rw-r--r--drivers/gpu/pvr/ttrace_common.h81
-rw-r--r--drivers/gpu/pvr/ttrace_tokens.h84
88 files changed, 15497 insertions, 5486 deletions
diff --git a/drivers/gpu/pvr/Makefile b/drivers/gpu/pvr/Makefile
index 0dc058d364d..d537d081489 100644
--- a/drivers/gpu/pvr/Makefile
+++ b/drivers/gpu/pvr/Makefile
@@ -26,8 +26,12 @@ ccflags-y = -DLINUX -D__linux__ -Idrivers/gpu/pvr \
26 -DPVR_LINUX_MISR_USING_PRIVATE_WORKQUEUE \ 26 -DPVR_LINUX_MISR_USING_PRIVATE_WORKQUEUE \
27 -DSYS_CUSTOM_POWERLOCK_WRAP \ 27 -DSYS_CUSTOM_POWERLOCK_WRAP \
28 -DSUPPORT_SGX_NEW_STATUS_VALS \ 28 -DSUPPORT_SGX_NEW_STATUS_VALS \
29 -DSYS_OMAP3430_PIN_MEMORY_BUS_CLOCK \ 29 -DSYS_OMAP3430_PIN_MEMORY_BUS_CLOCK \
30 -DSGX_EARLYSUSPEND \ 30 -DSGX_EARLYSUSPEND \
31 -DSUPPORT_DBGDRV_EVENT_OBJECTS \
32 -DPVR_NO_OMAP_TIMER \
33 -DSUPPORT_DYNAMIC_GTF_TIMING \
34 -DSUPPORT_SGX_LOW_LATENCY_SCHEDULING \
31 -DPVRSRV_MODNAME="\"pvrsrvkm"\" 35 -DPVRSRV_MODNAME="\"pvrsrvkm"\"
32 36
33ccflags-$(CONFIG_SGX540) += -Idrivers/gpu/pvr/omap4 -Idrivers/gpu/pvr/sgx \ 37ccflags-$(CONFIG_SGX540) += -Idrivers/gpu/pvr/omap4 -Idrivers/gpu/pvr/sgx \
@@ -48,8 +52,7 @@ ccflags-$(CONFIG_SGX_530_BUILD_RELEASE) += \
48 -DPVR_BUILD_TYPE="\"release\"" \ 52 -DPVR_BUILD_TYPE="\"release\"" \
49 -DRELEASE \ 53 -DRELEASE \
50 -DSUPPORT_ACTIVE_POWER_MANAGEMENT \ 54 -DSUPPORT_ACTIVE_POWER_MANAGEMENT \
51 -DSUPPORT_HW_RECOVERY \ 55 -DSUPPORT_HW_RECOVERY
52 -DSUPPORT_SGX_LOW_LATENCY_SCHEDULING
53 56
54ccflags-$(CONFIG_SGX_530_BUILD_DEBUG) += \ 57ccflags-$(CONFIG_SGX_530_BUILD_DEBUG) += \
55 -DPVR_BUILD_TYPE="\"debug\"" -DDEBUG \ 58 -DPVR_BUILD_TYPE="\"debug\"" -DDEBUG \
@@ -65,8 +68,7 @@ ccflags-$(CONFIG_SGX_540_BUILD_RELEASE) += \
65 -DPVR_BUILD_TYPE="\"release\"" \ 68 -DPVR_BUILD_TYPE="\"release\"" \
66 -DRELEASE \ 69 -DRELEASE \
67 -DSUPPORT_ACTIVE_POWER_MANAGEMENT \ 70 -DSUPPORT_ACTIVE_POWER_MANAGEMENT \
68 -DPVR_NO_FULL_CACHE_OPS \ 71 -DPVR_NO_FULL_CACHE_OPS
69 -DSUPPORT_SGX_LOW_LATENCY_SCHEDULING
70 72
71ccflags-$(CONFIG_SGX_540_BUILD_DEBUG) += \ 73ccflags-$(CONFIG_SGX_540_BUILD_DEBUG) += \
72 -DPVR_BUILD_TYPE="\"debug\"" -DDEBUG \ 74 -DPVR_BUILD_TYPE="\"debug\"" -DDEBUG \
diff --git a/drivers/gpu/pvr/bridged_pvr_bridge.c b/drivers/gpu/pvr/bridged_pvr_bridge.c
index f0dde100218..b06a7a394a6 100644
--- a/drivers/gpu/pvr/bridged_pvr_bridge.c
+++ b/drivers/gpu/pvr/bridged_pvr_bridge.c
@@ -1,26 +1,26 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation. 7 * version 2, as published by the Free Software Foundation.
8 * 8 *
9 * This program is distributed in the hope it will be useful but, except 9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the 10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose. 11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details. 12 * See the GNU General Public License for more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with 14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 * 17 *
18 * The full GNU General Public License is included in this distribution in 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING". 19 * the file called "COPYING".
20 * 20 *
21 * Contact Information: 21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com> 22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK 23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 * 24 *
25 ******************************************************************************/ 25 ******************************************************************************/
26 26
@@ -76,7 +76,7 @@ PVRSRV_BRIDGE_DISPATCH_TABLE_ENTRY g_BridgeDispatchTable[BRIDGE_DISPATCH_TABLE_E
76PVRSRV_BRIDGE_GLOBAL_STATS g_BridgeGlobalStats; 76PVRSRV_BRIDGE_GLOBAL_STATS g_BridgeGlobalStats;
77#endif 77#endif
78 78
79#if defined(PVR_SECURE_HANDLES) 79#if defined(PVR_SECURE_HANDLES) || defined (SUPPORT_SID_INTERFACE)
80static IMG_BOOL abSharedDeviceMemHeap[PVRSRV_MAX_CLIENT_HEAPS]; 80static IMG_BOOL abSharedDeviceMemHeap[PVRSRV_MAX_CLIENT_HEAPS];
81static IMG_BOOL *pbSharedDeviceMemHeap = abSharedDeviceMemHeap; 81static IMG_BOOL *pbSharedDeviceMemHeap = abSharedDeviceMemHeap;
82#else 82#else
@@ -87,1500 +87,1972 @@ static IMG_BOOL *pbSharedDeviceMemHeap = (IMG_BOOL*)IMG_NULL;
87#if defined(DEBUG_BRIDGE_KM) 87#if defined(DEBUG_BRIDGE_KM)
88PVRSRV_ERROR 88PVRSRV_ERROR
89CopyFromUserWrapper(PVRSRV_PER_PROCESS_DATA *pProcData, 89CopyFromUserWrapper(PVRSRV_PER_PROCESS_DATA *pProcData,
90 IMG_UINT32 ui32BridgeID, 90 IMG_UINT32 ui32BridgeID,
91 IMG_VOID *pvDest, 91 IMG_VOID *pvDest,
92 IMG_VOID *pvSrc, 92 IMG_VOID *pvSrc,
93 IMG_UINT32 ui32Size) 93 IMG_UINT32 ui32Size)
94{ 94{
95 g_BridgeDispatchTable[ui32BridgeID].ui32CopyFromUserTotalBytes+=ui32Size; 95 g_BridgeDispatchTable[ui32BridgeID].ui32CopyFromUserTotalBytes+=ui32Size;
96 g_BridgeGlobalStats.ui32TotalCopyFromUserBytes+=ui32Size; 96 g_BridgeGlobalStats.ui32TotalCopyFromUserBytes+=ui32Size;
97 return OSCopyFromUser(pProcData, pvDest, pvSrc, ui32Size); 97 return OSCopyFromUser(pProcData, pvDest, pvSrc, ui32Size);
98} 98}
99PVRSRV_ERROR 99PVRSRV_ERROR
100CopyToUserWrapper(PVRSRV_PER_PROCESS_DATA *pProcData, 100CopyToUserWrapper(PVRSRV_PER_PROCESS_DATA *pProcData,
101 IMG_UINT32 ui32BridgeID, 101 IMG_UINT32 ui32BridgeID,
102 IMG_VOID *pvDest, 102 IMG_VOID *pvDest,
103 IMG_VOID *pvSrc, 103 IMG_VOID *pvSrc,
104 IMG_UINT32 ui32Size) 104 IMG_UINT32 ui32Size)
105{ 105{
106 g_BridgeDispatchTable[ui32BridgeID].ui32CopyToUserTotalBytes+=ui32Size; 106 g_BridgeDispatchTable[ui32BridgeID].ui32CopyToUserTotalBytes+=ui32Size;
107 g_BridgeGlobalStats.ui32TotalCopyToUserBytes+=ui32Size; 107 g_BridgeGlobalStats.ui32TotalCopyToUserBytes+=ui32Size;
108 return OSCopyToUser(pProcData, pvDest, pvSrc, ui32Size); 108 return OSCopyToUser(pProcData, pvDest, pvSrc, ui32Size);
109} 109}
110#endif 110#endif
111 111
112 112
113static IMG_INT 113static IMG_INT
114PVRSRVEnumerateDevicesBW(IMG_UINT32 ui32BridgeID, 114PVRSRVEnumerateDevicesBW(IMG_UINT32 ui32BridgeID,
115 IMG_VOID *psBridgeIn, 115 IMG_VOID *psBridgeIn,
116 PVRSRV_BRIDGE_OUT_ENUMDEVICE *psEnumDeviceOUT, 116 PVRSRV_BRIDGE_OUT_ENUMDEVICE *psEnumDeviceOUT,
117 PVRSRV_PER_PROCESS_DATA *psPerProc) 117 PVRSRV_PER_PROCESS_DATA *psPerProc)
118{ 118{
119 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ENUM_DEVICES); 119 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ENUM_DEVICES);
120 120
121 PVR_UNREFERENCED_PARAMETER(psPerProc); 121 PVR_UNREFERENCED_PARAMETER(psPerProc);
122 PVR_UNREFERENCED_PARAMETER(psBridgeIn); 122 PVR_UNREFERENCED_PARAMETER(psBridgeIn);
123 123
124 psEnumDeviceOUT->eError = 124 psEnumDeviceOUT->eError =
125 PVRSRVEnumerateDevicesKM(&psEnumDeviceOUT->ui32NumDevices, 125 PVRSRVEnumerateDevicesKM(&psEnumDeviceOUT->ui32NumDevices,
126 psEnumDeviceOUT->asDeviceIdentifier); 126 psEnumDeviceOUT->asDeviceIdentifier);
127 127
128 return 0; 128 return 0;
129} 129}
130 130
131static IMG_INT 131static IMG_INT
132PVRSRVAcquireDeviceDataBW(IMG_UINT32 ui32BridgeID, 132PVRSRVAcquireDeviceDataBW(IMG_UINT32 ui32BridgeID,
133 PVRSRV_BRIDGE_IN_ACQUIRE_DEVICEINFO *psAcquireDevInfoIN, 133 PVRSRV_BRIDGE_IN_ACQUIRE_DEVICEINFO *psAcquireDevInfoIN,
134 PVRSRV_BRIDGE_OUT_ACQUIRE_DEVICEINFO *psAcquireDevInfoOUT, 134 PVRSRV_BRIDGE_OUT_ACQUIRE_DEVICEINFO *psAcquireDevInfoOUT,
135 PVRSRV_PER_PROCESS_DATA *psPerProc) 135 PVRSRV_PER_PROCESS_DATA *psPerProc)
136{ 136{
137 IMG_HANDLE hDevCookieInt; 137 IMG_HANDLE hDevCookieInt;
138 138
139 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ACQUIRE_DEVICEINFO); 139 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ACQUIRE_DEVICEINFO);
140
141 psAcquireDevInfoOUT->eError =
142 PVRSRVAcquireDeviceDataKM(psAcquireDevInfoIN->uiDevIndex,
143 psAcquireDevInfoIN->eDeviceType,
144 &hDevCookieInt);
145 if(psAcquireDevInfoOUT->eError != PVRSRV_OK)
146 {
147 return 0;
148 }
140 149
141 psAcquireDevInfoOUT->eError =
142 PVRSRVAcquireDeviceDataKM(psAcquireDevInfoIN->uiDevIndex,
143 psAcquireDevInfoIN->eDeviceType,
144 &hDevCookieInt);
145 if(psAcquireDevInfoOUT->eError != PVRSRV_OK)
146 {
147 return 0;
148 }
149 150
150 psAcquireDevInfoOUT->eError = 151 psAcquireDevInfoOUT->eError =
151 PVRSRVAllocHandle(psPerProc->psHandleBase, 152 PVRSRVAllocHandle(psPerProc->psHandleBase,
152 &psAcquireDevInfoOUT->hDevCookie, 153 &psAcquireDevInfoOUT->hDevCookie,
153 hDevCookieInt, 154 hDevCookieInt,
154 PVRSRV_HANDLE_TYPE_DEV_NODE, 155 PVRSRV_HANDLE_TYPE_DEV_NODE,
155 PVRSRV_HANDLE_ALLOC_FLAG_SHARED); 156 PVRSRV_HANDLE_ALLOC_FLAG_SHARED);
156 157
157 return 0; 158 return 0;
158} 159}
159 160
160 161
161static IMG_INT 162static IMG_INT
162PVRSRVCreateDeviceMemContextBW(IMG_UINT32 ui32BridgeID, 163PVRSRVCreateDeviceMemContextBW(IMG_UINT32 ui32BridgeID,
163 PVRSRV_BRIDGE_IN_CREATE_DEVMEMCONTEXT *psCreateDevMemContextIN, 164 PVRSRV_BRIDGE_IN_CREATE_DEVMEMCONTEXT *psCreateDevMemContextIN,
164 PVRSRV_BRIDGE_OUT_CREATE_DEVMEMCONTEXT *psCreateDevMemContextOUT, 165 PVRSRV_BRIDGE_OUT_CREATE_DEVMEMCONTEXT *psCreateDevMemContextOUT,
165 PVRSRV_PER_PROCESS_DATA *psPerProc) 166 PVRSRV_PER_PROCESS_DATA *psPerProc)
166{ 167{
167 IMG_HANDLE hDevCookieInt; 168 IMG_HANDLE hDevCookieInt;
168 IMG_HANDLE hDevMemContextInt; 169 IMG_HANDLE hDevMemContextInt;
169 IMG_UINT32 i; 170 IMG_UINT32 i;
170 IMG_BOOL bCreated; 171 IMG_BOOL bCreated;
171 172#if defined (SUPPORT_SID_INTERFACE)
172 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_CREATE_DEVMEMCONTEXT); 173 PVRSRV_HEAP_INFO_KM asHeapInfo[PVRSRV_MAX_CLIENT_HEAPS];
173 174#endif
174 NEW_HANDLE_BATCH_OR_ERROR(psCreateDevMemContextOUT->eError, psPerProc, PVRSRV_MAX_CLIENT_HEAPS + 1)
175 175
176 psCreateDevMemContextOUT->eError = 176 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_CREATE_DEVMEMCONTEXT);
177 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt,
178 psCreateDevMemContextIN->hDevCookie,
179 PVRSRV_HANDLE_TYPE_DEV_NODE);
180 177
181 if(psCreateDevMemContextOUT->eError != PVRSRV_OK)
182 {
183 return 0;
184 }
185 178
186 psCreateDevMemContextOUT->eError = 179 NEW_HANDLE_BATCH_OR_ERROR(psCreateDevMemContextOUT->eError, psPerProc, PVRSRV_MAX_CLIENT_HEAPS + 1)
187 PVRSRVCreateDeviceMemContextKM(hDevCookieInt,
188 psPerProc,
189 &hDevMemContextInt,
190 &psCreateDevMemContextOUT->ui32ClientHeapCount,
191 &psCreateDevMemContextOUT->sHeapInfo[0],
192 &bCreated,
193 pbSharedDeviceMemHeap);
194 180
195 if(psCreateDevMemContextOUT->eError != PVRSRV_OK) 181 psCreateDevMemContextOUT->eError =
196 { 182 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt,
197 return 0; 183 psCreateDevMemContextIN->hDevCookie,
198 } 184 PVRSRV_HANDLE_TYPE_DEV_NODE);
199 185
186 if(psCreateDevMemContextOUT->eError != PVRSRV_OK)
187 {
188 return 0;
189 }
200 190
201 if(bCreated) 191 psCreateDevMemContextOUT->eError =
202 { 192 PVRSRVCreateDeviceMemContextKM(hDevCookieInt,
203 PVRSRVAllocHandleNR(psPerProc->psHandleBase, 193 psPerProc,
204 &psCreateDevMemContextOUT->hDevMemContext, 194 &hDevMemContextInt,
205 hDevMemContextInt, 195 &psCreateDevMemContextOUT->ui32ClientHeapCount,
206 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT, 196#if defined (SUPPORT_SID_INTERFACE)
207 PVRSRV_HANDLE_ALLOC_FLAG_NONE); 197 &asHeapInfo[0],
208 } 198#else
209 else 199 &psCreateDevMemContextOUT->sHeapInfo[0],
210 { 200#endif
211 psCreateDevMemContextOUT->eError = 201 &bCreated,
212 PVRSRVFindHandle(psPerProc->psHandleBase, 202 pbSharedDeviceMemHeap);
213 &psCreateDevMemContextOUT->hDevMemContext, 203
214 hDevMemContextInt, 204 if(psCreateDevMemContextOUT->eError != PVRSRV_OK)
215 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT); 205 {
216 if(psCreateDevMemContextOUT->eError != PVRSRV_OK) 206 return 0;
217 { 207 }
218 return 0; 208
219 } 209
220 } 210 if(bCreated)
211 {
212 PVRSRVAllocHandleNR(psPerProc->psHandleBase,
213 &psCreateDevMemContextOUT->hDevMemContext,
214 hDevMemContextInt,
215 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT,
216 PVRSRV_HANDLE_ALLOC_FLAG_NONE);
217 }
218 else
219 {
220 psCreateDevMemContextOUT->eError =
221 PVRSRVFindHandle(psPerProc->psHandleBase,
222 &psCreateDevMemContextOUT->hDevMemContext,
223 hDevMemContextInt,
224 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT);
225 if(psCreateDevMemContextOUT->eError != PVRSRV_OK)
226 {
227 return 0;
228 }
229 }
230
231 for(i = 0; i < psCreateDevMemContextOUT->ui32ClientHeapCount; i++)
232 {
233#if defined (SUPPORT_SID_INTERFACE)
234 IMG_SID hDevMemHeapExt;
235#else
236 IMG_HANDLE hDevMemHeapExt;
237#endif
221 238
222 for(i = 0; i < psCreateDevMemContextOUT->ui32ClientHeapCount; i++) 239#if defined(PVR_SECURE_HANDLES) || defined (SUPPORT_SID_INTERFACE)
223 { 240 if(abSharedDeviceMemHeap[i])
224 IMG_HANDLE hDevMemHeapExt; 241#endif
225 242 {
226#if defined(PVR_SECURE_HANDLES) 243
227 if(abSharedDeviceMemHeap[i]) 244#if defined (SUPPORT_SID_INTERFACE)
228#endif 245 PVRSRVAllocHandleNR(psPerProc->psHandleBase,
229 { 246 &hDevMemHeapExt,
230 247 asHeapInfo[i].hDevMemHeap,
231 PVRSRVAllocHandleNR(psPerProc->psHandleBase, &hDevMemHeapExt, 248 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP,
232 psCreateDevMemContextOUT->sHeapInfo[i].hDevMemHeap, 249 PVRSRV_HANDLE_ALLOC_FLAG_SHARED);
233 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP, 250#else
234 PVRSRV_HANDLE_ALLOC_FLAG_SHARED); 251 PVRSRVAllocHandleNR(psPerProc->psHandleBase, &hDevMemHeapExt,
235 } 252 psCreateDevMemContextOUT->sHeapInfo[i].hDevMemHeap,
236#if defined(PVR_SECURE_HANDLES) 253 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP,
237 else 254 PVRSRV_HANDLE_ALLOC_FLAG_SHARED);
238 { 255#endif
239 256 }
240 if(bCreated) 257#if defined(PVR_SECURE_HANDLES) || defined (SUPPORT_SID_INTERFACE)
241 { 258 else
242 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase, &hDevMemHeapExt, 259 {
243 psCreateDevMemContextOUT->sHeapInfo[i].hDevMemHeap, 260
244 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP, 261 if(bCreated)
245 PVRSRV_HANDLE_ALLOC_FLAG_NONE, 262 {
246 psCreateDevMemContextOUT->hDevMemContext); 263#if defined (SUPPORT_SID_INTERFACE)
247 } 264 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
248 else 265 &hDevMemHeapExt,
249 { 266 asHeapInfo[i].hDevMemHeap,
250 psCreateDevMemContextOUT->eError = 267 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP,
251 PVRSRVFindHandle(psPerProc->psHandleBase, &hDevMemHeapExt, 268 PVRSRV_HANDLE_ALLOC_FLAG_NONE,
252 psCreateDevMemContextOUT->sHeapInfo[i].hDevMemHeap, 269 psCreateDevMemContextOUT->hDevMemContext);
253 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP); 270#else
254 if(psCreateDevMemContextOUT->eError != PVRSRV_OK) 271 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase, &hDevMemHeapExt,
255 { 272 psCreateDevMemContextOUT->sHeapInfo[i].hDevMemHeap,
256 return 0; 273 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP,
257 } 274 PVRSRV_HANDLE_ALLOC_FLAG_NONE,
258 } 275 psCreateDevMemContextOUT->hDevMemContext);
259 } 276#endif
260#endif 277 }
261 psCreateDevMemContextOUT->sHeapInfo[i].hDevMemHeap = hDevMemHeapExt; 278 else
262 } 279 {
280 psCreateDevMemContextOUT->eError =
281 PVRSRVFindHandle(psPerProc->psHandleBase,
282 &hDevMemHeapExt,
283#if defined (SUPPORT_SID_INTERFACE)
284 asHeapInfo[i].hDevMemHeap,
285#else
286 psCreateDevMemContextOUT->sHeapInfo[i].hDevMemHeap,
287#endif
288 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP);
289 if(psCreateDevMemContextOUT->eError != PVRSRV_OK)
290 {
291 return 0;
292 }
293 }
294 }
295#endif
296 psCreateDevMemContextOUT->sHeapInfo[i].hDevMemHeap = hDevMemHeapExt;
297#if defined (SUPPORT_SID_INTERFACE)
298 psCreateDevMemContextOUT->sHeapInfo[i].ui32HeapID = asHeapInfo[i].ui32HeapID;
299 psCreateDevMemContextOUT->sHeapInfo[i].sDevVAddrBase = asHeapInfo[i].sDevVAddrBase;
300 psCreateDevMemContextOUT->sHeapInfo[i].ui32HeapByteSize = asHeapInfo[i].ui32HeapByteSize;
301 psCreateDevMemContextOUT->sHeapInfo[i].ui32Attribs = asHeapInfo[i].ui32Attribs;
302 psCreateDevMemContextOUT->sHeapInfo[i].ui32XTileStride = asHeapInfo[i].ui32XTileStride;
303#endif
304 }
263 305
264 COMMIT_HANDLE_BATCH_OR_ERROR(psCreateDevMemContextOUT->eError, psPerProc) 306 COMMIT_HANDLE_BATCH_OR_ERROR(psCreateDevMemContextOUT->eError, psPerProc)
265 307
266 return 0; 308 return 0;
267} 309}
268 310
269static IMG_INT 311static IMG_INT
270PVRSRVDestroyDeviceMemContextBW(IMG_UINT32 ui32BridgeID, 312PVRSRVDestroyDeviceMemContextBW(IMG_UINT32 ui32BridgeID,
271 PVRSRV_BRIDGE_IN_DESTROY_DEVMEMCONTEXT *psDestroyDevMemContextIN, 313 PVRSRV_BRIDGE_IN_DESTROY_DEVMEMCONTEXT *psDestroyDevMemContextIN,
272 PVRSRV_BRIDGE_RETURN *psRetOUT, 314 PVRSRV_BRIDGE_RETURN *psRetOUT,
273 PVRSRV_PER_PROCESS_DATA *psPerProc) 315 PVRSRV_PER_PROCESS_DATA *psPerProc)
274{ 316{
275 IMG_HANDLE hDevCookieInt; 317 IMG_HANDLE hDevCookieInt;
276 IMG_HANDLE hDevMemContextInt; 318 IMG_HANDLE hDevMemContextInt;
277 IMG_BOOL bDestroyed; 319 IMG_BOOL bDestroyed;
278 320
279 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_DESTROY_DEVMEMCONTEXT); 321 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_DESTROY_DEVMEMCONTEXT);
280 322
281 psRetOUT->eError = 323 psRetOUT->eError =
282 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt, 324 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt,
283 psDestroyDevMemContextIN->hDevCookie, 325 psDestroyDevMemContextIN->hDevCookie,
284 PVRSRV_HANDLE_TYPE_DEV_NODE); 326 PVRSRV_HANDLE_TYPE_DEV_NODE);
285 327
286 if(psRetOUT->eError != PVRSRV_OK) 328 if(psRetOUT->eError != PVRSRV_OK)
287 { 329 {
288 return 0; 330 return 0;
289 } 331 }
290 332
291 psRetOUT->eError = 333 psRetOUT->eError =
292 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevMemContextInt, 334 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevMemContextInt,
293 psDestroyDevMemContextIN->hDevMemContext, 335 psDestroyDevMemContextIN->hDevMemContext,
294 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT); 336 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT);
295 337
296 if(psRetOUT->eError != PVRSRV_OK) 338 if(psRetOUT->eError != PVRSRV_OK)
297 { 339 {
298 return 0; 340 return 0;
299 } 341 }
300 342
301 psRetOUT->eError = 343 psRetOUT->eError =
302 PVRSRVDestroyDeviceMemContextKM(hDevCookieInt, hDevMemContextInt, &bDestroyed); 344 PVRSRVDestroyDeviceMemContextKM(hDevCookieInt, hDevMemContextInt, &bDestroyed);
303 345
304 if(psRetOUT->eError != PVRSRV_OK) 346 if(psRetOUT->eError != PVRSRV_OK)
305 { 347 {
306 return 0; 348 return 0;
307 } 349 }
308 350
309 if(bDestroyed) 351 if(bDestroyed)
310 { 352 {
311 psRetOUT->eError = 353 psRetOUT->eError =
312 PVRSRVReleaseHandle(psPerProc->psHandleBase, 354 PVRSRVReleaseHandle(psPerProc->psHandleBase,
313 psDestroyDevMemContextIN->hDevMemContext, 355 psDestroyDevMemContextIN->hDevMemContext,
314 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT); 356 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT);
315 } 357 }
316 358
317 return 0; 359 return 0;
318} 360}
319 361
320 362
321static IMG_INT 363static IMG_INT
322PVRSRVGetDeviceMemHeapInfoBW(IMG_UINT32 ui32BridgeID, 364PVRSRVGetDeviceMemHeapInfoBW(IMG_UINT32 ui32BridgeID,
323 PVRSRV_BRIDGE_IN_GET_DEVMEM_HEAPINFO *psGetDevMemHeapInfoIN, 365 PVRSRV_BRIDGE_IN_GET_DEVMEM_HEAPINFO *psGetDevMemHeapInfoIN,
324 PVRSRV_BRIDGE_OUT_GET_DEVMEM_HEAPINFO *psGetDevMemHeapInfoOUT, 366 PVRSRV_BRIDGE_OUT_GET_DEVMEM_HEAPINFO *psGetDevMemHeapInfoOUT,
325 PVRSRV_PER_PROCESS_DATA *psPerProc) 367 PVRSRV_PER_PROCESS_DATA *psPerProc)
326{ 368{
327 IMG_HANDLE hDevCookieInt; 369 IMG_HANDLE hDevCookieInt;
328 IMG_HANDLE hDevMemContextInt; 370 IMG_HANDLE hDevMemContextInt;
329 IMG_UINT32 i; 371 IMG_UINT32 i;
372#if defined (SUPPORT_SID_INTERFACE)
373 PVRSRV_HEAP_INFO_KM asHeapInfo[PVRSRV_MAX_CLIENT_HEAPS];
374#endif
330 375
331 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GET_DEVMEM_HEAPINFO); 376 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GET_DEVMEM_HEAPINFO);
332 377
333 NEW_HANDLE_BATCH_OR_ERROR(psGetDevMemHeapInfoOUT->eError, psPerProc, PVRSRV_MAX_CLIENT_HEAPS) 378 NEW_HANDLE_BATCH_OR_ERROR(psGetDevMemHeapInfoOUT->eError, psPerProc, PVRSRV_MAX_CLIENT_HEAPS)
334 379
335 psGetDevMemHeapInfoOUT->eError = 380 psGetDevMemHeapInfoOUT->eError =
336 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt, 381 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt,
337 psGetDevMemHeapInfoIN->hDevCookie, 382 psGetDevMemHeapInfoIN->hDevCookie,
338 PVRSRV_HANDLE_TYPE_DEV_NODE); 383 PVRSRV_HANDLE_TYPE_DEV_NODE);
339 384
340 if(psGetDevMemHeapInfoOUT->eError != PVRSRV_OK) 385 if(psGetDevMemHeapInfoOUT->eError != PVRSRV_OK)
341 { 386 {
342 return 0; 387 return 0;
343 } 388 }
344 389
345 psGetDevMemHeapInfoOUT->eError = 390 psGetDevMemHeapInfoOUT->eError =
346 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevMemContextInt, 391 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevMemContextInt,
347 psGetDevMemHeapInfoIN->hDevMemContext, 392 psGetDevMemHeapInfoIN->hDevMemContext,
348 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT); 393 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT);
349 394
350 if(psGetDevMemHeapInfoOUT->eError != PVRSRV_OK) 395 if(psGetDevMemHeapInfoOUT->eError != PVRSRV_OK)
351 { 396 {
352 return 0; 397 return 0;
353 } 398 }
354 399
355 psGetDevMemHeapInfoOUT->eError = 400 psGetDevMemHeapInfoOUT->eError =
356 PVRSRVGetDeviceMemHeapInfoKM(hDevCookieInt, 401 PVRSRVGetDeviceMemHeapInfoKM(hDevCookieInt,
357 hDevMemContextInt, 402 hDevMemContextInt,
358 &psGetDevMemHeapInfoOUT->ui32ClientHeapCount, 403 &psGetDevMemHeapInfoOUT->ui32ClientHeapCount,
359 &psGetDevMemHeapInfoOUT->sHeapInfo[0], 404#if defined (SUPPORT_SID_INTERFACE)
360 pbSharedDeviceMemHeap); 405 &asHeapInfo[0],
406#else
407 &psGetDevMemHeapInfoOUT->sHeapInfo[0],
408#endif
409 pbSharedDeviceMemHeap);
361 410
362 if(psGetDevMemHeapInfoOUT->eError != PVRSRV_OK) 411 if(psGetDevMemHeapInfoOUT->eError != PVRSRV_OK)
363 { 412 {
364 return 0; 413 return 0;
365 } 414 }
366 415
367 for(i = 0; i < psGetDevMemHeapInfoOUT->ui32ClientHeapCount; i++) 416 for(i = 0; i < psGetDevMemHeapInfoOUT->ui32ClientHeapCount; i++)
368 { 417 {
369 IMG_HANDLE hDevMemHeapExt; 418#if defined (SUPPORT_SID_INTERFACE)
370 419 IMG_SID hDevMemHeapExt;
371#if defined(PVR_SECURE_HANDLES) 420#else
372 if(abSharedDeviceMemHeap[i]) 421 IMG_HANDLE hDevMemHeapExt;
373#endif 422#endif
374 {
375
376 PVRSRVAllocHandleNR(psPerProc->psHandleBase, &hDevMemHeapExt,
377 psGetDevMemHeapInfoOUT->sHeapInfo[i].hDevMemHeap,
378 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP,
379 PVRSRV_HANDLE_ALLOC_FLAG_SHARED);
380 }
381#if defined(PVR_SECURE_HANDLES)
382 else
383 {
384
385 psGetDevMemHeapInfoOUT->eError =
386 PVRSRVFindHandle(psPerProc->psHandleBase, &hDevMemHeapExt,
387 psGetDevMemHeapInfoOUT->sHeapInfo[i].hDevMemHeap,
388 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP);
389 if(psGetDevMemHeapInfoOUT->eError != PVRSRV_OK)
390 {
391 return 0;
392 }
393 }
394#endif
395 psGetDevMemHeapInfoOUT->sHeapInfo[i].hDevMemHeap = hDevMemHeapExt;
396 }
397 423
398 COMMIT_HANDLE_BATCH_OR_ERROR(psGetDevMemHeapInfoOUT->eError, psPerProc) 424#if defined(PVR_SECURE_HANDLES) || defined (SUPPORT_SID_INTERFACE)
425 if(abSharedDeviceMemHeap[i])
426#endif
427 {
428
429#if defined (SUPPORT_SID_INTERFACE)
430 PVRSRVAllocHandleNR(psPerProc->psHandleBase,
431 &hDevMemHeapExt,
432 asHeapInfo[i].hDevMemHeap,
433 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP,
434 PVRSRV_HANDLE_ALLOC_FLAG_SHARED);
435#else
436 PVRSRVAllocHandleNR(psPerProc->psHandleBase, &hDevMemHeapExt,
437 psGetDevMemHeapInfoOUT->sHeapInfo[i].hDevMemHeap,
438 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP,
439 PVRSRV_HANDLE_ALLOC_FLAG_SHARED);
440#endif
441 }
442#if defined(PVR_SECURE_HANDLES) || defined (SUPPORT_SID_INTERFACE)
443 else
444 {
445
446 psGetDevMemHeapInfoOUT->eError =
447 PVRSRVFindHandle(psPerProc->psHandleBase,
448 &hDevMemHeapExt,
449#if defined (SUPPORT_SID_INTERFACE)
450 asHeapInfo[i].hDevMemHeap,
451#else
452 psGetDevMemHeapInfoOUT->sHeapInfo[i].hDevMemHeap,
453#endif
454 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP);
455 if(psGetDevMemHeapInfoOUT->eError != PVRSRV_OK)
456 {
457 return 0;
458 }
459 }
460#endif
461 psGetDevMemHeapInfoOUT->sHeapInfo[i].hDevMemHeap = hDevMemHeapExt;
462#if defined (SUPPORT_SID_INTERFACE)
463 psGetDevMemHeapInfoOUT->sHeapInfo[i].ui32HeapID = asHeapInfo[i].ui32HeapID;
464 psGetDevMemHeapInfoOUT->sHeapInfo[i].sDevVAddrBase = asHeapInfo[i].sDevVAddrBase;
465 psGetDevMemHeapInfoOUT->sHeapInfo[i].ui32HeapByteSize = asHeapInfo[i].ui32HeapByteSize;
466 psGetDevMemHeapInfoOUT->sHeapInfo[i].ui32Attribs = asHeapInfo[i].ui32Attribs;
467 psGetDevMemHeapInfoOUT->sHeapInfo[i].ui32XTileStride = asHeapInfo[i].ui32XTileStride;
468#endif
469 }
399 470
400 return 0; 471 COMMIT_HANDLE_BATCH_OR_ERROR(psGetDevMemHeapInfoOUT->eError, psPerProc)
472
473 return 0;
401} 474}
402 475
403 476
404#if defined(OS_PVRSRV_ALLOC_DEVICE_MEM_BW) 477#if defined(OS_PVRSRV_ALLOC_DEVICE_MEM_BW)
405IMG_INT 478IMG_INT
406PVRSRVAllocDeviceMemBW(IMG_UINT32 ui32BridgeID, 479PVRSRVAllocDeviceMemBW(IMG_UINT32 ui32BridgeID,
407 PVRSRV_BRIDGE_IN_ALLOCDEVICEMEM *psAllocDeviceMemIN, 480 PVRSRV_BRIDGE_IN_ALLOCDEVICEMEM *psAllocDeviceMemIN,
408 PVRSRV_BRIDGE_OUT_ALLOCDEVICEMEM *psAllocDeviceMemOUT, 481 PVRSRV_BRIDGE_OUT_ALLOCDEVICEMEM *psAllocDeviceMemOUT,
409 PVRSRV_PER_PROCESS_DATA *psPerProc); 482 PVRSRV_PER_PROCESS_DATA *psPerProc);
410#else 483#else
411static IMG_INT 484static IMG_INT
412PVRSRVAllocDeviceMemBW(IMG_UINT32 ui32BridgeID, 485PVRSRVAllocDeviceMemBW(IMG_UINT32 ui32BridgeID,
413 PVRSRV_BRIDGE_IN_ALLOCDEVICEMEM *psAllocDeviceMemIN, 486 PVRSRV_BRIDGE_IN_ALLOCDEVICEMEM *psAllocDeviceMemIN,
414 PVRSRV_BRIDGE_OUT_ALLOCDEVICEMEM *psAllocDeviceMemOUT, 487 PVRSRV_BRIDGE_OUT_ALLOCDEVICEMEM *psAllocDeviceMemOUT,
415 PVRSRV_PER_PROCESS_DATA *psPerProc) 488 PVRSRV_PER_PROCESS_DATA *psPerProc)
416{ 489{
417 PVRSRV_KERNEL_MEM_INFO *psMemInfo; 490 PVRSRV_KERNEL_MEM_INFO *psMemInfo;
418 IMG_HANDLE hDevCookieInt; 491 IMG_HANDLE hDevCookieInt;
419 IMG_HANDLE hDevMemHeapInt; 492 IMG_HANDLE hDevMemHeapInt;
420 493 IMG_UINT32 ui32ShareIndex;
421 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ALLOC_DEVICEMEM); 494 IMG_BOOL bUseShareMemWorkaround;
422 495
423 NEW_HANDLE_BATCH_OR_ERROR(psAllocDeviceMemOUT->eError, psPerProc, 2) 496 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ALLOC_DEVICEMEM);
424 497
425 psAllocDeviceMemOUT->eError = 498 NEW_HANDLE_BATCH_OR_ERROR(psAllocDeviceMemOUT->eError, psPerProc, 2)
426 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt, 499
427 psAllocDeviceMemIN->hDevCookie, 500 psAllocDeviceMemOUT->eError =
428 PVRSRV_HANDLE_TYPE_DEV_NODE); 501 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt,
429 502 psAllocDeviceMemIN->hDevCookie,
430 if(psAllocDeviceMemOUT->eError != PVRSRV_OK) 503 PVRSRV_HANDLE_TYPE_DEV_NODE);
431 { 504
432 return 0; 505 if(psAllocDeviceMemOUT->eError != PVRSRV_OK)
433 } 506 {
434 507 return 0;
435 psAllocDeviceMemOUT->eError = 508 }
436 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevMemHeapInt, 509
437 psAllocDeviceMemIN->hDevMemHeap, 510 psAllocDeviceMemOUT->eError =
438 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP); 511 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevMemHeapInt,
439 512 psAllocDeviceMemIN->hDevMemHeap,
440 if(psAllocDeviceMemOUT->eError != PVRSRV_OK) 513 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP);
441 { 514
442 return 0; 515 if(psAllocDeviceMemOUT->eError != PVRSRV_OK)
443 } 516 {
444 517 return 0;
445 psAllocDeviceMemOUT->eError = 518 }
446 PVRSRVAllocDeviceMemKM(hDevCookieInt, 519
447 psPerProc, 520
448 hDevMemHeapInt, 521
449 psAllocDeviceMemIN->ui32Attribs, 522 bUseShareMemWorkaround = ((psAllocDeviceMemIN->ui32Attribs & PVRSRV_MEM_XPROC) != 0) ? IMG_TRUE : IMG_FALSE;
450 psAllocDeviceMemIN->ui32Size, 523 ui32ShareIndex = 7654321;
451 psAllocDeviceMemIN->ui32Alignment, 524
452 &psMemInfo, 525 if (bUseShareMemWorkaround)
453 "" ); 526 {
454 527
455 if(psAllocDeviceMemOUT->eError != PVRSRV_OK) 528
456 { 529
457 return 0; 530 psAllocDeviceMemOUT->eError =
458 } 531 BM_XProcWorkaroundFindNewBufferAndSetShareIndex(&ui32ShareIndex);
459 532 if(psAllocDeviceMemOUT->eError != PVRSRV_OK)
460 OSMemSet(&psAllocDeviceMemOUT->sClientMemInfo, 533 {
461 0, 534 return 0;
462 sizeof(psAllocDeviceMemOUT->sClientMemInfo)); 535 }
463 536 }
464 psAllocDeviceMemOUT->sClientMemInfo.pvLinAddrKM = 537
465 psMemInfo->pvLinAddrKM; 538 psAllocDeviceMemOUT->eError =
539 PVRSRVAllocDeviceMemKM(hDevCookieInt,
540 psPerProc,
541 hDevMemHeapInt,
542 psAllocDeviceMemIN->ui32Attribs,
543 psAllocDeviceMemIN->ui32Size,
544 psAllocDeviceMemIN->ui32Alignment,
545 &psMemInfo,
546 "" );
547
548 if (bUseShareMemWorkaround)
549 {
550 PVR_ASSERT(ui32ShareIndex != 7654321);
551 BM_XProcWorkaroundUnsetShareIndex(ui32ShareIndex);
552 }
553
554 if(psAllocDeviceMemOUT->eError != PVRSRV_OK)
555 {
556 return 0;
557 }
558
559 psMemInfo->sShareMemWorkaround.bInUse = bUseShareMemWorkaround;
560 if (bUseShareMemWorkaround)
561 {
562 PVR_ASSERT(ui32ShareIndex != 7654321);
563 psMemInfo->sShareMemWorkaround.ui32ShareIndex = ui32ShareIndex;
564 psMemInfo->sShareMemWorkaround.hDevCookieInt = hDevCookieInt;
565 psMemInfo->sShareMemWorkaround.ui32OrigReqAttribs = psAllocDeviceMemIN->ui32Attribs;
566 psMemInfo->sShareMemWorkaround.ui32OrigReqSize = (IMG_UINT32)psAllocDeviceMemIN->ui32Size;
567 psMemInfo->sShareMemWorkaround.ui32OrigReqAlignment = (IMG_UINT32)psAllocDeviceMemIN->ui32Alignment;
568 }
569
570 OSMemSet(&psAllocDeviceMemOUT->sClientMemInfo,
571 0,
572 sizeof(psAllocDeviceMemOUT->sClientMemInfo));
573
574 psAllocDeviceMemOUT->sClientMemInfo.pvLinAddrKM =
575 psMemInfo->pvLinAddrKM;
466 576
467#if defined (__linux__) 577#if defined (__linux__)
468 psAllocDeviceMemOUT->sClientMemInfo.pvLinAddr = 0; 578 psAllocDeviceMemOUT->sClientMemInfo.pvLinAddr = 0;
469#else 579#else
470 psAllocDeviceMemOUT->sClientMemInfo.pvLinAddr = psMemInfo->pvLinAddrKM; 580 psAllocDeviceMemOUT->sClientMemInfo.pvLinAddr = psMemInfo->pvLinAddrKM;
581#endif
582 psAllocDeviceMemOUT->sClientMemInfo.sDevVAddr = psMemInfo->sDevVAddr;
583 psAllocDeviceMemOUT->sClientMemInfo.ui32Flags = psMemInfo->ui32Flags;
584 psAllocDeviceMemOUT->sClientMemInfo.uAllocSize = psMemInfo->uAllocSize;
585#if defined (SUPPORT_SID_INTERFACE)
586#else
587 psAllocDeviceMemOUT->sClientMemInfo.hMappingInfo = psMemInfo->sMemBlk.hOSMemHandle;
471#endif 588#endif
472 psAllocDeviceMemOUT->sClientMemInfo.sDevVAddr = psMemInfo->sDevVAddr;
473 psAllocDeviceMemOUT->sClientMemInfo.ui32Flags = psMemInfo->ui32Flags;
474 psAllocDeviceMemOUT->sClientMemInfo.ui32AllocSize = psMemInfo->ui32AllocSize;
475 psAllocDeviceMemOUT->sClientMemInfo.hMappingInfo = psMemInfo->sMemBlk.hOSMemHandle;
476
477 PVRSRVAllocHandleNR(psPerProc->psHandleBase,
478 &psAllocDeviceMemOUT->sClientMemInfo.hKernelMemInfo,
479 psMemInfo,
480 PVRSRV_HANDLE_TYPE_MEM_INFO,
481 PVRSRV_HANDLE_ALLOC_FLAG_NONE);
482
483 if(psAllocDeviceMemIN->ui32Attribs & PVRSRV_MEM_NO_SYNCOBJ)
484 {
485
486 OSMemSet(&psAllocDeviceMemOUT->sClientSyncInfo,
487 0,
488 sizeof (PVRSRV_CLIENT_SYNC_INFO));
489 psAllocDeviceMemOUT->sClientMemInfo.psClientSyncInfo = IMG_NULL;
490 }
491 else
492 {
493
494 589
495 psAllocDeviceMemOUT->sClientSyncInfo.psSyncData = 590 PVRSRVAllocHandleNR(psPerProc->psHandleBase,
496 psMemInfo->psKernelSyncInfo->psSyncData; 591 &psAllocDeviceMemOUT->sClientMemInfo.hKernelMemInfo,
497 psAllocDeviceMemOUT->sClientSyncInfo.sWriteOpsCompleteDevVAddr = 592 psMemInfo,
498 psMemInfo->psKernelSyncInfo->sWriteOpsCompleteDevVAddr; 593 PVRSRV_HANDLE_TYPE_MEM_INFO,
499 psAllocDeviceMemOUT->sClientSyncInfo.sReadOpsCompleteDevVAddr = 594 PVRSRV_HANDLE_ALLOC_FLAG_NONE);
500 psMemInfo->psKernelSyncInfo->sReadOpsCompleteDevVAddr; 595
596 #if defined (SUPPORT_SID_INTERFACE)
597 PVR_ASSERT(psAllocDeviceMemOUT->sClientMemInfo.hKernelMemInfo != 0);
598
599 if (psMemInfo->sMemBlk.hOSMemHandle != IMG_NULL)
600 {
601 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
602 &psAllocDeviceMemOUT->sClientMemInfo.hMappingInfo,
603 psMemInfo->sMemBlk.hOSMemHandle,
604 PVRSRV_HANDLE_TYPE_MEM_INFO,
605 PVRSRV_HANDLE_ALLOC_FLAG_NONE,
606 psAllocDeviceMemOUT->sClientMemInfo.hKernelMemInfo);
607 }
608 else
609 {
610 psAllocDeviceMemOUT->sClientMemInfo.hMappingInfo = 0;
611 }
612#endif
501 613
502 psAllocDeviceMemOUT->sClientSyncInfo.hMappingInfo = 614 if(psAllocDeviceMemIN->ui32Attribs & PVRSRV_MEM_NO_SYNCOBJ)
503 psMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle; 615 {
616
617 OSMemSet(&psAllocDeviceMemOUT->sClientSyncInfo,
618 0,
619 sizeof (PVRSRV_CLIENT_SYNC_INFO));
620 psAllocDeviceMemOUT->sClientMemInfo.psClientSyncInfo = IMG_NULL;
621 }
622 else
623 {
624
625
626#if !defined(PVRSRV_DISABLE_UM_SYNCOBJ_MAPPINGS)
627 psAllocDeviceMemOUT->sClientSyncInfo.psSyncData =
628 psMemInfo->psKernelSyncInfo->psSyncData;
629 psAllocDeviceMemOUT->sClientSyncInfo.sWriteOpsCompleteDevVAddr =
630 psMemInfo->psKernelSyncInfo->sWriteOpsCompleteDevVAddr;
631 psAllocDeviceMemOUT->sClientSyncInfo.sReadOpsCompleteDevVAddr =
632 psMemInfo->psKernelSyncInfo->sReadOpsCompleteDevVAddr;
633
634#if defined (SUPPORT_SID_INTERFACE)
635 if (psMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle != IMG_NULL)
636 {
637 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
638 &psAllocDeviceMemOUT->sClientSyncInfo.hMappingInfo,
639 psMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle,
640 PVRSRV_HANDLE_TYPE_SYNC_INFO,
641 PVRSRV_HANDLE_ALLOC_FLAG_NONE,
642 psAllocDeviceMemOUT->sClientMemInfo.hKernelMemInfo);
643 }
644 else
645 {
646 psAllocDeviceMemOUT->sClientSyncInfo.hMappingInfo = 0;
647 }
648#else
649 psAllocDeviceMemOUT->sClientSyncInfo.hMappingInfo =
650 psMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle;
651#endif
652#endif
504 653
505 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase, 654 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
506 &psAllocDeviceMemOUT->sClientSyncInfo.hKernelSyncInfo, 655 &psAllocDeviceMemOUT->sClientSyncInfo.hKernelSyncInfo,
507 psMemInfo->psKernelSyncInfo, 656 psMemInfo->psKernelSyncInfo,
508 PVRSRV_HANDLE_TYPE_SYNC_INFO, 657 PVRSRV_HANDLE_TYPE_SYNC_INFO,
509 PVRSRV_HANDLE_ALLOC_FLAG_NONE, 658 PVRSRV_HANDLE_ALLOC_FLAG_NONE,
510 psAllocDeviceMemOUT->sClientMemInfo.hKernelMemInfo); 659 psAllocDeviceMemOUT->sClientMemInfo.hKernelMemInfo);
511 660
512 psAllocDeviceMemOUT->sClientMemInfo.psClientSyncInfo = 661 psAllocDeviceMemOUT->sClientMemInfo.psClientSyncInfo =
513 &psAllocDeviceMemOUT->sClientSyncInfo; 662 &psAllocDeviceMemOUT->sClientSyncInfo;
514 663
515 } 664 }
516 665
517 COMMIT_HANDLE_BATCH_OR_ERROR(psAllocDeviceMemOUT->eError, psPerProc) 666 COMMIT_HANDLE_BATCH_OR_ERROR(psAllocDeviceMemOUT->eError, psPerProc)
518 667
519 return 0; 668 return 0;
520} 669}
521 670
522#endif 671#endif
523 672
524static IMG_INT 673static IMG_INT
525PVRSRVFreeDeviceMemBW(IMG_UINT32 ui32BridgeID, 674PVRSRVFreeDeviceMemBW(IMG_UINT32 ui32BridgeID,
526 PVRSRV_BRIDGE_IN_FREEDEVICEMEM *psFreeDeviceMemIN, 675 PVRSRV_BRIDGE_IN_FREEDEVICEMEM *psFreeDeviceMemIN,
527 PVRSRV_BRIDGE_RETURN *psRetOUT, 676 PVRSRV_BRIDGE_RETURN *psRetOUT,
528 PVRSRV_PER_PROCESS_DATA *psPerProc) 677 PVRSRV_PER_PROCESS_DATA *psPerProc)
529{ 678{
530 IMG_HANDLE hDevCookieInt; 679 IMG_HANDLE hDevCookieInt;
531 IMG_VOID *pvKernelMemInfo; 680 IMG_VOID *pvKernelMemInfo;
532 681
533 682
534 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_FREE_DEVICEMEM); 683 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_FREE_DEVICEMEM);
535 684
536 psRetOUT->eError = 685 psRetOUT->eError =
537 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt, 686 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt,
538 psFreeDeviceMemIN->hDevCookie, 687 psFreeDeviceMemIN->hDevCookie,
539 PVRSRV_HANDLE_TYPE_DEV_NODE); 688 PVRSRV_HANDLE_TYPE_DEV_NODE);
540 689
541 if(psRetOUT->eError != PVRSRV_OK) 690 if(psRetOUT->eError != PVRSRV_OK)
542 { 691 {
543 return 0; 692 return 0;
544 } 693 }
545 694
546 psRetOUT->eError = 695 psRetOUT->eError =
547 PVRSRVLookupHandle(psPerProc->psHandleBase, &pvKernelMemInfo, 696 PVRSRVLookupHandle(psPerProc->psHandleBase,
548 psFreeDeviceMemIN->psKernelMemInfo, 697 &pvKernelMemInfo,
549 PVRSRV_HANDLE_TYPE_MEM_INFO); 698#if defined (SUPPORT_SID_INTERFACE)
699 psFreeDeviceMemIN->hKernelMemInfo,
700#else
701 psFreeDeviceMemIN->psKernelMemInfo,
702#endif
703 PVRSRV_HANDLE_TYPE_MEM_INFO);
550 704
551 if(psRetOUT->eError != PVRSRV_OK) 705 if(psRetOUT->eError != PVRSRV_OK)
552 { 706 {
553 return 0; 707 return 0;
554 } 708 }
555 709
556 psRetOUT->eError = PVRSRVFreeDeviceMemKM(hDevCookieInt, pvKernelMemInfo); 710 psRetOUT->eError = PVRSRVFreeDeviceMemKM(hDevCookieInt, pvKernelMemInfo);
557 711
558 if(psRetOUT->eError != PVRSRV_OK) 712 if(psRetOUT->eError != PVRSRV_OK)
559 { 713 {
560 return 0; 714 return 0;
561 } 715 }
562 716
563 psRetOUT->eError = 717 psRetOUT->eError =
564 PVRSRVReleaseHandle(psPerProc->psHandleBase, 718 PVRSRVReleaseHandle(psPerProc->psHandleBase,
565 psFreeDeviceMemIN->psKernelMemInfo, 719#if defined (SUPPORT_SID_INTERFACE)
566 PVRSRV_HANDLE_TYPE_MEM_INFO); 720 psFreeDeviceMemIN->hKernelMemInfo,
721#else
722 psFreeDeviceMemIN->psKernelMemInfo,
723#endif
724 PVRSRV_HANDLE_TYPE_MEM_INFO);
567 725
568 return 0; 726 return 0;
569} 727}
570 728
571 729
572static IMG_INT 730static IMG_INT
573PVRSRVExportDeviceMemBW(IMG_UINT32 ui32BridgeID, 731PVRSRVExportDeviceMemBW(IMG_UINT32 ui32BridgeID,
574 PVRSRV_BRIDGE_IN_EXPORTDEVICEMEM *psExportDeviceMemIN, 732 PVRSRV_BRIDGE_IN_EXPORTDEVICEMEM *psExportDeviceMemIN,
575 PVRSRV_BRIDGE_OUT_EXPORTDEVICEMEM *psExportDeviceMemOUT, 733 PVRSRV_BRIDGE_OUT_EXPORTDEVICEMEM *psExportDeviceMemOUT,
576 PVRSRV_PER_PROCESS_DATA *psPerProc) 734 PVRSRV_PER_PROCESS_DATA *psPerProc)
577{ 735{
578 IMG_HANDLE hDevCookieInt; 736 IMG_HANDLE hDevCookieInt;
579 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 737#if defined (SUPPORT_SID_INTERFACE)
580 738 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo = IMG_NULL;
581 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_EXPORT_DEVICEMEM); 739#else
582 740 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
583 741#endif
584 psExportDeviceMemOUT->eError =
585 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt,
586 psExportDeviceMemIN->hDevCookie,
587 PVRSRV_HANDLE_TYPE_DEV_NODE);
588
589 if(psExportDeviceMemOUT->eError != PVRSRV_OK)
590 {
591 PVR_DPF((PVR_DBG_ERROR, "PVRSRVExportDeviceMemBW: can't find devcookie"));
592 return 0;
593 }
594
595
596 psExportDeviceMemOUT->eError =
597 PVRSRVLookupHandle(psPerProc->psHandleBase, (IMG_PVOID *)&psKernelMemInfo,
598 psExportDeviceMemIN->psKernelMemInfo,
599 PVRSRV_HANDLE_TYPE_MEM_INFO);
600
601 if(psExportDeviceMemOUT->eError != PVRSRV_OK)
602 {
603 PVR_DPF((PVR_DBG_ERROR, "PVRSRVExportDeviceMemBW: can't find kernel meminfo"));
604 return 0;
605 }
606
607
608 psExportDeviceMemOUT->eError =
609 PVRSRVFindHandle(KERNEL_HANDLE_BASE,
610 &psExportDeviceMemOUT->hMemInfo,
611 psKernelMemInfo,
612 PVRSRV_HANDLE_TYPE_MEM_INFO);
613 if(psExportDeviceMemOUT->eError == PVRSRV_OK)
614 {
615
616 PVR_DPF((PVR_DBG_MESSAGE, "PVRSRVExportDeviceMemBW: allocation is already exported"));
617 return 0;
618 }
619
620
621 psExportDeviceMemOUT->eError = PVRSRVAllocHandle(KERNEL_HANDLE_BASE,
622 &psExportDeviceMemOUT->hMemInfo,
623 psKernelMemInfo,
624 PVRSRV_HANDLE_TYPE_MEM_INFO,
625 PVRSRV_HANDLE_ALLOC_FLAG_NONE);
626 if (psExportDeviceMemOUT->eError != PVRSRV_OK)
627 {
628 PVR_DPF((PVR_DBG_ERROR, "PVRSRVExportDeviceMemBW: failed to allocate handle from global handle list"));
629 return 0;
630 }
631
632
633 psKernelMemInfo->ui32Flags |= PVRSRV_MEM_EXPORTED;
634 742
635 return 0; 743 PVR_ASSERT(ui32BridgeID == PVRSRV_GET_BRIDGE_ID(PVRSRV_BRIDGE_EXPORT_DEVICEMEM) ||
744 ui32BridgeID == PVRSRV_GET_BRIDGE_ID(PVRSRV_BRIDGE_EXPORT_DEVICEMEM_2));
745 PVR_UNREFERENCED_PARAMETER(ui32BridgeID);
746
747
748 psExportDeviceMemOUT->eError =
749 PVRSRVLookupHandle(psPerProc->psHandleBase,
750 &hDevCookieInt,
751 psExportDeviceMemIN->hDevCookie,
752 PVRSRV_HANDLE_TYPE_DEV_NODE);
753
754 if(psExportDeviceMemOUT->eError != PVRSRV_OK)
755 {
756 PVR_DPF((PVR_DBG_ERROR, "PVRSRVExportDeviceMemBW: can't find devcookie"));
757 return 0;
758 }
759
760
761 psExportDeviceMemOUT->eError =
762 PVRSRVLookupHandle(psPerProc->psHandleBase,
763 (IMG_PVOID *)&psKernelMemInfo,
764#if defined (SUPPORT_SID_INTERFACE)
765 psExportDeviceMemIN->hKernelMemInfo,
766#else
767 psExportDeviceMemIN->psKernelMemInfo,
768#endif
769 PVRSRV_HANDLE_TYPE_MEM_INFO);
770
771 if(psExportDeviceMemOUT->eError != PVRSRV_OK)
772 {
773 PVR_DPF((PVR_DBG_ERROR, "PVRSRVExportDeviceMemBW: can't find kernel meminfo"));
774 return 0;
775 }
776
777
778 psExportDeviceMemOUT->eError =
779 PVRSRVFindHandle(KERNEL_HANDLE_BASE,
780 &psExportDeviceMemOUT->hMemInfo,
781 psKernelMemInfo,
782 PVRSRV_HANDLE_TYPE_MEM_INFO);
783 if(psExportDeviceMemOUT->eError == PVRSRV_OK)
784 {
785
786 PVR_DPF((PVR_DBG_MESSAGE, "PVRSRVExportDeviceMemBW: allocation is already exported"));
787 return 0;
788 }
789
790
791 psExportDeviceMemOUT->eError = PVRSRVAllocHandle(KERNEL_HANDLE_BASE,
792 &psExportDeviceMemOUT->hMemInfo,
793 psKernelMemInfo,
794 PVRSRV_HANDLE_TYPE_MEM_INFO,
795 PVRSRV_HANDLE_ALLOC_FLAG_NONE);
796 if (psExportDeviceMemOUT->eError != PVRSRV_OK)
797 {
798 PVR_DPF((PVR_DBG_ERROR, "PVRSRVExportDeviceMemBW: failed to allocate handle from global handle list"));
799 return 0;
800 }
801
802
803 psKernelMemInfo->ui32Flags |= PVRSRV_MEM_EXPORTED;
804
805 return 0;
636} 806}
637 807
638 808
639static IMG_INT 809static IMG_INT
640PVRSRVMapDeviceMemoryBW(IMG_UINT32 ui32BridgeID, 810PVRSRVMapDeviceMemoryBW(IMG_UINT32 ui32BridgeID,
641 PVRSRV_BRIDGE_IN_MAP_DEV_MEMORY *psMapDevMemIN, 811 PVRSRV_BRIDGE_IN_MAP_DEV_MEMORY *psMapDevMemIN,
642 PVRSRV_BRIDGE_OUT_MAP_DEV_MEMORY *psMapDevMemOUT, 812 PVRSRV_BRIDGE_OUT_MAP_DEV_MEMORY *psMapDevMemOUT,
643 PVRSRV_PER_PROCESS_DATA *psPerProc) 813 PVRSRV_PER_PROCESS_DATA *psPerProc)
644{ 814{
645 PVRSRV_KERNEL_MEM_INFO *psSrcKernelMemInfo = IMG_NULL; 815 PVRSRV_KERNEL_MEM_INFO *psSrcKernelMemInfo = IMG_NULL;
646 PVRSRV_KERNEL_MEM_INFO *psDstKernelMemInfo = IMG_NULL; 816 PVRSRV_KERNEL_MEM_INFO *psDstKernelMemInfo = IMG_NULL;
647 IMG_HANDLE hDstDevMemHeap = IMG_NULL; 817 IMG_HANDLE hDstDevMemHeap = IMG_NULL;
648 818
649 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_MAP_DEV_MEMORY); 819 PVR_ASSERT(ui32BridgeID == PVRSRV_GET_BRIDGE_ID(PVRSRV_BRIDGE_MAP_DEV_MEMORY) ||
650 820 ui32BridgeID == PVRSRV_GET_BRIDGE_ID(PVRSRV_BRIDGE_MAP_DEV_MEMORY_2));
651 NEW_HANDLE_BATCH_OR_ERROR(psMapDevMemOUT->eError, psPerProc, 2) 821 PVR_UNREFERENCED_PARAMETER(ui32BridgeID);
652 822
653 823 NEW_HANDLE_BATCH_OR_ERROR(psMapDevMemOUT->eError, psPerProc, 2)
654 psMapDevMemOUT->eError = PVRSRVLookupHandle(KERNEL_HANDLE_BASE, 824
655 (IMG_VOID**)&psSrcKernelMemInfo, 825
656 psMapDevMemIN->hKernelMemInfo, 826 psMapDevMemOUT->eError = PVRSRVLookupHandle(KERNEL_HANDLE_BASE,
657 PVRSRV_HANDLE_TYPE_MEM_INFO); 827 (IMG_VOID**)&psSrcKernelMemInfo,
658 if(psMapDevMemOUT->eError != PVRSRV_OK) 828 psMapDevMemIN->hKernelMemInfo,
659 { 829 PVRSRV_HANDLE_TYPE_MEM_INFO);
660 return 0; 830 if(psMapDevMemOUT->eError != PVRSRV_OK)
661 } 831 {
662 832 return 0;
663 833 }
664 psMapDevMemOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 834
665 &hDstDevMemHeap, 835
666 psMapDevMemIN->hDstDevMemHeap, 836 psMapDevMemOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
667 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP); 837 &hDstDevMemHeap,
668 if(psMapDevMemOUT->eError != PVRSRV_OK) 838 psMapDevMemIN->hDstDevMemHeap,
669 { 839 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP);
670 return 0; 840 if(psMapDevMemOUT->eError != PVRSRV_OK)
671 } 841 {
672 842 return 0;
673 843 }
674 psMapDevMemOUT->eError = PVRSRVMapDeviceMemoryKM(psPerProc, 844
675 psSrcKernelMemInfo, 845
676 hDstDevMemHeap, 846 if (psSrcKernelMemInfo->sShareMemWorkaround.bInUse)
677 &psDstKernelMemInfo); 847 {
678 if(psMapDevMemOUT->eError != PVRSRV_OK) 848 PVR_DPF((PVR_DBG_MESSAGE, "using the mem wrap workaround."));
679 { 849
680 return 0; 850
681 } 851
682 852
683 OSMemSet(&psMapDevMemOUT->sDstClientMemInfo, 853
684 0, 854
685 sizeof(psMapDevMemOUT->sDstClientMemInfo)); 855
686 OSMemSet(&psMapDevMemOUT->sDstClientSyncInfo, 856
687 0, 857
688 sizeof(psMapDevMemOUT->sDstClientSyncInfo)); 858 psMapDevMemOUT->eError = BM_XProcWorkaroundSetShareIndex(psSrcKernelMemInfo->sShareMemWorkaround.ui32ShareIndex);
689 859 if(psMapDevMemOUT->eError != PVRSRV_OK)
690 psMapDevMemOUT->sDstClientMemInfo.pvLinAddrKM = 860 {
691 psDstKernelMemInfo->pvLinAddrKM; 861 PVR_DPF((PVR_DBG_ERROR, "PVRSRVMapDeviceMemoryBW(): failed to recycle shared buffer"));
692 862 return 0;
693 psMapDevMemOUT->sDstClientMemInfo.pvLinAddr = 0; 863 }
694 psMapDevMemOUT->sDstClientMemInfo.sDevVAddr = psDstKernelMemInfo->sDevVAddr; 864
695 psMapDevMemOUT->sDstClientMemInfo.ui32Flags = psDstKernelMemInfo->ui32Flags; 865 psMapDevMemOUT->eError =
696 psMapDevMemOUT->sDstClientMemInfo.ui32AllocSize = psDstKernelMemInfo->ui32AllocSize; 866 PVRSRVAllocDeviceMemKM(psSrcKernelMemInfo->sShareMemWorkaround.hDevCookieInt,
697 psMapDevMemOUT->sDstClientMemInfo.hMappingInfo = psDstKernelMemInfo->sMemBlk.hOSMemHandle; 867 psPerProc,
698 868 hDstDevMemHeap,
869 psSrcKernelMemInfo->sShareMemWorkaround.ui32OrigReqAttribs | PVRSRV_MEM_NO_SYNCOBJ,
870 psSrcKernelMemInfo->sShareMemWorkaround.ui32OrigReqSize,
871 psSrcKernelMemInfo->sShareMemWorkaround.ui32OrigReqAlignment,
872 &psDstKernelMemInfo,
873 "" );
874
875
876 BM_XProcWorkaroundUnsetShareIndex(psSrcKernelMemInfo->sShareMemWorkaround.ui32ShareIndex);
877 if(psMapDevMemOUT->eError != PVRSRV_OK)
878 {
879 PVR_DPF((PVR_DBG_ERROR, "lakjgfgewjlrgebhe"));
880 return 0;
881 }
882
883 if(psSrcKernelMemInfo->psKernelSyncInfo)
884 {
885 psSrcKernelMemInfo->psKernelSyncInfo->ui32RefCount++;
886 }
887
888 psDstKernelMemInfo->psKernelSyncInfo = psSrcKernelMemInfo->psKernelSyncInfo;
889 }
890 else
891 {
892
893 psMapDevMemOUT->eError = PVRSRVMapDeviceMemoryKM(psPerProc,
894 psSrcKernelMemInfo,
895 hDstDevMemHeap,
896 &psDstKernelMemInfo);
897 if(psMapDevMemOUT->eError != PVRSRV_OK)
898 {
899 return 0;
900 }
901 }
902
903
904 psDstKernelMemInfo->sShareMemWorkaround = psSrcKernelMemInfo->sShareMemWorkaround;
905
906 OSMemSet(&psMapDevMemOUT->sDstClientMemInfo,
907 0,
908 sizeof(psMapDevMemOUT->sDstClientMemInfo));
909 OSMemSet(&psMapDevMemOUT->sDstClientSyncInfo,
910 0,
911 sizeof(psMapDevMemOUT->sDstClientSyncInfo));
912
913 psMapDevMemOUT->sDstClientMemInfo.pvLinAddrKM =
914 psDstKernelMemInfo->pvLinAddrKM;
915
916 psMapDevMemOUT->sDstClientMemInfo.pvLinAddr = 0;
917 psMapDevMemOUT->sDstClientMemInfo.sDevVAddr = psDstKernelMemInfo->sDevVAddr;
918 psMapDevMemOUT->sDstClientMemInfo.ui32Flags = psDstKernelMemInfo->ui32Flags;
919 psMapDevMemOUT->sDstClientMemInfo.uAllocSize = psDstKernelMemInfo->uAllocSize;
920#if defined (SUPPORT_SID_INTERFACE)
921#else
922 psMapDevMemOUT->sDstClientMemInfo.hMappingInfo = psDstKernelMemInfo->sMemBlk.hOSMemHandle;
923#endif
699 924
700 PVRSRVAllocHandleNR(psPerProc->psHandleBase, 925
701 &psMapDevMemOUT->sDstClientMemInfo.hKernelMemInfo, 926 PVRSRVAllocHandleNR(psPerProc->psHandleBase,
702 psDstKernelMemInfo, 927 &psMapDevMemOUT->sDstClientMemInfo.hKernelMemInfo,
703 PVRSRV_HANDLE_TYPE_MEM_INFO, 928 psDstKernelMemInfo,
704 PVRSRV_HANDLE_ALLOC_FLAG_NONE); 929 PVRSRV_HANDLE_TYPE_MEM_INFO,
705 psMapDevMemOUT->sDstClientSyncInfo.hKernelSyncInfo = IMG_NULL; 930 PVRSRV_HANDLE_ALLOC_FLAG_NONE);
931 psMapDevMemOUT->sDstClientSyncInfo.hKernelSyncInfo = IMG_NULL;
932
933#if defined (SUPPORT_SID_INTERFACE)
934
935 if (psDstKernelMemInfo->sMemBlk.hOSMemHandle != IMG_NULL)
936 {
937 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
938 &psMapDevMemOUT->sDstClientMemInfo.hMappingInfo,
939 psDstKernelMemInfo->sMemBlk.hOSMemHandle,
940 PVRSRV_HANDLE_TYPE_MEM_INFO,
941 PVRSRV_HANDLE_ALLOC_FLAG_NONE,
942 psMapDevMemOUT->sDstClientMemInfo.hKernelMemInfo);
943 }
944 else
945 {
946 psMapDevMemOUT->sDstClientMemInfo.hMappingInfo = 0;
947 }
948#endif
706 949
950
951 if(psDstKernelMemInfo->psKernelSyncInfo)
952 {
953#if !defined(PVRSRV_DISABLE_UM_SYNCOBJ_MAPPINGS)
954 psMapDevMemOUT->sDstClientSyncInfo.psSyncData =
955 psDstKernelMemInfo->psKernelSyncInfo->psSyncData;
956 psMapDevMemOUT->sDstClientSyncInfo.sWriteOpsCompleteDevVAddr =
957 psDstKernelMemInfo->psKernelSyncInfo->sWriteOpsCompleteDevVAddr;
958 psMapDevMemOUT->sDstClientSyncInfo.sReadOpsCompleteDevVAddr =
959 psDstKernelMemInfo->psKernelSyncInfo->sReadOpsCompleteDevVAddr;
960
961#if defined (SUPPORT_SID_INTERFACE)
962
963 if (psDstKernelMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle != IMG_NULL)
964 {
965 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
966 &psMapDevMemOUT->sDstClientSyncInfo.hMappingInfo,
967 psDstKernelMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle,
968 PVRSRV_HANDLE_TYPE_MEM_INFO,
969 PVRSRV_HANDLE_ALLOC_FLAG_NONE,
970 psMapDevMemOUT->sDstClientMemInfo.hKernelMemInfo);
971 }
972 else
973 {
974 psMapDevMemOUT->sDstClientSyncInfo.hMappingInfo = 0;
975 }
976#else
977 psMapDevMemOUT->sDstClientSyncInfo.hMappingInfo =
978 psDstKernelMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle;
979#endif
980#endif
707 981
708 if(psDstKernelMemInfo->psKernelSyncInfo) 982 psMapDevMemOUT->sDstClientMemInfo.psClientSyncInfo = &psMapDevMemOUT->sDstClientSyncInfo;
709 { 983
710 psMapDevMemOUT->sDstClientSyncInfo.psSyncData = 984 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
711 psDstKernelMemInfo->psKernelSyncInfo->psSyncData; 985 &psMapDevMemOUT->sDstClientSyncInfo.hKernelSyncInfo,
712 psMapDevMemOUT->sDstClientSyncInfo.sWriteOpsCompleteDevVAddr = 986 psDstKernelMemInfo->psKernelSyncInfo,
713 psDstKernelMemInfo->psKernelSyncInfo->sWriteOpsCompleteDevVAddr; 987 PVRSRV_HANDLE_TYPE_SYNC_INFO,
714 psMapDevMemOUT->sDstClientSyncInfo.sReadOpsCompleteDevVAddr = 988 PVRSRV_HANDLE_ALLOC_FLAG_MULTI,
715 psDstKernelMemInfo->psKernelSyncInfo->sReadOpsCompleteDevVAddr; 989 psMapDevMemOUT->sDstClientMemInfo.hKernelMemInfo);
716 990 }
717 psMapDevMemOUT->sDstClientSyncInfo.hMappingInfo =
718 psDstKernelMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle;
719
720 psMapDevMemOUT->sDstClientMemInfo.psClientSyncInfo = &psMapDevMemOUT->sDstClientSyncInfo;
721
722 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
723 &psMapDevMemOUT->sDstClientSyncInfo.hKernelSyncInfo,
724 psDstKernelMemInfo->psKernelSyncInfo,
725 PVRSRV_HANDLE_TYPE_SYNC_INFO,
726 PVRSRV_HANDLE_ALLOC_FLAG_MULTI,
727 psMapDevMemOUT->sDstClientMemInfo.hKernelMemInfo);
728 }
729 991
730 COMMIT_HANDLE_BATCH_OR_ERROR(psMapDevMemOUT->eError, psPerProc) 992 COMMIT_HANDLE_BATCH_OR_ERROR(psMapDevMemOUT->eError, psPerProc)
731 993
732 return 0; 994 return 0;
733} 995}
734 996
735 997
736static IMG_INT 998static IMG_INT
737PVRSRVUnmapDeviceMemoryBW(IMG_UINT32 ui32BridgeID, 999PVRSRVUnmapDeviceMemoryBW(IMG_UINT32 ui32BridgeID,
738 PVRSRV_BRIDGE_IN_UNMAP_DEV_MEMORY *psUnmapDevMemIN, 1000 PVRSRV_BRIDGE_IN_UNMAP_DEV_MEMORY *psUnmapDevMemIN,
739 PVRSRV_BRIDGE_RETURN *psRetOUT, 1001 PVRSRV_BRIDGE_RETURN *psRetOUT,
740 PVRSRV_PER_PROCESS_DATA *psPerProc) 1002 PVRSRV_PER_PROCESS_DATA *psPerProc)
741{ 1003{
742 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo = IMG_NULL; 1004 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo = IMG_NULL;
743 1005
744 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_UNMAP_DEV_MEMORY); 1006 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_UNMAP_DEV_MEMORY);
745 1007
746 psRetOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 1008 psRetOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
747 (IMG_VOID**)&psKernelMemInfo, 1009 (IMG_VOID**)&psKernelMemInfo,
748 psUnmapDevMemIN->psKernelMemInfo, 1010#if defined (SUPPORT_SID_INTERFACE)
749 PVRSRV_HANDLE_TYPE_MEM_INFO); 1011 psUnmapDevMemIN->hKernelMemInfo,
750 if(psRetOUT->eError != PVRSRV_OK) 1012#else
751 { 1013 psUnmapDevMemIN->psKernelMemInfo,
752 return 0; 1014#endif
753 } 1015 PVRSRV_HANDLE_TYPE_MEM_INFO);
754 1016 if(psRetOUT->eError != PVRSRV_OK)
755 psRetOUT->eError = PVRSRVUnmapDeviceMemoryKM(psKernelMemInfo); 1017 {
756 if(psRetOUT->eError != PVRSRV_OK) 1018 return 0;
757 { 1019 }
758 return 0; 1020
759 } 1021 if (psKernelMemInfo->sShareMemWorkaround.bInUse)
760 1022 {
761 psRetOUT->eError = PVRSRVReleaseHandle(psPerProc->psHandleBase, 1023 psRetOUT->eError = PVRSRVFreeDeviceMemKM(psKernelMemInfo->sShareMemWorkaround.hDevCookieInt, psKernelMemInfo);
762 psUnmapDevMemIN->psKernelMemInfo, 1024 if(psRetOUT->eError != PVRSRV_OK)
763 PVRSRV_HANDLE_TYPE_MEM_INFO); 1025 {
1026 PVR_DPF((PVR_DBG_ERROR, "PVRSRVUnmapDeviceMemoryBW: internal error, should expect FreeDeviceMem to fail"));
1027 return 0;
1028 }
1029 }
1030 else
1031 {
1032 psRetOUT->eError = PVRSRVUnmapDeviceMemoryKM(psKernelMemInfo);
1033 if(psRetOUT->eError != PVRSRV_OK)
1034 {
1035 return 0;
1036 }
1037 }
1038
1039 psRetOUT->eError = PVRSRVReleaseHandle(psPerProc->psHandleBase,
1040#if defined (SUPPORT_SID_INTERFACE)
1041 psUnmapDevMemIN->hKernelMemInfo,
1042#else
1043 psUnmapDevMemIN->psKernelMemInfo,
1044#endif
1045 PVRSRV_HANDLE_TYPE_MEM_INFO);
764 1046
765 return 0; 1047 return 0;
766} 1048}
767 1049
768 1050
769 1051
770static IMG_INT 1052static IMG_INT
771PVRSRVMapDeviceClassMemoryBW(IMG_UINT32 ui32BridgeID, 1053PVRSRVMapDeviceClassMemoryBW(IMG_UINT32 ui32BridgeID,
772 PVRSRV_BRIDGE_IN_MAP_DEVICECLASS_MEMORY *psMapDevClassMemIN, 1054 PVRSRV_BRIDGE_IN_MAP_DEVICECLASS_MEMORY *psMapDevClassMemIN,
773 PVRSRV_BRIDGE_OUT_MAP_DEVICECLASS_MEMORY *psMapDevClassMemOUT, 1055 PVRSRV_BRIDGE_OUT_MAP_DEVICECLASS_MEMORY *psMapDevClassMemOUT,
774 PVRSRV_PER_PROCESS_DATA *psPerProc) 1056 PVRSRV_PER_PROCESS_DATA *psPerProc)
775{ 1057{
776 PVRSRV_KERNEL_MEM_INFO *psMemInfo; 1058 PVRSRV_KERNEL_MEM_INFO *psMemInfo;
777 IMG_HANDLE hOSMapInfo; 1059 IMG_HANDLE hOSMapInfo;
778 IMG_HANDLE hDeviceClassBufferInt; 1060 IMG_HANDLE hDeviceClassBufferInt;
779 IMG_HANDLE hDevMemContextInt; 1061 IMG_HANDLE hDevMemContextInt;
780 PVRSRV_HANDLE_TYPE eHandleType; 1062 PVRSRV_HANDLE_TYPE eHandleType;
781 1063
782 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_MAP_DEVICECLASS_MEMORY); 1064 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_MAP_DEVICECLASS_MEMORY);
783 1065
784 NEW_HANDLE_BATCH_OR_ERROR(psMapDevClassMemOUT->eError, psPerProc, 2) 1066 NEW_HANDLE_BATCH_OR_ERROR(psMapDevClassMemOUT->eError, psPerProc, 2)
785 1067
786 1068
787 psMapDevClassMemOUT->eError = 1069 psMapDevClassMemOUT->eError =
788 PVRSRVLookupHandleAnyType(psPerProc->psHandleBase, &hDeviceClassBufferInt, 1070 PVRSRVLookupHandleAnyType(psPerProc->psHandleBase,
789 &eHandleType, 1071 &hDeviceClassBufferInt,
790 psMapDevClassMemIN->hDeviceClassBuffer); 1072 &eHandleType,
791 1073 psMapDevClassMemIN->hDeviceClassBuffer);
792 if(psMapDevClassMemOUT->eError != PVRSRV_OK) 1074
793 { 1075 if(psMapDevClassMemOUT->eError != PVRSRV_OK)
794 return 0; 1076 {
795 } 1077 return 0;
796 1078 }
797 1079
798 psMapDevClassMemOUT->eError = 1080
799 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevMemContextInt, 1081 psMapDevClassMemOUT->eError =
800 psMapDevClassMemIN->hDevMemContext, 1082 PVRSRVLookupHandle(psPerProc->psHandleBase,
801 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT); 1083 &hDevMemContextInt,
802 1084 psMapDevClassMemIN->hDevMemContext,
803 if(psMapDevClassMemOUT->eError != PVRSRV_OK) 1085 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT);
804 { 1086
805 return 0; 1087 if(psMapDevClassMemOUT->eError != PVRSRV_OK)
806 } 1088 {
807 1089 return 0;
808 1090 }
809 switch(eHandleType) 1091
810 { 1092
811#if defined(PVR_SECURE_HANDLES) 1093 switch(eHandleType)
812 case PVRSRV_HANDLE_TYPE_DISP_BUFFER: 1094 {
813 case PVRSRV_HANDLE_TYPE_BUF_BUFFER: 1095#if defined(PVR_SECURE_HANDLES) || defined (SUPPORT_SID_INTERFACE)
1096 case PVRSRV_HANDLE_TYPE_DISP_BUFFER:
1097 case PVRSRV_HANDLE_TYPE_BUF_BUFFER:
814#else 1098#else
815 case PVRSRV_HANDLE_TYPE_NONE: 1099 case PVRSRV_HANDLE_TYPE_NONE:
1100#endif
1101 break;
1102 default:
1103 psMapDevClassMemOUT->eError = PVRSRV_ERROR_INVALID_HANDLE_TYPE;
1104 return 0;
1105 }
1106
1107 psMapDevClassMemOUT->eError =
1108 PVRSRVMapDeviceClassMemoryKM(psPerProc,
1109 hDevMemContextInt,
1110 hDeviceClassBufferInt,
1111 &psMemInfo,
1112 &hOSMapInfo);
1113 if(psMapDevClassMemOUT->eError != PVRSRV_OK)
1114 {
1115 return 0;
1116 }
1117
1118 OSMemSet(&psMapDevClassMemOUT->sClientMemInfo,
1119 0,
1120 sizeof(psMapDevClassMemOUT->sClientMemInfo));
1121 OSMemSet(&psMapDevClassMemOUT->sClientSyncInfo,
1122 0,
1123 sizeof(psMapDevClassMemOUT->sClientSyncInfo));
1124
1125 psMapDevClassMemOUT->sClientMemInfo.pvLinAddrKM =
1126 psMemInfo->pvLinAddrKM;
1127
1128 psMapDevClassMemOUT->sClientMemInfo.pvLinAddr = 0;
1129 psMapDevClassMemOUT->sClientMemInfo.sDevVAddr = psMemInfo->sDevVAddr;
1130 psMapDevClassMemOUT->sClientMemInfo.ui32Flags = psMemInfo->ui32Flags;
1131 psMapDevClassMemOUT->sClientMemInfo.uAllocSize = psMemInfo->uAllocSize;
1132#if defined (SUPPORT_SID_INTERFACE)
1133 if (psMemInfo->sMemBlk.hOSMemHandle != 0)
1134 {
1135 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
1136 &psMapDevClassMemOUT->sClientMemInfo.hMappingInfo,
1137 psMemInfo->sMemBlk.hOSMemHandle,
1138 PVRSRV_HANDLE_TYPE_MEM_INFO,
1139 PVRSRV_HANDLE_ALLOC_FLAG_NONE,
1140 psMapDevClassMemIN->hDeviceClassBuffer);
1141 }
1142 else
1143 {
1144 psMapDevClassMemOUT->sClientMemInfo.hMappingInfo = 0;
1145 }
1146#else
1147 psMapDevClassMemOUT->sClientMemInfo.hMappingInfo = psMemInfo->sMemBlk.hOSMemHandle;
816#endif 1148#endif
817 break;
818 default:
819 psMapDevClassMemOUT->eError = PVRSRV_ERROR_INVALID_HANDLE_TYPE;
820 return 0;
821 }
822 1149
823 psMapDevClassMemOUT->eError = 1150 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
824 PVRSRVMapDeviceClassMemoryKM(psPerProc, 1151 &psMapDevClassMemOUT->sClientMemInfo.hKernelMemInfo,
825 hDevMemContextInt, 1152 psMemInfo,
826 hDeviceClassBufferInt, 1153 PVRSRV_HANDLE_TYPE_MEM_INFO,
827 &psMemInfo, 1154 PVRSRV_HANDLE_ALLOC_FLAG_NONE,
828 &hOSMapInfo); 1155 psMapDevClassMemIN->hDeviceClassBuffer);
829 if(psMapDevClassMemOUT->eError != PVRSRV_OK) 1156
830 { 1157 psMapDevClassMemOUT->sClientSyncInfo.hKernelSyncInfo = IMG_NULL;
831 return 0; 1158
832 } 1159
1160 if(psMemInfo->psKernelSyncInfo)
1161 {
1162#if !defined(PVRSRV_DISABLE_UM_SYNCOBJ_MAPPINGS)
1163 psMapDevClassMemOUT->sClientSyncInfo.psSyncData =
1164 psMemInfo->psKernelSyncInfo->psSyncData;
1165 psMapDevClassMemOUT->sClientSyncInfo.sWriteOpsCompleteDevVAddr =
1166 psMemInfo->psKernelSyncInfo->sWriteOpsCompleteDevVAddr;
1167 psMapDevClassMemOUT->sClientSyncInfo.sReadOpsCompleteDevVAddr =
1168 psMemInfo->psKernelSyncInfo->sReadOpsCompleteDevVAddr;
1169
1170#if defined (SUPPORT_SID_INTERFACE)
1171 if (psMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle != 0)
1172 {
1173 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
1174 &psMapDevClassMemOUT->sClientSyncInfo.hMappingInfo,
1175 psMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle,
1176 PVRSRV_HANDLE_TYPE_SYNC_INFO,
1177 PVRSRV_HANDLE_ALLOC_FLAG_MULTI,
1178 psMapDevClassMemOUT->sClientMemInfo.hKernelMemInfo);
1179 }
1180 else
1181 {
1182 psMapDevClassMemOUT->sClientSyncInfo.hMappingInfo = 0;
1183 }
1184#else
1185 psMapDevClassMemOUT->sClientSyncInfo.hMappingInfo =
1186 psMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle;
1187#endif
1188#endif
833 1189
834 OSMemSet(&psMapDevClassMemOUT->sClientMemInfo, 1190 psMapDevClassMemOUT->sClientMemInfo.psClientSyncInfo = &psMapDevClassMemOUT->sClientSyncInfo;
835 0, 1191
836 sizeof(psMapDevClassMemOUT->sClientMemInfo)); 1192 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
837 OSMemSet(&psMapDevClassMemOUT->sClientSyncInfo, 1193 &psMapDevClassMemOUT->sClientSyncInfo.hKernelSyncInfo,
838 0, 1194 psMemInfo->psKernelSyncInfo,
839 sizeof(psMapDevClassMemOUT->sClientSyncInfo)); 1195 PVRSRV_HANDLE_TYPE_SYNC_INFO,
840 1196 PVRSRV_HANDLE_ALLOC_FLAG_MULTI,
841 psMapDevClassMemOUT->sClientMemInfo.pvLinAddrKM = 1197 psMapDevClassMemOUT->sClientMemInfo.hKernelMemInfo);
842 psMemInfo->pvLinAddrKM; 1198 }
843
844 psMapDevClassMemOUT->sClientMemInfo.pvLinAddr = 0;
845 psMapDevClassMemOUT->sClientMemInfo.sDevVAddr = psMemInfo->sDevVAddr;
846 psMapDevClassMemOUT->sClientMemInfo.ui32Flags = psMemInfo->ui32Flags;
847 psMapDevClassMemOUT->sClientMemInfo.ui32AllocSize = psMemInfo->ui32AllocSize;
848 psMapDevClassMemOUT->sClientMemInfo.hMappingInfo = psMemInfo->sMemBlk.hOSMemHandle;
849
850 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
851 &psMapDevClassMemOUT->sClientMemInfo.hKernelMemInfo,
852 psMemInfo,
853 PVRSRV_HANDLE_TYPE_MEM_INFO,
854 PVRSRV_HANDLE_ALLOC_FLAG_NONE,
855 psMapDevClassMemIN->hDeviceClassBuffer);
856
857 psMapDevClassMemOUT->sClientSyncInfo.hKernelSyncInfo = IMG_NULL;
858
859
860 if(psMemInfo->psKernelSyncInfo)
861 {
862 psMapDevClassMemOUT->sClientSyncInfo.psSyncData =
863 psMemInfo->psKernelSyncInfo->psSyncData;
864 psMapDevClassMemOUT->sClientSyncInfo.sWriteOpsCompleteDevVAddr =
865 psMemInfo->psKernelSyncInfo->sWriteOpsCompleteDevVAddr;
866 psMapDevClassMemOUT->sClientSyncInfo.sReadOpsCompleteDevVAddr =
867 psMemInfo->psKernelSyncInfo->sReadOpsCompleteDevVAddr;
868
869 psMapDevClassMemOUT->sClientSyncInfo.hMappingInfo =
870 psMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle;
871
872 psMapDevClassMemOUT->sClientMemInfo.psClientSyncInfo = &psMapDevClassMemOUT->sClientSyncInfo;
873
874 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
875 &psMapDevClassMemOUT->sClientSyncInfo.hKernelSyncInfo,
876 psMemInfo->psKernelSyncInfo,
877 PVRSRV_HANDLE_TYPE_SYNC_INFO,
878 PVRSRV_HANDLE_ALLOC_FLAG_MULTI,
879 psMapDevClassMemOUT->sClientMemInfo.hKernelMemInfo);
880 }
881 1199
882 COMMIT_HANDLE_BATCH_OR_ERROR(psMapDevClassMemOUT->eError, psPerProc) 1200 COMMIT_HANDLE_BATCH_OR_ERROR(psMapDevClassMemOUT->eError, psPerProc)
883 1201
884 return 0; 1202 return 0;
885} 1203}
886 1204
887static IMG_INT 1205static IMG_INT
888PVRSRVUnmapDeviceClassMemoryBW(IMG_UINT32 ui32BridgeID, 1206PVRSRVUnmapDeviceClassMemoryBW(IMG_UINT32 ui32BridgeID,
889 PVRSRV_BRIDGE_IN_UNMAP_DEVICECLASS_MEMORY *psUnmapDevClassMemIN, 1207 PVRSRV_BRIDGE_IN_UNMAP_DEVICECLASS_MEMORY *psUnmapDevClassMemIN,
890 PVRSRV_BRIDGE_RETURN *psRetOUT, 1208 PVRSRV_BRIDGE_RETURN *psRetOUT,
891 PVRSRV_PER_PROCESS_DATA *psPerProc) 1209 PVRSRV_PER_PROCESS_DATA *psPerProc)
892{ 1210{
893 IMG_VOID *pvKernelMemInfo; 1211 IMG_VOID *pvKernelMemInfo;
894
895 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_UNMAP_DEVICECLASS_MEMORY);
896
897 psRetOUT->eError =
898 PVRSRVLookupHandle(psPerProc->psHandleBase, &pvKernelMemInfo,
899 psUnmapDevClassMemIN->psKernelMemInfo,
900 PVRSRV_HANDLE_TYPE_MEM_INFO);
901 if(psRetOUT->eError != PVRSRV_OK)
902 {
903 return 0;
904 }
905 1212
906 psRetOUT->eError = PVRSRVUnmapDeviceClassMemoryKM(pvKernelMemInfo); 1213 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_UNMAP_DEVICECLASS_MEMORY);
907 1214
908 if(psRetOUT->eError != PVRSRV_OK) 1215 psRetOUT->eError =
909 { 1216 PVRSRVLookupHandle(psPerProc->psHandleBase, &pvKernelMemInfo,
910 return 0; 1217#if defined (SUPPORT_SID_INTERFACE)
911 } 1218 psUnmapDevClassMemIN->hKernelMemInfo,
912 1219#else
913 psRetOUT->eError = 1220 psUnmapDevClassMemIN->psKernelMemInfo,
914 PVRSRVReleaseHandle(psPerProc->psHandleBase, 1221#endif
915 psUnmapDevClassMemIN->psKernelMemInfo, 1222 PVRSRV_HANDLE_TYPE_MEM_INFO);
916 PVRSRV_HANDLE_TYPE_MEM_INFO); 1223 if(psRetOUT->eError != PVRSRV_OK)
1224 {
1225 return 0;
1226 }
1227
1228 psRetOUT->eError = PVRSRVUnmapDeviceClassMemoryKM(pvKernelMemInfo);
1229
1230 if(psRetOUT->eError != PVRSRV_OK)
1231 {
1232 return 0;
1233 }
1234
1235 psRetOUT->eError =
1236 PVRSRVReleaseHandle(psPerProc->psHandleBase,
1237#if defined (SUPPORT_SID_INTERFACE)
1238 psUnmapDevClassMemIN->hKernelMemInfo,
1239#else
1240 psUnmapDevClassMemIN->psKernelMemInfo,
1241#endif
1242 PVRSRV_HANDLE_TYPE_MEM_INFO);
917 1243
918 return 0; 1244 return 0;
919} 1245}
920 1246
921 1247
922#if defined(OS_PVRSRV_WRAP_EXT_MEM_BW) 1248#if defined(OS_PVRSRV_WRAP_EXT_MEM_BW)
923IMG_INT 1249IMG_INT
924PVRSRVWrapExtMemoryBW(IMG_UINT32 ui32BridgeID, 1250PVRSRVWrapExtMemoryBW(IMG_UINT32 ui32BridgeID,
925 PVRSRV_BRIDGE_IN_WRAP_EXT_MEMORY *psWrapExtMemIN, 1251 PVRSRV_BRIDGE_IN_WRAP_EXT_MEMORY *psWrapExtMemIN,
926 PVRSRV_BRIDGE_OUT_WRAP_EXT_MEMORY *psWrapExtMemOUT, 1252 PVRSRV_BRIDGE_OUT_WRAP_EXT_MEMORY *psWrapExtMemOUT,
927 PVRSRV_PER_PROCESS_DATA *psPerProc); 1253 PVRSRV_PER_PROCESS_DATA *psPerProc);
928#else 1254#else
929static IMG_INT 1255static IMG_INT
930PVRSRVWrapExtMemoryBW(IMG_UINT32 ui32BridgeID, 1256PVRSRVWrapExtMemoryBW(IMG_UINT32 ui32BridgeID,
931 PVRSRV_BRIDGE_IN_WRAP_EXT_MEMORY *psWrapExtMemIN, 1257 PVRSRV_BRIDGE_IN_WRAP_EXT_MEMORY *psWrapExtMemIN,
932 PVRSRV_BRIDGE_OUT_WRAP_EXT_MEMORY *psWrapExtMemOUT, 1258 PVRSRV_BRIDGE_OUT_WRAP_EXT_MEMORY *psWrapExtMemOUT,
933 PVRSRV_PER_PROCESS_DATA *psPerProc) 1259 PVRSRV_PER_PROCESS_DATA *psPerProc)
934{ 1260{
935 IMG_HANDLE hDevCookieInt; 1261 IMG_HANDLE hDevCookieInt;
936 IMG_HANDLE hDevMemContextInt; 1262 IMG_HANDLE hDevMemContextInt;
937 PVRSRV_KERNEL_MEM_INFO *psMemInfo; 1263 PVRSRV_KERNEL_MEM_INFO *psMemInfo;
938 IMG_SYS_PHYADDR *psSysPAddr = IMG_NULL; 1264 IMG_SYS_PHYADDR *psSysPAddr = IMG_NULL;
939 IMG_UINT32 ui32PageTableSize = 0; 1265 IMG_UINT32 ui32PageTableSize = 0;
940
941 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_WRAP_EXT_MEMORY);
942
943 NEW_HANDLE_BATCH_OR_ERROR(psWrapExtMemOUT->eError, psPerProc, 2)
944
945
946 psWrapExtMemOUT->eError =
947 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt,
948 psWrapExtMemIN->hDevCookie,
949 PVRSRV_HANDLE_TYPE_DEV_NODE);
950 if(psWrapExtMemOUT->eError != PVRSRV_OK)
951 {
952 return 0;
953 }
954
955
956 psWrapExtMemOUT->eError =
957 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevMemContextInt,
958 psWrapExtMemIN->hDevMemContext,
959 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT);
960
961 if(psWrapExtMemOUT->eError != PVRSRV_OK)
962 {
963 return 0;
964 }
965
966 if(psWrapExtMemIN->ui32NumPageTableEntries)
967 {
968 ui32PageTableSize = psWrapExtMemIN->ui32NumPageTableEntries
969 * sizeof(IMG_SYS_PHYADDR);
970
971 ASSIGN_AND_EXIT_ON_ERROR(psWrapExtMemOUT->eError,
972 OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
973 ui32PageTableSize,
974 (IMG_VOID **)&psSysPAddr, 0,
975 "Page Table"));
976
977 if(CopyFromUserWrapper(psPerProc,
978 ui32BridgeID,
979 psSysPAddr,
980 psWrapExtMemIN->psSysPAddr,
981 ui32PageTableSize) != PVRSRV_OK)
982 {
983 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, ui32PageTableSize, (IMG_VOID *)psSysPAddr, 0);
984
985 return -EFAULT;
986 }
987 }
988
989 psWrapExtMemOUT->eError =
990 PVRSRVWrapExtMemoryKM(hDevCookieInt,
991 psPerProc,
992 hDevMemContextInt,
993 psWrapExtMemIN->ui32ByteSize,
994 psWrapExtMemIN->ui32PageOffset,
995 psWrapExtMemIN->bPhysContig,
996 psSysPAddr,
997 psWrapExtMemIN->pvLinAddr,
998 psWrapExtMemIN->ui32Flags,
999 &psMemInfo);
1000
1001 if(psWrapExtMemIN->ui32NumPageTableEntries)
1002 {
1003 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
1004 ui32PageTableSize,
1005 (IMG_VOID *)psSysPAddr, 0);
1006
1007 }
1008
1009 if(psWrapExtMemOUT->eError != PVRSRV_OK)
1010 {
1011 return 0;
1012 }
1013
1014 psWrapExtMemOUT->sClientMemInfo.pvLinAddrKM =
1015 psMemInfo->pvLinAddrKM;
1016
1017
1018 psWrapExtMemOUT->sClientMemInfo.pvLinAddr = 0;
1019 psWrapExtMemOUT->sClientMemInfo.sDevVAddr = psMemInfo->sDevVAddr;
1020 psWrapExtMemOUT->sClientMemInfo.ui32Flags = psMemInfo->ui32Flags;
1021 psWrapExtMemOUT->sClientMemInfo.ui32AllocSize = psMemInfo->ui32AllocSize;
1022 psWrapExtMemOUT->sClientMemInfo.hMappingInfo = psMemInfo->sMemBlk.hOSMemHandle;
1023 1266
1024 PVRSRVAllocHandleNR(psPerProc->psHandleBase, 1267 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_WRAP_EXT_MEMORY);
1025 &psWrapExtMemOUT->sClientMemInfo.hKernelMemInfo, 1268
1026 psMemInfo, 1269 NEW_HANDLE_BATCH_OR_ERROR(psWrapExtMemOUT->eError, psPerProc, 2)
1027 PVRSRV_HANDLE_TYPE_MEM_INFO, 1270
1028 PVRSRV_HANDLE_ALLOC_FLAG_NONE); 1271
1272 psWrapExtMemOUT->eError =
1273 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt,
1274 psWrapExtMemIN->hDevCookie,
1275 PVRSRV_HANDLE_TYPE_DEV_NODE);
1276 if(psWrapExtMemOUT->eError != PVRSRV_OK)
1277 {
1278 return 0;
1279 }
1280
1281
1282 psWrapExtMemOUT->eError =
1283 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevMemContextInt,
1284 psWrapExtMemIN->hDevMemContext,
1285 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT);
1286
1287 if(psWrapExtMemOUT->eError != PVRSRV_OK)
1288 {
1289 return 0;
1290 }
1291
1292 if(psWrapExtMemIN->ui32NumPageTableEntries)
1293 {
1294 ui32PageTableSize = psWrapExtMemIN->ui32NumPageTableEntries
1295 * sizeof(IMG_SYS_PHYADDR);
1296
1297 ASSIGN_AND_EXIT_ON_ERROR(psWrapExtMemOUT->eError,
1298 OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
1299 ui32PageTableSize,
1300 (IMG_VOID **)&psSysPAddr, 0,
1301 "Page Table"));
1302
1303 if(CopyFromUserWrapper(psPerProc,
1304 ui32BridgeID,
1305 psSysPAddr,
1306 psWrapExtMemIN->psSysPAddr,
1307 ui32PageTableSize) != PVRSRV_OK)
1308 {
1309 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, ui32PageTableSize, (IMG_VOID *)psSysPAddr, 0);
1310
1311 return -EFAULT;
1312 }
1313 }
1314
1315 psWrapExtMemOUT->eError =
1316 PVRSRVWrapExtMemoryKM(hDevCookieInt,
1317 psPerProc,
1318 hDevMemContextInt,
1319 psWrapExtMemIN->ui32ByteSize,
1320 psWrapExtMemIN->ui32PageOffset,
1321 psWrapExtMemIN->bPhysContig,
1322 psSysPAddr,
1323 psWrapExtMemIN->pvLinAddr,
1324 psWrapExtMemIN->ui32Flags,
1325 &psMemInfo);
1326
1327 if(psWrapExtMemIN->ui32NumPageTableEntries)
1328 {
1329 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
1330 ui32PageTableSize,
1331 (IMG_VOID *)psSysPAddr, 0);
1332
1333 }
1334
1335 if(psWrapExtMemOUT->eError != PVRSRV_OK)
1336 {
1337 return 0;
1338 }
1339
1340 psWrapExtMemOUT->sClientMemInfo.pvLinAddrKM =
1341 psMemInfo->pvLinAddrKM;
1342
1343
1344 psWrapExtMemOUT->sClientMemInfo.pvLinAddr = 0;
1345 psWrapExtMemOUT->sClientMemInfo.sDevVAddr = psMemInfo->sDevVAddr;
1346 psWrapExtMemOUT->sClientMemInfo.ui32Flags = psMemInfo->ui32Flags;
1347 psWrapExtMemOUT->sClientMemInfo.uAllocSize = psMemInfo->uAllocSize;
1348#if defined (SUPPORT_SID_INTERFACE)
1349#else
1350 psWrapExtMemOUT->sClientMemInfo.hMappingInfo = psMemInfo->sMemBlk.hOSMemHandle;
1351#endif
1029 1352
1030 1353 PVRSRVAllocHandleNR(psPerProc->psHandleBase,
1031 psWrapExtMemOUT->sClientSyncInfo.psSyncData = 1354 &psWrapExtMemOUT->sClientMemInfo.hKernelMemInfo,
1032 psMemInfo->psKernelSyncInfo->psSyncData; 1355 psMemInfo,
1033 psWrapExtMemOUT->sClientSyncInfo.sWriteOpsCompleteDevVAddr = 1356 PVRSRV_HANDLE_TYPE_MEM_INFO,
1034 psMemInfo->psKernelSyncInfo->sWriteOpsCompleteDevVAddr; 1357 PVRSRV_HANDLE_ALLOC_FLAG_NONE);
1035 psWrapExtMemOUT->sClientSyncInfo.sReadOpsCompleteDevVAddr = 1358
1036 psMemInfo->psKernelSyncInfo->sReadOpsCompleteDevVAddr; 1359#if defined (SUPPORT_SID_INTERFACE)
1360
1361 if (psMemInfo->sMemBlk.hOSMemHandle != IMG_NULL)
1362 {
1363 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
1364 &psWrapExtMemOUT->sClientMemInfo.hMappingInfo,
1365 psMemInfo->sMemBlk.hOSMemHandle,
1366 PVRSRV_HANDLE_TYPE_MEM_INFO,
1367 PVRSRV_HANDLE_ALLOC_FLAG_NONE,
1368 psWrapExtMemOUT->sClientMemInfo.hKernelMemInfo);
1369 }
1370 else
1371 {
1372 psWrapExtMemOUT->sClientMemInfo.hMappingInfo = 0;
1373 }
1374#endif
1037 1375
1038 psWrapExtMemOUT->sClientSyncInfo.hMappingInfo = 1376
1039 psMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle; 1377#if !defined(PVRSRV_DISABLE_UM_SYNCOBJ_MAPPINGS)
1378 psWrapExtMemOUT->sClientSyncInfo.psSyncData =
1379 psMemInfo->psKernelSyncInfo->psSyncData;
1380 psWrapExtMemOUT->sClientSyncInfo.sWriteOpsCompleteDevVAddr =
1381 psMemInfo->psKernelSyncInfo->sWriteOpsCompleteDevVAddr;
1382 psWrapExtMemOUT->sClientSyncInfo.sReadOpsCompleteDevVAddr =
1383 psMemInfo->psKernelSyncInfo->sReadOpsCompleteDevVAddr;
1384
1385#if defined (SUPPORT_SID_INTERFACE)
1386
1387 if (psMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle != IMG_NULL)
1388 {
1389 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
1390 &psWrapExtMemOUT->sClientSyncInfo.hMappingInfo,
1391 psMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle,
1392 PVRSRV_HANDLE_TYPE_MEM_INFO,
1393 PVRSRV_HANDLE_ALLOC_FLAG_NONE,
1394 psWrapExtMemOUT->sClientMemInfo.hKernelMemInfo);
1395 }
1396 else
1397 {
1398 psWrapExtMemOUT->sClientSyncInfo.hMappingInfo = 0;
1399 }
1400#else
1401 psWrapExtMemOUT->sClientSyncInfo.hMappingInfo =
1402 psMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle;
1403#endif
1404#endif
1040 1405
1041 psWrapExtMemOUT->sClientMemInfo.psClientSyncInfo = &psWrapExtMemOUT->sClientSyncInfo; 1406 psWrapExtMemOUT->sClientMemInfo.psClientSyncInfo = &psWrapExtMemOUT->sClientSyncInfo;
1042 1407
1043 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase, 1408 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
1044 &psWrapExtMemOUT->sClientSyncInfo.hKernelSyncInfo, 1409 &psWrapExtMemOUT->sClientSyncInfo.hKernelSyncInfo,
1045 (IMG_HANDLE)psMemInfo->psKernelSyncInfo, 1410 (IMG_HANDLE)psMemInfo->psKernelSyncInfo,
1046 PVRSRV_HANDLE_TYPE_SYNC_INFO, 1411 PVRSRV_HANDLE_TYPE_SYNC_INFO,
1047 PVRSRV_HANDLE_ALLOC_FLAG_NONE, 1412 PVRSRV_HANDLE_ALLOC_FLAG_NONE,
1048 psWrapExtMemOUT->sClientMemInfo.hKernelMemInfo); 1413 psWrapExtMemOUT->sClientMemInfo.hKernelMemInfo);
1049 1414
1050 COMMIT_HANDLE_BATCH_OR_ERROR(psWrapExtMemOUT->eError, psPerProc) 1415 COMMIT_HANDLE_BATCH_OR_ERROR(psWrapExtMemOUT->eError, psPerProc)
1051 1416
1052 return 0; 1417 return 0;
1053} 1418}
1054#endif 1419#endif
1055 1420
1056static IMG_INT 1421static IMG_INT
1057PVRSRVUnwrapExtMemoryBW(IMG_UINT32 ui32BridgeID, 1422PVRSRVUnwrapExtMemoryBW(IMG_UINT32 ui32BridgeID,
1058 PVRSRV_BRIDGE_IN_UNWRAP_EXT_MEMORY *psUnwrapExtMemIN, 1423 PVRSRV_BRIDGE_IN_UNWRAP_EXT_MEMORY *psUnwrapExtMemIN,
1059 PVRSRV_BRIDGE_RETURN *psRetOUT, 1424 PVRSRV_BRIDGE_RETURN *psRetOUT,
1060 PVRSRV_PER_PROCESS_DATA *psPerProc) 1425 PVRSRV_PER_PROCESS_DATA *psPerProc)
1061{ 1426{
1062 IMG_VOID *pvMemInfo; 1427 IMG_VOID *pvMemInfo;
1063 1428
1064 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_UNWRAP_EXT_MEMORY); 1429 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_UNWRAP_EXT_MEMORY);
1065 1430
1066 psRetOUT->eError = 1431 psRetOUT->eError =
1067 PVRSRVLookupHandle(psPerProc->psHandleBase, 1432 PVRSRVLookupHandle(psPerProc->psHandleBase,
1068 &pvMemInfo, 1433 &pvMemInfo,
1069 psUnwrapExtMemIN->hKernelMemInfo, 1434 psUnwrapExtMemIN->hKernelMemInfo,
1070 PVRSRV_HANDLE_TYPE_MEM_INFO); 1435 PVRSRV_HANDLE_TYPE_MEM_INFO);
1071 if(psRetOUT->eError != PVRSRV_OK) 1436 if(psRetOUT->eError != PVRSRV_OK)
1072 { 1437 {
1073 return 0; 1438 return 0;
1074 } 1439 }
1075 1440
1076 psRetOUT->eError = 1441 psRetOUT->eError =
1077 PVRSRVUnwrapExtMemoryKM((PVRSRV_KERNEL_MEM_INFO *)pvMemInfo); 1442 PVRSRVUnwrapExtMemoryKM((PVRSRV_KERNEL_MEM_INFO *)pvMemInfo);
1078 if(psRetOUT->eError != PVRSRV_OK) 1443 if(psRetOUT->eError != PVRSRV_OK)
1079 { 1444 {
1080 return 0; 1445 return 0;
1081 } 1446 }
1082 1447
1083 psRetOUT->eError = 1448 psRetOUT->eError =
1084 PVRSRVReleaseHandle(psPerProc->psHandleBase, 1449 PVRSRVReleaseHandle(psPerProc->psHandleBase,
1085 psUnwrapExtMemIN->hKernelMemInfo, 1450 psUnwrapExtMemIN->hKernelMemInfo,
1086 PVRSRV_HANDLE_TYPE_MEM_INFO); 1451 PVRSRV_HANDLE_TYPE_MEM_INFO);
1087 1452
1088 return 0; 1453 return 0;
1089} 1454}
1090 1455
1091static IMG_INT 1456static IMG_INT
1092PVRSRVGetFreeDeviceMemBW(IMG_UINT32 ui32BridgeID, 1457PVRSRVGetFreeDeviceMemBW(IMG_UINT32 ui32BridgeID,
1093 PVRSRV_BRIDGE_IN_GETFREEDEVICEMEM *psGetFreeDeviceMemIN, 1458 PVRSRV_BRIDGE_IN_GETFREEDEVICEMEM *psGetFreeDeviceMemIN,
1094 PVRSRV_BRIDGE_OUT_GETFREEDEVICEMEM *psGetFreeDeviceMemOUT, 1459 PVRSRV_BRIDGE_OUT_GETFREEDEVICEMEM *psGetFreeDeviceMemOUT,
1095 PVRSRV_PER_PROCESS_DATA *psPerProc) 1460 PVRSRV_PER_PROCESS_DATA *psPerProc)
1096{ 1461{
1097 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GETFREE_DEVICEMEM); 1462 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GETFREE_DEVICEMEM);
1098 1463
1099 PVR_UNREFERENCED_PARAMETER(psPerProc); 1464 PVR_UNREFERENCED_PARAMETER(psPerProc);
1100 1465
1101 psGetFreeDeviceMemOUT->eError = 1466 psGetFreeDeviceMemOUT->eError =
1102 PVRSRVGetFreeDeviceMemKM(psGetFreeDeviceMemIN->ui32Flags, 1467 PVRSRVGetFreeDeviceMemKM(psGetFreeDeviceMemIN->ui32Flags,
1103 &psGetFreeDeviceMemOUT->ui32Total, 1468 &psGetFreeDeviceMemOUT->ui32Total,
1104 &psGetFreeDeviceMemOUT->ui32Free, 1469 &psGetFreeDeviceMemOUT->ui32Free,
1105 &psGetFreeDeviceMemOUT->ui32LargestBlock); 1470 &psGetFreeDeviceMemOUT->ui32LargestBlock);
1106 1471
1107 return 0; 1472 return 0;
1108} 1473}
1109 1474
1110static IMG_INT 1475static IMG_INT
1111PVRMMapOSMemHandleToMMapDataBW(IMG_UINT32 ui32BridgeID, 1476PVRMMapOSMemHandleToMMapDataBW(IMG_UINT32 ui32BridgeID,
1112 PVRSRV_BRIDGE_IN_MHANDLE_TO_MMAP_DATA *psMMapDataIN, 1477 PVRSRV_BRIDGE_IN_MHANDLE_TO_MMAP_DATA *psMMapDataIN,
1113 PVRSRV_BRIDGE_OUT_MHANDLE_TO_MMAP_DATA *psMMapDataOUT, 1478 PVRSRV_BRIDGE_OUT_MHANDLE_TO_MMAP_DATA *psMMapDataOUT,
1114 PVRSRV_PER_PROCESS_DATA *psPerProc) 1479 PVRSRV_PER_PROCESS_DATA *psPerProc)
1115{ 1480{
1116 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_MHANDLE_TO_MMAP_DATA); 1481 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_MHANDLE_TO_MMAP_DATA);
1117 1482
1118#if defined (__linux__) 1483#if defined (__linux__)
1119 psMMapDataOUT->eError = 1484 psMMapDataOUT->eError =
1120 PVRMMapOSMemHandleToMMapData(psPerProc, 1485 PVRMMapOSMemHandleToMMapData(psPerProc,
1121 psMMapDataIN->hMHandle, 1486 psMMapDataIN->hMHandle,
1122 &psMMapDataOUT->ui32MMapOffset, 1487 &psMMapDataOUT->ui32MMapOffset,
1123 &psMMapDataOUT->ui32ByteOffset, 1488 &psMMapDataOUT->ui32ByteOffset,
1124 &psMMapDataOUT->ui32RealByteSize, 1489 &psMMapDataOUT->ui32RealByteSize,
1125 &psMMapDataOUT->ui32UserVAddr); 1490 &psMMapDataOUT->ui32UserVAddr);
1126#else 1491#else
1127 PVR_UNREFERENCED_PARAMETER(psPerProc); 1492 PVR_UNREFERENCED_PARAMETER(psPerProc);
1128 PVR_UNREFERENCED_PARAMETER(psMMapDataIN); 1493 PVR_UNREFERENCED_PARAMETER(psMMapDataIN);
1129 1494
1130 psMMapDataOUT->eError = PVRSRV_ERROR_NOT_SUPPORTED; 1495 psMMapDataOUT->eError = PVRSRV_ERROR_NOT_SUPPORTED;
1131#endif 1496#endif
1132 return 0; 1497 return 0;
1133} 1498}
1134 1499
1135 1500
1136static IMG_INT 1501static IMG_INT
1137PVRMMapReleaseMMapDataBW(IMG_UINT32 ui32BridgeID, 1502PVRMMapReleaseMMapDataBW(IMG_UINT32 ui32BridgeID,
1138 PVRSRV_BRIDGE_IN_RELEASE_MMAP_DATA *psMMapDataIN, 1503 PVRSRV_BRIDGE_IN_RELEASE_MMAP_DATA *psMMapDataIN,
1139 PVRSRV_BRIDGE_OUT_RELEASE_MMAP_DATA *psMMapDataOUT, 1504 PVRSRV_BRIDGE_OUT_RELEASE_MMAP_DATA *psMMapDataOUT,
1140 PVRSRV_PER_PROCESS_DATA *psPerProc) 1505 PVRSRV_PER_PROCESS_DATA *psPerProc)
1141{ 1506{
1142 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_RELEASE_MMAP_DATA); 1507 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_RELEASE_MMAP_DATA);
1143 1508
1144#if defined (__linux__) 1509#if defined (__linux__)
1145 psMMapDataOUT->eError = 1510 psMMapDataOUT->eError =
1146 PVRMMapReleaseMMapData(psPerProc, 1511 PVRMMapReleaseMMapData(psPerProc,
1147 psMMapDataIN->hMHandle, 1512 psMMapDataIN->hMHandle,
1148 &psMMapDataOUT->bMUnmap, 1513 &psMMapDataOUT->bMUnmap,
1149 &psMMapDataOUT->ui32RealByteSize, 1514 &psMMapDataOUT->ui32RealByteSize,
1150 &psMMapDataOUT->ui32UserVAddr); 1515 &psMMapDataOUT->ui32UserVAddr);
1151#else 1516#else
1152
1153 PVR_UNREFERENCED_PARAMETER(psPerProc);
1154 PVR_UNREFERENCED_PARAMETER(psMMapDataIN);
1155 1517
1156 psMMapDataOUT->eError = PVRSRV_ERROR_NOT_SUPPORTED; 1518 PVR_UNREFERENCED_PARAMETER(psPerProc);
1157#endif 1519 PVR_UNREFERENCED_PARAMETER(psMMapDataIN);
1158 return 0; 1520
1521 psMMapDataOUT->eError = PVRSRV_ERROR_NOT_SUPPORTED;
1522#endif
1523 return 0;
1524}
1525
1526
1527#if defined (SUPPORT_SID_INTERFACE)
1528static IMG_INT
1529PVRSRVChangeDeviceMemoryAttributesBW(IMG_UINT32 ui32BridgeID,
1530 PVRSRV_BRIDGE_IN_CHG_DEV_MEM_ATTRIBS *psChgMemAttribIN,
1531 PVRSRV_BRIDGE_RETURN *psRetOUT,
1532 PVRSRV_PER_PROCESS_DATA *psPerProc)
1533{
1534 IMG_HANDLE hKernelMemInfo;
1535
1536 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_CHG_DEV_MEM_ATTRIBS);
1537
1538 psRetOUT->eError =
1539 PVRSRVLookupHandle(psPerProc->psHandleBase,
1540 &hKernelMemInfo,
1541 psChgMemAttribIN->hKernelMemInfo,
1542 PVRSRV_HANDLE_TYPE_MEM_INFO);
1543
1544 if(psRetOUT->eError != PVRSRV_OK)
1545 {
1546 return 0;
1547 }
1548
1549 psRetOUT->eError =
1550 PVRSRVChangeDeviceMemoryAttributesKM(hKernelMemInfo, psChgMemAttribIN->ui32Attribs);
1551
1552 return 0;
1159} 1553}
1554#else
1555static IMG_INT
1556PVRSRVChangeDeviceMemoryAttributesBW(IMG_UINT32 ui32BridgeID,
1557 PVRSRV_BRIDGE_IN_CHG_DEV_MEM_ATTRIBS *psChgMemAttribIN,
1558 PVRSRV_BRIDGE_RETURN *psRetOUT,
1559 PVRSRV_PER_PROCESS_DATA *psPerProc)
1560{
1561 PVR_UNREFERENCED_PARAMETER(ui32BridgeID);
1562 PVR_UNREFERENCED_PARAMETER(psChgMemAttribIN);
1563 PVR_UNREFERENCED_PARAMETER(psRetOUT);
1564 PVR_UNREFERENCED_PARAMETER(psPerProc);
1160 1565
1566 return 0;
1567}
1568#endif
1161 1569
1162#ifdef PDUMP 1570#ifdef PDUMP
1163static IMG_INT 1571static IMG_INT
1164PDumpIsCaptureFrameBW(IMG_UINT32 ui32BridgeID, 1572PDumpIsCaptureFrameBW(IMG_UINT32 ui32BridgeID,
1165 IMG_VOID *psBridgeIn, 1573 IMG_VOID *psBridgeIn,
1166 PVRSRV_BRIDGE_OUT_PDUMP_ISCAPTURING *psPDumpIsCapturingOUT, 1574 PVRSRV_BRIDGE_OUT_PDUMP_ISCAPTURING *psPDumpIsCapturingOUT,
1167 PVRSRV_PER_PROCESS_DATA *psPerProc) 1575 PVRSRV_PER_PROCESS_DATA *psPerProc)
1168{ 1576{
1169 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_ISCAPTURING); 1577 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_ISCAPTURING);
1170 PVR_UNREFERENCED_PARAMETER(psBridgeIn); 1578 PVR_UNREFERENCED_PARAMETER(psBridgeIn);
1171 PVR_UNREFERENCED_PARAMETER(psPerProc); 1579 PVR_UNREFERENCED_PARAMETER(psPerProc);
1172 1580
1173 psPDumpIsCapturingOUT->bIsCapturing = PDumpIsCaptureFrameKM(); 1581 psPDumpIsCapturingOUT->bIsCapturing = PDumpIsCaptureFrameKM();
1174 psPDumpIsCapturingOUT->eError = PVRSRV_OK; 1582 psPDumpIsCapturingOUT->eError = PVRSRV_OK;
1175 1583
1176 return 0; 1584 return 0;
1177} 1585}
1178 1586
1179static IMG_INT 1587static IMG_INT
1180PDumpCommentBW(IMG_UINT32 ui32BridgeID, 1588PDumpCommentBW(IMG_UINT32 ui32BridgeID,
1181 PVRSRV_BRIDGE_IN_PDUMP_COMMENT *psPDumpCommentIN, 1589 PVRSRV_BRIDGE_IN_PDUMP_COMMENT *psPDumpCommentIN,
1182 PVRSRV_BRIDGE_RETURN *psRetOUT, 1590 PVRSRV_BRIDGE_RETURN *psRetOUT,
1183 PVRSRV_PER_PROCESS_DATA *psPerProc) 1591 PVRSRV_PER_PROCESS_DATA *psPerProc)
1184{ 1592{
1185 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_COMMENT); 1593 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_COMMENT);
1186 PVR_UNREFERENCED_PARAMETER(psPerProc); 1594 PVR_UNREFERENCED_PARAMETER(psPerProc);
1187 1595
1188 psRetOUT->eError = PDumpCommentKM(&psPDumpCommentIN->szComment[0], 1596 psRetOUT->eError = PDumpCommentKM(&psPDumpCommentIN->szComment[0],
1189 psPDumpCommentIN->ui32Flags); 1597 psPDumpCommentIN->ui32Flags);
1190 return 0; 1598 return 0;
1191} 1599}
1192 1600
1193static IMG_INT 1601static IMG_INT
1194PDumpSetFrameBW(IMG_UINT32 ui32BridgeID, 1602PDumpSetFrameBW(IMG_UINT32 ui32BridgeID,
1195 PVRSRV_BRIDGE_IN_PDUMP_SETFRAME *psPDumpSetFrameIN, 1603 PVRSRV_BRIDGE_IN_PDUMP_SETFRAME *psPDumpSetFrameIN,
1196 PVRSRV_BRIDGE_RETURN *psRetOUT, 1604 PVRSRV_BRIDGE_RETURN *psRetOUT,
1197 PVRSRV_PER_PROCESS_DATA *psPerProc) 1605 PVRSRV_PER_PROCESS_DATA *psPerProc)
1198{ 1606{
1199 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_SETFRAME); 1607 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_SETFRAME);
1200 PVR_UNREFERENCED_PARAMETER(psPerProc); 1608 PVR_UNREFERENCED_PARAMETER(psPerProc);
1201 1609
1202 psRetOUT->eError = PDumpSetFrameKM(psPDumpSetFrameIN->ui32Frame); 1610 psRetOUT->eError = PDumpSetFrameKM(psPDumpSetFrameIN->ui32Frame);
1203 1611
1204 return 0; 1612 return 0;
1205} 1613}
1206 1614
1207static IMG_INT 1615static IMG_INT
1208PDumpRegWithFlagsBW(IMG_UINT32 ui32BridgeID, 1616PDumpRegWithFlagsBW(IMG_UINT32 ui32BridgeID,
1209 PVRSRV_BRIDGE_IN_PDUMP_DUMPREG *psPDumpRegDumpIN, 1617 PVRSRV_BRIDGE_IN_PDUMP_DUMPREG *psPDumpRegDumpIN,
1210 PVRSRV_BRIDGE_RETURN *psRetOUT, 1618 PVRSRV_BRIDGE_RETURN *psRetOUT,
1211 PVRSRV_PER_PROCESS_DATA *psPerProc) 1619 PVRSRV_PER_PROCESS_DATA *psPerProc)
1212{ 1620{
1213 PVRSRV_DEVICE_NODE *psDeviceNode; 1621 PVRSRV_DEVICE_NODE *psDeviceNode;
1214 1622
1215 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_REG); 1623 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_REG);
1216 1624
1217 psRetOUT->eError = 1625 psRetOUT->eError =
1218 PVRSRVLookupHandle(psPerProc->psHandleBase, 1626 PVRSRVLookupHandle(psPerProc->psHandleBase,
1219 (IMG_VOID **)&psDeviceNode, 1627 (IMG_VOID **)&psDeviceNode,
1220 psPDumpRegDumpIN->hDevCookie, 1628 psPDumpRegDumpIN->hDevCookie,
1221 PVRSRV_HANDLE_TYPE_DEV_NODE); 1629 PVRSRV_HANDLE_TYPE_DEV_NODE);
1222 if(psRetOUT->eError != PVRSRV_OK) 1630 if(psRetOUT->eError != PVRSRV_OK)
1223 { 1631 {
1224 return 0; 1632 return 0;
1225 } 1633 }
1226 1634
1227 psRetOUT->eError = PDumpRegWithFlagsKM (psPDumpRegDumpIN->szRegRegion, 1635 psRetOUT->eError = PDumpRegWithFlagsKM (psPDumpRegDumpIN->szRegRegion,
1228 psPDumpRegDumpIN->sHWReg.ui32RegAddr, 1636 psPDumpRegDumpIN->sHWReg.ui32RegAddr,
1229 psPDumpRegDumpIN->sHWReg.ui32RegVal, 1637 psPDumpRegDumpIN->sHWReg.ui32RegVal,
1230 psPDumpRegDumpIN->ui32Flags); 1638 psPDumpRegDumpIN->ui32Flags);
1231 1639
1232 return 0; 1640 return 0;
1233} 1641}
1234 1642
1235static IMG_INT 1643static IMG_INT
1236PDumpRegPolBW(IMG_UINT32 ui32BridgeID, 1644PDumpRegPolBW(IMG_UINT32 ui32BridgeID,
1237 PVRSRV_BRIDGE_IN_PDUMP_REGPOL *psPDumpRegPolIN, 1645 PVRSRV_BRIDGE_IN_PDUMP_REGPOL *psPDumpRegPolIN,
1238 PVRSRV_BRIDGE_RETURN *psRetOUT, 1646 PVRSRV_BRIDGE_RETURN *psRetOUT,
1239 PVRSRV_PER_PROCESS_DATA *psPerProc) 1647 PVRSRV_PER_PROCESS_DATA *psPerProc)
1240{ 1648{
1241 PVRSRV_DEVICE_NODE *psDeviceNode; 1649 PVRSRV_DEVICE_NODE *psDeviceNode;
1242 1650
1243 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_REGPOL); 1651 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_REGPOL);
1244 1652
1245 psRetOUT->eError = 1653 psRetOUT->eError =
1246 PVRSRVLookupHandle(psPerProc->psHandleBase, 1654 PVRSRVLookupHandle(psPerProc->psHandleBase,
1247 (IMG_VOID **)&psDeviceNode, 1655 (IMG_VOID **)&psDeviceNode,
1248 psPDumpRegPolIN->hDevCookie, 1656 psPDumpRegPolIN->hDevCookie,
1249 PVRSRV_HANDLE_TYPE_DEV_NODE); 1657 PVRSRV_HANDLE_TYPE_DEV_NODE);
1250 if(psRetOUT->eError != PVRSRV_OK) 1658 if(psRetOUT->eError != PVRSRV_OK)
1251 { 1659 {
1252 return 0; 1660 return 0;
1253 } 1661 }
1254 1662
1255 1663
1256 psRetOUT->eError = 1664 psRetOUT->eError =
1257 PDumpRegPolWithFlagsKM(psPDumpRegPolIN->szRegRegion, 1665 PDumpRegPolWithFlagsKM(psPDumpRegPolIN->szRegRegion,
1258 psPDumpRegPolIN->sHWReg.ui32RegAddr, 1666 psPDumpRegPolIN->sHWReg.ui32RegAddr,
1259 psPDumpRegPolIN->sHWReg.ui32RegVal, 1667 psPDumpRegPolIN->sHWReg.ui32RegVal,
1260 psPDumpRegPolIN->ui32Mask, 1668 psPDumpRegPolIN->ui32Mask,
1261 psPDumpRegPolIN->ui32Flags); 1669 psPDumpRegPolIN->ui32Flags,
1262 1670 PDUMP_POLL_OPERATOR_EQUAL);
1263 return 0; 1671
1672 return 0;
1264} 1673}
1265 1674
1266static IMG_INT 1675static IMG_INT
1267PDumpMemPolBW(IMG_UINT32 ui32BridgeID, 1676PDumpMemPolBW(IMG_UINT32 ui32BridgeID,
1268 PVRSRV_BRIDGE_IN_PDUMP_MEMPOL *psPDumpMemPolIN, 1677 PVRSRV_BRIDGE_IN_PDUMP_MEMPOL *psPDumpMemPolIN,
1269 PVRSRV_BRIDGE_RETURN *psRetOUT, 1678 PVRSRV_BRIDGE_RETURN *psRetOUT,
1270 PVRSRV_PER_PROCESS_DATA *psPerProc) 1679 PVRSRV_PER_PROCESS_DATA *psPerProc)
1271{ 1680{
1272 IMG_VOID *pvMemInfo; 1681 IMG_VOID *pvMemInfo;
1273
1274 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_MEMPOL);
1275
1276 psRetOUT->eError =
1277 PVRSRVLookupHandle(psPerProc->psHandleBase,
1278 &pvMemInfo,
1279 psPDumpMemPolIN->psKernelMemInfo,
1280 PVRSRV_HANDLE_TYPE_MEM_INFO);
1281 if(psRetOUT->eError != PVRSRV_OK)
1282 {
1283 return 0;
1284 }
1285 1682
1286 psRetOUT->eError = 1683 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_MEMPOL);
1287 PDumpMemPolKM(((PVRSRV_KERNEL_MEM_INFO *)pvMemInfo),
1288 psPDumpMemPolIN->ui32Offset,
1289 psPDumpMemPolIN->ui32Value,
1290 psPDumpMemPolIN->ui32Mask,
1291 psPDumpMemPolIN->eOperator,
1292 psPDumpMemPolIN->ui32Flags,
1293 MAKEUNIQUETAG(pvMemInfo));
1294 1684
1295 return 0; 1685 psRetOUT->eError =
1686 PVRSRVLookupHandle(psPerProc->psHandleBase,
1687 &pvMemInfo,
1688#if defined (SUPPORT_SID_INTERFACE)
1689 psPDumpMemPolIN->hKernelMemInfo,
1690#else
1691 psPDumpMemPolIN->psKernelMemInfo,
1692#endif
1693 PVRSRV_HANDLE_TYPE_MEM_INFO);
1694 if(psRetOUT->eError != PVRSRV_OK)
1695 {
1696 return 0;
1697 }
1698
1699 psRetOUT->eError =
1700 PDumpMemPolKM(((PVRSRV_KERNEL_MEM_INFO *)pvMemInfo),
1701 psPDumpMemPolIN->ui32Offset,
1702 psPDumpMemPolIN->ui32Value,
1703 psPDumpMemPolIN->ui32Mask,
1704 psPDumpMemPolIN->eOperator,
1705 psPDumpMemPolIN->ui32Flags,
1706 MAKEUNIQUETAG(pvMemInfo));
1707
1708 return 0;
1296} 1709}
1297 1710
1298static IMG_INT 1711static IMG_INT
1299PDumpMemBW(IMG_UINT32 ui32BridgeID, 1712PDumpMemBW(IMG_UINT32 ui32BridgeID,
1300 PVRSRV_BRIDGE_IN_PDUMP_DUMPMEM *psPDumpMemDumpIN, 1713 PVRSRV_BRIDGE_IN_PDUMP_DUMPMEM *psPDumpMemDumpIN,
1301 PVRSRV_BRIDGE_RETURN *psRetOUT, 1714 PVRSRV_BRIDGE_RETURN *psRetOUT,
1302 PVRSRV_PER_PROCESS_DATA *psPerProc) 1715 PVRSRV_PER_PROCESS_DATA *psPerProc)
1303{ 1716{
1304 IMG_VOID *pvMemInfo; 1717 IMG_VOID *pvMemInfo;
1305
1306 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_DUMPMEM);
1307
1308 psRetOUT->eError =
1309 PVRSRVLookupHandle(psPerProc->psHandleBase,
1310 &pvMemInfo,
1311 psPDumpMemDumpIN->psKernelMemInfo,
1312 PVRSRV_HANDLE_TYPE_MEM_INFO);
1313 if(psRetOUT->eError != PVRSRV_OK)
1314 {
1315 return 0;
1316 }
1317 1718
1318 psRetOUT->eError = 1719 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_DUMPMEM);
1319 PDumpMemUM(psPerProc,
1320 psPDumpMemDumpIN->pvAltLinAddr,
1321 psPDumpMemDumpIN->pvLinAddr,
1322 pvMemInfo,
1323 psPDumpMemDumpIN->ui32Offset,
1324 psPDumpMemDumpIN->ui32Bytes,
1325 psPDumpMemDumpIN->ui32Flags,
1326 MAKEUNIQUETAG(pvMemInfo));
1327 1720
1328 return 0; 1721 psRetOUT->eError =
1722 PVRSRVLookupHandle(psPerProc->psHandleBase,
1723 &pvMemInfo,
1724#if defined (SUPPORT_SID_INTERFACE)
1725 psPDumpMemDumpIN->hKernelMemInfo,
1726#else
1727 psPDumpMemDumpIN->psKernelMemInfo,
1728#endif
1729 PVRSRV_HANDLE_TYPE_MEM_INFO);
1730 if(psRetOUT->eError != PVRSRV_OK)
1731 {
1732 return 0;
1733 }
1734
1735 psRetOUT->eError =
1736 PDumpMemUM(psPerProc,
1737 psPDumpMemDumpIN->pvAltLinAddr,
1738 psPDumpMemDumpIN->pvLinAddr,
1739 pvMemInfo,
1740 psPDumpMemDumpIN->ui32Offset,
1741 psPDumpMemDumpIN->ui32Bytes,
1742 psPDumpMemDumpIN->ui32Flags,
1743 MAKEUNIQUETAG(pvMemInfo));
1744
1745 return 0;
1329} 1746}
1330 1747
1331static IMG_INT 1748static IMG_INT
1332PDumpBitmapBW(IMG_UINT32 ui32BridgeID, 1749PDumpBitmapBW(IMG_UINT32 ui32BridgeID,
1333 PVRSRV_BRIDGE_IN_PDUMP_BITMAP *psPDumpBitmapIN, 1750 PVRSRV_BRIDGE_IN_PDUMP_BITMAP *psPDumpBitmapIN,
1334 PVRSRV_BRIDGE_RETURN *psRetOUT, 1751 PVRSRV_BRIDGE_RETURN *psRetOUT,
1335 PVRSRV_PER_PROCESS_DATA *psPerProc) 1752 PVRSRV_PER_PROCESS_DATA *psPerProc)
1336{ 1753{
1337 PVRSRV_DEVICE_NODE *psDeviceNode; 1754 PVRSRV_DEVICE_NODE *psDeviceNode;
1338 IMG_HANDLE hDevMemContextInt; 1755 IMG_HANDLE hDevMemContextInt;
1339 1756
1340 PVR_UNREFERENCED_PARAMETER(ui32BridgeID); 1757 PVR_UNREFERENCED_PARAMETER(ui32BridgeID);
1341 1758
1342 psRetOUT->eError = 1759 psRetOUT->eError =
1343 PVRSRVLookupHandle(psPerProc->psHandleBase, (IMG_VOID **)&psDeviceNode, 1760 PVRSRVLookupHandle(psPerProc->psHandleBase, (IMG_VOID **)&psDeviceNode,
1344 psPDumpBitmapIN->hDevCookie, 1761 psPDumpBitmapIN->hDevCookie,
1345 PVRSRV_HANDLE_TYPE_DEV_NODE); 1762 PVRSRV_HANDLE_TYPE_DEV_NODE);
1346 1763
1347 psRetOUT->eError = 1764 psRetOUT->eError =
1348 PVRSRVLookupHandle( psPerProc->psHandleBase, 1765 PVRSRVLookupHandle( psPerProc->psHandleBase,
1349 &hDevMemContextInt, 1766 &hDevMemContextInt,
1350 psPDumpBitmapIN->hDevMemContext, 1767 psPDumpBitmapIN->hDevMemContext,
1351 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT); 1768 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT);
1352 1769
1353 if(psRetOUT->eError != PVRSRV_OK) 1770 if(psRetOUT->eError != PVRSRV_OK)
1354 { 1771 {
1355 return 0; 1772 return 0;
1356 } 1773 }
1357 1774
1358 psRetOUT->eError = 1775 psRetOUT->eError =
1359 PDumpBitmapKM(psDeviceNode, 1776 PDumpBitmapKM(psDeviceNode,
1360 &psPDumpBitmapIN->szFileName[0], 1777 &psPDumpBitmapIN->szFileName[0],
1361 psPDumpBitmapIN->ui32FileOffset, 1778 psPDumpBitmapIN->ui32FileOffset,
1362 psPDumpBitmapIN->ui32Width, 1779 psPDumpBitmapIN->ui32Width,
1363 psPDumpBitmapIN->ui32Height, 1780 psPDumpBitmapIN->ui32Height,
1364 psPDumpBitmapIN->ui32StrideInBytes, 1781 psPDumpBitmapIN->ui32StrideInBytes,
1365 psPDumpBitmapIN->sDevBaseAddr, 1782 psPDumpBitmapIN->sDevBaseAddr,
1366 hDevMemContextInt, 1783 hDevMemContextInt,
1367 psPDumpBitmapIN->ui32Size, 1784 psPDumpBitmapIN->ui32Size,
1368 psPDumpBitmapIN->ePixelFormat, 1785 psPDumpBitmapIN->ePixelFormat,
1369 psPDumpBitmapIN->eMemFormat, 1786 psPDumpBitmapIN->eMemFormat,
1370 psPDumpBitmapIN->ui32Flags); 1787 psPDumpBitmapIN->ui32Flags);
1371 1788
1372 return 0; 1789 return 0;
1373} 1790}
1374 1791
1375static IMG_INT 1792static IMG_INT
1376PDumpReadRegBW(IMG_UINT32 ui32BridgeID, 1793PDumpReadRegBW(IMG_UINT32 ui32BridgeID,
1377 PVRSRV_BRIDGE_IN_PDUMP_READREG *psPDumpReadRegIN, 1794 PVRSRV_BRIDGE_IN_PDUMP_READREG *psPDumpReadRegIN,
1378 PVRSRV_BRIDGE_RETURN *psRetOUT, 1795 PVRSRV_BRIDGE_RETURN *psRetOUT,
1379 PVRSRV_PER_PROCESS_DATA *psPerProc) 1796 PVRSRV_PER_PROCESS_DATA *psPerProc)
1380{ 1797{
1381 PVRSRV_DEVICE_NODE *psDeviceNode; 1798 PVRSRV_DEVICE_NODE *psDeviceNode;
1382 1799
1383 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_DUMPREADREG); 1800 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_DUMPREADREG);
1384 1801
1385 psRetOUT->eError = 1802 psRetOUT->eError =
1386 PVRSRVLookupHandle(psPerProc->psHandleBase, (IMG_VOID **)&psDeviceNode, 1803 PVRSRVLookupHandle(psPerProc->psHandleBase, (IMG_VOID **)&psDeviceNode,
1387 psPDumpReadRegIN->hDevCookie, 1804 psPDumpReadRegIN->hDevCookie,
1388 PVRSRV_HANDLE_TYPE_DEV_NODE); 1805 PVRSRV_HANDLE_TYPE_DEV_NODE);
1389 1806
1390 psRetOUT->eError = 1807 psRetOUT->eError =
1391 PDumpReadRegKM(&psPDumpReadRegIN->szRegRegion[0], 1808 PDumpReadRegKM(&psPDumpReadRegIN->szRegRegion[0],
1392 &psPDumpReadRegIN->szFileName[0], 1809 &psPDumpReadRegIN->szFileName[0],
1393 psPDumpReadRegIN->ui32FileOffset, 1810 psPDumpReadRegIN->ui32FileOffset,
1394 psPDumpReadRegIN->ui32Address, 1811 psPDumpReadRegIN->ui32Address,
1395 psPDumpReadRegIN->ui32Size, 1812 psPDumpReadRegIN->ui32Size,
1396 psPDumpReadRegIN->ui32Flags); 1813 psPDumpReadRegIN->ui32Flags);
1397 1814
1398 return 0; 1815 return 0;
1399} 1816}
1400 1817
1401static IMG_INT 1818static IMG_INT
1402PDumpDriverInfoBW(IMG_UINT32 ui32BridgeID, 1819PDumpMemPagesBW(IMG_UINT32 ui32BridgeID,
1403 PVRSRV_BRIDGE_IN_PDUMP_DRIVERINFO *psPDumpDriverInfoIN, 1820 PVRSRV_BRIDGE_IN_PDUMP_MEMPAGES *psPDumpMemPagesIN,
1404 PVRSRV_BRIDGE_RETURN *psRetOUT, 1821 PVRSRV_BRIDGE_RETURN *psRetOUT,
1405 PVRSRV_PER_PROCESS_DATA *psPerProc) 1822 PVRSRV_PER_PROCESS_DATA *psPerProc)
1406{ 1823{
1407 IMG_UINT32 ui32PDumpFlags; 1824 PVRSRV_DEVICE_NODE *psDeviceNode;
1408 1825
1409 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_DRIVERINFO); 1826 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_MEMPAGES);
1410 PVR_UNREFERENCED_PARAMETER(psPerProc);
1411 1827
1412 ui32PDumpFlags = 0; 1828 psRetOUT->eError =
1413 if(psPDumpDriverInfoIN->bContinuous) 1829 PVRSRVLookupHandle(psPerProc->psHandleBase,
1414 { 1830 (IMG_VOID **)&psDeviceNode,
1415 ui32PDumpFlags |= PDUMP_FLAGS_CONTINUOUS; 1831 psPDumpMemPagesIN->hDevCookie,
1416 } 1832 PVRSRV_HANDLE_TYPE_DEV_NODE);
1417 psRetOUT->eError =
1418 PDumpDriverInfoKM(&psPDumpDriverInfoIN->szString[0],
1419 ui32PDumpFlags);
1420 1833
1421 return 0; 1834 if(psRetOUT->eError != PVRSRV_OK)
1835 {
1836 return 0;
1837 }
1838
1839
1840 return 0;
1422} 1841}
1423 1842
1424static IMG_INT 1843static IMG_INT
1425PDumpSyncDumpBW(IMG_UINT32 ui32BridgeID, 1844PDumpDriverInfoBW(IMG_UINT32 ui32BridgeID,
1426 PVRSRV_BRIDGE_IN_PDUMP_DUMPSYNC *psPDumpSyncDumpIN, 1845 PVRSRV_BRIDGE_IN_PDUMP_DRIVERINFO *psPDumpDriverInfoIN,
1427 PVRSRV_BRIDGE_RETURN *psRetOUT, 1846 PVRSRV_BRIDGE_RETURN *psRetOUT,
1428 PVRSRV_PER_PROCESS_DATA *psPerProc) 1847 PVRSRV_PER_PROCESS_DATA *psPerProc)
1429{ 1848{
1430 IMG_UINT32 ui32Bytes = psPDumpSyncDumpIN->ui32Bytes; 1849 IMG_UINT32 ui32PDumpFlags;
1431 IMG_VOID *pvSyncInfo;
1432
1433 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_DUMPSYNC);
1434 1850
1435 psRetOUT->eError = 1851 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_DRIVERINFO);
1436 PVRSRVLookupHandle(psPerProc->psHandleBase, &pvSyncInfo, 1852 PVR_UNREFERENCED_PARAMETER(psPerProc);
1437 psPDumpSyncDumpIN->psKernelSyncInfo,
1438 PVRSRV_HANDLE_TYPE_SYNC_INFO);
1439 if(psRetOUT->eError != PVRSRV_OK)
1440 {
1441 return 0;
1442 }
1443 1853
1444 psRetOUT->eError = 1854 ui32PDumpFlags = 0;
1445 PDumpMemUM(psPerProc, 1855 if(psPDumpDriverInfoIN->bContinuous)
1446 psPDumpSyncDumpIN->pvAltLinAddr, 1856 {
1447 IMG_NULL, 1857 ui32PDumpFlags |= PDUMP_FLAGS_CONTINUOUS;
1448 ((PVRSRV_KERNEL_SYNC_INFO *)pvSyncInfo)->psSyncDataMemInfoKM, 1858 }
1449 psPDumpSyncDumpIN->ui32Offset, 1859 psRetOUT->eError =
1450 ui32Bytes, 1860 PDumpDriverInfoKM(&psPDumpDriverInfoIN->szString[0],
1451 0, 1861 ui32PDumpFlags);
1452 MAKEUNIQUETAG(((PVRSRV_KERNEL_SYNC_INFO *)pvSyncInfo)->psSyncDataMemInfoKM));
1453 1862
1454 return 0; 1863 return 0;
1455} 1864}
1456 1865
1457static IMG_INT 1866static IMG_INT
1458PDumpSyncPolBW(IMG_UINT32 ui32BridgeID, 1867PDumpSyncDumpBW(IMG_UINT32 ui32BridgeID,
1459 PVRSRV_BRIDGE_IN_PDUMP_SYNCPOL *psPDumpSyncPolIN, 1868 PVRSRV_BRIDGE_IN_PDUMP_DUMPSYNC *psPDumpSyncDumpIN,
1460 PVRSRV_BRIDGE_RETURN *psRetOUT, 1869 PVRSRV_BRIDGE_RETURN *psRetOUT,
1461 PVRSRV_PER_PROCESS_DATA *psPerProc) 1870 PVRSRV_PER_PROCESS_DATA *psPerProc)
1462{ 1871{
1463 IMG_UINT32 ui32Offset; 1872 IMG_UINT32 ui32Bytes = psPDumpSyncDumpIN->ui32Bytes;
1464 IMG_VOID *pvSyncInfo; 1873 IMG_VOID *pvSyncInfo;
1465 1874
1466 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_SYNCPOL); 1875 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_DUMPSYNC);
1467 1876
1468 psRetOUT->eError = 1877 psRetOUT->eError =
1469 PVRSRVLookupHandle(psPerProc->psHandleBase, &pvSyncInfo, 1878 PVRSRVLookupHandle(psPerProc->psHandleBase, &pvSyncInfo,
1470 psPDumpSyncPolIN->psKernelSyncInfo, 1879#if defined (SUPPORT_SID_INTERFACE)
1471 PVRSRV_HANDLE_TYPE_SYNC_INFO); 1880 psPDumpSyncDumpIN->hKernelSyncInfo,
1472 if(psRetOUT->eError != PVRSRV_OK) 1881#else
1473 { 1882 psPDumpSyncDumpIN->psKernelSyncInfo,
1474 return 0; 1883#endif
1475 } 1884 PVRSRV_HANDLE_TYPE_SYNC_INFO);
1476 1885 if(psRetOUT->eError != PVRSRV_OK)
1477 if(psPDumpSyncPolIN->bIsRead) 1886 {
1478 { 1887 return 0;
1479 ui32Offset = offsetof(PVRSRV_SYNC_DATA, ui32ReadOpsComplete); 1888 }
1480 } 1889
1481 else 1890 psRetOUT->eError =
1482 { 1891 PDumpMemUM(psPerProc,
1483 ui32Offset = offsetof(PVRSRV_SYNC_DATA, ui32WriteOpsComplete); 1892 psPDumpSyncDumpIN->pvAltLinAddr,
1484 } 1893 IMG_NULL,
1485 1894 ((PVRSRV_KERNEL_SYNC_INFO *)pvSyncInfo)->psSyncDataMemInfoKM,
1486 psRetOUT->eError = 1895 psPDumpSyncDumpIN->ui32Offset,
1487 PDumpMemPolKM(((PVRSRV_KERNEL_SYNC_INFO *)pvSyncInfo)->psSyncDataMemInfoKM, 1896 ui32Bytes,
1488 ui32Offset, 1897 0,
1489 psPDumpSyncPolIN->ui32Value, 1898 MAKEUNIQUETAG(((PVRSRV_KERNEL_SYNC_INFO *)pvSyncInfo)->psSyncDataMemInfoKM));
1490 psPDumpSyncPolIN->ui32Mask, 1899
1491 PDUMP_POLL_OPERATOR_EQUAL, 1900 return 0;
1492 0, 1901}
1493 MAKEUNIQUETAG(((PVRSRV_KERNEL_SYNC_INFO *)pvSyncInfo)->psSyncDataMemInfoKM));
1494 1902
1495 return 0; 1903static IMG_INT
1904PDumpSyncPolBW(IMG_UINT32 ui32BridgeID,
1905 PVRSRV_BRIDGE_IN_PDUMP_SYNCPOL *psPDumpSyncPolIN,
1906 PVRSRV_BRIDGE_RETURN *psRetOUT,
1907 PVRSRV_PER_PROCESS_DATA *psPerProc)
1908{
1909 IMG_UINT32 ui32Offset;
1910 IMG_VOID *pvSyncInfo;
1911 IMG_UINT32 ui32Value;
1912 IMG_UINT32 ui32Mask;
1913
1914 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_SYNCPOL);
1915
1916 psRetOUT->eError =
1917 PVRSRVLookupHandle(psPerProc->psHandleBase,
1918 &pvSyncInfo,
1919#if defined (SUPPORT_SID_INTERFACE)
1920 psPDumpSyncPolIN->hKernelSyncInfo,
1921#else
1922 psPDumpSyncPolIN->psKernelSyncInfo,
1923#endif
1924 PVRSRV_HANDLE_TYPE_SYNC_INFO);
1925 if(psRetOUT->eError != PVRSRV_OK)
1926 {
1927 return 0;
1928 }
1929
1930 if(psPDumpSyncPolIN->bIsRead)
1931 {
1932 ui32Offset = offsetof(PVRSRV_SYNC_DATA, ui32ReadOpsComplete);
1933 }
1934 else
1935 {
1936 ui32Offset = offsetof(PVRSRV_SYNC_DATA, ui32WriteOpsComplete);
1937 }
1938
1939
1940 if (psPDumpSyncPolIN->bUseLastOpDumpVal)
1941 {
1942 if(psPDumpSyncPolIN->bIsRead)
1943 {
1944 ui32Value = ((PVRSRV_KERNEL_SYNC_INFO *)pvSyncInfo)->psSyncData->ui32LastReadOpDumpVal;
1945 }
1946 else
1947 {
1948 ui32Value = ((PVRSRV_KERNEL_SYNC_INFO *)pvSyncInfo)->psSyncData->ui32LastOpDumpVal;
1949 }
1950 ui32Mask = 0xffffffff;
1951 }
1952 else
1953 {
1954 ui32Value = psPDumpSyncPolIN->ui32Value;
1955 ui32Mask = psPDumpSyncPolIN->ui32Mask;
1956 }
1957
1958 psRetOUT->eError =
1959 PDumpMemPolKM(((PVRSRV_KERNEL_SYNC_INFO *)pvSyncInfo)->psSyncDataMemInfoKM,
1960 ui32Offset,
1961 ui32Value,
1962 ui32Mask,
1963 PDUMP_POLL_OPERATOR_EQUAL,
1964 0,
1965 MAKEUNIQUETAG(((PVRSRV_KERNEL_SYNC_INFO *)pvSyncInfo)->psSyncDataMemInfoKM));
1966
1967 return 0;
1496} 1968}
1497 1969
1498 1970
1499static IMG_INT 1971static IMG_INT
1500PDumpCycleCountRegReadBW(IMG_UINT32 ui32BridgeID, 1972PDumpCycleCountRegReadBW(IMG_UINT32 ui32BridgeID,
1501 PVRSRV_BRIDGE_IN_PDUMP_CYCLE_COUNT_REG_READ *psPDumpCycleCountRegReadIN, 1973 PVRSRV_BRIDGE_IN_PDUMP_CYCLE_COUNT_REG_READ *psPDumpCycleCountRegReadIN,
1502 PVRSRV_BRIDGE_RETURN *psRetOUT, 1974 PVRSRV_BRIDGE_RETURN *psRetOUT,
1503 PVRSRV_PER_PROCESS_DATA *psPerProc) 1975 PVRSRV_PER_PROCESS_DATA *psPerProc)
1504{ 1976{
1505 PVRSRV_DEVICE_NODE *psDeviceNode; 1977 PVRSRV_DEVICE_NODE *psDeviceNode;
1506
1507 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_CYCLE_COUNT_REG_READ);
1508
1509 psRetOUT->eError =
1510 PVRSRVLookupHandle(psPerProc->psHandleBase,
1511 (IMG_VOID **)&psDeviceNode,
1512 psPDumpCycleCountRegReadIN->hDevCookie,
1513 PVRSRV_HANDLE_TYPE_DEV_NODE);
1514 if(psRetOUT->eError != PVRSRV_OK)
1515 {
1516 return 0;
1517 }
1518 1978
1519 PDumpCycleCountRegRead(&psDeviceNode->sDevId, 1979 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_CYCLE_COUNT_REG_READ);
1520 psPDumpCycleCountRegReadIN->ui32RegOffset,
1521 psPDumpCycleCountRegReadIN->bLastFrame);
1522 1980
1523 psRetOUT->eError = PVRSRV_OK; 1981 psRetOUT->eError =
1982 PVRSRVLookupHandle(psPerProc->psHandleBase,
1983 (IMG_VOID **)&psDeviceNode,
1984 psPDumpCycleCountRegReadIN->hDevCookie,
1985 PVRSRV_HANDLE_TYPE_DEV_NODE);
1986 if(psRetOUT->eError != PVRSRV_OK)
1987 {
1988 return 0;
1989 }
1524 1990
1525 return 0; 1991 PDumpCycleCountRegRead(&psDeviceNode->sDevId,
1992 psPDumpCycleCountRegReadIN->ui32RegOffset,
1993 psPDumpCycleCountRegReadIN->bLastFrame);
1994
1995 psRetOUT->eError = PVRSRV_OK;
1996
1997 return 0;
1526} 1998}
1527 1999
1528static IMG_INT 2000static IMG_INT
1529PDumpPDDevPAddrBW(IMG_UINT32 ui32BridgeID, 2001PDumpPDDevPAddrBW(IMG_UINT32 ui32BridgeID,
1530 PVRSRV_BRIDGE_IN_PDUMP_DUMPPDDEVPADDR *psPDumpPDDevPAddrIN, 2002 PVRSRV_BRIDGE_IN_PDUMP_DUMPPDDEVPADDR *psPDumpPDDevPAddrIN,
1531 PVRSRV_BRIDGE_RETURN *psRetOUT, 2003 PVRSRV_BRIDGE_RETURN *psRetOUT,
1532 PVRSRV_PER_PROCESS_DATA *psPerProc) 2004 PVRSRV_PER_PROCESS_DATA *psPerProc)
1533{ 2005{
1534 IMG_VOID *pvMemInfo; 2006 IMG_VOID *pvMemInfo;
1535 2007
1536 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_DUMPPDDEVPADDR); 2008 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_DUMPPDDEVPADDR);
1537 2009
1538 psRetOUT->eError = 2010 psRetOUT->eError =
1539 PVRSRVLookupHandle(psPerProc->psHandleBase, &pvMemInfo, 2011 PVRSRVLookupHandle(psPerProc->psHandleBase, &pvMemInfo,
1540 psPDumpPDDevPAddrIN->hKernelMemInfo, 2012 psPDumpPDDevPAddrIN->hKernelMemInfo,
1541 PVRSRV_HANDLE_TYPE_MEM_INFO); 2013 PVRSRV_HANDLE_TYPE_MEM_INFO);
1542 if(psRetOUT->eError != PVRSRV_OK) 2014 if(psRetOUT->eError != PVRSRV_OK)
1543 { 2015 {
1544 return 0; 2016 return 0;
1545 } 2017 }
1546 2018
1547 psRetOUT->eError = 2019 psRetOUT->eError =
1548 PDumpPDDevPAddrKM((PVRSRV_KERNEL_MEM_INFO *)pvMemInfo, 2020 PDumpPDDevPAddrKM((PVRSRV_KERNEL_MEM_INFO *)pvMemInfo,
1549 psPDumpPDDevPAddrIN->ui32Offset, 2021 psPDumpPDDevPAddrIN->ui32Offset,
1550 psPDumpPDDevPAddrIN->sPDDevPAddr, 2022 psPDumpPDDevPAddrIN->sPDDevPAddr,
1551 MAKEUNIQUETAG(pvMemInfo), 2023 MAKEUNIQUETAG(pvMemInfo),
1552 PDUMP_PD_UNIQUETAG); 2024 PDUMP_PD_UNIQUETAG);
1553 return 0; 2025 return 0;
1554} 2026}
1555 2027
1556static IMG_INT 2028static IMG_INT
1557PDumpStartInitPhaseBW(IMG_UINT32 ui32BridgeID, 2029PDumpStartInitPhaseBW(IMG_UINT32 ui32BridgeID,
1558 IMG_VOID *psBridgeIn, 2030 IMG_VOID *psBridgeIn,
1559 PVRSRV_BRIDGE_RETURN *psRetOUT, 2031 PVRSRV_BRIDGE_RETURN *psRetOUT,
1560 PVRSRV_PER_PROCESS_DATA *psPerProc) 2032 PVRSRV_PER_PROCESS_DATA *psPerProc)
1561{ 2033{
1562 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_STARTINITPHASE); 2034 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_STARTINITPHASE);
1563 PVR_UNREFERENCED_PARAMETER(psBridgeIn); 2035 PVR_UNREFERENCED_PARAMETER(psBridgeIn);
1564 PVR_UNREFERENCED_PARAMETER(psPerProc); 2036 PVR_UNREFERENCED_PARAMETER(psPerProc);
1565 2037
1566 psRetOUT->eError = PDumpStartInitPhaseKM(); 2038 psRetOUT->eError = PDumpStartInitPhaseKM();
1567 2039
1568 return 0; 2040 return 0;
1569} 2041}
1570 2042
1571static IMG_INT 2043static IMG_INT
1572PDumpStopInitPhaseBW(IMG_UINT32 ui32BridgeID, 2044PDumpStopInitPhaseBW(IMG_UINT32 ui32BridgeID,
1573 IMG_VOID *psBridgeIn, 2045 IMG_VOID *psBridgeIn,
1574 PVRSRV_BRIDGE_RETURN *psRetOUT, 2046 PVRSRV_BRIDGE_RETURN *psRetOUT,
1575 PVRSRV_PER_PROCESS_DATA *psPerProc) 2047 PVRSRV_PER_PROCESS_DATA *psPerProc)
1576{ 2048{
1577 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_STOPINITPHASE); 2049 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_PDUMP_STOPINITPHASE);
1578 PVR_UNREFERENCED_PARAMETER(psBridgeIn); 2050 PVR_UNREFERENCED_PARAMETER(psBridgeIn);
1579 PVR_UNREFERENCED_PARAMETER(psPerProc); 2051 PVR_UNREFERENCED_PARAMETER(psPerProc);
1580 2052
1581 psRetOUT->eError = PDumpStopInitPhaseKM(); 2053 psRetOUT->eError = PDumpStopInitPhaseKM();
1582 2054
1583 return 0; 2055 return 0;
1584} 2056}
1585 2057
1586#endif 2058#endif
@@ -1588,2307 +2060,2677 @@ PDumpStopInitPhaseBW(IMG_UINT32 ui32BridgeID,
1588 2060
1589static IMG_INT 2061static IMG_INT
1590PVRSRVGetMiscInfoBW(IMG_UINT32 ui32BridgeID, 2062PVRSRVGetMiscInfoBW(IMG_UINT32 ui32BridgeID,
1591 PVRSRV_BRIDGE_IN_GET_MISC_INFO *psGetMiscInfoIN, 2063 PVRSRV_BRIDGE_IN_GET_MISC_INFO *psGetMiscInfoIN,
1592 PVRSRV_BRIDGE_OUT_GET_MISC_INFO *psGetMiscInfoOUT, 2064 PVRSRV_BRIDGE_OUT_GET_MISC_INFO *psGetMiscInfoOUT,
1593 PVRSRV_PER_PROCESS_DATA *psPerProc) 2065 PVRSRV_PER_PROCESS_DATA *psPerProc)
1594{ 2066{
1595 PVRSRV_ERROR eError; 2067#if defined (SUPPORT_SID_INTERFACE)
2068 PVRSRV_MISC_INFO_KM sMiscInfo = {0};
2069#endif
2070 PVRSRV_ERROR eError;
2071
2072 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GET_MISC_INFO);
2073#if defined (SUPPORT_SID_INTERFACE)
2074 sMiscInfo.ui32StateRequest = psGetMiscInfoIN->sMiscInfo.ui32StateRequest;
2075 sMiscInfo.ui32StatePresent = psGetMiscInfoIN->sMiscInfo.ui32StatePresent;
2076 sMiscInfo.ui32MemoryStrLen = psGetMiscInfoIN->sMiscInfo.ui32MemoryStrLen;
2077 sMiscInfo.pszMemoryStr = psGetMiscInfoIN->sMiscInfo.pszMemoryStr;
2078
2079 OSMemCopy(&sMiscInfo.sCacheOpCtl,
2080 &psGetMiscInfoIN->sMiscInfo.sCacheOpCtl,
2081 sizeof(sMiscInfo.sCacheOpCtl));
2082#else
1596 2083
1597 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GET_MISC_INFO); 2084 OSMemCopy(&psGetMiscInfoOUT->sMiscInfo,
2085 &psGetMiscInfoIN->sMiscInfo,
2086 sizeof(PVRSRV_MISC_INFO));
2087#endif
1598 2088
1599 OSMemCopy(&psGetMiscInfoOUT->sMiscInfo, 2089 if (((psGetMiscInfoIN->sMiscInfo.ui32StateRequest & PVRSRV_MISC_INFO_MEMSTATS_PRESENT) != 0) &&
1600 &psGetMiscInfoIN->sMiscInfo, 2090 ((psGetMiscInfoIN->sMiscInfo.ui32StateRequest & PVRSRV_MISC_INFO_DDKVERSION_PRESENT) != 0) &&
1601 sizeof(PVRSRV_MISC_INFO)); 2091 ((psGetMiscInfoIN->sMiscInfo.ui32StateRequest & PVRSRV_MISC_INFO_FREEMEM_PRESENT) != 0))
2092 {
2093
2094 psGetMiscInfoOUT->eError = PVRSRV_ERROR_INVALID_PARAMS;
2095 return 0;
2096 }
2097
2098 if (((psGetMiscInfoIN->sMiscInfo.ui32StateRequest & PVRSRV_MISC_INFO_MEMSTATS_PRESENT) != 0) ||
2099 ((psGetMiscInfoIN->sMiscInfo.ui32StateRequest & PVRSRV_MISC_INFO_DDKVERSION_PRESENT) != 0) ||
2100 ((psGetMiscInfoIN->sMiscInfo.ui32StateRequest & PVRSRV_MISC_INFO_FREEMEM_PRESENT) != 0))
2101 {
2102
2103#if defined (SUPPORT_SID_INTERFACE)
2104 ASSIGN_AND_EXIT_ON_ERROR(psGetMiscInfoOUT->eError,
2105 OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
2106 psGetMiscInfoOUT->sMiscInfo.ui32MemoryStrLen,
2107 (IMG_VOID **)&sMiscInfo.pszMemoryStr, 0,
2108 "Output string buffer"));
2109 psGetMiscInfoOUT->eError = PVRSRVGetMiscInfoKM(&sMiscInfo);
2110
2111
2112 eError = CopyToUserWrapper(psPerProc, ui32BridgeID,
2113 psGetMiscInfoIN->sMiscInfo.pszMemoryStr,
2114 sMiscInfo.pszMemoryStr,
2115 sMiscInfo.ui32MemoryStrLen);
2116#else
2117 ASSIGN_AND_EXIT_ON_ERROR(psGetMiscInfoOUT->eError,
2118 OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
2119 psGetMiscInfoOUT->sMiscInfo.ui32MemoryStrLen,
2120 (IMG_VOID **)&psGetMiscInfoOUT->sMiscInfo.pszMemoryStr, 0,
2121 "Output string buffer"));
2122
2123 psGetMiscInfoOUT->eError = PVRSRVGetMiscInfoKM(&psGetMiscInfoOUT->sMiscInfo);
2124
2125
2126 eError = CopyToUserWrapper(psPerProc, ui32BridgeID,
2127 psGetMiscInfoIN->sMiscInfo.pszMemoryStr,
2128 psGetMiscInfoOUT->sMiscInfo.pszMemoryStr,
2129 psGetMiscInfoOUT->sMiscInfo.ui32MemoryStrLen);
2130#endif
1602 2131
1603 if (((psGetMiscInfoIN->sMiscInfo.ui32StateRequest & PVRSRV_MISC_INFO_MEMSTATS_PRESENT) != 0) && 2132
1604 ((psGetMiscInfoIN->sMiscInfo.ui32StateRequest & PVRSRV_MISC_INFO_DDKVERSION_PRESENT) != 0) && 2133#if defined (SUPPORT_SID_INTERFACE)
1605 ((psGetMiscInfoIN->sMiscInfo.ui32StateRequest & PVRSRV_MISC_INFO_FREEMEM_PRESENT) != 0)) 2134 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
1606 { 2135 sMiscInfo.ui32MemoryStrLen,
1607 2136 (IMG_VOID *)sMiscInfo.pszMemoryStr, 0);
1608 psGetMiscInfoOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; 2137#else
1609 return 0; 2138 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
1610 } 2139 psGetMiscInfoOUT->sMiscInfo.ui32MemoryStrLen,
2140 (IMG_VOID *)psGetMiscInfoOUT->sMiscInfo.pszMemoryStr, 0);
2141#endif
1611 2142
1612 if (((psGetMiscInfoIN->sMiscInfo.ui32StateRequest & PVRSRV_MISC_INFO_MEMSTATS_PRESENT) != 0) || 2143
1613 ((psGetMiscInfoIN->sMiscInfo.ui32StateRequest & PVRSRV_MISC_INFO_DDKVERSION_PRESENT) != 0) || 2144 psGetMiscInfoOUT->sMiscInfo.pszMemoryStr = psGetMiscInfoIN->sMiscInfo.pszMemoryStr;
1614 ((psGetMiscInfoIN->sMiscInfo.ui32StateRequest & PVRSRV_MISC_INFO_FREEMEM_PRESENT) != 0)) 2145
1615 { 2146 if(eError != PVRSRV_OK)
1616 2147 {
1617 ASSIGN_AND_EXIT_ON_ERROR(psGetMiscInfoOUT->eError, 2148
1618 OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, 2149 PVR_DPF((PVR_DBG_ERROR, "PVRSRVGetMiscInfoBW Error copy to user"));
1619 psGetMiscInfoOUT->sMiscInfo.ui32MemoryStrLen, 2150 return -EFAULT;
1620 (IMG_VOID **)&psGetMiscInfoOUT->sMiscInfo.pszMemoryStr, 0, 2151 }
1621 "Output string buffer")); 2152 }
1622 2153 else
1623 psGetMiscInfoOUT->eError = PVRSRVGetMiscInfoKM(&psGetMiscInfoOUT->sMiscInfo); 2154 {
1624 2155#if defined (SUPPORT_SID_INTERFACE)
1625 2156 psGetMiscInfoOUT->eError = PVRSRVGetMiscInfoKM(&sMiscInfo);
1626 eError = CopyToUserWrapper(psPerProc, ui32BridgeID, 2157#else
1627 psGetMiscInfoIN->sMiscInfo.pszMemoryStr, 2158 psGetMiscInfoOUT->eError = PVRSRVGetMiscInfoKM(&psGetMiscInfoOUT->sMiscInfo);
1628 psGetMiscInfoOUT->sMiscInfo.pszMemoryStr, 2159#endif
1629 psGetMiscInfoOUT->sMiscInfo.ui32MemoryStrLen); 2160 }
1630
1631
1632 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
1633 psGetMiscInfoOUT->sMiscInfo.ui32MemoryStrLen,
1634 (IMG_VOID *)psGetMiscInfoOUT->sMiscInfo.pszMemoryStr, 0);
1635 psGetMiscInfoOUT->sMiscInfo.pszMemoryStr = IMG_NULL;
1636
1637
1638 psGetMiscInfoOUT->sMiscInfo.pszMemoryStr = psGetMiscInfoIN->sMiscInfo.pszMemoryStr;
1639
1640 if(eError != PVRSRV_OK)
1641 {
1642
1643 PVR_DPF((PVR_DBG_ERROR, "PVRSRVGetMiscInfoBW Error copy to user"));
1644 return -EFAULT;
1645 }
1646 }
1647 else
1648 {
1649 psGetMiscInfoOUT->eError = PVRSRVGetMiscInfoKM(&psGetMiscInfoOUT->sMiscInfo);
1650 }
1651 2161
1652 2162
1653 if (psGetMiscInfoOUT->eError != PVRSRV_OK) 2163 if (psGetMiscInfoOUT->eError != PVRSRV_OK)
1654 { 2164 {
1655 return 0; 2165 return 0;
1656 } 2166 }
1657 2167
1658 2168
1659 if (psGetMiscInfoIN->sMiscInfo.ui32StateRequest & PVRSRV_MISC_INFO_GLOBALEVENTOBJECT_PRESENT) 2169#if defined (SUPPORT_SID_INTERFACE)
1660 { 2170 if (sMiscInfo.ui32StateRequest & PVRSRV_MISC_INFO_GLOBALEVENTOBJECT_PRESENT)
1661 psGetMiscInfoOUT->eError = PVRSRVAllocHandle(psPerProc->psHandleBase, 2171#else
1662 &psGetMiscInfoOUT->sMiscInfo.sGlobalEventObject.hOSEventKM, 2172 if (psGetMiscInfoIN->sMiscInfo.ui32StateRequest & PVRSRV_MISC_INFO_GLOBALEVENTOBJECT_PRESENT)
1663 psGetMiscInfoOUT->sMiscInfo.sGlobalEventObject.hOSEventKM, 2173#endif
1664 PVRSRV_HANDLE_TYPE_SHARED_EVENT_OBJECT, 2174 {
1665 PVRSRV_HANDLE_ALLOC_FLAG_SHARED); 2175 psGetMiscInfoOUT->eError = PVRSRVAllocHandle(psPerProc->psHandleBase,
1666 2176 &psGetMiscInfoOUT->sMiscInfo.sGlobalEventObject.hOSEventKM,
1667 if (psGetMiscInfoOUT->eError != PVRSRV_OK) 2177#if defined (SUPPORT_SID_INTERFACE)
1668 { 2178 sMiscInfo.sGlobalEventObject.hOSEventKM,
1669 return 0; 2179#else
1670 } 2180 psGetMiscInfoOUT->sMiscInfo.sGlobalEventObject.hOSEventKM,
1671 } 2181#endif
2182 PVRSRV_HANDLE_TYPE_SHARED_EVENT_OBJECT,
2183 PVRSRV_HANDLE_ALLOC_FLAG_SHARED);
1672 2184
1673 if (psGetMiscInfoOUT->sMiscInfo.hSOCTimerRegisterOSMemHandle) 2185 if (psGetMiscInfoOUT->eError != PVRSRV_OK)
1674 { 2186 {
1675 2187 return 0;
1676 psGetMiscInfoOUT->eError = PVRSRVAllocHandle(psPerProc->psHandleBase, 2188 }
1677 &psGetMiscInfoOUT->sMiscInfo.hSOCTimerRegisterOSMemHandle, 2189
1678 psGetMiscInfoOUT->sMiscInfo.hSOCTimerRegisterOSMemHandle, 2190#if defined (SUPPORT_SID_INTERFACE)
1679 PVRSRV_HANDLE_TYPE_SOC_TIMER, 2191 OSMemCopy(&psGetMiscInfoOUT->sMiscInfo.sGlobalEventObject.szName,
1680 PVRSRV_HANDLE_ALLOC_FLAG_SHARED); 2192 sMiscInfo.sGlobalEventObject.szName,
1681 2193 EVENTOBJNAME_MAXLENGTH);
1682 if (psGetMiscInfoOUT->eError != PVRSRV_OK) 2194
1683 { 2195#endif
1684 return 0; 2196 }
1685 }
1686 }
1687 2197
1688 return 0; 2198#if defined (SUPPORT_SID_INTERFACE)
2199 if (sMiscInfo.hSOCTimerRegisterOSMemHandle)
2200#else
2201 if (psGetMiscInfoOUT->sMiscInfo.hSOCTimerRegisterOSMemHandle)
2202#endif
2203 {
2204
2205 psGetMiscInfoOUT->eError = PVRSRVAllocHandle(psPerProc->psHandleBase,
2206 &psGetMiscInfoOUT->sMiscInfo.hSOCTimerRegisterOSMemHandle,
2207#if defined (SUPPORT_SID_INTERFACE)
2208 sMiscInfo.hSOCTimerRegisterOSMemHandle,
2209#else
2210 psGetMiscInfoOUT->sMiscInfo.hSOCTimerRegisterOSMemHandle,
2211#endif
2212 PVRSRV_HANDLE_TYPE_SOC_TIMER,
2213 PVRSRV_HANDLE_ALLOC_FLAG_SHARED);
2214
2215 if (psGetMiscInfoOUT->eError != PVRSRV_OK)
2216 {
2217 return 0;
2218 }
2219 }
2220#if defined (SUPPORT_SID_INTERFACE)
2221 else
2222 {
2223 psGetMiscInfoOUT->sMiscInfo.hSOCTimerRegisterOSMemHandle = 0;
2224 }
2225
2226
2227 psGetMiscInfoOUT->sMiscInfo.ui32StateRequest = sMiscInfo.ui32StateRequest;
2228 psGetMiscInfoOUT->sMiscInfo.ui32StatePresent = sMiscInfo.ui32StatePresent;
2229
2230 psGetMiscInfoOUT->sMiscInfo.pvSOCTimerRegisterKM = sMiscInfo.pvSOCTimerRegisterKM;
2231 psGetMiscInfoOUT->sMiscInfo.pvSOCTimerRegisterUM = sMiscInfo.pvSOCTimerRegisterUM;
2232 psGetMiscInfoOUT->sMiscInfo.pvSOCClockGateRegs = sMiscInfo.pvSOCClockGateRegs;
2233
2234 psGetMiscInfoOUT->sMiscInfo.ui32SOCClockGateRegsSize = sMiscInfo.ui32SOCClockGateRegsSize;
2235
2236 OSMemCopy(&psGetMiscInfoOUT->sMiscInfo.aui32DDKVersion,
2237 &sMiscInfo.aui32DDKVersion,
2238 sizeof(psGetMiscInfoOUT->sMiscInfo.aui32DDKVersion));
2239 OSMemCopy(&psGetMiscInfoOUT->sMiscInfo.sCacheOpCtl,
2240 &sMiscInfo.sCacheOpCtl,
2241 sizeof(psGetMiscInfoOUT->sMiscInfo.sCacheOpCtl));
2242#endif
2243
2244 return 0;
1689} 2245}
1690 2246
1691static IMG_INT 2247static IMG_INT
1692PVRSRVConnectBW(IMG_UINT32 ui32BridgeID, 2248PVRSRVConnectBW(IMG_UINT32 ui32BridgeID,
1693 PVRSRV_BRIDGE_IN_CONNECT_SERVICES *psConnectServicesIN, 2249 PVRSRV_BRIDGE_IN_CONNECT_SERVICES *psConnectServicesIN,
1694 PVRSRV_BRIDGE_OUT_CONNECT_SERVICES *psConnectServicesOUT, 2250 PVRSRV_BRIDGE_OUT_CONNECT_SERVICES *psConnectServicesOUT,
1695 PVRSRV_PER_PROCESS_DATA *psPerProc) 2251 PVRSRV_PER_PROCESS_DATA *psPerProc)
1696{ 2252{
1697 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_CONNECT_SERVICES); 2253 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_CONNECT_SERVICES);
1698 2254
1699#if defined(PDUMP) 2255#if defined(PDUMP)
1700 2256
1701 psPerProc->bPDumpPersistent |= ( (psConnectServicesIN->ui32Flags & SRV_FLAGS_PERSIST) != 0) ? IMG_TRUE : IMG_FALSE; 2257 if ((psConnectServicesIN->ui32Flags & SRV_FLAGS_PERSIST) != 0)
2258 {
2259 psPerProc->bPDumpPersistent = IMG_TRUE;
2260 }
1702 2261
1703#if defined(SUPPORT_PDUMP_MULTI_PROCESS) 2262#if defined(SUPPORT_PDUMP_MULTI_PROCESS)
1704 2263
1705 psPerProc->bPDumpActive |= ( (psConnectServicesIN->ui32Flags & SRV_FLAGS_PDUMP_ACTIVE) != 0) ? IMG_TRUE : IMG_FALSE; 2264 if ((psConnectServicesIN->ui32Flags & SRV_FLAGS_PDUMP_ACTIVE) != 0)
1706#endif 2265 {
2266 psPerProc->bPDumpActive = IMG_TRUE;
2267 }
2268#endif
1707#else 2269#else
1708 PVR_UNREFERENCED_PARAMETER(psConnectServicesIN); 2270 PVR_UNREFERENCED_PARAMETER(psConnectServicesIN);
1709#endif 2271#endif
1710 psConnectServicesOUT->hKernelServices = psPerProc->hPerProcData; 2272 psConnectServicesOUT->hKernelServices = psPerProc->hPerProcData;
1711 psConnectServicesOUT->eError = PVRSRV_OK; 2273 psConnectServicesOUT->eError = PVRSRV_OK;
1712 2274
1713 return 0; 2275 return 0;
1714} 2276}
1715 2277
1716static IMG_INT 2278static IMG_INT
1717PVRSRVDisconnectBW(IMG_UINT32 ui32BridgeID, 2279PVRSRVDisconnectBW(IMG_UINT32 ui32BridgeID,
1718 IMG_VOID *psBridgeIn, 2280 IMG_VOID *psBridgeIn,
1719 PVRSRV_BRIDGE_RETURN *psRetOUT, 2281 PVRSRV_BRIDGE_RETURN *psRetOUT,
1720 PVRSRV_PER_PROCESS_DATA *psPerProc) 2282 PVRSRV_PER_PROCESS_DATA *psPerProc)
1721{ 2283{
1722 PVR_UNREFERENCED_PARAMETER(psPerProc); 2284 PVR_UNREFERENCED_PARAMETER(psPerProc);
1723 PVR_UNREFERENCED_PARAMETER(psBridgeIn); 2285 PVR_UNREFERENCED_PARAMETER(psBridgeIn);
1724
1725 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_DISCONNECT_SERVICES);
1726 2286
2287 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_DISCONNECT_SERVICES);
1727 2288
1728 psRetOUT->eError = PVRSRV_OK; 2289
2290 psRetOUT->eError = PVRSRV_OK;
1729 2291
1730 return 0; 2292 return 0;
1731} 2293}
1732 2294
1733static IMG_INT 2295static IMG_INT
1734PVRSRVEnumerateDCBW(IMG_UINT32 ui32BridgeID, 2296PVRSRVEnumerateDCBW(IMG_UINT32 ui32BridgeID,
1735 PVRSRV_BRIDGE_IN_ENUMCLASS *psEnumDispClassIN, 2297 PVRSRV_BRIDGE_IN_ENUMCLASS *psEnumDispClassIN,
1736 PVRSRV_BRIDGE_OUT_ENUMCLASS *psEnumDispClassOUT, 2298 PVRSRV_BRIDGE_OUT_ENUMCLASS *psEnumDispClassOUT,
1737 PVRSRV_PER_PROCESS_DATA *psPerProc) 2299 PVRSRV_PER_PROCESS_DATA *psPerProc)
1738{ 2300{
1739 PVR_UNREFERENCED_PARAMETER(psPerProc); 2301 PVR_UNREFERENCED_PARAMETER(psPerProc);
1740 2302
1741 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ENUM_CLASS); 2303 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ENUM_CLASS);
1742 2304
1743 psEnumDispClassOUT->eError = 2305 psEnumDispClassOUT->eError =
1744 PVRSRVEnumerateDCKM(psEnumDispClassIN->sDeviceClass, 2306 PVRSRVEnumerateDCKM(psEnumDispClassIN->sDeviceClass,
1745 &psEnumDispClassOUT->ui32NumDevices, 2307 &psEnumDispClassOUT->ui32NumDevices,
1746 &psEnumDispClassOUT->ui32DevID[0]); 2308 &psEnumDispClassOUT->ui32DevID[0]);
1747 2309
1748 return 0; 2310 return 0;
1749} 2311}
1750 2312
1751static IMG_INT 2313static IMG_INT
1752PVRSRVOpenDCDeviceBW(IMG_UINT32 ui32BridgeID, 2314PVRSRVOpenDCDeviceBW(IMG_UINT32 ui32BridgeID,
1753 PVRSRV_BRIDGE_IN_OPEN_DISPCLASS_DEVICE *psOpenDispClassDeviceIN, 2315 PVRSRV_BRIDGE_IN_OPEN_DISPCLASS_DEVICE *psOpenDispClassDeviceIN,
1754 PVRSRV_BRIDGE_OUT_OPEN_DISPCLASS_DEVICE *psOpenDispClassDeviceOUT, 2316 PVRSRV_BRIDGE_OUT_OPEN_DISPCLASS_DEVICE *psOpenDispClassDeviceOUT,
1755 PVRSRV_PER_PROCESS_DATA *psPerProc) 2317 PVRSRV_PER_PROCESS_DATA *psPerProc)
1756{ 2318{
1757 IMG_HANDLE hDevCookieInt; 2319 IMG_HANDLE hDevCookieInt;
1758 IMG_HANDLE hDispClassInfoInt; 2320 IMG_HANDLE hDispClassInfoInt;
1759 2321
1760 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_OPEN_DISPCLASS_DEVICE); 2322 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_OPEN_DISPCLASS_DEVICE);
1761 2323
1762 NEW_HANDLE_BATCH_OR_ERROR(psOpenDispClassDeviceOUT->eError, psPerProc, 1) 2324 NEW_HANDLE_BATCH_OR_ERROR(psOpenDispClassDeviceOUT->eError, psPerProc, 1)
1763 2325
1764 psOpenDispClassDeviceOUT->eError = 2326 psOpenDispClassDeviceOUT->eError =
1765 PVRSRVLookupHandle(psPerProc->psHandleBase, 2327 PVRSRVLookupHandle(psPerProc->psHandleBase,
1766 &hDevCookieInt, 2328 &hDevCookieInt,
1767 psOpenDispClassDeviceIN->hDevCookie, 2329 psOpenDispClassDeviceIN->hDevCookie,
1768 PVRSRV_HANDLE_TYPE_DEV_NODE); 2330 PVRSRV_HANDLE_TYPE_DEV_NODE);
1769 if(psOpenDispClassDeviceOUT->eError != PVRSRV_OK) 2331 if(psOpenDispClassDeviceOUT->eError != PVRSRV_OK)
1770 { 2332 {
1771 return 0; 2333 return 0;
1772 } 2334 }
1773 2335
1774 psOpenDispClassDeviceOUT->eError = 2336 psOpenDispClassDeviceOUT->eError =
1775 PVRSRVOpenDCDeviceKM(psPerProc, 2337 PVRSRVOpenDCDeviceKM(psPerProc,
1776 psOpenDispClassDeviceIN->ui32DeviceID, 2338 psOpenDispClassDeviceIN->ui32DeviceID,
1777 hDevCookieInt, 2339 hDevCookieInt,
1778 &hDispClassInfoInt); 2340 &hDispClassInfoInt);
1779 2341
1780 if(psOpenDispClassDeviceOUT->eError != PVRSRV_OK) 2342 if(psOpenDispClassDeviceOUT->eError != PVRSRV_OK)
1781 { 2343 {
1782 return 0; 2344 return 0;
1783 } 2345 }
1784 2346
1785 PVRSRVAllocHandleNR(psPerProc->psHandleBase, 2347 PVRSRVAllocHandleNR(psPerProc->psHandleBase,
1786 &psOpenDispClassDeviceOUT->hDeviceKM, 2348 &psOpenDispClassDeviceOUT->hDeviceKM,
1787 hDispClassInfoInt, 2349 hDispClassInfoInt,
1788 PVRSRV_HANDLE_TYPE_DISP_INFO, 2350 PVRSRV_HANDLE_TYPE_DISP_INFO,
1789 PVRSRV_HANDLE_ALLOC_FLAG_NONE); 2351 PVRSRV_HANDLE_ALLOC_FLAG_NONE);
1790 COMMIT_HANDLE_BATCH_OR_ERROR(psOpenDispClassDeviceOUT->eError, psPerProc) 2352 COMMIT_HANDLE_BATCH_OR_ERROR(psOpenDispClassDeviceOUT->eError, psPerProc)
1791 2353
1792 return 0; 2354 return 0;
1793} 2355}
1794 2356
1795static IMG_INT 2357static IMG_INT
1796PVRSRVCloseDCDeviceBW(IMG_UINT32 ui32BridgeID, 2358PVRSRVCloseDCDeviceBW(IMG_UINT32 ui32BridgeID,
1797 PVRSRV_BRIDGE_IN_CLOSE_DISPCLASS_DEVICE *psCloseDispClassDeviceIN, 2359 PVRSRV_BRIDGE_IN_CLOSE_DISPCLASS_DEVICE *psCloseDispClassDeviceIN,
1798 PVRSRV_BRIDGE_RETURN *psRetOUT, 2360 PVRSRV_BRIDGE_RETURN *psRetOUT,
1799 PVRSRV_PER_PROCESS_DATA *psPerProc) 2361 PVRSRV_PER_PROCESS_DATA *psPerProc)
1800{ 2362{
1801 IMG_VOID *pvDispClassInfoInt; 2363 IMG_VOID *pvDispClassInfoInt;
1802 2364
1803 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_CLOSE_DISPCLASS_DEVICE); 2365 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_CLOSE_DISPCLASS_DEVICE);
1804 2366
1805 psRetOUT->eError = 2367 psRetOUT->eError =
1806 PVRSRVLookupHandle(psPerProc->psHandleBase, 2368 PVRSRVLookupHandle(psPerProc->psHandleBase,
1807 &pvDispClassInfoInt, 2369 &pvDispClassInfoInt,
1808 psCloseDispClassDeviceIN->hDeviceKM, 2370 psCloseDispClassDeviceIN->hDeviceKM,
1809 PVRSRV_HANDLE_TYPE_DISP_INFO); 2371 PVRSRV_HANDLE_TYPE_DISP_INFO);
1810 2372
1811 if(psRetOUT->eError != PVRSRV_OK) 2373 if(psRetOUT->eError != PVRSRV_OK)
1812 { 2374 {
1813 return 0; 2375 return 0;
1814 } 2376 }
1815 2377
1816 psRetOUT->eError = PVRSRVCloseDCDeviceKM(pvDispClassInfoInt, IMG_FALSE); 2378 psRetOUT->eError = PVRSRVCloseDCDeviceKM(pvDispClassInfoInt, IMG_FALSE);
1817 if(psRetOUT->eError != PVRSRV_OK) 2379 if(psRetOUT->eError != PVRSRV_OK)
1818 { 2380 {
1819 return 0; 2381 return 0;
1820 } 2382 }
1821 2383
1822 psRetOUT->eError = 2384 psRetOUT->eError =
1823 PVRSRVReleaseHandle(psPerProc->psHandleBase, 2385 PVRSRVReleaseHandle(psPerProc->psHandleBase,
1824 psCloseDispClassDeviceIN->hDeviceKM, 2386 psCloseDispClassDeviceIN->hDeviceKM,
1825 PVRSRV_HANDLE_TYPE_DISP_INFO); 2387 PVRSRV_HANDLE_TYPE_DISP_INFO);
1826 return 0; 2388 return 0;
1827} 2389}
1828 2390
1829static IMG_INT 2391static IMG_INT
1830PVRSRVEnumDCFormatsBW(IMG_UINT32 ui32BridgeID, 2392PVRSRVEnumDCFormatsBW(IMG_UINT32 ui32BridgeID,
1831 PVRSRV_BRIDGE_IN_ENUM_DISPCLASS_FORMATS *psEnumDispClassFormatsIN, 2393 PVRSRV_BRIDGE_IN_ENUM_DISPCLASS_FORMATS *psEnumDispClassFormatsIN,
1832 PVRSRV_BRIDGE_OUT_ENUM_DISPCLASS_FORMATS *psEnumDispClassFormatsOUT, 2394 PVRSRV_BRIDGE_OUT_ENUM_DISPCLASS_FORMATS *psEnumDispClassFormatsOUT,
1833 PVRSRV_PER_PROCESS_DATA *psPerProc) 2395 PVRSRV_PER_PROCESS_DATA *psPerProc)
1834{ 2396{
1835 IMG_VOID *pvDispClassInfoInt; 2397 IMG_VOID *pvDispClassInfoInt;
1836 2398
1837 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ENUM_DISPCLASS_FORMATS); 2399 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ENUM_DISPCLASS_FORMATS);
1838 2400
1839 psEnumDispClassFormatsOUT->eError = 2401 psEnumDispClassFormatsOUT->eError =
1840 PVRSRVLookupHandle(psPerProc->psHandleBase, 2402 PVRSRVLookupHandle(psPerProc->psHandleBase,
1841 &pvDispClassInfoInt, 2403 &pvDispClassInfoInt,
1842 psEnumDispClassFormatsIN->hDeviceKM, 2404 psEnumDispClassFormatsIN->hDeviceKM,
1843 PVRSRV_HANDLE_TYPE_DISP_INFO); 2405 PVRSRV_HANDLE_TYPE_DISP_INFO);
1844 if(psEnumDispClassFormatsOUT->eError != PVRSRV_OK) 2406 if(psEnumDispClassFormatsOUT->eError != PVRSRV_OK)
1845 { 2407 {
1846 return 0; 2408 return 0;
1847 } 2409 }
1848 2410
1849 psEnumDispClassFormatsOUT->eError = 2411 psEnumDispClassFormatsOUT->eError =
1850 PVRSRVEnumDCFormatsKM(pvDispClassInfoInt, 2412 PVRSRVEnumDCFormatsKM(pvDispClassInfoInt,
1851 &psEnumDispClassFormatsOUT->ui32Count, 2413 &psEnumDispClassFormatsOUT->ui32Count,
1852 psEnumDispClassFormatsOUT->asFormat); 2414 psEnumDispClassFormatsOUT->asFormat);
1853 2415
1854 return 0; 2416 return 0;
1855} 2417}
1856 2418
1857static IMG_INT 2419static IMG_INT
1858PVRSRVEnumDCDimsBW(IMG_UINT32 ui32BridgeID, 2420PVRSRVEnumDCDimsBW(IMG_UINT32 ui32BridgeID,
1859 PVRSRV_BRIDGE_IN_ENUM_DISPCLASS_DIMS *psEnumDispClassDimsIN, 2421 PVRSRV_BRIDGE_IN_ENUM_DISPCLASS_DIMS *psEnumDispClassDimsIN,
1860 PVRSRV_BRIDGE_OUT_ENUM_DISPCLASS_DIMS *psEnumDispClassDimsOUT, 2422 PVRSRV_BRIDGE_OUT_ENUM_DISPCLASS_DIMS *psEnumDispClassDimsOUT,
1861 PVRSRV_PER_PROCESS_DATA *psPerProc) 2423 PVRSRV_PER_PROCESS_DATA *psPerProc)
1862{ 2424{
1863 IMG_VOID *pvDispClassInfoInt; 2425 IMG_VOID *pvDispClassInfoInt;
1864 2426
1865 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ENUM_DISPCLASS_DIMS); 2427 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ENUM_DISPCLASS_DIMS);
1866 2428
1867 psEnumDispClassDimsOUT->eError = 2429 psEnumDispClassDimsOUT->eError =
1868 PVRSRVLookupHandle(psPerProc->psHandleBase, 2430 PVRSRVLookupHandle(psPerProc->psHandleBase,
1869 &pvDispClassInfoInt, 2431 &pvDispClassInfoInt,
1870 psEnumDispClassDimsIN->hDeviceKM, 2432 psEnumDispClassDimsIN->hDeviceKM,
1871 PVRSRV_HANDLE_TYPE_DISP_INFO); 2433 PVRSRV_HANDLE_TYPE_DISP_INFO);
1872 2434
1873 if(psEnumDispClassDimsOUT->eError != PVRSRV_OK) 2435 if(psEnumDispClassDimsOUT->eError != PVRSRV_OK)
1874 { 2436 {
1875 return 0; 2437 return 0;
1876 } 2438 }
1877 2439
1878 psEnumDispClassDimsOUT->eError = 2440 psEnumDispClassDimsOUT->eError =
1879 PVRSRVEnumDCDimsKM(pvDispClassInfoInt, 2441 PVRSRVEnumDCDimsKM(pvDispClassInfoInt,
1880 &psEnumDispClassDimsIN->sFormat, 2442 &psEnumDispClassDimsIN->sFormat,
1881 &psEnumDispClassDimsOUT->ui32Count, 2443 &psEnumDispClassDimsOUT->ui32Count,
1882 psEnumDispClassDimsOUT->asDim); 2444 psEnumDispClassDimsOUT->asDim);
1883 2445
1884 return 0; 2446 return 0;
1885} 2447}
1886 2448
1887static IMG_INT 2449static IMG_INT
1888PVRSRVGetDCSystemBufferBW(IMG_UINT32 ui32BridgeID, 2450PVRSRVGetDCSystemBufferBW(IMG_UINT32 ui32BridgeID,
1889 PVRSRV_BRIDGE_IN_GET_DISPCLASS_SYSBUFFER *psGetDispClassSysBufferIN, 2451 PVRSRV_BRIDGE_IN_GET_DISPCLASS_SYSBUFFER *psGetDispClassSysBufferIN,
1890 PVRSRV_BRIDGE_OUT_GET_DISPCLASS_SYSBUFFER *psGetDispClassSysBufferOUT, 2452 PVRSRV_BRIDGE_OUT_GET_DISPCLASS_SYSBUFFER *psGetDispClassSysBufferOUT,
1891 PVRSRV_PER_PROCESS_DATA *psPerProc) 2453 PVRSRV_PER_PROCESS_DATA *psPerProc)
1892{ 2454{
1893 IMG_HANDLE hBufferInt; 2455 IMG_HANDLE hBufferInt;
1894 IMG_VOID *pvDispClassInfoInt; 2456 IMG_VOID *pvDispClassInfoInt;
1895 2457
1896 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GET_DISPCLASS_SYSBUFFER); 2458 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GET_DISPCLASS_SYSBUFFER);
1897 2459
1898 NEW_HANDLE_BATCH_OR_ERROR(psGetDispClassSysBufferOUT->eError, psPerProc, 1) 2460 NEW_HANDLE_BATCH_OR_ERROR(psGetDispClassSysBufferOUT->eError, psPerProc, 1)
1899 2461
1900 psGetDispClassSysBufferOUT->eError = 2462 psGetDispClassSysBufferOUT->eError =
1901 PVRSRVLookupHandle(psPerProc->psHandleBase, 2463 PVRSRVLookupHandle(psPerProc->psHandleBase,
1902 &pvDispClassInfoInt, 2464 &pvDispClassInfoInt,
1903 psGetDispClassSysBufferIN->hDeviceKM, 2465 psGetDispClassSysBufferIN->hDeviceKM,
1904 PVRSRV_HANDLE_TYPE_DISP_INFO); 2466 PVRSRV_HANDLE_TYPE_DISP_INFO);
1905 if(psGetDispClassSysBufferOUT->eError != PVRSRV_OK) 2467 if(psGetDispClassSysBufferOUT->eError != PVRSRV_OK)
1906 { 2468 {
1907 return 0; 2469 return 0;
1908 } 2470 }
1909 2471
1910 psGetDispClassSysBufferOUT->eError = 2472 psGetDispClassSysBufferOUT->eError =
1911 PVRSRVGetDCSystemBufferKM(pvDispClassInfoInt, 2473 PVRSRVGetDCSystemBufferKM(pvDispClassInfoInt,
1912 &hBufferInt); 2474 &hBufferInt);
1913 2475
1914 if(psGetDispClassSysBufferOUT->eError != PVRSRV_OK) 2476 if(psGetDispClassSysBufferOUT->eError != PVRSRV_OK)
1915 { 2477 {
1916 return 0; 2478 return 0;
1917 } 2479 }
1918 2480
1919 2481
1920 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase, 2482 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
1921 &psGetDispClassSysBufferOUT->hBuffer, 2483 &psGetDispClassSysBufferOUT->hBuffer,
1922 hBufferInt, 2484 hBufferInt,
1923 PVRSRV_HANDLE_TYPE_DISP_BUFFER, 2485 PVRSRV_HANDLE_TYPE_DISP_BUFFER,
1924 (PVRSRV_HANDLE_ALLOC_FLAG)(PVRSRV_HANDLE_ALLOC_FLAG_PRIVATE | PVRSRV_HANDLE_ALLOC_FLAG_SHARED), 2486 (PVRSRV_HANDLE_ALLOC_FLAG)(PVRSRV_HANDLE_ALLOC_FLAG_PRIVATE | PVRSRV_HANDLE_ALLOC_FLAG_SHARED),
1925 psGetDispClassSysBufferIN->hDeviceKM); 2487 psGetDispClassSysBufferIN->hDeviceKM);
1926 2488
1927 COMMIT_HANDLE_BATCH_OR_ERROR(psGetDispClassSysBufferOUT->eError, psPerProc) 2489 COMMIT_HANDLE_BATCH_OR_ERROR(psGetDispClassSysBufferOUT->eError, psPerProc)
1928 2490
1929 return 0; 2491 return 0;
1930} 2492}
1931 2493
1932static IMG_INT 2494static IMG_INT
1933PVRSRVGetDCInfoBW(IMG_UINT32 ui32BridgeID, 2495PVRSRVGetDCInfoBW(IMG_UINT32 ui32BridgeID,
1934 PVRSRV_BRIDGE_IN_GET_DISPCLASS_INFO *psGetDispClassInfoIN, 2496 PVRSRV_BRIDGE_IN_GET_DISPCLASS_INFO *psGetDispClassInfoIN,
1935 PVRSRV_BRIDGE_OUT_GET_DISPCLASS_INFO *psGetDispClassInfoOUT, 2497 PVRSRV_BRIDGE_OUT_GET_DISPCLASS_INFO *psGetDispClassInfoOUT,
1936 PVRSRV_PER_PROCESS_DATA *psPerProc) 2498 PVRSRV_PER_PROCESS_DATA *psPerProc)
1937{ 2499{
1938 IMG_VOID *pvDispClassInfo; 2500 IMG_VOID *pvDispClassInfo;
1939 2501
1940 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GET_DISPCLASS_INFO); 2502 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GET_DISPCLASS_INFO);
1941 2503
1942 psGetDispClassInfoOUT->eError = 2504 psGetDispClassInfoOUT->eError =
1943 PVRSRVLookupHandle(psPerProc->psHandleBase, 2505 PVRSRVLookupHandle(psPerProc->psHandleBase,
1944 &pvDispClassInfo, 2506 &pvDispClassInfo,
1945 psGetDispClassInfoIN->hDeviceKM, 2507 psGetDispClassInfoIN->hDeviceKM,
1946 PVRSRV_HANDLE_TYPE_DISP_INFO); 2508 PVRSRV_HANDLE_TYPE_DISP_INFO);
1947 if(psGetDispClassInfoOUT->eError != PVRSRV_OK) 2509 if(psGetDispClassInfoOUT->eError != PVRSRV_OK)
1948 { 2510 {
1949 return 0; 2511 return 0;
1950 } 2512 }
1951 2513
1952 psGetDispClassInfoOUT->eError = 2514 psGetDispClassInfoOUT->eError =
1953 PVRSRVGetDCInfoKM(pvDispClassInfo, 2515 PVRSRVGetDCInfoKM(pvDispClassInfo,
1954 &psGetDispClassInfoOUT->sDisplayInfo); 2516 &psGetDispClassInfoOUT->sDisplayInfo);
1955 2517
1956 return 0; 2518 return 0;
1957} 2519}
1958 2520
1959static IMG_INT 2521static IMG_INT
1960PVRSRVCreateDCSwapChainBW(IMG_UINT32 ui32BridgeID, 2522PVRSRVCreateDCSwapChainBW(IMG_UINT32 ui32BridgeID,
1961 PVRSRV_BRIDGE_IN_CREATE_DISPCLASS_SWAPCHAIN *psCreateDispClassSwapChainIN, 2523 PVRSRV_BRIDGE_IN_CREATE_DISPCLASS_SWAPCHAIN *psCreateDispClassSwapChainIN,
1962 PVRSRV_BRIDGE_OUT_CREATE_DISPCLASS_SWAPCHAIN *psCreateDispClassSwapChainOUT, 2524 PVRSRV_BRIDGE_OUT_CREATE_DISPCLASS_SWAPCHAIN *psCreateDispClassSwapChainOUT,
1963 PVRSRV_PER_PROCESS_DATA *psPerProc) 2525 PVRSRV_PER_PROCESS_DATA *psPerProc)
1964{ 2526{
1965 IMG_VOID *pvDispClassInfo; 2527 IMG_VOID *pvDispClassInfo;
1966 IMG_HANDLE hSwapChainInt; 2528 IMG_HANDLE hSwapChainInt;
1967 IMG_UINT32 ui32SwapChainID; 2529 IMG_UINT32 ui32SwapChainID;
1968 2530
1969 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_CREATE_DISPCLASS_SWAPCHAIN); 2531 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_CREATE_DISPCLASS_SWAPCHAIN);
1970 2532
1971 NEW_HANDLE_BATCH_OR_ERROR(psCreateDispClassSwapChainOUT->eError, psPerProc, 1) 2533 NEW_HANDLE_BATCH_OR_ERROR(psCreateDispClassSwapChainOUT->eError, psPerProc, 1)
1972 2534
1973 psCreateDispClassSwapChainOUT->eError = 2535 psCreateDispClassSwapChainOUT->eError =
1974 PVRSRVLookupHandle(psPerProc->psHandleBase, 2536 PVRSRVLookupHandle(psPerProc->psHandleBase,
1975 &pvDispClassInfo, 2537 &pvDispClassInfo,
1976 psCreateDispClassSwapChainIN->hDeviceKM, 2538 psCreateDispClassSwapChainIN->hDeviceKM,
1977 PVRSRV_HANDLE_TYPE_DISP_INFO); 2539 PVRSRV_HANDLE_TYPE_DISP_INFO);
1978 2540
1979 if(psCreateDispClassSwapChainOUT->eError != PVRSRV_OK) 2541 if(psCreateDispClassSwapChainOUT->eError != PVRSRV_OK)
1980 { 2542 {
1981 return 0; 2543 return 0;
1982 } 2544 }
1983 2545
1984 2546
1985 ui32SwapChainID = psCreateDispClassSwapChainIN->ui32SwapChainID; 2547 ui32SwapChainID = psCreateDispClassSwapChainIN->ui32SwapChainID;
1986 2548
1987 psCreateDispClassSwapChainOUT->eError = 2549 psCreateDispClassSwapChainOUT->eError =
1988 PVRSRVCreateDCSwapChainKM(psPerProc, pvDispClassInfo, 2550 PVRSRVCreateDCSwapChainKM(psPerProc, pvDispClassInfo,
1989 psCreateDispClassSwapChainIN->ui32Flags, 2551 psCreateDispClassSwapChainIN->ui32Flags,
1990 &psCreateDispClassSwapChainIN->sDstSurfAttrib, 2552 &psCreateDispClassSwapChainIN->sDstSurfAttrib,
1991 &psCreateDispClassSwapChainIN->sSrcSurfAttrib, 2553 &psCreateDispClassSwapChainIN->sSrcSurfAttrib,
1992 psCreateDispClassSwapChainIN->ui32BufferCount, 2554 psCreateDispClassSwapChainIN->ui32BufferCount,
1993 psCreateDispClassSwapChainIN->ui32OEMFlags, 2555 psCreateDispClassSwapChainIN->ui32OEMFlags,
1994 &hSwapChainInt, 2556 &hSwapChainInt,
1995 &ui32SwapChainID); 2557 &ui32SwapChainID);
1996 2558
1997 if(psCreateDispClassSwapChainOUT->eError != PVRSRV_OK) 2559 if(psCreateDispClassSwapChainOUT->eError != PVRSRV_OK)
1998 { 2560 {
1999 return 0; 2561 return 0;
2000 } 2562 }
2001 2563
2002 2564
2003 psCreateDispClassSwapChainOUT->ui32SwapChainID = ui32SwapChainID; 2565 psCreateDispClassSwapChainOUT->ui32SwapChainID = ui32SwapChainID;
2004 2566
2005 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase, 2567 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
2006 &psCreateDispClassSwapChainOUT->hSwapChain, 2568 &psCreateDispClassSwapChainOUT->hSwapChain,
2007 hSwapChainInt, 2569 hSwapChainInt,
2008 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN, 2570 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN,
2009 PVRSRV_HANDLE_ALLOC_FLAG_NONE, 2571 PVRSRV_HANDLE_ALLOC_FLAG_NONE,
2010 psCreateDispClassSwapChainIN->hDeviceKM); 2572 psCreateDispClassSwapChainIN->hDeviceKM);
2011 2573
2012 COMMIT_HANDLE_BATCH_OR_ERROR(psCreateDispClassSwapChainOUT->eError, psPerProc) 2574 COMMIT_HANDLE_BATCH_OR_ERROR(psCreateDispClassSwapChainOUT->eError, psPerProc)
2013 2575
2014 return 0; 2576 return 0;
2015} 2577}
2016 2578
2017static IMG_INT 2579static IMG_INT
2018PVRSRVDestroyDCSwapChainBW(IMG_UINT32 ui32BridgeID, 2580PVRSRVDestroyDCSwapChainBW(IMG_UINT32 ui32BridgeID,
2019 PVRSRV_BRIDGE_IN_DESTROY_DISPCLASS_SWAPCHAIN *psDestroyDispClassSwapChainIN, 2581 PVRSRV_BRIDGE_IN_DESTROY_DISPCLASS_SWAPCHAIN *psDestroyDispClassSwapChainIN,
2020 PVRSRV_BRIDGE_RETURN *psRetOUT, 2582 PVRSRV_BRIDGE_RETURN *psRetOUT,
2021 PVRSRV_PER_PROCESS_DATA *psPerProc) 2583 PVRSRV_PER_PROCESS_DATA *psPerProc)
2022{ 2584{
2023 IMG_VOID *pvSwapChain; 2585 IMG_VOID *pvSwapChain;
2024 2586
2025 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_DESTROY_DISPCLASS_SWAPCHAIN); 2587 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_DESTROY_DISPCLASS_SWAPCHAIN);
2026 2588
2027 psRetOUT->eError = 2589 psRetOUT->eError =
2028 PVRSRVLookupHandle(psPerProc->psHandleBase, &pvSwapChain, 2590 PVRSRVLookupHandle(psPerProc->psHandleBase, &pvSwapChain,
2029 psDestroyDispClassSwapChainIN->hSwapChain, 2591 psDestroyDispClassSwapChainIN->hSwapChain,
2030 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN); 2592 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN);
2031 if(psRetOUT->eError != PVRSRV_OK) 2593 if(psRetOUT->eError != PVRSRV_OK)
2032 { 2594 {
2033 return 0; 2595 return 0;
2034 } 2596 }
2035 2597
2036 psRetOUT->eError = 2598 psRetOUT->eError =
2037 PVRSRVDestroyDCSwapChainKM(pvSwapChain); 2599 PVRSRVDestroyDCSwapChainKM(pvSwapChain);
2038 2600
2039 if(psRetOUT->eError != PVRSRV_OK) 2601 if(psRetOUT->eError != PVRSRV_OK)
2040 { 2602 {
2041 return 0; 2603 return 0;
2042 } 2604 }
2043 2605
2044 psRetOUT->eError = 2606 psRetOUT->eError =
2045 PVRSRVReleaseHandle(psPerProc->psHandleBase, 2607 PVRSRVReleaseHandle(psPerProc->psHandleBase,
2046 psDestroyDispClassSwapChainIN->hSwapChain, 2608 psDestroyDispClassSwapChainIN->hSwapChain,
2047 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN); 2609 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN);
2048 2610
2049 return 0; 2611 return 0;
2050} 2612}
2051 2613
2052static IMG_INT 2614static IMG_INT
2053PVRSRVSetDCDstRectBW(IMG_UINT32 ui32BridgeID, 2615PVRSRVSetDCDstRectBW(IMG_UINT32 ui32BridgeID,
2054 PVRSRV_BRIDGE_IN_SET_DISPCLASS_RECT *psSetDispClassDstRectIN, 2616 PVRSRV_BRIDGE_IN_SET_DISPCLASS_RECT *psSetDispClassDstRectIN,
2055 PVRSRV_BRIDGE_RETURN *psRetOUT, 2617 PVRSRV_BRIDGE_RETURN *psRetOUT,
2056 PVRSRV_PER_PROCESS_DATA *psPerProc) 2618 PVRSRV_PER_PROCESS_DATA *psPerProc)
2057{ 2619{
2058 IMG_VOID *pvDispClassInfo; 2620 IMG_VOID *pvDispClassInfo;
2059 IMG_VOID *pvSwapChain; 2621 IMG_VOID *pvSwapChain;
2060 2622
2061 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SET_DISPCLASS_DSTRECT); 2623 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SET_DISPCLASS_DSTRECT);
2062 2624
2063 psRetOUT->eError = 2625 psRetOUT->eError =
2064 PVRSRVLookupHandle(psPerProc->psHandleBase, 2626 PVRSRVLookupHandle(psPerProc->psHandleBase,
2065 &pvDispClassInfo, 2627 &pvDispClassInfo,
2066 psSetDispClassDstRectIN->hDeviceKM, 2628 psSetDispClassDstRectIN->hDeviceKM,
2067 PVRSRV_HANDLE_TYPE_DISP_INFO); 2629 PVRSRV_HANDLE_TYPE_DISP_INFO);
2068 if(psRetOUT->eError != PVRSRV_OK) 2630 if(psRetOUT->eError != PVRSRV_OK)
2069 { 2631 {
2070 return 0; 2632 return 0;
2071 } 2633 }
2072 2634
2073 psRetOUT->eError = 2635 psRetOUT->eError =
2074 PVRSRVLookupHandle(psPerProc->psHandleBase, 2636 PVRSRVLookupHandle(psPerProc->psHandleBase,
2075 &pvSwapChain, 2637 &pvSwapChain,
2076 psSetDispClassDstRectIN->hSwapChain, 2638 psSetDispClassDstRectIN->hSwapChain,
2077 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN); 2639 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN);
2078 2640
2079 if(psRetOUT->eError != PVRSRV_OK) 2641 if(psRetOUT->eError != PVRSRV_OK)
2080 { 2642 {
2081 return 0; 2643 return 0;
2082 } 2644 }
2083 2645
2084 psRetOUT->eError = 2646 psRetOUT->eError =
2085 PVRSRVSetDCDstRectKM(pvDispClassInfo, 2647 PVRSRVSetDCDstRectKM(pvDispClassInfo,
2086 pvSwapChain, 2648 pvSwapChain,
2087 &psSetDispClassDstRectIN->sRect); 2649 &psSetDispClassDstRectIN->sRect);
2088 2650
2089 return 0; 2651 return 0;
2090} 2652}
2091 2653
2092static IMG_INT 2654static IMG_INT
2093PVRSRVSetDCSrcRectBW(IMG_UINT32 ui32BridgeID, 2655PVRSRVSetDCSrcRectBW(IMG_UINT32 ui32BridgeID,
2094 PVRSRV_BRIDGE_IN_SET_DISPCLASS_RECT *psSetDispClassSrcRectIN, 2656 PVRSRV_BRIDGE_IN_SET_DISPCLASS_RECT *psSetDispClassSrcRectIN,
2095 PVRSRV_BRIDGE_RETURN *psRetOUT, 2657 PVRSRV_BRIDGE_RETURN *psRetOUT,
2096 PVRSRV_PER_PROCESS_DATA *psPerProc) 2658 PVRSRV_PER_PROCESS_DATA *psPerProc)
2097{ 2659{
2098 IMG_VOID *pvDispClassInfo; 2660 IMG_VOID *pvDispClassInfo;
2099 IMG_VOID *pvSwapChain; 2661 IMG_VOID *pvSwapChain;
2100 2662
2101 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SET_DISPCLASS_SRCRECT); 2663 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SET_DISPCLASS_SRCRECT);
2102 2664
2103 psRetOUT->eError = 2665 psRetOUT->eError =
2104 PVRSRVLookupHandle(psPerProc->psHandleBase, 2666 PVRSRVLookupHandle(psPerProc->psHandleBase,
2105 &pvDispClassInfo, 2667 &pvDispClassInfo,
2106 psSetDispClassSrcRectIN->hDeviceKM, 2668 psSetDispClassSrcRectIN->hDeviceKM,
2107 PVRSRV_HANDLE_TYPE_DISP_INFO); 2669 PVRSRV_HANDLE_TYPE_DISP_INFO);
2108 if(psRetOUT->eError != PVRSRV_OK) 2670 if(psRetOUT->eError != PVRSRV_OK)
2109 { 2671 {
2110 return 0; 2672 return 0;
2111 } 2673 }
2112 2674
2113 psRetOUT->eError = 2675 psRetOUT->eError =
2114 PVRSRVLookupHandle(psPerProc->psHandleBase, 2676 PVRSRVLookupHandle(psPerProc->psHandleBase,
2115 &pvSwapChain, 2677 &pvSwapChain,
2116 psSetDispClassSrcRectIN->hSwapChain, 2678 psSetDispClassSrcRectIN->hSwapChain,
2117 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN); 2679 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN);
2118 if(psRetOUT->eError != PVRSRV_OK) 2680 if(psRetOUT->eError != PVRSRV_OK)
2119 { 2681 {
2120 return 0; 2682 return 0;
2121 } 2683 }
2122 2684
2123 psRetOUT->eError = 2685 psRetOUT->eError =
2124 PVRSRVSetDCSrcRectKM(pvDispClassInfo, 2686 PVRSRVSetDCSrcRectKM(pvDispClassInfo,
2125 pvSwapChain, 2687 pvSwapChain,
2126 &psSetDispClassSrcRectIN->sRect); 2688 &psSetDispClassSrcRectIN->sRect);
2127 2689
2128 return 0; 2690 return 0;
2129} 2691}
2130 2692
2131static IMG_INT 2693static IMG_INT
2132PVRSRVSetDCDstColourKeyBW(IMG_UINT32 ui32BridgeID, 2694PVRSRVSetDCDstColourKeyBW(IMG_UINT32 ui32BridgeID,
2133 PVRSRV_BRIDGE_IN_SET_DISPCLASS_COLOURKEY *psSetDispClassColKeyIN, 2695 PVRSRV_BRIDGE_IN_SET_DISPCLASS_COLOURKEY *psSetDispClassColKeyIN,
2134 PVRSRV_BRIDGE_RETURN *psRetOUT, 2696 PVRSRV_BRIDGE_RETURN *psRetOUT,
2135 PVRSRV_PER_PROCESS_DATA *psPerProc) 2697 PVRSRV_PER_PROCESS_DATA *psPerProc)
2136{ 2698{
2137 IMG_VOID *pvDispClassInfo; 2699 IMG_VOID *pvDispClassInfo;
2138 IMG_VOID *pvSwapChain; 2700 IMG_VOID *pvSwapChain;
2139 2701
2140 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SET_DISPCLASS_DSTCOLOURKEY); 2702 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SET_DISPCLASS_DSTCOLOURKEY);
2141 2703
2142 psRetOUT->eError = 2704 psRetOUT->eError =
2143 PVRSRVLookupHandle(psPerProc->psHandleBase, 2705 PVRSRVLookupHandle(psPerProc->psHandleBase,
2144 &pvDispClassInfo, 2706 &pvDispClassInfo,
2145 psSetDispClassColKeyIN->hDeviceKM, 2707 psSetDispClassColKeyIN->hDeviceKM,
2146 PVRSRV_HANDLE_TYPE_DISP_INFO); 2708 PVRSRV_HANDLE_TYPE_DISP_INFO);
2147 if(psRetOUT->eError != PVRSRV_OK) 2709 if(psRetOUT->eError != PVRSRV_OK)
2148 { 2710 {
2149 return 0; 2711 return 0;
2150 } 2712 }
2151 2713
2152 psRetOUT->eError = 2714 psRetOUT->eError =
2153 PVRSRVLookupHandle(psPerProc->psHandleBase, 2715 PVRSRVLookupHandle(psPerProc->psHandleBase,
2154 &pvSwapChain, 2716 &pvSwapChain,
2155 psSetDispClassColKeyIN->hSwapChain, 2717 psSetDispClassColKeyIN->hSwapChain,
2156 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN); 2718 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN);
2157 if(psRetOUT->eError != PVRSRV_OK) 2719 if(psRetOUT->eError != PVRSRV_OK)
2158 { 2720 {
2159 return 0; 2721 return 0;
2160 } 2722 }
2161 2723
2162 psRetOUT->eError = 2724 psRetOUT->eError =
2163 PVRSRVSetDCDstColourKeyKM(pvDispClassInfo, 2725 PVRSRVSetDCDstColourKeyKM(pvDispClassInfo,
2164 pvSwapChain, 2726 pvSwapChain,
2165 psSetDispClassColKeyIN->ui32CKColour); 2727 psSetDispClassColKeyIN->ui32CKColour);
2166 2728
2167 return 0; 2729 return 0;
2168} 2730}
2169 2731
2170static IMG_INT 2732static IMG_INT
2171PVRSRVSetDCSrcColourKeyBW(IMG_UINT32 ui32BridgeID, 2733PVRSRVSetDCSrcColourKeyBW(IMG_UINT32 ui32BridgeID,
2172 PVRSRV_BRIDGE_IN_SET_DISPCLASS_COLOURKEY *psSetDispClassColKeyIN, 2734 PVRSRV_BRIDGE_IN_SET_DISPCLASS_COLOURKEY *psSetDispClassColKeyIN,
2173 PVRSRV_BRIDGE_RETURN *psRetOUT, 2735 PVRSRV_BRIDGE_RETURN *psRetOUT,
2174 PVRSRV_PER_PROCESS_DATA *psPerProc) 2736 PVRSRV_PER_PROCESS_DATA *psPerProc)
2175{ 2737{
2176 IMG_VOID *pvDispClassInfo; 2738 IMG_VOID *pvDispClassInfo;
2177 IMG_VOID *pvSwapChain; 2739 IMG_VOID *pvSwapChain;
2178 2740
2179 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SET_DISPCLASS_SRCCOLOURKEY); 2741 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SET_DISPCLASS_SRCCOLOURKEY);
2180 2742
2181 psRetOUT->eError = 2743 psRetOUT->eError =
2182 PVRSRVLookupHandle(psPerProc->psHandleBase, 2744 PVRSRVLookupHandle(psPerProc->psHandleBase,
2183 &pvDispClassInfo, 2745 &pvDispClassInfo,
2184 psSetDispClassColKeyIN->hDeviceKM, 2746 psSetDispClassColKeyIN->hDeviceKM,
2185 PVRSRV_HANDLE_TYPE_DISP_INFO); 2747 PVRSRV_HANDLE_TYPE_DISP_INFO);
2186 if(psRetOUT->eError != PVRSRV_OK) 2748 if(psRetOUT->eError != PVRSRV_OK)
2187 { 2749 {
2188 return 0; 2750 return 0;
2189 } 2751 }
2190 2752
2191 psRetOUT->eError = 2753 psRetOUT->eError =
2192 PVRSRVLookupHandle(psPerProc->psHandleBase, 2754 PVRSRVLookupHandle(psPerProc->psHandleBase,
2193 &pvSwapChain, 2755 &pvSwapChain,
2194 psSetDispClassColKeyIN->hSwapChain, 2756 psSetDispClassColKeyIN->hSwapChain,
2195 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN); 2757 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN);
2196 if(psRetOUT->eError != PVRSRV_OK) 2758 if(psRetOUT->eError != PVRSRV_OK)
2197 { 2759 {
2198 return 0; 2760 return 0;
2199 } 2761 }
2200 2762
2201 psRetOUT->eError = 2763 psRetOUT->eError =
2202 PVRSRVSetDCSrcColourKeyKM(pvDispClassInfo, 2764 PVRSRVSetDCSrcColourKeyKM(pvDispClassInfo,
2203 pvSwapChain, 2765 pvSwapChain,
2204 psSetDispClassColKeyIN->ui32CKColour); 2766 psSetDispClassColKeyIN->ui32CKColour);
2205 2767
2206 return 0; 2768 return 0;
2207} 2769}
2208 2770
2209static IMG_INT 2771static IMG_INT
2210PVRSRVGetDCBuffersBW(IMG_UINT32 ui32BridgeID, 2772PVRSRVGetDCBuffersBW(IMG_UINT32 ui32BridgeID,
2211 PVRSRV_BRIDGE_IN_GET_DISPCLASS_BUFFERS *psGetDispClassBuffersIN, 2773 PVRSRV_BRIDGE_IN_GET_DISPCLASS_BUFFERS *psGetDispClassBuffersIN,
2212 PVRSRV_BRIDGE_OUT_GET_DISPCLASS_BUFFERS *psGetDispClassBuffersOUT, 2774 PVRSRV_BRIDGE_OUT_GET_DISPCLASS_BUFFERS *psGetDispClassBuffersOUT,
2213 PVRSRV_PER_PROCESS_DATA *psPerProc) 2775 PVRSRV_PER_PROCESS_DATA *psPerProc)
2214{ 2776{
2215 IMG_VOID *pvDispClassInfo; 2777 IMG_VOID *pvDispClassInfo;
2216 IMG_VOID *pvSwapChain; 2778 IMG_VOID *pvSwapChain;
2217 IMG_UINT32 i; 2779 IMG_UINT32 i;
2218 2780#if defined (SUPPORT_SID_INTERFACE)
2219 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GET_DISPCLASS_BUFFERS); 2781 IMG_HANDLE *pahBuffer;
2220 2782#endif
2221 NEW_HANDLE_BATCH_OR_ERROR(psGetDispClassBuffersOUT->eError, psPerProc, PVRSRV_MAX_DC_SWAPCHAIN_BUFFERS)
2222
2223 psGetDispClassBuffersOUT->eError =
2224 PVRSRVLookupHandle(psPerProc->psHandleBase,
2225 &pvDispClassInfo,
2226 psGetDispClassBuffersIN->hDeviceKM,
2227 PVRSRV_HANDLE_TYPE_DISP_INFO);
2228 if(psGetDispClassBuffersOUT->eError != PVRSRV_OK)
2229 {
2230 return 0;
2231 }
2232 2783
2233 psGetDispClassBuffersOUT->eError = 2784 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GET_DISPCLASS_BUFFERS);
2234 PVRSRVLookupHandle(psPerProc->psHandleBase, 2785
2235 &pvSwapChain, 2786 NEW_HANDLE_BATCH_OR_ERROR(psGetDispClassBuffersOUT->eError, psPerProc, PVRSRV_MAX_DC_SWAPCHAIN_BUFFERS)
2236 psGetDispClassBuffersIN->hSwapChain, 2787
2237 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN); 2788 psGetDispClassBuffersOUT->eError =
2238 if(psGetDispClassBuffersOUT->eError != PVRSRV_OK) 2789 PVRSRVLookupHandle(psPerProc->psHandleBase,
2239 { 2790 &pvDispClassInfo,
2240 return 0; 2791 psGetDispClassBuffersIN->hDeviceKM,
2241 } 2792 PVRSRV_HANDLE_TYPE_DISP_INFO);
2793 if(psGetDispClassBuffersOUT->eError != PVRSRV_OK)
2794 {
2795 return 0;
2796 }
2797
2798 psGetDispClassBuffersOUT->eError =
2799 PVRSRVLookupHandle(psPerProc->psHandleBase,
2800 &pvSwapChain,
2801 psGetDispClassBuffersIN->hSwapChain,
2802 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN);
2803 if(psGetDispClassBuffersOUT->eError != PVRSRV_OK)
2804 {
2805 return 0;
2806 }
2807
2808#if defined (SUPPORT_SID_INTERFACE)
2809 psGetDispClassBuffersOUT->eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
2810 sizeof(IMG_HANDLE) * PVRSRV_MAX_DC_SWAPCHAIN_BUFFERS,
2811 (IMG_PVOID *)&pahBuffer, 0,
2812 "Temp Swapchain Buffers");
2813
2814 if (psGetDispClassBuffersOUT->eError != PVRSRV_OK)
2815 {
2816 return 0;
2817 }
2818#endif
2242 2819
2243 psGetDispClassBuffersOUT->eError = 2820 psGetDispClassBuffersOUT->eError =
2244 PVRSRVGetDCBuffersKM(pvDispClassInfo, 2821 PVRSRVGetDCBuffersKM(pvDispClassInfo,
2245 pvSwapChain, 2822 pvSwapChain,
2246 &psGetDispClassBuffersOUT->ui32BufferCount, 2823 &psGetDispClassBuffersOUT->ui32BufferCount,
2247 psGetDispClassBuffersOUT->ahBuffer); 2824#if defined (SUPPORT_SID_INTERFACE)
2248 if (psGetDispClassBuffersOUT->eError != PVRSRV_OK) 2825 pahBuffer);
2249 { 2826#else
2250 return 0; 2827 psGetDispClassBuffersOUT->ahBuffer);
2251 } 2828#endif
2829 if (psGetDispClassBuffersOUT->eError != PVRSRV_OK)
2830 {
2831 return 0;
2832 }
2252 2833
2253 PVR_ASSERT(psGetDispClassBuffersOUT->ui32BufferCount <= PVRSRV_MAX_DC_SWAPCHAIN_BUFFERS); 2834 PVR_ASSERT(psGetDispClassBuffersOUT->ui32BufferCount <= PVRSRV_MAX_DC_SWAPCHAIN_BUFFERS);
2254 2835
2255 for(i = 0; i < psGetDispClassBuffersOUT->ui32BufferCount; i++) 2836 for(i = 0; i < psGetDispClassBuffersOUT->ui32BufferCount; i++)
2256 { 2837 {
2257 IMG_HANDLE hBufferExt; 2838#if defined (SUPPORT_SID_INTERFACE)
2839 IMG_SID hBufferExt;
2840#else
2841 IMG_HANDLE hBufferExt;
2842#endif
2258 2843
2844
2845#if defined (SUPPORT_SID_INTERFACE)
2846 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
2847 &hBufferExt,
2848 pahBuffer[i],
2849 PVRSRV_HANDLE_TYPE_DISP_BUFFER,
2850 (PVRSRV_HANDLE_ALLOC_FLAG)(PVRSRV_HANDLE_ALLOC_FLAG_PRIVATE | PVRSRV_HANDLE_ALLOC_FLAG_SHARED),
2851 psGetDispClassBuffersIN->hSwapChain);
2852#else
2853 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
2854 &hBufferExt,
2855 psGetDispClassBuffersOUT->ahBuffer[i],
2856 PVRSRV_HANDLE_TYPE_DISP_BUFFER,
2857 (PVRSRV_HANDLE_ALLOC_FLAG)(PVRSRV_HANDLE_ALLOC_FLAG_PRIVATE | PVRSRV_HANDLE_ALLOC_FLAG_SHARED),
2858 psGetDispClassBuffersIN->hSwapChain);
2859#endif
2259 2860
2260 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase, 2861 psGetDispClassBuffersOUT->ahBuffer[i] = hBufferExt;
2261 &hBufferExt, 2862 }
2262 psGetDispClassBuffersOUT->ahBuffer[i],
2263 PVRSRV_HANDLE_TYPE_DISP_BUFFER,
2264 (PVRSRV_HANDLE_ALLOC_FLAG)(PVRSRV_HANDLE_ALLOC_FLAG_PRIVATE | PVRSRV_HANDLE_ALLOC_FLAG_SHARED),
2265 psGetDispClassBuffersIN->hSwapChain);
2266 2863
2267 psGetDispClassBuffersOUT->ahBuffer[i] = hBufferExt; 2864#if defined (SUPPORT_SID_INTERFACE)
2268 } 2865 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP,
2866 sizeof(IMG_HANDLE) * PVRSRV_MAX_DC_SWAPCHAIN_BUFFERS,
2867 (IMG_PVOID)pahBuffer, 0);
2868#endif
2269 2869
2270 COMMIT_HANDLE_BATCH_OR_ERROR(psGetDispClassBuffersOUT->eError, psPerProc) 2870 COMMIT_HANDLE_BATCH_OR_ERROR(psGetDispClassBuffersOUT->eError, psPerProc)
2271 2871
2272 return 0; 2872 return 0;
2273} 2873}
2274 2874
2275static IMG_INT 2875static IMG_INT
2276PVRSRVSwapToDCBufferBW(IMG_UINT32 ui32BridgeID, 2876PVRSRVSwapToDCBufferBW(IMG_UINT32 ui32BridgeID,
2277 PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_BUFFER *psSwapDispClassBufferIN, 2877 PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_BUFFER *psSwapDispClassBufferIN,
2278 PVRSRV_BRIDGE_RETURN *psRetOUT, 2878 PVRSRV_BRIDGE_RETURN *psRetOUT,
2279 PVRSRV_PER_PROCESS_DATA *psPerProc) 2879 PVRSRV_PER_PROCESS_DATA *psPerProc)
2280{ 2880{
2281 IMG_VOID *pvDispClassInfo; 2881 IMG_VOID *pvDispClassInfo;
2282 IMG_VOID *pvSwapChainBuf; 2882 IMG_VOID *pvSwapChainBuf;
2283 2883#if defined (SUPPORT_SID_INTERFACE)
2284 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SWAP_DISPCLASS_TO_BUFFER); 2884 IMG_HANDLE hPrivateTag;
2885#endif
2285 2886
2286 psRetOUT->eError = 2887 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SWAP_DISPCLASS_TO_BUFFER);
2287 PVRSRVLookupHandle(psPerProc->psHandleBase, 2888
2288 &pvDispClassInfo, 2889 psRetOUT->eError =
2289 psSwapDispClassBufferIN->hDeviceKM, 2890 PVRSRVLookupHandle(psPerProc->psHandleBase,
2290 PVRSRV_HANDLE_TYPE_DISP_INFO); 2891 &pvDispClassInfo,
2291 if(psRetOUT->eError != PVRSRV_OK) 2892 psSwapDispClassBufferIN->hDeviceKM,
2292 { 2893 PVRSRV_HANDLE_TYPE_DISP_INFO);
2293 return 0; 2894 if(psRetOUT->eError != PVRSRV_OK)
2294 } 2895 {
2896 return 0;
2897 }
2898
2899 psRetOUT->eError =
2900 PVRSRVLookupSubHandle(psPerProc->psHandleBase,
2901 &pvSwapChainBuf,
2902 psSwapDispClassBufferIN->hBuffer,
2903 PVRSRV_HANDLE_TYPE_DISP_BUFFER,
2904 psSwapDispClassBufferIN->hDeviceKM);
2905 if(psRetOUT->eError != PVRSRV_OK)
2906 {
2907 return 0;
2908 }
2909
2910#if defined (SUPPORT_SID_INTERFACE)
2911 if (psSwapDispClassBufferIN->hPrivateTag != 0)
2912 {
2913 psRetOUT->eError =
2914 PVRSRVLookupSubHandle(psPerProc->psHandleBase,
2915 &hPrivateTag,
2916 psSwapDispClassBufferIN->hPrivateTag,
2917 PVRSRV_HANDLE_TYPE_DISP_BUFFER,
2918 psSwapDispClassBufferIN->hDeviceKM);
2919 if(psRetOUT->eError != PVRSRV_OK)
2920 {
2921 return 0;
2922 }
2923 }
2924 else
2925 {
2926 hPrivateTag = IMG_NULL;
2927 }
2928#endif
2295 2929
2296 psRetOUT->eError =
2297 PVRSRVLookupSubHandle(psPerProc->psHandleBase,
2298 &pvSwapChainBuf,
2299 psSwapDispClassBufferIN->hBuffer,
2300 PVRSRV_HANDLE_TYPE_DISP_BUFFER,
2301 psSwapDispClassBufferIN->hDeviceKM);
2302 if(psRetOUT->eError != PVRSRV_OK)
2303 {
2304 return 0;
2305 }
2306 2930
2307 psRetOUT->eError = 2931 psRetOUT->eError =
2308 PVRSRVSwapToDCBufferKM(pvDispClassInfo, 2932 PVRSRVSwapToDCBufferKM(pvDispClassInfo,
2309 pvSwapChainBuf, 2933 pvSwapChainBuf,
2310 psSwapDispClassBufferIN->ui32SwapInterval, 2934 psSwapDispClassBufferIN->ui32SwapInterval,
2311 psSwapDispClassBufferIN->hPrivateTag, 2935#if defined (SUPPORT_SID_INTERFACE)
2312 psSwapDispClassBufferIN->ui32ClipRectCount, 2936 hPrivateTag,
2313 psSwapDispClassBufferIN->sClipRect); 2937#else
2938 psSwapDispClassBufferIN->hPrivateTag,
2939#endif
2940 psSwapDispClassBufferIN->ui32ClipRectCount,
2941 psSwapDispClassBufferIN->sClipRect);
2314 2942
2315 return 0; 2943 return 0;
2316} 2944}
2317 2945
2318static IMG_INT 2946static IMG_INT
2319PVRSRVSwapToDCSystemBW(IMG_UINT32 ui32BridgeID, 2947PVRSRVSwapToDCSystemBW(IMG_UINT32 ui32BridgeID,
2320 PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_SYSTEM *psSwapDispClassSystemIN, 2948 PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_SYSTEM *psSwapDispClassSystemIN,
2321 PVRSRV_BRIDGE_RETURN *psRetOUT, 2949 PVRSRV_BRIDGE_RETURN *psRetOUT,
2322 PVRSRV_PER_PROCESS_DATA *psPerProc) 2950 PVRSRV_PER_PROCESS_DATA *psPerProc)
2323{ 2951{
2324 IMG_VOID *pvDispClassInfo; 2952 IMG_VOID *pvDispClassInfo;
2325 IMG_VOID *pvSwapChain; 2953 IMG_VOID *pvSwapChain;
2326 2954
2327 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SWAP_DISPCLASS_TO_SYSTEM); 2955 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SWAP_DISPCLASS_TO_SYSTEM);
2328 2956
2329 psRetOUT->eError = 2957 psRetOUT->eError =
2330 PVRSRVLookupHandle(psPerProc->psHandleBase, 2958 PVRSRVLookupHandle(psPerProc->psHandleBase,
2331 &pvDispClassInfo, 2959 &pvDispClassInfo,
2332 psSwapDispClassSystemIN->hDeviceKM, 2960 psSwapDispClassSystemIN->hDeviceKM,
2333 PVRSRV_HANDLE_TYPE_DISP_INFO); 2961 PVRSRV_HANDLE_TYPE_DISP_INFO);
2334 if(psRetOUT->eError != PVRSRV_OK) 2962 if(psRetOUT->eError != PVRSRV_OK)
2335 { 2963 {
2336 return 0; 2964 return 0;
2337 } 2965 }
2338 2966
2339 psRetOUT->eError = 2967 psRetOUT->eError =
2340 PVRSRVLookupSubHandle(psPerProc->psHandleBase, 2968 PVRSRVLookupSubHandle(psPerProc->psHandleBase,
2341 &pvSwapChain, 2969 &pvSwapChain,
2342 psSwapDispClassSystemIN->hSwapChain, 2970 psSwapDispClassSystemIN->hSwapChain,
2343 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN, 2971 PVRSRV_HANDLE_TYPE_DISP_SWAP_CHAIN,
2344 psSwapDispClassSystemIN->hDeviceKM); 2972 psSwapDispClassSystemIN->hDeviceKM);
2345 if(psRetOUT->eError != PVRSRV_OK) 2973 if(psRetOUT->eError != PVRSRV_OK)
2346 { 2974 {
2347 return 0; 2975 return 0;
2348 } 2976 }
2349 psRetOUT->eError = 2977 psRetOUT->eError =
2350 PVRSRVSwapToDCSystemKM(pvDispClassInfo, 2978 PVRSRVSwapToDCSystemKM(pvDispClassInfo,
2351 pvSwapChain); 2979 pvSwapChain);
2352 2980
2353 return 0; 2981 return 0;
2354} 2982}
2355 2983
2356static IMG_INT 2984static IMG_INT
2357PVRSRVOpenBCDeviceBW(IMG_UINT32 ui32BridgeID, 2985PVRSRVOpenBCDeviceBW(IMG_UINT32 ui32BridgeID,
2358 PVRSRV_BRIDGE_IN_OPEN_BUFFERCLASS_DEVICE *psOpenBufferClassDeviceIN, 2986 PVRSRV_BRIDGE_IN_OPEN_BUFFERCLASS_DEVICE *psOpenBufferClassDeviceIN,
2359 PVRSRV_BRIDGE_OUT_OPEN_BUFFERCLASS_DEVICE *psOpenBufferClassDeviceOUT, 2987 PVRSRV_BRIDGE_OUT_OPEN_BUFFERCLASS_DEVICE *psOpenBufferClassDeviceOUT,
2360 PVRSRV_PER_PROCESS_DATA *psPerProc) 2988 PVRSRV_PER_PROCESS_DATA *psPerProc)
2361{ 2989{
2362 IMG_HANDLE hDevCookieInt; 2990 IMG_HANDLE hDevCookieInt;
2363 IMG_HANDLE hBufClassInfo; 2991 IMG_HANDLE hBufClassInfo;
2364 2992
2365 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_OPEN_BUFFERCLASS_DEVICE); 2993 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_OPEN_BUFFERCLASS_DEVICE);
2366 2994
2367 NEW_HANDLE_BATCH_OR_ERROR(psOpenBufferClassDeviceOUT->eError, psPerProc, 1) 2995 NEW_HANDLE_BATCH_OR_ERROR(psOpenBufferClassDeviceOUT->eError, psPerProc, 1)
2368 2996
2369 psOpenBufferClassDeviceOUT->eError = 2997 psOpenBufferClassDeviceOUT->eError =
2370 PVRSRVLookupHandle(psPerProc->psHandleBase, 2998 PVRSRVLookupHandle(psPerProc->psHandleBase,
2371 &hDevCookieInt, 2999 &hDevCookieInt,
2372 psOpenBufferClassDeviceIN->hDevCookie, 3000 psOpenBufferClassDeviceIN->hDevCookie,
2373 PVRSRV_HANDLE_TYPE_DEV_NODE); 3001 PVRSRV_HANDLE_TYPE_DEV_NODE);
2374 if(psOpenBufferClassDeviceOUT->eError != PVRSRV_OK) 3002 if(psOpenBufferClassDeviceOUT->eError != PVRSRV_OK)
2375 { 3003 {
2376 return 0; 3004 return 0;
2377 } 3005 }
2378 3006
2379 psOpenBufferClassDeviceOUT->eError = 3007 psOpenBufferClassDeviceOUT->eError =
2380 PVRSRVOpenBCDeviceKM(psPerProc, 3008 PVRSRVOpenBCDeviceKM(psPerProc,
2381 psOpenBufferClassDeviceIN->ui32DeviceID, 3009 psOpenBufferClassDeviceIN->ui32DeviceID,
2382 hDevCookieInt, 3010 hDevCookieInt,
2383 &hBufClassInfo); 3011 &hBufClassInfo);
2384 if(psOpenBufferClassDeviceOUT->eError != PVRSRV_OK) 3012 if(psOpenBufferClassDeviceOUT->eError != PVRSRV_OK)
2385 { 3013 {
2386 return 0; 3014 return 0;
2387 } 3015 }
2388 3016
2389 PVRSRVAllocHandleNR(psPerProc->psHandleBase, 3017 PVRSRVAllocHandleNR(psPerProc->psHandleBase,
2390 &psOpenBufferClassDeviceOUT->hDeviceKM, 3018 &psOpenBufferClassDeviceOUT->hDeviceKM,
2391 hBufClassInfo, 3019 hBufClassInfo,
2392 PVRSRV_HANDLE_TYPE_BUF_INFO, 3020 PVRSRV_HANDLE_TYPE_BUF_INFO,
2393 PVRSRV_HANDLE_ALLOC_FLAG_NONE); 3021 PVRSRV_HANDLE_ALLOC_FLAG_NONE);
2394 3022
2395 COMMIT_HANDLE_BATCH_OR_ERROR(psOpenBufferClassDeviceOUT->eError, psPerProc) 3023 COMMIT_HANDLE_BATCH_OR_ERROR(psOpenBufferClassDeviceOUT->eError, psPerProc)
2396 3024
2397 return 0; 3025 return 0;
2398} 3026}
2399 3027
2400static IMG_INT 3028static IMG_INT
2401PVRSRVCloseBCDeviceBW(IMG_UINT32 ui32BridgeID, 3029PVRSRVCloseBCDeviceBW(IMG_UINT32 ui32BridgeID,
2402 PVRSRV_BRIDGE_IN_CLOSE_BUFFERCLASS_DEVICE *psCloseBufferClassDeviceIN, 3030 PVRSRV_BRIDGE_IN_CLOSE_BUFFERCLASS_DEVICE *psCloseBufferClassDeviceIN,
2403 PVRSRV_BRIDGE_RETURN *psRetOUT, 3031 PVRSRV_BRIDGE_RETURN *psRetOUT,
2404 PVRSRV_PER_PROCESS_DATA *psPerProc) 3032 PVRSRV_PER_PROCESS_DATA *psPerProc)
2405{ 3033{
2406 IMG_VOID *pvBufClassInfo; 3034 IMG_VOID *pvBufClassInfo;
2407 3035
2408 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_CLOSE_BUFFERCLASS_DEVICE); 3036 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_CLOSE_BUFFERCLASS_DEVICE);
2409 3037
2410 psRetOUT->eError = 3038 psRetOUT->eError =
2411 PVRSRVLookupHandle(psPerProc->psHandleBase, 3039 PVRSRVLookupHandle(psPerProc->psHandleBase,
2412 &pvBufClassInfo, 3040 &pvBufClassInfo,
2413 psCloseBufferClassDeviceIN->hDeviceKM, 3041 psCloseBufferClassDeviceIN->hDeviceKM,
2414 PVRSRV_HANDLE_TYPE_BUF_INFO); 3042 PVRSRV_HANDLE_TYPE_BUF_INFO);
2415 if(psRetOUT->eError != PVRSRV_OK) 3043 if(psRetOUT->eError != PVRSRV_OK)
2416 { 3044 {
2417 return 0; 3045 return 0;
2418 } 3046 }
2419 3047
2420 psRetOUT->eError = 3048 psRetOUT->eError =
2421 PVRSRVCloseBCDeviceKM(pvBufClassInfo, IMG_FALSE); 3049 PVRSRVCloseBCDeviceKM(pvBufClassInfo, IMG_FALSE);
2422 3050
2423 if(psRetOUT->eError != PVRSRV_OK) 3051 if(psRetOUT->eError != PVRSRV_OK)
2424 { 3052 {
2425 return 0; 3053 return 0;
2426 } 3054 }
2427 3055
2428 psRetOUT->eError = PVRSRVReleaseHandle(psPerProc->psHandleBase, 3056 psRetOUT->eError = PVRSRVReleaseHandle(psPerProc->psHandleBase,
2429 psCloseBufferClassDeviceIN->hDeviceKM, 3057 psCloseBufferClassDeviceIN->hDeviceKM,
2430 PVRSRV_HANDLE_TYPE_BUF_INFO); 3058 PVRSRV_HANDLE_TYPE_BUF_INFO);
2431 3059
2432 return 0; 3060 return 0;
2433} 3061}
2434 3062
2435static IMG_INT 3063static IMG_INT
2436PVRSRVGetBCInfoBW(IMG_UINT32 ui32BridgeID, 3064PVRSRVGetBCInfoBW(IMG_UINT32 ui32BridgeID,
2437 PVRSRV_BRIDGE_IN_GET_BUFFERCLASS_INFO *psGetBufferClassInfoIN, 3065 PVRSRV_BRIDGE_IN_GET_BUFFERCLASS_INFO *psGetBufferClassInfoIN,
2438 PVRSRV_BRIDGE_OUT_GET_BUFFERCLASS_INFO *psGetBufferClassInfoOUT, 3066 PVRSRV_BRIDGE_OUT_GET_BUFFERCLASS_INFO *psGetBufferClassInfoOUT,
2439 PVRSRV_PER_PROCESS_DATA *psPerProc) 3067 PVRSRV_PER_PROCESS_DATA *psPerProc)
2440{ 3068{
2441 IMG_VOID *pvBufClassInfo; 3069 IMG_VOID *pvBufClassInfo;
2442 3070
2443 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GET_BUFFERCLASS_INFO); 3071 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GET_BUFFERCLASS_INFO);
2444 3072
2445 psGetBufferClassInfoOUT->eError = 3073 psGetBufferClassInfoOUT->eError =
2446 PVRSRVLookupHandle(psPerProc->psHandleBase, 3074 PVRSRVLookupHandle(psPerProc->psHandleBase,
2447 &pvBufClassInfo, 3075 &pvBufClassInfo,
2448 psGetBufferClassInfoIN->hDeviceKM, 3076 psGetBufferClassInfoIN->hDeviceKM,
2449 PVRSRV_HANDLE_TYPE_BUF_INFO); 3077 PVRSRV_HANDLE_TYPE_BUF_INFO);
2450 if(psGetBufferClassInfoOUT->eError != PVRSRV_OK) 3078 if(psGetBufferClassInfoOUT->eError != PVRSRV_OK)
2451 { 3079 {
2452 return 0; 3080 return 0;
2453 } 3081 }
2454 3082
2455 psGetBufferClassInfoOUT->eError = 3083 psGetBufferClassInfoOUT->eError =
2456 PVRSRVGetBCInfoKM(pvBufClassInfo, 3084 PVRSRVGetBCInfoKM(pvBufClassInfo,
2457 &psGetBufferClassInfoOUT->sBufferInfo); 3085 &psGetBufferClassInfoOUT->sBufferInfo);
2458 return 0; 3086 return 0;
2459} 3087}
2460 3088
2461static IMG_INT 3089static IMG_INT
2462PVRSRVGetBCBufferBW(IMG_UINT32 ui32BridgeID, 3090PVRSRVGetBCBufferBW(IMG_UINT32 ui32BridgeID,
2463 PVRSRV_BRIDGE_IN_GET_BUFFERCLASS_BUFFER *psGetBufferClassBufferIN, 3091 PVRSRV_BRIDGE_IN_GET_BUFFERCLASS_BUFFER *psGetBufferClassBufferIN,
2464 PVRSRV_BRIDGE_OUT_GET_BUFFERCLASS_BUFFER *psGetBufferClassBufferOUT, 3092 PVRSRV_BRIDGE_OUT_GET_BUFFERCLASS_BUFFER *psGetBufferClassBufferOUT,
2465 PVRSRV_PER_PROCESS_DATA *psPerProc) 3093 PVRSRV_PER_PROCESS_DATA *psPerProc)
2466{ 3094{
2467 IMG_VOID *pvBufClassInfo; 3095 IMG_VOID *pvBufClassInfo;
2468 IMG_HANDLE hBufferInt; 3096 IMG_HANDLE hBufferInt;
2469 3097
2470 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GET_BUFFERCLASS_BUFFER); 3098 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GET_BUFFERCLASS_BUFFER);
2471 3099
2472 NEW_HANDLE_BATCH_OR_ERROR(psGetBufferClassBufferOUT->eError, psPerProc, 1) 3100 NEW_HANDLE_BATCH_OR_ERROR(psGetBufferClassBufferOUT->eError, psPerProc, 1)
2473 3101
2474 psGetBufferClassBufferOUT->eError = 3102 psGetBufferClassBufferOUT->eError =
2475 PVRSRVLookupHandle(psPerProc->psHandleBase, 3103 PVRSRVLookupHandle(psPerProc->psHandleBase,
2476 &pvBufClassInfo, 3104 &pvBufClassInfo,
2477 psGetBufferClassBufferIN->hDeviceKM, 3105 psGetBufferClassBufferIN->hDeviceKM,
2478 PVRSRV_HANDLE_TYPE_BUF_INFO); 3106 PVRSRV_HANDLE_TYPE_BUF_INFO);
2479 if(psGetBufferClassBufferOUT->eError != PVRSRV_OK) 3107 if(psGetBufferClassBufferOUT->eError != PVRSRV_OK)
2480 { 3108 {
2481 return 0; 3109 return 0;
2482 } 3110 }
2483 3111
2484 psGetBufferClassBufferOUT->eError = 3112 psGetBufferClassBufferOUT->eError =
2485 PVRSRVGetBCBufferKM(pvBufClassInfo, 3113 PVRSRVGetBCBufferKM(pvBufClassInfo,
2486 psGetBufferClassBufferIN->ui32BufferIndex, 3114 psGetBufferClassBufferIN->ui32BufferIndex,
2487 &hBufferInt); 3115 &hBufferInt);
2488 3116
2489 if(psGetBufferClassBufferOUT->eError != PVRSRV_OK) 3117 if(psGetBufferClassBufferOUT->eError != PVRSRV_OK)
2490 { 3118 {
2491 return 0; 3119 return 0;
2492 } 3120 }
2493 3121
2494 3122
2495 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase, 3123 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
2496 &psGetBufferClassBufferOUT->hBuffer, 3124 &psGetBufferClassBufferOUT->hBuffer,
2497 hBufferInt, 3125 hBufferInt,
2498 PVRSRV_HANDLE_TYPE_BUF_BUFFER, 3126 PVRSRV_HANDLE_TYPE_BUF_BUFFER,
2499 (PVRSRV_HANDLE_ALLOC_FLAG)(PVRSRV_HANDLE_ALLOC_FLAG_PRIVATE | PVRSRV_HANDLE_ALLOC_FLAG_SHARED), 3127 (PVRSRV_HANDLE_ALLOC_FLAG)(PVRSRV_HANDLE_ALLOC_FLAG_PRIVATE | PVRSRV_HANDLE_ALLOC_FLAG_SHARED),
2500 psGetBufferClassBufferIN->hDeviceKM); 3128 psGetBufferClassBufferIN->hDeviceKM);
2501 3129
2502 COMMIT_HANDLE_BATCH_OR_ERROR(psGetBufferClassBufferOUT->eError, psPerProc) 3130 COMMIT_HANDLE_BATCH_OR_ERROR(psGetBufferClassBufferOUT->eError, psPerProc)
2503 3131
2504 return 0; 3132 return 0;
2505} 3133}
2506 3134
2507 3135
2508static IMG_INT 3136static IMG_INT
2509PVRSRVAllocSharedSysMemoryBW(IMG_UINT32 ui32BridgeID, 3137PVRSRVAllocSharedSysMemoryBW(IMG_UINT32 ui32BridgeID,
2510 PVRSRV_BRIDGE_IN_ALLOC_SHARED_SYS_MEM *psAllocSharedSysMemIN, 3138 PVRSRV_BRIDGE_IN_ALLOC_SHARED_SYS_MEM *psAllocSharedSysMemIN,
2511 PVRSRV_BRIDGE_OUT_ALLOC_SHARED_SYS_MEM *psAllocSharedSysMemOUT, 3139 PVRSRV_BRIDGE_OUT_ALLOC_SHARED_SYS_MEM *psAllocSharedSysMemOUT,
2512 PVRSRV_PER_PROCESS_DATA *psPerProc) 3140 PVRSRV_PER_PROCESS_DATA *psPerProc)
2513{ 3141{
2514 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 3142 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
2515 3143
2516 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ALLOC_SHARED_SYS_MEM); 3144 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ALLOC_SHARED_SYS_MEM);
2517 3145
2518 NEW_HANDLE_BATCH_OR_ERROR(psAllocSharedSysMemOUT->eError, psPerProc, 1) 3146 NEW_HANDLE_BATCH_OR_ERROR(psAllocSharedSysMemOUT->eError, psPerProc, 1)
2519 3147
2520 psAllocSharedSysMemOUT->eError = 3148 psAllocSharedSysMemOUT->eError =
2521 PVRSRVAllocSharedSysMemoryKM(psPerProc, 3149 PVRSRVAllocSharedSysMemoryKM(psPerProc,
2522 psAllocSharedSysMemIN->ui32Flags, 3150 psAllocSharedSysMemIN->ui32Flags,
2523 psAllocSharedSysMemIN->ui32Size, 3151 psAllocSharedSysMemIN->ui32Size,
2524 &psKernelMemInfo); 3152 &psKernelMemInfo);
2525 if(psAllocSharedSysMemOUT->eError != PVRSRV_OK) 3153 if(psAllocSharedSysMemOUT->eError != PVRSRV_OK)
2526 { 3154 {
2527 return 0; 3155 return 0;
2528 } 3156 }
2529 3157
2530 OSMemSet(&psAllocSharedSysMemOUT->sClientMemInfo, 3158 OSMemSet(&psAllocSharedSysMemOUT->sClientMemInfo,
2531 0, 3159 0,
2532 sizeof(psAllocSharedSysMemOUT->sClientMemInfo)); 3160 sizeof(psAllocSharedSysMemOUT->sClientMemInfo));
2533 3161
2534 psAllocSharedSysMemOUT->sClientMemInfo.pvLinAddrKM = 3162 psAllocSharedSysMemOUT->sClientMemInfo.pvLinAddrKM =
2535 psKernelMemInfo->pvLinAddrKM; 3163 psKernelMemInfo->pvLinAddrKM;
2536 3164
2537 psAllocSharedSysMemOUT->sClientMemInfo.pvLinAddr = 0; 3165 psAllocSharedSysMemOUT->sClientMemInfo.pvLinAddr = 0;
2538 psAllocSharedSysMemOUT->sClientMemInfo.ui32Flags = 3166 psAllocSharedSysMemOUT->sClientMemInfo.ui32Flags =
2539 psKernelMemInfo->ui32Flags; 3167 psKernelMemInfo->ui32Flags;
2540 psAllocSharedSysMemOUT->sClientMemInfo.ui32AllocSize = 3168 psAllocSharedSysMemOUT->sClientMemInfo.uAllocSize =
2541 psKernelMemInfo->ui32AllocSize; 3169 psKernelMemInfo->uAllocSize;
2542 psAllocSharedSysMemOUT->sClientMemInfo.hMappingInfo = psKernelMemInfo->sMemBlk.hOSMemHandle; 3170#if defined (SUPPORT_SID_INTERFACE)
3171 if (psKernelMemInfo->sMemBlk.hOSMemHandle != IMG_NULL)
3172 {
3173 PVRSRVAllocHandleNR(psPerProc->psHandleBase,
3174 &psAllocSharedSysMemOUT->sClientMemInfo.hMappingInfo,
3175 psKernelMemInfo->sMemBlk.hOSMemHandle,
3176 PVRSRV_HANDLE_TYPE_SHARED_SYS_MEM_INFO,
3177 PVRSRV_HANDLE_ALLOC_FLAG_NONE);
3178 }
3179 else
3180 {
3181 psAllocSharedSysMemOUT->sClientMemInfo.hMappingInfo = 0;
3182 }
3183#else
3184 psAllocSharedSysMemOUT->sClientMemInfo.hMappingInfo = psKernelMemInfo->sMemBlk.hOSMemHandle;
3185#endif
2543 3186
2544 PVRSRVAllocHandleNR(psPerProc->psHandleBase, 3187 PVRSRVAllocHandleNR(psPerProc->psHandleBase,
2545 &psAllocSharedSysMemOUT->sClientMemInfo.hKernelMemInfo, 3188 &psAllocSharedSysMemOUT->sClientMemInfo.hKernelMemInfo,
2546 psKernelMemInfo, 3189 psKernelMemInfo,
2547 PVRSRV_HANDLE_TYPE_SHARED_SYS_MEM_INFO, 3190 PVRSRV_HANDLE_TYPE_SHARED_SYS_MEM_INFO,
2548 PVRSRV_HANDLE_ALLOC_FLAG_NONE); 3191 PVRSRV_HANDLE_ALLOC_FLAG_NONE);
2549 3192
2550 COMMIT_HANDLE_BATCH_OR_ERROR(psAllocSharedSysMemOUT->eError, psPerProc) 3193 COMMIT_HANDLE_BATCH_OR_ERROR(psAllocSharedSysMemOUT->eError, psPerProc)
2551 3194
2552 return 0; 3195 return 0;
2553} 3196}
2554 3197
2555static IMG_INT 3198static IMG_INT
2556PVRSRVFreeSharedSysMemoryBW(IMG_UINT32 ui32BridgeID, 3199PVRSRVFreeSharedSysMemoryBW(IMG_UINT32 ui32BridgeID,
2557 PVRSRV_BRIDGE_IN_FREE_SHARED_SYS_MEM *psFreeSharedSysMemIN, 3200 PVRSRV_BRIDGE_IN_FREE_SHARED_SYS_MEM *psFreeSharedSysMemIN,
2558 PVRSRV_BRIDGE_OUT_FREE_SHARED_SYS_MEM *psFreeSharedSysMemOUT, 3201 PVRSRV_BRIDGE_OUT_FREE_SHARED_SYS_MEM *psFreeSharedSysMemOUT,
2559 PVRSRV_PER_PROCESS_DATA *psPerProc) 3202 PVRSRV_PER_PROCESS_DATA *psPerProc)
2560{ 3203{
2561 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 3204 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
2562
2563 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_FREE_SHARED_SYS_MEM);
2564 3205
2565 psFreeSharedSysMemOUT->eError = 3206 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_FREE_SHARED_SYS_MEM);
2566 PVRSRVLookupHandle(psPerProc->psHandleBase,
2567 (IMG_VOID **)&psKernelMemInfo,
2568 psFreeSharedSysMemIN->psKernelMemInfo,
2569 PVRSRV_HANDLE_TYPE_SHARED_SYS_MEM_INFO);
2570 3207
2571 if(psFreeSharedSysMemOUT->eError != PVRSRV_OK) 3208 psFreeSharedSysMemOUT->eError =
2572 return 0; 3209 PVRSRVLookupHandle(psPerProc->psHandleBase,
2573 3210 (IMG_VOID **)&psKernelMemInfo,
2574 psFreeSharedSysMemOUT->eError = 3211#if defined (SUPPORT_SID_INTERFACE)
2575 PVRSRVFreeSharedSysMemoryKM(psKernelMemInfo); 3212 psFreeSharedSysMemIN->hKernelMemInfo,
2576 if(psFreeSharedSysMemOUT->eError != PVRSRV_OK) 3213#else
2577 return 0; 3214 psFreeSharedSysMemIN->psKernelMemInfo,
3215#endif
3216 PVRSRV_HANDLE_TYPE_SHARED_SYS_MEM_INFO);
3217
3218 if(psFreeSharedSysMemOUT->eError != PVRSRV_OK)
3219 return 0;
3220
3221 psFreeSharedSysMemOUT->eError =
3222 PVRSRVFreeSharedSysMemoryKM(psKernelMemInfo);
3223 if(psFreeSharedSysMemOUT->eError != PVRSRV_OK)
3224 return 0;
3225#if defined (SUPPORT_SID_INTERFACE)
3226 if (psFreeSharedSysMemIN->hMappingInfo != 0)
3227 {
3228 psFreeSharedSysMemOUT->eError =
3229 PVRSRVReleaseHandle(psPerProc->psHandleBase,
3230 psFreeSharedSysMemIN->hMappingInfo,
3231 PVRSRV_HANDLE_TYPE_SHARED_SYS_MEM_INFO);
3232 if(psFreeSharedSysMemOUT->eError != PVRSRV_OK)
3233 {
3234 return 0;
3235 }
3236 }
3237#endif
2578 3238
2579 psFreeSharedSysMemOUT->eError = 3239 psFreeSharedSysMemOUT->eError =
2580 PVRSRVReleaseHandle(psPerProc->psHandleBase, 3240 PVRSRVReleaseHandle(psPerProc->psHandleBase,
2581 psFreeSharedSysMemIN->psKernelMemInfo, 3241#if defined (SUPPORT_SID_INTERFACE)
2582 PVRSRV_HANDLE_TYPE_SHARED_SYS_MEM_INFO); 3242 psFreeSharedSysMemIN->hKernelMemInfo,
2583 return 0; 3243#else
3244 psFreeSharedSysMemIN->psKernelMemInfo,
3245#endif
3246 PVRSRV_HANDLE_TYPE_SHARED_SYS_MEM_INFO);
3247 return 0;
2584} 3248}
2585 3249
2586static IMG_INT 3250static IMG_INT
2587PVRSRVMapMemInfoMemBW(IMG_UINT32 ui32BridgeID, 3251PVRSRVMapMemInfoMemBW(IMG_UINT32 ui32BridgeID,
2588 PVRSRV_BRIDGE_IN_MAP_MEMINFO_MEM *psMapMemInfoMemIN, 3252 PVRSRV_BRIDGE_IN_MAP_MEMINFO_MEM *psMapMemInfoMemIN,
2589 PVRSRV_BRIDGE_OUT_MAP_MEMINFO_MEM *psMapMemInfoMemOUT, 3253 PVRSRV_BRIDGE_OUT_MAP_MEMINFO_MEM *psMapMemInfoMemOUT,
2590 PVRSRV_PER_PROCESS_DATA *psPerProc) 3254 PVRSRV_PER_PROCESS_DATA *psPerProc)
2591{ 3255{
2592 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 3256 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
2593 PVRSRV_HANDLE_TYPE eHandleType; 3257 PVRSRV_HANDLE_TYPE eHandleType;
2594 IMG_HANDLE hParent; 3258#if defined (SUPPORT_SID_INTERFACE)
2595 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_MAP_MEMINFO_MEM); 3259 IMG_SID hParent;
2596
2597 NEW_HANDLE_BATCH_OR_ERROR(psMapMemInfoMemOUT->eError, psPerProc, 2)
2598
2599 psMapMemInfoMemOUT->eError =
2600 PVRSRVLookupHandleAnyType(psPerProc->psHandleBase,
2601 (IMG_VOID **)&psKernelMemInfo,
2602 &eHandleType,
2603 psMapMemInfoMemIN->hKernelMemInfo);
2604 if(psMapMemInfoMemOUT->eError != PVRSRV_OK)
2605 {
2606 return 0;
2607 }
2608
2609 switch (eHandleType)
2610 {
2611#if defined(PVR_SECURE_HANDLES)
2612 case PVRSRV_HANDLE_TYPE_MEM_INFO:
2613 case PVRSRV_HANDLE_TYPE_MEM_INFO_REF:
2614 case PVRSRV_HANDLE_TYPE_SHARED_SYS_MEM_INFO:
2615#else 3260#else
2616 case PVRSRV_HANDLE_TYPE_NONE: 3261 IMG_HANDLE hParent;
3262#endif
3263 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_MAP_MEMINFO_MEM);
3264
3265 NEW_HANDLE_BATCH_OR_ERROR(psMapMemInfoMemOUT->eError, psPerProc, 2)
3266
3267 psMapMemInfoMemOUT->eError =
3268 PVRSRVLookupHandleAnyType(psPerProc->psHandleBase,
3269 (IMG_VOID **)&psKernelMemInfo,
3270 &eHandleType,
3271 psMapMemInfoMemIN->hKernelMemInfo);
3272 if(psMapMemInfoMemOUT->eError != PVRSRV_OK)
3273 {
3274 return 0;
3275 }
3276
3277 switch (eHandleType)
3278 {
3279#if defined(PVR_SECURE_HANDLES) || defined (SUPPORT_SID_INTERFACE)
3280 case PVRSRV_HANDLE_TYPE_MEM_INFO:
3281 case PVRSRV_HANDLE_TYPE_MEM_INFO_REF:
3282 case PVRSRV_HANDLE_TYPE_SHARED_SYS_MEM_INFO:
3283#else
3284 case PVRSRV_HANDLE_TYPE_NONE:
3285#endif
3286 break;
3287 default:
3288 psMapMemInfoMemOUT->eError = PVRSRV_ERROR_INVALID_HANDLE_TYPE;
3289 return 0;
3290 }
3291
3292
3293 psMapMemInfoMemOUT->eError =
3294 PVRSRVGetParentHandle(psPerProc->psHandleBase,
3295 &hParent,
3296 psMapMemInfoMemIN->hKernelMemInfo,
3297 eHandleType);
3298 if (psMapMemInfoMemOUT->eError != PVRSRV_OK)
3299 {
3300 return 0;
3301 }
3302#if defined (SUPPORT_SID_INTERFACE)
3303 if (hParent == 0)
3304#else
3305 if (hParent == IMG_NULL)
3306#endif
3307 {
3308 hParent = psMapMemInfoMemIN->hKernelMemInfo;
3309 }
3310
3311 OSMemSet(&psMapMemInfoMemOUT->sClientMemInfo,
3312 0,
3313 sizeof(psMapMemInfoMemOUT->sClientMemInfo));
3314
3315 psMapMemInfoMemOUT->sClientMemInfo.pvLinAddrKM =
3316 psKernelMemInfo->pvLinAddrKM;
3317
3318 psMapMemInfoMemOUT->sClientMemInfo.pvLinAddr = 0;
3319 psMapMemInfoMemOUT->sClientMemInfo.sDevVAddr =
3320 psKernelMemInfo->sDevVAddr;
3321 psMapMemInfoMemOUT->sClientMemInfo.ui32Flags =
3322 psKernelMemInfo->ui32Flags;
3323 psMapMemInfoMemOUT->sClientMemInfo.uAllocSize =
3324 psKernelMemInfo->uAllocSize;
3325#if defined (SUPPORT_SID_INTERFACE)
3326 if (psKernelMemInfo->sMemBlk.hOSMemHandle != IMG_NULL)
3327 {
3328 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
3329 &psMapMemInfoMemOUT->sClientMemInfo.hMappingInfo,
3330 psKernelMemInfo->sMemBlk.hOSMemHandle,
3331 PVRSRV_HANDLE_TYPE_MEM_INFO_REF,
3332 PVRSRV_HANDLE_ALLOC_FLAG_MULTI,
3333 hParent);
3334 }
3335 else
3336 {
3337 psMapMemInfoMemOUT->sClientMemInfo.hMappingInfo = 0;
3338 }
3339#else
3340 psMapMemInfoMemOUT->sClientMemInfo.hMappingInfo = psKernelMemInfo->sMemBlk.hOSMemHandle;
2617#endif 3341#endif
2618 break;
2619 default:
2620 psMapMemInfoMemOUT->eError = PVRSRV_ERROR_INVALID_HANDLE_TYPE;
2621 return 0;
2622 }
2623
2624
2625 psMapMemInfoMemOUT->eError =
2626 PVRSRVGetParentHandle(psPerProc->psHandleBase,
2627 &hParent,
2628 psMapMemInfoMemIN->hKernelMemInfo,
2629 eHandleType);
2630 if (psMapMemInfoMemOUT->eError != PVRSRV_OK)
2631 {
2632 return 0;
2633 }
2634 if (hParent == IMG_NULL)
2635 {
2636 hParent = psMapMemInfoMemIN->hKernelMemInfo;
2637 }
2638
2639 OSMemSet(&psMapMemInfoMemOUT->sClientMemInfo,
2640 0,
2641 sizeof(psMapMemInfoMemOUT->sClientMemInfo));
2642
2643 psMapMemInfoMemOUT->sClientMemInfo.pvLinAddrKM =
2644 psKernelMemInfo->pvLinAddrKM;
2645
2646 psMapMemInfoMemOUT->sClientMemInfo.pvLinAddr = 0;
2647 psMapMemInfoMemOUT->sClientMemInfo.sDevVAddr =
2648 psKernelMemInfo->sDevVAddr;
2649 psMapMemInfoMemOUT->sClientMemInfo.ui32Flags =
2650 psKernelMemInfo->ui32Flags;
2651 psMapMemInfoMemOUT->sClientMemInfo.ui32AllocSize =
2652 psKernelMemInfo->ui32AllocSize;
2653 psMapMemInfoMemOUT->sClientMemInfo.hMappingInfo = psKernelMemInfo->sMemBlk.hOSMemHandle;
2654
2655 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
2656 &psMapMemInfoMemOUT->sClientMemInfo.hKernelMemInfo,
2657 psKernelMemInfo,
2658 PVRSRV_HANDLE_TYPE_MEM_INFO_REF,
2659 PVRSRV_HANDLE_ALLOC_FLAG_MULTI,
2660 hParent);
2661
2662 if(psKernelMemInfo->ui32Flags & PVRSRV_MEM_NO_SYNCOBJ)
2663 {
2664
2665 OSMemSet(&psMapMemInfoMemOUT->sClientSyncInfo,
2666 0,
2667 sizeof (PVRSRV_CLIENT_SYNC_INFO));
2668 }
2669 else
2670 {
2671
2672 psMapMemInfoMemOUT->sClientSyncInfo.psSyncData =
2673 psKernelMemInfo->psKernelSyncInfo->psSyncData;
2674 psMapMemInfoMemOUT->sClientSyncInfo.sWriteOpsCompleteDevVAddr =
2675 psKernelMemInfo->psKernelSyncInfo->sWriteOpsCompleteDevVAddr;
2676 psMapMemInfoMemOUT->sClientSyncInfo.sReadOpsCompleteDevVAddr =
2677 psKernelMemInfo->psKernelSyncInfo->sReadOpsCompleteDevVAddr;
2678 3342
2679 psMapMemInfoMemOUT->sClientSyncInfo.hMappingInfo = 3343 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
2680 psKernelMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle; 3344 &psMapMemInfoMemOUT->sClientMemInfo.hKernelMemInfo,
3345 psKernelMemInfo,
3346 PVRSRV_HANDLE_TYPE_MEM_INFO_REF,
3347 PVRSRV_HANDLE_ALLOC_FLAG_MULTI,
3348 hParent);
3349
3350 if(psKernelMemInfo->ui32Flags & PVRSRV_MEM_NO_SYNCOBJ)
3351 {
3352
3353 OSMemSet(&psMapMemInfoMemOUT->sClientSyncInfo,
3354 0,
3355 sizeof (PVRSRV_CLIENT_SYNC_INFO));
3356 }
3357 else
3358 {
3359
3360#if !defined(PVRSRV_DISABLE_UM_SYNCOBJ_MAPPINGS)
3361 psMapMemInfoMemOUT->sClientSyncInfo.psSyncData =
3362 psKernelMemInfo->psKernelSyncInfo->psSyncData;
3363 psMapMemInfoMemOUT->sClientSyncInfo.sWriteOpsCompleteDevVAddr =
3364 psKernelMemInfo->psKernelSyncInfo->sWriteOpsCompleteDevVAddr;
3365 psMapMemInfoMemOUT->sClientSyncInfo.sReadOpsCompleteDevVAddr =
3366 psKernelMemInfo->psKernelSyncInfo->sReadOpsCompleteDevVAddr;
3367
3368#if defined (SUPPORT_SID_INTERFACE)
3369 if (psKernelMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle != IMG_NULL)
3370 {
3371 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
3372 &psMapMemInfoMemOUT->sClientSyncInfo.hMappingInfo,
3373 psKernelMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle,
3374 PVRSRV_HANDLE_TYPE_SYNC_INFO,
3375 PVRSRV_HANDLE_ALLOC_FLAG_MULTI,
3376 psMapMemInfoMemOUT->sClientMemInfo.hKernelMemInfo);
3377 }
3378 else
3379 {
3380 psMapMemInfoMemOUT->sClientSyncInfo.hMappingInfo = 0;
3381 }
3382#else
3383 psMapMemInfoMemOUT->sClientSyncInfo.hMappingInfo =
3384 psKernelMemInfo->psKernelSyncInfo->psSyncDataMemInfoKM->sMemBlk.hOSMemHandle;
3385#endif
3386#endif
2681 3387
2682 psMapMemInfoMemOUT->sClientMemInfo.psClientSyncInfo = &psMapMemInfoMemOUT->sClientSyncInfo; 3388 psMapMemInfoMemOUT->sClientMemInfo.psClientSyncInfo = &psMapMemInfoMemOUT->sClientSyncInfo;
2683 3389
2684 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase, 3390 PVRSRVAllocSubHandleNR(psPerProc->psHandleBase,
2685 &psMapMemInfoMemOUT->sClientSyncInfo.hKernelSyncInfo, 3391 &psMapMemInfoMemOUT->sClientSyncInfo.hKernelSyncInfo,
2686 psKernelMemInfo->psKernelSyncInfo, 3392 psKernelMemInfo->psKernelSyncInfo,
2687 PVRSRV_HANDLE_TYPE_SYNC_INFO, 3393 PVRSRV_HANDLE_TYPE_SYNC_INFO,
2688 PVRSRV_HANDLE_ALLOC_FLAG_MULTI, 3394 PVRSRV_HANDLE_ALLOC_FLAG_MULTI,
2689 psMapMemInfoMemOUT->sClientMemInfo.hKernelMemInfo); 3395 psMapMemInfoMemOUT->sClientMemInfo.hKernelMemInfo);
2690 } 3396 }
2691 3397
2692 COMMIT_HANDLE_BATCH_OR_ERROR(psMapMemInfoMemOUT->eError, psPerProc) 3398 COMMIT_HANDLE_BATCH_OR_ERROR(psMapMemInfoMemOUT->eError, psPerProc)
2693 3399
2694 return 0; 3400 return 0;
2695} 3401}
2696 3402
2697 3403
2698 3404
2699static IMG_INT 3405static IMG_INT
2700MMU_GetPDDevPAddrBW(IMG_UINT32 ui32BridgeID, 3406MMU_GetPDDevPAddrBW(IMG_UINT32 ui32BridgeID,
2701 PVRSRV_BRIDGE_IN_GETMMU_PD_DEVPADDR *psGetMmuPDDevPAddrIN, 3407 PVRSRV_BRIDGE_IN_GETMMU_PD_DEVPADDR *psGetMmuPDDevPAddrIN,
2702 PVRSRV_BRIDGE_OUT_GETMMU_PD_DEVPADDR *psGetMmuPDDevPAddrOUT, 3408 PVRSRV_BRIDGE_OUT_GETMMU_PD_DEVPADDR *psGetMmuPDDevPAddrOUT,
2703 PVRSRV_PER_PROCESS_DATA *psPerProc) 3409 PVRSRV_PER_PROCESS_DATA *psPerProc)
2704{ 3410{
2705 IMG_HANDLE hDevMemContextInt; 3411 IMG_HANDLE hDevMemContextInt;
2706 3412
2707 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GETMMU_PD_DEVPADDR); 3413 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_GETMMU_PD_DEVPADDR);
2708 3414
2709 psGetMmuPDDevPAddrOUT->eError = 3415 psGetMmuPDDevPAddrOUT->eError =
2710 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevMemContextInt, 3416 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevMemContextInt,
2711 psGetMmuPDDevPAddrIN->hDevMemContext, 3417 psGetMmuPDDevPAddrIN->hDevMemContext,
2712 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT); 3418 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT);
2713 if(psGetMmuPDDevPAddrOUT->eError != PVRSRV_OK) 3419 if(psGetMmuPDDevPAddrOUT->eError != PVRSRV_OK)
2714 { 3420 {
2715 return 0; 3421 return 0;
2716 } 3422 }
2717 3423
2718 psGetMmuPDDevPAddrOUT->sPDDevPAddr = 3424 psGetMmuPDDevPAddrOUT->sPDDevPAddr =
2719 BM_GetDeviceNode(hDevMemContextInt)->pfnMMUGetPDDevPAddr(BM_GetMMUContextFromMemContext(hDevMemContextInt)); 3425 BM_GetDeviceNode(hDevMemContextInt)->pfnMMUGetPDDevPAddr(BM_GetMMUContextFromMemContext(hDevMemContextInt));
2720 if(psGetMmuPDDevPAddrOUT->sPDDevPAddr.uiAddr) 3426 if(psGetMmuPDDevPAddrOUT->sPDDevPAddr.uiAddr)
2721 { 3427 {
2722 psGetMmuPDDevPAddrOUT->eError = PVRSRV_OK; 3428 psGetMmuPDDevPAddrOUT->eError = PVRSRV_OK;
2723 } 3429 }
2724 else 3430 else
2725 { 3431 {
2726 psGetMmuPDDevPAddrOUT->eError = PVRSRV_ERROR_INVALID_PHYS_ADDR; 3432 psGetMmuPDDevPAddrOUT->eError = PVRSRV_ERROR_INVALID_PHYS_ADDR;
2727 } 3433 }
2728 return 0; 3434 return 0;
2729} 3435}
2730 3436
2731 3437
2732 3438
2733IMG_INT 3439IMG_INT
2734DummyBW(IMG_UINT32 ui32BridgeID, 3440DummyBW(IMG_UINT32 ui32BridgeID,
2735 IMG_VOID *psBridgeIn, 3441 IMG_VOID *psBridgeIn,
2736 IMG_VOID *psBridgeOut, 3442 IMG_VOID *psBridgeOut,
2737 PVRSRV_PER_PROCESS_DATA *psPerProc) 3443 PVRSRV_PER_PROCESS_DATA *psPerProc)
2738{ 3444{
2739#if !defined(DEBUG) 3445#if !defined(DEBUG)
2740 PVR_UNREFERENCED_PARAMETER(ui32BridgeID); 3446 PVR_UNREFERENCED_PARAMETER(ui32BridgeID);
2741#endif 3447#endif
2742 PVR_UNREFERENCED_PARAMETER(psBridgeIn); 3448 PVR_UNREFERENCED_PARAMETER(psBridgeIn);
2743 PVR_UNREFERENCED_PARAMETER(psBridgeOut); 3449 PVR_UNREFERENCED_PARAMETER(psBridgeOut);
2744 PVR_UNREFERENCED_PARAMETER(psPerProc); 3450 PVR_UNREFERENCED_PARAMETER(psPerProc);
2745 3451
2746#if defined(DEBUG_BRIDGE_KM) 3452#if defined(DEBUG_BRIDGE_KM)
2747 PVR_DPF((PVR_DBG_ERROR, "%s: BRIDGE ERROR: BridgeID %u (%s) mapped to " 3453 PVR_DPF((PVR_DBG_ERROR, "%s: BRIDGE ERROR: BridgeID %u (%s) mapped to "
2748 "Dummy Wrapper (probably not what you want!)", 3454 "Dummy Wrapper (probably not what you want!)",
2749 __FUNCTION__, ui32BridgeID, g_BridgeDispatchTable[ui32BridgeID].pszIOCName)); 3455 __FUNCTION__, ui32BridgeID, g_BridgeDispatchTable[ui32BridgeID].pszIOCName));
2750#else 3456#else
2751 PVR_DPF((PVR_DBG_ERROR, "%s: BRIDGE ERROR: BridgeID %u mapped to " 3457 PVR_DPF((PVR_DBG_ERROR, "%s: BRIDGE ERROR: BridgeID %u mapped to "
2752 "Dummy Wrapper (probably not what you want!)", 3458 "Dummy Wrapper (probably not what you want!)",
2753 __FUNCTION__, ui32BridgeID)); 3459 __FUNCTION__, ui32BridgeID));
2754#endif 3460#endif
2755 return -ENOTTY; 3461 return -ENOTTY;
2756} 3462}
2757 3463
2758 3464
2759IMG_VOID 3465IMG_VOID
2760_SetDispatchTableEntry(IMG_UINT32 ui32Index, 3466_SetDispatchTableEntry(IMG_UINT32 ui32Index,
2761 const IMG_CHAR *pszIOCName, 3467 const IMG_CHAR *pszIOCName,
2762 BridgeWrapperFunction pfFunction, 3468 BridgeWrapperFunction pfFunction,
2763 const IMG_CHAR *pszFunctionName) 3469 const IMG_CHAR *pszFunctionName)
2764{ 3470{
2765 static IMG_UINT32 ui32PrevIndex = ~0UL; 3471 static IMG_UINT32 ui32PrevIndex = ~0UL;
2766#if !defined(DEBUG) 3472#if !defined(DEBUG)
2767 PVR_UNREFERENCED_PARAMETER(pszIOCName); 3473 PVR_UNREFERENCED_PARAMETER(pszIOCName);
2768#endif 3474#endif
2769#if !defined(DEBUG_BRIDGE_KM_DISPATCH_TABLE) && !defined(DEBUG_BRIDGE_KM) 3475#if !defined(DEBUG_BRIDGE_KM_DISPATCH_TABLE) && !defined(DEBUG_BRIDGE_KM)
2770 PVR_UNREFERENCED_PARAMETER(pszFunctionName); 3476 PVR_UNREFERENCED_PARAMETER(pszFunctionName);
2771#endif 3477#endif
2772 3478
2773#if defined(DEBUG_BRIDGE_KM_DISPATCH_TABLE) 3479#if defined(DEBUG_BRIDGE_KM_DISPATCH_TABLE)
2774 3480
2775 PVR_DPF((PVR_DBG_WARNING, "%s: %d %s %s", __FUNCTION__, ui32Index, pszIOCName, pszFunctionName)); 3481 PVR_DPF((PVR_DBG_WARNING, "%s: %d %s %s", __FUNCTION__, ui32Index, pszIOCName, pszFunctionName));
2776#endif 3482#endif
2777 3483
2778 3484
2779 if(g_BridgeDispatchTable[ui32Index].pfFunction) 3485 if(g_BridgeDispatchTable[ui32Index].pfFunction)
2780 { 3486 {
2781#if defined(DEBUG_BRIDGE_KM) 3487#if defined(DEBUG_BRIDGE_KM)
2782 PVR_DPF((PVR_DBG_ERROR, 3488 PVR_DPF((PVR_DBG_ERROR,
2783 "%s: BUG!: Adding dispatch table entry for %s clobbers an existing entry for %s", 3489 "%s: BUG!: Adding dispatch table entry for %s clobbers an existing entry for %s",
2784 __FUNCTION__, pszIOCName, g_BridgeDispatchTable[ui32Index].pszIOCName)); 3490 __FUNCTION__, pszIOCName, g_BridgeDispatchTable[ui32Index].pszIOCName));
2785#else 3491#else
2786 PVR_DPF((PVR_DBG_ERROR, 3492 PVR_DPF((PVR_DBG_ERROR,
2787 "%s: BUG!: Adding dispatch table entry for %s clobbers an existing entry (index=%u)", 3493 "%s: BUG!: Adding dispatch table entry for %s clobbers an existing entry (index=%u)",
2788 __FUNCTION__, pszIOCName, ui32Index)); 3494 __FUNCTION__, pszIOCName, ui32Index));
2789#endif 3495#endif
2790 PVR_DPF((PVR_DBG_ERROR, "NOTE: Enabling DEBUG_BRIDGE_KM_DISPATCH_TABLE may help debug this issue.")); 3496 PVR_DPF((PVR_DBG_ERROR, "NOTE: Enabling DEBUG_BRIDGE_KM_DISPATCH_TABLE may help debug this issue."));
2791 } 3497 }
2792 3498
2793 3499
2794 if((ui32PrevIndex != ~0UL) && 3500 if((ui32PrevIndex != ~0UL) &&
2795 ((ui32Index >= ui32PrevIndex + DISPATCH_TABLE_GAP_THRESHOLD) || 3501 ((ui32Index >= ui32PrevIndex + DISPATCH_TABLE_GAP_THRESHOLD) ||
2796 (ui32Index <= ui32PrevIndex))) 3502 (ui32Index <= ui32PrevIndex)))
2797 { 3503 {
2798#if defined(DEBUG_BRIDGE_KM) 3504#if defined(DEBUG_BRIDGE_KM)
2799 PVR_DPF((PVR_DBG_WARNING, 3505 PVR_DPF((PVR_DBG_WARNING,
2800 "%s: There is a gap in the dispatch table between indices %u (%s) and %u (%s)", 3506 "%s: There is a gap in the dispatch table between indices %u (%s) and %u (%s)",
2801 __FUNCTION__, ui32PrevIndex, g_BridgeDispatchTable[ui32PrevIndex].pszIOCName, 3507 __FUNCTION__, ui32PrevIndex, g_BridgeDispatchTable[ui32PrevIndex].pszIOCName,
2802 ui32Index, pszIOCName)); 3508 ui32Index, pszIOCName));
2803#else 3509#else
2804 PVR_DPF((PVR_DBG_WARNING, 3510 PVR_DPF((PVR_DBG_WARNING,
2805 "%s: There is a gap in the dispatch table between indices %u and %u (%s)", 3511 "%s: There is a gap in the dispatch table between indices %u and %u (%s)",
2806 __FUNCTION__, (IMG_UINT)ui32PrevIndex, (IMG_UINT)ui32Index, pszIOCName)); 3512 __FUNCTION__, (IMG_UINT)ui32PrevIndex, (IMG_UINT)ui32Index, pszIOCName));
2807#endif 3513#endif
2808 PVR_DPF((PVR_DBG_ERROR, "NOTE: Enabling DEBUG_BRIDGE_KM_DISPATCH_TABLE may help debug this issue.")); 3514 PVR_DPF((PVR_DBG_ERROR, "NOTE: Enabling DEBUG_BRIDGE_KM_DISPATCH_TABLE may help debug this issue."));
2809 } 3515 }
2810 3516
2811 g_BridgeDispatchTable[ui32Index].pfFunction = pfFunction; 3517 g_BridgeDispatchTable[ui32Index].pfFunction = pfFunction;
2812#if defined(DEBUG_BRIDGE_KM) 3518#if defined(DEBUG_BRIDGE_KM)
2813 g_BridgeDispatchTable[ui32Index].pszIOCName = pszIOCName; 3519 g_BridgeDispatchTable[ui32Index].pszIOCName = pszIOCName;
2814 g_BridgeDispatchTable[ui32Index].pszFunctionName = pszFunctionName; 3520 g_BridgeDispatchTable[ui32Index].pszFunctionName = pszFunctionName;
2815 g_BridgeDispatchTable[ui32Index].ui32CallCount = 0; 3521 g_BridgeDispatchTable[ui32Index].ui32CallCount = 0;
2816 g_BridgeDispatchTable[ui32Index].ui32CopyFromUserTotalBytes = 0; 3522 g_BridgeDispatchTable[ui32Index].ui32CopyFromUserTotalBytes = 0;
2817#endif 3523#endif
2818 3524
2819 ui32PrevIndex = ui32Index; 3525 ui32PrevIndex = ui32Index;
2820} 3526}
2821 3527
2822static IMG_INT 3528static IMG_INT
2823PVRSRVInitSrvConnectBW(IMG_UINT32 ui32BridgeID, 3529PVRSRVInitSrvConnectBW(IMG_UINT32 ui32BridgeID,
2824 IMG_VOID *psBridgeIn, 3530 IMG_VOID *psBridgeIn,
2825 PVRSRV_BRIDGE_RETURN *psRetOUT, 3531 PVRSRV_BRIDGE_RETURN *psRetOUT,
2826 PVRSRV_PER_PROCESS_DATA *psPerProc) 3532 PVRSRV_PER_PROCESS_DATA *psPerProc)
2827{ 3533{
2828 PVR_UNREFERENCED_PARAMETER(psBridgeIn); 3534 PVR_UNREFERENCED_PARAMETER(psBridgeIn);
2829
2830 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_INITSRV_CONNECT);
2831 PVR_UNREFERENCED_PARAMETER(psBridgeIn);
2832 3535
3536 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_INITSRV_CONNECT);
3537 PVR_UNREFERENCED_PARAMETER(psBridgeIn);
2833 3538
2834 if((OSProcHasPrivSrvInit() == IMG_FALSE) || PVRSRVGetInitServerState(PVRSRV_INIT_SERVER_RUNNING) || PVRSRVGetInitServerState(PVRSRV_INIT_SERVER_RAN)) 3539
2835 { 3540 if((OSProcHasPrivSrvInit() == IMG_FALSE) || PVRSRVGetInitServerState(PVRSRV_INIT_SERVER_RUNNING) || PVRSRVGetInitServerState(PVRSRV_INIT_SERVER_RAN))
2836 psRetOUT->eError = PVRSRV_ERROR_SRV_CONNECT_FAILED; 3541 {
2837 return 0; 3542 psRetOUT->eError = PVRSRV_ERROR_SRV_CONNECT_FAILED;
2838 } 3543 return 0;
3544 }
2839 3545
2840#if defined (__linux__) 3546#if defined (__linux__)
2841 PVRSRVSetInitServerState(PVRSRV_INIT_SERVER_RUNNING, IMG_TRUE); 3547 PVRSRVSetInitServerState(PVRSRV_INIT_SERVER_RUNNING, IMG_TRUE);
2842#endif 3548#endif
2843 psPerProc->bInitProcess = IMG_TRUE; 3549 psPerProc->bInitProcess = IMG_TRUE;
2844 3550
2845 psRetOUT->eError = PVRSRV_OK; 3551 psRetOUT->eError = PVRSRV_OK;
2846 3552
2847 return 0; 3553 return 0;
2848} 3554}
2849 3555
2850 3556
2851static IMG_INT 3557static IMG_INT
2852PVRSRVInitSrvDisconnectBW(IMG_UINT32 ui32BridgeID, 3558PVRSRVInitSrvDisconnectBW(IMG_UINT32 ui32BridgeID,
2853 PVRSRV_BRIDGE_IN_INITSRV_DISCONNECT *psInitSrvDisconnectIN, 3559 PVRSRV_BRIDGE_IN_INITSRV_DISCONNECT *psInitSrvDisconnectIN,
2854 PVRSRV_BRIDGE_RETURN *psRetOUT, 3560 PVRSRV_BRIDGE_RETURN *psRetOUT,
2855 PVRSRV_PER_PROCESS_DATA *psPerProc) 3561 PVRSRV_PER_PROCESS_DATA *psPerProc)
2856{ 3562{
2857 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_INITSRV_DISCONNECT); 3563 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_INITSRV_DISCONNECT);
2858 3564
2859 if(!psPerProc->bInitProcess) 3565 if(!psPerProc->bInitProcess)
2860 { 3566 {
2861 psRetOUT->eError = PVRSRV_ERROR_SRV_DISCONNECT_FAILED; 3567 psRetOUT->eError = PVRSRV_ERROR_SRV_DISCONNECT_FAILED;
2862 return 0; 3568 return 0;
2863 } 3569 }
2864 3570
2865 psPerProc->bInitProcess = IMG_FALSE; 3571 psPerProc->bInitProcess = IMG_FALSE;
2866 3572
2867 PVRSRVSetInitServerState(PVRSRV_INIT_SERVER_RUNNING, IMG_FALSE); 3573 PVRSRVSetInitServerState(PVRSRV_INIT_SERVER_RUNNING, IMG_FALSE);
2868 PVRSRVSetInitServerState(PVRSRV_INIT_SERVER_RAN, IMG_TRUE); 3574 PVRSRVSetInitServerState(PVRSRV_INIT_SERVER_RAN, IMG_TRUE);
2869 3575
2870 psRetOUT->eError = PVRSRVFinaliseSystem(psInitSrvDisconnectIN->bInitSuccesful); 3576 psRetOUT->eError = PVRSRVFinaliseSystem(psInitSrvDisconnectIN->bInitSuccesful);
2871 3577
2872 PVRSRVSetInitServerState( PVRSRV_INIT_SERVER_SUCCESSFUL , 3578 PVRSRVSetInitServerState( PVRSRV_INIT_SERVER_SUCCESSFUL ,
2873 ((psRetOUT->eError == PVRSRV_OK) && (psInitSrvDisconnectIN->bInitSuccesful)) 3579 ((psRetOUT->eError == PVRSRV_OK) && (psInitSrvDisconnectIN->bInitSuccesful))
2874 ? IMG_TRUE : IMG_FALSE); 3580 ? IMG_TRUE : IMG_FALSE);
2875 3581
2876 return 0; 3582 return 0;
2877} 3583}
2878 3584
2879 3585
2880static IMG_INT 3586static IMG_INT
2881PVRSRVEventObjectWaitBW(IMG_UINT32 ui32BridgeID, 3587PVRSRVEventObjectWaitBW(IMG_UINT32 ui32BridgeID,
2882 PVRSRV_BRIDGE_IN_EVENT_OBJECT_WAIT *psEventObjectWaitIN, 3588 PVRSRV_BRIDGE_IN_EVENT_OBJECT_WAIT *psEventObjectWaitIN,
2883 PVRSRV_BRIDGE_RETURN *psRetOUT, 3589 PVRSRV_BRIDGE_RETURN *psRetOUT,
2884 PVRSRV_PER_PROCESS_DATA *psPerProc) 3590 PVRSRV_PER_PROCESS_DATA *psPerProc)
2885{ 3591{
2886 IMG_HANDLE hOSEventKM; 3592 IMG_HANDLE hOSEventKM;
2887 3593
2888 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_EVENT_OBJECT_WAIT); 3594 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_EVENT_OBJECT_WAIT);
2889 3595
2890 psRetOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 3596 psRetOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
2891 &hOSEventKM, 3597 &hOSEventKM,
2892 psEventObjectWaitIN->hOSEventKM, 3598 psEventObjectWaitIN->hOSEventKM,
2893 PVRSRV_HANDLE_TYPE_EVENT_OBJECT_CONNECT); 3599 PVRSRV_HANDLE_TYPE_EVENT_OBJECT_CONNECT);
2894 3600
2895 if(psRetOUT->eError != PVRSRV_OK) 3601 if(psRetOUT->eError != PVRSRV_OK)
2896 { 3602 {
2897 return 0; 3603 return 0;
2898 } 3604 }
2899 3605
2900 psRetOUT->eError = OSEventObjectWait(hOSEventKM); 3606 psRetOUT->eError = OSEventObjectWaitKM(hOSEventKM);
2901 3607
2902 return 0; 3608 return 0;
2903} 3609}
2904 3610
2905 3611
2906static IMG_INT 3612static IMG_INT
2907PVRSRVEventObjectOpenBW(IMG_UINT32 ui32BridgeID, 3613PVRSRVEventObjectOpenBW(IMG_UINT32 ui32BridgeID,
2908 PVRSRV_BRIDGE_IN_EVENT_OBJECT_OPEN *psEventObjectOpenIN, 3614 PVRSRV_BRIDGE_IN_EVENT_OBJECT_OPEN *psEventObjectOpenIN,
2909 PVRSRV_BRIDGE_OUT_EVENT_OBJECT_OPEN *psEventObjectOpenOUT, 3615 PVRSRV_BRIDGE_OUT_EVENT_OBJECT_OPEN *psEventObjectOpenOUT,
2910 PVRSRV_PER_PROCESS_DATA *psPerProc) 3616 PVRSRV_PER_PROCESS_DATA *psPerProc)
2911{ 3617{
3618#if defined (SUPPORT_SID_INTERFACE)
3619 PVRSRV_EVENTOBJECT_KM sEventObject;
3620 IMG_HANDLE hOSEvent;
3621#endif
2912 3622
2913 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_EVENT_OBJECT_OPEN); 3623 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_EVENT_OBJECT_OPEN);
2914 3624
2915 NEW_HANDLE_BATCH_OR_ERROR(psEventObjectOpenOUT->eError, psPerProc, 1) 3625 NEW_HANDLE_BATCH_OR_ERROR(psEventObjectOpenOUT->eError, psPerProc, 1)
2916 3626
2917 psEventObjectOpenOUT->eError = 3627 psEventObjectOpenOUT->eError =
2918 PVRSRVLookupHandle(psPerProc->psHandleBase, 3628 PVRSRVLookupHandle(psPerProc->psHandleBase,
2919 &psEventObjectOpenIN->sEventObject.hOSEventKM, 3629#if defined (SUPPORT_SID_INTERFACE)
2920 psEventObjectOpenIN->sEventObject.hOSEventKM, 3630 &sEventObject.hOSEventKM,
2921 PVRSRV_HANDLE_TYPE_SHARED_EVENT_OBJECT); 3631#else
3632 &psEventObjectOpenIN->sEventObject.hOSEventKM,
3633#endif
3634 psEventObjectOpenIN->sEventObject.hOSEventKM,
3635 PVRSRV_HANDLE_TYPE_SHARED_EVENT_OBJECT);
2922 3636
2923 if(psEventObjectOpenOUT->eError != PVRSRV_OK) 3637 if(psEventObjectOpenOUT->eError != PVRSRV_OK)
2924 { 3638 {
2925 return 0; 3639 return 0;
2926 } 3640 }
2927 3641
2928 psEventObjectOpenOUT->eError = OSEventObjectOpen(&psEventObjectOpenIN->sEventObject, &psEventObjectOpenOUT->hOSEvent); 3642#if defined (SUPPORT_SID_INTERFACE)
3643 OSMemCopy(&sEventObject.szName,
3644 &psEventObjectOpenIN->sEventObject.szName,
3645 EVENTOBJNAME_MAXLENGTH);
2929 3646
2930 if(psEventObjectOpenOUT->eError != PVRSRV_OK) 3647 psEventObjectOpenOUT->eError = OSEventObjectOpenKM(&sEventObject, &hOSEvent);
2931 { 3648#else
2932 return 0; 3649 psEventObjectOpenOUT->eError = OSEventObjectOpenKM(&psEventObjectOpenIN->sEventObject, &psEventObjectOpenOUT->hOSEvent);
2933 } 3650#endif
2934 3651
2935 PVRSRVAllocHandleNR(psPerProc->psHandleBase, 3652 if(psEventObjectOpenOUT->eError != PVRSRV_OK)
2936 &psEventObjectOpenOUT->hOSEvent, 3653 {
2937 psEventObjectOpenOUT->hOSEvent, 3654 return 0;
2938 PVRSRV_HANDLE_TYPE_EVENT_OBJECT_CONNECT, 3655 }
2939 PVRSRV_HANDLE_ALLOC_FLAG_MULTI); 3656
3657#if defined (SUPPORT_SID_INTERFACE)
3658#if !defined (WINXP) && !defined(SUPPORT_VISTA)
3659 PVRSRVAllocHandleNR(psPerProc->psHandleBase,
3660 &psEventObjectOpenOUT->hOSEvent,
3661 hOSEvent,
3662 PVRSRV_HANDLE_TYPE_EVENT_OBJECT_CONNECT,
3663 PVRSRV_HANDLE_ALLOC_FLAG_MULTI);
3664#endif
3665#else
3666 PVRSRVAllocHandleNR(psPerProc->psHandleBase,
3667 &psEventObjectOpenOUT->hOSEvent,
3668 psEventObjectOpenOUT->hOSEvent,
3669 PVRSRV_HANDLE_TYPE_EVENT_OBJECT_CONNECT,
3670 PVRSRV_HANDLE_ALLOC_FLAG_MULTI);
3671#endif
2940 3672
2941 COMMIT_HANDLE_BATCH_OR_ERROR(psEventObjectOpenOUT->eError, psPerProc) 3673 COMMIT_HANDLE_BATCH_OR_ERROR(psEventObjectOpenOUT->eError, psPerProc)
2942 3674
2943 return 0; 3675 return 0;
2944} 3676}
2945 3677
2946 3678
2947static IMG_INT 3679static IMG_INT
2948PVRSRVEventObjectCloseBW(IMG_UINT32 ui32BridgeID, 3680PVRSRVEventObjectCloseBW(IMG_UINT32 ui32BridgeID,
2949 PVRSRV_BRIDGE_IN_EVENT_OBJECT_CLOSE *psEventObjectCloseIN, 3681 PVRSRV_BRIDGE_IN_EVENT_OBJECT_CLOSE *psEventObjectCloseIN,
2950 PVRSRV_BRIDGE_RETURN *psRetOUT, 3682 PVRSRV_BRIDGE_RETURN *psRetOUT,
2951 PVRSRV_PER_PROCESS_DATA *psPerProc) 3683 PVRSRV_PER_PROCESS_DATA *psPerProc)
2952{ 3684{
2953 IMG_HANDLE hOSEventKM; 3685 IMG_HANDLE hOSEventKM;
2954 3686#if defined (SUPPORT_SID_INTERFACE)
2955 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_EVENT_OBJECT_CLOSE); 3687 PVRSRV_EVENTOBJECT_KM sEventObject;
2956 3688#endif
2957 psRetOUT->eError =
2958 PVRSRVLookupHandle(psPerProc->psHandleBase,
2959 &psEventObjectCloseIN->sEventObject.hOSEventKM,
2960 psEventObjectCloseIN->sEventObject.hOSEventKM,
2961 PVRSRV_HANDLE_TYPE_SHARED_EVENT_OBJECT);
2962 if(psRetOUT->eError != PVRSRV_OK)
2963 {
2964 return 0;
2965 }
2966
2967 psRetOUT->eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
2968 &hOSEventKM,
2969 psEventObjectCloseIN->hOSEventKM,
2970 PVRSRV_HANDLE_TYPE_EVENT_OBJECT_CONNECT);
2971 3689
2972 if(psRetOUT->eError != PVRSRV_OK) 3690 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_EVENT_OBJECT_CLOSE);
2973 {
2974 return 0;
2975 }
2976 3691
2977 psRetOUT->eError = OSEventObjectClose(&psEventObjectCloseIN->sEventObject, hOSEventKM); 3692 psRetOUT->eError =
3693 PVRSRVLookupHandle(psPerProc->psHandleBase,
3694#if defined (SUPPORT_SID_INTERFACE)
3695 &sEventObject.hOSEventKM,
3696#else
3697 &psEventObjectCloseIN->sEventObject.hOSEventKM,
3698#endif
3699 psEventObjectCloseIN->sEventObject.hOSEventKM,
3700 PVRSRV_HANDLE_TYPE_SHARED_EVENT_OBJECT);
3701 if(psRetOUT->eError != PVRSRV_OK)
3702 {
3703 return 0;
3704 }
3705
3706 psRetOUT->eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
3707 &hOSEventKM,
3708 psEventObjectCloseIN->hOSEventKM,
3709 PVRSRV_HANDLE_TYPE_EVENT_OBJECT_CONNECT);
3710
3711 if(psRetOUT->eError != PVRSRV_OK)
3712 {
3713 return 0;
3714 }
3715
3716#if defined (SUPPORT_SID_INTERFACE)
3717 if(CopyFromUserWrapper(psPerProc, ui32BridgeID,
3718 &sEventObject.szName,
3719 &psEventObjectCloseIN->sEventObject.szName,
3720 EVENTOBJNAME_MAXLENGTH) != PVRSRV_OK)
3721 {
3722
3723 return -EFAULT;
3724 }
3725
3726 psRetOUT->eError = OSEventObjectCloseKM(&sEventObject, hOSEventKM);
3727#else
3728 psRetOUT->eError = OSEventObjectCloseKM(&psEventObjectCloseIN->sEventObject, hOSEventKM);
3729#endif
2978 3730
2979 return 0; 3731 return 0;
2980} 3732}
2981 3733
2982 3734
2983typedef struct _MODIFY_SYNC_OP_INFO 3735typedef struct _MODIFY_SYNC_OP_INFO
2984{ 3736{
2985 IMG_HANDLE hResItem; 3737 IMG_HANDLE hResItem;
2986 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo; 3738 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo;
2987 IMG_UINT32 ui32ModifyFlags; 3739 IMG_UINT32 ui32ModifyFlags;
2988 IMG_UINT32 ui32ReadOpsPendingSnapShot; 3740 IMG_UINT32 ui32ReadOpsPendingSnapShot;
2989 IMG_UINT32 ui32WriteOpsPendingSnapShot; 3741 IMG_UINT32 ui32WriteOpsPendingSnapShot;
2990} MODIFY_SYNC_OP_INFO; 3742} MODIFY_SYNC_OP_INFO;
2991 3743
2992 3744
2993static PVRSRV_ERROR DoQuerySyncOpsSatisfied(MODIFY_SYNC_OP_INFO *psModSyncOpInfo) 3745static PVRSRV_ERROR DoQuerySyncOpsSatisfied(PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo,
3746 IMG_UINT32 ui32ReadOpsPendingSnapShot,
3747 IMG_UINT32 ui32WriteOpsPendingSnapShot)
2994{ 3748{
2995 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo; 3749 IMG_UINT32 ui32WriteOpsPending;
3750 IMG_UINT32 ui32ReadOpsPending;
2996 3751
2997 psKernelSyncInfo = psModSyncOpInfo->psKernelSyncInfo; 3752
3753 if (!psKernelSyncInfo)
3754 {
3755 return PVRSRV_ERROR_INVALID_PARAMS;
3756 }
2998 3757
2999 if (!psKernelSyncInfo) 3758
3000 {
3001 return PVRSRV_ERROR_INVALID_PARAMS;
3002 }
3003 3759
3004 if((psModSyncOpInfo->ui32WriteOpsPendingSnapShot == psKernelSyncInfo->psSyncData->ui32WriteOpsComplete)
3005 && (psModSyncOpInfo->ui32ReadOpsPendingSnapShot == psKernelSyncInfo->psSyncData->ui32ReadOpsComplete))
3006 {
3007#if defined(PDUMP)
3008 3760
3009 3761
3010 3762
3011 PDumpComment("Poll for read ops complete to reach value (%u)", psModSyncOpInfo->ui32ReadOpsPendingSnapShot);
3012 PDumpMemPolKM(psKernelSyncInfo->psSyncDataMemInfoKM,
3013 offsetof(PVRSRV_SYNC_DATA, ui32ReadOpsComplete),
3014 psModSyncOpInfo->ui32ReadOpsPendingSnapShot,
3015 0xFFFFFFFF,
3016 PDUMP_POLL_OPERATOR_EQUAL,
3017 0,
3018 MAKEUNIQUETAG(psKernelSyncInfo->psSyncDataMemInfoKM));
3019 3763
3020 3764
3021 PDumpComment("Poll for write ops complete to reach value (%u)", psModSyncOpInfo->ui32WriteOpsPendingSnapShot);
3022 PDumpMemPolKM(psKernelSyncInfo->psSyncDataMemInfoKM,
3023 offsetof(PVRSRV_SYNC_DATA, ui32WriteOpsComplete),
3024 psModSyncOpInfo->ui32WriteOpsPendingSnapShot,
3025 0xFFFFFFFF,
3026 PDUMP_POLL_OPERATOR_EQUAL,
3027 0,
3028 MAKEUNIQUETAG(psKernelSyncInfo->psSyncDataMemInfoKM));
3029#endif
3030 return PVRSRV_OK;
3031 }
3032 else
3033 {
3034 return PVRSRV_ERROR_RETRY;
3035 }
3036}
3037
3038static PVRSRV_ERROR DoModifyCompleteSyncOps(MODIFY_SYNC_OP_INFO *psModSyncOpInfo)
3039{
3040 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo;
3041 3765
3042 psKernelSyncInfo = psModSyncOpInfo->psKernelSyncInfo;
3043
3044 if (!psKernelSyncInfo)
3045 {
3046 return PVRSRV_ERROR_INVALID_PARAMS;
3047 }
3048
3049
3050 if((psModSyncOpInfo->ui32WriteOpsPendingSnapShot != psKernelSyncInfo->psSyncData->ui32WriteOpsComplete)
3051 || (psModSyncOpInfo->ui32ReadOpsPendingSnapShot != psKernelSyncInfo->psSyncData->ui32ReadOpsComplete))
3052 {
3053 return PVRSRV_ERROR_BAD_SYNC_STATE;
3054 }
3055 3766
3056 3767
3057 if(psModSyncOpInfo->ui32ModifyFlags & PVRSRV_MODIFYSYNCOPS_FLAGS_WO_INC) 3768 ui32WriteOpsPending = psKernelSyncInfo->psSyncData->ui32WriteOpsPending;
3058 { 3769 ui32ReadOpsPending = psKernelSyncInfo->psSyncData->ui32ReadOpsPending;
3059 psKernelSyncInfo->psSyncData->ui32WriteOpsComplete++;
3060 }
3061 3770
3771 if((ui32WriteOpsPending - ui32WriteOpsPendingSnapShot >=
3772 ui32WriteOpsPending - psKernelSyncInfo->psSyncData->ui32WriteOpsComplete) &&
3773 (ui32ReadOpsPending - ui32ReadOpsPendingSnapShot >=
3774 ui32ReadOpsPending - psKernelSyncInfo->psSyncData->ui32ReadOpsComplete))
3775 {
3776#if defined(PDUMP) && !defined(SUPPORT_VGX)
3777
3778 PDumpComment("Poll for read ops complete to reach value (pdump: %u, actual snapshot: %u)",
3779 psKernelSyncInfo->psSyncData->ui32LastReadOpDumpVal,
3780 ui32ReadOpsPendingSnapShot);
3781 PDumpMemPolKM(psKernelSyncInfo->psSyncDataMemInfoKM,
3782 offsetof(PVRSRV_SYNC_DATA, ui32ReadOpsComplete),
3783 psKernelSyncInfo->psSyncData->ui32LastReadOpDumpVal,
3784 0xFFFFFFFF,
3785 PDUMP_POLL_OPERATOR_EQUAL,
3786 0,
3787 MAKEUNIQUETAG(psKernelSyncInfo->psSyncDataMemInfoKM));
3062 3788
3063 if(psModSyncOpInfo->ui32ModifyFlags & PVRSRV_MODIFYSYNCOPS_FLAGS_RO_INC) 3789
3064 { 3790 PDumpComment("Poll for write ops complete to reach value (pdump: %u, actual snapshot: %u)",
3065 psKernelSyncInfo->psSyncData->ui32ReadOpsComplete++; 3791 psKernelSyncInfo->psSyncData->ui32LastOpDumpVal,
3066 } 3792 ui32WriteOpsPendingSnapShot);
3793 PDumpMemPolKM(psKernelSyncInfo->psSyncDataMemInfoKM,
3794 offsetof(PVRSRV_SYNC_DATA, ui32WriteOpsComplete),
3795 psKernelSyncInfo->psSyncData->ui32LastOpDumpVal,
3796 0xFFFFFFFF,
3797 PDUMP_POLL_OPERATOR_EQUAL,
3798 0,
3799 MAKEUNIQUETAG(psKernelSyncInfo->psSyncDataMemInfoKM));
3800
3067 3801
3068 return PVRSRV_OK; 3802#endif
3803 return PVRSRV_OK;
3804 }
3805 else
3806 {
3807 return PVRSRV_ERROR_RETRY;
3808 }
3069} 3809}
3070 3810
3071 3811
3072static PVRSRV_ERROR ModifyCompleteSyncOpsCallBack(IMG_PVOID pvParam, 3812static PVRSRV_ERROR DoModifyCompleteSyncOps(MODIFY_SYNC_OP_INFO *psModSyncOpInfo)
3073 IMG_UINT32 ui32Param)
3074{ 3813{
3075 MODIFY_SYNC_OP_INFO *psModSyncOpInfo; 3814 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo;
3076 3815
3077 PVR_UNREFERENCED_PARAMETER(ui32Param); 3816 psKernelSyncInfo = psModSyncOpInfo->psKernelSyncInfo;
3078 3817
3079 if (!pvParam) 3818 if (!psKernelSyncInfo)
3080 { 3819 {
3081 PVR_DPF((PVR_DBG_ERROR, "ModifyCompleteSyncOpsCallBack: invalid parameter")); 3820 return PVRSRV_ERROR_INVALID_PARAMS;
3082 return PVRSRV_ERROR_INVALID_PARAMS; 3821 }
3083 } 3822
3084 3823
3085 psModSyncOpInfo = (MODIFY_SYNC_OP_INFO*)pvParam; 3824 if((psModSyncOpInfo->ui32WriteOpsPendingSnapShot != psKernelSyncInfo->psSyncData->ui32WriteOpsComplete)
3086 3825 || (psModSyncOpInfo->ui32ReadOpsPendingSnapShot != psKernelSyncInfo->psSyncData->ui32ReadOpsComplete))
3087 if (psModSyncOpInfo->psKernelSyncInfo) 3826 {
3088 { 3827 return PVRSRV_ERROR_BAD_SYNC_STATE;
3089 3828 }
3090 LOOP_UNTIL_TIMEOUT(MAX_HW_TIME_US) 3829
3091 { 3830
3092 if (DoQuerySyncOpsSatisfied(psModSyncOpInfo) == PVRSRV_OK) 3831 if(psModSyncOpInfo->ui32ModifyFlags & PVRSRV_MODIFYSYNCOPS_FLAGS_WO_INC)
3093 { 3832 {
3094 goto OpFlushedComplete; 3833 psKernelSyncInfo->psSyncData->ui32WriteOpsComplete++;
3095 } 3834 }
3096 PVR_DPF((PVR_DBG_WARNING, "ModifyCompleteSyncOpsCallBack: waiting for current Ops to flush")); 3835
3097 OSSleepms(1); 3836
3098 } END_LOOP_UNTIL_TIMEOUT(); 3837 if(psModSyncOpInfo->ui32ModifyFlags & PVRSRV_MODIFYSYNCOPS_FLAGS_RO_INC)
3099 3838 {
3100 PVR_DPF((PVR_DBG_ERROR, "ModifyCompleteSyncOpsCallBack: timeout whilst waiting for current Ops to flush.")); 3839 psKernelSyncInfo->psSyncData->ui32ReadOpsComplete++;
3101 PVR_DPF((PVR_DBG_ERROR, " Write ops pending snapshot = %d, write ops complete = %d", 3840 }
3102 psModSyncOpInfo->ui32WriteOpsPendingSnapShot, 3841
3103 psModSyncOpInfo->psKernelSyncInfo->psSyncData->ui32WriteOpsComplete)); 3842 return PVRSRV_OK;
3104 PVR_DPF((PVR_DBG_ERROR, " Read ops pending snapshot = %d, write ops complete = %d", 3843}
3105 psModSyncOpInfo->ui32ReadOpsPendingSnapShot,
3106 psModSyncOpInfo->psKernelSyncInfo->psSyncData->ui32ReadOpsComplete));
3107
3108 return PVRSRV_ERROR_TIMEOUT;
3109
3110 OpFlushedComplete:
3111
3112 DoModifyCompleteSyncOps(psModSyncOpInfo);
3113 }
3114
3115 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(MODIFY_SYNC_OP_INFO), (IMG_VOID *)psModSyncOpInfo, 0);
3116
3117
3118 3844
3119 PVRSRVScheduleDeviceCallbacks();
3120 3845
3121 return PVRSRV_OK; 3846static PVRSRV_ERROR ModifyCompleteSyncOpsCallBack(IMG_PVOID pvParam,
3847 IMG_UINT32 ui32Param)
3848{
3849 MODIFY_SYNC_OP_INFO *psModSyncOpInfo;
3850
3851 PVR_UNREFERENCED_PARAMETER(ui32Param);
3852
3853 if (!pvParam)
3854 {
3855 PVR_DPF((PVR_DBG_ERROR, "ModifyCompleteSyncOpsCallBack: invalid parameter"));
3856 return PVRSRV_ERROR_INVALID_PARAMS;
3857 }
3858
3859 psModSyncOpInfo = (MODIFY_SYNC_OP_INFO*)pvParam;
3860
3861 if (psModSyncOpInfo->psKernelSyncInfo)
3862 {
3863
3864 LOOP_UNTIL_TIMEOUT(MAX_HW_TIME_US)
3865 {
3866 if (DoQuerySyncOpsSatisfied(psModSyncOpInfo->psKernelSyncInfo,
3867 psModSyncOpInfo->ui32ReadOpsPendingSnapShot,
3868 psModSyncOpInfo->ui32WriteOpsPendingSnapShot) == PVRSRV_OK)
3869 {
3870 goto OpFlushedComplete;
3871 }
3872 PVR_DPF((PVR_DBG_WARNING, "ModifyCompleteSyncOpsCallBack: waiting for current Ops to flush"));
3873 OSSleepms(1);
3874 } END_LOOP_UNTIL_TIMEOUT();
3875
3876 PVR_DPF((PVR_DBG_ERROR, "ModifyCompleteSyncOpsCallBack: timeout whilst waiting for current Ops to flush."));
3877 PVR_DPF((PVR_DBG_ERROR, " Write ops pending snapshot = %d, write ops complete = %d",
3878 psModSyncOpInfo->ui32WriteOpsPendingSnapShot,
3879 psModSyncOpInfo->psKernelSyncInfo->psSyncData->ui32WriteOpsComplete));
3880 PVR_DPF((PVR_DBG_ERROR, " Read ops pending snapshot = %d, write ops complete = %d",
3881 psModSyncOpInfo->ui32ReadOpsPendingSnapShot,
3882 psModSyncOpInfo->psKernelSyncInfo->psSyncData->ui32ReadOpsComplete));
3883
3884 return PVRSRV_ERROR_TIMEOUT;
3885
3886 OpFlushedComplete:
3887
3888 DoModifyCompleteSyncOps(psModSyncOpInfo);
3889 }
3890
3891 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(MODIFY_SYNC_OP_INFO), (IMG_VOID *)psModSyncOpInfo, 0);
3892
3893
3894
3895 PVRSRVScheduleDeviceCallbacks();
3896
3897 return PVRSRV_OK;
3122} 3898}
3123 3899
3124 3900
3125static IMG_INT 3901static IMG_INT
3126PVRSRVCreateSyncInfoModObjBW(IMG_UINT32 ui32BridgeID, 3902PVRSRVCreateSyncInfoModObjBW(IMG_UINT32 ui32BridgeID,
3127 IMG_VOID *psBridgeIn, 3903 IMG_VOID *psBridgeIn,
3128 PVRSRV_BRIDGE_OUT_CREATE_SYNC_INFO_MOD_OBJ *psCreateSyncInfoModObjOUT, 3904 PVRSRV_BRIDGE_OUT_CREATE_SYNC_INFO_MOD_OBJ *psCreateSyncInfoModObjOUT,
3129 PVRSRV_PER_PROCESS_DATA *psPerProc) 3905 PVRSRV_PER_PROCESS_DATA *psPerProc)
3130{ 3906{
3131 MODIFY_SYNC_OP_INFO *psModSyncOpInfo; 3907 MODIFY_SYNC_OP_INFO *psModSyncOpInfo;
3132 3908
3133 PVR_UNREFERENCED_PARAMETER(psBridgeIn); 3909 PVR_UNREFERENCED_PARAMETER(psBridgeIn);
3134 3910
3135 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_CREATE_SYNC_INFO_MOD_OBJ); 3911 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_CREATE_SYNC_INFO_MOD_OBJ);
3136 3912
3137 NEW_HANDLE_BATCH_OR_ERROR(psCreateSyncInfoModObjOUT->eError, psPerProc, 1) 3913 NEW_HANDLE_BATCH_OR_ERROR(psCreateSyncInfoModObjOUT->eError, psPerProc, 1)
3138 3914
3139 ASSIGN_AND_EXIT_ON_ERROR(psCreateSyncInfoModObjOUT->eError, 3915 ASSIGN_AND_EXIT_ON_ERROR(psCreateSyncInfoModObjOUT->eError,
3140 OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, 3916 OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
3141 sizeof(MODIFY_SYNC_OP_INFO), 3917 sizeof(MODIFY_SYNC_OP_INFO),
3142 (IMG_VOID **)&psModSyncOpInfo, 0, 3918 (IMG_VOID **)&psModSyncOpInfo, 0,
3143 "ModSyncOpInfo (MODIFY_SYNC_OP_INFO)")); 3919 "ModSyncOpInfo (MODIFY_SYNC_OP_INFO)"));
3144 3920
3145 psModSyncOpInfo->psKernelSyncInfo = IMG_NULL; 3921 psModSyncOpInfo->psKernelSyncInfo = IMG_NULL;
3146 3922
3147 psCreateSyncInfoModObjOUT->eError = PVRSRVAllocHandle(psPerProc->psHandleBase, 3923 psCreateSyncInfoModObjOUT->eError = PVRSRVAllocHandle(psPerProc->psHandleBase,
3148 &psCreateSyncInfoModObjOUT->hKernelSyncInfoModObj, 3924 &psCreateSyncInfoModObjOUT->hKernelSyncInfoModObj,
3149 psModSyncOpInfo, 3925 psModSyncOpInfo,
3150 PVRSRV_HANDLE_TYPE_SYNC_INFO_MOD_OBJ, 3926 PVRSRV_HANDLE_TYPE_SYNC_INFO_MOD_OBJ,
3151 PVRSRV_HANDLE_ALLOC_FLAG_PRIVATE); 3927 PVRSRV_HANDLE_ALLOC_FLAG_PRIVATE);
3152 3928
3153 if (psCreateSyncInfoModObjOUT->eError != PVRSRV_OK) 3929 if (psCreateSyncInfoModObjOUT->eError != PVRSRV_OK)
3154 { 3930 {
3155 return 0; 3931 return 0;
3156 } 3932 }
3157 3933
3158 psModSyncOpInfo->hResItem = ResManRegisterRes(psPerProc->hResManContext, 3934 psModSyncOpInfo->hResItem = ResManRegisterRes(psPerProc->hResManContext,
3159 RESMAN_TYPE_MODIFY_SYNC_OPS, 3935 RESMAN_TYPE_MODIFY_SYNC_OPS,
3160 psModSyncOpInfo, 3936 psModSyncOpInfo,
3161 0, 3937 0,
3162 &ModifyCompleteSyncOpsCallBack); 3938 &ModifyCompleteSyncOpsCallBack);
3163 3939
3164 COMMIT_HANDLE_BATCH_OR_ERROR(psCreateSyncInfoModObjOUT->eError, psPerProc) 3940 COMMIT_HANDLE_BATCH_OR_ERROR(psCreateSyncInfoModObjOUT->eError, psPerProc)
3165 3941
3166 return 0; 3942 return 0;
3167} 3943}
3168 3944
3169 3945
3170static IMG_INT 3946static IMG_INT
3171PVRSRVDestroySyncInfoModObjBW(IMG_UINT32 ui32BridgeID, 3947PVRSRVDestroySyncInfoModObjBW(IMG_UINT32 ui32BridgeID,
3172 PVRSRV_BRIDGE_IN_DESTROY_SYNC_INFO_MOD_OBJ *psDestroySyncInfoModObjIN, 3948 PVRSRV_BRIDGE_IN_DESTROY_SYNC_INFO_MOD_OBJ *psDestroySyncInfoModObjIN,
3173 PVRSRV_BRIDGE_RETURN *psDestroySyncInfoModObjOUT, 3949 PVRSRV_BRIDGE_RETURN *psDestroySyncInfoModObjOUT,
3174 PVRSRV_PER_PROCESS_DATA *psPerProc) 3950 PVRSRV_PER_PROCESS_DATA *psPerProc)
3175{ 3951{
3176 MODIFY_SYNC_OP_INFO *psModSyncOpInfo; 3952 MODIFY_SYNC_OP_INFO *psModSyncOpInfo;
3177 3953
3178 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_DESTROY_SYNC_INFO_MOD_OBJ); 3954 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_DESTROY_SYNC_INFO_MOD_OBJ);
3179 3955
3180 psDestroySyncInfoModObjOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 3956 psDestroySyncInfoModObjOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
3181 (IMG_VOID**)&psModSyncOpInfo, 3957 (IMG_VOID**)&psModSyncOpInfo,
3182 psDestroySyncInfoModObjIN->hKernelSyncInfoModObj, 3958 psDestroySyncInfoModObjIN->hKernelSyncInfoModObj,
3183 PVRSRV_HANDLE_TYPE_SYNC_INFO_MOD_OBJ); 3959 PVRSRV_HANDLE_TYPE_SYNC_INFO_MOD_OBJ);
3184 if (psDestroySyncInfoModObjOUT->eError != PVRSRV_OK) 3960 if (psDestroySyncInfoModObjOUT->eError != PVRSRV_OK)
3185 { 3961 {
3186 PVR_DPF((PVR_DBG_ERROR, "PVRSRVDestroySyncInfoModObjBW: PVRSRVLookupHandle failed")); 3962 PVR_DPF((PVR_DBG_ERROR, "PVRSRVDestroySyncInfoModObjBW: PVRSRVLookupHandle failed"));
3187 return 0; 3963 return 0;
3188 } 3964 }
3189 3965
3190 if(psModSyncOpInfo->psKernelSyncInfo != IMG_NULL) 3966 if(psModSyncOpInfo->psKernelSyncInfo != IMG_NULL)
3191 { 3967 {
3192 3968
3193 psDestroySyncInfoModObjOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; 3969 psDestroySyncInfoModObjOUT->eError = PVRSRV_ERROR_INVALID_PARAMS;
3194 return 0; 3970 return 0;
3195 } 3971 }
3196 3972
3197 psDestroySyncInfoModObjOUT->eError = PVRSRVReleaseHandle(psPerProc->psHandleBase, 3973 psDestroySyncInfoModObjOUT->eError = PVRSRVReleaseHandle(psPerProc->psHandleBase,
3198 psDestroySyncInfoModObjIN->hKernelSyncInfoModObj, 3974 psDestroySyncInfoModObjIN->hKernelSyncInfoModObj,
3199 PVRSRV_HANDLE_TYPE_SYNC_INFO_MOD_OBJ); 3975 PVRSRV_HANDLE_TYPE_SYNC_INFO_MOD_OBJ);
3200 3976
3201 if (psDestroySyncInfoModObjOUT->eError != PVRSRV_OK) 3977 if (psDestroySyncInfoModObjOUT->eError != PVRSRV_OK)
3202 { 3978 {
3203 PVR_DPF((PVR_DBG_ERROR, "PVRSRVDestroySyncInfoModObjBW: PVRSRVReleaseHandle failed")); 3979 PVR_DPF((PVR_DBG_ERROR, "PVRSRVDestroySyncInfoModObjBW: PVRSRVReleaseHandle failed"));
3204 return 0; 3980 return 0;
3205 } 3981 }
3206 3982
3207 psDestroySyncInfoModObjOUT->eError = ResManFreeResByPtr(psModSyncOpInfo->hResItem); 3983 psDestroySyncInfoModObjOUT->eError = ResManFreeResByPtr(psModSyncOpInfo->hResItem);
3208 if (psDestroySyncInfoModObjOUT->eError != PVRSRV_OK) 3984 if (psDestroySyncInfoModObjOUT->eError != PVRSRV_OK)
3209 { 3985 {
3210 PVR_DPF((PVR_DBG_ERROR, "PVRSRVDestroySyncInfoModObjBW: ResManFreeResByPtr failed")); 3986 PVR_DPF((PVR_DBG_ERROR, "PVRSRVDestroySyncInfoModObjBW: ResManFreeResByPtr failed"));
3211 return 0; 3987 return 0;
3212 } 3988 }
3213 3989
3214 return 0; 3990 return 0;
3215} 3991}
3216 3992
3217 3993
3218static IMG_INT 3994static IMG_INT
3219PVRSRVModifyPendingSyncOpsBW(IMG_UINT32 ui32BridgeID, 3995PVRSRVModifyPendingSyncOpsBW(IMG_UINT32 ui32BridgeID,
3220 PVRSRV_BRIDGE_IN_MODIFY_PENDING_SYNC_OPS *psModifySyncOpsIN, 3996 PVRSRV_BRIDGE_IN_MODIFY_PENDING_SYNC_OPS *psModifySyncOpsIN,
3221 PVRSRV_BRIDGE_OUT_MODIFY_PENDING_SYNC_OPS *psModifySyncOpsOUT, 3997 PVRSRV_BRIDGE_OUT_MODIFY_PENDING_SYNC_OPS *psModifySyncOpsOUT,
3222 PVRSRV_PER_PROCESS_DATA *psPerProc) 3998 PVRSRV_PER_PROCESS_DATA *psPerProc)
3223{ 3999{
3224 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo; 4000 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo;
3225 MODIFY_SYNC_OP_INFO *psModSyncOpInfo; 4001 MODIFY_SYNC_OP_INFO *psModSyncOpInfo;
3226 4002
3227 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_MODIFY_PENDING_SYNC_OPS); 4003 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_MODIFY_PENDING_SYNC_OPS);
3228 4004
3229 psModifySyncOpsOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 4005 psModifySyncOpsOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
3230 (IMG_VOID**)&psModSyncOpInfo, 4006 (IMG_VOID**)&psModSyncOpInfo,
3231 psModifySyncOpsIN->hKernelSyncInfoModObj, 4007 psModifySyncOpsIN->hKernelSyncInfoModObj,
3232 PVRSRV_HANDLE_TYPE_SYNC_INFO_MOD_OBJ); 4008 PVRSRV_HANDLE_TYPE_SYNC_INFO_MOD_OBJ);
3233 if (psModifySyncOpsOUT->eError != PVRSRV_OK) 4009 if (psModifySyncOpsOUT->eError != PVRSRV_OK)
3234 { 4010 {
3235 PVR_DPF((PVR_DBG_ERROR, "PVRSRVModifyPendingSyncOpsBW: PVRSRVLookupHandle failed")); 4011 PVR_DPF((PVR_DBG_ERROR, "PVRSRVModifyPendingSyncOpsBW: PVRSRVLookupHandle failed"));
3236 return 0; 4012 return 0;
3237 } 4013 }
3238 4014
3239 psModifySyncOpsOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 4015 psModifySyncOpsOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
3240 (IMG_VOID**)&psKernelSyncInfo, 4016 (IMG_VOID**)&psKernelSyncInfo,
3241 psModifySyncOpsIN->hKernelSyncInfo, 4017 psModifySyncOpsIN->hKernelSyncInfo,
3242 PVRSRV_HANDLE_TYPE_SYNC_INFO); 4018 PVRSRV_HANDLE_TYPE_SYNC_INFO);
3243 if (psModifySyncOpsOUT->eError != PVRSRV_OK) 4019 if (psModifySyncOpsOUT->eError != PVRSRV_OK)
3244 { 4020 {
3245 PVR_DPF((PVR_DBG_ERROR, "PVRSRVModifyPendingSyncOpsBW: PVRSRVLookupHandle failed")); 4021 PVR_DPF((PVR_DBG_ERROR, "PVRSRVModifyPendingSyncOpsBW: PVRSRVLookupHandle failed"));
3246 return 0; 4022 return 0;
3247 } 4023 }
3248 4024
3249 if(psModSyncOpInfo->psKernelSyncInfo) 4025 if(psModSyncOpInfo->psKernelSyncInfo)
3250 { 4026 {
3251 4027
3252 psModifySyncOpsOUT->eError = PVRSRV_ERROR_RETRY; 4028 psModifySyncOpsOUT->eError = PVRSRV_ERROR_RETRY;
3253 PVR_DPF((PVR_DBG_VERBOSE, "PVRSRVModifyPendingSyncOpsBW: SyncInfo Modification object is not empty")); 4029 PVR_DPF((PVR_DBG_VERBOSE, "PVRSRVModifyPendingSyncOpsBW: SyncInfo Modification object is not empty"));
3254 return 0; 4030 return 0;
3255 } 4031 }
4032
4033
4034 psModSyncOpInfo->psKernelSyncInfo = psKernelSyncInfo;
4035 psModSyncOpInfo->ui32ModifyFlags = psModifySyncOpsIN->ui32ModifyFlags;
4036 psModSyncOpInfo->ui32ReadOpsPendingSnapShot = psKernelSyncInfo->psSyncData->ui32ReadOpsPending;
4037 psModSyncOpInfo->ui32WriteOpsPendingSnapShot = psKernelSyncInfo->psSyncData->ui32WriteOpsPending;
4038
4039
4040
4041 psModifySyncOpsOUT->ui32ReadOpsPending = psKernelSyncInfo->psSyncData->ui32ReadOpsPending;
4042 psModifySyncOpsOUT->ui32WriteOpsPending = psKernelSyncInfo->psSyncData->ui32WriteOpsPending;
4043
4044 if(psModifySyncOpsIN->ui32ModifyFlags & PVRSRV_MODIFYSYNCOPS_FLAGS_WO_INC)
4045 {
4046 psKernelSyncInfo->psSyncData->ui32WriteOpsPending++;
4047 }
4048
4049 if(psModifySyncOpsIN->ui32ModifyFlags & PVRSRV_MODIFYSYNCOPS_FLAGS_RO_INC)
4050 {
4051 psKernelSyncInfo->psSyncData->ui32ReadOpsPending++;
4052 }
4053
4054
4055 psModifySyncOpsOUT->eError = ResManDissociateRes(psModSyncOpInfo->hResItem,
4056 psPerProc->hResManContext);
4057
4058 if (psModifySyncOpsOUT->eError != PVRSRV_OK)
4059 {
4060 PVR_DPF((PVR_DBG_ERROR, "PVRSRVModifyPendingSyncOpsBW: PVRSRVLookupHandle failed"));
4061 return 0;
4062 }
4063
4064 return 0;
4065}
3256 4066
3257 4067
3258 psModSyncOpInfo->psKernelSyncInfo = psKernelSyncInfo; 4068static IMG_INT
3259 psModSyncOpInfo->ui32ModifyFlags = psModifySyncOpsIN->ui32ModifyFlags; 4069PVRSRVModifyCompleteSyncOpsBW(IMG_UINT32 ui32BridgeID,
3260 psModSyncOpInfo->ui32ReadOpsPendingSnapShot = psKernelSyncInfo->psSyncData->ui32ReadOpsPending; 4070 PVRSRV_BRIDGE_IN_MODIFY_COMPLETE_SYNC_OPS *psModifySyncOpsIN,
3261 psModSyncOpInfo->ui32WriteOpsPendingSnapShot = psKernelSyncInfo->psSyncData->ui32WriteOpsPending; 4071 PVRSRV_BRIDGE_RETURN *psModifySyncOpsOUT,
4072 PVRSRV_PER_PROCESS_DATA *psPerProc)
4073{
4074 MODIFY_SYNC_OP_INFO *psModSyncOpInfo;
3262 4075
4076 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_MODIFY_COMPLETE_SYNC_OPS);
3263 4077
4078 psModifySyncOpsOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
4079 (IMG_VOID**)&psModSyncOpInfo,
4080 psModifySyncOpsIN->hKernelSyncInfoModObj,
4081 PVRSRV_HANDLE_TYPE_SYNC_INFO_MOD_OBJ);
4082 if (psModifySyncOpsOUT->eError != PVRSRV_OK)
4083 {
4084 PVR_DPF((PVR_DBG_ERROR, "PVRSRVModifyCompleteSyncOpsBW: PVRSRVLookupHandle failed"));
4085 return 0;
4086 }
3264 4087
3265 psModifySyncOpsOUT->ui32ReadOpsPending = psKernelSyncInfo->psSyncData->ui32ReadOpsPending; 4088 if(psModSyncOpInfo->psKernelSyncInfo == IMG_NULL)
3266 psModifySyncOpsOUT->ui32WriteOpsPending = psKernelSyncInfo->psSyncData->ui32WriteOpsPending; 4089 {
4090
4091 psModifySyncOpsOUT->eError = PVRSRV_ERROR_INVALID_PARAMS;
4092 return 0;
4093 }
3267 4094
3268 if(psModifySyncOpsIN->ui32ModifyFlags & PVRSRV_MODIFYSYNCOPS_FLAGS_WO_INC) 4095 psModifySyncOpsOUT->eError = DoModifyCompleteSyncOps(psModSyncOpInfo);
3269 {
3270 psKernelSyncInfo->psSyncData->ui32WriteOpsPending++;
3271 }
3272 4096
3273 if(psModifySyncOpsIN->ui32ModifyFlags & PVRSRV_MODIFYSYNCOPS_FLAGS_RO_INC) 4097 if (psModifySyncOpsOUT->eError != PVRSRV_OK)
3274 { 4098 {
3275 psKernelSyncInfo->psSyncData->ui32ReadOpsPending++; 4099 PVR_DPF((PVR_DBG_ERROR, "PVRSRVModifyCompleteSyncOpsBW: DoModifyCompleteSyncOps failed"));
3276 } 4100 return 0;
4101 }
3277 4102
4103 psModSyncOpInfo->psKernelSyncInfo = IMG_NULL;
3278 4104
3279 psModifySyncOpsOUT->eError = ResManDissociateRes(psModSyncOpInfo->hResItem, 4105
3280 psPerProc->hResManContext); 4106 PVRSRVScheduleDeviceCallbacks();
3281 4107
3282 if (psModifySyncOpsOUT->eError != PVRSRV_OK) 4108 return 0;
3283 {
3284 PVR_DPF((PVR_DBG_ERROR, "PVRSRVModifyPendingSyncOpsBW: PVRSRVLookupHandle failed"));
3285 return 0;
3286 }
3287
3288 return 0;
3289} 4109}
3290 4110
3291 4111
3292static IMG_INT 4112static IMG_INT
3293PVRSRVModifyCompleteSyncOpsBW(IMG_UINT32 ui32BridgeID, 4113PVRSRVSyncOpsTakeTokenBW(IMG_UINT32 ui32BridgeID,
3294 PVRSRV_BRIDGE_IN_MODIFY_COMPLETE_SYNC_OPS *psModifySyncOpsIN, 4114 PVRSRV_BRIDGE_IN_SYNC_OPS_TAKE_TOKEN *psSyncOpsTakeTokenIN,
3295 PVRSRV_BRIDGE_RETURN *psModifySyncOpsOUT, 4115 PVRSRV_BRIDGE_OUT_SYNC_OPS_TAKE_TOKEN *psSyncOpsTakeTokenOUT,
3296 PVRSRV_PER_PROCESS_DATA *psPerProc) 4116 PVRSRV_PER_PROCESS_DATA *psPerProc)
3297{ 4117{
3298 MODIFY_SYNC_OP_INFO *psModSyncOpInfo; 4118 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo;
3299 4119
3300 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_MODIFY_COMPLETE_SYNC_OPS); 4120 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SYNC_OPS_TAKE_TOKEN);
3301 4121
3302 psModifySyncOpsOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 4122 psSyncOpsTakeTokenOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
3303 (IMG_VOID**)&psModSyncOpInfo, 4123 (IMG_VOID**)&psKernelSyncInfo,
3304 psModifySyncOpsIN->hKernelSyncInfoModObj, 4124 psSyncOpsTakeTokenIN->hKernelSyncInfo,
3305 PVRSRV_HANDLE_TYPE_SYNC_INFO_MOD_OBJ); 4125 PVRSRV_HANDLE_TYPE_SYNC_INFO);
3306 if (psModifySyncOpsOUT->eError != PVRSRV_OK) 4126 if (psSyncOpsTakeTokenOUT->eError != PVRSRV_OK)
3307 { 4127 {
3308 PVR_DPF((PVR_DBG_ERROR, "PVRSRVModifyCompleteSyncOpsBW: PVRSRVLookupHandle failed")); 4128 PVR_DPF((PVR_DBG_ERROR, "PVRSRVSyncOpsTakeTokenBW: PVRSRVLookupHandle failed"));
3309 return 0; 4129 return 0;
3310 } 4130 }
3311 4131
3312 if(psModSyncOpInfo->psKernelSyncInfo == IMG_NULL) 4132
3313 {
3314 4133
3315 psModifySyncOpsOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; 4134 psSyncOpsTakeTokenOUT->ui32ReadOpsPending = psKernelSyncInfo->psSyncData->ui32ReadOpsPending;
3316 return 0; 4135 psSyncOpsTakeTokenOUT->ui32WriteOpsPending = psKernelSyncInfo->psSyncData->ui32WriteOpsPending;
3317 }
3318
3319 psModifySyncOpsOUT->eError = DoModifyCompleteSyncOps(psModSyncOpInfo);
3320
3321 if (psModifySyncOpsOUT->eError != PVRSRV_OK)
3322 {
3323 PVR_DPF((PVR_DBG_ERROR, "PVRSRVModifyCompleteSyncOpsBW: DoModifyCompleteSyncOps failed"));
3324 return 0;
3325 }
3326
3327 psModSyncOpInfo->psKernelSyncInfo = IMG_NULL;
3328 4136
4137 return 0;
4138}
3329 4139
3330 PVRSRVScheduleDeviceCallbacks();
3331 4140
3332 return 0; 4141static IMG_INT
4142PVRSRVSyncOpsFlushToTokenBW(IMG_UINT32 ui32BridgeID,
4143 PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_TOKEN *psSyncOpsFlushToTokenIN,
4144 PVRSRV_BRIDGE_RETURN *psSyncOpsFlushToTokenOUT,
4145 PVRSRV_PER_PROCESS_DATA *psPerProc)
4146{
4147 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo;
4148 IMG_UINT32 ui32ReadOpsPendingSnapshot;
4149 IMG_UINT32 ui32WriteOpsPendingSnapshot;
4150
4151 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SYNC_OPS_FLUSH_TO_TOKEN);
4152
4153 psSyncOpsFlushToTokenOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
4154 (IMG_VOID**)&psKernelSyncInfo,
4155 psSyncOpsFlushToTokenIN->hKernelSyncInfo,
4156 PVRSRV_HANDLE_TYPE_SYNC_INFO);
4157 if (psSyncOpsFlushToTokenOUT->eError != PVRSRV_OK)
4158 {
4159 PVR_DPF((PVR_DBG_ERROR, "PVRSRVSyncOpsFlushToTokenBW: PVRSRVLookupHandle failed"));
4160 return 0;
4161 }
4162
4163 ui32ReadOpsPendingSnapshot = psSyncOpsFlushToTokenIN->ui32ReadOpsPendingSnapshot;
4164 ui32WriteOpsPendingSnapshot = psSyncOpsFlushToTokenIN->ui32WriteOpsPendingSnapshot;
4165
4166 psSyncOpsFlushToTokenOUT->eError = DoQuerySyncOpsSatisfied(psKernelSyncInfo,
4167 ui32ReadOpsPendingSnapshot,
4168 ui32WriteOpsPendingSnapshot);
4169
4170 if (psSyncOpsFlushToTokenOUT->eError != PVRSRV_OK && psSyncOpsFlushToTokenOUT->eError != PVRSRV_ERROR_RETRY)
4171 {
4172 PVR_DPF((PVR_DBG_ERROR, "PVRSRVSyncOpsFlushToTokenBW: DoQuerySyncOpsSatisfied failed"));
4173 return 0;
4174 }
4175
4176 return 0;
3333} 4177}
3334 4178
3335 4179
3336static IMG_INT 4180static IMG_INT
3337PVRSRVSyncOpsFlushToModObjBW(IMG_UINT32 ui32BridgeID, 4181PVRSRVSyncOpsFlushToModObjBW(IMG_UINT32 ui32BridgeID,
3338 PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_MOD_OBJ *psSyncOpsFlushToModObjIN, 4182 PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_MOD_OBJ *psSyncOpsFlushToModObjIN,
3339 PVRSRV_BRIDGE_RETURN *psSyncOpsFlushToModObjOUT, 4183 PVRSRV_BRIDGE_RETURN *psSyncOpsFlushToModObjOUT,
3340 PVRSRV_PER_PROCESS_DATA *psPerProc) 4184 PVRSRV_PER_PROCESS_DATA *psPerProc)
3341{ 4185{
3342 MODIFY_SYNC_OP_INFO *psModSyncOpInfo; 4186 MODIFY_SYNC_OP_INFO *psModSyncOpInfo;
3343 4187
3344 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SYNC_OPS_FLUSH_TO_MOD_OBJ); 4188 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SYNC_OPS_FLUSH_TO_MOD_OBJ);
3345 4189
3346 psSyncOpsFlushToModObjOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 4190 psSyncOpsFlushToModObjOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
3347 (IMG_VOID**)&psModSyncOpInfo, 4191 (IMG_VOID**)&psModSyncOpInfo,
3348 psSyncOpsFlushToModObjIN->hKernelSyncInfoModObj, 4192 psSyncOpsFlushToModObjIN->hKernelSyncInfoModObj,
3349 PVRSRV_HANDLE_TYPE_SYNC_INFO_MOD_OBJ); 4193 PVRSRV_HANDLE_TYPE_SYNC_INFO_MOD_OBJ);
3350 if (psSyncOpsFlushToModObjOUT->eError != PVRSRV_OK) 4194 if (psSyncOpsFlushToModObjOUT->eError != PVRSRV_OK)
3351 { 4195 {
3352 PVR_DPF((PVR_DBG_ERROR, "PVRSRVSyncOpsFlushToModObjBW: PVRSRVLookupHandle failed")); 4196 PVR_DPF((PVR_DBG_ERROR, "PVRSRVSyncOpsFlushToModObjBW: PVRSRVLookupHandle failed"));
3353 return 0; 4197 return 0;
3354 } 4198 }
3355 4199
3356 if(psModSyncOpInfo->psKernelSyncInfo == IMG_NULL) 4200 if(psModSyncOpInfo->psKernelSyncInfo == IMG_NULL)
3357 { 4201 {
3358 4202
3359 psSyncOpsFlushToModObjOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; 4203 psSyncOpsFlushToModObjOUT->eError = PVRSRV_ERROR_INVALID_PARAMS;
3360 return 0; 4204 return 0;
3361 } 4205 }
3362 4206
3363 psSyncOpsFlushToModObjOUT->eError = DoQuerySyncOpsSatisfied(psModSyncOpInfo); 4207 psSyncOpsFlushToModObjOUT->eError = DoQuerySyncOpsSatisfied(psModSyncOpInfo->psKernelSyncInfo,
3364 4208 psModSyncOpInfo->ui32ReadOpsPendingSnapShot,
3365 if (psSyncOpsFlushToModObjOUT->eError != PVRSRV_OK && psSyncOpsFlushToModObjOUT->eError != PVRSRV_ERROR_RETRY) 4209 psModSyncOpInfo->ui32WriteOpsPendingSnapShot);
3366 { 4210
3367 PVR_DPF((PVR_DBG_ERROR, "PVRSRVSyncOpsFlushToModObjBW: DoQuerySyncOpsSatisfied failed")); 4211 if (psSyncOpsFlushToModObjOUT->eError != PVRSRV_OK && psSyncOpsFlushToModObjOUT->eError != PVRSRV_ERROR_RETRY)
3368 return 0; 4212 {
3369 } 4213 PVR_DPF((PVR_DBG_ERROR, "PVRSRVSyncOpsFlushToModObjBW: DoQuerySyncOpsSatisfied failed"));
3370 4214 return 0;
3371 return 0; 4215 }
4216
4217 return 0;
3372} 4218}
3373 4219
3374 4220
3375static IMG_INT 4221static IMG_INT
3376PVRSRVSyncOpsFlushToDeltaBW(IMG_UINT32 ui32BridgeID, 4222PVRSRVSyncOpsFlushToDeltaBW(IMG_UINT32 ui32BridgeID,
3377 PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_DELTA *psSyncOpsFlushToDeltaIN, 4223 PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_DELTA *psSyncOpsFlushToDeltaIN,
3378 PVRSRV_BRIDGE_RETURN *psSyncOpsFlushToDeltaOUT, 4224 PVRSRV_BRIDGE_RETURN *psSyncOpsFlushToDeltaOUT,
3379 PVRSRV_PER_PROCESS_DATA *psPerProc) 4225 PVRSRV_PER_PROCESS_DATA *psPerProc)
3380{ 4226{
3381 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo; 4227 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo;
3382 IMG_UINT32 ui32DeltaRead; 4228 IMG_UINT32 ui32DeltaRead;
3383 IMG_UINT32 ui32DeltaWrite; 4229 IMG_UINT32 ui32DeltaWrite;
3384 4230
3385 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SYNC_OPS_FLUSH_TO_DELTA); 4231 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SYNC_OPS_FLUSH_TO_DELTA);
3386 4232
3387 psSyncOpsFlushToDeltaOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 4233 psSyncOpsFlushToDeltaOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
3388 (IMG_VOID**)&psSyncInfo, 4234 (IMG_VOID**)&psSyncInfo,
3389 psSyncOpsFlushToDeltaIN->hKernelSyncInfo, 4235 psSyncOpsFlushToDeltaIN->hKernelSyncInfo,
3390 PVRSRV_HANDLE_TYPE_SYNC_INFO); 4236 PVRSRV_HANDLE_TYPE_SYNC_INFO);
3391 if (psSyncOpsFlushToDeltaOUT->eError != PVRSRV_OK) 4237 if (psSyncOpsFlushToDeltaOUT->eError != PVRSRV_OK)
3392 { 4238 {
3393 PVR_DPF((PVR_DBG_ERROR, "PVRSRVSyncOpsFlushToDeltaBW: PVRSRVLookupHandle failed")); 4239 PVR_DPF((PVR_DBG_ERROR, "PVRSRVSyncOpsFlushToDeltaBW: PVRSRVLookupHandle failed"));
3394 return 0; 4240 return 0;
3395 } 4241 }
3396 4242
3397 ui32DeltaRead = psSyncInfo->psSyncData->ui32ReadOpsPending - psSyncInfo->psSyncData->ui32ReadOpsComplete; 4243
3398 ui32DeltaWrite = psSyncInfo->psSyncData->ui32WriteOpsPending - psSyncInfo->psSyncData->ui32WriteOpsComplete; 4244 ui32DeltaRead = psSyncInfo->psSyncData->ui32ReadOpsPending - psSyncInfo->psSyncData->ui32ReadOpsComplete;
4245 ui32DeltaWrite = psSyncInfo->psSyncData->ui32WriteOpsPending - psSyncInfo->psSyncData->ui32WriteOpsComplete;
4246
4247 if (ui32DeltaRead <= psSyncOpsFlushToDeltaIN->ui32Delta && ui32DeltaWrite <= psSyncOpsFlushToDeltaIN->ui32Delta)
4248 {
4249#if defined(PDUMP) && !defined(SUPPORT_VGX)
4250
4251 PDumpComment("Poll for read ops complete to delta (%u)",
4252 psSyncOpsFlushToDeltaIN->ui32Delta);
4253 psSyncOpsFlushToDeltaOUT->eError =
4254 PDumpMemPolKM(psSyncInfo->psSyncDataMemInfoKM,
4255 offsetof(PVRSRV_SYNC_DATA, ui32ReadOpsComplete),
4256 psSyncInfo->psSyncData->ui32LastReadOpDumpVal,
4257 0xFFFFFFFF,
4258 PDUMP_POLL_OPERATOR_GREATEREQUAL,
4259 0,
4260 MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM));
4261
4262
4263 PDumpComment("Poll for write ops complete to delta (%u)",
4264 psSyncOpsFlushToDeltaIN->ui32Delta);
4265 psSyncOpsFlushToDeltaOUT->eError =
4266 PDumpMemPolKM(psSyncInfo->psSyncDataMemInfoKM,
4267 offsetof(PVRSRV_SYNC_DATA, ui32WriteOpsComplete),
4268 psSyncInfo->psSyncData->ui32LastOpDumpVal,
4269 0xFFFFFFFF,
4270 PDUMP_POLL_OPERATOR_GREATEREQUAL,
4271 0,
4272 MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM));
4273#endif
3399 4274
3400 if (ui32DeltaRead <= psSyncOpsFlushToDeltaIN->ui32Delta && ui32DeltaWrite <= psSyncOpsFlushToDeltaIN->ui32Delta) 4275 psSyncOpsFlushToDeltaOUT->eError = PVRSRV_OK;
3401 { 4276 }
3402#if defined(PDUMP) 4277 else
3403 IMG_UINT32 ui32MinimumReadOpsComplete; 4278 {
3404 4279 psSyncOpsFlushToDeltaOUT->eError = PVRSRV_ERROR_RETRY;
3405 ui32MinimumReadOpsComplete = psSyncInfo->psSyncData->ui32ReadOpsPending; 4280 }
3406 if (ui32MinimumReadOpsComplete < psSyncOpsFlushToDeltaIN->ui32Delta)
3407 {
3408 ui32MinimumReadOpsComplete = 0;
3409 }
3410 else
3411 {
3412 ui32MinimumReadOpsComplete = ui32MinimumReadOpsComplete - psSyncOpsFlushToDeltaIN->ui32Delta;
3413 }
3414
3415
3416 PDumpComment("Poll for read ops complete to delta (%u)",
3417 psSyncOpsFlushToDeltaIN->ui32Delta);
3418 psSyncOpsFlushToDeltaOUT->eError =
3419 PDumpMemPolKM(psSyncInfo->psSyncDataMemInfoKM,
3420 offsetof(PVRSRV_SYNC_DATA, ui32ReadOpsComplete),
3421 psSyncInfo->psSyncData->ui32LastReadOpDumpVal,
3422 0xFFFFFFFF,
3423 PDUMP_POLL_OPERATOR_GREATEREQUAL,
3424 0,
3425 MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM));
3426
3427
3428 PDumpComment("Poll for write ops complete to delta (%u)",
3429 psSyncOpsFlushToDeltaIN->ui32Delta);
3430 psSyncOpsFlushToDeltaOUT->eError =
3431 PDumpMemPolKM(psSyncInfo->psSyncDataMemInfoKM,
3432 offsetof(PVRSRV_SYNC_DATA, ui32WriteOpsComplete),
3433 psSyncInfo->psSyncData->ui32LastOpDumpVal,
3434 0xFFFFFFFF,
3435 PDUMP_POLL_OPERATOR_GREATEREQUAL,
3436 0,
3437 MAKEUNIQUETAG(psSyncInfo->psSyncDataMemInfoKM));
3438#endif
3439
3440 psSyncOpsFlushToDeltaOUT->eError = PVRSRV_OK;
3441 }
3442 else
3443 {
3444 psSyncOpsFlushToDeltaOUT->eError = PVRSRV_ERROR_RETRY;
3445 }
3446 4281
3447 return 0; 4282 return 0;
3448} 4283}
3449 4284
3450 4285
3451static PVRSRV_ERROR 4286static PVRSRV_ERROR
3452FreeSyncInfoCallback(IMG_PVOID pvParam, 4287FreeSyncInfoCallback(IMG_PVOID pvParam,
3453 IMG_UINT32 ui32Param) 4288 IMG_UINT32 ui32Param)
3454{ 4289{
3455 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo; 4290 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo;
3456 PVRSRV_ERROR eError; 4291 PVRSRV_ERROR eError;
3457 4292
3458 PVR_UNREFERENCED_PARAMETER(ui32Param); 4293 PVR_UNREFERENCED_PARAMETER(ui32Param);
3459 4294
3460 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)pvParam; 4295 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)pvParam;
3461 4296
3462 eError = PVRSRVFreeSyncInfoKM(psSyncInfo); 4297 eError = PVRSRVFreeSyncInfoKM(psSyncInfo);
3463 if (eError != PVRSRV_OK) 4298 if (eError != PVRSRV_OK)
3464 { 4299 {
3465 return eError; 4300 return eError;
3466 } 4301 }
3467 4302
3468 return PVRSRV_OK; 4303 return PVRSRV_OK;
3469} 4304}
3470 4305
3471 4306
3472static IMG_INT 4307static IMG_INT
3473PVRSRVAllocSyncInfoBW(IMG_UINT32 ui32BridgeID, 4308PVRSRVAllocSyncInfoBW(IMG_UINT32 ui32BridgeID,
3474 PVRSRV_BRIDGE_IN_ALLOC_SYNC_INFO *psAllocSyncInfoIN, 4309 PVRSRV_BRIDGE_IN_ALLOC_SYNC_INFO *psAllocSyncInfoIN,
3475 PVRSRV_BRIDGE_OUT_ALLOC_SYNC_INFO *psAllocSyncInfoOUT, 4310 PVRSRV_BRIDGE_OUT_ALLOC_SYNC_INFO *psAllocSyncInfoOUT,
3476 PVRSRV_PER_PROCESS_DATA *psPerProc) 4311 PVRSRV_PER_PROCESS_DATA *psPerProc)
3477{ 4312{
3478 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo; 4313 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo;
3479 PVRSRV_ERROR eError; 4314 PVRSRV_ERROR eError;
3480 PVRSRV_DEVICE_NODE *psDeviceNode; 4315 PVRSRV_DEVICE_NODE *psDeviceNode;
3481 IMG_HANDLE hDevMemContext; 4316 IMG_HANDLE hDevMemContext;
3482 4317
3483 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ALLOC_SYNC_INFO); 4318 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_ALLOC_SYNC_INFO);
3484 4319
3485 NEW_HANDLE_BATCH_OR_ERROR(psAllocSyncInfoOUT->eError, psPerProc, 1) 4320 NEW_HANDLE_BATCH_OR_ERROR(psAllocSyncInfoOUT->eError, psPerProc, 1)
3486 4321
3487 eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 4322 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
3488 (IMG_HANDLE *)&psDeviceNode, 4323 (IMG_HANDLE *)&psDeviceNode,
3489 psAllocSyncInfoIN->hDevCookie, 4324 psAllocSyncInfoIN->hDevCookie,
3490 PVRSRV_HANDLE_TYPE_DEV_NODE); 4325 PVRSRV_HANDLE_TYPE_DEV_NODE);
3491 if(eError != PVRSRV_OK) 4326 if(eError != PVRSRV_OK)
3492 { 4327 {
3493 goto allocsyncinfo_errorexit; 4328 goto allocsyncinfo_errorexit;
3494 } 4329 }
3495 4330
3496 hDevMemContext = psDeviceNode->sDevMemoryInfo.pBMKernelContext; 4331 hDevMemContext = psDeviceNode->sDevMemoryInfo.pBMKernelContext;
3497 4332
3498 eError = PVRSRVAllocSyncInfoKM(psDeviceNode, 4333 eError = PVRSRVAllocSyncInfoKM(psDeviceNode,
3499 hDevMemContext, 4334 hDevMemContext,
3500 &psSyncInfo); 4335 &psSyncInfo);
3501 4336
3502 if (eError != PVRSRV_OK) 4337 if (eError != PVRSRV_OK)
3503 { 4338 {
3504 goto allocsyncinfo_errorexit; 4339 goto allocsyncinfo_errorexit;
3505 } 4340 }
3506 4341
3507 eError = PVRSRVAllocHandle(psPerProc->psHandleBase, 4342 eError = PVRSRVAllocHandle(psPerProc->psHandleBase,
3508 &psAllocSyncInfoOUT->hKernelSyncInfo, 4343 &psAllocSyncInfoOUT->hKernelSyncInfo,
3509 psSyncInfo, 4344 psSyncInfo,
3510 PVRSRV_HANDLE_TYPE_SYNC_INFO, 4345 PVRSRV_HANDLE_TYPE_SYNC_INFO,
3511 PVRSRV_HANDLE_ALLOC_FLAG_PRIVATE); 4346 PVRSRV_HANDLE_ALLOC_FLAG_PRIVATE);
3512 4347
3513 if(eError != PVRSRV_OK) 4348 if(eError != PVRSRV_OK)
3514 { 4349 {
3515 goto allocsyncinfo_errorexit_freesyncinfo; 4350 goto allocsyncinfo_errorexit_freesyncinfo;
3516 } 4351 }
3517 4352
3518 psSyncInfo->hResItem = ResManRegisterRes(psPerProc->hResManContext, 4353 psSyncInfo->hResItem = ResManRegisterRes(psPerProc->hResManContext,
3519 RESMAN_TYPE_SYNC_INFO, 4354 RESMAN_TYPE_SYNC_INFO,
3520 psSyncInfo, 4355 psSyncInfo,
3521 0, 4356 0,
3522 FreeSyncInfoCallback); 4357 FreeSyncInfoCallback);
3523 4358
3524 4359
3525 goto allocsyncinfo_commit; 4360 goto allocsyncinfo_commit;
3526 4361
3527 4362
3528 allocsyncinfo_errorexit_freesyncinfo: 4363 allocsyncinfo_errorexit_freesyncinfo:
3529 PVRSRVFreeSyncInfoKM(psSyncInfo); 4364 PVRSRVFreeSyncInfoKM(psSyncInfo);
3530 4365
3531 allocsyncinfo_errorexit: 4366 allocsyncinfo_errorexit:
3532 4367
3533 4368
3534 allocsyncinfo_commit: 4369 allocsyncinfo_commit:
3535 psAllocSyncInfoOUT->eError = eError; 4370 psAllocSyncInfoOUT->eError = eError;
3536 COMMIT_HANDLE_BATCH_OR_ERROR(eError, psPerProc); 4371 COMMIT_HANDLE_BATCH_OR_ERROR(eError, psPerProc);
3537 4372
3538 return 0; 4373 return 0;
3539} 4374}
3540 4375
3541 4376
3542static IMG_INT 4377static IMG_INT
3543PVRSRVFreeSyncInfoBW(IMG_UINT32 ui32BridgeID, 4378PVRSRVFreeSyncInfoBW(IMG_UINT32 ui32BridgeID,
3544 PVRSRV_BRIDGE_IN_FREE_SYNC_INFO *psFreeSyncInfoIN, 4379 PVRSRV_BRIDGE_IN_FREE_SYNC_INFO *psFreeSyncInfoIN,
3545 PVRSRV_BRIDGE_RETURN *psFreeSyncInfoOUT, 4380 PVRSRV_BRIDGE_RETURN *psFreeSyncInfoOUT,
3546 PVRSRV_PER_PROCESS_DATA *psPerProc) 4381 PVRSRV_PER_PROCESS_DATA *psPerProc)
3547{ 4382{
3548 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo; 4383 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo;
3549 PVRSRV_ERROR eError; 4384 PVRSRV_ERROR eError;
3550 4385
3551 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_FREE_SYNC_INFO); 4386 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_FREE_SYNC_INFO);
3552 4387
3553 eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 4388 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
3554 (IMG_VOID**)&psSyncInfo, 4389 (IMG_VOID**)&psSyncInfo,
3555 psFreeSyncInfoIN->hKernelSyncInfo, 4390 psFreeSyncInfoIN->hKernelSyncInfo,
3556 PVRSRV_HANDLE_TYPE_SYNC_INFO); 4391 PVRSRV_HANDLE_TYPE_SYNC_INFO);
3557 if (eError != PVRSRV_OK) 4392 if (eError != PVRSRV_OK)
3558 { 4393 {
3559 PVR_DPF((PVR_DBG_ERROR, "PVRSRVFreeSyncInfoBW: PVRSRVLookupHandle failed")); 4394 PVR_DPF((PVR_DBG_ERROR, "PVRSRVFreeSyncInfoBW: PVRSRVLookupHandle failed"));
3560 psFreeSyncInfoOUT->eError = eError; 4395 psFreeSyncInfoOUT->eError = eError;
3561 return 0; 4396 return 0;
3562 } 4397 }
3563 4398
3564 eError = PVRSRVReleaseHandle(psPerProc->psHandleBase, 4399 eError = PVRSRVReleaseHandle(psPerProc->psHandleBase,
3565 psFreeSyncInfoIN->hKernelSyncInfo, 4400 psFreeSyncInfoIN->hKernelSyncInfo,
3566 PVRSRV_HANDLE_TYPE_SYNC_INFO); 4401 PVRSRV_HANDLE_TYPE_SYNC_INFO);
3567 4402
3568 if (eError != PVRSRV_OK) 4403 if (eError != PVRSRV_OK)
3569 { 4404 {
3570 PVR_DPF((PVR_DBG_ERROR, "PVRSRVFreeSyncInfoBW: PVRSRVReleaseHandle failed")); 4405 PVR_DPF((PVR_DBG_ERROR, "PVRSRVFreeSyncInfoBW: PVRSRVReleaseHandle failed"));
3571 psFreeSyncInfoOUT->eError = eError; 4406 psFreeSyncInfoOUT->eError = eError;
3572 return 0; 4407 return 0;
3573 } 4408 }
3574 4409
3575 eError = ResManFreeResByPtr(psSyncInfo->hResItem); 4410 eError = ResManFreeResByPtr(psSyncInfo->hResItem);
3576 if (eError != PVRSRV_OK) 4411 if (eError != PVRSRV_OK)
3577 { 4412 {
3578 PVR_DPF((PVR_DBG_ERROR, "PVRSRVFreeSyncInfoBW: ResManFreeResByPtr failed")); 4413 PVR_DPF((PVR_DBG_ERROR, "PVRSRVFreeSyncInfoBW: ResManFreeResByPtr failed"));
3579 psFreeSyncInfoOUT->eError = eError; 4414 psFreeSyncInfoOUT->eError = eError;
3580 return 0; 4415 return 0;
3581 } 4416 }
3582 4417
3583 return 0; 4418 return 0;
3584} 4419}
3585 4420
3586 4421
3587PVRSRV_ERROR 4422PVRSRV_ERROR
3588CommonBridgeInit(IMG_VOID) 4423CommonBridgeInit(IMG_VOID)
3589{ 4424{
3590 IMG_UINT32 i; 4425 IMG_UINT32 i;
3591 4426
3592 SetDispatchTableEntry(PVRSRV_BRIDGE_ENUM_DEVICES, PVRSRVEnumerateDevicesBW); 4427 SetDispatchTableEntry(PVRSRV_BRIDGE_ENUM_DEVICES, PVRSRVEnumerateDevicesBW);
3593 SetDispatchTableEntry(PVRSRV_BRIDGE_ACQUIRE_DEVICEINFO, PVRSRVAcquireDeviceDataBW); 4428 SetDispatchTableEntry(PVRSRV_BRIDGE_ACQUIRE_DEVICEINFO, PVRSRVAcquireDeviceDataBW);
3594 SetDispatchTableEntry(PVRSRV_BRIDGE_RELEASE_DEVICEINFO, DummyBW); 4429 SetDispatchTableEntry(PVRSRV_BRIDGE_RELEASE_DEVICEINFO, DummyBW);
3595 SetDispatchTableEntry(PVRSRV_BRIDGE_CREATE_DEVMEMCONTEXT, PVRSRVCreateDeviceMemContextBW); 4430 SetDispatchTableEntry(PVRSRV_BRIDGE_CREATE_DEVMEMCONTEXT, PVRSRVCreateDeviceMemContextBW);
3596 SetDispatchTableEntry(PVRSRV_BRIDGE_DESTROY_DEVMEMCONTEXT, PVRSRVDestroyDeviceMemContextBW); 4431 SetDispatchTableEntry(PVRSRV_BRIDGE_DESTROY_DEVMEMCONTEXT, PVRSRVDestroyDeviceMemContextBW);
3597 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_DEVMEM_HEAPINFO, PVRSRVGetDeviceMemHeapInfoBW); 4432 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_DEVMEM_HEAPINFO, PVRSRVGetDeviceMemHeapInfoBW);
3598 SetDispatchTableEntry(PVRSRV_BRIDGE_ALLOC_DEVICEMEM, PVRSRVAllocDeviceMemBW); 4433 SetDispatchTableEntry(PVRSRV_BRIDGE_ALLOC_DEVICEMEM, PVRSRVAllocDeviceMemBW);
3599 SetDispatchTableEntry(PVRSRV_BRIDGE_FREE_DEVICEMEM, PVRSRVFreeDeviceMemBW); 4434 SetDispatchTableEntry(PVRSRV_BRIDGE_FREE_DEVICEMEM, PVRSRVFreeDeviceMemBW);
3600 SetDispatchTableEntry(PVRSRV_BRIDGE_GETFREE_DEVICEMEM, PVRSRVGetFreeDeviceMemBW); 4435 SetDispatchTableEntry(PVRSRV_BRIDGE_GETFREE_DEVICEMEM, PVRSRVGetFreeDeviceMemBW);
3601 SetDispatchTableEntry(PVRSRV_BRIDGE_CREATE_COMMANDQUEUE, DummyBW); 4436 SetDispatchTableEntry(PVRSRV_BRIDGE_CREATE_COMMANDQUEUE, DummyBW);
3602 SetDispatchTableEntry(PVRSRV_BRIDGE_DESTROY_COMMANDQUEUE, DummyBW); 4437 SetDispatchTableEntry(PVRSRV_BRIDGE_DESTROY_COMMANDQUEUE, DummyBW);
3603 SetDispatchTableEntry(PVRSRV_BRIDGE_MHANDLE_TO_MMAP_DATA, PVRMMapOSMemHandleToMMapDataBW); 4438 SetDispatchTableEntry(PVRSRV_BRIDGE_MHANDLE_TO_MMAP_DATA, PVRMMapOSMemHandleToMMapDataBW);
3604 SetDispatchTableEntry(PVRSRV_BRIDGE_CONNECT_SERVICES, PVRSRVConnectBW); 4439 SetDispatchTableEntry(PVRSRV_BRIDGE_CONNECT_SERVICES, PVRSRVConnectBW);
3605 SetDispatchTableEntry(PVRSRV_BRIDGE_DISCONNECT_SERVICES, PVRSRVDisconnectBW); 4440 SetDispatchTableEntry(PVRSRV_BRIDGE_DISCONNECT_SERVICES, PVRSRVDisconnectBW);
3606 SetDispatchTableEntry(PVRSRV_BRIDGE_WRAP_DEVICE_MEM, DummyBW); 4441 SetDispatchTableEntry(PVRSRV_BRIDGE_WRAP_DEVICE_MEM, DummyBW);
3607 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_DEVICEMEMINFO, DummyBW); 4442 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_DEVICEMEMINFO, DummyBW);
3608 SetDispatchTableEntry(PVRSRV_BRIDGE_RESERVE_DEV_VIRTMEM , DummyBW); 4443 SetDispatchTableEntry(PVRSRV_BRIDGE_RESERVE_DEV_VIRTMEM , DummyBW);
3609 SetDispatchTableEntry(PVRSRV_BRIDGE_FREE_DEV_VIRTMEM, DummyBW); 4444 SetDispatchTableEntry(PVRSRV_BRIDGE_FREE_DEV_VIRTMEM, DummyBW);
3610 SetDispatchTableEntry(PVRSRV_BRIDGE_MAP_EXT_MEMORY, DummyBW); 4445 SetDispatchTableEntry(PVRSRV_BRIDGE_MAP_EXT_MEMORY, DummyBW);
3611 SetDispatchTableEntry(PVRSRV_BRIDGE_UNMAP_EXT_MEMORY, DummyBW); 4446 SetDispatchTableEntry(PVRSRV_BRIDGE_UNMAP_EXT_MEMORY, DummyBW);
3612 SetDispatchTableEntry(PVRSRV_BRIDGE_MAP_DEV_MEMORY, PVRSRVMapDeviceMemoryBW); 4447 SetDispatchTableEntry(PVRSRV_BRIDGE_MAP_DEV_MEMORY, PVRSRVMapDeviceMemoryBW);
3613 SetDispatchTableEntry(PVRSRV_BRIDGE_UNMAP_DEV_MEMORY, PVRSRVUnmapDeviceMemoryBW); 4448 SetDispatchTableEntry(PVRSRV_BRIDGE_UNMAP_DEV_MEMORY, PVRSRVUnmapDeviceMemoryBW);
3614 SetDispatchTableEntry(PVRSRV_BRIDGE_MAP_DEVICECLASS_MEMORY, PVRSRVMapDeviceClassMemoryBW); 4449 SetDispatchTableEntry(PVRSRV_BRIDGE_MAP_DEVICECLASS_MEMORY, PVRSRVMapDeviceClassMemoryBW);
3615 SetDispatchTableEntry(PVRSRV_BRIDGE_UNMAP_DEVICECLASS_MEMORY, PVRSRVUnmapDeviceClassMemoryBW); 4450 SetDispatchTableEntry(PVRSRV_BRIDGE_UNMAP_DEVICECLASS_MEMORY, PVRSRVUnmapDeviceClassMemoryBW);
3616 SetDispatchTableEntry(PVRSRV_BRIDGE_MAP_MEM_INFO_TO_USER, DummyBW); 4451 SetDispatchTableEntry(PVRSRV_BRIDGE_MAP_MEM_INFO_TO_USER, DummyBW);
3617 SetDispatchTableEntry(PVRSRV_BRIDGE_UNMAP_MEM_INFO_FROM_USER, DummyBW); 4452 SetDispatchTableEntry(PVRSRV_BRIDGE_UNMAP_MEM_INFO_FROM_USER, DummyBW);
3618 SetDispatchTableEntry(PVRSRV_BRIDGE_EXPORT_DEVICEMEM, PVRSRVExportDeviceMemBW); 4453 SetDispatchTableEntry(PVRSRV_BRIDGE_EXPORT_DEVICEMEM, PVRSRVExportDeviceMemBW);
3619 SetDispatchTableEntry(PVRSRV_BRIDGE_RELEASE_MMAP_DATA, PVRMMapReleaseMMapDataBW); 4454 SetDispatchTableEntry(PVRSRV_BRIDGE_RELEASE_MMAP_DATA, PVRMMapReleaseMMapDataBW);
3620 4455 SetDispatchTableEntry(PVRSRV_BRIDGE_CHG_DEV_MEM_ATTRIBS, PVRSRVChangeDeviceMemoryAttributesBW);
3621 4456 SetDispatchTableEntry(PVRSRV_BRIDGE_MAP_DEV_MEMORY_2, PVRSRVMapDeviceMemoryBW);
3622 SetDispatchTableEntry(PVRSRV_BRIDGE_PROCESS_SIMISR_EVENT, DummyBW); 4457 SetDispatchTableEntry(PVRSRV_BRIDGE_EXPORT_DEVICEMEM_2, PVRSRVExportDeviceMemBW);
3623 SetDispatchTableEntry(PVRSRV_BRIDGE_REGISTER_SIM_PROCESS, DummyBW); 4458
3624 SetDispatchTableEntry(PVRSRV_BRIDGE_UNREGISTER_SIM_PROCESS, DummyBW); 4459
3625 4460 SetDispatchTableEntry(PVRSRV_BRIDGE_PROCESS_SIMISR_EVENT, DummyBW);
3626 4461 SetDispatchTableEntry(PVRSRV_BRIDGE_REGISTER_SIM_PROCESS, DummyBW);
3627 SetDispatchTableEntry(PVRSRV_BRIDGE_MAPPHYSTOUSERSPACE, DummyBW); 4462 SetDispatchTableEntry(PVRSRV_BRIDGE_UNREGISTER_SIM_PROCESS, DummyBW);
3628 SetDispatchTableEntry(PVRSRV_BRIDGE_UNMAPPHYSTOUSERSPACE, DummyBW); 4463
3629 SetDispatchTableEntry(PVRSRV_BRIDGE_GETPHYSTOUSERSPACEMAP, DummyBW); 4464
3630 4465 SetDispatchTableEntry(PVRSRV_BRIDGE_MAPPHYSTOUSERSPACE, DummyBW);
3631 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_FB_STATS, DummyBW); 4466 SetDispatchTableEntry(PVRSRV_BRIDGE_UNMAPPHYSTOUSERSPACE, DummyBW);
3632 4467 SetDispatchTableEntry(PVRSRV_BRIDGE_GETPHYSTOUSERSPACEMAP, DummyBW);
3633 4468
3634 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_MISC_INFO, PVRSRVGetMiscInfoBW); 4469 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_FB_STATS, DummyBW);
3635 SetDispatchTableEntry(PVRSRV_BRIDGE_RELEASE_MISC_INFO, DummyBW); 4470
3636 4471
3637 4472 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_MISC_INFO, PVRSRVGetMiscInfoBW);
4473 SetDispatchTableEntry(PVRSRV_BRIDGE_RELEASE_MISC_INFO, DummyBW);
4474
4475
3638#if defined (SUPPORT_OVERLAY_ROTATE_BLIT) 4476#if defined (SUPPORT_OVERLAY_ROTATE_BLIT)
3639 SetDispatchTableEntry(PVRSRV_BRIDGE_INIT_3D_OVL_BLT_RES, DummyBW); 4477 SetDispatchTableEntry(PVRSRV_BRIDGE_INIT_3D_OVL_BLT_RES, DummyBW);
3640 SetDispatchTableEntry(PVRSRV_BRIDGE_DEINIT_3D_OVL_BLT_RES, DummyBW); 4478 SetDispatchTableEntry(PVRSRV_BRIDGE_DEINIT_3D_OVL_BLT_RES, DummyBW);
3641#endif 4479#endif
3642 4480
3643 4481
3644 4482
3645#if defined(PDUMP) 4483#if defined(PDUMP)
3646 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_INIT, DummyBW); 4484 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_INIT, DummyBW);
3647 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_MEMPOL, PDumpMemPolBW); 4485 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_MEMPOL, PDumpMemPolBW);
3648 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_DUMPMEM, PDumpMemBW); 4486 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_DUMPMEM, PDumpMemBW);
3649 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_REG, PDumpRegWithFlagsBW); 4487 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_REG, PDumpRegWithFlagsBW);
3650 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_REGPOL, PDumpRegPolBW); 4488 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_REGPOL, PDumpRegPolBW);
3651 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_COMMENT, PDumpCommentBW); 4489 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_COMMENT, PDumpCommentBW);
3652 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_SETFRAME, PDumpSetFrameBW); 4490 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_SETFRAME, PDumpSetFrameBW);
3653 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_ISCAPTURING, PDumpIsCaptureFrameBW); 4491 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_ISCAPTURING, PDumpIsCaptureFrameBW);
3654 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_DUMPBITMAP, PDumpBitmapBW); 4492 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_DUMPBITMAP, PDumpBitmapBW);
3655 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_DUMPREADREG, PDumpReadRegBW); 4493 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_DUMPREADREG, PDumpReadRegBW);
3656 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_SYNCPOL, PDumpSyncPolBW); 4494 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_SYNCPOL, PDumpSyncPolBW);
3657 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_DUMPSYNC, PDumpSyncDumpBW); 4495 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_DUMPSYNC, PDumpSyncDumpBW);
3658 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_DRIVERINFO, PDumpDriverInfoBW); 4496 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_MEMPAGES, PDumpMemPagesBW);
3659 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_DUMPPDDEVPADDR, PDumpPDDevPAddrBW); 4497 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_DRIVERINFO, PDumpDriverInfoBW);
3660 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_CYCLE_COUNT_REG_READ, PDumpCycleCountRegReadBW); 4498 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_DUMPPDDEVPADDR, PDumpPDDevPAddrBW);
3661 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_STARTINITPHASE, PDumpStartInitPhaseBW); 4499 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_CYCLE_COUNT_REG_READ, PDumpCycleCountRegReadBW);
3662 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_STOPINITPHASE, PDumpStopInitPhaseBW); 4500 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_STARTINITPHASE, PDumpStartInitPhaseBW);
3663#endif 4501 SetDispatchTableEntry(PVRSRV_BRIDGE_PDUMP_STOPINITPHASE, PDumpStopInitPhaseBW);
3664 4502#endif
3665 4503
3666 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_OEMJTABLE, DummyBW); 4504
3667 4505 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_OEMJTABLE, DummyBW);
3668 4506
3669 SetDispatchTableEntry(PVRSRV_BRIDGE_ENUM_CLASS, PVRSRVEnumerateDCBW); 4507
3670 4508 SetDispatchTableEntry(PVRSRV_BRIDGE_ENUM_CLASS, PVRSRVEnumerateDCBW);
3671 4509
3672 SetDispatchTableEntry(PVRSRV_BRIDGE_OPEN_DISPCLASS_DEVICE, PVRSRVOpenDCDeviceBW); 4510
3673 SetDispatchTableEntry(PVRSRV_BRIDGE_CLOSE_DISPCLASS_DEVICE, PVRSRVCloseDCDeviceBW); 4511 SetDispatchTableEntry(PVRSRV_BRIDGE_OPEN_DISPCLASS_DEVICE, PVRSRVOpenDCDeviceBW);
3674 SetDispatchTableEntry(PVRSRV_BRIDGE_ENUM_DISPCLASS_FORMATS, PVRSRVEnumDCFormatsBW); 4512 SetDispatchTableEntry(PVRSRV_BRIDGE_CLOSE_DISPCLASS_DEVICE, PVRSRVCloseDCDeviceBW);
3675 SetDispatchTableEntry(PVRSRV_BRIDGE_ENUM_DISPCLASS_DIMS, PVRSRVEnumDCDimsBW); 4513 SetDispatchTableEntry(PVRSRV_BRIDGE_ENUM_DISPCLASS_FORMATS, PVRSRVEnumDCFormatsBW);
3676 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_DISPCLASS_SYSBUFFER, PVRSRVGetDCSystemBufferBW); 4514 SetDispatchTableEntry(PVRSRV_BRIDGE_ENUM_DISPCLASS_DIMS, PVRSRVEnumDCDimsBW);
3677 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_DISPCLASS_INFO, PVRSRVGetDCInfoBW); 4515 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_DISPCLASS_SYSBUFFER, PVRSRVGetDCSystemBufferBW);
3678 SetDispatchTableEntry(PVRSRV_BRIDGE_CREATE_DISPCLASS_SWAPCHAIN, PVRSRVCreateDCSwapChainBW); 4516 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_DISPCLASS_INFO, PVRSRVGetDCInfoBW);
3679 SetDispatchTableEntry(PVRSRV_BRIDGE_DESTROY_DISPCLASS_SWAPCHAIN, PVRSRVDestroyDCSwapChainBW); 4517 SetDispatchTableEntry(PVRSRV_BRIDGE_CREATE_DISPCLASS_SWAPCHAIN, PVRSRVCreateDCSwapChainBW);
3680 SetDispatchTableEntry(PVRSRV_BRIDGE_SET_DISPCLASS_DSTRECT, PVRSRVSetDCDstRectBW); 4518 SetDispatchTableEntry(PVRSRV_BRIDGE_DESTROY_DISPCLASS_SWAPCHAIN, PVRSRVDestroyDCSwapChainBW);
3681 SetDispatchTableEntry(PVRSRV_BRIDGE_SET_DISPCLASS_SRCRECT, PVRSRVSetDCSrcRectBW); 4519 SetDispatchTableEntry(PVRSRV_BRIDGE_SET_DISPCLASS_DSTRECT, PVRSRVSetDCDstRectBW);
3682 SetDispatchTableEntry(PVRSRV_BRIDGE_SET_DISPCLASS_DSTCOLOURKEY, PVRSRVSetDCDstColourKeyBW); 4520 SetDispatchTableEntry(PVRSRV_BRIDGE_SET_DISPCLASS_SRCRECT, PVRSRVSetDCSrcRectBW);
3683 SetDispatchTableEntry(PVRSRV_BRIDGE_SET_DISPCLASS_SRCCOLOURKEY, PVRSRVSetDCSrcColourKeyBW); 4521 SetDispatchTableEntry(PVRSRV_BRIDGE_SET_DISPCLASS_DSTCOLOURKEY, PVRSRVSetDCDstColourKeyBW);
3684 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_DISPCLASS_BUFFERS, PVRSRVGetDCBuffersBW); 4522 SetDispatchTableEntry(PVRSRV_BRIDGE_SET_DISPCLASS_SRCCOLOURKEY, PVRSRVSetDCSrcColourKeyBW);
3685 SetDispatchTableEntry(PVRSRV_BRIDGE_SWAP_DISPCLASS_TO_BUFFER, PVRSRVSwapToDCBufferBW); 4523 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_DISPCLASS_BUFFERS, PVRSRVGetDCBuffersBW);
3686 SetDispatchTableEntry(PVRSRV_BRIDGE_SWAP_DISPCLASS_TO_SYSTEM, PVRSRVSwapToDCSystemBW); 4524 SetDispatchTableEntry(PVRSRV_BRIDGE_SWAP_DISPCLASS_TO_BUFFER, PVRSRVSwapToDCBufferBW);
3687 4525 SetDispatchTableEntry(PVRSRV_BRIDGE_SWAP_DISPCLASS_TO_SYSTEM, PVRSRVSwapToDCSystemBW);
3688 4526
3689 SetDispatchTableEntry(PVRSRV_BRIDGE_OPEN_BUFFERCLASS_DEVICE, PVRSRVOpenBCDeviceBW); 4527
3690 SetDispatchTableEntry(PVRSRV_BRIDGE_CLOSE_BUFFERCLASS_DEVICE, PVRSRVCloseBCDeviceBW); 4528 SetDispatchTableEntry(PVRSRV_BRIDGE_OPEN_BUFFERCLASS_DEVICE, PVRSRVOpenBCDeviceBW);
3691 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_BUFFERCLASS_INFO, PVRSRVGetBCInfoBW); 4529 SetDispatchTableEntry(PVRSRV_BRIDGE_CLOSE_BUFFERCLASS_DEVICE, PVRSRVCloseBCDeviceBW);
3692 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_BUFFERCLASS_BUFFER, PVRSRVGetBCBufferBW); 4530 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_BUFFERCLASS_INFO, PVRSRVGetBCInfoBW);
3693 4531 SetDispatchTableEntry(PVRSRV_BRIDGE_GET_BUFFERCLASS_BUFFER, PVRSRVGetBCBufferBW);
3694 4532
3695 SetDispatchTableEntry(PVRSRV_BRIDGE_WRAP_EXT_MEMORY, PVRSRVWrapExtMemoryBW); 4533
3696 SetDispatchTableEntry(PVRSRV_BRIDGE_UNWRAP_EXT_MEMORY, PVRSRVUnwrapExtMemoryBW); 4534 SetDispatchTableEntry(PVRSRV_BRIDGE_WRAP_EXT_MEMORY, PVRSRVWrapExtMemoryBW);
3697 4535 SetDispatchTableEntry(PVRSRV_BRIDGE_UNWRAP_EXT_MEMORY, PVRSRVUnwrapExtMemoryBW);
3698 4536
3699 SetDispatchTableEntry(PVRSRV_BRIDGE_ALLOC_SHARED_SYS_MEM, PVRSRVAllocSharedSysMemoryBW); 4537
3700 SetDispatchTableEntry(PVRSRV_BRIDGE_FREE_SHARED_SYS_MEM, PVRSRVFreeSharedSysMemoryBW); 4538 SetDispatchTableEntry(PVRSRV_BRIDGE_ALLOC_SHARED_SYS_MEM, PVRSRVAllocSharedSysMemoryBW);
3701 SetDispatchTableEntry(PVRSRV_BRIDGE_MAP_MEMINFO_MEM, PVRSRVMapMemInfoMemBW); 4539 SetDispatchTableEntry(PVRSRV_BRIDGE_FREE_SHARED_SYS_MEM, PVRSRVFreeSharedSysMemoryBW);
3702 4540 SetDispatchTableEntry(PVRSRV_BRIDGE_MAP_MEMINFO_MEM, PVRSRVMapMemInfoMemBW);
3703 4541
3704 SetDispatchTableEntry(PVRSRV_BRIDGE_GETMMU_PD_DEVPADDR, MMU_GetPDDevPAddrBW); 4542
3705 4543 SetDispatchTableEntry(PVRSRV_BRIDGE_GETMMU_PD_DEVPADDR, MMU_GetPDDevPAddrBW);
3706 4544
3707 SetDispatchTableEntry(PVRSRV_BRIDGE_INITSRV_CONNECT, &PVRSRVInitSrvConnectBW); 4545
3708 SetDispatchTableEntry(PVRSRV_BRIDGE_INITSRV_DISCONNECT, &PVRSRVInitSrvDisconnectBW); 4546 SetDispatchTableEntry(PVRSRV_BRIDGE_INITSRV_CONNECT, &PVRSRVInitSrvConnectBW);
3709 4547 SetDispatchTableEntry(PVRSRV_BRIDGE_INITSRV_DISCONNECT, &PVRSRVInitSrvDisconnectBW);
3710 4548
3711 SetDispatchTableEntry(PVRSRV_BRIDGE_EVENT_OBJECT_WAIT, &PVRSRVEventObjectWaitBW); 4549
3712 SetDispatchTableEntry(PVRSRV_BRIDGE_EVENT_OBJECT_OPEN, &PVRSRVEventObjectOpenBW); 4550 SetDispatchTableEntry(PVRSRV_BRIDGE_EVENT_OBJECT_WAIT, &PVRSRVEventObjectWaitBW);
3713 SetDispatchTableEntry(PVRSRV_BRIDGE_EVENT_OBJECT_CLOSE, &PVRSRVEventObjectCloseBW); 4551 SetDispatchTableEntry(PVRSRV_BRIDGE_EVENT_OBJECT_OPEN, &PVRSRVEventObjectOpenBW);
3714 4552 SetDispatchTableEntry(PVRSRV_BRIDGE_EVENT_OBJECT_CLOSE, &PVRSRVEventObjectCloseBW);
3715 SetDispatchTableEntry(PVRSRV_BRIDGE_CREATE_SYNC_INFO_MOD_OBJ, PVRSRVCreateSyncInfoModObjBW); 4553
3716 SetDispatchTableEntry(PVRSRV_BRIDGE_DESTROY_SYNC_INFO_MOD_OBJ, PVRSRVDestroySyncInfoModObjBW); 4554 SetDispatchTableEntry(PVRSRV_BRIDGE_CREATE_SYNC_INFO_MOD_OBJ, PVRSRVCreateSyncInfoModObjBW);
3717 SetDispatchTableEntry(PVRSRV_BRIDGE_MODIFY_PENDING_SYNC_OPS, PVRSRVModifyPendingSyncOpsBW); 4555 SetDispatchTableEntry(PVRSRV_BRIDGE_DESTROY_SYNC_INFO_MOD_OBJ, PVRSRVDestroySyncInfoModObjBW);
3718 SetDispatchTableEntry(PVRSRV_BRIDGE_MODIFY_COMPLETE_SYNC_OPS, PVRSRVModifyCompleteSyncOpsBW); 4556 SetDispatchTableEntry(PVRSRV_BRIDGE_MODIFY_PENDING_SYNC_OPS, PVRSRVModifyPendingSyncOpsBW);
3719 SetDispatchTableEntry(PVRSRV_BRIDGE_SYNC_OPS_FLUSH_TO_MOD_OBJ, PVRSRVSyncOpsFlushToModObjBW); 4557 SetDispatchTableEntry(PVRSRV_BRIDGE_MODIFY_COMPLETE_SYNC_OPS, PVRSRVModifyCompleteSyncOpsBW);
3720 SetDispatchTableEntry(PVRSRV_BRIDGE_SYNC_OPS_FLUSH_TO_DELTA, PVRSRVSyncOpsFlushToDeltaBW); 4558 SetDispatchTableEntry(PVRSRV_BRIDGE_SYNC_OPS_TAKE_TOKEN, PVRSRVSyncOpsTakeTokenBW);
3721 SetDispatchTableEntry(PVRSRV_BRIDGE_ALLOC_SYNC_INFO, PVRSRVAllocSyncInfoBW); 4559 SetDispatchTableEntry(PVRSRV_BRIDGE_SYNC_OPS_FLUSH_TO_TOKEN, PVRSRVSyncOpsFlushToTokenBW);
3722 SetDispatchTableEntry(PVRSRV_BRIDGE_FREE_SYNC_INFO, PVRSRVFreeSyncInfoBW); 4560 SetDispatchTableEntry(PVRSRV_BRIDGE_SYNC_OPS_FLUSH_TO_MOD_OBJ, PVRSRVSyncOpsFlushToModObjBW);
4561 SetDispatchTableEntry(PVRSRV_BRIDGE_SYNC_OPS_FLUSH_TO_DELTA, PVRSRVSyncOpsFlushToDeltaBW);
4562 SetDispatchTableEntry(PVRSRV_BRIDGE_ALLOC_SYNC_INFO, PVRSRVAllocSyncInfoBW);
4563 SetDispatchTableEntry(PVRSRV_BRIDGE_FREE_SYNC_INFO, PVRSRVFreeSyncInfoBW);
3723 4564
3724#if defined (SUPPORT_SGX) 4565#if defined (SUPPORT_SGX)
3725 SetSGXDispatchTableEntry(); 4566 SetSGXDispatchTableEntry();
3726#endif 4567#endif
3727#if defined (SUPPORT_VGX) 4568#if defined (SUPPORT_VGX)
3728 SetVGXDispatchTableEntry(); 4569 SetVGXDispatchTableEntry();
3729#endif 4570#endif
3730#if defined (SUPPORT_MSVDX) 4571#if defined (SUPPORT_MSVDX)
3731 SetMSVDXDispatchTableEntry(); 4572 SetMSVDXDispatchTableEntry();
3732#endif 4573#endif
3733 4574
3734 4575
3735 4576
3736 4577
3737 for(i=0;i<BRIDGE_DISPATCH_TABLE_ENTRY_COUNT;i++) 4578 for(i=0;i<BRIDGE_DISPATCH_TABLE_ENTRY_COUNT;i++)
3738 { 4579 {
3739 if(!g_BridgeDispatchTable[i].pfFunction) 4580 if(!g_BridgeDispatchTable[i].pfFunction)
3740 { 4581 {
3741 g_BridgeDispatchTable[i].pfFunction = &DummyBW; 4582 g_BridgeDispatchTable[i].pfFunction = &DummyBW;
3742#if defined(DEBUG_BRIDGE_KM) 4583#if defined(DEBUG_BRIDGE_KM)
3743 g_BridgeDispatchTable[i].pszIOCName = "_PVRSRV_BRIDGE_DUMMY"; 4584 g_BridgeDispatchTable[i].pszIOCName = "_PVRSRV_BRIDGE_DUMMY";
3744 g_BridgeDispatchTable[i].pszFunctionName = "DummyBW"; 4585 g_BridgeDispatchTable[i].pszFunctionName = "DummyBW";
3745 g_BridgeDispatchTable[i].ui32CallCount = 0; 4586 g_BridgeDispatchTable[i].ui32CallCount = 0;
3746 g_BridgeDispatchTable[i].ui32CopyFromUserTotalBytes = 0; 4587 g_BridgeDispatchTable[i].ui32CopyFromUserTotalBytes = 0;
3747 g_BridgeDispatchTable[i].ui32CopyToUserTotalBytes = 0; 4588 g_BridgeDispatchTable[i].ui32CopyToUserTotalBytes = 0;
3748#endif 4589#endif
3749 } 4590 }
3750 } 4591 }
3751 4592
3752 return PVRSRV_OK; 4593 return PVRSRV_OK;
3753} 4594}
3754 4595
3755IMG_INT BridgedDispatchKM(PVRSRV_PER_PROCESS_DATA * psPerProc, 4596IMG_INT BridgedDispatchKM(PVRSRV_PER_PROCESS_DATA * psPerProc,
3756 PVRSRV_BRIDGE_PACKAGE * psBridgePackageKM) 4597 PVRSRV_BRIDGE_PACKAGE * psBridgePackageKM)
3757{ 4598{
3758 4599
3759 IMG_VOID * psBridgeIn; 4600 IMG_VOID * psBridgeIn;
3760 IMG_VOID * psBridgeOut; 4601 IMG_VOID * psBridgeOut;
3761 BridgeWrapperFunction pfBridgeHandler; 4602 BridgeWrapperFunction pfBridgeHandler;
3762 IMG_UINT32 ui32BridgeID = psBridgePackageKM->ui32BridgeID; 4603 IMG_UINT32 ui32BridgeID = psBridgePackageKM->ui32BridgeID;
3763 IMG_INT err = -EFAULT; 4604 IMG_INT err = -EFAULT;
3764 4605
3765#if defined(DEBUG_TRACE_BRIDGE_KM) 4606#if defined(DEBUG_TRACE_BRIDGE_KM)
3766 PVR_DPF((PVR_DBG_ERROR, "%s: %s", 4607 PVR_DPF((PVR_DBG_ERROR, "%s: %s",
3767 __FUNCTION__, 4608 __FUNCTION__,
3768 g_BridgeDispatchTable[ui32BridgeID].pszIOCName)); 4609 g_BridgeDispatchTable[ui32BridgeID].pszIOCName));
3769#endif 4610#endif
3770 4611
3771#if defined(DEBUG_BRIDGE_KM) 4612#if defined(DEBUG_BRIDGE_KM)
3772 g_BridgeDispatchTable[ui32BridgeID].ui32CallCount++; 4613 g_BridgeDispatchTable[ui32BridgeID].ui32CallCount++;
3773 g_BridgeGlobalStats.ui32IOCTLCount++; 4614 g_BridgeGlobalStats.ui32IOCTLCount++;
3774#endif 4615#endif
3775 4616
3776 if(!psPerProc->bInitProcess) 4617 if(!psPerProc->bInitProcess)
3777 { 4618 {
3778 if(PVRSRVGetInitServerState(PVRSRV_INIT_SERVER_RAN)) 4619 if(PVRSRVGetInitServerState(PVRSRV_INIT_SERVER_RAN))
3779 { 4620 {
3780 if(!PVRSRVGetInitServerState(PVRSRV_INIT_SERVER_SUCCESSFUL)) 4621 if(!PVRSRVGetInitServerState(PVRSRV_INIT_SERVER_SUCCESSFUL))
3781 { 4622 {
3782 PVR_DPF((PVR_DBG_ERROR, "%s: Initialisation failed. Driver unusable.", 4623 PVR_DPF((PVR_DBG_ERROR, "%s: Initialisation failed. Driver unusable.",
3783 __FUNCTION__)); 4624 __FUNCTION__));
3784 goto return_fault; 4625 goto return_fault;
3785 } 4626 }
3786 } 4627 }
3787 else 4628 else
3788 { 4629 {
3789 if(PVRSRVGetInitServerState(PVRSRV_INIT_SERVER_RUNNING)) 4630 if(PVRSRVGetInitServerState(PVRSRV_INIT_SERVER_RUNNING))
3790 { 4631 {
3791 PVR_DPF((PVR_DBG_ERROR, "%s: Initialisation is in progress", 4632 PVR_DPF((PVR_DBG_ERROR, "%s: Initialisation is in progress",
3792 __FUNCTION__)); 4633 __FUNCTION__));
3793 goto return_fault; 4634 goto return_fault;
3794 } 4635 }
3795 else 4636 else
3796 { 4637 {
3797 4638
3798 switch(ui32BridgeID) 4639 switch(ui32BridgeID)
3799 { 4640 {
3800 case PVRSRV_GET_BRIDGE_ID(PVRSRV_BRIDGE_CONNECT_SERVICES): 4641 case PVRSRV_GET_BRIDGE_ID(PVRSRV_BRIDGE_CONNECT_SERVICES):
3801 case PVRSRV_GET_BRIDGE_ID(PVRSRV_BRIDGE_DISCONNECT_SERVICES): 4642 case PVRSRV_GET_BRIDGE_ID(PVRSRV_BRIDGE_DISCONNECT_SERVICES):
3802 case PVRSRV_GET_BRIDGE_ID(PVRSRV_BRIDGE_INITSRV_CONNECT): 4643 case PVRSRV_GET_BRIDGE_ID(PVRSRV_BRIDGE_INITSRV_CONNECT):
3803 case PVRSRV_GET_BRIDGE_ID(PVRSRV_BRIDGE_INITSRV_DISCONNECT): 4644 case PVRSRV_GET_BRIDGE_ID(PVRSRV_BRIDGE_INITSRV_DISCONNECT):
3804 break; 4645 break;
3805 default: 4646 default:
3806 PVR_DPF((PVR_DBG_ERROR, "%s: Driver initialisation not completed yet.", 4647 PVR_DPF((PVR_DBG_ERROR, "%s: Driver initialisation not completed yet.",
3807 __FUNCTION__)); 4648 __FUNCTION__));
3808 goto return_fault; 4649 goto return_fault;
3809 } 4650 }
3810 } 4651 }
3811 } 4652 }
3812 } 4653 }
3813 4654
3814 4655
3815 4656
3816#if defined(__linux__) 4657#if defined(__linux__)
3817 { 4658 {
3818 4659
3819 SYS_DATA *psSysData; 4660 SYS_DATA *psSysData;
3820 4661
3821 SysAcquireData(&psSysData); 4662 SysAcquireData(&psSysData);
3822 4663
3823 4664
3824 psBridgeIn = ((ENV_DATA *)psSysData->pvEnvSpecificData)->pvBridgeData; 4665 psBridgeIn = ((ENV_DATA *)psSysData->pvEnvSpecificData)->pvBridgeData;
3825 psBridgeOut = (IMG_PVOID)((IMG_PBYTE)psBridgeIn + PVRSRV_MAX_BRIDGE_IN_SIZE); 4666 psBridgeOut = (IMG_PVOID)((IMG_PBYTE)psBridgeIn + PVRSRV_MAX_BRIDGE_IN_SIZE);
3826 4667
3827 4668
3828#if defined(DEBUG) 4669#if defined(DEBUG)
3829 PVR_ASSERT(psBridgePackageKM->ui32InBufferSize < PVRSRV_MAX_BRIDGE_IN_SIZE); 4670 PVR_ASSERT(psBridgePackageKM->ui32InBufferSize < PVRSRV_MAX_BRIDGE_IN_SIZE);
3830 PVR_ASSERT(psBridgePackageKM->ui32OutBufferSize < PVRSRV_MAX_BRIDGE_OUT_SIZE); 4671 PVR_ASSERT(psBridgePackageKM->ui32OutBufferSize < PVRSRV_MAX_BRIDGE_OUT_SIZE);
3831#endif 4672#endif
3832 4673
3833 if(psBridgePackageKM->ui32InBufferSize > 0) 4674 if(psBridgePackageKM->ui32InBufferSize > 0)
3834 { 4675 {
3835 if(!OSAccessOK(PVR_VERIFY_READ, 4676 if(!OSAccessOK(PVR_VERIFY_READ,
3836 psBridgePackageKM->pvParamIn, 4677 psBridgePackageKM->pvParamIn,
3837 psBridgePackageKM->ui32InBufferSize)) 4678 psBridgePackageKM->ui32InBufferSize))
3838 { 4679 {
3839 PVR_DPF((PVR_DBG_ERROR, "%s: Invalid pvParamIn pointer", __FUNCTION__)); 4680 PVR_DPF((PVR_DBG_ERROR, "%s: Invalid pvParamIn pointer", __FUNCTION__));
3840 } 4681 }
3841 4682
3842 if(CopyFromUserWrapper(psPerProc, 4683 if(CopyFromUserWrapper(psPerProc,
3843 ui32BridgeID, 4684 ui32BridgeID,
3844 psBridgeIn, 4685 psBridgeIn,
3845 psBridgePackageKM->pvParamIn, 4686 psBridgePackageKM->pvParamIn,
3846 psBridgePackageKM->ui32InBufferSize) 4687 psBridgePackageKM->ui32InBufferSize)
3847 != PVRSRV_OK) 4688 != PVRSRV_OK)
3848 { 4689 {
3849 goto return_fault; 4690 goto return_fault;
3850 } 4691 }
3851 } 4692 }
3852 } 4693 }
3853#else 4694#else
3854 psBridgeIn = psBridgePackageKM->pvParamIn; 4695 psBridgeIn = psBridgePackageKM->pvParamIn;
3855 psBridgeOut = psBridgePackageKM->pvParamOut; 4696 psBridgeOut = psBridgePackageKM->pvParamOut;
3856#endif 4697#endif
3857 4698
3858 if(ui32BridgeID >= (BRIDGE_DISPATCH_TABLE_ENTRY_COUNT)) 4699 if(ui32BridgeID >= (BRIDGE_DISPATCH_TABLE_ENTRY_COUNT))
3859 { 4700 {
3860 PVR_DPF((PVR_DBG_ERROR, "%s: ui32BridgeID = %d is out if range!", 4701 PVR_DPF((PVR_DBG_ERROR, "%s: ui32BridgeID = %d is out if range!",
3861 __FUNCTION__, ui32BridgeID)); 4702 __FUNCTION__, ui32BridgeID));
3862 goto return_fault; 4703 goto return_fault;
3863 } 4704 }
3864 pfBridgeHandler = 4705 pfBridgeHandler =
3865 (BridgeWrapperFunction)g_BridgeDispatchTable[ui32BridgeID].pfFunction; 4706 (BridgeWrapperFunction)g_BridgeDispatchTable[ui32BridgeID].pfFunction;
3866 err = pfBridgeHandler(ui32BridgeID, 4707 err = pfBridgeHandler(ui32BridgeID,
3867 psBridgeIn, 4708 psBridgeIn,
3868 psBridgeOut, 4709 psBridgeOut,
3869 psPerProc); 4710 psPerProc);
3870 if(err < 0) 4711 if(err < 0)
3871 { 4712 {
3872 goto return_fault; 4713 goto return_fault;
3873 } 4714 }
3874 4715
3875 4716
3876#if defined(__linux__) 4717#if defined(__linux__)
3877 4718
3878 if(CopyToUserWrapper(psPerProc, 4719 if(CopyToUserWrapper(psPerProc,
3879 ui32BridgeID, 4720 ui32BridgeID,
3880 psBridgePackageKM->pvParamOut, 4721 psBridgePackageKM->pvParamOut,
3881 psBridgeOut, 4722 psBridgeOut,
3882 psBridgePackageKM->ui32OutBufferSize) 4723 psBridgePackageKM->ui32OutBufferSize)
3883 != PVRSRV_OK) 4724 != PVRSRV_OK)
3884 { 4725 {
3885 goto return_fault; 4726 goto return_fault;
3886 } 4727 }
3887#endif 4728#endif
3888 4729
3889 err = 0; 4730 err = 0;
3890return_fault: 4731return_fault:
3891 ReleaseHandleBatch(psPerProc); 4732
3892 return err; 4733 ReleaseHandleBatch(psPerProc);
4734 return err;
3893} 4735}
3894 4736
diff --git a/drivers/gpu/pvr/bridged_pvr_bridge.h b/drivers/gpu/pvr/bridged_pvr_bridge.h
index 004257429bd..6106e6f8bdb 100644
--- a/drivers/gpu/pvr/bridged_pvr_bridge.h
+++ b/drivers/gpu/pvr/bridged_pvr_bridge.h
@@ -83,7 +83,7 @@ CopyToUserWrapper(PVRSRV_PER_PROCESS_DATA *pProcData,
83#define ASSIGN_AND_EXIT_ON_ERROR(error, src) \ 83#define ASSIGN_AND_EXIT_ON_ERROR(error, src) \
84 ASSIGN_AND_RETURN_ON_ERROR(error, src, 0) 84 ASSIGN_AND_RETURN_ON_ERROR(error, src, 0)
85 85
86#if defined (PVR_SECURE_HANDLES) 86#if defined (PVR_SECURE_HANDLES) || defined (SUPPORT_SID_INTERFACE)
87#ifdef INLINE_IS_PRAGMA 87#ifdef INLINE_IS_PRAGMA
88#pragma inline(NewHandleBatch) 88#pragma inline(NewHandleBatch)
89#endif 89#endif
diff --git a/drivers/gpu/pvr/bridged_support.c b/drivers/gpu/pvr/bridged_support.c
index e10e577121f..de95ef82d0a 100644
--- a/drivers/gpu/pvr/bridged_support.c
+++ b/drivers/gpu/pvr/bridged_support.c
@@ -30,7 +30,11 @@
30 30
31 31
32PVRSRV_ERROR 32PVRSRV_ERROR
33#if defined (SUPPORT_SID_INTERFACE)
34PVRSRVLookupOSMemHandle(PVRSRV_HANDLE_BASE *psHandleBase, IMG_HANDLE *phOSMemHandle, IMG_SID hMHandle)
35#else
33PVRSRVLookupOSMemHandle(PVRSRV_HANDLE_BASE *psHandleBase, IMG_HANDLE *phOSMemHandle, IMG_HANDLE hMHandle) 36PVRSRVLookupOSMemHandle(PVRSRV_HANDLE_BASE *psHandleBase, IMG_HANDLE *phOSMemHandle, IMG_HANDLE hMHandle)
37#endif
34{ 38{
35 IMG_HANDLE hMHandleInt; 39 IMG_HANDLE hMHandleInt;
36 PVRSRV_HANDLE_TYPE eHandleType; 40 PVRSRV_HANDLE_TYPE eHandleType;
@@ -47,7 +51,7 @@ PVRSRVLookupOSMemHandle(PVRSRV_HANDLE_BASE *psHandleBase, IMG_HANDLE *phOSMemHan
47 51
48 switch(eHandleType) 52 switch(eHandleType)
49 { 53 {
50#if defined(PVR_SECURE_HANDLES) 54#if defined(PVR_SECURE_HANDLES) || defined (SUPPORT_SID_INTERFACE)
51 case PVRSRV_HANDLE_TYPE_MEM_INFO: 55 case PVRSRV_HANDLE_TYPE_MEM_INFO:
52 case PVRSRV_HANDLE_TYPE_MEM_INFO_REF: 56 case PVRSRV_HANDLE_TYPE_MEM_INFO_REF:
53 case PVRSRV_HANDLE_TYPE_SHARED_SYS_MEM_INFO: 57 case PVRSRV_HANDLE_TYPE_SHARED_SYS_MEM_INFO:
diff --git a/drivers/gpu/pvr/bridged_support.h b/drivers/gpu/pvr/bridged_support.h
index 371715d6ea8..3c222e5b351 100644
--- a/drivers/gpu/pvr/bridged_support.h
+++ b/drivers/gpu/pvr/bridged_support.h
@@ -33,7 +33,11 @@
33extern "C" { 33extern "C" {
34#endif 34#endif
35 35
36#if defined (SUPPORT_SID_INTERFACE)
37PVRSRV_ERROR PVRSRVLookupOSMemHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phOSMemHandle, IMG_SID hMHandle);
38#else
36PVRSRV_ERROR PVRSRVLookupOSMemHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phOSMemHandle, IMG_HANDLE hMHandle); 39PVRSRV_ERROR PVRSRVLookupOSMemHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phOSMemHandle, IMG_HANDLE hMHandle);
40#endif
37 41
38#if defined (__cplusplus) 42#if defined (__cplusplus)
39} 43}
diff --git a/drivers/gpu/pvr/buffer_manager.c b/drivers/gpu/pvr/buffer_manager.c
index 32367e215f8..7026a58d1bc 100644
--- a/drivers/gpu/pvr/buffer_manager.c
+++ b/drivers/gpu/pvr/buffer_manager.c
@@ -787,8 +787,11 @@ static PVRSRV_ERROR BM_DestroyContextCallBack(IMG_PVOID pvParam,
787 } 787 }
788 else 788 else
789 { 789 {
790 790 if (pBMContext->ppsThis != IMG_NULL)
791 List_BM_CONTEXT_Remove(pBMContext); 791 {
792
793 List_BM_CONTEXT_Remove(pBMContext);
794 }
792 } 795 }
793 796
794 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(BM_CONTEXT), pBMContext, IMG_NULL); 797 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(BM_CONTEXT), pBMContext, IMG_NULL);
@@ -1006,6 +1009,11 @@ BM_CreateHeap (IMG_HANDLE hBMContext,
1006 psDeviceNode = pBMContext->psDeviceNode; 1009 psDeviceNode = pBMContext->psDeviceNode;
1007 1010
1008 1011
1012
1013 PVR_ASSERT((psDevMemHeapInfo->ui32HeapSize & (psDevMemHeapInfo->ui32DataPageSize - 1)) == 0);
1014 PVR_ASSERT(psDevMemHeapInfo->ui32HeapSize > 0);
1015
1016
1009 1017
1010 1018
1011 1019
@@ -1096,7 +1104,7 @@ ErrorExit:
1096 if (psBMHeap->pMMUHeap != IMG_NULL) 1104 if (psBMHeap->pMMUHeap != IMG_NULL)
1097 { 1105 {
1098 psDeviceNode->pfnMMUDelete (psBMHeap->pMMUHeap); 1106 psDeviceNode->pfnMMUDelete (psBMHeap->pMMUHeap);
1099 psDeviceNode->pfnMMUFinalise (pBMContext->psMMUContext); 1107
1100 } 1108 }
1101 1109
1102 1110
@@ -1379,6 +1387,11 @@ BM_Wrap ( IMG_HANDLE hDevMemHeap,
1379 1387
1380 return IMG_TRUE; 1388 return IMG_TRUE;
1381 } 1389 }
1390 else
1391 {
1392
1393 HASH_Remove(psBMContext->pBufferHash, (IMG_UINTPTR_T)sHashAddress.uiAddr);
1394 }
1382 } 1395 }
1383 1396
1384 1397
@@ -1567,7 +1580,7 @@ DevMemoryAlloc (BM_CONTEXT *pBMContext,
1567{ 1580{
1568 PVRSRV_DEVICE_NODE *psDeviceNode; 1581 PVRSRV_DEVICE_NODE *psDeviceNode;
1569#ifdef PDUMP 1582#ifdef PDUMP
1570 IMG_UINT32 ui32PDumpSize = pMapping->uSize; 1583 IMG_UINT32 ui32PDumpSize = (IMG_UINT32)pMapping->uSize;
1571#endif 1584#endif
1572 1585
1573 psDeviceNode = pBMContext->psDeviceNode; 1586 psDeviceNode = pBMContext->psDeviceNode;
@@ -1613,8 +1626,8 @@ DevMemoryAlloc (BM_CONTEXT *pBMContext,
1613#if defined(SUPPORT_PDUMP_MULTI_PROCESS) 1626#if defined(SUPPORT_PDUMP_MULTI_PROCESS)
1614 psDeviceNode->pfnMMUIsHeapShared(pMapping->pBMHeap->pMMUHeap), 1627 psDeviceNode->pfnMMUIsHeapShared(pMapping->pBMHeap->pMMUHeap),
1615#else 1628#else
1616 IMG_FALSE, 1629 IMG_FALSE,
1617#endif 1630#endif
1618 (IMG_HANDLE)pMapping); 1631 (IMG_HANDLE)pMapping);
1619#endif 1632#endif
1620 1633
@@ -1677,35 +1690,321 @@ static IMG_VOID
1677DevMemoryFree (BM_MAPPING *pMapping) 1690DevMemoryFree (BM_MAPPING *pMapping)
1678{ 1691{
1679 PVRSRV_DEVICE_NODE *psDeviceNode; 1692 PVRSRV_DEVICE_NODE *psDeviceNode;
1693 IMG_DEV_PHYADDR sDevPAddr;
1680#ifdef PDUMP 1694#ifdef PDUMP
1681 IMG_UINT32 ui32PSize; 1695 IMG_UINT32 ui32PSize;
1682#endif 1696#endif
1683 1697
1698 psDeviceNode = pMapping->pBMHeap->pBMContext->psDeviceNode;
1699 sDevPAddr = psDeviceNode->pfnMMUGetPhysPageAddr(pMapping->pBMHeap->pMMUHeap, pMapping->DevVAddr);
1700
1701 if (sDevPAddr.uiAddr != 0)
1702 {
1684#ifdef PDUMP 1703#ifdef PDUMP
1704
1705 if(pMapping->ui32Flags & PVRSRV_MEM_DUMMY)
1706 {
1707
1708 ui32PSize = pMapping->pBMHeap->sDevArena.ui32DataPageSize;
1709 }
1710 else
1711 {
1712 ui32PSize = (IMG_UINT32)pMapping->uSize;
1713 }
1685 1714
1686 if(pMapping->ui32Flags & PVRSRV_MEM_DUMMY) 1715 PDUMPFREEPAGES(pMapping->pBMHeap,
1716 pMapping->DevVAddr,
1717 ui32PSize,
1718 pMapping->pBMHeap->sDevArena.ui32DataPageSize,
1719 (IMG_HANDLE)pMapping,
1720 (pMapping->ui32Flags & PVRSRV_MEM_INTERLEAVED) ? IMG_TRUE : IMG_FALSE);
1721#endif
1722 }
1723 psDeviceNode->pfnMMUFree (pMapping->pBMHeap->pMMUHeap, pMapping->DevVAddr, IMG_CAST_TO_DEVVADDR_UINT(pMapping->uSize));
1724}
1725
1726#define XPROC_WORKAROUND_NUM_SHAREABLES 200
1727
1728#define XPROC_WORKAROUND_BAD_SHAREINDEX 0773407734
1729
1730static IMG_UINT32 gXProcWorkaroundShareIndex = XPROC_WORKAROUND_BAD_SHAREINDEX;
1731
1732
1733static struct {
1734 IMG_UINT32 ui32RefCount;
1735 IMG_UINT32 ui32AllocFlags;
1736 IMG_UINT32 ui32Size;
1737 IMG_UINT32 ui32PageSize;
1738 RA_ARENA *psArena;
1739 IMG_SYS_PHYADDR sSysPAddr;
1740 IMG_VOID *pvCpuVAddr;
1741 IMG_HANDLE hOSMemHandle;
1742} gXProcWorkaroundShareData[XPROC_WORKAROUND_NUM_SHAREABLES] = {{0}};
1743
1744PVRSRV_ERROR BM_XProcWorkaroundSetShareIndex(IMG_UINT32 ui32Index)
1745{
1746
1747
1748
1749 if (gXProcWorkaroundShareIndex != XPROC_WORKAROUND_BAD_SHAREINDEX)
1687 { 1750 {
1688 1751 PVR_DPF((PVR_DBG_ERROR, "No, it's already set!"));
1689 ui32PSize = pMapping->pBMHeap->sDevArena.ui32DataPageSize; 1752 return PVRSRV_ERROR_INVALID_PARAMS;
1753 }
1754
1755 gXProcWorkaroundShareIndex = ui32Index;
1756
1757 return PVRSRV_OK;
1758}
1759
1760PVRSRV_ERROR BM_XProcWorkaroundUnsetShareIndex(IMG_UINT32 ui32Index)
1761{
1762
1763
1764
1765 if (gXProcWorkaroundShareIndex == XPROC_WORKAROUND_BAD_SHAREINDEX)
1766 {
1767 PVR_DPF((PVR_DBG_ERROR, "huh? how can it be bad??"));
1768 return PVRSRV_ERROR_INVALID_PARAMS;
1769 }
1770 if (gXProcWorkaroundShareIndex != ui32Index)
1771 {
1772 PVR_DPF((PVR_DBG_ERROR, "gXProcWorkaroundShareIndex == 0x%08x != 0x%08x == ui32Index", gXProcWorkaroundShareIndex, ui32Index));
1773 return PVRSRV_ERROR_INVALID_PARAMS;
1774 }
1775
1776 gXProcWorkaroundShareIndex = XPROC_WORKAROUND_BAD_SHAREINDEX;
1777
1778 return PVRSRV_OK;
1779}
1780
1781PVRSRV_ERROR BM_XProcWorkaroundFindNewBufferAndSetShareIndex(IMG_UINT32 *pui32Index)
1782{
1783
1784
1785
1786 if (gXProcWorkaroundShareIndex != XPROC_WORKAROUND_BAD_SHAREINDEX)
1787 {
1788 return PVRSRV_ERROR_INVALID_PARAMS;
1789 }
1790
1791 for (*pui32Index = 0; *pui32Index < XPROC_WORKAROUND_NUM_SHAREABLES; (*pui32Index)++)
1792 {
1793 if (gXProcWorkaroundShareData[*pui32Index].ui32RefCount == 0)
1794 {
1795 gXProcWorkaroundShareIndex = *pui32Index;
1796 return PVRSRV_OK;
1797 }
1798 }
1799
1800 PVR_DPF((PVR_DBG_ERROR, "ran out of shared buffers"));
1801 return PVRSRV_ERROR_OUT_OF_MEMORY;
1802}
1803
1804static PVRSRV_ERROR
1805XProcWorkaroundAllocShareable(RA_ARENA *psArena,
1806 IMG_UINT32 ui32AllocFlags,
1807 IMG_UINT32 ui32Size,
1808 IMG_UINT32 ui32PageSize,
1809 IMG_VOID **ppvCpuVAddr,
1810 IMG_HANDLE *phOSMemHandle)
1811{
1812 if ((ui32AllocFlags & PVRSRV_MEM_XPROC) == 0)
1813 {
1814 PVR_DPF((PVR_DBG_VERBOSE, "XProcWorkaroundAllocShareable: bad flags"));
1815 return PVRSRV_ERROR_INVALID_PARAMS;
1816 }
1817
1818 if (gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].ui32RefCount > 0)
1819 {
1820 PVR_DPF((PVR_DBG_VERBOSE,
1821 "XProcWorkaroundAllocShareable: re-using previously allocated pages"));
1822
1823 ui32AllocFlags &= ~PVRSRV_HAP_MAPTYPE_MASK;
1824 ui32AllocFlags |= PVRSRV_HAP_SINGLE_PROCESS;
1825
1826 if (ui32AllocFlags != gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].ui32AllocFlags)
1827 {
1828 PVR_DPF((PVR_DBG_ERROR,
1829 "Can't! Flags don't match! (I had 0x%08x, you gave 0x%08x)",
1830 gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].ui32AllocFlags,
1831 ui32AllocFlags));
1832 return PVRSRV_ERROR_INVALID_PARAMS;
1833 }
1834
1835 if (ui32Size != gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].ui32Size)
1836 {
1837 PVR_DPF((PVR_DBG_ERROR,
1838 "Can't! Size doesn't match!"));
1839 return PVRSRV_ERROR_INVALID_PARAMS;
1840 }
1841
1842 if (ui32PageSize != gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].ui32PageSize)
1843 {
1844 PVR_DPF((PVR_DBG_ERROR,
1845 "Can't! Page Size doesn't match!"));
1846 return PVRSRV_ERROR_INVALID_PARAMS;
1847 }
1848
1849 *ppvCpuVAddr = gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].pvCpuVAddr;
1850 *phOSMemHandle = gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].hOSMemHandle;
1851
1852 gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].ui32RefCount ++;
1853
1854 return PVRSRV_OK;
1690 } 1855 }
1691 else 1856 else
1692 { 1857 {
1693 ui32PSize = pMapping->uSize; 1858 if (psArena != IMG_NULL)
1859 {
1860 IMG_CPU_PHYADDR sCpuPAddr;
1861 IMG_SYS_PHYADDR sSysPAddr;
1862
1863 PVR_DPF((PVR_DBG_VERBOSE,
1864 "XProcWorkaroundAllocShareable: making a NEW allocation from local mem"));
1865
1866 if (!RA_Alloc (psArena,
1867 ui32Size,
1868 IMG_NULL,
1869 IMG_NULL,
1870 0,
1871 ui32PageSize,
1872 0,
1873 (IMG_UINTPTR_T *)&sSysPAddr.uiAddr))
1874 {
1875 PVR_DPF((PVR_DBG_ERROR, "XProcWorkaroundAllocShareable: RA_Alloc(0x%x) FAILED", ui32Size));
1876 return PVRSRV_ERROR_OUT_OF_MEMORY;
1877 }
1878
1879 sCpuPAddr = SysSysPAddrToCpuPAddr(sSysPAddr);
1880 if(OSReservePhys(sCpuPAddr,
1881 ui32Size,
1882 ui32AllocFlags,
1883 (IMG_VOID **)&gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].pvCpuVAddr,
1884 &gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].hOSMemHandle) != PVRSRV_OK)
1885 {
1886 PVR_DPF((PVR_DBG_ERROR, "XProcWorkaroundAllocShareable: OSReservePhys failed"));
1887 return PVRSRV_ERROR_OUT_OF_MEMORY;
1888 }
1889 gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].sSysPAddr = sSysPAddr;
1890 }
1891 else
1892 {
1893 PVR_DPF((PVR_DBG_VERBOSE,
1894 "XProcWorkaroundAllocShareable: making a NEW allocation from OS"));
1895
1896 ui32AllocFlags &= ~PVRSRV_HAP_MAPTYPE_MASK;
1897 ui32AllocFlags |= PVRSRV_HAP_SINGLE_PROCESS;
1898
1899
1900 if (OSAllocPages(ui32AllocFlags,
1901 ui32Size,
1902 ui32PageSize,
1903 (IMG_VOID **)&gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].pvCpuVAddr,
1904 &gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].hOSMemHandle) != PVRSRV_OK)
1905 {
1906 PVR_DPF((PVR_DBG_ERROR,
1907 "XProcWorkaroundAllocShareable: OSAllocPages(0x%x) failed",
1908 ui32PageSize));
1909 return PVRSRV_ERROR_OUT_OF_MEMORY;
1910 }
1911 }
1912
1913 gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].psArena = psArena;
1914 gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].ui32AllocFlags = ui32AllocFlags;
1915 gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].ui32Size = ui32Size;
1916 gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].ui32PageSize = ui32PageSize;
1917
1918 *ppvCpuVAddr = gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].pvCpuVAddr;
1919 *phOSMemHandle = gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].hOSMemHandle;
1920
1921 gXProcWorkaroundShareData[gXProcWorkaroundShareIndex].ui32RefCount ++;
1922
1923 return PVRSRV_OK;
1694 } 1924 }
1925}
1695 1926
1696 PDUMPFREEPAGES(pMapping->pBMHeap, 1927static PVRSRV_ERROR XProcWorkaroundHandleToSI(IMG_HANDLE hOSMemHandle, IMG_UINT32 *pui32SI)
1697 pMapping->DevVAddr, 1928{
1698 ui32PSize, 1929
1699 pMapping->pBMHeap->sDevArena.ui32DataPageSize, 1930 IMG_UINT32 ui32SI;
1700 (IMG_HANDLE)pMapping, 1931 IMG_BOOL bFound;
1701 (pMapping->ui32Flags & PVRSRV_MEM_INTERLEAVED) ? IMG_TRUE : IMG_FALSE); 1932 IMG_BOOL bErrorDups;
1702#endif
1703 1933
1704 psDeviceNode = pMapping->pBMHeap->pBMContext->psDeviceNode; 1934 bFound = IMG_FALSE;
1935 bErrorDups = IMG_FALSE;
1705 1936
1706 psDeviceNode->pfnMMUFree (pMapping->pBMHeap->pMMUHeap, pMapping->DevVAddr, IMG_CAST_TO_DEVVADDR_UINT(pMapping->uSize)); 1937 for (ui32SI = 0; ui32SI < XPROC_WORKAROUND_NUM_SHAREABLES; ui32SI++)
1938 {
1939 if (gXProcWorkaroundShareData[ui32SI].ui32RefCount>0 && gXProcWorkaroundShareData[ui32SI].hOSMemHandle == hOSMemHandle)
1940 {
1941 if (bFound)
1942 {
1943 bErrorDups = IMG_TRUE;
1944 }
1945 else
1946 {
1947 *pui32SI = ui32SI;
1948 bFound = IMG_TRUE;
1949 }
1950 }
1951 }
1952
1953 if (bErrorDups || !bFound)
1954 {
1955 return PVRSRV_ERROR_BM_BAD_SHAREMEM_HANDLE;
1956 }
1957
1958 return PVRSRV_OK;
1959}
1960
1961static IMG_VOID XProcWorkaroundFreeShareable(IMG_HANDLE hOSMemHandle)
1962{
1963 IMG_UINT32 ui32SI = (IMG_UINT32)((IMG_UINTPTR_T)hOSMemHandle & 0xffffU);
1964 PVRSRV_ERROR eError;
1965
1966 eError = XProcWorkaroundHandleToSI(hOSMemHandle, &ui32SI);
1967 if (eError != PVRSRV_OK)
1968 {
1969 PVR_DPF((PVR_DBG_ERROR, "bad handle"));
1970 return;
1971 }
1972
1973 gXProcWorkaroundShareData[ui32SI].ui32RefCount --;
1974
1975 PVR_DPF((PVR_DBG_VERBOSE, "Reduced refcount of SI[%d] from %d to %d",
1976 ui32SI, gXProcWorkaroundShareData[ui32SI].ui32RefCount+1, gXProcWorkaroundShareData[ui32SI].ui32RefCount));
1977
1978 if (gXProcWorkaroundShareData[ui32SI].ui32RefCount == 0)
1979 {
1980 if (gXProcWorkaroundShareData[ui32SI].psArena != IMG_NULL)
1981 {
1982 IMG_SYS_PHYADDR sSysPAddr;
1983
1984 if (gXProcWorkaroundShareData[ui32SI].pvCpuVAddr != IMG_NULL)
1985 {
1986 OSUnReservePhys(gXProcWorkaroundShareData[ui32SI].pvCpuVAddr,
1987 gXProcWorkaroundShareData[ui32SI].ui32Size,
1988 gXProcWorkaroundShareData[ui32SI].ui32AllocFlags,
1989 gXProcWorkaroundShareData[ui32SI].hOSMemHandle);
1990 }
1991 sSysPAddr = gXProcWorkaroundShareData[ui32SI].sSysPAddr;
1992 RA_Free (gXProcWorkaroundShareData[ui32SI].psArena,
1993 sSysPAddr.uiAddr,
1994 IMG_FALSE);
1995 }
1996 else
1997 {
1998 PVR_DPF((PVR_DBG_VERBOSE, "freeing OS memory"));
1999 OSFreePages(gXProcWorkaroundShareData[ui32SI].ui32AllocFlags,
2000 gXProcWorkaroundShareData[ui32SI].ui32PageSize,
2001 gXProcWorkaroundShareData[ui32SI].pvCpuVAddr,
2002 gXProcWorkaroundShareData[ui32SI].hOSMemHandle);
2003 }
2004 }
1707} 2005}
1708 2006
2007
1709static IMG_BOOL 2008static IMG_BOOL
1710BM_ImportMemory (IMG_VOID *pH, 2009BM_ImportMemory (IMG_VOID *pH,
1711 IMG_SIZE_T uRequestSize, 2010 IMG_SIZE_T uRequestSize,
@@ -1720,7 +2019,7 @@ BM_ImportMemory (IMG_VOID *pH,
1720 IMG_BOOL bResult; 2019 IMG_BOOL bResult;
1721 IMG_SIZE_T uSize; 2020 IMG_SIZE_T uSize;
1722 IMG_SIZE_T uPSize; 2021 IMG_SIZE_T uPSize;
1723 IMG_UINT32 uDevVAddrAlignment = 0; 2022 IMG_SIZE_T uDevVAddrAlignment = 0;
1724 2023
1725 PVR_DPF ((PVR_DBG_MESSAGE, 2024 PVR_DPF ((PVR_DBG_MESSAGE,
1726 "BM_ImportMemory (pBMContext=0x%x, uRequestSize=0x%x, uFlags=0x%x, uAlign=0x%x)", 2025 "BM_ImportMemory (pBMContext=0x%x, uRequestSize=0x%x, uFlags=0x%x, uAlign=0x%x)",
@@ -1771,6 +2070,103 @@ BM_ImportMemory (IMG_VOID *pH,
1771 uPSize = pMapping->uSize; 2070 uPSize = pMapping->uSize;
1772 } 2071 }
1773 2072
2073 if (uFlags & PVRSRV_MEM_XPROC)
2074 {
2075 IMG_UINT32 ui32Attribs = pBMHeap->ui32Attribs | PVRSRV_MEM_XPROC;
2076 IMG_BOOL bBadBackingStoreType;
2077
2078 bBadBackingStoreType = IMG_TRUE;
2079
2080 if ((ui32Attribs & PVRSRV_BACKINGSTORE_SYSMEM_NONCONTIG) != 0)
2081 {
2082#ifndef MAX
2083#define MAX(a,b) ((a) > (b) ? (a) : (b))
2084#endif
2085 uDevVAddrAlignment = MAX(pBMHeap->sDevArena.ui32DataPageSize, HOST_PAGESIZE());
2086
2087
2088 if (uPSize % uDevVAddrAlignment != 0)
2089 {
2090 PVR_DPF((PVR_DBG_ERROR, "Cannot use use this memory sharing workaround with allocations that might be suballocated"));
2091 goto fail_mapping_alloc;
2092 }
2093 uDevVAddrAlignment = 0;
2094
2095
2096 if (pMapping->ui32Flags & PVRSRV_HAP_CACHETYPE_MASK)
2097 {
2098 ui32Attribs &= ~PVRSRV_HAP_CACHETYPE_MASK;
2099 ui32Attribs |= (pMapping->ui32Flags & PVRSRV_HAP_CACHETYPE_MASK);
2100 }
2101
2102
2103 if (XProcWorkaroundAllocShareable(IMG_NULL,
2104 ui32Attribs,
2105 (IMG_UINT32)uPSize,
2106 pBMHeap->sDevArena.ui32DataPageSize,
2107 (IMG_VOID **)&pMapping->CpuVAddr,
2108 &pMapping->hOSMemHandle) != PVRSRV_OK)
2109 {
2110 PVR_DPF((PVR_DBG_ERROR,
2111 "BM_ImportMemory: XProcWorkaroundAllocShareable(0x%x) failed",
2112 uPSize));
2113 goto fail_mapping_alloc;
2114 }
2115
2116
2117
2118
2119 pMapping->eCpuMemoryOrigin = hm_env;
2120 bBadBackingStoreType = IMG_FALSE;
2121 }
2122
2123 if ((ui32Attribs & PVRSRV_BACKINGSTORE_LOCALMEM_CONTIG) != 0)
2124 {
2125 uDevVAddrAlignment = pBMHeap->sDevArena.ui32DataPageSize;
2126
2127 if (uPSize % uDevVAddrAlignment != 0)
2128 {
2129 PVR_DPF((PVR_DBG_ERROR, "Cannot use use this memory sharing workaround with allocations that might be suballocated"));
2130 goto fail_mapping_alloc;
2131 }
2132 uDevVAddrAlignment = 0;
2133
2134
2135 if (pMapping->ui32Flags & PVRSRV_HAP_CACHETYPE_MASK)
2136 {
2137 ui32Attribs &= ~PVRSRV_HAP_CACHETYPE_MASK;
2138 ui32Attribs |= (pMapping->ui32Flags & PVRSRV_HAP_CACHETYPE_MASK);
2139 }
2140
2141
2142 if (XProcWorkaroundAllocShareable(pBMHeap->pLocalDevMemArena,
2143 ui32Attribs,
2144 (IMG_UINT32)uPSize,
2145 pBMHeap->sDevArena.ui32DataPageSize,
2146 (IMG_VOID **)&pMapping->CpuVAddr,
2147 &pMapping->hOSMemHandle) != PVRSRV_OK)
2148 {
2149 PVR_DPF((PVR_DBG_ERROR,
2150 "BM_ImportMemory: XProcWorkaroundAllocShareable(0x%x) failed",
2151 uPSize));
2152 goto fail_mapping_alloc;
2153 }
2154
2155
2156
2157
2158 pMapping->eCpuMemoryOrigin = hm_env;
2159 bBadBackingStoreType = IMG_FALSE;
2160 }
2161
2162 if (bBadBackingStoreType)
2163 {
2164 PVR_DPF((PVR_DBG_ERROR, "Cannot use this memory sharing workaround with this type of backing store"));
2165 goto fail_mapping_alloc;
2166 }
2167 }
2168 else
2169
1774 2170
1775 2171
1776 if(pBMHeap->ui32Attribs & PVRSRV_BACKINGSTORE_SYSMEM_NONCONTIG) 2172 if(pBMHeap->ui32Attribs & PVRSRV_BACKINGSTORE_SYSMEM_NONCONTIG)
@@ -1854,7 +2250,7 @@ BM_ImportMemory (IMG_VOID *pH,
1854 pMapping, 2250 pMapping,
1855 IMG_NULL, 2251 IMG_NULL,
1856 uFlags, 2252 uFlags,
1857 uDevVAddrAlignment, 2253 (IMG_UINT32)uDevVAddrAlignment,
1858 &pMapping->DevVAddr); 2254 &pMapping->DevVAddr);
1859 if (!bResult) 2255 if (!bResult)
1860 { 2256 {
@@ -1892,7 +2288,12 @@ fail_dev_mem_alloc:
1892 uPSize = pMapping->uSize; 2288 uPSize = pMapping->uSize;
1893 } 2289 }
1894 2290
1895 if(pBMHeap->ui32Attribs & PVRSRV_BACKINGSTORE_SYSMEM_NONCONTIG) 2291 if (uFlags & PVRSRV_MEM_XPROC)
2292 {
2293 XProcWorkaroundFreeShareable(pMapping->hOSMemHandle);
2294 }
2295 else
2296 if(pBMHeap->ui32Attribs & PVRSRV_BACKINGSTORE_SYSMEM_NONCONTIG)
1896 { 2297 {
1897 OSFreePages(pBMHeap->ui32Attribs, 2298 OSFreePages(pBMHeap->ui32Attribs,
1898 uPSize, 2299 uPSize,
@@ -1959,7 +2360,12 @@ BM_FreeMemory (IMG_VOID *h, IMG_UINTPTR_T _base, BM_MAPPING *psMapping)
1959 uPSize = psMapping->uSize; 2360 uPSize = psMapping->uSize;
1960 } 2361 }
1961 2362
1962 if(pBMHeap->ui32Attribs & PVRSRV_BACKINGSTORE_SYSMEM_NONCONTIG) 2363 if (psMapping->ui32Flags & PVRSRV_MEM_XPROC)
2364 {
2365 XProcWorkaroundFreeShareable(psMapping->hOSMemHandle);
2366 }
2367 else
2368 if(pBMHeap->ui32Attribs & PVRSRV_BACKINGSTORE_SYSMEM_NONCONTIG)
1963 { 2369 {
1964 OSFreePages(pBMHeap->ui32Attribs, 2370 OSFreePages(pBMHeap->ui32Attribs,
1965 uPSize, 2371 uPSize,
@@ -2002,6 +2408,7 @@ IMG_VOID BM_GetPhysPageAddr(PVRSRV_KERNEL_MEM_INFO *psMemInfo,
2002 2408
2003 PVR_ASSERT((sDevVPageAddr.uiAddr & 0xFFF) == 0); 2409 PVR_ASSERT((sDevVPageAddr.uiAddr & 0xFFF) == 0);
2004 2410
2411
2005 psDeviceNode = ((BM_BUF*)psMemInfo->sMemBlk.hBuffer)->pMapping->pBMHeap->pBMContext->psDeviceNode; 2412 psDeviceNode = ((BM_BUF*)psMemInfo->sMemBlk.hBuffer)->pMapping->pBMHeap->pBMContext->psDeviceNode;
2006 2413
2007 *psDevPAddr = psDeviceNode->pfnMMUGetPhysPageAddr(((BM_BUF*)psMemInfo->sMemBlk.hBuffer)->pMapping->pBMHeap->pMMUHeap, 2414 *psDevPAddr = psDeviceNode->pfnMMUGetPhysPageAddr(((BM_BUF*)psMemInfo->sMemBlk.hBuffer)->pMapping->pBMHeap->pMMUHeap,
diff --git a/drivers/gpu/pvr/buffer_manager.h b/drivers/gpu/pvr/buffer_manager.h
index 1467cd3939f..b821545e946 100644
--- a/drivers/gpu/pvr/buffer_manager.h
+++ b/drivers/gpu/pvr/buffer_manager.h
@@ -202,6 +202,11 @@ IMG_VOID BM_Export(BM_HANDLE hBuf);
202 202
203IMG_VOID BM_FreeExport(BM_HANDLE hBuf, IMG_UINT32 ui32Flags); 203IMG_VOID BM_FreeExport(BM_HANDLE hBuf, IMG_UINT32 ui32Flags);
204 204
205PVRSRV_ERROR BM_XProcWorkaroundSetShareIndex(IMG_UINT32 ui32Index);
206PVRSRV_ERROR BM_XProcWorkaroundUnsetShareIndex(IMG_UINT32 ui32Index);
207PVRSRV_ERROR BM_XProcWorkaroundFindNewBufferAndSetShareIndex(IMG_UINT32 *pui32Index);
208
209
205#if defined(__cplusplus) 210#if defined(__cplusplus)
206} 211}
207#endif 212#endif
diff --git a/drivers/gpu/pvr/dbgdrvif.h b/drivers/gpu/pvr/dbgdrvif.h
index 6029ef965ee..dab4d13eb48 100644
--- a/drivers/gpu/pvr/dbgdrvif.h
+++ b/drivers/gpu/pvr/dbgdrvif.h
@@ -1,26 +1,26 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation. 7 * version 2, as published by the Free Software Foundation.
8 * 8 *
9 * This program is distributed in the hope it will be useful but, except 9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the 10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose. 11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details. 12 * See the GNU General Public License for more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with 14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 * 17 *
18 * The full GNU General Public License is included in this distribution in 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING". 19 * the file called "COPYING".
20 * 20 *
21 * Contact Information: 21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com> 22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK 23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 * 24 *
25 ******************************************************************************/ 25 ******************************************************************************/
26 26
@@ -28,8 +28,21 @@
28#define _DBGDRVIF_ 28#define _DBGDRVIF_
29 29
30 30
31#if defined(__linux__)
32
33#define FILE_DEVICE_UNKNOWN 0
34#define METHOD_BUFFERED 0
35#define FILE_ANY_ACCESS 0
36
37#define CTL_CODE( DeviceType, Function, Method, Access ) (Function)
38#define MAKEIOCTLINDEX(i) ((i) & 0xFFF)
39
40#else
41
31#include "ioctldef.h" 42#include "ioctldef.h"
32 43
44#endif
45
33#define DEBUG_CAPMODE_FRAMED 0x00000001UL 46#define DEBUG_CAPMODE_FRAMED 0x00000001UL
34#define DEBUG_CAPMODE_CONTINUOUS 0x00000002UL 47#define DEBUG_CAPMODE_CONTINUOUS 0x00000002UL
35#define DEBUG_CAPMODE_HOTKEY 0x00000004UL 48#define DEBUG_CAPMODE_HOTKEY 0x00000004UL
@@ -238,17 +251,17 @@ typedef struct _DBG_IN_WRITE_LF_
238 251
239typedef struct _DBG_STREAM_CONTROL_ 252typedef struct _DBG_STREAM_CONTROL_
240{ 253{
241 IMG_BOOL bInitPhaseComplete; 254 IMG_BOOL bInitPhaseComplete;
242 IMG_UINT32 ui32Flags; 255 IMG_UINT32 ui32Flags;
243 256
244 IMG_UINT32 ui32CapMode; 257 IMG_UINT32 ui32CapMode;
245 IMG_UINT32 ui32OutMode; 258 IMG_UINT32 ui32OutMode;
246 IMG_UINT32 ui32DebugLevel; 259 IMG_UINT32 ui32DebugLevel;
247 IMG_UINT32 ui32DefaultMode; 260 IMG_UINT32 ui32DefaultMode;
248 IMG_UINT32 ui32Start; 261 IMG_UINT32 ui32Start;
249 IMG_UINT32 ui32End; 262 IMG_UINT32 ui32End;
250 IMG_UINT32 ui32Current; 263 IMG_UINT32 ui32Current;
251 IMG_UINT32 ui32SampleRate; 264 IMG_UINT32 ui32SampleRate;
252 IMG_UINT32 ui32Reserved; 265 IMG_UINT32 ui32Reserved;
253} DBG_STREAM_CONTROL, *PDBG_STREAM_CONTROL; 266} DBG_STREAM_CONTROL, *PDBG_STREAM_CONTROL;
254typedef struct _DBG_STREAM_ 267typedef struct _DBG_STREAM_
@@ -262,13 +275,13 @@ typedef struct _DBG_STREAM_
262 IMG_UINT32 ui32RPtr; 275 IMG_UINT32 ui32RPtr;
263 IMG_UINT32 ui32WPtr; 276 IMG_UINT32 ui32WPtr;
264 IMG_UINT32 ui32DataWritten; 277 IMG_UINT32 ui32DataWritten;
265 IMG_UINT32 ui32Marker; 278 IMG_UINT32 ui32Marker;
266 IMG_UINT32 ui32InitPhaseWOff; 279 IMG_UINT32 ui32InitPhaseWOff;
267 280
268 281
269 282
270 283
271 IMG_CHAR szName[30]; 284 IMG_CHAR szName[30];
272} DBG_STREAM,*PDBG_STREAM; 285} DBG_STREAM,*PDBG_STREAM;
273 286
274typedef struct _DBGKM_CONNECT_NOTIFIER_ 287typedef struct _DBGKM_CONNECT_NOTIFIER_
@@ -279,36 +292,36 @@ typedef struct _DBGKM_CONNECT_NOTIFIER_
279typedef struct _DBGKM_SERVICE_TABLE_ 292typedef struct _DBGKM_SERVICE_TABLE_
280{ 293{
281 IMG_UINT32 ui32Size; 294 IMG_UINT32 ui32Size;
282 IMG_VOID * (IMG_CALLCONV *pfnCreateStream) (IMG_CHAR * pszName,IMG_UINT32 ui32CapMode,IMG_UINT32 ui32OutMode,IMG_UINT32 ui32Flags,IMG_UINT32 ui32Pages); 295 IMG_VOID * (IMG_CALLCONV *pfnCreateStream) (IMG_CHAR * pszName,IMG_UINT32 ui32CapMode,IMG_UINT32 ui32OutMode,IMG_UINT32 ui32Flags,IMG_UINT32 ui32Pages);
283 IMG_VOID (IMG_CALLCONV *pfnDestroyStream) (PDBG_STREAM psStream); 296 IMG_VOID (IMG_CALLCONV *pfnDestroyStream) (PDBG_STREAM psStream);
284 IMG_VOID * (IMG_CALLCONV *pfnFindStream) (IMG_CHAR * pszName, IMG_BOOL bResetInitBuffer); 297 IMG_VOID * (IMG_CALLCONV *pfnFindStream) (IMG_CHAR * pszName, IMG_BOOL bResetInitBuffer);
285 IMG_UINT32 (IMG_CALLCONV *pfnWriteString) (PDBG_STREAM psStream,IMG_CHAR * pszString,IMG_UINT32 ui32Level); 298 IMG_UINT32 (IMG_CALLCONV *pfnWriteString) (PDBG_STREAM psStream,IMG_CHAR * pszString,IMG_UINT32 ui32Level);
286 IMG_UINT32 (IMG_CALLCONV *pfnReadString) (PDBG_STREAM psStream,IMG_CHAR * pszString,IMG_UINT32 ui32Limit); 299 IMG_UINT32 (IMG_CALLCONV *pfnReadString) (PDBG_STREAM psStream,IMG_CHAR * pszString,IMG_UINT32 ui32Limit);
287 IMG_UINT32 (IMG_CALLCONV *pfnWriteBIN) (PDBG_STREAM psStream,IMG_UINT8 *pui8InBuf,IMG_UINT32 ui32InBuffSize,IMG_UINT32 ui32Level); 300 IMG_UINT32 (IMG_CALLCONV *pfnWriteBIN) (PDBG_STREAM psStream,IMG_UINT8 *pui8InBuf,IMG_UINT32 ui32InBuffSize,IMG_UINT32 ui32Level);
288 IMG_UINT32 (IMG_CALLCONV *pfnReadBIN) (PDBG_STREAM psStream,IMG_BOOL bReadInitBuffer, IMG_UINT32 ui32OutBufferSize,IMG_UINT8 *pui8OutBuf); 301 IMG_UINT32 (IMG_CALLCONV *pfnReadBIN) (PDBG_STREAM psStream,IMG_BOOL bReadInitBuffer, IMG_UINT32 ui32OutBufferSize,IMG_UINT8 *pui8OutBuf);
289 IMG_VOID (IMG_CALLCONV *pfnSetCaptureMode) (PDBG_STREAM psStream,IMG_UINT32 ui32CapMode,IMG_UINT32 ui32Start,IMG_UINT32 ui32Stop,IMG_UINT32 ui32SampleRate); 302 IMG_VOID (IMG_CALLCONV *pfnSetCaptureMode) (PDBG_STREAM psStream,IMG_UINT32 ui32CapMode,IMG_UINT32 ui32Start,IMG_UINT32 ui32Stop,IMG_UINT32 ui32SampleRate);
290 IMG_VOID (IMG_CALLCONV *pfnSetOutputMode) (PDBG_STREAM psStream,IMG_UINT32 ui32OutMode); 303 IMG_VOID (IMG_CALLCONV *pfnSetOutputMode) (PDBG_STREAM psStream,IMG_UINT32 ui32OutMode);
291 IMG_VOID (IMG_CALLCONV *pfnSetDebugLevel) (PDBG_STREAM psStream,IMG_UINT32 ui32DebugLevel); 304 IMG_VOID (IMG_CALLCONV *pfnSetDebugLevel) (PDBG_STREAM psStream,IMG_UINT32 ui32DebugLevel);
292 IMG_VOID (IMG_CALLCONV *pfnSetFrame) (PDBG_STREAM psStream,IMG_UINT32 ui32Frame); 305 IMG_VOID (IMG_CALLCONV *pfnSetFrame) (PDBG_STREAM psStream,IMG_UINT32 ui32Frame);
293 IMG_UINT32 (IMG_CALLCONV *pfnGetFrame) (PDBG_STREAM psStream); 306 IMG_UINT32 (IMG_CALLCONV *pfnGetFrame) (PDBG_STREAM psStream);
294 IMG_VOID (IMG_CALLCONV *pfnOverrideMode) (PDBG_STREAM psStream,IMG_UINT32 ui32Mode); 307 IMG_VOID (IMG_CALLCONV *pfnOverrideMode) (PDBG_STREAM psStream,IMG_UINT32 ui32Mode);
295 IMG_VOID (IMG_CALLCONV *pfnDefaultMode) (PDBG_STREAM psStream); 308 IMG_VOID (IMG_CALLCONV *pfnDefaultMode) (PDBG_STREAM psStream);
296 IMG_UINT32 (IMG_CALLCONV *pfnDBGDrivWrite2) (PDBG_STREAM psStream,IMG_UINT8 *pui8InBuf,IMG_UINT32 ui32InBuffSize,IMG_UINT32 ui32Level); 309 IMG_UINT32 (IMG_CALLCONV *pfnDBGDrivWrite2) (PDBG_STREAM psStream,IMG_UINT8 *pui8InBuf,IMG_UINT32 ui32InBuffSize,IMG_UINT32 ui32Level);
297 IMG_UINT32 (IMG_CALLCONV *pfnWriteStringCM) (PDBG_STREAM psStream,IMG_CHAR * pszString,IMG_UINT32 ui32Level); 310 IMG_UINT32 (IMG_CALLCONV *pfnWriteStringCM) (PDBG_STREAM psStream,IMG_CHAR * pszString,IMG_UINT32 ui32Level);
298 IMG_UINT32 (IMG_CALLCONV *pfnWriteBINCM) (PDBG_STREAM psStream,IMG_UINT8 *pui8InBuf,IMG_UINT32 ui32InBuffSize,IMG_UINT32 ui32Level); 311 IMG_UINT32 (IMG_CALLCONV *pfnWriteBINCM) (PDBG_STREAM psStream,IMG_UINT8 *pui8InBuf,IMG_UINT32 ui32InBuffSize,IMG_UINT32 ui32Level);
299 IMG_VOID (IMG_CALLCONV *pfnSetMarker) (PDBG_STREAM psStream,IMG_UINT32 ui32Marker); 312 IMG_VOID (IMG_CALLCONV *pfnSetMarker) (PDBG_STREAM psStream,IMG_UINT32 ui32Marker);
300 IMG_UINT32 (IMG_CALLCONV *pfnGetMarker) (PDBG_STREAM psStream); 313 IMG_UINT32 (IMG_CALLCONV *pfnGetMarker) (PDBG_STREAM psStream);
301 IMG_VOID (IMG_CALLCONV *pfnStartInitPhase) (PDBG_STREAM psStream); 314 IMG_VOID (IMG_CALLCONV *pfnStartInitPhase) (PDBG_STREAM psStream);
302 IMG_VOID (IMG_CALLCONV *pfnStopInitPhase) (PDBG_STREAM psStream); 315 IMG_VOID (IMG_CALLCONV *pfnStopInitPhase) (PDBG_STREAM psStream);
303 IMG_BOOL (IMG_CALLCONV *pfnIsCaptureFrame) (PDBG_STREAM psStream, IMG_BOOL bCheckPreviousFrame); 316 IMG_BOOL (IMG_CALLCONV *pfnIsCaptureFrame) (PDBG_STREAM psStream, IMG_BOOL bCheckPreviousFrame);
304 IMG_UINT32 (IMG_CALLCONV *pfnWriteLF) (PDBG_STREAM psStream, IMG_UINT8 *pui8InBuf, IMG_UINT32 ui32InBuffSize, IMG_UINT32 ui32Level, IMG_UINT32 ui32Flags); 317 IMG_UINT32 (IMG_CALLCONV *pfnWriteLF) (PDBG_STREAM psStream, IMG_UINT8 *pui8InBuf, IMG_UINT32 ui32InBuffSize, IMG_UINT32 ui32Level, IMG_UINT32 ui32Flags);
305 IMG_UINT32 (IMG_CALLCONV *pfnReadLF) (PDBG_STREAM psStream, IMG_UINT32 ui32OutBuffSize, IMG_UINT8 *pui8OutBuf); 318 IMG_UINT32 (IMG_CALLCONV *pfnReadLF) (PDBG_STREAM psStream, IMG_UINT32 ui32OutBuffSize, IMG_UINT8 *pui8OutBuf);
306 IMG_UINT32 (IMG_CALLCONV *pfnGetStreamOffset) (PDBG_STREAM psStream); 319 IMG_UINT32 (IMG_CALLCONV *pfnGetStreamOffset) (PDBG_STREAM psStream);
307 IMG_VOID (IMG_CALLCONV *pfnSetStreamOffset) (PDBG_STREAM psStream, IMG_UINT32 ui32StreamOffset); 320 IMG_VOID (IMG_CALLCONV *pfnSetStreamOffset) (PDBG_STREAM psStream, IMG_UINT32 ui32StreamOffset);
308 IMG_BOOL (IMG_CALLCONV *pfnIsLastCaptureFrame) (PDBG_STREAM psStream); 321 IMG_BOOL (IMG_CALLCONV *pfnIsLastCaptureFrame) (PDBG_STREAM psStream);
309 IMG_VOID (IMG_CALLCONV *pfnWaitForEvent) (DBG_EVENT eEvent); 322 IMG_VOID (IMG_CALLCONV *pfnWaitForEvent) (DBG_EVENT eEvent);
310 IMG_VOID (IMG_CALLCONV *pfnSetConnectNotifier) (DBGKM_CONNECT_NOTIFIER fn_notifier); 323 IMG_VOID (IMG_CALLCONV *pfnSetConnectNotifier) (DBGKM_CONNECT_NOTIFIER fn_notifier);
311 IMG_UINT32 (IMG_CALLCONV *pfnWritePersist) (PDBG_STREAM psStream,IMG_UINT8 *pui8InBuf,IMG_UINT32 ui32InBuffSize,IMG_UINT32 ui32Level); 324 IMG_UINT32 (IMG_CALLCONV *pfnWritePersist) (PDBG_STREAM psStream,IMG_UINT8 *pui8InBuf,IMG_UINT32 ui32InBuffSize,IMG_UINT32 ui32Level);
312} DBGKM_SERVICE_TABLE, *PDBGKM_SERVICE_TABLE; 325} DBGKM_SERVICE_TABLE, *PDBGKM_SERVICE_TABLE;
313 326
314 327
diff --git a/drivers/gpu/pvr/device.h b/drivers/gpu/pvr/device.h
index f41bd9e26e6..fbc26a6a66d 100644
--- a/drivers/gpu/pvr/device.h
+++ b/drivers/gpu/pvr/device.h
@@ -222,6 +222,8 @@ typedef struct _PVRSRV_DEVICE_NODE_
222#endif 222#endif
223 IMG_DEV_PHYADDR (*pfnMMUGetPhysPageAddr)(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR sDevVPageAddr); 223 IMG_DEV_PHYADDR (*pfnMMUGetPhysPageAddr)(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR sDevVPageAddr);
224 IMG_DEV_PHYADDR (*pfnMMUGetPDDevPAddr)(MMU_CONTEXT *pMMUContext); 224 IMG_DEV_PHYADDR (*pfnMMUGetPDDevPAddr)(MMU_CONTEXT *pMMUContext);
225 IMG_VOID (*pfnMMUGetCacheFlushRange)(MMU_CONTEXT *pMMUContext, IMG_UINT32 *pui32RangeMask);
226 IMG_VOID (*pfnMMUGetPDPhysAddr)(MMU_CONTEXT *pMMUContext, IMG_DEV_PHYADDR *psDevPAddr);
225 227
226 228
227 PVRSRV_ERROR (*pfnAllocMemTilingRange)(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode, 229 PVRSRV_ERROR (*pfnAllocMemTilingRange)(struct _PVRSRV_DEVICE_NODE_ *psDeviceNode,
diff --git a/drivers/gpu/pvr/deviceclass.c b/drivers/gpu/pvr/deviceclass.c
index 471ce0cf12b..effcdfbf055 100644
--- a/drivers/gpu/pvr/deviceclass.c
+++ b/drivers/gpu/pvr/deviceclass.c
@@ -557,6 +557,17 @@ static PVRSRV_ERROR CloseDCDeviceCallBack(IMG_PVOID pvParam,
557 psDCPerContextInfo = (PVRSRV_DISPLAYCLASS_PERCONTEXT_INFO *)pvParam; 557 psDCPerContextInfo = (PVRSRV_DISPLAYCLASS_PERCONTEXT_INFO *)pvParam;
558 psDCInfo = psDCPerContextInfo->psDCInfo; 558 psDCInfo = psDCPerContextInfo->psDCInfo;
559 559
560 if(psDCInfo->sSystemBuffer.sDeviceClassBuffer.ui32MemMapRefCount != 0)
561 {
562 PVR_DPF((PVR_DBG_ERROR,"CloseDCDeviceCallBack: system buffer (0x%p) still mapped (refcount = %d)",
563 &psDCInfo->sSystemBuffer.sDeviceClassBuffer,
564 psDCInfo->sSystemBuffer.sDeviceClassBuffer.ui32MemMapRefCount));
565#if 0
566
567 return PVRSRV_ERROR_STILL_MAPPED;
568#endif
569 }
570
560 psDCInfo->ui32RefCount--; 571 psDCInfo->ui32RefCount--;
561 if(psDCInfo->ui32RefCount == 0) 572 if(psDCInfo->ui32RefCount == 0)
562 { 573 {
@@ -658,6 +669,7 @@ PVRSRV_ERROR PVRSRVOpenDCDeviceKM (PVRSRV_PER_PROCESS_DATA *psPerProc,
658 } 669 }
659 670
660 psDCInfo->sSystemBuffer.sDeviceClassBuffer.psKernelSyncInfo->ui32RefCount++; 671 psDCInfo->sSystemBuffer.sDeviceClassBuffer.psKernelSyncInfo->ui32RefCount++;
672 psDCInfo->sSystemBuffer.sDeviceClassBuffer.ui32MemMapRefCount = 0;
661 } 673 }
662 674
663 psDCPerContextInfo->psDCInfo = psDCInfo; 675 psDCPerContextInfo->psDCInfo = psDCInfo;
@@ -812,7 +824,6 @@ static PVRSRV_ERROR DestroyDCSwapChain(PVRSRV_DC_SWAPCHAIN *psSwapChain)
812 PVRSRV_DISPLAYCLASS_INFO *psDCInfo = psSwapChain->psDCInfo; 824 PVRSRV_DISPLAYCLASS_INFO *psDCInfo = psSwapChain->psDCInfo;
813 IMG_UINT32 i; 825 IMG_UINT32 i;
814 826
815
816 827
817 if( psDCInfo->psDCSwapChainShared ) 828 if( psDCInfo->psDCSwapChainShared )
818 { 829 {
@@ -873,9 +884,24 @@ static PVRSRV_ERROR DestroyDCSwapChainRefCallBack(IMG_PVOID pvParam, IMG_UINT32
873{ 884{
874 PVRSRV_DC_SWAPCHAIN_REF *psSwapChainRef = (PVRSRV_DC_SWAPCHAIN_REF *) pvParam; 885 PVRSRV_DC_SWAPCHAIN_REF *psSwapChainRef = (PVRSRV_DC_SWAPCHAIN_REF *) pvParam;
875 PVRSRV_ERROR eError = PVRSRV_OK; 886 PVRSRV_ERROR eError = PVRSRV_OK;
887 IMG_UINT32 i;
876 888
877 PVR_UNREFERENCED_PARAMETER(ui32Param); 889 PVR_UNREFERENCED_PARAMETER(ui32Param);
878 890
891 for (i = 0; i < psSwapChainRef->psSwapChain->ui32BufferCount; i++)
892 {
893 if (psSwapChainRef->psSwapChain->asBuffer[i].sDeviceClassBuffer.ui32MemMapRefCount != 0)
894 {
895 PVR_DPF((PVR_DBG_ERROR, "DestroyDCSwapChainRefCallBack: swapchain (0x%p) still mapped (ui32MemMapRefCount = %d)",
896 &psSwapChainRef->psSwapChain->asBuffer[i].sDeviceClassBuffer,
897 psSwapChainRef->psSwapChain->asBuffer[i].sDeviceClassBuffer.ui32MemMapRefCount));
898#if 0
899
900 return PVRSRV_ERROR_STILL_MAPPED;
901#endif
902 }
903 }
904
879 if(--psSwapChainRef->psSwapChain->ui32RefCount == 0) 905 if(--psSwapChainRef->psSwapChain->ui32RefCount == 0)
880 { 906 {
881 eError = DestroyDCSwapChain(psSwapChainRef->psSwapChain); 907 eError = DestroyDCSwapChain(psSwapChainRef->psSwapChain);
@@ -1313,6 +1339,7 @@ PVRSRV_ERROR PVRSRVSwapToDCBufferKM(IMG_HANDLE hDeviceKM,
1313 IMG_UINT32 ui32NumSrcSyncs = 1; 1339 IMG_UINT32 ui32NumSrcSyncs = 1;
1314 PVRSRV_KERNEL_SYNC_INFO *apsSrcSync[2]; 1340 PVRSRV_KERNEL_SYNC_INFO *apsSrcSync[2];
1315 PVRSRV_COMMAND *psCommand; 1341 PVRSRV_COMMAND *psCommand;
1342 SYS_DATA *psSysData;
1316 1343
1317 if(!hDeviceKM || !hBuffer || !psClipRect) 1344 if(!hDeviceKM || !hBuffer || !psClipRect)
1318 { 1345 {
@@ -1320,14 +1347,6 @@ PVRSRV_ERROR PVRSRVSwapToDCBufferKM(IMG_HANDLE hDeviceKM,
1320 return PVRSRV_ERROR_INVALID_PARAMS; 1347 return PVRSRV_ERROR_INVALID_PARAMS;
1321 } 1348 }
1322 1349
1323#if defined(SUPPORT_LMA)
1324 eError = PVRSRVPowerLock(KERNEL_ID, IMG_FALSE);
1325 if(eError != PVRSRV_OK)
1326 {
1327 return eError;
1328 }
1329#endif
1330
1331 psBuffer = (PVRSRV_DC_BUFFER*)hBuffer; 1350 psBuffer = (PVRSRV_DC_BUFFER*)hBuffer;
1332 psDCInfo = DCDeviceHandleToDCInfo(hDeviceKM); 1351 psDCInfo = DCDeviceHandleToDCInfo(hDeviceKM);
1333 1352
@@ -1427,28 +1446,15 @@ PVRSRV_ERROR PVRSRVSwapToDCBufferKM(IMG_HANDLE hDeviceKM,
1427 1446
1428 1447
1429 1448
1449 SysAcquireData(&psSysData);
1450 eError = OSScheduleMISR(psSysData);
1430 1451
1431 1452 if (eError != PVRSRV_OK)
1432
1433
1434
1435
1436
1437 LOOP_UNTIL_TIMEOUT(MAX_HW_TIME_US)
1438 { 1453 {
1439 if(PVRSRVProcessQueues(KERNEL_ID, IMG_FALSE) != PVRSRV_ERROR_PROCESSING_BLOCKED) 1454 PVR_DPF((PVR_DBG_ERROR,"PVRSRVSwapToDCBufferKM: Failed to schedule MISR"));
1440 { 1455 goto Exit;
1441 goto ProcessedQueues; 1456 }
1442 }
1443 OSWaitus(MAX_HW_TIME_US/WAIT_TRY_COUNT);
1444 } END_LOOP_UNTIL_TIMEOUT();
1445
1446 PVR_DPF((PVR_DBG_ERROR,"PVRSRVSwapToDCBufferKM: Failed to process queues"));
1447
1448 eError = PVRSRV_ERROR_FAILED_TO_PROCESS_QUEUE;
1449 goto Exit;
1450 1457
1451ProcessedQueues:
1452 1458
1453 psBuffer->psSwapChain->psLastFlipBuffer = psBuffer; 1459 psBuffer->psSwapChain->psLastFlipBuffer = psBuffer;
1454 1460
@@ -1459,9 +1465,6 @@ Exit:
1459 eError = PVRSRV_ERROR_RETRY; 1465 eError = PVRSRV_ERROR_RETRY;
1460 } 1466 }
1461 1467
1462#if defined(SUPPORT_LMA)
1463 PVRSRVPowerUnlock(KERNEL_ID);
1464#endif
1465 return eError; 1468 return eError;
1466} 1469}
1467 1470
@@ -1481,6 +1484,7 @@ PVRSRV_ERROR PVRSRVSwapToDCSystemKM(IMG_HANDLE hDeviceKM,
1481 PVRSRV_COMMAND *psCommand; 1484 PVRSRV_COMMAND *psCommand;
1482 IMG_BOOL bAddReferenceToLast = IMG_TRUE; 1485 IMG_BOOL bAddReferenceToLast = IMG_TRUE;
1483 IMG_UINT16 ui16SwapCommandID = DC_FLIP_COMMAND; 1486 IMG_UINT16 ui16SwapCommandID = DC_FLIP_COMMAND;
1487 SYS_DATA *psSysData;
1484 1488
1485 if(!hDeviceKM || !hSwapChainRef) 1489 if(!hDeviceKM || !hSwapChainRef)
1486 { 1490 {
@@ -1488,14 +1492,6 @@ PVRSRV_ERROR PVRSRVSwapToDCSystemKM(IMG_HANDLE hDeviceKM,
1488 return PVRSRV_ERROR_INVALID_PARAMS; 1492 return PVRSRV_ERROR_INVALID_PARAMS;
1489 } 1493 }
1490 1494
1491#if defined(SUPPORT_LMA)
1492 eError = PVRSRVPowerLock(KERNEL_ID, IMG_FALSE);
1493 if(eError != PVRSRV_OK)
1494 {
1495 return eError;
1496 }
1497#endif
1498
1499 psDCInfo = DCDeviceHandleToDCInfo(hDeviceKM); 1495 psDCInfo = DCDeviceHandleToDCInfo(hDeviceKM);
1500 psSwapChainRef = (PVRSRV_DC_SWAPCHAIN_REF*)hSwapChainRef; 1496 psSwapChainRef = (PVRSRV_DC_SWAPCHAIN_REF*)hSwapChainRef;
1501 psSwapChain = psSwapChainRef->psSwapChain; 1497 psSwapChain = psSwapChainRef->psSwapChain;
@@ -1581,28 +1577,15 @@ PVRSRV_ERROR PVRSRVSwapToDCSystemKM(IMG_HANDLE hDeviceKM,
1581 } 1577 }
1582 1578
1583 1579
1580 SysAcquireData(&psSysData);
1581 eError = OSScheduleMISR(psSysData);
1584 1582
1585 1583 if (eError != PVRSRV_OK)
1586
1587
1588
1589
1590
1591 LOOP_UNTIL_TIMEOUT(MAX_HW_TIME_US)
1592 { 1584 {
1593 if(PVRSRVProcessQueues(KERNEL_ID, IMG_FALSE) != PVRSRV_ERROR_PROCESSING_BLOCKED) 1585 PVR_DPF((PVR_DBG_ERROR,"PVRSRVSwapToDCSystemKM: Failed to schedule MISR"));
1594 { 1586 goto Exit;
1595 goto ProcessedQueues; 1587 }
1596 }
1597
1598 OSWaitus(MAX_HW_TIME_US/WAIT_TRY_COUNT);
1599 } END_LOOP_UNTIL_TIMEOUT();
1600
1601 PVR_DPF((PVR_DBG_ERROR,"PVRSRVSwapToDCSystemKM: Failed to process queues"));
1602 eError = PVRSRV_ERROR_FAILED_TO_PROCESS_QUEUE;
1603 goto Exit;
1604 1588
1605ProcessedQueues:
1606 1589
1607 psSwapChain->psLastFlipBuffer = &psDCInfo->sSystemBuffer; 1590 psSwapChain->psLastFlipBuffer = &psDCInfo->sSystemBuffer;
1608 1591
@@ -1615,9 +1598,6 @@ Exit:
1615 eError = PVRSRV_ERROR_RETRY; 1598 eError = PVRSRV_ERROR_RETRY;
1616 } 1599 }
1617 1600
1618#if defined(SUPPORT_LMA)
1619 PVRSRVPowerUnlock(KERNEL_ID);
1620#endif
1621 return eError; 1601 return eError;
1622} 1602}
1623 1603
@@ -1736,17 +1716,29 @@ static PVRSRV_ERROR CloseBCDeviceCallBack(IMG_PVOID pvParam,
1736{ 1716{
1737 PVRSRV_BUFFERCLASS_PERCONTEXT_INFO *psBCPerContextInfo; 1717 PVRSRV_BUFFERCLASS_PERCONTEXT_INFO *psBCPerContextInfo;
1738 PVRSRV_BUFFERCLASS_INFO *psBCInfo; 1718 PVRSRV_BUFFERCLASS_INFO *psBCInfo;
1719 IMG_UINT32 i;
1739 1720
1740 PVR_UNREFERENCED_PARAMETER(ui32Param); 1721 PVR_UNREFERENCED_PARAMETER(ui32Param);
1741 1722
1742 psBCPerContextInfo = (PVRSRV_BUFFERCLASS_PERCONTEXT_INFO *)pvParam; 1723 psBCPerContextInfo = (PVRSRV_BUFFERCLASS_PERCONTEXT_INFO *)pvParam;
1724
1743 psBCInfo = psBCPerContextInfo->psBCInfo; 1725 psBCInfo = psBCPerContextInfo->psBCInfo;
1744 1726
1727 for (i = 0; i < psBCInfo->ui32BufferCount; i++)
1728 {
1729 if (psBCInfo->psBuffer[i].sDeviceClassBuffer.ui32MemMapRefCount != 0)
1730 {
1731 PVR_DPF((PVR_DBG_ERROR, "CloseBCDeviceCallBack: buffer %d (0x%p) still mapped (ui32MemMapRefCount = %d)",
1732 i,
1733 &psBCInfo->psBuffer[i].sDeviceClassBuffer,
1734 psBCInfo->psBuffer[i].sDeviceClassBuffer.ui32MemMapRefCount));
1735 return PVRSRV_ERROR_STILL_MAPPED;
1736 }
1737 }
1738
1745 psBCInfo->ui32RefCount--; 1739 psBCInfo->ui32RefCount--;
1746 if(psBCInfo->ui32RefCount == 0) 1740 if(psBCInfo->ui32RefCount == 0)
1747 { 1741 {
1748 IMG_UINT32 i;
1749
1750 1742
1751 psBCInfo->psFuncTable->pfnCloseBCDevice(psBCInfo->ui32DeviceID, psBCInfo->hExtDevice); 1743 psBCInfo->psFuncTable->pfnCloseBCDevice(psBCInfo->ui32DeviceID, psBCInfo->hExtDevice);
1752 1744
@@ -1900,6 +1892,7 @@ PVRSRV_ERROR PVRSRVOpenBCDeviceKM (PVRSRV_PER_PROCESS_DATA *psPerProc,
1900 psBCInfo->psBuffer[i].sDeviceClassBuffer.pfnGetBufferAddr = psBCInfo->psFuncTable->pfnGetBufferAddr; 1892 psBCInfo->psBuffer[i].sDeviceClassBuffer.pfnGetBufferAddr = psBCInfo->psFuncTable->pfnGetBufferAddr;
1901 psBCInfo->psBuffer[i].sDeviceClassBuffer.hDevMemContext = psBCInfo->hDevMemContext; 1893 psBCInfo->psBuffer[i].sDeviceClassBuffer.hDevMemContext = psBCInfo->hDevMemContext;
1902 psBCInfo->psBuffer[i].sDeviceClassBuffer.hExtDevice = psBCInfo->hExtDevice; 1894 psBCInfo->psBuffer[i].sDeviceClassBuffer.hExtDevice = psBCInfo->hExtDevice;
1895 psBCInfo->psBuffer[i].sDeviceClassBuffer.ui32MemMapRefCount = 0;
1903 } 1896 }
1904 } 1897 }
1905 1898
diff --git a/drivers/gpu/pvr/devicemem.c b/drivers/gpu/pvr/devicemem.c
index aeba0deb0cb..a14308b9351 100644
--- a/drivers/gpu/pvr/devicemem.c
+++ b/drivers/gpu/pvr/devicemem.c
@@ -52,12 +52,18 @@ typedef struct _PVRSRV_DC_MAPINFO_
52 PVRSRV_DEVICE_NODE *psDeviceNode; 52 PVRSRV_DEVICE_NODE *psDeviceNode;
53 IMG_UINT32 ui32RangeIndex; 53 IMG_UINT32 ui32RangeIndex;
54 IMG_UINT32 ui32TilingStride; 54 IMG_UINT32 ui32TilingStride;
55 PVRSRV_DEVICECLASS_BUFFER *psDeviceClassBuffer;
55} PVRSRV_DC_MAPINFO; 56} PVRSRV_DC_MAPINFO;
56 57
58static IMG_UINT32 g_ui32SyncUID = 0;
57 59
58IMG_EXPORT 60IMG_EXPORT
59PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDeviceMemHeapsKM(IMG_HANDLE hDevCookie, 61PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDeviceMemHeapsKM(IMG_HANDLE hDevCookie,
62#if defined (SUPPORT_SID_INTERFACE)
63 PVRSRV_HEAP_INFO_KM *psHeapInfo)
64#else
60 PVRSRV_HEAP_INFO *psHeapInfo) 65 PVRSRV_HEAP_INFO *psHeapInfo)
66#endif
61{ 67{
62 PVRSRV_DEVICE_NODE *psDeviceNode; 68 PVRSRV_DEVICE_NODE *psDeviceNode;
63 IMG_UINT32 ui32HeapCount; 69 IMG_UINT32 ui32HeapCount;
@@ -105,7 +111,11 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVCreateDeviceMemContextKM(IMG_HANDLE hDevCook
105 PVRSRV_PER_PROCESS_DATA *psPerProc, 111 PVRSRV_PER_PROCESS_DATA *psPerProc,
106 IMG_HANDLE *phDevMemContext, 112 IMG_HANDLE *phDevMemContext,
107 IMG_UINT32 *pui32ClientHeapCount, 113 IMG_UINT32 *pui32ClientHeapCount,
114#if defined (SUPPORT_SID_INTERFACE)
115 PVRSRV_HEAP_INFO_KM *psHeapInfo,
116#else
108 PVRSRV_HEAP_INFO *psHeapInfo, 117 PVRSRV_HEAP_INFO *psHeapInfo,
118#endif
109 IMG_BOOL *pbCreated, 119 IMG_BOOL *pbCreated,
110 IMG_BOOL *pbShared) 120 IMG_BOOL *pbShared)
111{ 121{
@@ -117,7 +127,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVCreateDeviceMemContextKM(IMG_HANDLE hDevCook
117 IMG_DEV_PHYADDR sPDDevPAddr; 127 IMG_DEV_PHYADDR sPDDevPAddr;
118 IMG_UINT32 i; 128 IMG_UINT32 i;
119 129
120#if !defined(PVR_SECURE_HANDLES) 130#if !defined(PVR_SECURE_HANDLES) && !defined (SUPPORT_SID_INTERFACE)
121 PVR_UNREFERENCED_PARAMETER(pbShared); 131 PVR_UNREFERENCED_PARAMETER(pbShared);
122#endif 132#endif
123 133
@@ -164,7 +174,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVCreateDeviceMemContextKM(IMG_HANDLE hDevCook
164 psHeapInfo[ui32ClientHeapCount].sDevVAddrBase = psDeviceMemoryHeap[i].sDevVAddrBase; 174 psHeapInfo[ui32ClientHeapCount].sDevVAddrBase = psDeviceMemoryHeap[i].sDevVAddrBase;
165 psHeapInfo[ui32ClientHeapCount].ui32HeapByteSize = psDeviceMemoryHeap[i].ui32HeapSize; 175 psHeapInfo[ui32ClientHeapCount].ui32HeapByteSize = psDeviceMemoryHeap[i].ui32HeapSize;
166 psHeapInfo[ui32ClientHeapCount].ui32Attribs = psDeviceMemoryHeap[i].ui32Attribs; 176 psHeapInfo[ui32ClientHeapCount].ui32Attribs = psDeviceMemoryHeap[i].ui32Attribs;
167#if defined(PVR_SECURE_HANDLES) 177#if defined(PVR_SECURE_HANDLES) || defined (SUPPORT_SID_INTERFACE)
168 pbShared[ui32ClientHeapCount] = IMG_TRUE; 178 pbShared[ui32ClientHeapCount] = IMG_TRUE;
169#endif 179#endif
170 ui32ClientHeapCount++; 180 ui32ClientHeapCount++;
@@ -172,8 +182,20 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVCreateDeviceMemContextKM(IMG_HANDLE hDevCook
172 } 182 }
173 case DEVICE_MEMORY_HEAP_PERCONTEXT: 183 case DEVICE_MEMORY_HEAP_PERCONTEXT:
174 { 184 {
175 hDevMemHeap = BM_CreateHeap(hDevMemContext, 185 if (psDeviceMemoryHeap[i].ui32HeapSize > 0)
176 &psDeviceMemoryHeap[i]); 186 {
187 hDevMemHeap = BM_CreateHeap(hDevMemContext,
188 &psDeviceMemoryHeap[i]);
189 if (hDevMemHeap == IMG_NULL)
190 {
191 BM_DestroyContext(hDevMemContext, IMG_NULL);
192 return PVRSRV_ERROR_OUT_OF_MEMORY;
193 }
194 }
195 else
196 {
197 hDevMemHeap = IMG_NULL;
198 }
177 199
178 200
179 psHeapInfo[ui32ClientHeapCount].ui32HeapID = psDeviceMemoryHeap[i].ui32HeapID; 201 psHeapInfo[ui32ClientHeapCount].ui32HeapID = psDeviceMemoryHeap[i].ui32HeapID;
@@ -181,7 +203,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVCreateDeviceMemContextKM(IMG_HANDLE hDevCook
181 psHeapInfo[ui32ClientHeapCount].sDevVAddrBase = psDeviceMemoryHeap[i].sDevVAddrBase; 203 psHeapInfo[ui32ClientHeapCount].sDevVAddrBase = psDeviceMemoryHeap[i].sDevVAddrBase;
182 psHeapInfo[ui32ClientHeapCount].ui32HeapByteSize = psDeviceMemoryHeap[i].ui32HeapSize; 204 psHeapInfo[ui32ClientHeapCount].ui32HeapByteSize = psDeviceMemoryHeap[i].ui32HeapSize;
183 psHeapInfo[ui32ClientHeapCount].ui32Attribs = psDeviceMemoryHeap[i].ui32Attribs; 205 psHeapInfo[ui32ClientHeapCount].ui32Attribs = psDeviceMemoryHeap[i].ui32Attribs;
184#if defined(PVR_SECURE_HANDLES) 206#if defined(PVR_SECURE_HANDLES) || defined (SUPPORT_SID_INTERFACE)
185 pbShared[ui32ClientHeapCount] = IMG_FALSE; 207 pbShared[ui32ClientHeapCount] = IMG_FALSE;
186#endif 208#endif
187 209
@@ -215,7 +237,11 @@ IMG_EXPORT
215PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDeviceMemHeapInfoKM(IMG_HANDLE hDevCookie, 237PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDeviceMemHeapInfoKM(IMG_HANDLE hDevCookie,
216 IMG_HANDLE hDevMemContext, 238 IMG_HANDLE hDevMemContext,
217 IMG_UINT32 *pui32ClientHeapCount, 239 IMG_UINT32 *pui32ClientHeapCount,
240#if defined (SUPPORT_SID_INTERFACE)
241 PVRSRV_HEAP_INFO_KM *psHeapInfo,
242#else
218 PVRSRV_HEAP_INFO *psHeapInfo, 243 PVRSRV_HEAP_INFO *psHeapInfo,
244#endif
219 IMG_BOOL *pbShared) 245 IMG_BOOL *pbShared)
220{ 246{
221 PVRSRV_DEVICE_NODE *psDeviceNode; 247 PVRSRV_DEVICE_NODE *psDeviceNode;
@@ -224,7 +250,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDeviceMemHeapInfoKM(IMG_HANDLE hDevCookie
224 IMG_HANDLE hDevMemHeap; 250 IMG_HANDLE hDevMemHeap;
225 IMG_UINT32 i; 251 IMG_UINT32 i;
226 252
227#if !defined(PVR_SECURE_HANDLES) 253#if !defined(PVR_SECURE_HANDLES) && !defined (SUPPORT_SID_INTERFACE)
228 PVR_UNREFERENCED_PARAMETER(pbShared); 254 PVR_UNREFERENCED_PARAMETER(pbShared);
229#endif 255#endif
230 256
@@ -259,7 +285,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDeviceMemHeapInfoKM(IMG_HANDLE hDevCookie
259 psHeapInfo[ui32ClientHeapCount].sDevVAddrBase = psDeviceMemoryHeap[i].sDevVAddrBase; 285 psHeapInfo[ui32ClientHeapCount].sDevVAddrBase = psDeviceMemoryHeap[i].sDevVAddrBase;
260 psHeapInfo[ui32ClientHeapCount].ui32HeapByteSize = psDeviceMemoryHeap[i].ui32HeapSize; 286 psHeapInfo[ui32ClientHeapCount].ui32HeapByteSize = psDeviceMemoryHeap[i].ui32HeapSize;
261 psHeapInfo[ui32ClientHeapCount].ui32Attribs = psDeviceMemoryHeap[i].ui32Attribs; 287 psHeapInfo[ui32ClientHeapCount].ui32Attribs = psDeviceMemoryHeap[i].ui32Attribs;
262#if defined(PVR_SECURE_HANDLES) 288#if defined(PVR_SECURE_HANDLES) || defined (SUPPORT_SID_INTERFACE)
263 pbShared[ui32ClientHeapCount] = IMG_TRUE; 289 pbShared[ui32ClientHeapCount] = IMG_TRUE;
264#endif 290#endif
265 ui32ClientHeapCount++; 291 ui32ClientHeapCount++;
@@ -267,8 +293,20 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDeviceMemHeapInfoKM(IMG_HANDLE hDevCookie
267 } 293 }
268 case DEVICE_MEMORY_HEAP_PERCONTEXT: 294 case DEVICE_MEMORY_HEAP_PERCONTEXT:
269 { 295 {
270 hDevMemHeap = BM_CreateHeap(hDevMemContext, 296 if (psDeviceMemoryHeap[i].ui32HeapSize > 0)
271 &psDeviceMemoryHeap[i]); 297 {
298 hDevMemHeap = BM_CreateHeap(hDevMemContext,
299 &psDeviceMemoryHeap[i]);
300
301 if (hDevMemHeap == IMG_NULL)
302 {
303 return PVRSRV_ERROR_OUT_OF_MEMORY;
304 }
305 }
306 else
307 {
308 hDevMemHeap = IMG_NULL;
309 }
272 310
273 311
274 psHeapInfo[ui32ClientHeapCount].ui32HeapID = psDeviceMemoryHeap[i].ui32HeapID; 312 psHeapInfo[ui32ClientHeapCount].ui32HeapID = psDeviceMemoryHeap[i].ui32HeapID;
@@ -276,7 +314,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDeviceMemHeapInfoKM(IMG_HANDLE hDevCookie
276 psHeapInfo[ui32ClientHeapCount].sDevVAddrBase = psDeviceMemoryHeap[i].sDevVAddrBase; 314 psHeapInfo[ui32ClientHeapCount].sDevVAddrBase = psDeviceMemoryHeap[i].sDevVAddrBase;
277 psHeapInfo[ui32ClientHeapCount].ui32HeapByteSize = psDeviceMemoryHeap[i].ui32HeapSize; 315 psHeapInfo[ui32ClientHeapCount].ui32HeapByteSize = psDeviceMemoryHeap[i].ui32HeapSize;
278 psHeapInfo[ui32ClientHeapCount].ui32Attribs = psDeviceMemoryHeap[i].ui32Attribs; 316 psHeapInfo[ui32ClientHeapCount].ui32Attribs = psDeviceMemoryHeap[i].ui32Attribs;
279#if defined(PVR_SECURE_HANDLES) 317#if defined(PVR_SECURE_HANDLES) || defined (SUPPORT_SID_INTERFACE)
280 pbShared[ui32ClientHeapCount] = IMG_FALSE; 318 pbShared[ui32ClientHeapCount] = IMG_FALSE;
281#endif 319#endif
282 320
@@ -354,7 +392,7 @@ static PVRSRV_ERROR AllocDeviceMem(IMG_HANDLE hDevCookie,
354 392
355 psMemInfo->sDevVAddr = psMemBlock->sDevVirtAddr; 393 psMemInfo->sDevVAddr = psMemBlock->sDevVirtAddr;
356 394
357 psMemInfo->ui32AllocSize = ui32Size; 395 psMemInfo->uAllocSize = ui32Size;
358 396
359 397
360 psMemInfo->pvSysBackupBuffer = IMG_NULL; 398 psMemInfo->pvSysBackupBuffer = IMG_NULL;
@@ -387,7 +425,7 @@ static PVRSRV_ERROR FreeDeviceMem2(PVRSRV_KERNEL_MEM_INFO *psMemInfo, IMG_BOOL b
387 if ((psMemInfo->pvSysBackupBuffer) && bFromAllocator) 425 if ((psMemInfo->pvSysBackupBuffer) && bFromAllocator)
388 { 426 {
389 427
390 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, psMemInfo->ui32AllocSize, psMemInfo->pvSysBackupBuffer, IMG_NULL); 428 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, psMemInfo->uAllocSize, psMemInfo->pvSysBackupBuffer, IMG_NULL);
391 psMemInfo->pvSysBackupBuffer = IMG_NULL; 429 psMemInfo->pvSysBackupBuffer = IMG_NULL;
392 } 430 }
393 431
@@ -415,7 +453,7 @@ static PVRSRV_ERROR FreeDeviceMem(PVRSRV_KERNEL_MEM_INFO *psMemInfo)
415 if(psMemInfo->pvSysBackupBuffer) 453 if(psMemInfo->pvSysBackupBuffer)
416 { 454 {
417 455
418 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, psMemInfo->ui32AllocSize, psMemInfo->pvSysBackupBuffer, IMG_NULL); 456 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, psMemInfo->uAllocSize, psMemInfo->pvSysBackupBuffer, IMG_NULL);
419 psMemInfo->pvSysBackupBuffer = IMG_NULL; 457 psMemInfo->pvSysBackupBuffer = IMG_NULL;
420 } 458 }
421 459
@@ -492,13 +530,14 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVAllocSyncInfoKM(IMG_HANDLE hDevCookie,
492 PDUMPMEM(psKernelSyncInfo->psSyncDataMemInfoKM->pvLinAddrKM, 530 PDUMPMEM(psKernelSyncInfo->psSyncDataMemInfoKM->pvLinAddrKM,
493 psKernelSyncInfo->psSyncDataMemInfoKM, 531 psKernelSyncInfo->psSyncDataMemInfoKM,
494 0, 532 0,
495 psKernelSyncInfo->psSyncDataMemInfoKM->ui32AllocSize, 533 (IMG_UINT32)psKernelSyncInfo->psSyncDataMemInfoKM->uAllocSize,
496 PDUMP_FLAGS_CONTINUOUS, 534 PDUMP_FLAGS_CONTINUOUS,
497 MAKEUNIQUETAG(psKernelSyncInfo->psSyncDataMemInfoKM)); 535 MAKEUNIQUETAG(psKernelSyncInfo->psSyncDataMemInfoKM));
498#endif 536#endif
499 537
500 psKernelSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr = psKernelSyncInfo->psSyncDataMemInfoKM->sDevVAddr.uiAddr + offsetof(PVRSRV_SYNC_DATA, ui32WriteOpsComplete); 538 psKernelSyncInfo->sWriteOpsCompleteDevVAddr.uiAddr = psKernelSyncInfo->psSyncDataMemInfoKM->sDevVAddr.uiAddr + offsetof(PVRSRV_SYNC_DATA, ui32WriteOpsComplete);
501 psKernelSyncInfo->sReadOpsCompleteDevVAddr.uiAddr = psKernelSyncInfo->psSyncDataMemInfoKM->sDevVAddr.uiAddr + offsetof(PVRSRV_SYNC_DATA, ui32ReadOpsComplete); 539 psKernelSyncInfo->sReadOpsCompleteDevVAddr.uiAddr = psKernelSyncInfo->psSyncDataMemInfoKM->sDevVAddr.uiAddr + offsetof(PVRSRV_SYNC_DATA, ui32ReadOpsComplete);
540 psKernelSyncInfo->ui32UID = g_ui32SyncUID++;
502 541
503 542
504 psKernelSyncInfo->psSyncDataMemInfoKM->psKernelSyncInfo = IMG_NULL; 543 psKernelSyncInfo->psSyncDataMemInfoKM->psKernelSyncInfo = IMG_NULL;
@@ -514,14 +553,14 @@ IMG_EXPORT
514PVRSRV_ERROR IMG_CALLCONV PVRSRVFreeSyncInfoKM(PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo) 553PVRSRV_ERROR IMG_CALLCONV PVRSRVFreeSyncInfoKM(PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo)
515{ 554{
516 PVRSRV_ERROR eError; 555 PVRSRV_ERROR eError;
517 556
518 if (psKernelSyncInfo->ui32RefCount != 0) 557 if (psKernelSyncInfo->ui32RefCount != 0)
519 { 558 {
520 PVR_DPF((PVR_DBG_ERROR, "oops: sync info ref count not zero at destruction")); 559 PVR_DPF((PVR_DBG_ERROR, "oops: sync info ref count not zero at destruction"));
521 560
522 return PVRSRV_ERROR_OUT_OF_MEMORY; 561 return PVRSRV_ERROR_OUT_OF_MEMORY;
523 } 562 }
524 563
525 eError = FreeDeviceMem(psKernelSyncInfo->psSyncDataMemInfoKM); 564 eError = FreeDeviceMem(psKernelSyncInfo->psSyncDataMemInfoKM);
526 (IMG_VOID)OSFreeMem(PVRSRV_PAGEABLE_SELECT, sizeof(PVRSRV_KERNEL_SYNC_INFO), psKernelSyncInfo, IMG_NULL); 565 (IMG_VOID)OSFreeMem(PVRSRV_PAGEABLE_SELECT, sizeof(PVRSRV_KERNEL_SYNC_INFO), psKernelSyncInfo, IMG_NULL);
527 566
@@ -558,9 +597,13 @@ static PVRSRV_ERROR FreeMemCallBackCommon(PVRSRV_KERNEL_MEM_INFO *psMemInfo,
558 psMemInfo->ui32RefCount--; 597 psMemInfo->ui32RefCount--;
559 598
560 599
561 if((psMemInfo->ui32Flags & PVRSRV_MEM_EXPORTED) && (bFromAllocator == IMG_TRUE)) 600 if(((psMemInfo->ui32Flags & PVRSRV_MEM_EXPORTED) != 0) && (bFromAllocator == IMG_TRUE))
562 { 601 {
602#if defined (SUPPORT_SID_INTERFACE)
603 IMG_SID hMemInfo = 0;
604#else
563 IMG_HANDLE hMemInfo = IMG_NULL; 605 IMG_HANDLE hMemInfo = IMG_NULL;
606#endif
564 607
565 608
566 eError = PVRSRVFindHandle(KERNEL_HANDLE_BASE, 609 eError = PVRSRVFindHandle(KERNEL_HANDLE_BASE,
@@ -611,8 +654,10 @@ static PVRSRV_ERROR FreeMemCallBackCommon(PVRSRV_KERNEL_MEM_INFO *psMemInfo,
611 } 654 }
612 655
613 656
614 657 if (eError == PVRSRV_OK)
615 eError = FreeDeviceMem2(psMemInfo, bFromAllocator); 658 {
659 eError = FreeDeviceMem2(psMemInfo, bFromAllocator);
660 }
616 661
617 return eError; 662 return eError;
618} 663}
@@ -821,8 +866,8 @@ IMG_EXPORT
821PVRSRV_ERROR IMG_CALLCONV PVRSRVWrapExtMemoryKM(IMG_HANDLE hDevCookie, 866PVRSRV_ERROR IMG_CALLCONV PVRSRVWrapExtMemoryKM(IMG_HANDLE hDevCookie,
822 PVRSRV_PER_PROCESS_DATA *psPerProc, 867 PVRSRV_PER_PROCESS_DATA *psPerProc,
823 IMG_HANDLE hDevMemContext, 868 IMG_HANDLE hDevMemContext,
824 IMG_SIZE_T ui32ByteSize, 869 IMG_SIZE_T uByteSize,
825 IMG_SIZE_T ui32PageOffset, 870 IMG_SIZE_T uPageOffset,
826 IMG_BOOL bPhysContig, 871 IMG_BOOL bPhysContig,
827 IMG_SYS_PHYADDR *psExtSysPAddr, 872 IMG_SYS_PHYADDR *psExtSysPAddr,
828 IMG_VOID *pvLinAddr, 873 IMG_VOID *pvLinAddr,
@@ -842,11 +887,11 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVWrapExtMemoryKM(IMG_HANDLE hDevCookie,
842 IMG_VOID *pvPageAlignedCPUVAddr; 887 IMG_VOID *pvPageAlignedCPUVAddr;
843 IMG_SYS_PHYADDR *psIntSysPAddr = IMG_NULL; 888 IMG_SYS_PHYADDR *psIntSysPAddr = IMG_NULL;
844 IMG_HANDLE hOSWrapMem = IMG_NULL; 889 IMG_HANDLE hOSWrapMem = IMG_NULL;
845 DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap; 890 DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap;
846 IMG_UINT32 i; 891 IMG_UINT32 i;
847 IMG_SIZE_T ui32PageCount = 0; 892 IMG_SIZE_T uPageCount = 0;
848 893
849 894
850 psDeviceNode = (PVRSRV_DEVICE_NODE*)hDevCookie; 895 psDeviceNode = (PVRSRV_DEVICE_NODE*)hDevCookie;
851 PVR_ASSERT(psDeviceNode != IMG_NULL); 896 PVR_ASSERT(psDeviceNode != IMG_NULL);
852 897
@@ -859,15 +904,15 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVWrapExtMemoryKM(IMG_HANDLE hDevCookie,
859 if(pvLinAddr) 904 if(pvLinAddr)
860 { 905 {
861 906
862 ui32PageOffset = (IMG_UINTPTR_T)pvLinAddr & (ui32HostPageSize - 1); 907 uPageOffset = (IMG_UINTPTR_T)pvLinAddr & (ui32HostPageSize - 1);
863 908
864 909
865 ui32PageCount = HOST_PAGEALIGN(ui32ByteSize + ui32PageOffset) / ui32HostPageSize; 910 uPageCount = HOST_PAGEALIGN(uByteSize + uPageOffset) / ui32HostPageSize;
866 pvPageAlignedCPUVAddr = (IMG_VOID *)((IMG_UINTPTR_T)pvLinAddr - ui32PageOffset); 911 pvPageAlignedCPUVAddr = (IMG_VOID *)((IMG_UINTPTR_T)pvLinAddr - uPageOffset);
867 912
868 913
869 if(OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, 914 if(OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
870 ui32PageCount * sizeof(IMG_SYS_PHYADDR), 915 uPageCount * sizeof(IMG_SYS_PHYADDR),
871 (IMG_VOID **)&psIntSysPAddr, IMG_NULL, 916 (IMG_VOID **)&psIntSysPAddr, IMG_NULL,
872 "Array of Page Addresses") != PVRSRV_OK) 917 "Array of Page Addresses") != PVRSRV_OK)
873 { 918 {
@@ -876,7 +921,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVWrapExtMemoryKM(IMG_HANDLE hDevCookie,
876 } 921 }
877 922
878 eError = OSAcquirePhysPageAddr(pvPageAlignedCPUVAddr, 923 eError = OSAcquirePhysPageAddr(pvPageAlignedCPUVAddr,
879 ui32PageCount * ui32HostPageSize, 924 uPageCount * ui32HostPageSize,
880 psIntSysPAddr, 925 psIntSysPAddr,
881 &hOSWrapMem); 926 &hOSWrapMem);
882 if(eError != PVRSRV_OK) 927 if(eError != PVRSRV_OK)
@@ -897,7 +942,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVWrapExtMemoryKM(IMG_HANDLE hDevCookie,
897 { 942 {
898 943
899 } 944 }
900 945
901 946
902 psDevMemoryInfo = &((BM_CONTEXT*)hDevMemContext)->psDeviceNode->sDevMemoryInfo; 947 psDevMemoryInfo = &((BM_CONTEXT*)hDevMemContext)->psDeviceNode->sDevMemoryInfo;
903 psDeviceMemoryHeap = psDevMemoryInfo->psDeviceMemoryHeap; 948 psDeviceMemoryHeap = psDevMemoryInfo->psDeviceMemoryHeap;
@@ -908,7 +953,14 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVWrapExtMemoryKM(IMG_HANDLE hDevCookie,
908 if(psDeviceMemoryHeap[i].DevMemHeapType == DEVICE_MEMORY_HEAP_PERCONTEXT) 953 if(psDeviceMemoryHeap[i].DevMemHeapType == DEVICE_MEMORY_HEAP_PERCONTEXT)
909 { 954 {
910 955
911 hDevMemHeap = BM_CreateHeap(hDevMemContext, &psDeviceMemoryHeap[i]); 956 if (psDeviceMemoryHeap[i].ui32HeapSize > 0)
957 {
958 hDevMemHeap = BM_CreateHeap(hDevMemContext, &psDeviceMemoryHeap[i]);
959 }
960 else
961 {
962 hDevMemHeap = IMG_NULL;
963 }
912 } 964 }
913 else 965 else
914 { 966 {
@@ -941,8 +993,8 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVWrapExtMemoryKM(IMG_HANDLE hDevCookie,
941 psMemBlock = &(psMemInfo->sMemBlk); 993 psMemBlock = &(psMemInfo->sMemBlk);
942 994
943 bBMError = BM_Wrap(hDevMemHeap, 995 bBMError = BM_Wrap(hDevMemHeap,
944 ui32ByteSize, 996 uByteSize,
945 ui32PageOffset, 997 uPageOffset,
946 bPhysContig, 998 bPhysContig,
947 psExtSysPAddr, 999 psExtSysPAddr,
948 IMG_NULL, 1000 IMG_NULL,
@@ -967,7 +1019,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVWrapExtMemoryKM(IMG_HANDLE hDevCookie,
967 1019
968 psMemInfo->pvLinAddrKM = BM_HandleToCpuVaddr(hBuffer); 1020 psMemInfo->pvLinAddrKM = BM_HandleToCpuVaddr(hBuffer);
969 psMemInfo->sDevVAddr = psMemBlock->sDevVirtAddr; 1021 psMemInfo->sDevVAddr = psMemBlock->sDevVirtAddr;
970 psMemInfo->ui32AllocSize = ui32ByteSize; 1022 psMemInfo->uAllocSize = uByteSize;
971 1023
972 1024
973 1025
@@ -1033,10 +1085,10 @@ ErrorExitPhase2:
1033ErrorExitPhase1: 1085ErrorExitPhase1:
1034 if(psIntSysPAddr) 1086 if(psIntSysPAddr)
1035 { 1087 {
1036 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, ui32PageCount * sizeof(IMG_SYS_PHYADDR), psIntSysPAddr, IMG_NULL); 1088 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, uPageCount * sizeof(IMG_SYS_PHYADDR), psIntSysPAddr, IMG_NULL);
1037 1089
1038 } 1090 }
1039 1091
1040 return eError; 1092 return eError;
1041} 1093}
1042 1094
@@ -1080,7 +1132,7 @@ static PVRSRV_ERROR UnmapDeviceMemoryCallBack(IMG_PVOID pvParam,
1080 } 1132 }
1081 } 1133 }
1082 } 1134 }
1083 1135
1084 eError = FreeDeviceMem(psMapData->psMemInfo); 1136 eError = FreeDeviceMem(psMapData->psMemInfo);
1085 if(eError != PVRSRV_OK) 1137 if(eError != PVRSRV_OK)
1086 { 1138 {
@@ -1106,7 +1158,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceMemoryKM(PVRSRV_PER_PROCESS_DATA *psPer
1106{ 1158{
1107 PVRSRV_ERROR eError; 1159 PVRSRV_ERROR eError;
1108 IMG_UINT32 i; 1160 IMG_UINT32 i;
1109 IMG_SIZE_T ui32PageCount, ui32PageOffset; 1161 IMG_SIZE_T uPageCount, uPageOffset;
1110 IMG_SIZE_T ui32HostPageSize = HOST_PAGESIZE(); 1162 IMG_SIZE_T ui32HostPageSize = HOST_PAGESIZE();
1111 IMG_SYS_PHYADDR *psSysPAddr = IMG_NULL; 1163 IMG_SYS_PHYADDR *psSysPAddr = IMG_NULL;
1112 IMG_DEV_PHYADDR sDevPAddr; 1164 IMG_DEV_PHYADDR sDevPAddr;
@@ -1130,16 +1182,16 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceMemoryKM(PVRSRV_PER_PROCESS_DATA *psPer
1130 1182
1131 *ppsDstMemInfo = IMG_NULL; 1183 *ppsDstMemInfo = IMG_NULL;
1132 1184
1133 ui32PageOffset = psSrcMemInfo->sDevVAddr.uiAddr & (ui32HostPageSize - 1); 1185 uPageOffset = psSrcMemInfo->sDevVAddr.uiAddr & (ui32HostPageSize - 1);
1134 ui32PageCount = HOST_PAGEALIGN(psSrcMemInfo->ui32AllocSize + ui32PageOffset) / ui32HostPageSize; 1186 uPageCount = HOST_PAGEALIGN(psSrcMemInfo->uAllocSize + uPageOffset) / ui32HostPageSize;
1135 pvPageAlignedCPUVAddr = (IMG_VOID *)((IMG_UINTPTR_T)psSrcMemInfo->pvLinAddrKM - ui32PageOffset); 1187 pvPageAlignedCPUVAddr = (IMG_VOID *)((IMG_UINTPTR_T)psSrcMemInfo->pvLinAddrKM - uPageOffset);
1136 1188
1137 1189
1138 1190
1139 1191
1140 1192
1141 if(OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, 1193 if(OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
1142 ui32PageCount*sizeof(IMG_SYS_PHYADDR), 1194 uPageCount*sizeof(IMG_SYS_PHYADDR),
1143 (IMG_VOID **)&psSysPAddr, IMG_NULL, 1195 (IMG_VOID **)&psSysPAddr, IMG_NULL,
1144 "Array of Page Addresses") != PVRSRV_OK) 1196 "Array of Page Addresses") != PVRSRV_OK)
1145 { 1197 {
@@ -1153,8 +1205,8 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceMemoryKM(PVRSRV_PER_PROCESS_DATA *psPer
1153 psDeviceNode = psBuf->pMapping->pBMHeap->pBMContext->psDeviceNode; 1205 psDeviceNode = psBuf->pMapping->pBMHeap->pBMContext->psDeviceNode;
1154 1206
1155 1207
1156 sDevVAddr.uiAddr = psSrcMemInfo->sDevVAddr.uiAddr - IMG_CAST_TO_DEVVADDR_UINT(ui32PageOffset); 1208 sDevVAddr.uiAddr = psSrcMemInfo->sDevVAddr.uiAddr - IMG_CAST_TO_DEVVADDR_UINT(uPageOffset);
1157 for(i=0; i<ui32PageCount; i++) 1209 for(i=0; i<uPageCount; i++)
1158 { 1210 {
1159 BM_GetPhysPageAddr(psSrcMemInfo, sDevVAddr, &sDevPAddr); 1211 BM_GetPhysPageAddr(psSrcMemInfo, sDevVAddr, &sDevPAddr);
1160 1212
@@ -1176,7 +1228,6 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceMemoryKM(PVRSRV_PER_PROCESS_DATA *psPer
1176 goto ErrorExit; 1228 goto ErrorExit;
1177 } 1229 }
1178 1230
1179
1180 if(OSAllocMem(PVRSRV_PAGEABLE_SELECT, 1231 if(OSAllocMem(PVRSRV_PAGEABLE_SELECT,
1181 sizeof(PVRSRV_KERNEL_MEM_INFO), 1232 sizeof(PVRSRV_KERNEL_MEM_INFO),
1182 (IMG_VOID **)&psMemInfo, IMG_NULL, 1233 (IMG_VOID **)&psMemInfo, IMG_NULL,
@@ -1193,8 +1244,8 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceMemoryKM(PVRSRV_PER_PROCESS_DATA *psPer
1193 psMemBlock = &(psMemInfo->sMemBlk); 1244 psMemBlock = &(psMemInfo->sMemBlk);
1194 1245
1195 bBMError = BM_Wrap(hDstDevMemHeap, 1246 bBMError = BM_Wrap(hDstDevMemHeap,
1196 psSrcMemInfo->ui32AllocSize, 1247 psSrcMemInfo->uAllocSize,
1197 ui32PageOffset, 1248 uPageOffset,
1198 IMG_FALSE, 1249 IMG_FALSE,
1199 psSysPAddr, 1250 psSysPAddr,
1200 pvPageAlignedCPUVAddr, 1251 pvPageAlignedCPUVAddr,
@@ -1223,12 +1274,14 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceMemoryKM(PVRSRV_PER_PROCESS_DATA *psPer
1223 1274
1224 1275
1225 psMemInfo->sDevVAddr = psMemBlock->sDevVirtAddr; 1276 psMemInfo->sDevVAddr = psMemBlock->sDevVirtAddr;
1226 psMemInfo->ui32AllocSize = psSrcMemInfo->ui32AllocSize; 1277 psMemInfo->uAllocSize = psSrcMemInfo->uAllocSize;
1227 psMemInfo->psKernelSyncInfo = psSrcMemInfo->psKernelSyncInfo; 1278 psMemInfo->psKernelSyncInfo = psSrcMemInfo->psKernelSyncInfo;
1228 1279
1229 1280
1230 if( psMemInfo->psKernelSyncInfo ) 1281 if(psMemInfo->psKernelSyncInfo)
1282 {
1231 psMemInfo->psKernelSyncInfo->ui32RefCount++; 1283 psMemInfo->psKernelSyncInfo->ui32RefCount++;
1284 }
1232 1285
1233 1286
1234 1287
@@ -1324,6 +1377,11 @@ static PVRSRV_ERROR UnmapDeviceClassMemoryCallBack(IMG_PVOID pvParam,
1324 } 1377 }
1325#endif 1378#endif
1326 1379
1380 (psDCMapInfo->psDeviceClassBuffer->ui32MemMapRefCount)--;
1381 PVR_TRACE(("decrementing (0x%p) psDCMapInfo->psDeviceClassBuffer->ui32MemMapRefCount... == %d",
1382 psDCMapInfo->psDeviceClassBuffer,
1383 psDCMapInfo->psDeviceClassBuffer->ui32MemMapRefCount));
1384
1327 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(PVRSRV_DC_MAPINFO), psDCMapInfo, IMG_NULL); 1385 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, sizeof(PVRSRV_DC_MAPINFO), psDCMapInfo, IMG_NULL);
1328 1386
1329 return FreeMemCallBackCommon(psMemInfo, ui32Param, IMG_TRUE); 1387 return FreeMemCallBackCommon(psMemInfo, ui32Param, IMG_TRUE);
@@ -1348,7 +1406,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceClassMemoryKM(PVRSRV_PER_PROCESS_DATA *
1348 DEVICE_MEMORY_INFO *psDevMemoryInfo; 1406 DEVICE_MEMORY_INFO *psDevMemoryInfo;
1349 DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap; 1407 DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap;
1350 IMG_HANDLE hDevMemHeap = IMG_NULL; 1408 IMG_HANDLE hDevMemHeap = IMG_NULL;
1351 IMG_SIZE_T ui32ByteSize; 1409 IMG_SIZE_T uByteSize;
1352 IMG_SIZE_T ui32Offset; 1410 IMG_SIZE_T ui32Offset;
1353 IMG_SIZE_T ui32PageSize = HOST_PAGESIZE(); 1411 IMG_SIZE_T ui32PageSize = HOST_PAGESIZE();
1354 BM_HANDLE hBuffer; 1412 BM_HANDLE hBuffer;
@@ -1398,7 +1456,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceClassMemoryKM(PVRSRV_PER_PROCESS_DATA *
1398 eError = psDeviceClassBuffer->pfnGetBufferAddr(psDeviceClassBuffer->hExtDevice, 1456 eError = psDeviceClassBuffer->pfnGetBufferAddr(psDeviceClassBuffer->hExtDevice,
1399 psDeviceClassBuffer->hExtBuffer, 1457 psDeviceClassBuffer->hExtBuffer,
1400 &psSysPAddr, 1458 &psSysPAddr,
1401 &ui32ByteSize, 1459 &uByteSize,
1402 &pvCPUVAddr, 1460 &pvCPUVAddr,
1403 phOSMapInfo, 1461 phOSMapInfo,
1404 &bPhysContig, 1462 &bPhysContig,
@@ -1421,7 +1479,14 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceClassMemoryKM(PVRSRV_PER_PROCESS_DATA *
1421 if(psDeviceMemoryHeap[i].DevMemHeapType == DEVICE_MEMORY_HEAP_PERCONTEXT) 1479 if(psDeviceMemoryHeap[i].DevMemHeapType == DEVICE_MEMORY_HEAP_PERCONTEXT)
1422 { 1480 {
1423 1481
1424 hDevMemHeap = BM_CreateHeap(hDevMemContext, &psDeviceMemoryHeap[i]); 1482 if (psDeviceMemoryHeap[i].ui32HeapSize > 0)
1483 {
1484 hDevMemHeap = BM_CreateHeap(hDevMemContext, &psDeviceMemoryHeap[i]);
1485 }
1486 else
1487 {
1488 hDevMemHeap = IMG_NULL;
1489 }
1425 } 1490 }
1426 else 1491 else
1427 { 1492 {
@@ -1457,7 +1522,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceClassMemoryKM(PVRSRV_PER_PROCESS_DATA *
1457 psMemBlock = &(psMemInfo->sMemBlk); 1522 psMemBlock = &(psMemInfo->sMemBlk);
1458 1523
1459 bBMError = BM_Wrap(hDevMemHeap, 1524 bBMError = BM_Wrap(hDevMemHeap,
1460 ui32ByteSize, 1525 uByteSize,
1461 ui32Offset, 1526 ui32Offset,
1462 bPhysContig, 1527 bPhysContig,
1463 psSysPAddr, 1528 psSysPAddr,
@@ -1486,7 +1551,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceClassMemoryKM(PVRSRV_PER_PROCESS_DATA *
1486 1551
1487 1552
1488 psMemInfo->sDevVAddr = psMemBlock->sDevVirtAddr; 1553 psMemInfo->sDevVAddr = psMemBlock->sDevVirtAddr;
1489 psMemInfo->ui32AllocSize = ui32ByteSize; 1554 psMemInfo->uAllocSize = uByteSize;
1490 psMemInfo->psKernelSyncInfo = psDeviceClassBuffer->psKernelSyncInfo; 1555 psMemInfo->psKernelSyncInfo = psDeviceClassBuffer->psKernelSyncInfo;
1491 1556
1492 1557
@@ -1495,6 +1560,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceClassMemoryKM(PVRSRV_PER_PROCESS_DATA *
1495 1560
1496 1561
1497 psDCMapInfo->psMemInfo = psMemInfo; 1562 psDCMapInfo->psMemInfo = psMemInfo;
1563 psDCMapInfo->psDeviceClassBuffer = psDeviceClassBuffer;
1498 1564
1499#if defined(SUPPORT_MEMORY_TILING) 1565#if defined(SUPPORT_MEMORY_TILING)
1500 psDCMapInfo->psDeviceNode = psDeviceNode; 1566 psDCMapInfo->psDeviceNode = psDeviceNode;
@@ -1521,6 +1587,11 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceClassMemoryKM(PVRSRV_PER_PROCESS_DATA *
1521 0, 1587 0,
1522 &UnmapDeviceClassMemoryCallBack); 1588 &UnmapDeviceClassMemoryCallBack);
1523 1589
1590 (psDeviceClassBuffer->ui32MemMapRefCount)++;
1591 PVR_TRACE(("incrementing (0x%p) psDeviceClassBuffer->ui32MemMapRefCount... == %d",
1592 psDeviceClassBuffer,
1593 psDeviceClassBuffer->ui32MemMapRefCount));
1594
1524 psMemInfo->ui32RefCount++; 1595 psMemInfo->ui32RefCount++;
1525 1596
1526 psMemInfo->memType = PVRSRV_MEMTYPE_DEVICECLASS; 1597 psMemInfo->memType = PVRSRV_MEMTYPE_DEVICECLASS;
@@ -1529,9 +1600,9 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceClassMemoryKM(PVRSRV_PER_PROCESS_DATA *
1529 *ppsMemInfo = psMemInfo; 1600 *ppsMemInfo = psMemInfo;
1530 1601
1531#if defined(SUPPORT_PDUMP_MULTI_PROCESS) 1602#if defined(SUPPORT_PDUMP_MULTI_PROCESS)
1532 1603
1533 PDUMPCOMMENT("Dump display surface"); 1604 PDUMPCOMMENT("Dump display surface");
1534 PDUMPMEM(IMG_NULL, psMemInfo, ui32Offset, psMemInfo->ui32AllocSize, PDUMP_FLAGS_CONTINUOUS, ((BM_BUF*)psMemInfo->sMemBlk.hBuffer)->pMapping); 1605 PDUMPMEM(IMG_NULL, psMemInfo, ui32Offset, psMemInfo->uAllocSize, PDUMP_FLAGS_CONTINUOUS, ((BM_BUF*)psMemInfo->sMemBlk.hBuffer)->pMapping);
1535#endif 1606#endif
1536 return PVRSRV_OK; 1607 return PVRSRV_OK;
1537 1608
@@ -1562,3 +1633,29 @@ ErrorExitPhase1:
1562 return eError; 1633 return eError;
1563} 1634}
1564 1635
1636
1637IMG_EXPORT
1638PVRSRV_ERROR IMG_CALLCONV PVRSRVChangeDeviceMemoryAttributesKM(IMG_HANDLE hKernelMemInfo, IMG_UINT32 ui32Attribs)
1639{
1640 PVRSRV_KERNEL_MEM_INFO *psKMMemInfo;
1641
1642 if (hKernelMemInfo == IMG_NULL)
1643 {
1644 return PVRSRV_ERROR_INVALID_PARAMS;
1645 }
1646
1647 psKMMemInfo = (PVRSRV_KERNEL_MEM_INFO *)hKernelMemInfo;
1648
1649 if (ui32Attribs & PVRSRV_CHANGEDEVMEM_ATTRIBS_CACHECOHERENT)
1650 {
1651 psKMMemInfo->ui32Flags |= PVRSRV_MEM_CACHE_CONSISTENT;
1652 }
1653 else
1654 {
1655 psKMMemInfo->ui32Flags &= ~PVRSRV_MEM_CACHE_CONSISTENT;
1656 }
1657
1658 return PVRSRV_OK;
1659}
1660
1661
diff --git a/drivers/gpu/pvr/handle.c b/drivers/gpu/pvr/handle.c
index 5e34af5b280..de80394384c 100644
--- a/drivers/gpu/pvr/handle.c
+++ b/drivers/gpu/pvr/handle.c
@@ -24,7 +24,7 @@
24 * 24 *
25 ******************************************************************************/ 25 ******************************************************************************/
26 26
27#ifdef PVR_SECURE_HANDLES 27#if defined(PVR_SECURE_HANDLES) || defined (SUPPORT_SID_INTERFACE)
28#include <stddef.h> 28#include <stddef.h>
29 29
30#include "services_headers.h" 30#include "services_headers.h"
@@ -47,8 +47,14 @@
47 47
48#define INDEX_IS_VALID(psBase, i) ((i) < (psBase)->ui32TotalHandCount) 48#define INDEX_IS_VALID(psBase, i) ((i) < (psBase)->ui32TotalHandCount)
49 49
50#define INDEX_TO_HANDLE(i) ((IMG_HANDLE)((i) + 1)) 50#if defined (SUPPORT_SID_INTERFACE)
51#define INDEX_TO_HANDLE(i) ((IMG_SID)((i) + 1))
51#define HANDLE_TO_INDEX(h) ((IMG_UINT32)(h) - 1) 52#define HANDLE_TO_INDEX(h) ((IMG_UINT32)(h) - 1)
53#else
54#define INDEX_TO_HANDLE(i) ((IMG_HANDLE)((IMG_UINTPTR_T)(i) + 1))
55#define HANDLE_TO_INDEX(h) ((IMG_UINT32)(IMG_UINTPTR_T)(h) - 1)
56
57#endif
52 58
53#define INDEX_TO_BLOCK_INDEX(i) DIVIDE_BY_BLOCK_SIZE(i) 59#define INDEX_TO_BLOCK_INDEX(i) DIVIDE_BY_BLOCK_SIZE(i)
54#define BLOCK_INDEX_TO_INDEX(i) MULTIPLY_BY_BLOCK_SIZE(i) 60#define BLOCK_INDEX_TO_INDEX(i) MULTIPLY_BY_BLOCK_SIZE(i)
@@ -108,7 +114,11 @@ struct sHandleList
108{ 114{
109 IMG_UINT32 ui32Prev; 115 IMG_UINT32 ui32Prev;
110 IMG_UINT32 ui32Next; 116 IMG_UINT32 ui32Next;
117#if defined (SUPPORT_SID_INTERFACE)
118 IMG_SID hParent;
119#else
111 IMG_HANDLE hParent; 120 IMG_HANDLE hParent;
121#endif
112}; 122};
113 123
114enum ePVRSRVInternalHandleFlag 124enum ePVRSRVInternalHandleFlag
@@ -217,7 +227,11 @@ typedef IMG_UINTPTR_T HAND_KEY[HAND_KEY_LEN];
217#pragma inline(HandleListInit) 227#pragma inline(HandleListInit)
218#endif 228#endif
219static INLINE 229static INLINE
230#if defined (SUPPORT_SID_INTERFACE)
231IMG_VOID HandleListInit(IMG_UINT32 ui32Index, struct sHandleList *psList, IMG_SID hParent)
232#else
220IMG_VOID HandleListInit(IMG_UINT32 ui32Index, struct sHandleList *psList, IMG_HANDLE hParent) 233IMG_VOID HandleListInit(IMG_UINT32 ui32Index, struct sHandleList *psList, IMG_HANDLE hParent)
234#endif
221{ 235{
222 psList->ui32Next = ui32Index; 236 psList->ui32Next = ui32Index;
223 psList->ui32Prev = ui32Index; 237 psList->ui32Prev = ui32Index;
@@ -259,7 +273,7 @@ IMG_BOOL HandleListIsEmpty(IMG_UINT32 ui32Index, struct sHandleList *psList)
259 IMG_BOOL bIsEmpty2; 273 IMG_BOOL bIsEmpty2;
260 274
261 bIsEmpty2 = (IMG_BOOL)(psList->ui32Prev == ui32Index); 275 bIsEmpty2 = (IMG_BOOL)(psList->ui32Prev == ui32Index);
262 PVR_ASSERT(bIsEmpty == bIsEmpty2); 276 PVR_ASSERT(bIsEmpty == bIsEmpty2)
263 } 277 }
264#endif 278#endif
265 279
@@ -273,7 +287,7 @@ IMG_BOOL HandleListIsEmpty(IMG_UINT32 ui32Index, struct sHandleList *psList)
273static INLINE 287static INLINE
274IMG_BOOL NoChildren(struct sHandle *psHandle) 288IMG_BOOL NoChildren(struct sHandle *psHandle)
275{ 289{
276 PVR_ASSERT(psHandle->sChildren.hParent == HANDLE_PTR_TO_HANDLE(psHandle)); 290 PVR_ASSERT(psHandle->sChildren.hParent == HANDLE_PTR_TO_HANDLE(psHandle))
277 291
278 return HandleListIsEmpty(HANDLE_PTR_TO_INDEX(psHandle), &psHandle->sChildren); 292 return HandleListIsEmpty(HANDLE_PTR_TO_INDEX(psHandle), &psHandle->sChildren);
279} 293}
@@ -286,13 +300,13 @@ IMG_BOOL NoParent(struct sHandle *psHandle)
286{ 300{
287 if (HandleListIsEmpty(HANDLE_PTR_TO_INDEX(psHandle), &psHandle->sSiblings)) 301 if (HandleListIsEmpty(HANDLE_PTR_TO_INDEX(psHandle), &psHandle->sSiblings))
288 { 302 {
289 PVR_ASSERT(psHandle->sSiblings.hParent == IMG_NULL); 303 PVR_ASSERT(psHandle->sSiblings.hParent == IMG_NULL)
290 304
291 return IMG_TRUE; 305 return IMG_TRUE;
292 } 306 }
293 else 307 else
294 { 308 {
295 PVR_ASSERT(psHandle->sSiblings.hParent != IMG_NULL); 309 PVR_ASSERT(psHandle->sSiblings.hParent != IMG_NULL)
296 } 310 }
297 return IMG_FALSE; 311 return IMG_FALSE;
298} 312}
@@ -301,7 +315,11 @@ IMG_BOOL NoParent(struct sHandle *psHandle)
301#pragma inline(ParentHandle) 315#pragma inline(ParentHandle)
302#endif 316#endif
303static INLINE 317static INLINE
318#if defined (SUPPORT_SID_INTERFACE)
319IMG_SID ParentHandle(struct sHandle *psHandle)
320#else
304IMG_HANDLE ParentHandle(struct sHandle *psHandle) 321IMG_HANDLE ParentHandle(struct sHandle *psHandle)
322#endif
305{ 323{
306 return psHandle->sSiblings.hParent; 324 return psHandle->sSiblings.hParent;
307} 325}
@@ -318,9 +336,9 @@ IMG_VOID HandleListInsertBefore(PVRSRV_HANDLE_BASE *psBase, IMG_UINT32 ui32InsIn
318 336
319 struct sHandleList *psPrevIns = LIST_PTR_FROM_INDEX_AND_OFFSET(psBase, psIns->ui32Prev, ui32ParentIndex, uiParentOffset, uiEntryOffset); 337 struct sHandleList *psPrevIns = LIST_PTR_FROM_INDEX_AND_OFFSET(psBase, psIns->ui32Prev, ui32ParentIndex, uiParentOffset, uiEntryOffset);
320 338
321 PVR_ASSERT(psEntry->hParent == IMG_NULL); 339 PVR_ASSERT(psEntry->hParent == IMG_NULL)
322 PVR_ASSERT(ui32InsIndex == psPrevIns->ui32Next); 340 PVR_ASSERT(ui32InsIndex == psPrevIns->ui32Next)
323 PVR_ASSERT(LIST_PTR_FROM_INDEX_AND_OFFSET(psBase, ui32ParentIndex, ui32ParentIndex, uiParentOffset, uiParentOffset)->hParent == INDEX_TO_HANDLE(ui32ParentIndex)); 341 PVR_ASSERT(LIST_PTR_FROM_INDEX_AND_OFFSET(psBase, ui32ParentIndex, ui32ParentIndex, uiParentOffset, uiParentOffset)->hParent == INDEX_TO_HANDLE(ui32ParentIndex))
324 342
325 psEntry->ui32Prev = psIns->ui32Prev; 343 psEntry->ui32Prev = psIns->ui32Prev;
326 psIns->ui32Prev = ui32EntryIndex; 344 psIns->ui32Prev = ui32EntryIndex;
@@ -338,7 +356,7 @@ IMG_VOID AdoptChild(PVRSRV_HANDLE_BASE *psBase, struct sHandle *psParent, struct
338{ 356{
339 IMG_UINT32 ui32Parent = HANDLE_TO_INDEX(psParent->sChildren.hParent); 357 IMG_UINT32 ui32Parent = HANDLE_TO_INDEX(psParent->sChildren.hParent);
340 358
341 PVR_ASSERT(ui32Parent == HANDLE_PTR_TO_INDEX(psParent)); 359 PVR_ASSERT(ui32Parent == HANDLE_PTR_TO_INDEX(psParent))
342 360
343 HandleListInsertBefore(psBase, ui32Parent, &psParent->sChildren, offsetof(struct sHandle, sChildren), HANDLE_PTR_TO_INDEX(psChild), &psChild->sSiblings, offsetof(struct sHandle, sSiblings), ui32Parent); 361 HandleListInsertBefore(psBase, ui32Parent, &psParent->sChildren, offsetof(struct sHandle, sChildren), HANDLE_PTR_TO_INDEX(psChild), &psChild->sSiblings, offsetof(struct sHandle, sSiblings), ui32Parent);
344 362
@@ -357,7 +375,7 @@ IMG_VOID HandleListRemove(PVRSRV_HANDLE_BASE *psBase, IMG_UINT32 ui32EntryIndex,
357 struct sHandleList *psNext = LIST_PTR_FROM_INDEX_AND_OFFSET(psBase, psEntry->ui32Next, HANDLE_TO_INDEX(psEntry->hParent), uiParentOffset, uiEntryOffset); 375 struct sHandleList *psNext = LIST_PTR_FROM_INDEX_AND_OFFSET(psBase, psEntry->ui32Next, HANDLE_TO_INDEX(psEntry->hParent), uiParentOffset, uiEntryOffset);
358 376
359 377
360 PVR_ASSERT(psEntry->hParent != IMG_NULL); 378 PVR_ASSERT(psEntry->hParent != IMG_NULL)
361 379
362 psPrev->ui32Next = psEntry->ui32Next; 380 psPrev->ui32Next = psEntry->ui32Next;
363 psNext->ui32Prev = psEntry->ui32Prev; 381 psNext->ui32Prev = psEntry->ui32Prev;
@@ -384,7 +402,7 @@ PVRSRV_ERROR HandleListIterate(PVRSRV_HANDLE_BASE *psBase, struct sHandleList *p
384 IMG_UINT32 ui32Index; 402 IMG_UINT32 ui32Index;
385 IMG_UINT32 ui32Parent = HANDLE_TO_INDEX(psHead->hParent); 403 IMG_UINT32 ui32Parent = HANDLE_TO_INDEX(psHead->hParent);
386 404
387 PVR_ASSERT(psHead->hParent != IMG_NULL); 405 PVR_ASSERT(psHead->hParent != IMG_NULL)
388 406
389 407
390 for(ui32Index = psHead->ui32Next; ui32Index != ui32Parent; ) 408 for(ui32Index = psHead->ui32Next; ui32Index != ui32Parent; )
@@ -394,7 +412,7 @@ PVRSRV_ERROR HandleListIterate(PVRSRV_HANDLE_BASE *psBase, struct sHandleList *p
394 struct sHandleList *psEntry = LIST_PTR_FROM_INDEX_AND_OFFSET(psBase, ui32Index, ui32Parent, uiParentOffset, uiEntryOffset); 412 struct sHandleList *psEntry = LIST_PTR_FROM_INDEX_AND_OFFSET(psBase, ui32Index, ui32Parent, uiParentOffset, uiEntryOffset);
395 PVRSRV_ERROR eError; 413 PVRSRV_ERROR eError;
396 414
397 PVR_ASSERT(psEntry->hParent == psHead->hParent); 415 PVR_ASSERT(psEntry->hParent == psHead->hParent)
398 416
399 ui32Index = psEntry->ui32Next; 417 ui32Index = psEntry->ui32Next;
400 418
@@ -421,7 +439,11 @@ PVRSRV_ERROR IterateOverChildren(PVRSRV_HANDLE_BASE *psBase, struct sHandle *psP
421#pragma inline(GetHandleStructure) 439#pragma inline(GetHandleStructure)
422#endif 440#endif
423static INLINE 441static INLINE
442#if defined (SUPPORT_SID_INTERFACE)
443PVRSRV_ERROR GetHandleStructure(PVRSRV_HANDLE_BASE *psBase, struct sHandle **ppsHandle, IMG_SID hHandle, PVRSRV_HANDLE_TYPE eType)
444#else
424PVRSRV_ERROR GetHandleStructure(PVRSRV_HANDLE_BASE *psBase, struct sHandle **ppsHandle, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType) 445PVRSRV_ERROR GetHandleStructure(PVRSRV_HANDLE_BASE *psBase, struct sHandle **ppsHandle, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType)
446#endif
425{ 447{
426 IMG_UINT32 ui32Index = HANDLE_TO_INDEX(hHandle); 448 IMG_UINT32 ui32Index = HANDLE_TO_INDEX(hHandle);
427 struct sHandle *psHandle; 449 struct sHandle *psHandle;
@@ -430,6 +452,9 @@ PVRSRV_ERROR GetHandleStructure(PVRSRV_HANDLE_BASE *psBase, struct sHandle **pps
430 if (!INDEX_IS_VALID(psBase, ui32Index)) 452 if (!INDEX_IS_VALID(psBase, ui32Index))
431 { 453 {
432 PVR_DPF((PVR_DBG_ERROR, "GetHandleStructure: Handle index out of range (%u >= %u)", ui32Index, psBase->ui32TotalHandCount)); 454 PVR_DPF((PVR_DBG_ERROR, "GetHandleStructure: Handle index out of range (%u >= %u)", ui32Index, psBase->ui32TotalHandCount));
455#if defined (SUPPORT_SID_INTERFACE)
456 PVR_DBG_BREAK
457#endif
433 return PVRSRV_ERROR_HANDLE_INDEX_OUT_OF_RANGE; 458 return PVRSRV_ERROR_HANDLE_INDEX_OUT_OF_RANGE;
434 } 459 }
435 460
@@ -437,6 +462,9 @@ PVRSRV_ERROR GetHandleStructure(PVRSRV_HANDLE_BASE *psBase, struct sHandle **pps
437 if (psHandle->eType == PVRSRV_HANDLE_TYPE_NONE) 462 if (psHandle->eType == PVRSRV_HANDLE_TYPE_NONE)
438 { 463 {
439 PVR_DPF((PVR_DBG_ERROR, "GetHandleStructure: Handle not allocated (index: %u)", ui32Index)); 464 PVR_DPF((PVR_DBG_ERROR, "GetHandleStructure: Handle not allocated (index: %u)", ui32Index));
465#if defined (SUPPORT_SID_INTERFACE)
466 PVR_DBG_BREAK
467#endif
440 return PVRSRV_ERROR_HANDLE_NOT_ALLOCATED; 468 return PVRSRV_ERROR_HANDLE_NOT_ALLOCATED;
441 } 469 }
442 470
@@ -444,6 +472,9 @@ PVRSRV_ERROR GetHandleStructure(PVRSRV_HANDLE_BASE *psBase, struct sHandle **pps
444 if (eType != PVRSRV_HANDLE_TYPE_NONE && eType != psHandle->eType) 472 if (eType != PVRSRV_HANDLE_TYPE_NONE && eType != psHandle->eType)
445 { 473 {
446 PVR_DPF((PVR_DBG_ERROR, "GetHandleStructure: Handle type mismatch (%d != %d)", eType, psHandle->eType)); 474 PVR_DPF((PVR_DBG_ERROR, "GetHandleStructure: Handle type mismatch (%d != %d)", eType, psHandle->eType));
475#if defined (SUPPORT_SID_INTERFACE)
476 PVR_DBG_BREAK
477#endif
447 return PVRSRV_ERROR_HANDLE_TYPE_MISMATCH; 478 return PVRSRV_ERROR_HANDLE_TYPE_MISMATCH;
448 } 479 }
449 480
@@ -457,7 +488,11 @@ PVRSRV_ERROR GetHandleStructure(PVRSRV_HANDLE_BASE *psBase, struct sHandle **pps
457#pragma inline(ParentIfPrivate) 488#pragma inline(ParentIfPrivate)
458#endif 489#endif
459static INLINE 490static INLINE
491#if defined (SUPPORT_SID_INTERFACE)
492IMG_SID ParentIfPrivate(struct sHandle *psHandle)
493#else
460IMG_HANDLE ParentIfPrivate(struct sHandle *psHandle) 494IMG_HANDLE ParentIfPrivate(struct sHandle *psHandle)
495#endif
461{ 496{
462 return TEST_ALLOC_FLAG(psHandle, PVRSRV_HANDLE_ALLOC_FLAG_PRIVATE) ? 497 return TEST_ALLOC_FLAG(psHandle, PVRSRV_HANDLE_ALLOC_FLAG_PRIVATE) ?
463 ParentHandle(psHandle) : IMG_NULL; 498 ParentHandle(psHandle) : IMG_NULL;
@@ -467,7 +502,11 @@ IMG_HANDLE ParentIfPrivate(struct sHandle *psHandle)
467#pragma inline(InitKey) 502#pragma inline(InitKey)
468#endif 503#endif
469static INLINE 504static INLINE
505#if defined (SUPPORT_SID_INTERFACE)
506IMG_VOID InitKey(HAND_KEY aKey, PVRSRV_HANDLE_BASE *psBase, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, IMG_SID hParent)
507#else
470IMG_VOID InitKey(HAND_KEY aKey, PVRSRV_HANDLE_BASE *psBase, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, IMG_HANDLE hParent) 508IMG_VOID InitKey(HAND_KEY aKey, PVRSRV_HANDLE_BASE *psBase, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, IMG_HANDLE hParent)
509#endif
471{ 510{
472 PVR_UNREFERENCED_PARAMETER(psBase); 511 PVR_UNREFERENCED_PARAMETER(psBase);
473 512
@@ -502,8 +541,8 @@ PVRSRV_ERROR ReallocHandleArray(PVRSRV_HANDLE_BASE *psBase, IMG_UINT32 ui32NewCo
502 if (((ui32OldCount % HANDLE_BLOCK_SIZE) != 0) || 541 if (((ui32OldCount % HANDLE_BLOCK_SIZE) != 0) ||
503 ((ui32NewCount % HANDLE_BLOCK_SIZE) != 0)) 542 ((ui32NewCount % HANDLE_BLOCK_SIZE) != 0))
504 { 543 {
505 PVR_ASSERT((ui32OldCount % HANDLE_BLOCK_SIZE) == 0); 544 PVR_ASSERT((ui32OldCount % HANDLE_BLOCK_SIZE) == 0)
506 PVR_ASSERT((ui32NewCount % HANDLE_BLOCK_SIZE) == 0); 545 PVR_ASSERT((ui32NewCount % HANDLE_BLOCK_SIZE) == 0)
507 546
508 return PVRSRV_ERROR_INVALID_PARAMS; 547 return PVRSRV_ERROR_INVALID_PARAMS;
509 } 548 }
@@ -511,7 +550,7 @@ PVRSRV_ERROR ReallocHandleArray(PVRSRV_HANDLE_BASE *psBase, IMG_UINT32 ui32NewCo
511 if (ui32NewCount != 0) 550 if (ui32NewCount != 0)
512 { 551 {
513 552
514 eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, 553 eError = OSAllocMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
515 HANDLE_ARRAY_SIZE(ui32NewCount) * sizeof(struct sHandleIndex), 554 HANDLE_ARRAY_SIZE(ui32NewCount) * sizeof(struct sHandleIndex),
516 (IMG_VOID **)&psNewArray, 555 (IMG_VOID **)&psNewArray,
517 &hNewArrayBlockAlloc, 556 &hNewArrayBlockAlloc,
@@ -550,7 +589,7 @@ PVRSRV_ERROR ReallocHandleArray(PVRSRV_HANDLE_BASE *psBase, IMG_UINT32 ui32NewCo
550 589
551 struct sHandleIndex *psIndex = INDEX_TO_INDEX_STRUCT_PTR(psNewArray, ui32Index); 590 struct sHandleIndex *psIndex = INDEX_TO_INDEX_STRUCT_PTR(psNewArray, ui32Index);
552 591
553 eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, 592 eError = OSAllocMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
554 sizeof(struct sHandle) * HANDLE_BLOCK_SIZE, 593 sizeof(struct sHandle) * HANDLE_BLOCK_SIZE,
555 (IMG_VOID **)&psIndex->psHandle, 594 (IMG_VOID **)&psIndex->psHandle,
556 &psIndex->hBlockAlloc, 595 &psIndex->hBlockAlloc,
@@ -658,12 +697,12 @@ PVRSRV_ERROR ReallocHandleArray(PVRSRV_HANDLE_BASE *psBase, IMG_UINT32 ui32NewCo
658 } 697 }
659 } 698 }
660 699
661 PVR_ASSERT(psBase->ui32FirstFreeIndex <= psBase->ui32TotalHandCount); 700 PVR_ASSERT(psBase->ui32FirstFreeIndex <= psBase->ui32TotalHandCount)
662 701
663 return PVRSRV_OK; 702 return PVRSRV_OK;
664 703
665error: 704error:
666 PVR_ASSERT(eReturn != PVRSRV_OK); 705 PVR_ASSERT(eReturn != PVRSRV_OK)
667 706
668 if (psNewArray != IMG_NULL) 707 if (psNewArray != IMG_NULL)
669 { 708 {
@@ -714,11 +753,17 @@ static PVRSRV_ERROR FreeHandle(PVRSRV_HANDLE_BASE *psBase, struct sHandle *psHan
714 753
715 if (!TEST_ALLOC_FLAG(psHandle, PVRSRV_HANDLE_ALLOC_FLAG_MULTI) && !BATCHED_HANDLE_PARTIALLY_FREE(psHandle)) 754 if (!TEST_ALLOC_FLAG(psHandle, PVRSRV_HANDLE_ALLOC_FLAG_MULTI) && !BATCHED_HANDLE_PARTIALLY_FREE(psHandle))
716 { 755 {
756#if defined (SUPPORT_SID_INTERFACE)
757 IMG_SID hHandle;
758 hHandle = (IMG_SID) HASH_Remove_Extended(psBase->psHashTab, aKey);
759#else
717 IMG_HANDLE hHandle; 760 IMG_HANDLE hHandle;
718 hHandle = (IMG_HANDLE) HASH_Remove_Extended(psBase->psHashTab, aKey); 761 hHandle = (IMG_HANDLE) HASH_Remove_Extended(psBase->psHashTab, aKey);
719 762
720 PVR_ASSERT(hHandle != IMG_NULL); 763#endif
721 PVR_ASSERT(hHandle == INDEX_TO_HANDLE(ui32Index)); 764
765 PVR_ASSERT(hHandle != IMG_NULL)
766 PVR_ASSERT(hHandle == INDEX_TO_HANDLE(ui32Index))
722 PVR_UNREFERENCED_PARAMETER(hHandle); 767 PVR_UNREFERENCED_PARAMETER(hHandle);
723 } 768 }
724 769
@@ -749,20 +794,20 @@ static PVRSRV_ERROR FreeHandle(PVRSRV_HANDLE_BASE *psBase, struct sHandle *psHan
749 { 794 {
750 if (psBase->ui32FreeHandCount == 0) 795 if (psBase->ui32FreeHandCount == 0)
751 { 796 {
752 PVR_ASSERT(psBase->ui32FirstFreeIndex == 0); 797 PVR_ASSERT(psBase->ui32FirstFreeIndex == 0)
753 PVR_ASSERT(psBase->ui32LastFreeIndexPlusOne == 0); 798 PVR_ASSERT(psBase->ui32LastFreeIndexPlusOne == 0)
754 799
755 psBase->ui32FirstFreeIndex = ui32Index; 800 psBase->ui32FirstFreeIndex = ui32Index;
756 } 801 }
757 else 802 else
758 { 803 {
759 804
760 PVR_ASSERT(psBase->ui32LastFreeIndexPlusOne != 0); 805 PVR_ASSERT(psBase->ui32LastFreeIndexPlusOne != 0)
761 PVR_ASSERT(INDEX_TO_HANDLE_STRUCT_PTR(psBase, psBase->ui32LastFreeIndexPlusOne - 1)->ui32NextIndexPlusOne == 0); 806 PVR_ASSERT(INDEX_TO_HANDLE_STRUCT_PTR(psBase, psBase->ui32LastFreeIndexPlusOne - 1)->ui32NextIndexPlusOne == 0)
762 INDEX_TO_HANDLE_STRUCT_PTR(psBase, psBase->ui32LastFreeIndexPlusOne - 1)->ui32NextIndexPlusOne = ui32Index + 1; 807 INDEX_TO_HANDLE_STRUCT_PTR(psBase, psBase->ui32LastFreeIndexPlusOne - 1)->ui32NextIndexPlusOne = ui32Index + 1;
763 } 808 }
764 809
765 PVR_ASSERT(psHandle->ui32NextIndexPlusOne == 0); 810 PVR_ASSERT(psHandle->ui32NextIndexPlusOne == 0)
766 811
767 812
768 psBase->ui32LastFreeIndexPlusOne = ui32Index + 1; 813 psBase->ui32LastFreeIndexPlusOne = ui32Index + 1;
@@ -771,7 +816,7 @@ static PVRSRV_ERROR FreeHandle(PVRSRV_HANDLE_BASE *psBase, struct sHandle *psHan
771 psBase->ui32FreeHandCount++; 816 psBase->ui32FreeHandCount++;
772 INDEX_TO_FREE_HAND_BLOCK_COUNT(psBase, ui32Index)++; 817 INDEX_TO_FREE_HAND_BLOCK_COUNT(psBase, ui32Index)++;
773 818
774 PVR_ASSERT(INDEX_TO_FREE_HAND_BLOCK_COUNT(psBase, ui32Index)<= HANDLE_BLOCK_SIZE); 819 PVR_ASSERT(INDEX_TO_FREE_HAND_BLOCK_COUNT(psBase, ui32Index)<= HANDLE_BLOCK_SIZE)
775 820
776#ifdef DEBUG 821#ifdef DEBUG
777 { 822 {
@@ -783,7 +828,7 @@ static PVRSRV_ERROR FreeHandle(PVRSRV_HANDLE_BASE *psBase, struct sHandle *psHan
783 ui32FreeHandCount += INDEX_TO_FREE_HAND_BLOCK_COUNT(psBase, ui32BlockedIndex); 828 ui32FreeHandCount += INDEX_TO_FREE_HAND_BLOCK_COUNT(psBase, ui32BlockedIndex);
784 } 829 }
785 830
786 PVR_ASSERT(ui32FreeHandCount == psBase->ui32FreeHandCount); 831 PVR_ASSERT(ui32FreeHandCount == psBase->ui32FreeHandCount)
787 } 832 }
788#endif 833#endif
789 834
@@ -875,15 +920,23 @@ static PVRSRV_ERROR FreeHandleBase(PVRSRV_HANDLE_BASE *psBase)
875#pragma inline(FindHandle) 920#pragma inline(FindHandle)
876#endif 921#endif
877static INLINE 922static INLINE
923#if defined (SUPPORT_SID_INTERFACE)
924IMG_SID FindHandle(PVRSRV_HANDLE_BASE *psBase, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, IMG_SID hParent)
925#else
878IMG_HANDLE FindHandle(PVRSRV_HANDLE_BASE *psBase, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, IMG_HANDLE hParent) 926IMG_HANDLE FindHandle(PVRSRV_HANDLE_BASE *psBase, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, IMG_HANDLE hParent)
927#endif
879{ 928{
880 HAND_KEY aKey; 929 HAND_KEY aKey;
881 930
882 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE); 931 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE)
883 932
884 InitKey(aKey, psBase, pvData, eType, hParent); 933 InitKey(aKey, psBase, pvData, eType, hParent);
885 934
935#if defined (SUPPORT_SID_INTERFACE)
936 return (IMG_SID) HASH_Retrieve_Extended(psBase->psHashTab, aKey);
937#else
886 return (IMG_HANDLE) HASH_Retrieve_Extended(psBase->psHashTab, aKey); 938 return (IMG_HANDLE) HASH_Retrieve_Extended(psBase->psHashTab, aKey);
939#endif
887} 940}
888 941
889static PVRSRV_ERROR IncreaseHandleArraySize(PVRSRV_HANDLE_BASE *psBase, IMG_UINT32 ui32Delta) 942static PVRSRV_ERROR IncreaseHandleArraySize(PVRSRV_HANDLE_BASE *psBase, IMG_UINT32 ui32Delta)
@@ -893,7 +946,7 @@ static PVRSRV_ERROR IncreaseHandleArraySize(PVRSRV_HANDLE_BASE *psBase, IMG_UINT
893 IMG_UINT32 ui32NewTotalHandCount = psBase->ui32TotalHandCount + ui32DeltaAdjusted; 946 IMG_UINT32 ui32NewTotalHandCount = psBase->ui32TotalHandCount + ui32DeltaAdjusted;
894; 947;
895 948
896 PVR_ASSERT(ui32Delta != 0); 949 PVR_ASSERT(ui32Delta != 0)
897 950
898 951
899 if (ui32NewTotalHandCount > psBase->ui32MaxIndexPlusOne || ui32NewTotalHandCount <= psBase->ui32TotalHandCount) 952 if (ui32NewTotalHandCount > psBase->ui32MaxIndexPlusOne || ui32NewTotalHandCount <= psBase->ui32TotalHandCount)
@@ -909,7 +962,7 @@ static PVRSRV_ERROR IncreaseHandleArraySize(PVRSRV_HANDLE_BASE *psBase, IMG_UINT
909 } 962 }
910 } 963 }
911 964
912 PVR_ASSERT(ui32DeltaAdjusted >= ui32Delta); 965 PVR_ASSERT(ui32DeltaAdjusted >= ui32Delta)
913 966
914 967
915 eError = ReallocHandleArray(psBase, ui32NewTotalHandCount); 968 eError = ReallocHandleArray(psBase, ui32NewTotalHandCount);
@@ -941,28 +994,36 @@ static PVRSRV_ERROR EnsureFreeHandles(PVRSRV_HANDLE_BASE *psBase, IMG_UINT32 ui3
941 return PVRSRV_OK; 994 return PVRSRV_OK;
942} 995}
943 996
997#if defined (SUPPORT_SID_INTERFACE)
998static PVRSRV_ERROR AllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_SID *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, PVRSRV_HANDLE_ALLOC_FLAG eFlag, IMG_SID hParent)
999#else
944static PVRSRV_ERROR AllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, PVRSRV_HANDLE_ALLOC_FLAG eFlag, IMG_HANDLE hParent) 1000static PVRSRV_ERROR AllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, PVRSRV_HANDLE_ALLOC_FLAG eFlag, IMG_HANDLE hParent)
1001#endif
945{ 1002{
946 IMG_UINT32 ui32NewIndex = DEFAULT_MAX_INDEX_PLUS_ONE; 1003 IMG_UINT32 ui32NewIndex = DEFAULT_MAX_INDEX_PLUS_ONE;
947 struct sHandle *psNewHandle = IMG_NULL; 1004 struct sHandle *psNewHandle = IMG_NULL;
1005#if defined (SUPPORT_SID_INTERFACE)
1006 IMG_SID hHandle;
1007#else
948 IMG_HANDLE hHandle; 1008 IMG_HANDLE hHandle;
1009#endif
949 HAND_KEY aKey; 1010 HAND_KEY aKey;
950 PVRSRV_ERROR eError; 1011 PVRSRV_ERROR eError;
951 1012
952 1013
953 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE); 1014 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE)
954 PVR_ASSERT(psBase != IMG_NULL); 1015 PVR_ASSERT(psBase != IMG_NULL)
955 PVR_ASSERT(psBase->psHashTab != IMG_NULL); 1016 PVR_ASSERT(psBase->psHashTab != IMG_NULL)
956 1017
957 if (!TEST_FLAG(eFlag, PVRSRV_HANDLE_ALLOC_FLAG_MULTI)) 1018 if (!TEST_FLAG(eFlag, PVRSRV_HANDLE_ALLOC_FLAG_MULTI))
958 { 1019 {
959 1020
960 PVR_ASSERT(FindHandle(psBase, pvData, eType, hParent) == IMG_NULL); 1021 PVR_ASSERT(FindHandle(psBase, pvData, eType, hParent) == IMG_NULL)
961 } 1022 }
962 1023
963 if (psBase->ui32FreeHandCount == 0 && HANDLES_BATCHED(psBase)) 1024 if (psBase->ui32FreeHandCount == 0 && HANDLES_BATCHED(psBase))
964 { 1025 {
965 PVR_DPF((PVR_DBG_WARNING, "AllocHandle: Handle batch size (%u) was too small, allocating additional space", psBase->ui32HandBatchSize)); 1026 PVR_DPF((PVR_DBG_WARNING, "AllocHandle: Handle batch size (%u) was too small, allocating additional space", psBase->ui32HandBatchSize));
966 } 1027 }
967 1028
968 1029
@@ -988,7 +1049,7 @@ static PVRSRV_ERROR AllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle
988 1049
989 1050
990 1051
991 PVR_ASSERT((psBase->ui32FirstFreeIndex % HANDLE_BLOCK_SIZE) == 0); 1052 PVR_ASSERT((psBase->ui32FirstFreeIndex % HANDLE_BLOCK_SIZE) == 0)
992 1053
993 for (ui32BlockedIndex = ROUND_DOWN_TO_MULTIPLE_OF_BLOCK_SIZE(psBase->ui32FirstFreeIndex); ui32BlockedIndex < psBase->ui32TotalHandCount; ui32BlockedIndex += HANDLE_BLOCK_SIZE) 1054 for (ui32BlockedIndex = ROUND_DOWN_TO_MULTIPLE_OF_BLOCK_SIZE(psBase->ui32FirstFreeIndex); ui32BlockedIndex < psBase->ui32TotalHandCount; ui32BlockedIndex += HANDLE_BLOCK_SIZE)
994 { 1055 {
@@ -1009,9 +1070,9 @@ static PVRSRV_ERROR AllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle
1009 } 1070 }
1010 } 1071 }
1011 psBase->ui32FirstFreeIndex = 0; 1072 psBase->ui32FirstFreeIndex = 0;
1012 PVR_ASSERT(ui32NewIndex < psBase->ui32TotalHandCount); 1073 PVR_ASSERT(ui32NewIndex < psBase->ui32TotalHandCount)
1013 } 1074 }
1014 PVR_ASSERT(psNewHandle != IMG_NULL); 1075 PVR_ASSERT(psNewHandle != IMG_NULL)
1015 1076
1016 1077
1017 hHandle = INDEX_TO_HANDLE(ui32NewIndex); 1078 hHandle = INDEX_TO_HANDLE(ui32NewIndex);
@@ -1033,8 +1094,8 @@ static PVRSRV_ERROR AllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle
1033 1094
1034 psBase->ui32FreeHandCount--; 1095 psBase->ui32FreeHandCount--;
1035 1096
1036 PVR_ASSERT(INDEX_TO_FREE_HAND_BLOCK_COUNT(psBase, ui32NewIndex) <= HANDLE_BLOCK_SIZE); 1097 PVR_ASSERT(INDEX_TO_FREE_HAND_BLOCK_COUNT(psBase, ui32NewIndex) <= HANDLE_BLOCK_SIZE)
1037 PVR_ASSERT(INDEX_TO_FREE_HAND_BLOCK_COUNT(psBase, ui32NewIndex) > 0); 1098 PVR_ASSERT(INDEX_TO_FREE_HAND_BLOCK_COUNT(psBase, ui32NewIndex) > 0)
1038 1099
1039 INDEX_TO_FREE_HAND_BLOCK_COUNT(psBase, ui32NewIndex)--; 1100 INDEX_TO_FREE_HAND_BLOCK_COUNT(psBase, ui32NewIndex)--;
1040 1101
@@ -1044,8 +1105,8 @@ static PVRSRV_ERROR AllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle
1044 1105
1045 if (psBase->ui32FreeHandCount == 0) 1106 if (psBase->ui32FreeHandCount == 0)
1046 { 1107 {
1047 PVR_ASSERT(psBase->ui32FirstFreeIndex == ui32NewIndex); 1108 PVR_ASSERT(psBase->ui32FirstFreeIndex == ui32NewIndex)
1048 PVR_ASSERT(psBase->ui32LastFreeIndexPlusOne == (ui32NewIndex + 1)); 1109 PVR_ASSERT(psBase->ui32LastFreeIndexPlusOne == (ui32NewIndex + 1))
1049 1110
1050 psBase->ui32LastFreeIndexPlusOne = 0; 1111 psBase->ui32LastFreeIndexPlusOne = 0;
1051 psBase->ui32FirstFreeIndex = 0; 1112 psBase->ui32FirstFreeIndex = 0;
@@ -1060,7 +1121,7 @@ static PVRSRV_ERROR AllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle
1060 } 1121 }
1061 1122
1062 1123
1063 PVR_ASSERT(psNewHandle->ui32Index == ui32NewIndex); 1124 PVR_ASSERT(psNewHandle->ui32Index == ui32NewIndex)
1064 1125
1065 1126
1066 psNewHandle->eType = eType; 1127 psNewHandle->eType = eType;
@@ -1070,12 +1131,12 @@ static PVRSRV_ERROR AllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle
1070 1131
1071 InitParentList(psNewHandle); 1132 InitParentList(psNewHandle);
1072#if defined(DEBUG) 1133#if defined(DEBUG)
1073 PVR_ASSERT(NoChildren(psNewHandle)); 1134 PVR_ASSERT(NoChildren(psNewHandle))
1074#endif 1135#endif
1075 1136
1076 InitChildEntry(psNewHandle); 1137 InitChildEntry(psNewHandle);
1077#if defined(DEBUG) 1138#if defined(DEBUG)
1078 PVR_ASSERT(NoParent(psNewHandle)); 1139 PVR_ASSERT(NoParent(psNewHandle))
1079#endif 1140#endif
1080 1141
1081 if (HANDLES_BATCHED(psBase)) 1142 if (HANDLES_BATCHED(psBase))
@@ -1099,12 +1160,24 @@ static PVRSRV_ERROR AllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle
1099 return PVRSRV_OK; 1160 return PVRSRV_OK;
1100} 1161}
1101 1162
1163#if defined (SUPPORT_SID_INTERFACE)
1164PVRSRV_ERROR PVRSRVAllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_SID *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, PVRSRV_HANDLE_ALLOC_FLAG eFlag)
1165#else
1102PVRSRV_ERROR PVRSRVAllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, PVRSRV_HANDLE_ALLOC_FLAG eFlag) 1166PVRSRV_ERROR PVRSRVAllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, PVRSRV_HANDLE_ALLOC_FLAG eFlag)
1167#endif
1103{ 1168{
1169#if defined (SUPPORT_SID_INTERFACE)
1170 IMG_SID hHandle;
1171#else
1104 IMG_HANDLE hHandle; 1172 IMG_HANDLE hHandle;
1173#endif
1105 PVRSRV_ERROR eError; 1174 PVRSRV_ERROR eError;
1106 1175
1176#if defined (SUPPORT_SID_INTERFACE)
1177 *phHandle = 0;
1178#else
1107 *phHandle = IMG_NULL; 1179 *phHandle = IMG_NULL;
1180#endif
1108 1181
1109 if (HANDLES_BATCHED(psBase)) 1182 if (HANDLES_BATCHED(psBase))
1110 { 1183 {
@@ -1113,13 +1186,17 @@ PVRSRV_ERROR PVRSRVAllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle,
1113 } 1186 }
1114 1187
1115 1188
1116 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE); 1189 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE)
1117 1190
1118 if (!TEST_FLAG(eFlag, PVRSRV_HANDLE_ALLOC_FLAG_MULTI)) 1191 if (!TEST_FLAG(eFlag, PVRSRV_HANDLE_ALLOC_FLAG_MULTI))
1119 { 1192 {
1120 1193
1121 hHandle = FindHandle(psBase, pvData, eType, IMG_NULL); 1194 hHandle = FindHandle(psBase, pvData, eType, IMG_NULL);
1195#if defined (SUPPORT_SID_INTERFACE)
1196 if (hHandle != 0)
1197#else
1122 if (hHandle != IMG_NULL) 1198 if (hHandle != IMG_NULL)
1199#endif
1123 { 1200 {
1124 struct sHandle *psHandle; 1201 struct sHandle *psHandle;
1125 1202
@@ -1137,12 +1214,16 @@ PVRSRV_ERROR PVRSRVAllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle,
1137 eError = PVRSRV_OK; 1214 eError = PVRSRV_OK;
1138 goto exit_ok; 1215 goto exit_ok;
1139 } 1216 }
1217
1218#if defined (SUPPORT_SID_INTERFACE)
1219 PVR_DBG_BREAK
1220#endif
1140 return PVRSRV_ERROR_HANDLE_NOT_SHAREABLE; 1221 return PVRSRV_ERROR_HANDLE_NOT_SHAREABLE;
1141 } 1222 }
1142 } 1223 }
1143 1224
1144 eError = AllocHandle(psBase, phHandle, pvData, eType, eFlag, IMG_NULL); 1225 eError = AllocHandle(psBase, phHandle, pvData, eType, eFlag, IMG_NULL);
1145 1226
1146exit_ok: 1227exit_ok:
1147 if (HANDLES_BATCHED(psBase) && (eError == PVRSRV_OK)) 1228 if (HANDLES_BATCHED(psBase) && (eError == PVRSRV_OK))
1148 { 1229 {
@@ -1152,15 +1233,26 @@ exit_ok:
1152 return eError; 1233 return eError;
1153} 1234}
1154 1235
1236#if defined (SUPPORT_SID_INTERFACE)
1237PVRSRV_ERROR PVRSRVAllocSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_SID *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, PVRSRV_HANDLE_ALLOC_FLAG eFlag, IMG_SID hParent)
1238#else
1155PVRSRV_ERROR PVRSRVAllocSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, PVRSRV_HANDLE_ALLOC_FLAG eFlag, IMG_HANDLE hParent) 1239PVRSRV_ERROR PVRSRVAllocSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, PVRSRV_HANDLE_ALLOC_FLAG eFlag, IMG_HANDLE hParent)
1240#endif
1156{ 1241{
1157 struct sHandle *psPHand; 1242 struct sHandle *psPHand;
1158 struct sHandle *psCHand; 1243 struct sHandle *psCHand;
1159 PVRSRV_ERROR eError; 1244 PVRSRV_ERROR eError;
1245#if defined (SUPPORT_SID_INTERFACE)
1246 IMG_SID hParentKey;
1247 IMG_SID hHandle;
1248
1249 *phHandle = 0;
1250#else
1160 IMG_HANDLE hParentKey; 1251 IMG_HANDLE hParentKey;
1161 IMG_HANDLE hHandle; 1252 IMG_HANDLE hHandle;
1162 1253
1163 *phHandle = IMG_NULL; 1254 *phHandle = IMG_NULL;
1255#endif
1164 1256
1165 if (HANDLES_BATCHED(psBase)) 1257 if (HANDLES_BATCHED(psBase))
1166 { 1258 {
@@ -1169,7 +1261,7 @@ PVRSRV_ERROR PVRSRVAllocSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHand
1169 } 1261 }
1170 1262
1171 1263
1172 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE); 1264 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE)
1173 1265
1174 hParentKey = TEST_FLAG(eFlag, PVRSRV_HANDLE_ALLOC_FLAG_PRIVATE) ? 1266 hParentKey = TEST_FLAG(eFlag, PVRSRV_HANDLE_ALLOC_FLAG_PRIVATE) ?
1175 hParent : IMG_NULL; 1267 hParent : IMG_NULL;
@@ -1185,7 +1277,11 @@ PVRSRV_ERROR PVRSRVAllocSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHand
1185 { 1277 {
1186 1278
1187 hHandle = FindHandle(psBase, pvData, eType, hParentKey); 1279 hHandle = FindHandle(psBase, pvData, eType, hParentKey);
1280#if defined (SUPPORT_SID_INTERFACE)
1281 if (hHandle != 0)
1282#else
1188 if (hHandle != IMG_NULL) 1283 if (hHandle != IMG_NULL)
1284#endif
1189 { 1285 {
1190 struct sHandle *psCHandle; 1286 struct sHandle *psCHandle;
1191 PVRSRV_ERROR eErr; 1287 PVRSRV_ERROR eErr;
@@ -1197,7 +1293,7 @@ PVRSRV_ERROR PVRSRVAllocSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHand
1197 return eErr; 1293 return eErr;
1198 } 1294 }
1199 1295
1200 PVR_ASSERT(hParentKey != IMG_NULL && ParentHandle(HANDLE_TO_HANDLE_STRUCT_PTR(psBase, hHandle)) == hParent); 1296 PVR_ASSERT(hParentKey != IMG_NULL && ParentHandle(HANDLE_TO_HANDLE_STRUCT_PTR(psBase, hHandle)) == hParent)
1201 1297
1202 1298
1203 if (TEST_FLAG(psCHandle->eFlag & eFlag, PVRSRV_HANDLE_ALLOC_FLAG_SHARED) && ParentHandle(HANDLE_TO_HANDLE_STRUCT_PTR(psBase, hHandle)) == hParent) 1299 if (TEST_FLAG(psCHandle->eFlag & eFlag, PVRSRV_HANDLE_ALLOC_FLAG_SHARED) && ParentHandle(HANDLE_TO_HANDLE_STRUCT_PTR(psBase, hHandle)) == hParent)
@@ -1205,6 +1301,9 @@ PVRSRV_ERROR PVRSRVAllocSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHand
1205 *phHandle = hHandle; 1301 *phHandle = hHandle;
1206 goto exit_ok; 1302 goto exit_ok;
1207 } 1303 }
1304#if defined (SUPPORT_SID_INTERFACE)
1305 PVR_DBG_BREAK
1306#endif
1208 return PVRSRV_ERROR_HANDLE_NOT_SHAREABLE; 1307 return PVRSRV_ERROR_HANDLE_NOT_SHAREABLE;
1209 } 1308 }
1210 } 1309 }
@@ -1233,14 +1332,26 @@ exit_ok:
1233 return PVRSRV_OK; 1332 return PVRSRV_OK;
1234} 1333}
1235 1334
1335#if defined (SUPPORT_SID_INTERFACE)
1336PVRSRV_ERROR PVRSRVFindHandle(PVRSRV_HANDLE_BASE *psBase, IMG_SID *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType)
1337#else
1236PVRSRV_ERROR PVRSRVFindHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType) 1338PVRSRV_ERROR PVRSRVFindHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType)
1339#endif
1237{ 1340{
1341#if defined (SUPPORT_SID_INTERFACE)
1342 IMG_SID hHandle;
1343#else
1238 IMG_HANDLE hHandle; 1344 IMG_HANDLE hHandle;
1345#endif
1239 1346
1240 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE); 1347 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE)
1241 1348
1242 1349
1350#if defined (SUPPORT_SID_INTERFACE)
1351 hHandle = (IMG_SID) FindHandle(psBase, pvData, eType, IMG_NULL);
1352#else
1243 hHandle = (IMG_HANDLE) FindHandle(psBase, pvData, eType, IMG_NULL); 1353 hHandle = (IMG_HANDLE) FindHandle(psBase, pvData, eType, IMG_NULL);
1354#endif
1244 if (hHandle == IMG_NULL) 1355 if (hHandle == IMG_NULL)
1245 { 1356 {
1246 return PVRSRV_ERROR_HANDLE_NOT_FOUND; 1357 return PVRSRV_ERROR_HANDLE_NOT_FOUND;
@@ -1251,7 +1362,11 @@ PVRSRV_ERROR PVRSRVFindHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle,
1251 return PVRSRV_OK; 1362 return PVRSRV_OK;
1252} 1363}
1253 1364
1365#if defined (SUPPORT_SID_INTERFACE)
1366PVRSRV_ERROR PVRSRVLookupHandleAnyType(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, PVRSRV_HANDLE_TYPE *peType, IMG_SID hHandle)
1367#else
1254PVRSRV_ERROR PVRSRVLookupHandleAnyType(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, PVRSRV_HANDLE_TYPE *peType, IMG_HANDLE hHandle) 1368PVRSRV_ERROR PVRSRVLookupHandleAnyType(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, PVRSRV_HANDLE_TYPE *peType, IMG_HANDLE hHandle)
1369#endif
1255{ 1370{
1256 struct sHandle *psHandle; 1371 struct sHandle *psHandle;
1257 PVRSRV_ERROR eError; 1372 PVRSRV_ERROR eError;
@@ -1260,6 +1375,9 @@ PVRSRV_ERROR PVRSRVLookupHandleAnyType(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *pp
1260 if (eError != PVRSRV_OK) 1375 if (eError != PVRSRV_OK)
1261 { 1376 {
1262 PVR_DPF((PVR_DBG_ERROR, "PVRSRVLookupHandleAnyType: Error looking up handle (%d)", eError)); 1377 PVR_DPF((PVR_DBG_ERROR, "PVRSRVLookupHandleAnyType: Error looking up handle (%d)", eError));
1378#if defined (SUPPORT_SID_INTERFACE)
1379 PVR_DBG_BREAK
1380#endif
1263 return eError; 1381 return eError;
1264 } 1382 }
1265 1383
@@ -1269,17 +1387,27 @@ PVRSRV_ERROR PVRSRVLookupHandleAnyType(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *pp
1269 return PVRSRV_OK; 1387 return PVRSRV_OK;
1270} 1388}
1271 1389
1390#if defined (SUPPORT_SID_INTERFACE)
1391PVRSRV_ERROR PVRSRVLookupHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, IMG_SID hHandle, PVRSRV_HANDLE_TYPE eType)
1392#else
1272PVRSRV_ERROR PVRSRVLookupHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType) 1393PVRSRV_ERROR PVRSRVLookupHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType)
1394#endif
1273{ 1395{
1274 struct sHandle *psHandle; 1396 struct sHandle *psHandle;
1275 PVRSRV_ERROR eError; 1397 PVRSRV_ERROR eError;
1276 1398
1277 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE); 1399 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE)
1400#if defined (SUPPORT_SID_INTERFACE)
1401 PVR_ASSERT(hHandle != 0)
1402#endif
1278 1403
1279 eError = GetHandleStructure(psBase, &psHandle, hHandle, eType); 1404 eError = GetHandleStructure(psBase, &psHandle, hHandle, eType);
1280 if (eError != PVRSRV_OK) 1405 if (eError != PVRSRV_OK)
1281 { 1406 {
1282 PVR_DPF((PVR_DBG_ERROR, "PVRSRVLookupHandle: Error looking up handle (%d)", eError)); 1407 PVR_DPF((PVR_DBG_ERROR, "PVRSRVLookupHandle: Error looking up handle (%d)", eError));
1408#if defined (SUPPORT_SID_INTERFACE)
1409 PVR_DBG_BREAK
1410#endif
1283 return eError; 1411 return eError;
1284 } 1412 }
1285 1413
@@ -1288,13 +1416,20 @@ PVRSRV_ERROR PVRSRVLookupHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData,
1288 return PVRSRV_OK; 1416 return PVRSRV_OK;
1289} 1417}
1290 1418
1419#if defined (SUPPORT_SID_INTERFACE)
1420PVRSRV_ERROR PVRSRVLookupSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, IMG_SID hHandle, PVRSRV_HANDLE_TYPE eType, IMG_SID hAncestor)
1421#else
1291PVRSRV_ERROR PVRSRVLookupSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType, IMG_HANDLE hAncestor) 1422PVRSRV_ERROR PVRSRVLookupSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType, IMG_HANDLE hAncestor)
1423#endif
1292{ 1424{
1293 struct sHandle *psPHand; 1425 struct sHandle *psPHand;
1294 struct sHandle *psCHand; 1426 struct sHandle *psCHand;
1295 PVRSRV_ERROR eError; 1427 PVRSRV_ERROR eError;
1296 1428
1297 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE); 1429 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE)
1430#if defined (SUPPORT_SID_INTERFACE)
1431 PVR_ASSERT(hHandle != 0)
1432#endif
1298 1433
1299 eError = GetHandleStructure(psBase, &psCHand, hHandle, eType); 1434 eError = GetHandleStructure(psBase, &psCHand, hHandle, eType);
1300 if (eError != PVRSRV_OK) 1435 if (eError != PVRSRV_OK)
@@ -1319,12 +1454,16 @@ PVRSRV_ERROR PVRSRVLookupSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvDat
1319 return PVRSRV_OK; 1454 return PVRSRV_OK;
1320} 1455}
1321 1456
1457#if defined (SUPPORT_SID_INTERFACE)
1458PVRSRV_ERROR PVRSRVGetParentHandle(PVRSRV_HANDLE_BASE *psBase, IMG_SID *phParent, IMG_SID hHandle, PVRSRV_HANDLE_TYPE eType)
1459#else
1322PVRSRV_ERROR PVRSRVGetParentHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *phParent, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType) 1460PVRSRV_ERROR PVRSRVGetParentHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *phParent, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType)
1461#endif
1323{ 1462{
1324 struct sHandle *psHandle; 1463 struct sHandle *psHandle;
1325 PVRSRV_ERROR eError; 1464 PVRSRV_ERROR eError;
1326 1465
1327 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE); 1466 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE)
1328 1467
1329 eError = GetHandleStructure(psBase, &psHandle, hHandle, eType); 1468 eError = GetHandleStructure(psBase, &psHandle, hHandle, eType);
1330 if (eError != PVRSRV_OK) 1469 if (eError != PVRSRV_OK)
@@ -1338,17 +1477,24 @@ PVRSRV_ERROR PVRSRVGetParentHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *phPare
1338 return PVRSRV_OK; 1477 return PVRSRV_OK;
1339} 1478}
1340 1479
1480#if defined (SUPPORT_SID_INTERFACE)
1481PVRSRV_ERROR PVRSRVLookupAndReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, IMG_SID hHandle, PVRSRV_HANDLE_TYPE eType)
1482#else
1341PVRSRV_ERROR PVRSRVLookupAndReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType) 1483PVRSRV_ERROR PVRSRVLookupAndReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType)
1484#endif
1342{ 1485{
1343 struct sHandle *psHandle; 1486 struct sHandle *psHandle;
1344 PVRSRV_ERROR eError; 1487 PVRSRV_ERROR eError;
1345 1488
1346 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE); 1489 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE)
1347 1490
1348 eError = GetHandleStructure(psBase, &psHandle, hHandle, eType); 1491 eError = GetHandleStructure(psBase, &psHandle, hHandle, eType);
1349 if (eError != PVRSRV_OK) 1492 if (eError != PVRSRV_OK)
1350 { 1493 {
1351 PVR_DPF((PVR_DBG_ERROR, "PVRSRVLookupAndReleaseHandle: Error looking up handle (%d)", eError)); 1494 PVR_DPF((PVR_DBG_ERROR, "PVRSRVLookupAndReleaseHandle: Error looking up handle (%d)", eError));
1495#if defined (SUPPORT_SID_INTERFACE)
1496 PVR_DBG_BREAK
1497#endif
1352 return eError; 1498 return eError;
1353 } 1499 }
1354 1500
@@ -1359,12 +1505,16 @@ PVRSRV_ERROR PVRSRVLookupAndReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID
1359 return eError; 1505 return eError;
1360} 1506}
1361 1507
1508#if defined (SUPPORT_SID_INTERFACE)
1509PVRSRV_ERROR PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_SID hHandle, PVRSRV_HANDLE_TYPE eType)
1510#else
1362PVRSRV_ERROR PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType) 1511PVRSRV_ERROR PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType)
1512#endif
1363{ 1513{
1364 struct sHandle *psHandle; 1514 struct sHandle *psHandle;
1365 PVRSRV_ERROR eError; 1515 PVRSRV_ERROR eError;
1366 1516
1367 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE); 1517 PVR_ASSERT(eType != PVRSRV_HANDLE_TYPE_NONE)
1368 1518
1369 eError = GetHandleStructure(psBase, &psHandle, hHandle, eType); 1519 eError = GetHandleStructure(psBase, &psHandle, hHandle, eType);
1370 if (eError != PVRSRV_OK) 1520 if (eError != PVRSRV_OK)
@@ -1406,11 +1556,11 @@ PVRSRV_ERROR PVRSRVNewHandleBatch(PVRSRV_HANDLE_BASE *psBase, IMG_UINT32 ui32Bat
1406 1556
1407 psBase->ui32TotalHandCountPreBatch = psBase->ui32TotalHandCount; 1557 psBase->ui32TotalHandCountPreBatch = psBase->ui32TotalHandCount;
1408 1558
1409 PVR_ASSERT(psBase->ui32BatchHandAllocFailures == 0); 1559 PVR_ASSERT(psBase->ui32BatchHandAllocFailures == 0)
1410 1560
1411 PVR_ASSERT(psBase->ui32FirstBatchIndexPlusOne == 0); 1561 PVR_ASSERT(psBase->ui32FirstBatchIndexPlusOne == 0)
1412 1562
1413 PVR_ASSERT(HANDLES_BATCHED(psBase)); 1563 PVR_ASSERT(HANDLES_BATCHED(psBase))
1414 1564
1415 return PVRSRV_OK; 1565 return PVRSRV_OK;
1416} 1566}
@@ -1437,14 +1587,14 @@ static PVRSRV_ERROR PVRSRVHandleBatchCommitOrRelease(PVRSRV_HANDLE_BASE *psBase,
1437 bCommitBatch = IMG_FALSE; 1587 bCommitBatch = IMG_FALSE;
1438 } 1588 }
1439 1589
1440 PVR_ASSERT(psBase->ui32BatchHandAllocFailures == 0 || !bCommit); 1590 PVR_ASSERT(psBase->ui32BatchHandAllocFailures == 0 || !bCommit)
1441 1591
1442 ui32IndexPlusOne = psBase->ui32FirstBatchIndexPlusOne; 1592 ui32IndexPlusOne = psBase->ui32FirstBatchIndexPlusOne;
1443 while(ui32IndexPlusOne != 0) 1593 while(ui32IndexPlusOne != 0)
1444 { 1594 {
1445 struct sHandle *psHandle = INDEX_TO_HANDLE_STRUCT_PTR(psBase, ui32IndexPlusOne - 1); 1595 struct sHandle *psHandle = INDEX_TO_HANDLE_STRUCT_PTR(psBase, ui32IndexPlusOne - 1);
1446 IMG_UINT32 ui32NextIndexPlusOne = psHandle->ui32NextIndexPlusOne; 1596 IMG_UINT32 ui32NextIndexPlusOne = psHandle->ui32NextIndexPlusOne;
1447 PVR_ASSERT(BATCHED_HANDLE(psHandle)); 1597 PVR_ASSERT(BATCHED_HANDLE(psHandle))
1448 1598
1449 psHandle->ui32NextIndexPlusOne = 0; 1599 psHandle->ui32NextIndexPlusOne = 0;
1450 1600
@@ -1464,7 +1614,7 @@ static PVRSRV_ERROR PVRSRVHandleBatchCommitOrRelease(PVRSRV_HANDLE_BASE *psBase,
1464 { 1614 {
1465 PVR_DPF((PVR_DBG_ERROR, "PVRSRVHandleBatchCommitOrRelease: Error freeing handle (%d)", eError)); 1615 PVR_DPF((PVR_DBG_ERROR, "PVRSRVHandleBatchCommitOrRelease: Error freeing handle (%d)", eError));
1466 } 1616 }
1467 PVR_ASSERT(eError == PVRSRV_OK); 1617 PVR_ASSERT(eError == PVRSRV_OK)
1468 } 1618 }
1469 else 1619 else
1470 { 1620 {
@@ -1480,7 +1630,7 @@ static PVRSRV_ERROR PVRSRVHandleBatchCommitOrRelease(PVRSRV_HANDLE_BASE *psBase,
1480 { 1630 {
1481 IMG_UINT32 ui32Delta = psBase->ui32TotalHandCount - psBase->ui32TotalHandCountPreBatch; 1631 IMG_UINT32 ui32Delta = psBase->ui32TotalHandCount - psBase->ui32TotalHandCountPreBatch;
1482 1632
1483 PVR_ASSERT(psBase->ui32TotalHandCount > psBase->ui32TotalHandCountPreBatch); 1633 PVR_ASSERT(psBase->ui32TotalHandCount > psBase->ui32TotalHandCountPreBatch)
1484 1634
1485 PVR_DPF((PVR_DBG_WARNING, "PVRSRVHandleBatchCommitOrRelease: The batch size was too small. Batch size was %u, but needs to be %u", psBase->ui32HandBatchSize, psBase->ui32HandBatchSize + ui32Delta)); 1635 PVR_DPF((PVR_DBG_WARNING, "PVRSRVHandleBatchCommitOrRelease: The batch size was too small. Batch size was %u, but needs to be %u", psBase->ui32HandBatchSize, psBase->ui32HandBatchSize + ui32Delta));
1486 1636
@@ -1494,7 +1644,7 @@ static PVRSRV_ERROR PVRSRVHandleBatchCommitOrRelease(PVRSRV_HANDLE_BASE *psBase,
1494 1644
1495 if (psBase->ui32BatchHandAllocFailures != 0 && bCommit) 1645 if (psBase->ui32BatchHandAllocFailures != 0 && bCommit)
1496 { 1646 {
1497 PVR_ASSERT(!bCommitBatch); 1647 PVR_ASSERT(!bCommitBatch)
1498 1648
1499 return PVRSRV_ERROR_HANDLE_BATCH_COMMIT_FAILURE; 1649 return PVRSRV_ERROR_HANDLE_BATCH_COMMIT_FAILURE;
1500 } 1650 }
@@ -1546,9 +1696,9 @@ PVRSRV_ERROR PVRSRVSetMaxHandle(PVRSRV_HANDLE_BASE *psBase, IMG_UINT32 ui32MaxHa
1546 psBase->ui32MaxIndexPlusOne = ui32MaxHandleRounded; 1696 psBase->ui32MaxIndexPlusOne = ui32MaxHandleRounded;
1547 } 1697 }
1548 1698
1549 PVR_ASSERT(psBase->ui32MaxIndexPlusOne != 0); 1699 PVR_ASSERT(psBase->ui32MaxIndexPlusOne != 0)
1550 PVR_ASSERT(psBase->ui32MaxIndexPlusOne <= DEFAULT_MAX_INDEX_PLUS_ONE); 1700 PVR_ASSERT(psBase->ui32MaxIndexPlusOne <= DEFAULT_MAX_INDEX_PLUS_ONE)
1551 PVR_ASSERT((psBase->ui32MaxIndexPlusOne % HANDLE_BLOCK_SIZE) == 0); 1701 PVR_ASSERT((psBase->ui32MaxIndexPlusOne % HANDLE_BLOCK_SIZE) == 0)
1552 1702
1553 return PVRSRV_OK; 1703 return PVRSRV_OK;
1554} 1704}
@@ -1595,7 +1745,7 @@ PVRSRV_ERROR PVRSRVPurgeHandles(PVRSRV_HANDLE_BASE *psBase)
1595 return PVRSRV_ERROR_INVALID_PARAMS; 1745 return PVRSRV_ERROR_INVALID_PARAMS;
1596 } 1746 }
1597 1747
1598 PVR_ASSERT((psBase->ui32TotalHandCount % HANDLE_BLOCK_SIZE) == 0); 1748 PVR_ASSERT((psBase->ui32TotalHandCount % HANDLE_BLOCK_SIZE) == 0)
1599 1749
1600 for (ui32BlockIndex = INDEX_TO_BLOCK_INDEX(psBase->ui32TotalHandCount); ui32BlockIndex != 0; ui32BlockIndex--) 1750 for (ui32BlockIndex = INDEX_TO_BLOCK_INDEX(psBase->ui32TotalHandCount); ui32BlockIndex != 0; ui32BlockIndex--)
1601 { 1751 {
@@ -1629,7 +1779,7 @@ PVRSRV_ERROR PVRSRVAllocHandleBase(PVRSRV_HANDLE_BASE **ppsBase)
1629 IMG_HANDLE hBlockAlloc; 1779 IMG_HANDLE hBlockAlloc;
1630 PVRSRV_ERROR eError; 1780 PVRSRV_ERROR eError;
1631 1781
1632 eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, 1782 eError = OSAllocMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
1633 sizeof(*psBase), 1783 sizeof(*psBase),
1634 (IMG_PVOID *)&psBase, 1784 (IMG_PVOID *)&psBase,
1635 &hBlockAlloc, 1785 &hBlockAlloc,
@@ -1663,7 +1813,7 @@ PVRSRV_ERROR PVRSRVFreeHandleBase(PVRSRV_HANDLE_BASE *psBase)
1663{ 1813{
1664 PVRSRV_ERROR eError; 1814 PVRSRV_ERROR eError;
1665 1815
1666 PVR_ASSERT(psBase != gpsKernelHandleBase); 1816 PVR_ASSERT(psBase != gpsKernelHandleBase)
1667 1817
1668 eError = FreeHandleBase(psBase); 1818 eError = FreeHandleBase(psBase);
1669 if (eError != PVRSRV_OK) 1819 if (eError != PVRSRV_OK)
@@ -1678,7 +1828,7 @@ PVRSRV_ERROR PVRSRVHandleInit(IMG_VOID)
1678{ 1828{
1679 PVRSRV_ERROR eError; 1829 PVRSRV_ERROR eError;
1680 1830
1681 PVR_ASSERT(gpsKernelHandleBase == IMG_NULL); 1831 PVR_ASSERT(gpsKernelHandleBase == IMG_NULL)
1682 1832
1683 eError = PVRSRVAllocHandleBase(&gpsKernelHandleBase); 1833 eError = PVRSRVAllocHandleBase(&gpsKernelHandleBase);
1684 if (eError != PVRSRV_OK) 1834 if (eError != PVRSRV_OK)
diff --git a/drivers/gpu/pvr/handle.h b/drivers/gpu/pvr/handle.h
index 56de04aede0..43f34a0cafd 100644
--- a/drivers/gpu/pvr/handle.h
+++ b/drivers/gpu/pvr/handle.h
@@ -59,7 +59,8 @@ typedef enum
59 PVRSRV_HANDLE_TYPE_EVENT_OBJECT_CONNECT, 59 PVRSRV_HANDLE_TYPE_EVENT_OBJECT_CONNECT,
60 PVRSRV_HANDLE_TYPE_MMAP_INFO, 60 PVRSRV_HANDLE_TYPE_MMAP_INFO,
61 PVRSRV_HANDLE_TYPE_SOC_TIMER, 61 PVRSRV_HANDLE_TYPE_SOC_TIMER,
62 PVRSRV_HANDLE_TYPE_SYNC_INFO_MOD_OBJ 62 PVRSRV_HANDLE_TYPE_SYNC_INFO_MOD_OBJ,
63 PVRSRV_HANDLE_TYPE_RESITEM_INFO
63} PVRSRV_HANDLE_TYPE; 64} PVRSRV_HANDLE_TYPE;
64 65
65typedef enum 66typedef enum
@@ -77,11 +78,30 @@ typedef enum
77struct _PVRSRV_HANDLE_BASE_; 78struct _PVRSRV_HANDLE_BASE_;
78typedef struct _PVRSRV_HANDLE_BASE_ PVRSRV_HANDLE_BASE; 79typedef struct _PVRSRV_HANDLE_BASE_ PVRSRV_HANDLE_BASE;
79 80
80#ifdef PVR_SECURE_HANDLES 81#if defined (PVR_SECURE_HANDLES) || defined (SUPPORT_SID_INTERFACE)
81extern PVRSRV_HANDLE_BASE *gpsKernelHandleBase; 82extern PVRSRV_HANDLE_BASE *gpsKernelHandleBase;
82 83
83#define KERNEL_HANDLE_BASE (gpsKernelHandleBase) 84#define KERNEL_HANDLE_BASE (gpsKernelHandleBase)
84 85
86#if defined (SUPPORT_SID_INTERFACE)
87PVRSRV_ERROR PVRSRVAllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_SID *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, PVRSRV_HANDLE_ALLOC_FLAG eFlag);
88
89PVRSRV_ERROR PVRSRVAllocSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_SID *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, PVRSRV_HANDLE_ALLOC_FLAG eFlag, IMG_SID hParent);
90
91PVRSRV_ERROR PVRSRVFindHandle(PVRSRV_HANDLE_BASE *psBase, IMG_SID *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType);
92
93PVRSRV_ERROR PVRSRVLookupHandleAnyType(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, PVRSRV_HANDLE_TYPE *peType, IMG_SID hHandle);
94
95PVRSRV_ERROR PVRSRVLookupHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, IMG_SID hHandle, PVRSRV_HANDLE_TYPE eType);
96
97PVRSRV_ERROR PVRSRVLookupSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, IMG_SID hHandle, PVRSRV_HANDLE_TYPE eType, IMG_SID hAncestor);
98
99PVRSRV_ERROR PVRSRVGetParentHandle(PVRSRV_HANDLE_BASE *psBase, IMG_SID *phParent, IMG_SID hHandle, PVRSRV_HANDLE_TYPE eType);
100
101PVRSRV_ERROR PVRSRVLookupAndReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, IMG_SID hHandle, PVRSRV_HANDLE_TYPE eType);
102
103PVRSRV_ERROR PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_SID hHandle, PVRSRV_HANDLE_TYPE eType);
104#else
85PVRSRV_ERROR PVRSRVAllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, PVRSRV_HANDLE_ALLOC_FLAG eFlag); 105PVRSRV_ERROR PVRSRVAllocHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, PVRSRV_HANDLE_ALLOC_FLAG eFlag);
86 106
87PVRSRV_ERROR PVRSRVAllocSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, PVRSRV_HANDLE_ALLOC_FLAG eFlag, IMG_HANDLE hParent); 107PVRSRV_ERROR PVRSRVAllocSubHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE *phHandle, IMG_VOID *pvData, PVRSRV_HANDLE_TYPE eType, PVRSRV_HANDLE_ALLOC_FLAG eFlag, IMG_HANDLE hParent);
@@ -99,6 +119,7 @@ PVRSRV_ERROR PVRSRVGetParentHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *phPare
99PVRSRV_ERROR PVRSRVLookupAndReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType); 119PVRSRV_ERROR PVRSRVLookupAndReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_PVOID *ppvData, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType);
100 120
101PVRSRV_ERROR PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType); 121PVRSRV_ERROR PVRSRVReleaseHandle(PVRSRV_HANDLE_BASE *psBase, IMG_HANDLE hHandle, PVRSRV_HANDLE_TYPE eType);
122#endif
102 123
103PVRSRV_ERROR PVRSRVNewHandleBatch(PVRSRV_HANDLE_BASE *psBase, IMG_UINT32 ui32BatchSize); 124PVRSRV_ERROR PVRSRVNewHandleBatch(PVRSRV_HANDLE_BASE *psBase, IMG_UINT32 ui32BatchSize);
104 125
diff --git a/drivers/gpu/pvr/hash.c b/drivers/gpu/pvr/hash.c
index 32b0779d456..488bf1b20e6 100644
--- a/drivers/gpu/pvr/hash.c
+++ b/drivers/gpu/pvr/hash.c
@@ -80,7 +80,7 @@ IMG_UINT32
80HASH_Func_Default (IMG_SIZE_T uKeySize, IMG_VOID *pKey, IMG_UINT32 uHashTabLen) 80HASH_Func_Default (IMG_SIZE_T uKeySize, IMG_VOID *pKey, IMG_UINT32 uHashTabLen)
81{ 81{
82 IMG_UINTPTR_T *p = (IMG_UINTPTR_T *)pKey; 82 IMG_UINTPTR_T *p = (IMG_UINTPTR_T *)pKey;
83 IMG_UINT32 uKeyLen = uKeySize / sizeof(IMG_UINTPTR_T); 83 IMG_UINT32 uKeyLen = (IMG_UINT32)(uKeySize / sizeof(IMG_UINTPTR_T));
84 IMG_UINT32 ui; 84 IMG_UINT32 ui;
85 IMG_UINT32 uHashKey = 0; 85 IMG_UINT32 uHashKey = 0;
86 86
@@ -112,7 +112,7 @@ HASH_Key_Comp_Default (IMG_SIZE_T uKeySize, IMG_VOID *pKey1, IMG_VOID *pKey2)
112{ 112{
113 IMG_UINTPTR_T *p1 = (IMG_UINTPTR_T *)pKey1; 113 IMG_UINTPTR_T *p1 = (IMG_UINTPTR_T *)pKey1;
114 IMG_UINTPTR_T *p2 = (IMG_UINTPTR_T *)pKey2; 114 IMG_UINTPTR_T *p2 = (IMG_UINTPTR_T *)pKey2;
115 IMG_UINT32 uKeyLen = uKeySize / sizeof(IMG_UINTPTR_T); 115 IMG_UINT32 uKeyLen = (IMG_UINT32)(uKeySize / sizeof(IMG_UINTPTR_T));
116 IMG_UINT32 ui; 116 IMG_UINT32 ui;
117 117
118 PVR_ASSERT((uKeySize % sizeof(IMG_UINTPTR_T)) == 0); 118 PVR_ASSERT((uKeySize % sizeof(IMG_UINTPTR_T)) == 0);
@@ -228,7 +228,7 @@ HASH_TABLE * HASH_Create_Extended (IMG_UINT32 uInitialLen, IMG_SIZE_T uKeySize,
228 pHash->uCount = 0; 228 pHash->uCount = 0;
229 pHash->uSize = uInitialLen; 229 pHash->uSize = uInitialLen;
230 pHash->uMinimumSize = uInitialLen; 230 pHash->uMinimumSize = uInitialLen;
231 pHash->uKeySize = uKeySize; 231 pHash->uKeySize = (IMG_UINT32)uKeySize;
232 pHash->pfnHashFunc = pfnHashFunc; 232 pHash->pfnHashFunc = pfnHashFunc;
233 pHash->pfnKeyComp = pfnKeyComp; 233 pHash->pfnKeyComp = pfnKeyComp;
234 234
@@ -305,6 +305,9 @@ HASH_Insert_Extended (HASH_TABLE *pHash, IMG_VOID *pKey, IMG_UINTPTR_T v)
305 OSMemCopy(pBucket->k, pKey, pHash->uKeySize); 305 OSMemCopy(pBucket->k, pKey, pHash->uKeySize);
306 if (_ChainInsert (pHash, pBucket, pHash->ppBucketTable, pHash->uSize) != PVRSRV_OK) 306 if (_ChainInsert (pHash, pBucket, pHash->ppBucketTable, pHash->uSize) != PVRSRV_OK)
307 { 307 {
308 OSFreeMem(PVRSRV_PAGEABLE_SELECT,
309 sizeof(BUCKET) + pHash->uKeySize,
310 pBucket, IMG_NULL);
308 return IMG_FALSE; 311 return IMG_FALSE;
309 } 312 }
310 313
@@ -444,6 +447,31 @@ HASH_Retrieve (HASH_TABLE *pHash, IMG_UINTPTR_T k)
444 return HASH_Retrieve_Extended(pHash, &k); 447 return HASH_Retrieve_Extended(pHash, &k);
445} 448}
446 449
450PVRSRV_ERROR
451HASH_Iterate(HASH_TABLE *pHash, HASH_pfnCallback pfnCallback)
452{
453 IMG_UINT32 uIndex;
454 for (uIndex=0; uIndex < pHash->uSize; uIndex++)
455 {
456 BUCKET *pBucket;
457 pBucket = pHash->ppBucketTable[uIndex];
458 while (pBucket != IMG_NULL)
459 {
460 PVRSRV_ERROR eError;
461 BUCKET *pNextBucket = pBucket->pNext;
462
463 eError = pfnCallback((IMG_UINTPTR_T) ((IMG_VOID *) *(pBucket->k)), (IMG_UINTPTR_T) pBucket->v);
464
465
466 if (eError != PVRSRV_OK)
467 return eError;
468
469 pBucket = pNextBucket;
470 }
471 }
472 return PVRSRV_OK;
473}
474
447#ifdef HASH_TRACE 475#ifdef HASH_TRACE
448IMG_VOID 476IMG_VOID
449HASH_Dump (HASH_TABLE *pHash) 477HASH_Dump (HASH_TABLE *pHash)
diff --git a/drivers/gpu/pvr/hash.h b/drivers/gpu/pvr/hash.h
index d45f4a98dda..24b7da07b91 100644
--- a/drivers/gpu/pvr/hash.h
+++ b/drivers/gpu/pvr/hash.h
@@ -39,6 +39,11 @@ typedef IMG_BOOL HASH_KEY_COMP(IMG_SIZE_T uKeySize, IMG_VOID *pKey1, IMG_VOID *p
39 39
40typedef struct _HASH_TABLE_ HASH_TABLE; 40typedef struct _HASH_TABLE_ HASH_TABLE;
41 41
42typedef PVRSRV_ERROR (*HASH_pfnCallback) (
43 IMG_UINTPTR_T k,
44 IMG_UINTPTR_T v
45);
46
42IMG_UINT32 HASH_Func_Default (IMG_SIZE_T uKeySize, IMG_VOID *pKey, IMG_UINT32 uHashTabLen); 47IMG_UINT32 HASH_Func_Default (IMG_SIZE_T uKeySize, IMG_VOID *pKey, IMG_UINT32 uHashTabLen);
43 48
44IMG_BOOL HASH_Key_Comp_Default (IMG_SIZE_T uKeySize, IMG_VOID *pKey1, IMG_VOID *pKey2); 49IMG_BOOL HASH_Key_Comp_Default (IMG_SIZE_T uKeySize, IMG_VOID *pKey1, IMG_VOID *pKey2);
@@ -61,6 +66,8 @@ IMG_UINTPTR_T HASH_Retrieve_Extended (HASH_TABLE *pHash, IMG_VOID *pKey);
61 66
62IMG_UINTPTR_T HASH_Retrieve (HASH_TABLE *pHash, IMG_UINTPTR_T k); 67IMG_UINTPTR_T HASH_Retrieve (HASH_TABLE *pHash, IMG_UINTPTR_T k);
63 68
69PVRSRV_ERROR HASH_Iterate(HASH_TABLE *pHash, HASH_pfnCallback pfnCallback);
70
64#ifdef HASH_TRACE 71#ifdef HASH_TRACE
65IMG_VOID HASH_Dump (HASH_TABLE *pHash); 72IMG_VOID HASH_Dump (HASH_TABLE *pHash);
66#endif 73#endif
diff --git a/drivers/gpu/pvr/img_types.h b/drivers/gpu/pvr/img_types.h
index 31962aaedbb..4401f4dd92c 100644
--- a/drivers/gpu/pvr/img_types.h
+++ b/drivers/gpu/pvr/img_types.h
@@ -56,16 +56,19 @@ typedef signed long IMG_INT32, *IMG_PINT32;
56 #define IMG_UINT32_MAX 0xFFFFFFFFUL 56 #define IMG_UINT32_MAX 0xFFFFFFFFUL
57#endif 57#endif
58 58
59#if defined(USE_CODE)
60
61typedef unsigned __int64 IMG_UINT64, *IMG_PUINT64;
62typedef __int64 IMG_INT64, *IMG_PINT64;
63
64#else
59 #if (defined(LINUX) || defined(__METAG)) 65 #if (defined(LINUX) || defined(__METAG))
60#if !defined(USE_CODE)
61 typedef unsigned long long IMG_UINT64, *IMG_PUINT64; 66 typedef unsigned long long IMG_UINT64, *IMG_PUINT64;
62 typedef long long IMG_INT64, *IMG_PINT64; 67 typedef long long IMG_INT64, *IMG_PINT64;
63#endif
64 #else 68 #else
65
66 #error("define an OS") 69 #error("define an OS")
67
68 #endif 70 #endif
71#endif
69 72
70#if !(defined(LINUX) && defined (__KERNEL__)) 73#if !(defined(LINUX) && defined (__KERNEL__))
71typedef float IMG_FLOAT, *IMG_PFLOAT; 74typedef float IMG_FLOAT, *IMG_PFLOAT;
@@ -84,22 +87,23 @@ typedef void IMG_VOID, *IMG_PVOID;
84typedef IMG_INT32 IMG_RESULT; 87typedef IMG_INT32 IMG_RESULT;
85 88
86#if defined(_WIN64) 89#if defined(_WIN64)
87typedef unsigned __int64 IMG_UINTPTR_T; 90 typedef unsigned __int64 IMG_UINTPTR_T;
91 typedef signed __int64 IMG_PTRDIFF_T;
92 typedef IMG_UINT64 IMG_SIZE_T;
88#else 93#else
89typedef unsigned int IMG_UINTPTR_T; 94 typedef unsigned int IMG_UINTPTR_T;
95 typedef IMG_UINT32 IMG_SIZE_T;
90#endif 96#endif
91 97
92typedef IMG_PVOID IMG_HANDLE; 98typedef IMG_PVOID IMG_HANDLE;
93 99
94typedef void** IMG_HVOID, * IMG_PHVOID; 100typedef void** IMG_HVOID, * IMG_PHVOID;
95 101
96typedef IMG_UINT32 IMG_SIZE_T;
97
98#define IMG_NULL 0 102#define IMG_NULL 0
99 103
100typedef IMG_UINT32 IMG_SID; 104typedef IMG_UINT32 IMG_SID;
101 105
102 106typedef IMG_UINT32 IMG_EVENTSID;
103typedef IMG_PVOID IMG_CPU_VIRTADDR; 107typedef IMG_PVOID IMG_CPU_VIRTADDR;
104 108
105typedef struct _IMG_DEV_VIRTADDR 109typedef struct _IMG_DEV_VIRTADDR
@@ -110,6 +114,8 @@ typedef struct _IMG_DEV_VIRTADDR
110 114
111} IMG_DEV_VIRTADDR; 115} IMG_DEV_VIRTADDR;
112 116
117typedef IMG_UINT32 IMG_DEVMEM_SIZE_T;
118
113typedef struct _IMG_CPU_PHYADDR 119typedef struct _IMG_CPU_PHYADDR
114{ 120{
115 121
diff --git a/drivers/gpu/pvr/ioctldef.h b/drivers/gpu/pvr/ioctldef.h
deleted file mode 100644
index 4b23ad437a7..00000000000
--- a/drivers/gpu/pvr/ioctldef.h
+++ /dev/null
@@ -1,98 +0,0 @@
1/**********************************************************************
2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 *
25 ******************************************************************************/
26
27#ifndef __IOCTLDEF_H__
28#define __IOCTLDEF_H__
29
30#define MAKEIOCTLINDEX(i) (((i) >> 2) & 0xFFF)
31
32#ifndef CTL_CODE
33
34#define DEVICE_TYPE ULONG
35
36#define FILE_DEVICE_BEEP 0x00000001
37#define FILE_DEVICE_CD_ROM 0x00000002
38#define FILE_DEVICE_CD_ROM_FILE_SYSTEM 0x00000003
39#define FILE_DEVICE_CONTROLLER 0x00000004
40#define FILE_DEVICE_DATALINK 0x00000005
41#define FILE_DEVICE_DFS 0x00000006
42#define FILE_DEVICE_DISK 0x00000007
43#define FILE_DEVICE_DISK_FILE_SYSTEM 0x00000008
44#define FILE_DEVICE_FILE_SYSTEM 0x00000009
45#define FILE_DEVICE_INPORT_PORT 0x0000000a
46#define FILE_DEVICE_KEYBOARD 0x0000000b
47#define FILE_DEVICE_MAILSLOT 0x0000000c
48#define FILE_DEVICE_MIDI_IN 0x0000000d
49#define FILE_DEVICE_MIDI_OUT 0x0000000e
50#define FILE_DEVICE_MOUSE 0x0000000f
51#define FILE_DEVICE_MULTI_UNC_PROVIDER 0x00000010
52#define FILE_DEVICE_NAMED_PIPE 0x00000011
53#define FILE_DEVICE_NETWORK 0x00000012
54#define FILE_DEVICE_NETWORK_BROWSER 0x00000013
55#define FILE_DEVICE_NETWORK_FILE_SYSTEM 0x00000014
56#define FILE_DEVICE_NULL 0x00000015
57#define FILE_DEVICE_PARALLEL_PORT 0x00000016
58#define FILE_DEVICE_PHYSICAL_NETCARD 0x00000017
59#define FILE_DEVICE_PRINTER 0x00000018
60#define FILE_DEVICE_SCANNER 0x00000019
61#define FILE_DEVICE_SERIAL_MOUSE_PORT 0x0000001a
62#define FILE_DEVICE_SERIAL_PORT 0x0000001b
63#define FILE_DEVICE_SCREEN 0x0000001c
64#define FILE_DEVICE_SOUND 0x0000001d
65#define FILE_DEVICE_STREAMS 0x0000001e
66#define FILE_DEVICE_TAPE 0x0000001f
67#define FILE_DEVICE_TAPE_FILE_SYSTEM 0x00000020
68#define FILE_DEVICE_TRANSPORT 0x00000021
69#define FILE_DEVICE_UNKNOWN 0x00000022
70#define FILE_DEVICE_VIDEO 0x00000023
71#define FILE_DEVICE_VIRTUAL_DISK 0x00000024
72#define FILE_DEVICE_WAVE_IN 0x00000025
73#define FILE_DEVICE_WAVE_OUT 0x00000026
74#define FILE_DEVICE_8042_PORT 0x00000027
75#define FILE_DEVICE_NETWORK_REDIRECTOR 0x00000028
76#define FILE_DEVICE_BATTERY 0x00000029
77#define FILE_DEVICE_BUS_EXTENDER 0x0000002a
78#define FILE_DEVICE_MODEM 0x0000002b
79#define FILE_DEVICE_VDM 0x0000002c
80#define FILE_DEVICE_MASS_STORAGE 0x0000002d
81
82#define CTL_CODE( DeviceType, Function, Method, Access ) ( \
83 ((DeviceType) << 16) | ((Access) << 14) | ((Function) << 2) | (Method) \
84)
85
86#define METHOD_BUFFERED 0
87#define METHOD_IN_DIRECT 1
88#define METHOD_OUT_DIRECT 2
89#define METHOD_NEITHER 3
90
91#define FILE_ANY_ACCESS 0
92#define FILE_READ_ACCESS ( 0x0001 )
93#define FILE_WRITE_ACCESS ( 0x0002 )
94
95#endif
96
97#endif
98
diff --git a/drivers/gpu/pvr/mem.c b/drivers/gpu/pvr/mem.c
index a2673d53c23..8bf28bfe122 100644
--- a/drivers/gpu/pvr/mem.c
+++ b/drivers/gpu/pvr/mem.c
@@ -37,7 +37,7 @@ FreeSharedSysMemCallBack(IMG_PVOID pvParam,
37 PVR_UNREFERENCED_PARAMETER(ui32Param); 37 PVR_UNREFERENCED_PARAMETER(ui32Param);
38 38
39 OSFreePages(psKernelMemInfo->ui32Flags, 39 OSFreePages(psKernelMemInfo->ui32Flags,
40 psKernelMemInfo->ui32AllocSize, 40 psKernelMemInfo->uAllocSize,
41 psKernelMemInfo->pvLinAddrKM, 41 psKernelMemInfo->pvLinAddrKM,
42 psKernelMemInfo->sMemBlk.hOSMemHandle); 42 psKernelMemInfo->sMemBlk.hOSMemHandle);
43 43
@@ -54,7 +54,7 @@ FreeSharedSysMemCallBack(IMG_PVOID pvParam,
54IMG_EXPORT PVRSRV_ERROR 54IMG_EXPORT PVRSRV_ERROR
55PVRSRVAllocSharedSysMemoryKM(PVRSRV_PER_PROCESS_DATA *psPerProc, 55PVRSRVAllocSharedSysMemoryKM(PVRSRV_PER_PROCESS_DATA *psPerProc,
56 IMG_UINT32 ui32Flags, 56 IMG_UINT32 ui32Flags,
57 IMG_SIZE_T ui32Size, 57 IMG_SIZE_T uSize,
58 PVRSRV_KERNEL_MEM_INFO **ppsKernelMemInfo) 58 PVRSRV_KERNEL_MEM_INFO **ppsKernelMemInfo)
59{ 59{
60 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 60 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
@@ -73,11 +73,11 @@ PVRSRVAllocSharedSysMemoryKM(PVRSRV_PER_PROCESS_DATA *psPerProc,
73 ui32Flags &= ~PVRSRV_HAP_MAPTYPE_MASK; 73 ui32Flags &= ~PVRSRV_HAP_MAPTYPE_MASK;
74 ui32Flags |= PVRSRV_HAP_MULTI_PROCESS; 74 ui32Flags |= PVRSRV_HAP_MULTI_PROCESS;
75 psKernelMemInfo->ui32Flags = ui32Flags; 75 psKernelMemInfo->ui32Flags = ui32Flags;
76 psKernelMemInfo->ui32AllocSize = ui32Size; 76 psKernelMemInfo->uAllocSize = uSize;
77 77
78 if(OSAllocPages(psKernelMemInfo->ui32Flags, 78 if(OSAllocPages(psKernelMemInfo->ui32Flags,
79 psKernelMemInfo->ui32AllocSize, 79 psKernelMemInfo->uAllocSize,
80 HOST_PAGESIZE(), 80 (IMG_UINT32)HOST_PAGESIZE(),
81 &psKernelMemInfo->pvLinAddrKM, 81 &psKernelMemInfo->pvLinAddrKM,
82 &psKernelMemInfo->sMemBlk.hOSMemHandle) 82 &psKernelMemInfo->sMemBlk.hOSMemHandle)
83 != PVRSRV_OK) 83 != PVRSRV_OK)
diff --git a/drivers/gpu/pvr/mm.c b/drivers/gpu/pvr/mm.c
index ecaba8e1015..39efdb0c846 100644
--- a/drivers/gpu/pvr/mm.c
+++ b/drivers/gpu/pvr/mm.c
@@ -335,10 +335,10 @@ LinuxMMCleanup(IMG_VOID)
335 335
336 336
337IMG_VOID * 337IMG_VOID *
338_KMallocWrapper(IMG_UINT32 ui32ByteSize, IMG_CHAR *pszFileName, IMG_UINT32 ui32Line) 338_KMallocWrapper(IMG_UINT32 ui32ByteSize, gfp_t uFlags, IMG_CHAR *pszFileName, IMG_UINT32 ui32Line)
339{ 339{
340 IMG_VOID *pvRet; 340 IMG_VOID *pvRet;
341 pvRet = kmalloc(ui32ByteSize, GFP_KERNEL); 341 pvRet = kmalloc(ui32ByteSize, uFlags);
342#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS) 342#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS)
343 if(pvRet) 343 if(pvRet)
344 { 344 {
@@ -395,7 +395,7 @@ DebugMemAllocRecordAdd(DEBUG_MEM_ALLOC_TYPE eAllocType,
395 psRecord->pvCpuVAddr = pvCpuVAddr; 395 psRecord->pvCpuVAddr = pvCpuVAddr;
396 psRecord->ulCpuPAddr = ulCpuPAddr; 396 psRecord->ulCpuPAddr = ulCpuPAddr;
397 psRecord->pvPrivateData = pvPrivateData; 397 psRecord->pvPrivateData = pvPrivateData;
398 psRecord->pid = current->pid; 398 psRecord->pid = OSGetCurrentProcessIDKM();
399 psRecord->ui32Bytes = ui32Bytes; 399 psRecord->ui32Bytes = ui32Bytes;
400 psRecord->pszFileName = pszFileName; 400 psRecord->pszFileName = pszFileName;
401 psRecord->ui32Line = ui32Line; 401 psRecord->ui32Line = ui32Line;
@@ -1318,7 +1318,7 @@ DebugLinuxMemAreaRecordAdd(LinuxMemArea *psLinuxMemArea, IMG_UINT32 ui32Flags)
1318 1318
1319 psNewRecord->psLinuxMemArea = psLinuxMemArea; 1319 psNewRecord->psLinuxMemArea = psLinuxMemArea;
1320 psNewRecord->ui32Flags = ui32Flags; 1320 psNewRecord->ui32Flags = ui32Flags;
1321 psNewRecord->pid = current->pid; 1321 psNewRecord->pid = OSGetCurrentProcessIDKM();
1322 1322
1323 List_DEBUG_LINUX_MEM_AREA_REC_Insert(&g_LinuxMemAreaRecords, psNewRecord); 1323 List_DEBUG_LINUX_MEM_AREA_REC_Insert(&g_LinuxMemAreaRecords, psNewRecord);
1324 } 1324 }
diff --git a/drivers/gpu/pvr/mm.h b/drivers/gpu/pvr/mm.h
index 047b3ad540c..62aa079dcc6 100644
--- a/drivers/gpu/pvr/mm.h
+++ b/drivers/gpu/pvr/mm.h
@@ -160,11 +160,11 @@ IMG_VOID LinuxMMCleanup(IMG_VOID);
160 160
161 161
162#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS) 162#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS)
163#define KMallocWrapper(ui32ByteSize) _KMallocWrapper(ui32ByteSize, __FILE__, __LINE__) 163#define KMallocWrapper(ui32ByteSize, uFlags) _KMallocWrapper(ui32ByteSize, uFlags, __FILE__, __LINE__)
164#else 164#else
165#define KMallocWrapper(ui32ByteSize) _KMallocWrapper(ui32ByteSize, NULL, 0) 165#define KMallocWrapper(ui32ByteSize, uFlags) _KMallocWrapper(ui32ByteSize, uFlags, NULL, 0)
166#endif 166#endif
167IMG_VOID *_KMallocWrapper(IMG_UINT32 ui32ByteSize, IMG_CHAR *szFileName, IMG_UINT32 ui32Line); 167IMG_VOID *_KMallocWrapper(IMG_UINT32 ui32ByteSize, gfp_t uFlags, IMG_CHAR *szFileName, IMG_UINT32 ui32Line);
168 168
169 169
170#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS) 170#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS)
diff --git a/drivers/gpu/pvr/mmap.c b/drivers/gpu/pvr/mmap.c
index 66cef26e522..c9a30f1c8d4 100644
--- a/drivers/gpu/pvr/mmap.c
+++ b/drivers/gpu/pvr/mmap.c
@@ -67,7 +67,7 @@
67#include "pvr_drm.h" 67#include "pvr_drm.h"
68#endif 68#endif
69 69
70#if !defined(PVR_SECURE_HANDLES) 70#if !defined(PVR_SECURE_HANDLES) && !defined (SUPPORT_SID_INTERFACE)
71#error "The mmap code requires PVR_SECURE_HANDLES" 71#error "The mmap code requires PVR_SECURE_HANDLES"
72#endif 72#endif
73 73
@@ -146,7 +146,11 @@ MMapOffsetToHandle(IMG_UINT32 pfn)
146#endif 146#endif
147 147
148static inline IMG_UINT32 148static inline IMG_UINT32
149#if defined (SUPPORT_SID_INTERFACE)
150HandleToMMapOffset(IMG_SID hHandle)
151#else
149HandleToMMapOffset(IMG_HANDLE hHandle) 152HandleToMMapOffset(IMG_HANDLE hHandle)
153#endif
150{ 154{
151 IMG_UINT32 ulHandle = (IMG_UINT32)hHandle; 155 IMG_UINT32 ulHandle = (IMG_UINT32)hHandle;
152 156
@@ -270,11 +274,15 @@ DetermineUsersSizeAndByteOffset(LinuxMemArea *psLinuxMemArea,
270 274
271PVRSRV_ERROR 275PVRSRV_ERROR
272PVRMMapOSMemHandleToMMapData(PVRSRV_PER_PROCESS_DATA *psPerProc, 276PVRMMapOSMemHandleToMMapData(PVRSRV_PER_PROCESS_DATA *psPerProc,
273 IMG_HANDLE hMHandle, 277#if defined (SUPPORT_SID_INTERFACE)
274 IMG_UINT32 *pui32MMapOffset, 278 IMG_SID hMHandle,
275 IMG_UINT32 *pui32ByteOffset, 279#else
276 IMG_UINT32 *pui32RealByteSize, 280 IMG_HANDLE hMHandle,
277 IMG_UINT32 *pui32UserVAddr) 281#endif
282 IMG_UINT32 *pui32MMapOffset,
283 IMG_UINT32 *pui32ByteOffset,
284 IMG_UINT32 *pui32RealByteSize,
285 IMG_UINT32 *pui32UserVAddr)
278{ 286{
279 LinuxMemArea *psLinuxMemArea; 287 LinuxMemArea *psLinuxMemArea;
280 PKV_OFFSET_STRUCT psOffsetStruct; 288 PKV_OFFSET_STRUCT psOffsetStruct;
@@ -288,9 +296,13 @@ PVRMMapOSMemHandleToMMapData(PVRSRV_PER_PROCESS_DATA *psPerProc,
288 eError = PVRSRVLookupOSMemHandle(psPerProc->psHandleBase, &hOSMemHandle, hMHandle); 296 eError = PVRSRVLookupOSMemHandle(psPerProc->psHandleBase, &hOSMemHandle, hMHandle);
289 if (eError != PVRSRV_OK) 297 if (eError != PVRSRV_OK)
290 { 298 {
291 PVR_DPF((PVR_DBG_ERROR, "%s: Lookup of handle %p failed", __FUNCTION__, hMHandle)); 299#if defined (SUPPORT_SID_INTERFACE)
300 PVR_DPF((PVR_DBG_ERROR, "%s: Lookup of handle %x failed", __FUNCTION__, hMHandle));
301#else
302 PVR_DPF((PVR_DBG_ERROR, "%s: Lookup of handle %p failed", __FUNCTION__, hMHandle));
303#endif
292 304
293 goto exit_unlock; 305 goto exit_unlock;
294 } 306 }
295 307
296 psLinuxMemArea = (LinuxMemArea *)hOSMemHandle; 308 psLinuxMemArea = (LinuxMemArea *)hOSMemHandle;
@@ -364,7 +376,11 @@ exit_unlock:
364 376
365PVRSRV_ERROR 377PVRSRV_ERROR
366PVRMMapReleaseMMapData(PVRSRV_PER_PROCESS_DATA *psPerProc, 378PVRMMapReleaseMMapData(PVRSRV_PER_PROCESS_DATA *psPerProc,
379#if defined (SUPPORT_SID_INTERFACE)
380 IMG_SID hMHandle,
381#else
367 IMG_HANDLE hMHandle, 382 IMG_HANDLE hMHandle,
383#endif
368 IMG_BOOL *pbMUnmap, 384 IMG_BOOL *pbMUnmap,
369 IMG_UINT32 *pui32RealByteSize, 385 IMG_UINT32 *pui32RealByteSize,
370 IMG_UINT32 *pui32UserVAddr) 386 IMG_UINT32 *pui32UserVAddr)
@@ -382,7 +398,11 @@ PVRMMapReleaseMMapData(PVRSRV_PER_PROCESS_DATA *psPerProc,
382 eError = PVRSRVLookupOSMemHandle(psPerProc->psHandleBase, &hOSMemHandle, hMHandle); 398 eError = PVRSRVLookupOSMemHandle(psPerProc->psHandleBase, &hOSMemHandle, hMHandle);
383 if (eError != PVRSRV_OK) 399 if (eError != PVRSRV_OK)
384 { 400 {
401#if defined (SUPPORT_SID_INTERFACE)
402 PVR_DPF((PVR_DBG_ERROR, "%s: Lookup of handle %x failed", __FUNCTION__, hMHandle));
403#else
385 PVR_DPF((PVR_DBG_ERROR, "%s: Lookup of handle %p failed", __FUNCTION__, hMHandle)); 404 PVR_DPF((PVR_DBG_ERROR, "%s: Lookup of handle %p failed", __FUNCTION__, hMHandle));
405#endif
386 406
387 goto exit_unlock; 407 goto exit_unlock;
388 } 408 }
@@ -414,7 +434,11 @@ PVRMMapReleaseMMapData(PVRSRV_PER_PROCESS_DATA *psPerProc,
414 } 434 }
415 435
416 436
437#if defined (SUPPORT_SID_INTERFACE)
438 PVR_DPF((PVR_DBG_ERROR, "%s: Mapping data not found for handle %x (memory area %p)", __FUNCTION__, hMHandle, psLinuxMemArea));
439#else
417 PVR_DPF((PVR_DBG_ERROR, "%s: Mapping data not found for handle %p (memory area %p)", __FUNCTION__, hMHandle, psLinuxMemArea)); 440 PVR_DPF((PVR_DBG_ERROR, "%s: Mapping data not found for handle %p (memory area %p)", __FUNCTION__, hMHandle, psLinuxMemArea));
441#endif
418 442
419 eError = PVRSRV_ERROR_MAPPING_NOT_FOUND; 443 eError = PVRSRV_ERROR_MAPPING_NOT_FOUND;
420 444
@@ -590,10 +614,6 @@ MMapVOpenNoLock(struct vm_area_struct* ps_vma)
590 psOffsetStruct->ui32MMapOffset, 614 psOffsetStruct->ui32MMapOffset,
591 psOffsetStruct->ui32Mapped)); 615 psOffsetStruct->ui32Mapped));
592#endif 616#endif
593
594#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
595 MOD_INC_USE_COUNT;
596#endif
597} 617}
598 618
599 619
@@ -637,10 +657,6 @@ MMapVCloseNoLock(struct vm_area_struct* ps_vma)
637 } 657 }
638 658
639 ps_vma->vm_private_data = NULL; 659 ps_vma->vm_private_data = NULL;
640
641#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
642 MOD_DEC_USE_COUNT;
643#endif
644} 660}
645 661
646static void 662static void
diff --git a/drivers/gpu/pvr/mmap.h b/drivers/gpu/pvr/mmap.h
index 486154a241f..9330da15170 100644
--- a/drivers/gpu/pvr/mmap.h
+++ b/drivers/gpu/pvr/mmap.h
@@ -94,14 +94,23 @@ PVRSRV_ERROR PVRMMapRemoveRegisteredArea(LinuxMemArea *psLinuxMemArea);
94 94
95 95
96PVRSRV_ERROR PVRMMapOSMemHandleToMMapData(PVRSRV_PER_PROCESS_DATA *psPerProc, 96PVRSRV_ERROR PVRMMapOSMemHandleToMMapData(PVRSRV_PER_PROCESS_DATA *psPerProc,
97 IMG_HANDLE hMHandle, 97#if defined (SUPPORT_SID_INTERFACE)
98 IMG_UINT32 *pui32MMapOffset, 98 IMG_SID hMHandle,
99 IMG_UINT32 *pui32ByteOffset, 99#else
100 IMG_UINT32 *pui32RealByteSize, IMG_UINT32 *pui32UserVAddr); 100 IMG_HANDLE hMHandle,
101#endif
102 IMG_UINT32 *pui32MMapOffset,
103 IMG_UINT32 *pui32ByteOffset,
104 IMG_UINT32 *pui32RealByteSize,
105 IMG_UINT32 *pui32UserVAddr);
101 106
102PVRSRV_ERROR 107PVRSRV_ERROR
103PVRMMapReleaseMMapData(PVRSRV_PER_PROCESS_DATA *psPerProc, 108PVRMMapReleaseMMapData(PVRSRV_PER_PROCESS_DATA *psPerProc,
109#if defined (SUPPORT_SID_INTERFACE)
110 IMG_SID hMHandle,
111#else
104 IMG_HANDLE hMHandle, 112 IMG_HANDLE hMHandle,
113#endif
105 IMG_BOOL *pbMUnmap, 114 IMG_BOOL *pbMUnmap,
106 IMG_UINT32 *pui32RealByteSize, 115 IMG_UINT32 *pui32RealByteSize,
107 IMG_UINT32 *pui32UserVAddr); 116 IMG_UINT32 *pui32UserVAddr);
diff --git a/drivers/gpu/pvr/module.c b/drivers/gpu/pvr/module.c
index d0c6eb14e3d..c9fc0cf44e5 100644
--- a/drivers/gpu/pvr/module.c
+++ b/drivers/gpu/pvr/module.c
@@ -47,8 +47,6 @@
47#include <linux/version.h> 47#include <linux/version.h>
48#include <linux/fs.h> 48#include <linux/fs.h>
49#include <linux/proc_fs.h> 49#include <linux/proc_fs.h>
50#include <linux/pm_runtime.h>
51#include <plat/gpu.h>
52 50
53#if defined(SUPPORT_DRI_DRM) 51#if defined(SUPPORT_DRI_DRM)
54#include <drm/drmP.h> 52#include <drm/drmP.h>
@@ -127,11 +125,11 @@ static int PVRSRVRelease(struct inode* pInode, struct file* pFile);
127 125
128static struct file_operations pvrsrv_fops = 126static struct file_operations pvrsrv_fops =
129{ 127{
130 .owner = THIS_MODULE, 128 .owner=THIS_MODULE,
131 .unlocked_ioctl = PVRSRV_BridgeDispatchKM, 129 .unlocked_ioctl = PVRSRV_BridgeDispatchKM,
132 .open = PVRSRVOpen, 130 .open=PVRSRVOpen,
133 .release = PVRSRVRelease, 131 .release=PVRSRVRelease,
134 .mmap = PVRMMap, 132 .mmap=PVRMMap,
135}; 133};
136#endif 134#endif
137 135
@@ -201,9 +199,24 @@ static LDM_DRV powervr_driver = {
201 .shutdown = PVRSRVDriverShutdown, 199 .shutdown = PVRSRVDriverShutdown,
202}; 200};
203 201
204struct gpu_platform_data *gpsSgxPlatformData;
205LDM_DEV *gpsPVRLDMDev; 202LDM_DEV *gpsPVRLDMDev;
206 203
204#if defined(MODULE) && defined(PVR_LDM_PLATFORM_MODULE)
205
206static IMG_VOID PVRSRVDeviceRelease(struct device unref__ *pDevice)
207{
208}
209
210static struct platform_device powervr_device = {
211 .name = DEVNAME,
212 .id = -1,
213 .dev = {
214 .release = PVRSRVDeviceRelease
215 }
216};
217
218#endif
219
207#if defined(PVR_LDM_PLATFORM_MODULE) 220#if defined(PVR_LDM_PLATFORM_MODULE)
208static int PVRSRVDriverProbe(LDM_DEV *pDevice) 221static int PVRSRVDriverProbe(LDM_DEV *pDevice)
209#endif 222#endif
@@ -221,16 +234,8 @@ static int __devinit PVRSRVDriverProbe(LDM_DEV *pDevice, const struct pci_device
221 { 234 {
222 return -EINVAL; 235 return -EINVAL;
223 } 236 }
224#endif 237#endif
225
226 gpsSgxPlatformData = pDevice->dev.platform_data;
227 if(!gpsSgxPlatformData)
228 {
229 PVR_TRACE(("No SGX platform device data."));
230 }
231 238
232 pm_runtime_enable(&pDevice->dev);
233
234 psSysData = SysAcquireDataNoCheck(); 239 psSysData = SysAcquireDataNoCheck();
235 if ( psSysData == IMG_NULL) 240 if ( psSysData == IMG_NULL)
236 { 241 {
@@ -269,8 +274,6 @@ static void __devexit PVRSRVDriverRemove(LDM_DEV *pDevice)
269 } 274 }
270#endif 275#endif
271 (IMG_VOID)SysDeinitialise(psSysData); 276 (IMG_VOID)SysDeinitialise(psSysData);
272
273 pm_runtime_disable(&pDevice->dev);
274 277
275 gpsPVRLDMDev = IMG_NULL; 278 gpsPVRLDMDev = IMG_NULL;
276 279
@@ -425,7 +428,9 @@ static int PVRSRVOpen(struct inode unref__ * pInode, struct file *pFile)
425 if(eError != PVRSRV_OK) 428 if(eError != PVRSRV_OK)
426 goto err_unlock; 429 goto err_unlock;
427 430
428#if defined(PVR_SECURE_FD_EXPORT) 431#if defined (SUPPORT_SID_INTERFACE)
432 psPrivateData->hKernelMemInfo = 0;
433#else
429 psPrivateData->hKernelMemInfo = NULL; 434 psPrivateData->hKernelMemInfo = NULL;
430#endif 435#endif
431#if defined(SUPPORT_DRI_DRM) && defined(PVR_SECURE_DRM_AUTH_EXPORT) 436#if defined(SUPPORT_DRI_DRM) && defined(PVR_SECURE_DRM_AUTH_EXPORT)
@@ -464,7 +469,7 @@ static int PVRSRVRelease(struct inode unref__ * pInode, struct file *pFile)
464 list_del(&psPrivateData->sDRMAuthListItem); 469 list_del(&psPrivateData->sDRMAuthListItem);
465#endif 470#endif
466 471
467 472
468 gui32ReleasePID = psPrivateData->ui32OpenPID; 473 gui32ReleasePID = psPrivateData->ui32OpenPID;
469 PVRSRVProcessDisconnect(psPrivateData->ui32OpenPID); 474 PVRSRVProcessDisconnect(psPrivateData->ui32OpenPID);
470 gui32ReleasePID = 0; 475 gui32ReleasePID = 0;
@@ -474,7 +479,7 @@ static int PVRSRVRelease(struct inode unref__ * pInode, struct file *pFile)
474 psPrivateData, psPrivateData->hBlockAlloc); 479 psPrivateData, psPrivateData->hBlockAlloc);
475 480
476#if !defined(SUPPORT_DRI_DRM) 481#if !defined(SUPPORT_DRI_DRM)
477 PRIVATE_DATA(pFile) = IMG_NULL; 482 PRIVATE_DATA(pFile) = IMG_NULL;
478#endif 483#endif
479 } 484 }
480 485
@@ -541,6 +546,16 @@ static int __init PVRCore_Init(IMG_VOID)
541 goto init_failed; 546 goto init_failed;
542 } 547 }
543 548
549#if defined(MODULE)
550 if ((error = platform_device_register(&powervr_device)) != 0)
551 {
552 platform_driver_unregister(&powervr_driver);
553
554 PVR_DPF((PVR_DBG_ERROR, "PVRCore_Init: unable to register platform device (%d)", error));
555
556 goto init_failed;
557 }
558#endif
544#endif 559#endif
545 560
546#if defined(PVR_LDM_PCI_MODULE) 561#if defined(PVR_LDM_PCI_MODULE)
@@ -623,6 +638,9 @@ sys_deinit:
623#endif 638#endif
624 639
625#if defined (PVR_LDM_PLATFORM_MODULE) 640#if defined (PVR_LDM_PLATFORM_MODULE)
641#if defined (MODULE)
642 platform_device_unregister(&powervr_device);
643#endif
626 platform_driver_unregister(&powervr_driver); 644 platform_driver_unregister(&powervr_driver);
627#endif 645#endif
628 646
@@ -689,6 +707,9 @@ static void __exit PVRCore_Cleanup(void)
689#endif 707#endif
690 708
691#if defined (PVR_LDM_PLATFORM_MODULE) 709#if defined (PVR_LDM_PLATFORM_MODULE)
710#if defined (MODULE)
711 platform_device_unregister(&powervr_device);
712#endif
692 platform_driver_unregister(&powervr_driver); 713 platform_driver_unregister(&powervr_driver);
693#endif 714#endif
694 715
diff --git a/drivers/gpu/pvr/omap4/sysconfig.c b/drivers/gpu/pvr/omap4/sysconfig.c
index 56ecb5ab9db..4904f2acb01 100644
--- a/drivers/gpu/pvr/omap4/sysconfig.c
+++ b/drivers/gpu/pvr/omap4/sysconfig.c
@@ -63,97 +63,6 @@ IMG_UINT32 PVRSRV_BridgeDispatchKM(IMG_UINT32 Ioctl,
63 IMG_UINT32 OutBufLen, 63 IMG_UINT32 OutBufLen,
64 IMG_UINT32 *pdwBytesTransferred); 64 IMG_UINT32 *pdwBytesTransferred);
65 65
66#if defined(DEBUG) && defined(DUMP_OMAP34xx_CLOCKS) && defined(__linux__)
67
68#pragma GCC diagnostic ignored "-Wstrict-prototypes"
69#include <mach/clock.h>
70
71#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29))
72#include <../mach-omap2/clock_34xx.h>
73#define ONCHIP_CLKS onchip_clks
74#else
75#include <../mach-omap2/clock34xx.h>
76#define ONCHIP_CLKS onchip_34xx_clks
77#endif
78
79static void omap3_clk_recalc(struct clk *clk) {}
80static void omap3_followparent_recalc(struct clk *clk) {}
81static void omap3_propagate_rate(struct clk *clk) {}
82static void omap3_table_recalc(struct clk *clk) {}
83static long omap3_round_to_table_rate(struct clk *clk, unsigned long rate) { return 0; }
84static int omap3_select_table_rate(struct clk *clk, unsigned long rate) { return 0; }
85
86#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,29))
87static void omap3_dpll_recalc(struct clk *clk, unsigned long parent_rate,
88 u8 rate_storage) {}
89static void omap3_clkoutx2_recalc(struct clk *clk, unsigned long parent_rate,
90 u8 rate_storage) {}
91static void omap3_dpll_allow_idle(struct clk *clk) {}
92static void omap3_dpll_deny_idle(struct clk *clk) {}
93static u32 omap3_dpll_autoidle_read(struct clk *clk) { return 0; }
94static int omap3_noncore_dpll_enable(struct clk *clk) { return 0; }
95static void omap3_noncore_dpll_disable(struct clk *clk) {}
96static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) { return 0; }
97static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate) { return 0; }
98void followparent_recalc(struct clk *clk, unsigned long new_parent_rate,
99 u8 rate_storage) {}
100long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate) { return 0; }
101void omap2_clksel_recalc(struct clk *clk, unsigned long new_parent_rate,
102 u8 rate_storage) {}
103long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate) { return 0; }
104int omap2_clksel_set_rate(struct clk *clk, unsigned long rate) { return 0; }
105void omap2_fixed_divisor_recalc(struct clk *clk, unsigned long new_parent_rate,
106 u8 rate_storage) {}
107void omap2_init_clksel_parent(struct clk *clk) {}
108#endif
109
110static void dump_omap34xx_clocks(void)
111{
112 struct clk **c;
113#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29))
114 struct vdd_prcm_config *t1 = vdd1_rate_table;
115 struct vdd_prcm_config *t2 = vdd2_rate_table;
116
117 t1 = t1;
118 t2 = t2;
119#else
120
121 omap3_dpll_allow_idle(0);
122 omap3_dpll_deny_idle(0);
123 omap3_dpll_autoidle_read(0);
124 omap3_clk_recalc(0);
125 omap3_followparent_recalc(0);
126 omap3_propagate_rate(0);
127 omap3_table_recalc(0);
128 omap3_round_to_table_rate(0, 0);
129 omap3_select_table_rate(0, 0);
130#endif
131
132 for(c = ONCHIP_CLKS; c < ONCHIP_CLKS + ARRAY_SIZE(ONCHIP_CLKS); c++)
133 {
134 struct clk *cp = *c, *copy;
135 unsigned long rate;
136 copy = clk_get(NULL, cp->name);
137 if(!copy)
138 continue;
139 rate = clk_get_rate(copy);
140 if (rate < 1000000)
141 {
142 PVR_DPF((PVR_DBG_ERROR, "%s: clock %s is %lu KHz (%lu Hz)", __func__, cp->name, rate/1000, rate));
143 }
144 else
145 {
146 PVR_DPF((PVR_DBG_ERROR, "%s: clock %s is %lu MHz (%lu Hz)", __func__, cp->name, rate/1000000, rate));
147 }
148 }
149}
150
151#else
152
153static INLINE void dump_omap34xx_clocks(void) {}
154
155#endif
156
157#if defined(SGX_OCP_REGS_ENABLED) 66#if defined(SGX_OCP_REGS_ENABLED)
158 67
159#define SYS_OMAP4430_OCP_REGS_SYS_PHYS_BASE (SYS_OMAP4430_SGX_REGS_SYS_PHYS_BASE + EUR_CR_OCP_REVISION) 68#define SYS_OMAP4430_OCP_REGS_SYS_PHYS_BASE (SYS_OMAP4430_SGX_REGS_SYS_PHYS_BASE + EUR_CR_OCP_REVISION)
@@ -168,6 +77,9 @@ static PVRSRV_ERROR EnableSGXClocksWrap(SYS_DATA *psSysData)
168 if(eError == PVRSRV_OK) 77 if(eError == PVRSRV_OK)
169 { 78 {
170 OSWriteHWReg(gpvOCPRegsLinAddr, 79 OSWriteHWReg(gpvOCPRegsLinAddr,
80 EUR_CR_OCP_SYSCONFIG - EUR_CR_OCP_REVISION,
81 0x14);
82 OSWriteHWReg(gpvOCPRegsLinAddr,
171 EUR_CR_OCP_DEBUG_CONFIG - EUR_CR_OCP_REVISION, 83 EUR_CR_OCP_DEBUG_CONFIG - EUR_CR_OCP_REVISION,
172 EUR_CR_OCP_DEBUG_CONFIG_THALIA_INT_BYPASS_MASK); 84 EUR_CR_OCP_DEBUG_CONFIG_THALIA_INT_BYPASS_MASK);
173 } 85 }
@@ -175,14 +87,14 @@ static PVRSRV_ERROR EnableSGXClocksWrap(SYS_DATA *psSysData)
175 return eError; 87 return eError;
176} 88}
177 89
178#else 90#else
179 91
180static INLINE PVRSRV_ERROR EnableSGXClocksWrap(SYS_DATA *psSysData) 92static INLINE PVRSRV_ERROR EnableSGXClocksWrap(SYS_DATA *psSysData)
181{ 93{
182 return EnableSGXClocks(psSysData); 94 return EnableSGXClocks(psSysData);
183} 95}
184 96
185#endif 97#endif
186 98
187static INLINE PVRSRV_ERROR EnableSystemClocksWrap(SYS_DATA *psSysData) 99static INLINE PVRSRV_ERROR EnableSystemClocksWrap(SYS_DATA *psSysData)
188{ 100{
@@ -191,7 +103,7 @@ static INLINE PVRSRV_ERROR EnableSystemClocksWrap(SYS_DATA *psSysData)
191#if !defined(SUPPORT_ACTIVE_POWER_MANAGEMENT) 103#if !defined(SUPPORT_ACTIVE_POWER_MANAGEMENT)
192 if(eError == PVRSRV_OK) 104 if(eError == PVRSRV_OK)
193 { 105 {
194 106
195 EnableSGXClocksWrap(psSysData); 107 EnableSGXClocksWrap(psSysData);
196 } 108 }
197#endif 109#endif
@@ -208,13 +120,13 @@ static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData)
208 120
209 PVR_UNREFERENCED_PARAMETER(psSysData); 121 PVR_UNREFERENCED_PARAMETER(psSysData);
210 122
211 123
212 gsSGXDeviceMap.ui32Flags = 0x0; 124 gsSGXDeviceMap.ui32Flags = 0x0;
213 125
214#if defined(NO_HARDWARE) 126#if defined(NO_HARDWARE)
215 127
216 128
217 eError = OSBaseAllocContigMemory(SYS_OMAP4430_SGX_REGS_SIZE, 129 eError = OSBaseAllocContigMemory(SYS_OMAP4430_SGX_REGS_SIZE,
218 &gsSGXRegsCPUVAddr, 130 &gsSGXRegsCPUVAddr,
219 &sCpuPAddr); 131 &sCpuPAddr);
220 if(eError != PVRSRV_OK) 132 if(eError != PVRSRV_OK)
@@ -225,21 +137,21 @@ static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData)
225 gsSGXDeviceMap.sRegsSysPBase = SysCpuPAddrToSysPAddr(gsSGXDeviceMap.sRegsCpuPBase); 137 gsSGXDeviceMap.sRegsSysPBase = SysCpuPAddrToSysPAddr(gsSGXDeviceMap.sRegsCpuPBase);
226 gsSGXDeviceMap.ui32RegsSize = SYS_OMAP4430_SGX_REGS_SIZE; 138 gsSGXDeviceMap.ui32RegsSize = SYS_OMAP4430_SGX_REGS_SIZE;
227#if defined(__linux__) 139#if defined(__linux__)
228 140
229 gsSGXDeviceMap.pvRegsCpuVBase = gsSGXRegsCPUVAddr; 141 gsSGXDeviceMap.pvRegsCpuVBase = gsSGXRegsCPUVAddr;
230#else 142#else
231 143
232 gsSGXDeviceMap.pvRegsCpuVBase = IMG_NULL; 144 gsSGXDeviceMap.pvRegsCpuVBase = IMG_NULL;
233#endif 145#endif
234 146
235 OSMemSet(gsSGXRegsCPUVAddr, 0, SYS_OMAP4430_SGX_REGS_SIZE); 147 OSMemSet(gsSGXRegsCPUVAddr, 0, SYS_OMAP4430_SGX_REGS_SIZE);
236 148
237 149
238 150
239 151
240 gsSGXDeviceMap.ui32IRQ = 0; 152 gsSGXDeviceMap.ui32IRQ = 0;
241 153
242#else 154#else
243 155
244 gsSGXDeviceMap.sRegsSysPBase.uiAddr = SYS_OMAP4430_SGX_REGS_SYS_PHYS_BASE; 156 gsSGXDeviceMap.sRegsSysPBase.uiAddr = SYS_OMAP4430_SGX_REGS_SYS_PHYS_BASE;
245 gsSGXDeviceMap.sRegsCpuPBase = SysSysPAddrToCpuPAddr(gsSGXDeviceMap.sRegsSysPBase); 157 gsSGXDeviceMap.sRegsCpuPBase = SysSysPAddrToCpuPAddr(gsSGXDeviceMap.sRegsSysPBase);
@@ -251,11 +163,14 @@ static PVRSRV_ERROR SysLocateDevices(SYS_DATA *psSysData)
251 163
252#if defined(PDUMP) 164#if defined(PDUMP)
253 { 165 {
166
254 static IMG_CHAR pszPDumpDevName[] = "SGXMEM"; 167 static IMG_CHAR pszPDumpDevName[] = "SGXMEM";
255 gsSGXDeviceMap.pszPDumpDevName = pszPDumpDevName; 168 gsSGXDeviceMap.pszPDumpDevName = pszPDumpDevName;
256 } 169 }
257#endif 170#endif
258 171
172
173
259 174
260 return PVRSRV_OK; 175 return PVRSRV_OK;
261} 176}
@@ -318,7 +233,7 @@ PVRSRV_ERROR SysInitialise(IMG_VOID)
318 IMG_UINT32 i; 233 IMG_UINT32 i;
319 PVRSRV_ERROR eError; 234 PVRSRV_ERROR eError;
320 PVRSRV_DEVICE_NODE *psDeviceNode; 235 PVRSRV_DEVICE_NODE *psDeviceNode;
321#if !defined(NO_OMAP_TIMER) 236#if !defined(PVR_NO_OMAP_TIMER)
322 IMG_CPU_PHYADDR TimerRegPhysBase; 237 IMG_CPU_PHYADDR TimerRegPhysBase;
323#endif 238#endif
324#if !defined(SGX_DYNAMIC_TIMING_INFO) 239#if !defined(SGX_DYNAMIC_TIMING_INFO)
@@ -344,7 +259,7 @@ PVRSRV_ERROR SysInitialise(IMG_VOID)
344 259
345 gpsSysData->ui32NumDevices = SYS_DEVICE_COUNT; 260 gpsSysData->ui32NumDevices = SYS_DEVICE_COUNT;
346 261
347 262
348 for(i=0; i<SYS_DEVICE_COUNT; i++) 263 for(i=0; i<SYS_DEVICE_COUNT; i++)
349 { 264 {
350 gpsSysData->sDeviceID[i].uiID = i; 265 gpsSysData->sDeviceID[i].uiID = i;
@@ -363,8 +278,8 @@ PVRSRV_ERROR SysInitialise(IMG_VOID)
363 return eError; 278 return eError;
364 } 279 }
365 280
366#if !defined(NO_OMAP_TIMER) 281#if !defined(PVR_NO_OMAP_TIMER)
367 TimerRegPhysBase.uiAddr = SYS_OMAP3430_GP11TIMER_REGS_SYS_PHYS_BASE; 282 TimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_REGS_SYS_PHYS_BASE;
368 gpsSysData->pvSOCTimerRegisterKM = IMG_NULL; 283 gpsSysData->pvSOCTimerRegisterKM = IMG_NULL;
369 gpsSysData->hSOCTimerRegisterOSMemHandle = 0; 284 gpsSysData->hSOCTimerRegisterOSMemHandle = 0;
370 OSReservePhys(TimerRegPhysBase, 285 OSReservePhys(TimerRegPhysBase,
@@ -372,27 +287,27 @@ PVRSRV_ERROR SysInitialise(IMG_VOID)
372 PVRSRV_HAP_MULTI_PROCESS|PVRSRV_HAP_UNCACHED, 287 PVRSRV_HAP_MULTI_PROCESS|PVRSRV_HAP_UNCACHED,
373 (IMG_VOID **)&gpsSysData->pvSOCTimerRegisterKM, 288 (IMG_VOID **)&gpsSysData->pvSOCTimerRegisterKM,
374 &gpsSysData->hSOCTimerRegisterOSMemHandle); 289 &gpsSysData->hSOCTimerRegisterOSMemHandle);
375#endif 290#endif
376 291
377#if !defined(SGX_DYNAMIC_TIMING_INFO) 292#if !defined(SGX_DYNAMIC_TIMING_INFO)
378 293
379 psTimingInfo = &gsSGXDeviceMap.sTimingInfo; 294 psTimingInfo = &gsSGXDeviceMap.sTimingInfo;
380 psTimingInfo->ui32CoreClockSpeed = SYS_SGX_CLOCK_SPEED; 295 psTimingInfo->ui32CoreClockSpeed = SYS_SGX_CLOCK_SPEED;
381 psTimingInfo->ui32HWRecoveryFreq = SYS_SGX_HWRECOVERY_TIMEOUT_FREQ; 296 psTimingInfo->ui32HWRecoveryFreq = SYS_SGX_HWRECOVERY_TIMEOUT_FREQ;
382#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT) 297#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT)
383 psTimingInfo->bEnableActivePM = IMG_TRUE; 298 psTimingInfo->bEnableActivePM = IMG_TRUE;
384#else 299#else
385 psTimingInfo->bEnableActivePM = IMG_FALSE; 300 psTimingInfo->bEnableActivePM = IMG_FALSE;
386#endif 301#endif
387 psTimingInfo->ui32ActivePowManLatencyms = SYS_SGX_ACTIVE_POWER_LATENCY_MS; 302 psTimingInfo->ui32ActivePowManLatencyms = SYS_SGX_ACTIVE_POWER_LATENCY_MS;
388 psTimingInfo->ui32uKernelFreq = SYS_SGX_PDS_TIMER_FREQ; 303 psTimingInfo->ui32uKernelFreq = SYS_SGX_PDS_TIMER_FREQ;
389#endif 304#endif
390 305
391 306
392 307
393 gpsSysSpecificData->ui32SrcClockDiv = 3; 308 gpsSysSpecificData->ui32SrcClockDiv = 3;
394 309
395 310
396 311
397 312
398 313
@@ -428,6 +343,18 @@ PVRSRV_ERROR SysInitialise(IMG_VOID)
428 } 343 }
429#endif 344#endif
430 345
346 eError = SysPMRuntimeRegister();
347 if (eError != PVRSRV_OK)
348 {
349 PVR_DPF((PVR_DBG_ERROR,"SysInitialise: Failed to register with OSPM!"));
350 (IMG_VOID)SysDeinitialise(gpsSysData);
351 gpsSysData = IMG_NULL;
352 return eError;
353 }
354 SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_PM_RUNTIME);
355
356
357
431 358
432 eError = PVRSRVRegisterDevice(gpsSysData, SGXRegisterDevice, 359 eError = PVRSRVRegisterDevice(gpsSysData, SGXRegisterDevice,
433 DEVICE_SGX_INTERRUPT, &gui32SGXDeviceID); 360 DEVICE_SGX_INTERRUPT, &gui32SGXDeviceID);
@@ -440,13 +367,14 @@ PVRSRV_ERROR SysInitialise(IMG_VOID)
440 } 367 }
441 SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_REGDEV); 368 SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_REGDEV);
442 369
370
443 371
444 372
445 373
446 psDeviceNode = gpsSysData->psDeviceNodeList; 374 psDeviceNode = gpsSysData->psDeviceNodeList;
447 while(psDeviceNode) 375 while(psDeviceNode)
448 { 376 {
449 377
450 switch(psDeviceNode->sDevId.eDeviceType) 378 switch(psDeviceNode->sDevId.eDeviceType)
451 { 379 {
452 case PVRSRV_DEVICE_TYPE_SGX: 380 case PVRSRV_DEVICE_TYPE_SGX:
@@ -454,16 +382,16 @@ PVRSRV_ERROR SysInitialise(IMG_VOID)
454 DEVICE_MEMORY_INFO *psDevMemoryInfo; 382 DEVICE_MEMORY_INFO *psDevMemoryInfo;
455 DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap; 383 DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap;
456 384
457 385
458 386
459 387
460 psDeviceNode->psLocalDevMemArena = IMG_NULL; 388 psDeviceNode->psLocalDevMemArena = IMG_NULL;
461 389
462 390
463 psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo; 391 psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo;
464 psDeviceMemoryHeap = psDevMemoryInfo->psDeviceMemoryHeap; 392 psDeviceMemoryHeap = psDevMemoryInfo->psDeviceMemoryHeap;
465 393
466 394
467 for(i=0; i<psDevMemoryInfo->ui32HeapCount; i++) 395 for(i=0; i<psDevMemoryInfo->ui32HeapCount; i++)
468 { 396 {
469 psDeviceMemoryHeap[i].ui32Attribs |= PVRSRV_BACKINGSTORE_SYSMEM_NONCONTIG; 397 psDeviceMemoryHeap[i].ui32Attribs |= PVRSRV_BACKINGSTORE_SYSMEM_NONCONTIG;
@@ -479,7 +407,7 @@ PVRSRV_ERROR SysInitialise(IMG_VOID)
479 return PVRSRV_ERROR_INIT_FAILURE; 407 return PVRSRV_ERROR_INIT_FAILURE;
480 } 408 }
481 409
482 410
483 psDeviceNode = psDeviceNode->psNext; 411 psDeviceNode = psDeviceNode->psNext;
484 } 412 }
485 413
@@ -501,9 +429,7 @@ PVRSRV_ERROR SysInitialise(IMG_VOID)
501 gpsSysData = IMG_NULL; 429 gpsSysData = IMG_NULL;
502 return eError; 430 return eError;
503 } 431 }
504#endif 432#endif
505
506 dump_omap34xx_clocks();
507 433
508 eError = PVRSRVInitialiseDevice(gui32SGXDeviceID); 434 eError = PVRSRVInitialiseDevice(gui32SGXDeviceID);
509 if (eError != PVRSRV_OK) 435 if (eError != PVRSRV_OK)
@@ -516,9 +442,9 @@ PVRSRV_ERROR SysInitialise(IMG_VOID)
516 SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_INITDEV); 442 SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_INITDEV);
517 443
518#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT) 444#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT)
519 445
520 DisableSGXClocks(gpsSysData); 446 DisableSGXClocks(gpsSysData);
521#endif 447#endif
522 448
523 return PVRSRV_OK; 449 return PVRSRV_OK;
524} 450}
@@ -535,7 +461,7 @@ PVRSRV_ERROR SysFinalise(IMG_VOID)
535 PVR_DPF((PVR_DBG_ERROR,"SysInitialise: Failed to Enable SGX clocks (%d)", eError)); 461 PVR_DPF((PVR_DBG_ERROR,"SysInitialise: Failed to Enable SGX clocks (%d)", eError));
536 return eError; 462 return eError;
537 } 463 }
538#endif 464#endif
539 465
540 eError = OSInstallMISR(gpsSysData); 466 eError = OSInstallMISR(gpsSysData);
541 if (eError != PVRSRV_OK) 467 if (eError != PVRSRV_OK)
@@ -546,7 +472,7 @@ PVRSRV_ERROR SysFinalise(IMG_VOID)
546 SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_MISR); 472 SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_MISR);
547 473
548#if defined(SYS_USING_INTERRUPTS) 474#if defined(SYS_USING_INTERRUPTS)
549 475
550 eError = OSInstallDeviceLISR(gpsSysData, gsSGXDeviceMap.ui32IRQ, "SGX ISR", gpsSGXDevNode); 476 eError = OSInstallDeviceLISR(gpsSysData, gsSGXDeviceMap.ui32IRQ, "SGX ISR", gpsSGXDevNode);
551 if (eError != PVRSRV_OK) 477 if (eError != PVRSRV_OK)
552 { 478 {
@@ -554,9 +480,10 @@ PVRSRV_ERROR SysFinalise(IMG_VOID)
554 return eError; 480 return eError;
555 } 481 }
556 SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LISR); 482 SYS_SPECIFIC_DATA_SET(&gsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LISR);
557#endif 483#endif
558
559 484
485#if defined(__linux__)
486
560 gpsSysData->pszVersionString = SysCreateVersionString(gsSGXDeviceMap.sRegsCpuPBase); 487 gpsSysData->pszVersionString = SysCreateVersionString(gsSGXDeviceMap.sRegsCpuPBase);
561 if (!gpsSysData->pszVersionString) 488 if (!gpsSysData->pszVersionString)
562 { 489 {
@@ -566,11 +493,12 @@ PVRSRV_ERROR SysFinalise(IMG_VOID)
566 { 493 {
567 PVR_DPF((PVR_DBG_WARNING, "SysFinalise: Version string: %s", gpsSysData->pszVersionString)); 494 PVR_DPF((PVR_DBG_WARNING, "SysFinalise: Version string: %s", gpsSysData->pszVersionString));
568 } 495 }
496#endif
569 497
570#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT) 498#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT)
571 499
572 DisableSGXClocks(gpsSysData); 500 DisableSGXClocks(gpsSysData);
573#endif 501#endif
574 502
575 gpsSysSpecificData->bSGXInitComplete = IMG_TRUE; 503 gpsSysSpecificData->bSGXInitComplete = IMG_TRUE;
576 504
@@ -592,7 +520,7 @@ PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData)
592 return eError; 520 return eError;
593 } 521 }
594 } 522 }
595#endif 523#endif
596 524
597 if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_MISR)) 525 if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_MISR))
598 { 526 {
@@ -625,14 +553,26 @@ PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData)
625 return eError; 553 return eError;
626 } 554 }
627 } 555 }
628 556
557 if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_PM_RUNTIME))
558 {
559 eError = SysPMRuntimeUnregister();
560 if (eError != PVRSRV_OK)
561 {
562 PVR_DPF((PVR_DBG_ERROR,"SysDeinitialise: Failed to unregister with OSPM!"));
563 (IMG_VOID)SysDeinitialise(gpsSysData);
564 gpsSysData = IMG_NULL;
565 return eError;
566 }
567 }
568
629#if defined(SGX_OCP_REGS_ENABLED) 569#if defined(SGX_OCP_REGS_ENABLED)
630 if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_OCPREGS)) 570 if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_OCPREGS))
631 { 571 {
632 OSUnMapPhysToLin(gpvOCPRegsLinAddr, 572 OSUnMapPhysToLin(gpvOCPRegsLinAddr,
633 SYS_OMAP4430_OCP_REGS_SIZE, 573 SYS_OMAP4430_OCP_REGS_SIZE,
634 PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY, 574 PVRSRV_HAP_UNCACHED|PVRSRV_HAP_KERNEL_ONLY,
635 IMG_NULL); 575 IMG_NULL);
636 } 576 }
637#endif 577#endif
638 578
@@ -644,7 +584,7 @@ PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData)
644 } 584 }
645 585
646 if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_ENVDATA)) 586 if (SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_ENVDATA))
647 { 587 {
648 eError = OSDeInitEnvData(gpsSysData->pvEnvSpecificData); 588 eError = OSDeInitEnvData(gpsSysData->pvEnvSpecificData);
649 if (eError != PVRSRV_OK) 589 if (eError != PVRSRV_OK)
650 { 590 {
@@ -653,7 +593,6 @@ PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData)
653 } 593 }
654 } 594 }
655 595
656#if !defined(NO_OMAP_TIMER)
657 if(gpsSysData->pvSOCTimerRegisterKM) 596 if(gpsSysData->pvSOCTimerRegisterKM)
658 { 597 {
659 OSUnReservePhys(gpsSysData->pvSOCTimerRegisterKM, 598 OSUnReservePhys(gpsSysData->pvSOCTimerRegisterKM,
@@ -661,18 +600,18 @@ PVRSRV_ERROR SysDeinitialise (SYS_DATA *psSysData)
661 PVRSRV_HAP_MULTI_PROCESS|PVRSRV_HAP_UNCACHED, 600 PVRSRV_HAP_MULTI_PROCESS|PVRSRV_HAP_UNCACHED,
662 gpsSysData->hSOCTimerRegisterOSMemHandle); 601 gpsSysData->hSOCTimerRegisterOSMemHandle);
663 } 602 }
664#endif
665 603
666 SysDeinitialiseCommon(gpsSysData); 604 SysDeinitialiseCommon(gpsSysData);
667 605
668#if defined(NO_HARDWARE) 606#if defined(NO_HARDWARE)
669 if(SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LOCATEDEV)) 607 if(SYS_SPECIFIC_DATA_TEST(gpsSysSpecificData, SYS_SPECIFIC_DATA_ENABLE_LOCATEDEV))
670 { 608 {
671 609
672 OSBaseFreeContigMemory(SYS_OMAP4430_SGX_REGS_SIZE, gsSGXRegsCPUVAddr, gsSGXDeviceMap.sRegsCpuPBase); 610 OSBaseFreeContigMemory(SYS_OMAP4430_SGX_REGS_SIZE, gsSGXRegsCPUVAddr, gsSGXDeviceMap.sRegsCpuPBase);
673 } 611 }
674#endif 612#endif
675 613
614
676 gpsSysSpecificData->ui32SysSpecificData = 0; 615 gpsSysSpecificData->ui32SysSpecificData = 0;
677 gpsSysSpecificData->bSGXInitComplete = IMG_FALSE; 616 gpsSysSpecificData->bSGXInitComplete = IMG_FALSE;
678 617
@@ -690,7 +629,7 @@ PVRSRV_ERROR SysGetDeviceMemoryMap(PVRSRV_DEVICE_TYPE eDeviceType,
690 { 629 {
691 case PVRSRV_DEVICE_TYPE_SGX: 630 case PVRSRV_DEVICE_TYPE_SGX:
692 { 631 {
693 632
694 *ppvDeviceMap = (IMG_VOID*)&gsSGXDeviceMap; 633 *ppvDeviceMap = (IMG_VOID*)&gsSGXDeviceMap;
695 634
696 break; 635 break;
@@ -711,9 +650,9 @@ IMG_DEV_PHYADDR SysCpuPAddrToDevPAddr(PVRSRV_DEVICE_TYPE eDeviceType,
711 650
712 PVR_UNREFERENCED_PARAMETER(eDeviceType); 651 PVR_UNREFERENCED_PARAMETER(eDeviceType);
713 652
714 653
715 DevPAddr.uiAddr = CpuPAddr.uiAddr; 654 DevPAddr.uiAddr = CpuPAddr.uiAddr;
716 655
717 return DevPAddr; 656 return DevPAddr;
718} 657}
719 658
@@ -721,7 +660,7 @@ IMG_CPU_PHYADDR SysSysPAddrToCpuPAddr (IMG_SYS_PHYADDR sys_paddr)
721{ 660{
722 IMG_CPU_PHYADDR cpu_paddr; 661 IMG_CPU_PHYADDR cpu_paddr;
723 662
724 663
725 cpu_paddr.uiAddr = sys_paddr.uiAddr; 664 cpu_paddr.uiAddr = sys_paddr.uiAddr;
726 return cpu_paddr; 665 return cpu_paddr;
727} 666}
@@ -730,7 +669,7 @@ IMG_SYS_PHYADDR SysCpuPAddrToSysPAddr (IMG_CPU_PHYADDR cpu_paddr)
730{ 669{
731 IMG_SYS_PHYADDR sys_paddr; 670 IMG_SYS_PHYADDR sys_paddr;
732 671
733 672
734 sys_paddr.uiAddr = cpu_paddr.uiAddr; 673 sys_paddr.uiAddr = cpu_paddr.uiAddr;
735 return sys_paddr; 674 return sys_paddr;
736} 675}
@@ -742,7 +681,7 @@ IMG_DEV_PHYADDR SysSysPAddrToDevPAddr(PVRSRV_DEVICE_TYPE eDeviceType, IMG_SYS_PH
742 681
743 PVR_UNREFERENCED_PARAMETER(eDeviceType); 682 PVR_UNREFERENCED_PARAMETER(eDeviceType);
744 683
745 684
746 DevPAddr.uiAddr = SysPAddr.uiAddr; 685 DevPAddr.uiAddr = SysPAddr.uiAddr;
747 686
748 return DevPAddr; 687 return DevPAddr;
@@ -755,7 +694,7 @@ IMG_SYS_PHYADDR SysDevPAddrToSysPAddr(PVRSRV_DEVICE_TYPE eDeviceType, IMG_DEV_PH
755 694
756 PVR_UNREFERENCED_PARAMETER(eDeviceType); 695 PVR_UNREFERENCED_PARAMETER(eDeviceType);
757 696
758 697
759 SysPAddr.uiAddr = DevPAddr.uiAddr; 698 SysPAddr.uiAddr = DevPAddr.uiAddr;
760 699
761 return SysPAddr; 700 return SysPAddr;
@@ -779,10 +718,10 @@ IMG_UINT32 SysGetInterruptSource(SYS_DATA *psSysData,
779{ 718{
780 PVR_UNREFERENCED_PARAMETER(psSysData); 719 PVR_UNREFERENCED_PARAMETER(psSysData);
781#if defined(NO_HARDWARE) 720#if defined(NO_HARDWARE)
782 721
783 return 0xFFFFFFFF; 722 return 0xFFFFFFFF;
784#else 723#else
785 724
786 return psDeviceNode->ui32SOCInterruptBit; 725 return psDeviceNode->ui32SOCInterruptBit;
787#endif 726#endif
788} 727}
@@ -793,7 +732,7 @@ IMG_VOID SysClearInterrupts(SYS_DATA* psSysData, IMG_UINT32 ui32ClearBits)
793 PVR_UNREFERENCED_PARAMETER(psSysData); 732 PVR_UNREFERENCED_PARAMETER(psSysData);
794 PVR_UNREFERENCED_PARAMETER(ui32ClearBits); 733 PVR_UNREFERENCED_PARAMETER(ui32ClearBits);
795 734
796 735
797 OSReadHWReg(((PVRSRV_SGXDEV_INFO *)gpsSGXDevNode->pvDevice)->pvRegsBaseKM, 736 OSReadHWReg(((PVRSRV_SGXDEV_INFO *)gpsSGXDevNode->pvDevice)->pvRegsBaseKM,
798 EUR_CR_EVENT_HOST_CLEAR); 737 EUR_CR_EVENT_HOST_CLEAR);
799} 738}
@@ -908,9 +847,9 @@ PVRSRV_ERROR SysDevicePrePowerState(IMG_UINT32 ui32DeviceIndex,
908 PVR_DPF((PVR_DBG_MESSAGE, "SysDevicePrePowerState: SGX Entering state D3")); 847 PVR_DPF((PVR_DBG_MESSAGE, "SysDevicePrePowerState: SGX Entering state D3"));
909 DisableSGXClocks(gpsSysData); 848 DisableSGXClocks(gpsSysData);
910 } 849 }
911#else 850#else
912 PVR_UNREFERENCED_PARAMETER(eNewPowerState ); 851 PVR_UNREFERENCED_PARAMETER(eNewPowerState );
913#endif 852#endif
914 return PVRSRV_OK; 853 return PVRSRV_OK;
915} 854}
916 855
@@ -934,9 +873,9 @@ PVRSRV_ERROR SysDevicePostPowerState(IMG_UINT32 ui32DeviceIndex,
934 PVR_DPF((PVR_DBG_MESSAGE, "SysDevicePostPowerState: SGX Leaving state D3")); 873 PVR_DPF((PVR_DBG_MESSAGE, "SysDevicePostPowerState: SGX Leaving state D3"));
935 eError = EnableSGXClocksWrap(gpsSysData); 874 eError = EnableSGXClocksWrap(gpsSysData);
936 } 875 }
937#else 876#else
938 PVR_UNREFERENCED_PARAMETER(eCurrentPowerState); 877 PVR_UNREFERENCED_PARAMETER(eCurrentPowerState);
939#endif 878#endif
940 879
941 return eError; 880 return eError;
942} 881}
@@ -957,7 +896,7 @@ PVRSRV_ERROR SysOEMFunction ( IMG_UINT32 ui32ID,
957 if ((ui32ID == OEM_GET_EXT_FUNCS) && 896 if ((ui32ID == OEM_GET_EXT_FUNCS) &&
958 (ulOutSize == sizeof(PVRSRV_DC_OEM_JTABLE))) 897 (ulOutSize == sizeof(PVRSRV_DC_OEM_JTABLE)))
959 { 898 {
960 899
961 PVRSRV_DC_OEM_JTABLE *psOEMJTable = (PVRSRV_DC_OEM_JTABLE*) pvOut; 900 PVRSRV_DC_OEM_JTABLE *psOEMJTable = (PVRSRV_DC_OEM_JTABLE*) pvOut;
962 psOEMJTable->pfnOEMBridgeDispatch = &PVRSRV_BridgeDispatchKM; 901 psOEMJTable->pfnOEMBridgeDispatch = &PVRSRV_BridgeDispatchKM;
963 return PVRSRV_OK; 902 return PVRSRV_OK;
diff --git a/drivers/gpu/pvr/omap4/sysconfig.h b/drivers/gpu/pvr/omap4/sysconfig.h
index bf789072847..b3714fd7074 100644
--- a/drivers/gpu/pvr/omap4/sysconfig.h
+++ b/drivers/gpu/pvr/omap4/sysconfig.h
@@ -1,26 +1,26 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation. 7 * version 2, as published by the Free Software Foundation.
8 * 8 *
9 * This program is distributed in the hope it will be useful but, except 9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the 10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose. 11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details. 12 * See the GNU General Public License for more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with 14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 * 17 *
18 * The full GNU General Public License is included in this distribution in 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING". 19 * the file called "COPYING".
20 * 20 *
21 * Contact Information: 21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com> 22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK 23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 * 24 *
25 ******************************************************************************/ 25 ******************************************************************************/
26 26
@@ -31,37 +31,29 @@
31 31
32#define VS_PRODUCT_NAME "OMAP4" 32#define VS_PRODUCT_NAME "OMAP4"
33 33
34#if defined(SGX_CLK_PER_192) 34#if defined(SGX540) && (SGX_CORE_REV == 120)
35#define SYS_SGX_CLOCK_SPEED 192000000 35#define SYS_SGX_CLOCK_SPEED 320000000
36#else 36#else
37#if defined(SGX_CLK_CORE_DIV8) 37#define SYS_SGX_CLOCK_SPEED 304742400
38#define SYS_SGX_CLOCK_SPEED 190464000
39#else
40#if defined(SGX_CLK_CORE_DIV5)
41#if defined(CONFIG_SGX_REV110)
42#define SYS_SGX_CLOCK_SPEED 304742400
43#endif
44#if defined(CONFIG_SGX_REV120)
45#define SYS_SGX_CLOCK_SPEED 307200000
46#endif
47#endif
48#endif
49#endif 38#endif
50 39
51#define SYS_SGX_HWRECOVERY_TIMEOUT_FREQ (100) 40#define SYS_SGX_HWRECOVERY_TIMEOUT_FREQ (100)
52#define SYS_SGX_PDS_TIMER_FREQ (1000) 41#define SYS_SGX_PDS_TIMER_FREQ (1000)
53 42
54#if !defined(SYS_SGX_ACTIVE_POWER_LATENCY_MS) 43#if !defined(SYS_SGX_ACTIVE_POWER_LATENCY_MS)
55#define SYS_SGX_ACTIVE_POWER_LATENCY_MS (100) 44#define SYS_SGX_ACTIVE_POWER_LATENCY_MS (1)
56#endif 45#endif
57 46
58 47
59
60#define SYS_OMAP4430_SGX_REGS_SYS_PHYS_BASE 0x56000000 48#define SYS_OMAP4430_SGX_REGS_SYS_PHYS_BASE 0x56000000
61#define SYS_OMAP4430_SGX_REGS_SIZE 0xFFFF
62 49
63#define SYS_OMAP4430_SGX_IRQ 53 /* OMAP 4 IRQs are offset by 32 */ 50#define SYS_OMAP4430_SGX_REGS_SIZE 0xFFFF
64 51
52#define SYS_OMAP4430_SGX_IRQ 53
65 53
54#define SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE 0x48088038
55#define SYS_OMAP4430_GP11TIMER_REGS_SYS_PHYS_BASE 0x4808803C
56#define SYS_OMAP4430_GP11TIMER_TSICR_SYS_PHYS_BASE 0x48088054
66 57
67#endif 58
59#endif
diff --git a/drivers/gpu/pvr/omap4/sysinfo.h b/drivers/gpu/pvr/omap4/sysinfo.h
index 80b86febda6..42489f0c632 100644
--- a/drivers/gpu/pvr/omap4/sysinfo.h
+++ b/drivers/gpu/pvr/omap4/sysinfo.h
@@ -1,26 +1,26 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation. 7 * version 2, as published by the Free Software Foundation.
8 * 8 *
9 * This program is distributed in the hope it will be useful but, except 9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the 10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose. 11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details. 12 * See the GNU General Public License for more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with 14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 * 17 *
18 * The full GNU General Public License is included in this distribution in 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING". 19 * the file called "COPYING".
20 * 20 *
21 * Contact Information: 21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com> 22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK 23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 * 24 *
25 ******************************************************************************/ 25 ******************************************************************************/
26 26
@@ -29,12 +29,13 @@
29 29
30#if defined(PVR_LINUX_USING_WORKQUEUES) 30#if defined(PVR_LINUX_USING_WORKQUEUES)
31#define MAX_HW_TIME_US (1000000) 31#define MAX_HW_TIME_US (1000000)
32#define WAIT_TRY_COUNT (20000)
32#else 33#else
33#define MAX_HW_TIME_US (500000) 34#define MAX_HW_TIME_US (500000)
35#define WAIT_TRY_COUNT (10000)
34#endif 36#endif
35 37
36#define WAIT_TRY_COUNT (10000)
37 38
38#define SYS_DEVICE_COUNT 4 39#define SYS_DEVICE_COUNT 15
39 40
40#endif 41#endif
diff --git a/drivers/gpu/pvr/omap4/syslocal.h b/drivers/gpu/pvr/omap4/syslocal.h
index 766870f366c..bc7748c4705 100644
--- a/drivers/gpu/pvr/omap4/syslocal.h
+++ b/drivers/gpu/pvr/omap4/syslocal.h
@@ -1,26 +1,26 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation. 7 * version 2, as published by the Free Software Foundation.
8 * 8 *
9 * This program is distributed in the hope it will be useful but, except 9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the 10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose. 11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details. 12 * See the GNU General Public License for more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with 14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 * 17 *
18 * The full GNU General Public License is included in this distribution in 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING". 19 * the file called "COPYING".
20 * 20 *
21 * Contact Information: 21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com> 22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK 23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 * 24 *
25 ******************************************************************************/ 25 ******************************************************************************/
26 26
@@ -41,21 +41,21 @@
41#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,26)) 41#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,26))
42#include <linux/semaphore.h> 42#include <linux/semaphore.h>
43#include <linux/resource.h> 43#include <linux/resource.h>
44#else 44#else
45#include <asm/semaphore.h> 45#include <asm/semaphore.h>
46#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22)) 46#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22))
47#include <asm/arch/resource.h> 47#include <asm/arch/resource.h>
48#endif 48#endif
49#endif 49#endif
50 50
51#endif 51#endif
52 52
53#if defined (__cplusplus) 53#if defined (__cplusplus)
54extern "C" { 54extern "C" {
55#endif 55#endif
56 56
57 57
58 58
59IMG_CHAR *SysCreateVersionString(IMG_CPU_PHYADDR sRegRegion); 59IMG_CHAR *SysCreateVersionString(IMG_CPU_PHYADDR sRegRegion);
60 60
61IMG_VOID DisableSystemClocks(SYS_DATA *psSysData); 61IMG_VOID DisableSystemClocks(SYS_DATA *psSysData);
@@ -77,13 +77,14 @@ PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData);
77#define SYS_SPECIFIC_DATA_PM_UNINSTALL_LISR 0x00000200 77#define SYS_SPECIFIC_DATA_PM_UNINSTALL_LISR 0x00000200
78#define SYS_SPECIFIC_DATA_PM_DISABLE_SYSCLOCKS 0x00000400 78#define SYS_SPECIFIC_DATA_PM_DISABLE_SYSCLOCKS 0x00000400
79#define SYS_SPECIFIC_DATA_ENABLE_OCPREGS 0x00000800 79#define SYS_SPECIFIC_DATA_ENABLE_OCPREGS 0x00000800
80#define SYS_SPECIFIC_DATA_ENABLE_PM_RUNTIME 0x00001000
80 81
81#define SYS_SPECIFIC_DATA_SET(psSysSpecData, flag) ((IMG_VOID)((psSysSpecData)->ui32SysSpecificData |= (flag))) 82#define SYS_SPECIFIC_DATA_SET(psSysSpecData, flag) ((IMG_VOID)((psSysSpecData)->ui32SysSpecificData |= (flag)))
82 83
83#define SYS_SPECIFIC_DATA_CLEAR(psSysSpecData, flag) ((IMG_VOID)((psSysSpecData)->ui32SysSpecificData &= ~(flag))) 84#define SYS_SPECIFIC_DATA_CLEAR(psSysSpecData, flag) ((IMG_VOID)((psSysSpecData)->ui32SysSpecificData &= ~(flag)))
84 85
85#define SYS_SPECIFIC_DATA_TEST(psSysSpecData, flag) (((psSysSpecData)->ui32SysSpecificData & (flag)) != 0) 86#define SYS_SPECIFIC_DATA_TEST(psSysSpecData, flag) (((psSysSpecData)->ui32SysSpecificData & (flag)) != 0)
86 87
87typedef struct _SYS_SPECIFIC_DATA_TAG_ 88typedef struct _SYS_SPECIFIC_DATA_TAG_
88{ 89{
89 IMG_UINT32 ui32SysSpecificData; 90 IMG_UINT32 ui32SysSpecificData;
@@ -110,16 +111,11 @@ typedef struct _SYS_SPECIFIC_DATA_TAG_
110 struct clk *psSGX_FCK; 111 struct clk *psSGX_FCK;
111 struct clk *psSGX_ICK; 112 struct clk *psSGX_ICK;
112 struct clk *psMPU_CK; 113 struct clk *psMPU_CK;
113#if !defined(NO_OMAP_TIMER)
114#if defined(DEBUG) || defined(TIMING) 114#if defined(DEBUG) || defined(TIMING)
115 struct clk *psGPT11_FCK; 115 struct clk *psGPT11_FCK;
116 struct clk *psGPT11_ICK; 116 struct clk *psGPT11_ICK;
117#endif 117#endif
118#endif 118#endif
119#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,22))
120 struct constraint_handle *pVdd2Handle;
121#endif
122#endif
123} SYS_SPECIFIC_DATA; 119} SYS_SPECIFIC_DATA;
124 120
125extern SYS_SPECIFIC_DATA *gpsSysSpecificData; 121extern SYS_SPECIFIC_DATA *gpsSysSpecificData;
@@ -129,10 +125,35 @@ IMG_BOOL WrapSystemPowerChange(SYS_SPECIFIC_DATA *psSysSpecData);
129IMG_VOID UnwrapSystemPowerChange(SYS_SPECIFIC_DATA *psSysSpecData); 125IMG_VOID UnwrapSystemPowerChange(SYS_SPECIFIC_DATA *psSysSpecData);
130#endif 126#endif
131 127
132#if defined(__cplusplus) 128#if defined(__linux__)
129
130PVRSRV_ERROR SysPMRuntimeRegister(void);
131PVRSRV_ERROR SysPMRuntimeUnregister(void);
132
133#else
134
135#ifdef INLINE_IS_PRAGMA
136#pragma inline(SysPMRuntimeRegister)
137#endif
138static INLINE PVRSRV_ERROR SysPMRuntimeRegister(void)
139{
140 return PVRSRV_OK;
133} 141}
142
143#ifdef INLINE_IS_PRAGMA
144#pragma inline(SysPMRuntimeUnregister)
134#endif 145#endif
146static INLINE PVRSRV_ERROR SysPMRuntimeUnregister(void)
147{
148 return PVRSRV_OK;
149}
150
151#endif
135 152
153#if defined(__cplusplus)
154}
136#endif 155#endif
137 156
157#endif
158
138 159
diff --git a/drivers/gpu/pvr/omap4/sysutils.c b/drivers/gpu/pvr/omap4/sysutils.c
index d2c4231315c..3d3def0c720 100644
--- a/drivers/gpu/pvr/omap4/sysutils.c
+++ b/drivers/gpu/pvr/omap4/sysutils.c
@@ -1,33 +1,30 @@
1/********************************************************************** 1/**********************************************************************
2 * 2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved. 3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 * 4 *
5 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License, 6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation. 7 * version 2, as published by the Free Software Foundation.
8 * 8 *
9 * This program is distributed in the hope it will be useful but, except 9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the 10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose. 11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details. 12 * See the GNU General Public License for more details.
13 * 13 *
14 * You should have received a copy of the GNU General Public License along with 14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 * 17 *
18 * The full GNU General Public License is included in this distribution in 18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING". 19 * the file called "COPYING".
20 * 20 *
21 * Contact Information: 21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com> 22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK 23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 * 24 *
25 ******************************************************************************/ 25 ******************************************************************************/
26 26
27#if defined(__linux__) 27#if defined(__linux__)
28#if defined(PVR_LINUX_USING_WORKQUEUES)
29#include "sysutils_linux_wqueue_compat.c"
30#else
31#include "sysutils_linux.c" 28#include "sysutils_linux.c"
32#endif 29#endif
33#endif 30
diff --git a/drivers/gpu/pvr/omap4/sysutils_linux.c b/drivers/gpu/pvr/omap4/sysutils_linux.c
new file mode 100644
index 00000000000..40b2cc35ccc
--- /dev/null
+++ b/drivers/gpu/pvr/omap4/sysutils_linux.c
@@ -0,0 +1,537 @@
1/**********************************************************************
2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 *
25 ******************************************************************************/
26
27#include <linux/version.h>
28#include <linux/clk.h>
29#include <linux/err.h>
30#include <linux/hardirq.h>
31#include <linux/mutex.h>
32
33#include "sgxdefs.h"
34#include "services_headers.h"
35#include "sysinfo.h"
36#include "sgxapi_km.h"
37#include "sysconfig.h"
38#include "sgxinfokm.h"
39#include "syslocal.h"
40
41#include <linux/platform_device.h>
42#include <linux/pm_runtime.h>
43
44#if !defined(PVR_LINUX_USING_WORKQUEUES)
45#error "PVR_LINUX_USING_WORKQUEUES must be defined"
46#endif
47
48#if ((defined(DEBUG) || defined(TIMING)) && \
49 (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,34))) && \
50 !defined(PVR_NO_OMAP_TIMER)
51#define PVR_OMAP4_TIMING_PRCM
52#endif
53
54#define ONE_MHZ 1000000
55#define HZ_TO_MHZ(m) ((m) / ONE_MHZ)
56
57#if defined(SUPPORT_OMAP3430_SGXFCLK_96M)
58#define SGX_PARENT_CLOCK "cm_96m_fck"
59#else
60#define SGX_PARENT_CLOCK "core_ck"
61#endif
62
63#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM)
64extern struct platform_device *gpsPVRLDMDev;
65#endif
66
67static IMG_VOID PowerLockWrap(SYS_SPECIFIC_DATA *psSysSpecData)
68{
69 if (!in_interrupt())
70 {
71 mutex_lock(&psSysSpecData->sPowerLock);
72
73 }
74}
75
76static IMG_VOID PowerLockUnwrap(SYS_SPECIFIC_DATA *psSysSpecData)
77{
78 if (!in_interrupt())
79 {
80 mutex_unlock(&psSysSpecData->sPowerLock);
81 }
82}
83
84PVRSRV_ERROR SysPowerLockWrap(IMG_VOID)
85{
86 SYS_DATA *psSysData;
87
88 SysAcquireData(&psSysData);
89
90 PowerLockWrap(psSysData->pvSysSpecificData);
91
92 return PVRSRV_OK;
93}
94
95IMG_VOID SysPowerLockUnwrap(IMG_VOID)
96{
97 SYS_DATA *psSysData;
98
99 SysAcquireData(&psSysData);
100
101 PowerLockUnwrap(psSysData->pvSysSpecificData);
102}
103
104IMG_BOOL WrapSystemPowerChange(SYS_SPECIFIC_DATA *psSysSpecData)
105{
106 return IMG_TRUE;
107}
108
109IMG_VOID UnwrapSystemPowerChange(SYS_SPECIFIC_DATA *psSysSpecData)
110{
111}
112
113static inline IMG_UINT32 scale_by_rate(IMG_UINT32 val, IMG_UINT32 rate1, IMG_UINT32 rate2)
114{
115 if (rate1 >= rate2)
116 {
117 return val * (rate1 / rate2);
118 }
119
120 return val / (rate2 / rate1);
121}
122
123static inline IMG_UINT32 scale_prop_to_SGX_clock(IMG_UINT32 val, IMG_UINT32 rate)
124{
125 return scale_by_rate(val, rate, SYS_SGX_CLOCK_SPEED);
126}
127
128static inline IMG_UINT32 scale_inv_prop_to_SGX_clock(IMG_UINT32 val, IMG_UINT32 rate)
129{
130 return scale_by_rate(val, SYS_SGX_CLOCK_SPEED, rate);
131}
132
133IMG_VOID SysGetSGXTimingInformation(SGX_TIMING_INFORMATION *psTimingInfo)
134{
135 IMG_UINT32 rate;
136
137#if defined(NO_HARDWARE)
138 rate = SYS_SGX_CLOCK_SPEED;
139#else
140 PVR_ASSERT(atomic_read(&gpsSysSpecificData->sSGXClocksEnabled) != 0);
141
142#if defined(OMAP4_PRCM_ENABLE)
143 rate = clk_get_rate(gpsSysSpecificData->psSGX_FCK);
144#else
145 rate = SYS_SGX_CLOCK_SPEED;
146#endif
147 PVR_ASSERT(rate != 0);
148#endif
149 psTimingInfo->ui32CoreClockSpeed = rate;
150 psTimingInfo->ui32HWRecoveryFreq = scale_prop_to_SGX_clock(SYS_SGX_HWRECOVERY_TIMEOUT_FREQ, rate);
151 psTimingInfo->ui32uKernelFreq = scale_prop_to_SGX_clock(SYS_SGX_PDS_TIMER_FREQ, rate);
152#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT)
153 psTimingInfo->bEnableActivePM = IMG_TRUE;
154#else
155 psTimingInfo->bEnableActivePM = IMG_FALSE;
156#endif
157 psTimingInfo->ui32ActivePowManLatencyms = SYS_SGX_ACTIVE_POWER_LATENCY_MS;
158}
159
160PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData)
161{
162#if !defined(NO_HARDWARE)
163 SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
164#if defined(OMAP4_PRCM_ENABLE)
165 long lNewRate;
166 long lRate;
167 IMG_INT res;
168#endif
169
170
171 if (atomic_read(&psSysSpecData->sSGXClocksEnabled) != 0)
172 {
173 return PVRSRV_OK;
174 }
175
176 PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: Enabling SGX Clocks"));
177
178#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM)
179 pm_runtime_get_sync(&gpsPVRLDMDev->dev);
180#endif
181
182#if defined(OMAP4_PRCM_ENABLE)
183
184#if defined(DEBUG)
185 {
186 IMG_UINT32 rate = clk_get_rate(psSysSpecData->psMPU_CK);
187 PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: CPU Clock is %dMhz", HZ_TO_MHZ(rate)));
188 }
189#endif
190
191 res = clk_enable(psSysSpecData->psSGX_FCK);
192 if (res < 0)
193 {
194 PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't enable SGX functional clock (%d)", res));
195 return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK;
196 }
197
198 res = clk_enable(psSysSpecData->psSGX_ICK);
199 if (res < 0)
200 {
201 PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't enable SGX interface clock (%d)", res));
202
203 clk_disable(psSysSpecData->psSGX_FCK);
204 return PVRSRV_ERROR_UNABLE_TO_ENABLE_CLOCK;
205 }
206
207 lNewRate = clk_round_rate(psSysSpecData->psSGX_FCK, SYS_SGX_CLOCK_SPEED + ONE_MHZ);
208 if (lNewRate <= 0)
209 {
210 PVR_DPF((PVR_DBG_ERROR, "EnableSGXClocks: Couldn't round SGX functional clock rate"));
211 return PVRSRV_ERROR_UNABLE_TO_ROUND_CLOCK_RATE;
212 }
213
214
215 lRate = clk_get_rate(psSysSpecData->psSGX_FCK);
216 if (lRate != lNewRate)
217 {
218 res = clk_set_rate(psSysSpecData->psSGX_FCK, lNewRate);
219 if (res < 0)
220 {
221 PVR_DPF((PVR_DBG_WARNING, "EnableSGXClocks: Couldn't set SGX functional clock rate (%d)", res));
222 }
223 }
224
225#if defined(DEBUG)
226 {
227 IMG_UINT32 rate = clk_get_rate(psSysSpecData->psSGX_FCK);
228 PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: SGX Functional Clock is %dMhz", HZ_TO_MHZ(rate)));
229 }
230#endif
231
232#endif
233
234
235 atomic_set(&psSysSpecData->sSGXClocksEnabled, 1);
236
237#else
238 PVR_UNREFERENCED_PARAMETER(psSysData);
239#endif
240 return PVRSRV_OK;
241}
242
243
244IMG_VOID DisableSGXClocks(SYS_DATA *psSysData)
245{
246#if !defined(NO_HARDWARE)
247 SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
248
249
250 if (atomic_read(&psSysSpecData->sSGXClocksEnabled) == 0)
251 {
252 return;
253 }
254
255 PVR_DPF((PVR_DBG_MESSAGE, "DisableSGXClocks: Disabling SGX Clocks"));
256
257#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM)
258 pm_runtime_put_sync(&gpsPVRLDMDev->dev);
259#endif
260
261#if defined(OMAP4_PRCM_ENABLE)
262 if (psSysSpecData->psSGX_ICK)
263 {
264 clk_disable(psSysSpecData->psSGX_ICK);
265 }
266
267 if (psSysSpecData->psSGX_FCK)
268 {
269 clk_disable(psSysSpecData->psSGX_FCK);
270 }
271#endif
272
273
274 atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
275
276#else
277 PVR_UNREFERENCED_PARAMETER(psSysData);
278#endif
279}
280
281PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
282{
283 SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
284#if (defined(OMAP4_PRCM_ENABLE) || defined(PVR_OMAP4_TIMING_PRCM))
285 struct clk *psCLK;
286 IMG_INT res;
287#endif
288#if defined(PVR_OMAP4_TIMING_PRCM)
289 struct clk *sys_ck;
290 IMG_INT rate;
291#endif
292 PVRSRV_ERROR eError;
293
294#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER)
295 IMG_CPU_PHYADDR TimerRegPhysBase;
296 IMG_HANDLE hTimerEnable;
297 IMG_UINT32 *pui32TimerEnable;
298#endif
299
300 PVR_TRACE(("EnableSystemClocks: Enabling System Clocks"));
301
302 if (!psSysSpecData->bSysClocksOneTimeInit)
303 {
304 mutex_init(&psSysSpecData->sPowerLock);
305
306 atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
307
308#if defined(OMAP4_PRCM_ENABLE)
309 psCLK = clk_get(NULL, SGX_PARENT_CLOCK);
310 if (IS_ERR(psCLK))
311 {
312 PVR_DPF((PVR_DBG_ERROR, "EnableSsystemClocks: Couldn't get Core Clock"));
313 goto ExitError;
314 }
315 psSysSpecData->psCORE_CK = psCLK;
316
317 psCLK = clk_get(NULL, "sgx_fck");
318 if (IS_ERR(psCLK))
319 {
320 PVR_DPF((PVR_DBG_ERROR, "EnableSsystemClocks: Couldn't get SGX Functional Clock"));
321 goto ExitError;
322 }
323 psSysSpecData->psSGX_FCK = psCLK;
324
325 psCLK = clk_get(NULL, "sgx_ick");
326 if (IS_ERR(psCLK))
327 {
328 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get SGX Interface Clock"));
329 goto ExitError;
330 }
331 psSysSpecData->psSGX_ICK = psCLK;
332
333#if defined(DEBUG)
334 psCLK = clk_get(NULL, "mpu_ck");
335 if (IS_ERR(psCLK))
336 {
337 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get MPU Clock"));
338 goto ExitError;
339 }
340 psSysSpecData->psMPU_CK = psCLK;
341#endif
342 res = clk_set_parent(psSysSpecData->psSGX_FCK, psSysSpecData->psCORE_CK);
343 if (res < 0)
344 {
345 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't set SGX parent clock (%d)", res));
346 goto ExitError;
347 }
348#endif
349
350 psSysSpecData->bSysClocksOneTimeInit = IMG_TRUE;
351 }
352
353#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER)
354#if defined(PVR_OMAP4_TIMING_PRCM)
355
356 psCLK = clk_get(NULL, "gpt11_fck");
357 if (IS_ERR(psCLK))
358 {
359 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock"));
360 goto ExitUnRegisterConstraintNotifications;
361 }
362 psSysSpecData->psGPT11_FCK = psCLK;
363
364 psCLK = clk_get(NULL, "gpt11_ick");
365 if (IS_ERR(psCLK))
366 {
367 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock"));
368 goto ExitUnRegisterConstraintNotifications;
369 }
370 psSysSpecData->psGPT11_ICK = psCLK;
371
372 sys_ck = clk_get(NULL, "sys_clkin_ck");
373 if (IS_ERR(sys_ck))
374 {
375 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get System clock"));
376 goto ExitUnRegisterConstraintNotifications;
377 }
378
379 if(clk_get_parent(psSysSpecData->psGPT11_FCK) != sys_ck)
380 {
381 PVR_TRACE(("Setting GPTIMER11 parent to System Clock"));
382 res = clk_set_parent(psSysSpecData->psGPT11_FCK, sys_ck);
383 if (res < 0)
384 {
385 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't set GPTIMER11 parent clock (%d)", res));
386 goto ExitUnRegisterConstraintNotifications;
387 }
388 }
389
390 rate = clk_get_rate(psSysSpecData->psGPT11_FCK);
391 PVR_TRACE(("GPTIMER11 clock is %dMHz", HZ_TO_MHZ(rate)));
392
393 res = clk_enable(psSysSpecData->psGPT11_FCK);
394 if (res < 0)
395 {
396 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res));
397 goto ExitUnRegisterConstraintNotifications;
398 }
399
400 res = clk_enable(psSysSpecData->psGPT11_ICK);
401 if (res < 0)
402 {
403 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 interface clock (%d)", res));
404 goto ExitDisableGPT11FCK;
405 }
406#endif
407
408
409 TimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_TSICR_SYS_PHYS_BASE;
410 pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase,
411 4,
412 PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
413 &hTimerEnable);
414
415 if (pui32TimerEnable == IMG_NULL)
416 {
417 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
418 goto ExitDisableGPT11ICK;
419 }
420
421 if(!(*pui32TimerEnable & 4))
422 {
423 PVR_TRACE(("Setting GPTIMER11 mode to posted (currently is non-posted)"));
424
425
426 *pui32TimerEnable |= 4;
427 }
428
429 OSUnMapPhysToLin(pui32TimerEnable,
430 4,
431 PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
432 hTimerEnable);
433
434
435 TimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE;
436 pui32TimerEnable = OSMapPhysToLin(TimerRegPhysBase,
437 4,
438 PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
439 &hTimerEnable);
440
441 if (pui32TimerEnable == IMG_NULL)
442 {
443 PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed"));
444 goto ExitDisableGPT11ICK;
445 }
446
447
448 *pui32TimerEnable = 3;
449
450 OSUnMapPhysToLin(pui32TimerEnable,
451 4,
452 PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
453 hTimerEnable);
454
455#endif
456
457 eError = PVRSRV_OK;
458 goto Exit;
459
460#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER)
461ExitDisableGPT11ICK:
462#if defined(PVR_OMAP4_TIMING_PRCM)
463 clk_disable(psSysSpecData->psGPT11_ICK);
464ExitDisableGPT11FCK:
465 clk_disable(psSysSpecData->psGPT11_FCK);
466ExitUnRegisterConstraintNotifications:
467#endif
468#endif
469#if defined(OMAP4_PRCM_ENABLE)
470ExitError:
471#endif
472 eError = PVRSRV_ERROR_DISABLE_CLOCK_FAILURE;
473Exit:
474 return eError;
475}
476
477IMG_VOID DisableSystemClocks(SYS_DATA *psSysData)
478{
479#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER)
480#if defined(PVR_OMAP4_TIMING_PRCM)
481 SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
482#endif
483 IMG_CPU_PHYADDR TimerRegPhysBase;
484 IMG_HANDLE hTimerDisable;
485 IMG_UINT32 *pui32TimerDisable;
486#endif
487
488 PVR_TRACE(("DisableSystemClocks: Disabling System Clocks"));
489
490
491 DisableSGXClocks(psSysData);
492
493#if (defined(DEBUG) || defined(TIMING)) && !defined(PVR_NO_OMAP_TIMER)
494
495 TimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE;
496 pui32TimerDisable = OSMapPhysToLin(TimerRegPhysBase,
497 4,
498 PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
499 &hTimerDisable);
500
501 if (pui32TimerDisable == IMG_NULL)
502 {
503 PVR_DPF((PVR_DBG_ERROR, "DisableSystemClocks: OSMapPhysToLin failed"));
504 }
505 else
506 {
507 *pui32TimerDisable = 0;
508
509 OSUnMapPhysToLin(pui32TimerDisable,
510 4,
511 PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED,
512 hTimerDisable);
513 }
514
515#if defined(PVR_OMAP4_TIMING_PRCM)
516 clk_disable(psSysSpecData->psGPT11_ICK);
517
518 clk_disable(psSysSpecData->psGPT11_FCK);
519#endif
520#endif
521}
522
523PVRSRV_ERROR SysPMRuntimeRegister(void)
524{
525#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM)
526 pm_runtime_enable(&gpsPVRLDMDev->dev);
527#endif
528 return PVRSRV_OK;
529}
530
531PVRSRV_ERROR SysPMRuntimeUnregister(void)
532{
533#if defined(LDM_PLATFORM) && !defined(SUPPORT_DRI_DRM)
534 pm_runtime_disable(&gpsPVRLDMDev->dev);
535#endif
536 return PVRSRV_OK;
537}
diff --git a/drivers/gpu/pvr/omap4/sysutils_linux_wqueue_compat.c b/drivers/gpu/pvr/omap4/sysutils_linux_wqueue_compat.c
deleted file mode 100644
index 5aa875d6895..00000000000
--- a/drivers/gpu/pvr/omap4/sysutils_linux_wqueue_compat.c
+++ /dev/null
@@ -1,198 +0,0 @@
1/**********************************************************************
2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 *
25 ******************************************************************************/
26
27#include <linux/version.h>
28#include <linux/clk.h>
29#include <linux/err.h>
30#include <linux/hardirq.h>
31#include <linux/mutex.h>
32
33#include <plat/gpu.h>
34#include <plat/omap-pm.h>
35#include <linux/pm_runtime.h>
36#include <plat/omap_device.h>
37#include "sgxdefs.h"
38#include "services_headers.h"
39#include "sysinfo.h"
40#include "sgxapi_km.h"
41#include "sysconfig.h"
42#include "sgxinfokm.h"
43#include "syslocal.h"
44
45#if !defined(PVR_LINUX_USING_WORKQUEUES)
46#error "PVR_LINUX_USING_WORKQUEUES must be defined"
47#endif
48
49#define ONE_MHZ 1000000
50#define HZ_TO_MHZ(m) ((m) / ONE_MHZ)
51
52#define LDM_DEV struct platform_device
53extern LDM_DEV *gpsPVRLDMDev;
54extern struct gpu_platform_data *gpsSgxPlatformData;
55
56
57#if !defined(NO_HARDWARE)
58
59static struct pm_qos_request_list *qos_request;
60
61#endif
62
63PVRSRV_ERROR SysPowerLockWrap(SYS_DATA unref__ *psSysData)
64{
65 return PVRSRV_OK;
66}
67
68IMG_VOID SysPowerLockUnwrap(SYS_DATA unref__ *psSysData)
69{
70}
71
72IMG_BOOL WrapSystemPowerChange(SYS_SPECIFIC_DATA *psSysSpecData)
73{
74 return IMG_TRUE;
75}
76
77IMG_VOID UnwrapSystemPowerChange(SYS_SPECIFIC_DATA *psSysSpecData)
78{
79}
80
81static inline IMG_UINT32 scale_by_rate(IMG_UINT32 val, IMG_UINT32 rate1, IMG_UINT32 rate2)
82{
83 if (rate1 >= rate2)
84 {
85 return val * (rate1 / rate2);
86 }
87
88 return val / (rate2 / rate1);
89}
90
91static inline IMG_UINT32 scale_prop_to_SGX_clock(IMG_UINT32 val, IMG_UINT32 rate)
92{
93 return scale_by_rate(val, rate, SYS_SGX_CLOCK_SPEED);
94}
95
96static inline IMG_UINT32 scale_inv_prop_to_SGX_clock(IMG_UINT32 val, IMG_UINT32 rate)
97{
98 return scale_by_rate(val, SYS_SGX_CLOCK_SPEED, rate);
99}
100
101IMG_VOID SysGetSGXTimingInformation(SGX_TIMING_INFORMATION *psTimingInfo)
102{
103 IMG_UINT32 rate;
104
105#if defined(NO_HARDWARE)
106 rate = SYS_SGX_CLOCK_SPEED;
107#else
108 PVR_ASSERT(atomic_read(&gpsSysSpecificData->sSGXClocksEnabled) != 0);
109
110 rate = SYS_SGX_CLOCK_SPEED;
111 PVR_ASSERT(rate != 0);
112#endif
113 psTimingInfo->ui32CoreClockSpeed = rate;
114 psTimingInfo->ui32HWRecoveryFreq = scale_prop_to_SGX_clock(SYS_SGX_HWRECOVERY_TIMEOUT_FREQ, rate);
115 psTimingInfo->ui32uKernelFreq = scale_prop_to_SGX_clock(SYS_SGX_PDS_TIMER_FREQ, rate);
116#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT)
117 psTimingInfo->bEnableActivePM = IMG_TRUE;
118#else
119 psTimingInfo->bEnableActivePM = IMG_FALSE;
120#endif
121 psTimingInfo->ui32ActivePowManLatencyms = SYS_SGX_ACTIVE_POWER_LATENCY_MS;
122}
123
124PVRSRV_ERROR EnableSGXClocks(SYS_DATA *psSysData)
125{
126#if !defined(NO_HARDWARE)
127 SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
128
129 if (atomic_read(&psSysSpecData->sSGXClocksEnabled) != 0)
130 {
131 return PVRSRV_OK;
132 }
133 PVR_DPF((PVR_DBG_MESSAGE, "EnableSGXClocks: Enabling SGX Clocks"));
134
135 pm_runtime_get_sync(&gpsPVRLDMDev->dev);
136 gpsSgxPlatformData->set_max_mpu_wakeup_lat(&qos_request, 0);
137 omap_device_set_rate(&gpsPVRLDMDev->dev,
138 &gpsPVRLDMDev->dev, SYS_SGX_CLOCK_SPEED);
139 atomic_set(&psSysSpecData->sSGXClocksEnabled, 1);
140
141#else
142 PVR_UNREFERENCED_PARAMETER(psSysData);
143#endif
144 return PVRSRV_OK;
145}
146
147
148IMG_VOID DisableSGXClocks(SYS_DATA *psSysData)
149{
150#if !defined(NO_HARDWARE)
151 SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
152
153
154 if (atomic_read(&psSysSpecData->sSGXClocksEnabled) == 0)
155 {
156 return;
157 }
158
159 PVR_DPF((PVR_DBG_MESSAGE, "DisableSGXClocks: Disabling SGX Clocks"));
160
161 pm_runtime_put_sync(&gpsPVRLDMDev->dev);
162 gpsSgxPlatformData->set_max_mpu_wakeup_lat(&qos_request, -1);
163 omap_device_set_rate(&gpsPVRLDMDev->dev, &gpsPVRLDMDev->dev, 0);
164 atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
165
166#else
167 PVR_UNREFERENCED_PARAMETER(psSysData);
168#endif
169}
170
171PVRSRV_ERROR EnableSystemClocks(SYS_DATA *psSysData)
172{
173 SYS_SPECIFIC_DATA *psSysSpecData = (SYS_SPECIFIC_DATA *) psSysData->pvSysSpecificData;
174 PVRSRV_ERROR eError;
175
176 PVR_TRACE(("EnableSystemClocks: Enabling System Clocks"));
177
178 if (!psSysSpecData->bSysClocksOneTimeInit)
179 {
180 mutex_init(&psSysSpecData->sPowerLock);
181
182 atomic_set(&psSysSpecData->sSGXClocksEnabled, 0);
183 psSysSpecData->bSysClocksOneTimeInit = IMG_TRUE;
184 }
185
186 eError = PVRSRV_OK;
187
188 return eError;
189}
190
191IMG_VOID DisableSystemClocks(SYS_DATA *psSysData)
192{
193
194 PVR_TRACE(("DisableSystemClocks: Disabling System Clocks"));
195
196 DisableSGXClocks(psSysData);
197
198}
diff --git a/drivers/gpu/pvr/osfunc.c b/drivers/gpu/pvr/osfunc.c
index ba3bf01bcf9..c72dd561410 100644
--- a/drivers/gpu/pvr/osfunc.c
+++ b/drivers/gpu/pvr/osfunc.c
@@ -83,9 +83,6 @@
83 83
84#define EVENT_OBJECT_TIMEOUT_MS (100) 84#define EVENT_OBJECT_TIMEOUT_MS (100)
85 85
86#define HOST_ALLOC_MEM_USING_KMALLOC ((IMG_HANDLE)0)
87#define HOST_ALLOC_MEM_USING_VMALLOC ((IMG_HANDLE)1)
88
89#if !defined(DEBUG_LINUX_MEMORY_ALLOCATIONS) 86#if !defined(DEBUG_LINUX_MEMORY_ALLOCATIONS)
90PVRSRV_ERROR OSAllocMem_Impl(IMG_UINT32 ui32Flags, IMG_UINT32 ui32Size, IMG_PVOID *ppvCpuVAddr, IMG_HANDLE *phBlockAlloc) 87PVRSRV_ERROR OSAllocMem_Impl(IMG_UINT32 ui32Flags, IMG_UINT32 ui32Size, IMG_PVOID *ppvCpuVAddr, IMG_HANDLE *phBlockAlloc)
91#else 88#else
@@ -93,40 +90,26 @@ PVRSRV_ERROR OSAllocMem_Impl(IMG_UINT32 ui32Flags, IMG_UINT32 ui32Size, IMG_PVOI
93#endif 90#endif
94{ 91{
95 PVR_UNREFERENCED_PARAMETER(ui32Flags); 92 PVR_UNREFERENCED_PARAMETER(ui32Flags);
93 PVR_UNREFERENCED_PARAMETER(phBlockAlloc);
96 94
97#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS) 95#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS)
98 *ppvCpuVAddr = _KMallocWrapper(ui32Size, pszFilename, ui32Line); 96 *ppvCpuVAddr = _KMallocWrapper(ui32Size, GFP_KERNEL | __GFP_NOWARN, pszFilename, ui32Line);
99#else 97#else
100 *ppvCpuVAddr = KMallocWrapper(ui32Size); 98 *ppvCpuVAddr = KMallocWrapper(ui32Size, GFP_KERNEL | __GFP_NOWARN);
101#endif 99#endif
102 if(*ppvCpuVAddr) 100
103 { 101 if(!*ppvCpuVAddr)
104 if (phBlockAlloc)
105 { 102 {
106 103
107 *phBlockAlloc = HOST_ALLOC_MEM_USING_KMALLOC;
108 }
109 }
110 else
111 {
112 if (!phBlockAlloc)
113 {
114 return PVRSRV_ERROR_OUT_OF_MEMORY;
115 }
116
117
118#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS) 104#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS)
119 *ppvCpuVAddr = _VMallocWrapper(ui32Size, PVRSRV_HAP_CACHED, pszFilename, ui32Line); 105 *ppvCpuVAddr = _VMallocWrapper(ui32Size, PVRSRV_HAP_CACHED, pszFilename, ui32Line);
120#else 106#else
121 *ppvCpuVAddr = VMallocWrapper(ui32Size, PVRSRV_HAP_CACHED); 107 *ppvCpuVAddr = VMallocWrapper(ui32Size, PVRSRV_HAP_CACHED);
122#endif 108#endif
123 if (!*ppvCpuVAddr) 109 if (!*ppvCpuVAddr)
124 { 110 {
125 return PVRSRV_ERROR_OUT_OF_MEMORY; 111 return PVRSRV_ERROR_OUT_OF_MEMORY;
126 } 112 }
127
128
129 *phBlockAlloc = HOST_ALLOC_MEM_USING_VMALLOC;
130 } 113 }
131 114
132 return PVRSRV_OK; 115 return PVRSRV_OK;
@@ -138,22 +121,23 @@ PVRSRV_ERROR OSFreeMem_Impl(IMG_UINT32 ui32Flags, IMG_UINT32 ui32Size, IMG_PVOID
138#else 121#else
139PVRSRV_ERROR OSFreeMem_Impl(IMG_UINT32 ui32Flags, IMG_UINT32 ui32Size, IMG_PVOID pvCpuVAddr, IMG_HANDLE hBlockAlloc, IMG_CHAR *pszFilename, IMG_UINT32 ui32Line) 122PVRSRV_ERROR OSFreeMem_Impl(IMG_UINT32 ui32Flags, IMG_UINT32 ui32Size, IMG_PVOID pvCpuVAddr, IMG_HANDLE hBlockAlloc, IMG_CHAR *pszFilename, IMG_UINT32 ui32Line)
140#endif 123#endif
141{ 124{
142 PVR_UNREFERENCED_PARAMETER(ui32Flags); 125 PVR_UNREFERENCED_PARAMETER(ui32Flags);
143 PVR_UNREFERENCED_PARAMETER(ui32Size); 126 PVR_UNREFERENCED_PARAMETER(ui32Size);
127 PVR_UNREFERENCED_PARAMETER(hBlockAlloc);
144 128
145 if (hBlockAlloc == HOST_ALLOC_MEM_USING_VMALLOC) 129 if (is_vmalloc_addr(pvCpuVAddr))
146 { 130 {
147#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS) 131#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS)
148 _VFreeWrapper(pvCpuVAddr, pszFilename, ui32Line); 132 _VFreeWrapper(pvCpuVAddr, pszFilename, ui32Line);
149#else 133#else
150 VFreeWrapper(pvCpuVAddr); 134 VFreeWrapper(pvCpuVAddr);
151#endif 135#endif
152 } 136 }
153 else 137 else
154 { 138 {
155#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS) 139#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS)
156 _KFreeWrapper(pvCpuVAddr, pszFilename, ui32Line); 140 _KFreeWrapper(pvCpuVAddr, pszFilename, ui32Line);
157#else 141#else
158 KFreeWrapper(pvCpuVAddr); 142 KFreeWrapper(pvCpuVAddr);
159#endif 143#endif
@@ -305,7 +289,7 @@ OSGetSubMemHandle(IMG_HANDLE hOSMemHandle,
305 289
306 eError = PVRMMapRegisterArea(psLinuxMemArea); 290 eError = PVRMMapRegisterArea(psLinuxMemArea);
307 if(eError != PVRSRV_OK) 291 if(eError != PVRSRV_OK)
308 { 292 {
309 goto failed_register_area; 293 goto failed_register_area;
310 } 294 }
311 295
@@ -524,6 +508,25 @@ IMG_VOID OSSleepms(IMG_UINT32 ui32Timems)
524} 508}
525 509
526 510
511
512IMG_HANDLE OSFuncHighResTimerCreate(IMG_VOID)
513{
514
515 return (IMG_HANDLE) 1;
516}
517
518
519IMG_UINT32 OSFuncHighResTimerGetus(IMG_HANDLE hTimer)
520{
521 return (IMG_UINT32) jiffies_to_usecs(jiffies);
522}
523
524
525IMG_VOID OSFuncHighResTimerDestroy(IMG_HANDLE hTimer)
526{
527 PVR_UNREFERENCED_PARAMETER(hTimer);
528}
529
527IMG_UINT32 OSGetCurrentProcessIDKM(IMG_VOID) 530IMG_UINT32 OSGetCurrentProcessIDKM(IMG_VOID)
528{ 531{
529 if (in_interrupt()) 532 if (in_interrupt())
@@ -1002,7 +1005,7 @@ PVRSRV_ERROR OSUnlockResource (PVRSRV_RESOURCE *psResource, IMG_UINT32 ui32ID)
1002 if(psResource->ui32ID == ui32ID) 1005 if(psResource->ui32ID == ui32ID)
1003 { 1006 {
1004 psResource->ui32ID = 0; 1007 psResource->ui32ID = 0;
1005 smp_mb(); 1008 smp_mb();
1006 *pui32Access = 0; 1009 *pui32Access = 0;
1007 } 1010 }
1008 else 1011 else
@@ -1032,6 +1035,18 @@ IMG_BOOL OSIsResourceLocked (PVRSRV_RESOURCE *psResource, IMG_UINT32 ui32ID)
1032} 1035}
1033 1036
1034 1037
1038#if !defined(SYS_CUSTOM_POWERLOCK_WRAP)
1039PVRSRV_ERROR OSPowerLockWrap (IMG_VOID)
1040{
1041 return PVRSRV_OK;
1042}
1043
1044IMG_VOID OSPowerLockUnwrap (IMG_VOID)
1045{
1046}
1047#endif
1048
1049
1035IMG_CPU_PHYADDR OSMapLinToCPUPhys(IMG_HANDLE hOSMemHandle, 1050IMG_CPU_PHYADDR OSMapLinToCPUPhys(IMG_HANDLE hOSMemHandle,
1036 IMG_VOID *pvLinAddr) 1051 IMG_VOID *pvLinAddr)
1037{ 1052{
@@ -1382,9 +1397,9 @@ PVRSRV_ERROR OSBaseAllocContigMemory(IMG_UINT32 ui32Size, IMG_CPU_VIRTADDR *pvLi
1382 IMG_VOID *pvKernLinAddr; 1397 IMG_VOID *pvKernLinAddr;
1383 1398
1384#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS) 1399#if defined(DEBUG_LINUX_MEMORY_ALLOCATIONS)
1385 pvKernLinAddr = _KMallocWrapper(ui32Size, __FILE__, __LINE__); 1400 pvKernLinAddr = _KMallocWrapper(ui32Size, GFP_KERNEL, __FILE__, __LINE__);
1386#else 1401#else
1387 pvKernLinAddr = KMallocWrapper(ui32Size); 1402 pvKernLinAddr = KMallocWrapper(ui32Size, GFP_KERNEL);
1388#endif 1403#endif
1389 if (!pvKernLinAddr) 1404 if (!pvKernLinAddr)
1390 { 1405 {
@@ -1952,7 +1967,11 @@ PVRSRV_ERROR OSDisableTimer (IMG_HANDLE hTimer)
1952} 1967}
1953 1968
1954 1969
1955PVRSRV_ERROR OSEventObjectCreate(const IMG_CHAR *pszName, PVRSRV_EVENTOBJECT *psEventObject) 1970#if defined (SUPPORT_SID_INTERFACE)
1971PVRSRV_ERROR OSEventObjectCreateKM(const IMG_CHAR *pszName, PVRSRV_EVENTOBJECT_KM *psEventObject)
1972#else
1973PVRSRV_ERROR OSEventObjectCreateKM(const IMG_CHAR *pszName, PVRSRV_EVENTOBJECT *psEventObject)
1974#endif
1956{ 1975{
1957 1976
1958 PVRSRV_ERROR eError = PVRSRV_OK; 1977 PVRSRV_ERROR eError = PVRSRV_OK;
@@ -1968,7 +1987,11 @@ PVRSRV_ERROR OSEventObjectCreate(const IMG_CHAR *pszName, PVRSRV_EVENTOBJECT *ps
1968 { 1987 {
1969 1988
1970 static IMG_UINT16 ui16NameIndex = 0; 1989 static IMG_UINT16 ui16NameIndex = 0;
1990#if defined (SUPPORT_SID_INTERFACE)
1991 snprintf(psEventObject->szName, EVENTOBJNAME_MAXLENGTH, "PVRSRV_EVENTOBJECT_KM_%d", ui16NameIndex++);
1992#else
1971 snprintf(psEventObject->szName, EVENTOBJNAME_MAXLENGTH, "PVRSRV_EVENTOBJECT_%d", ui16NameIndex++); 1993 snprintf(psEventObject->szName, EVENTOBJNAME_MAXLENGTH, "PVRSRV_EVENTOBJECT_%d", ui16NameIndex++);
1994#endif
1972 } 1995 }
1973 1996
1974 if(LinuxEventObjectListCreate(&psEventObject->hOSEventKM) != PVRSRV_OK) 1997 if(LinuxEventObjectListCreate(&psEventObject->hOSEventKM) != PVRSRV_OK)
@@ -1979,7 +2002,7 @@ PVRSRV_ERROR OSEventObjectCreate(const IMG_CHAR *pszName, PVRSRV_EVENTOBJECT *ps
1979 } 2002 }
1980 else 2003 else
1981 { 2004 {
1982 PVR_DPF((PVR_DBG_ERROR, "OSEventObjectCreate: psEventObject is not a valid pointer")); 2005 PVR_DPF((PVR_DBG_ERROR, "OSEventObjectCreateKM: psEventObject is not a valid pointer"));
1983 eError = PVRSRV_ERROR_UNABLE_TO_CREATE_EVENT; 2006 eError = PVRSRV_ERROR_UNABLE_TO_CREATE_EVENT;
1984 } 2007 }
1985 2008
@@ -1988,7 +2011,11 @@ PVRSRV_ERROR OSEventObjectCreate(const IMG_CHAR *pszName, PVRSRV_EVENTOBJECT *ps
1988} 2011}
1989 2012
1990 2013
1991PVRSRV_ERROR OSEventObjectDestroy(PVRSRV_EVENTOBJECT *psEventObject) 2014#if defined (SUPPORT_SID_INTERFACE)
2015PVRSRV_ERROR OSEventObjectDestroyKM(PVRSRV_EVENTOBJECT_KM *psEventObject)
2016#else
2017PVRSRV_ERROR OSEventObjectDestroyKM(PVRSRV_EVENTOBJECT *psEventObject)
2018#endif
1992{ 2019{
1993 PVRSRV_ERROR eError = PVRSRV_OK; 2020 PVRSRV_ERROR eError = PVRSRV_OK;
1994 2021
@@ -2000,20 +2027,20 @@ PVRSRV_ERROR OSEventObjectDestroy(PVRSRV_EVENTOBJECT *psEventObject)
2000 } 2027 }
2001 else 2028 else
2002 { 2029 {
2003 PVR_DPF((PVR_DBG_ERROR, "OSEventObjectDestroy: hOSEventKM is not a valid pointer")); 2030 PVR_DPF((PVR_DBG_ERROR, "OSEventObjectDestroyKM: hOSEventKM is not a valid pointer"));
2004 eError = PVRSRV_ERROR_INVALID_PARAMS; 2031 eError = PVRSRV_ERROR_INVALID_PARAMS;
2005 } 2032 }
2006 } 2033 }
2007 else 2034 else
2008 { 2035 {
2009 PVR_DPF((PVR_DBG_ERROR, "OSEventObjectDestroy: psEventObject is not a valid pointer")); 2036 PVR_DPF((PVR_DBG_ERROR, "OSEventObjectDestroyKM: psEventObject is not a valid pointer"));
2010 eError = PVRSRV_ERROR_INVALID_PARAMS; 2037 eError = PVRSRV_ERROR_INVALID_PARAMS;
2011 } 2038 }
2012 2039
2013 return eError; 2040 return eError;
2014} 2041}
2015 2042
2016PVRSRV_ERROR OSEventObjectWait(IMG_HANDLE hOSEventKM) 2043PVRSRV_ERROR OSEventObjectWaitKM(IMG_HANDLE hOSEventKM)
2017{ 2044{
2018 PVRSRV_ERROR eError; 2045 PVRSRV_ERROR eError;
2019 2046
@@ -2023,14 +2050,18 @@ PVRSRV_ERROR OSEventObjectWait(IMG_HANDLE hOSEventKM)
2023 } 2050 }
2024 else 2051 else
2025 { 2052 {
2026 PVR_DPF((PVR_DBG_ERROR, "OSEventObjectWait: hOSEventKM is not a valid handle")); 2053 PVR_DPF((PVR_DBG_ERROR, "OSEventObjectWaitKM: hOSEventKM is not a valid handle"));
2027 eError = PVRSRV_ERROR_INVALID_PARAMS; 2054 eError = PVRSRV_ERROR_INVALID_PARAMS;
2028 } 2055 }
2029 2056
2030 return eError; 2057 return eError;
2031} 2058}
2032 2059
2033PVRSRV_ERROR OSEventObjectOpen(PVRSRV_EVENTOBJECT *psEventObject, 2060#if defined (SUPPORT_SID_INTERFACE)
2061PVRSRV_ERROR OSEventObjectOpenKM(PVRSRV_EVENTOBJECT_KM *psEventObject,
2062#else
2063PVRSRV_ERROR OSEventObjectOpenKM(PVRSRV_EVENTOBJECT *psEventObject,
2064#endif
2034 IMG_HANDLE *phOSEvent) 2065 IMG_HANDLE *phOSEvent)
2035{ 2066{
2036 PVRSRV_ERROR eError = PVRSRV_OK; 2067 PVRSRV_ERROR eError = PVRSRV_OK;
@@ -2046,14 +2077,18 @@ PVRSRV_ERROR OSEventObjectOpen(PVRSRV_EVENTOBJECT *psEventObject,
2046 } 2077 }
2047 else 2078 else
2048 { 2079 {
2049 PVR_DPF((PVR_DBG_ERROR, "OSEventObjectCreate: psEventObject is not a valid pointer")); 2080 PVR_DPF((PVR_DBG_ERROR, "OSEventObjectCreateKM: psEventObject is not a valid pointer"));
2050 eError = PVRSRV_ERROR_INVALID_PARAMS; 2081 eError = PVRSRV_ERROR_INVALID_PARAMS;
2051 } 2082 }
2052 2083
2053 return eError; 2084 return eError;
2054} 2085}
2055 2086
2056PVRSRV_ERROR OSEventObjectClose(PVRSRV_EVENTOBJECT *psEventObject, 2087#if defined (SUPPORT_SID_INTERFACE)
2088PVRSRV_ERROR OSEventObjectCloseKM(PVRSRV_EVENTOBJECT_KM *psEventObject,
2089#else
2090PVRSRV_ERROR OSEventObjectCloseKM(PVRSRV_EVENTOBJECT *psEventObject,
2091#endif
2057 IMG_HANDLE hOSEventKM) 2092 IMG_HANDLE hOSEventKM)
2058{ 2093{
2059 PVRSRV_ERROR eError = PVRSRV_OK; 2094 PVRSRV_ERROR eError = PVRSRV_OK;
@@ -2069,7 +2104,7 @@ PVRSRV_ERROR OSEventObjectClose(PVRSRV_EVENTOBJECT *psEventObject,
2069 } 2104 }
2070 else 2105 else
2071 { 2106 {
2072 PVR_DPF((PVR_DBG_ERROR, "OSEventObjectDestroy: psEventObject is not a valid pointer")); 2107 PVR_DPF((PVR_DBG_ERROR, "OSEventObjectDestroyKM: psEventObject is not a valid pointer"));
2073 eError = PVRSRV_ERROR_INVALID_PARAMS; 2108 eError = PVRSRV_ERROR_INVALID_PARAMS;
2074 } 2109 }
2075 2110
@@ -2077,7 +2112,7 @@ PVRSRV_ERROR OSEventObjectClose(PVRSRV_EVENTOBJECT *psEventObject,
2077 2112
2078} 2113}
2079 2114
2080PVRSRV_ERROR OSEventObjectSignal(IMG_HANDLE hOSEventKM) 2115PVRSRV_ERROR OSEventObjectSignalKM(IMG_HANDLE hOSEventKM)
2081{ 2116{
2082 PVRSRV_ERROR eError; 2117 PVRSRV_ERROR eError;
2083 2118
@@ -2087,7 +2122,7 @@ PVRSRV_ERROR OSEventObjectSignal(IMG_HANDLE hOSEventKM)
2087 } 2122 }
2088 else 2123 else
2089 { 2124 {
2090 PVR_DPF((PVR_DBG_ERROR, "OSEventObjectSignal: hOSEventKM is not a valid handle")); 2125 PVR_DPF((PVR_DBG_ERROR, "OSEventObjectSignalKM: hOSEventKM is not a valid handle"));
2091 eError = PVRSRV_ERROR_INVALID_PARAMS; 2126 eError = PVRSRV_ERROR_INVALID_PARAMS;
2092 } 2127 }
2093 2128
@@ -2684,7 +2719,7 @@ IMG_BOOL CheckExecuteCacheOp(IMG_HANDLE hOSMemHandle,
2684 psLinuxMemArea = psLinuxMemArea->uData.sSubAlloc.psParentLinuxMemArea; 2719 psLinuxMemArea = psLinuxMemArea->uData.sSubAlloc.psParentLinuxMemArea;
2685 } 2720 }
2686 2721
2687 2722
2688 PVR_ASSERT(psLinuxMemArea->eAreaType != LINUX_MEM_AREA_SUB_ALLOC); 2723 PVR_ASSERT(psLinuxMemArea->eAreaType != LINUX_MEM_AREA_SUB_ALLOC);
2689 2724
2690 switch(psLinuxMemArea->eAreaType) 2725 switch(psLinuxMemArea->eAreaType)
@@ -2695,7 +2730,7 @@ IMG_BOOL CheckExecuteCacheOp(IMG_HANDLE hOSMemHandle,
2695 { 2730 {
2696 pvMinVAddr = psLinuxMemArea->uData.sVmalloc.pvVmallocAddress + ui32AreaOffset; 2731 pvMinVAddr = psLinuxMemArea->uData.sVmalloc.pvVmallocAddress + ui32AreaOffset;
2697 2732
2698 2733
2699 if(pvRangeAddrStart < pvMinVAddr) 2734 if(pvRangeAddrStart < pvMinVAddr)
2700 goto err_blocked; 2735 goto err_blocked;
2701 2736
@@ -2703,8 +2738,8 @@ IMG_BOOL CheckExecuteCacheOp(IMG_HANDLE hOSMemHandle,
2703 } 2738 }
2704 else 2739 else
2705 { 2740 {
2706 2741
2707 2742
2708 2743
2709 pvMinVAddr = FindMMapBaseVAddr(psMMapOffsetStructList, 2744 pvMinVAddr = FindMMapBaseVAddr(psMMapOffsetStructList,
2710 pvRangeAddrStart, ui32Length); 2745 pvRangeAddrStart, ui32Length);
@@ -2714,21 +2749,21 @@ IMG_BOOL CheckExecuteCacheOp(IMG_HANDLE hOSMemHandle,
2714 pfnInnerCacheOp(pvRangeAddrStart, pvRangeAddrStart + ui32Length); 2749 pfnInnerCacheOp(pvRangeAddrStart, pvRangeAddrStart + ui32Length);
2715 2750
2716#if defined(CONFIG_OUTER_CACHE) 2751#if defined(CONFIG_OUTER_CACHE)
2717 2752
2718 pvRangeAddrStart = psLinuxMemArea->uData.sVmalloc.pvVmallocAddress + 2753 pvRangeAddrStart = psLinuxMemArea->uData.sVmalloc.pvVmallocAddress +
2719 (ui32AreaOffset & PAGE_MASK) + (pvRangeAddrStart - pvMinVAddr); 2754 (ui32AreaOffset & PAGE_MASK) + (pvRangeAddrStart - pvMinVAddr);
2720 } 2755 }
2721 2756
2722 pfnMemAreaToPhys = VMallocAreaToPhys; 2757 pfnMemAreaToPhys = VMallocAreaToPhys;
2723#else 2758#else
2724 } 2759 }
2725#endif 2760#endif
2726 break; 2761 break;
2727 } 2762 }
2728 2763
2729 case LINUX_MEM_AREA_EXTERNAL_KV: 2764 case LINUX_MEM_AREA_EXTERNAL_KV:
2730 { 2765 {
2731 2766
2732 if (psLinuxMemArea->uData.sExternalKV.bPhysContig == IMG_TRUE) 2767 if (psLinuxMemArea->uData.sExternalKV.bPhysContig == IMG_TRUE)
2733 { 2768 {
2734 PVR_DPF((PVR_DBG_WARNING, "%s: Attempt to flush contiguous external memory", __func__)); 2769 PVR_DPF((PVR_DBG_WARNING, "%s: Attempt to flush contiguous external memory", __func__));
@@ -2736,7 +2771,7 @@ IMG_BOOL CheckExecuteCacheOp(IMG_HANDLE hOSMemHandle,
2736 goto err_blocked; 2771 goto err_blocked;
2737 } 2772 }
2738 2773
2739 2774
2740 if (psLinuxMemArea->uData.sExternalKV.pvExternalKV != IMG_NULL) 2775 if (psLinuxMemArea->uData.sExternalKV.pvExternalKV != IMG_NULL)
2741 { 2776 {
2742 PVR_DPF((PVR_DBG_WARNING, "%s: Attempt to flush external memory with a kernel virtual address", __func__)); 2777 PVR_DPF((PVR_DBG_WARNING, "%s: Attempt to flush external memory with a kernel virtual address", __func__));
@@ -2865,7 +2900,7 @@ IMG_BOOL OSFlushCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
2865 IMG_VOID *pvRangeAddrStart, 2900 IMG_VOID *pvRangeAddrStart,
2866 IMG_UINT32 ui32Length) 2901 IMG_UINT32 ui32Length)
2867{ 2902{
2868 2903
2869 return CheckExecuteCacheOp(hOSMemHandle, pvRangeAddrStart, ui32Length, 2904 return CheckExecuteCacheOp(hOSMemHandle, pvRangeAddrStart, ui32Length,
2870 x86_flush_cache_range, IMG_NULL); 2905 x86_flush_cache_range, IMG_NULL);
2871} 2906}
@@ -2874,7 +2909,7 @@ IMG_BOOL OSCleanCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
2874 IMG_VOID *pvRangeAddrStart, 2909 IMG_VOID *pvRangeAddrStart,
2875 IMG_UINT32 ui32Length) 2910 IMG_UINT32 ui32Length)
2876{ 2911{
2877 2912
2878 return CheckExecuteCacheOp(hOSMemHandle, pvRangeAddrStart, ui32Length, 2913 return CheckExecuteCacheOp(hOSMemHandle, pvRangeAddrStart, ui32Length,
2879 x86_flush_cache_range, IMG_NULL); 2914 x86_flush_cache_range, IMG_NULL);
2880} 2915}
@@ -2883,12 +2918,12 @@ IMG_BOOL OSInvalidateCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
2883 IMG_VOID *pvRangeAddrStart, 2918 IMG_VOID *pvRangeAddrStart,
2884 IMG_UINT32 ui32Length) 2919 IMG_UINT32 ui32Length)
2885{ 2920{
2886 2921
2887 return CheckExecuteCacheOp(hOSMemHandle, pvRangeAddrStart, ui32Length, 2922 return CheckExecuteCacheOp(hOSMemHandle, pvRangeAddrStart, ui32Length,
2888 x86_flush_cache_range, IMG_NULL); 2923 x86_flush_cache_range, IMG_NULL);
2889} 2924}
2890 2925
2891#else 2926#else
2892 2927
2893#if defined(__arm__) 2928#if defined(__arm__)
2894 2929
@@ -2900,7 +2935,7 @@ static void per_cpu_cache_flush(void *arg)
2900 2935
2901IMG_VOID OSCleanCPUCacheKM(IMG_VOID) 2936IMG_VOID OSCleanCPUCacheKM(IMG_VOID)
2902{ 2937{
2903 2938
2904 ON_EACH_CPU(per_cpu_cache_flush, NULL, 1); 2939 ON_EACH_CPU(per_cpu_cache_flush, NULL, 1);
2905#if defined(CONFIG_OUTER_CACHE) && !defined(PVR_NO_FULL_CACHE_OPS) 2940#if defined(CONFIG_OUTER_CACHE) && !defined(PVR_NO_FULL_CACHE_OPS)
2906 outer_clean_all(); 2941 outer_clean_all();
@@ -2939,18 +2974,18 @@ IMG_BOOL OSInvalidateCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
2939 dmac_inv_range, outer_inv_range); 2974 dmac_inv_range, outer_inv_range);
2940} 2975}
2941 2976
2942#else 2977#else
2943 2978
2944#if defined(__mips__) 2979#if defined(__mips__)
2945IMG_VOID OSCleanCPUCacheKM(IMG_VOID) 2980IMG_VOID OSCleanCPUCacheKM(IMG_VOID)
2946{ 2981{
2947 2982
2948 dma_cache_wback(0, 0x100000); 2983 dma_cache_wback(0, 0x100000);
2949} 2984}
2950 2985
2951IMG_VOID OSFlushCPUCacheKM(IMG_VOID) 2986IMG_VOID OSFlushCPUCacheKM(IMG_VOID)
2952{ 2987{
2953 2988
2954 dma_cache_wback_inv(0, 0x100000); 2989 dma_cache_wback_inv(0, 0x100000);
2955} 2990}
2956 2991
@@ -2978,15 +3013,15 @@ IMG_BOOL OSInvalidateCPUCacheRangeKM(IMG_HANDLE hOSMemHandle,
2978 return IMG_TRUE; 3013 return IMG_TRUE;
2979} 3014}
2980 3015
2981#else 3016#else
2982 3017
2983#error "Implement CPU cache flush/clean/invalidate primitives for this CPU!" 3018#error "Implement CPU cache flush/clean/invalidate primitives for this CPU!"
2984 3019
2985#endif 3020#endif
2986 3021
2987#endif 3022#endif
2988 3023
2989#endif 3024#endif
2990 3025
2991PVRSRV_ERROR PVROSFuncInit(IMG_VOID) 3026PVRSRV_ERROR PVROSFuncInit(IMG_VOID)
2992{ 3027{
@@ -2995,7 +3030,7 @@ PVRSRV_ERROR PVROSFuncInit(IMG_VOID)
2995 psTimerWorkQueue = create_workqueue("pvr_timer"); 3030 psTimerWorkQueue = create_workqueue("pvr_timer");
2996 if (psTimerWorkQueue == NULL) 3031 if (psTimerWorkQueue == NULL)
2997 { 3032 {
2998 PVR_DPF((PVR_DBG_ERROR, "%s: couldn't create timer workqueue", __FUNCTION__)); 3033 PVR_DPF((PVR_DBG_ERROR, "%s: couldn't create timer workqueue", __FUNCTION__));
2999 return PVRSRV_ERROR_UNABLE_TO_CREATE_THREAD; 3034 return PVRSRV_ERROR_UNABLE_TO_CREATE_THREAD;
3000 3035
3001 } 3036 }
diff --git a/drivers/gpu/pvr/osfunc.h b/drivers/gpu/pvr/osfunc.h
index dc209a04fac..6fdb795facd 100644
--- a/drivers/gpu/pvr/osfunc.h
+++ b/drivers/gpu/pvr/osfunc.h
@@ -406,15 +406,27 @@ IMG_CHAR* OSStringCopy(IMG_CHAR *pszDest, const IMG_CHAR *pszSrc);
406IMG_INT32 OSSNPrintf(IMG_CHAR *pStr, IMG_SIZE_T ui32Size, const IMG_CHAR *pszFormat, ...) IMG_FORMAT_PRINTF(3, 4); 406IMG_INT32 OSSNPrintf(IMG_CHAR *pStr, IMG_SIZE_T ui32Size, const IMG_CHAR *pszFormat, ...) IMG_FORMAT_PRINTF(3, 4);
407#define OSStringLength(pszString) strlen(pszString) 407#define OSStringLength(pszString) strlen(pszString)
408 408
409PVRSRV_ERROR OSEventObjectCreate(const IMG_CHAR *pszName, 409#if defined (SUPPORT_SID_INTERFACE)
410PVRSRV_ERROR OSEventObjectCreateKM(const IMG_CHAR *pszName,
411 PVRSRV_EVENTOBJECT_KM *psEventObject);
412PVRSRV_ERROR OSEventObjectDestroyKM(PVRSRV_EVENTOBJECT_KM *psEventObject);
413PVRSRV_ERROR OSEventObjectSignalKM(IMG_HANDLE hOSEventKM);
414PVRSRV_ERROR OSEventObjectWaitKM(IMG_HANDLE hOSEventKM);
415PVRSRV_ERROR OSEventObjectOpenKM(PVRSRV_EVENTOBJECT_KM *psEventObject,
416 IMG_HANDLE *phOSEvent);
417PVRSRV_ERROR OSEventObjectCloseKM(PVRSRV_EVENTOBJECT_KM *psEventObject,
418 IMG_HANDLE hOSEventKM);
419#else
420PVRSRV_ERROR OSEventObjectCreateKM(const IMG_CHAR *pszName,
410 PVRSRV_EVENTOBJECT *psEventObject); 421 PVRSRV_EVENTOBJECT *psEventObject);
411PVRSRV_ERROR OSEventObjectDestroy(PVRSRV_EVENTOBJECT *psEventObject); 422PVRSRV_ERROR OSEventObjectDestroyKM(PVRSRV_EVENTOBJECT *psEventObject);
412PVRSRV_ERROR OSEventObjectSignal(IMG_HANDLE hOSEventKM); 423PVRSRV_ERROR OSEventObjectSignalKM(IMG_HANDLE hOSEventKM);
413PVRSRV_ERROR OSEventObjectWait(IMG_HANDLE hOSEventKM); 424PVRSRV_ERROR OSEventObjectWaitKM(IMG_HANDLE hOSEventKM);
414PVRSRV_ERROR OSEventObjectOpen(PVRSRV_EVENTOBJECT *psEventObject, 425PVRSRV_ERROR OSEventObjectOpenKM(PVRSRV_EVENTOBJECT *psEventObject,
415 IMG_HANDLE *phOSEvent); 426 IMG_HANDLE *phOSEvent);
416PVRSRV_ERROR OSEventObjectClose(PVRSRV_EVENTOBJECT *psEventObject, 427PVRSRV_ERROR OSEventObjectCloseKM(PVRSRV_EVENTOBJECT *psEventObject,
417 IMG_HANDLE hOSEventKM); 428 IMG_HANDLE hOSEventKM);
429#endif
418 430
419 431
420PVRSRV_ERROR OSBaseAllocContigMemory(IMG_SIZE_T ui32Size, IMG_CPU_VIRTADDR *pLinAddr, IMG_CPU_PHYADDR *pPhysAddr); 432PVRSRV_ERROR OSBaseAllocContigMemory(IMG_SIZE_T ui32Size, IMG_CPU_VIRTADDR *pLinAddr, IMG_CPU_PHYADDR *pPhysAddr);
@@ -445,14 +457,24 @@ PVRSRV_ERROR OSCreateResource(PVRSRV_RESOURCE *psResource);
445PVRSRV_ERROR OSDestroyResource(PVRSRV_RESOURCE *psResource); 457PVRSRV_ERROR OSDestroyResource(PVRSRV_RESOURCE *psResource);
446IMG_VOID OSBreakResourceLock(PVRSRV_RESOURCE *psResource, IMG_UINT32 ui32ID); 458IMG_VOID OSBreakResourceLock(PVRSRV_RESOURCE *psResource, IMG_UINT32 ui32ID);
447 459
460#if defined(SYS_CUSTOM_POWERLOCK_WRAP)
461#define OSPowerLockWrap SysPowerLockWrap
462#define OSPowerLockUnwrap SysPowerLockUnwrap
463#else
464PVRSRV_ERROR OSPowerLockWrap(IMG_VOID);
448 465
466IMG_VOID OSPowerLockUnwrap(IMG_VOID);
467#endif
449 468
469
450IMG_VOID OSWaitus(IMG_UINT32 ui32Timeus); 470IMG_VOID OSWaitus(IMG_UINT32 ui32Timeus);
451 471
452 472
453IMG_VOID OSSleepms(IMG_UINT32 ui32Timems); 473IMG_VOID OSSleepms(IMG_UINT32 ui32Timems);
454 474
455 475IMG_HANDLE OSFuncHighResTimerCreate(IMG_VOID);
476IMG_UINT32 OSFuncHighResTimerGetus(IMG_HANDLE hTimer);
477IMG_VOID OSFuncHighResTimerDestroy(IMG_HANDLE hTimer);
456IMG_VOID OSReleaseThreadQuanta(IMG_VOID); 478IMG_VOID OSReleaseThreadQuanta(IMG_VOID);
457IMG_UINT32 OSPCIReadDword(IMG_UINT32 ui32Bus, IMG_UINT32 ui32Dev, IMG_UINT32 ui32Func, IMG_UINT32 ui32Reg); 479IMG_UINT32 OSPCIReadDword(IMG_UINT32 ui32Bus, IMG_UINT32 ui32Dev, IMG_UINT32 ui32Func, IMG_UINT32 ui32Reg);
458IMG_VOID OSPCIWriteDword(IMG_UINT32 ui32Bus, IMG_UINT32 ui32Dev, IMG_UINT32 ui32Func, IMG_UINT32 ui32Reg, IMG_UINT32 ui32Value); 480IMG_VOID OSPCIWriteDword(IMG_UINT32 ui32Bus, IMG_UINT32 ui32Dev, IMG_UINT32 ui32Func, IMG_UINT32 ui32Reg, IMG_UINT32 ui32Value);
@@ -476,7 +498,7 @@ typedef enum _HOST_PCI_INIT_FLAGS_
476{ 498{
477 HOST_PCI_INIT_FLAG_BUS_MASTER = 0x00000001, 499 HOST_PCI_INIT_FLAG_BUS_MASTER = 0x00000001,
478 HOST_PCI_INIT_FLAG_MSI = 0x00000002, 500 HOST_PCI_INIT_FLAG_MSI = 0x00000002,
479 HOST_PCI_INIT_FLAG_FORCE_I32 = 0x7fffffff 501 HOST_PCI_INIT_FLAG_FORCE_I32 = 0x7fffffff
480} HOST_PCI_INIT_FLAGS; 502} HOST_PCI_INIT_FLAGS;
481 503
482struct _PVRSRV_PCI_DEV_OPAQUE_STRUCT_; 504struct _PVRSRV_PCI_DEV_OPAQUE_STRUCT_;
diff --git a/drivers/gpu/pvr/pdump_common.c b/drivers/gpu/pvr/pdump_common.c
index c2c0dada01f..10f68171361 100644
--- a/drivers/gpu/pvr/pdump_common.c
+++ b/drivers/gpu/pvr/pdump_common.c
@@ -28,9 +28,6 @@
28#include <stdarg.h> 28#include <stdarg.h>
29 29
30#include "services_headers.h" 30#include "services_headers.h"
31#if defined(SUPPORT_SGX)
32#include "sgxdefs.h"
33#endif
34#include "perproc.h" 31#include "perproc.h"
35 32
36#include "pdump_km.h" 33#include "pdump_km.h"
@@ -46,8 +43,6 @@
46#define PDUMP_DBG(a) 43#define PDUMP_DBG(a)
47#endif 44#endif
48 45
49#define PDUMP_DATAMASTER_PIXEL (1)
50#define PDUMP_DATAMASTER_EDM (3)
51 46
52#define PTR_PLUS(t, p, x) ((t)(((IMG_CHAR *)(p)) + (x))) 47#define PTR_PLUS(t, p, x) ((t)(((IMG_CHAR *)(p)) + (x)))
53#define VPTR_PLUS(p, x) PTR_PLUS(IMG_VOID *, p, x) 48#define VPTR_PLUS(p, x) PTR_PLUS(IMG_VOID *, p, x)
@@ -68,6 +63,7 @@ static INLINE
68IMG_BOOL _PDumpIsPersistent(IMG_VOID) 63IMG_BOOL _PDumpIsPersistent(IMG_VOID)
69{ 64{
70 PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData(); 65 PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData();
66
71 if(psPerProc == IMG_NULL) 67 if(psPerProc == IMG_NULL)
72 { 68 {
73 69
@@ -83,12 +79,12 @@ IMG_BOOL _PDumpIsProcessActive(IMG_VOID)
83 PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData(); 79 PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData();
84 if(psPerProc == IMG_NULL) 80 if(psPerProc == IMG_NULL)
85 { 81 {
86 82
87 return IMG_TRUE; 83 return IMG_TRUE;
88 } 84 }
89 return psPerProc->bPDumpActive; 85 return psPerProc->bPDumpActive;
90} 86}
91#endif 87#endif
92 88
93#if defined(PDUMP_DEBUG_OUTFILES) 89#if defined(PDUMP_DEBUG_OUTFILES)
94static INLINE 90static INLINE
@@ -102,7 +98,7 @@ IMG_UINT32 _PDumpGetPID(IMG_VOID)
102 } 98 }
103 return psPerProc->ui32PID; 99 return psPerProc->ui32PID;
104} 100}
105#endif 101#endif
106 102
107static IMG_VOID *GetTempBuffer(IMG_VOID) 103static IMG_VOID *GetTempBuffer(IMG_VOID)
108{ 104{
@@ -192,7 +188,6 @@ PVRSRV_ERROR PDumpSetFrameKM(IMG_UINT32 ui32Frame)
192#endif 188#endif
193} 189}
194 190
195
196PVRSRV_ERROR PDumpRegWithFlagsKM(IMG_CHAR *pszPDumpRegName, 191PVRSRV_ERROR PDumpRegWithFlagsKM(IMG_CHAR *pszPDumpRegName,
197 IMG_UINT32 ui32Reg, 192 IMG_UINT32 ui32Reg,
198 IMG_UINT32 ui32Data, 193 IMG_UINT32 ui32Data,
@@ -224,7 +219,8 @@ PVRSRV_ERROR PDumpRegPolWithFlagsKM(IMG_CHAR *pszPDumpRegName,
224 IMG_UINT32 ui32RegAddr, 219 IMG_UINT32 ui32RegAddr,
225 IMG_UINT32 ui32RegValue, 220 IMG_UINT32 ui32RegValue,
226 IMG_UINT32 ui32Mask, 221 IMG_UINT32 ui32Mask,
227 IMG_UINT32 ui32Flags) 222 IMG_UINT32 ui32Flags,
223 PDUMP_POLL_OPERATOR eOperator)
228{ 224{
229 225
230 #define POLL_DELAY 1000U 226 #define POLL_DELAY 1000U
@@ -260,7 +256,7 @@ PVRSRV_ERROR PDumpRegPolWithFlagsKM(IMG_CHAR *pszPDumpRegName,
260 256
261 eErr = PDumpOSBufprintf(hScript, ui32MaxLen, "POL :%s:0x%08X 0x%08X 0x%08X %d %u %d\r\n", 257 eErr = PDumpOSBufprintf(hScript, ui32MaxLen, "POL :%s:0x%08X 0x%08X 0x%08X %d %u %d\r\n",
262 pszPDumpRegName, ui32RegAddr, ui32RegValue, 258 pszPDumpRegName, ui32RegAddr, ui32RegValue,
263 ui32Mask, 0, ui32PollCount, POLL_DELAY); 259 ui32Mask, eOperator, ui32PollCount, POLL_DELAY);
264 if(eErr != PVRSRV_OK) 260 if(eErr != PVRSRV_OK)
265 { 261 {
266 return eErr; 262 return eErr;
@@ -271,9 +267,9 @@ PVRSRV_ERROR PDumpRegPolWithFlagsKM(IMG_CHAR *pszPDumpRegName,
271} 267}
272 268
273 269
274PVRSRV_ERROR PDumpRegPolKM(IMG_CHAR *pszPDumpRegName, IMG_UINT32 ui32RegAddr, IMG_UINT32 ui32RegValue, IMG_UINT32 ui32Mask) 270PVRSRV_ERROR PDumpRegPolKM(IMG_CHAR *pszPDumpRegName, IMG_UINT32 ui32RegAddr, IMG_UINT32 ui32RegValue, IMG_UINT32 ui32Mask, PDUMP_POLL_OPERATOR eOperator)
275{ 271{
276 return PDumpRegPolWithFlagsKM(pszPDumpRegName, ui32RegAddr, ui32RegValue, ui32Mask, PDUMP_FLAGS_CONTINUOUS); 272 return PDumpRegPolWithFlagsKM(pszPDumpRegName, ui32RegAddr, ui32RegValue, ui32Mask, PDUMP_FLAGS_CONTINUOUS, eOperator);
277} 273}
278 274
279PVRSRV_ERROR PDumpMallocPages (PVRSRV_DEVICE_IDENTIFIER *psDevID, 275PVRSRV_ERROR PDumpMallocPages (PVRSRV_DEVICE_IDENTIFIER *psDevID,
@@ -295,7 +291,7 @@ PVRSRV_ERROR PDumpMallocPages (PVRSRV_DEVICE_IDENTIFIER *psDevID,
295 291
296 PDUMP_GET_SCRIPT_STRING(); 292 PDUMP_GET_SCRIPT_STRING();
297#if defined(SUPPORT_PDUMP_MULTI_PROCESS) 293#if defined(SUPPORT_PDUMP_MULTI_PROCESS)
298 294
299 ui32Flags |= ( _PDumpIsPersistent() || bShared ) ? PDUMP_FLAGS_PERSISTENT : 0; 295 ui32Flags |= ( _PDumpIsPersistent() || bShared ) ? PDUMP_FLAGS_PERSISTENT : 0;
300#else 296#else
301 PVR_UNREFERENCED_PARAMETER(bShared); 297 PVR_UNREFERENCED_PARAMETER(bShared);
@@ -366,13 +362,14 @@ PVRSRV_ERROR PDumpMallocPages (PVRSRV_DEVICE_IDENTIFIER *psDevID,
366 return PVRSRV_OK; 362 return PVRSRV_OK;
367} 363}
368 364
365
369PVRSRV_ERROR PDumpMallocPageTable (PVRSRV_DEVICE_IDENTIFIER *psDevId, 366PVRSRV_ERROR PDumpMallocPageTable (PVRSRV_DEVICE_IDENTIFIER *psDevId,
370 IMG_HANDLE hOSMemHandle, 367 IMG_HANDLE hOSMemHandle,
371 IMG_UINT32 ui32Offset, 368 IMG_UINT32 ui32Offset,
372 IMG_CPU_VIRTADDR pvLinAddr, 369 IMG_CPU_VIRTADDR pvLinAddr,
373 IMG_UINT32 ui32PTSize, 370 IMG_UINT32 ui32PTSize,
374 IMG_UINT32 ui32Flags, 371 IMG_UINT32 ui32Flags,
375 IMG_HANDLE hUniqueTag) 372 IMG_HANDLE hUniqueTag)
376{ 373{
377 PVRSRV_ERROR eErr; 374 PVRSRV_ERROR eErr;
378 IMG_DEV_PHYADDR sDevPAddr; 375 IMG_DEV_PHYADDR sDevPAddr;
@@ -382,7 +379,7 @@ PVRSRV_ERROR PDumpMallocPageTable (PVRSRV_DEVICE_IDENTIFIER *psDevId,
382 PVR_ASSERT(((IMG_UINTPTR_T)pvLinAddr & (ui32PTSize - 1)) == 0); 379 PVR_ASSERT(((IMG_UINTPTR_T)pvLinAddr & (ui32PTSize - 1)) == 0);
383 ui32Flags |= PDUMP_FLAGS_CONTINUOUS; 380 ui32Flags |= PDUMP_FLAGS_CONTINUOUS;
384 ui32Flags |= ( _PDumpIsPersistent() ) ? PDUMP_FLAGS_PERSISTENT : 0; 381 ui32Flags |= ( _PDumpIsPersistent() ) ? PDUMP_FLAGS_PERSISTENT : 0;
385 382
386 383
387 384
388 eErr = PDumpOSBufprintf(hScript, 385 eErr = PDumpOSBufprintf(hScript,
@@ -458,10 +455,10 @@ PVRSRV_ERROR PDumpFreePages (BM_HEAP *psBMHeap,
458 } 455 }
459 456
460#if defined(SUPPORT_PDUMP_MULTI_PROCESS) 457#if defined(SUPPORT_PDUMP_MULTI_PROCESS)
461 458
462 { 459 {
463 PVRSRV_DEVICE_NODE *psDeviceNode = psBMHeap->pBMContext->psDeviceNode; 460 PVRSRV_DEVICE_NODE *psDeviceNode = psBMHeap->pBMContext->psDeviceNode;
464 461
465 if( psDeviceNode->pfnMMUIsHeapShared(psBMHeap->pMMUHeap) ) 462 if( psDeviceNode->pfnMMUIsHeapShared(psBMHeap->pMMUHeap) )
466 { 463 {
467 ui32Flags |= PDUMP_FLAGS_PERSISTENT; 464 ui32Flags |= PDUMP_FLAGS_PERSISTENT;
@@ -478,15 +475,16 @@ PVRSRV_ERROR PDumpFreePages (BM_HEAP *psBMHeap,
478 if (!bInterleaved || (ui32PageCounter % 2) == 0) 475 if (!bInterleaved || (ui32PageCounter % 2) == 0)
479 { 476 {
480 sDevPAddr = psDeviceNode->pfnMMUGetPhysPageAddr(psBMHeap->pMMUHeap, sDevVAddr); 477 sDevPAddr = psDeviceNode->pfnMMUGetPhysPageAddr(psBMHeap->pMMUHeap, sDevVAddr);
478
479 PVR_ASSERT(sDevPAddr.uiAddr != 0)
480
481 eErr = PDumpOSBufprintf(hScript, ui32MaxLen, "FREE :%s:PA_%08X%08X\r\n",
482 psDeviceNode->sDevId.pszPDumpDevName, (IMG_UINT32)(IMG_UINTPTR_T)hUniqueTag, sDevPAddr.uiAddr);
483 if(eErr != PVRSRV_OK)
481 { 484 {
482 eErr = PDumpOSBufprintf(hScript, ui32MaxLen, "FREE :%s:PA_%08X%08X\r\n", 485 return eErr;
483 psDeviceNode->sDevId.pszPDumpDevName, (IMG_UINT32)(IMG_UINTPTR_T)hUniqueTag, sDevPAddr.uiAddr);
484 if(eErr != PVRSRV_OK)
485 {
486 return eErr;
487 }
488 PDumpOSWriteString2(hScript, ui32Flags);
489 } 486 }
487 PDumpOSWriteString2(hScript, ui32Flags);
490 } 488 }
491 else 489 else
492 { 490 {
@@ -652,6 +650,12 @@ PVRSRV_ERROR PDumpMemPolKM(PVRSRV_KERNEL_MEM_INFO *psMemInfo,
652 PDUMP_MMU_ATTRIB *psMMUAttrib; 650 PDUMP_MMU_ATTRIB *psMMUAttrib;
653 651
654 PDUMP_GET_SCRIPT_STRING(); 652 PDUMP_GET_SCRIPT_STRING();
653
654 if (PDumpOSIsSuspended())
655 {
656 return PVRSRV_OK;
657 }
658
655 if ( _PDumpIsPersistent() ) 659 if ( _PDumpIsPersistent() )
656 { 660 {
657 661
@@ -659,7 +663,7 @@ PVRSRV_ERROR PDumpMemPolKM(PVRSRV_KERNEL_MEM_INFO *psMemInfo,
659 } 663 }
660 664
661 665
662 PVR_ASSERT((ui32Offset + sizeof(IMG_UINT32)) <= psMemInfo->ui32AllocSize); 666 PVR_ASSERT((ui32Offset + sizeof(IMG_UINT32)) <= psMemInfo->uAllocSize);
663 667
664 psMMUAttrib = ((BM_BUF*)psMemInfo->sMemBlk.hBuffer)->pMapping->pBMHeap->psMMUAttrib; 668 psMMUAttrib = ((BM_BUF*)psMemInfo->sMemBlk.hBuffer)->pMapping->pBMHeap->psMMUAttrib;
665 669
@@ -750,29 +754,29 @@ PVRSRV_ERROR PDumpMemKM(IMG_PVOID pvAltLinAddr,
750 754
751 PDUMP_GET_SCRIPT_AND_FILE_STRING(); 755 PDUMP_GET_SCRIPT_AND_FILE_STRING();
752 756
757
758 if (ui32Bytes == 0 || PDumpOSIsSuspended())
759 {
760 return PVRSRV_OK;
761 }
762
753 psMMUAttrib = ((BM_BUF*)psMemInfo->sMemBlk.hBuffer)->pMapping->pBMHeap->psMMUAttrib; 763 psMMUAttrib = ((BM_BUF*)psMemInfo->sMemBlk.hBuffer)->pMapping->pBMHeap->psMMUAttrib;
754 764
755 765
756 766
757 PVR_ASSERT((ui32Offset + ui32Bytes) <= psMemInfo->ui32AllocSize); 767 PVR_ASSERT((ui32Offset + ui32Bytes) <= psMemInfo->uAllocSize);
758 768
759 if (!PDumpOSJTInitialised()) 769 if (!PDumpOSJTInitialised())
760 { 770 {
761 return PVRSRV_ERROR_PDUMP_NOT_AVAILABLE; 771 return PVRSRV_ERROR_PDUMP_NOT_AVAILABLE;
762 } 772 }
763 773
764
765 if (ui32Bytes == 0 || PDumpOSIsSuspended())
766 {
767 return PVRSRV_OK;
768 }
769
770#if defined(SUPPORT_PDUMP_MULTI_PROCESS) 774#if defined(SUPPORT_PDUMP_MULTI_PROCESS)
771 775
772 { 776 {
773 BM_HEAP *pHeap = ((BM_BUF*)psMemInfo->sMemBlk.hBuffer)->pMapping->pBMHeap; 777 BM_HEAP *pHeap = ((BM_BUF*)psMemInfo->sMemBlk.hBuffer)->pMapping->pBMHeap;
774 PVRSRV_DEVICE_NODE *psDeviceNode = pHeap->pBMContext->psDeviceNode; 778 PVRSRV_DEVICE_NODE *psDeviceNode = pHeap->pBMContext->psDeviceNode;
775 779
776 if( psDeviceNode->pfnMMUIsHeapShared(pHeap->pMMUHeap) ) 780 if( psDeviceNode->pfnMMUIsHeapShared(pHeap->pMMUHeap) )
777 { 781 {
778 ui32Flags |= PDUMP_FLAGS_PERSISTENT; 782 ui32Flags |= PDUMP_FLAGS_PERSISTENT;
@@ -936,7 +940,7 @@ PVRSRV_ERROR PDumpMemPDEntriesKM(PDUMP_MMU_ATTRIB *psMMUAttrib,
936 940
937 941
938 sMMUAttrib = *psMMUAttrib; 942 sMMUAttrib = *psMMUAttrib;
939 sMMUAttrib.ui32PTSize = HOST_PAGESIZE(); 943 sMMUAttrib.ui32PTSize = (IMG_UINT32)HOST_PAGESIZE();
940 return PDumpMemPTEntriesKM( &sMMUAttrib, 944 return PDumpMemPTEntriesKM( &sMMUAttrib,
941 hOSMemHandle, 945 hOSMemHandle,
942 pvLinAddr, 946 pvLinAddr,
@@ -970,6 +974,11 @@ PVRSRV_ERROR PDumpMemPTEntriesKM(PDUMP_MMU_ATTRIB *psMMUAttrib,
970 PDUMP_GET_SCRIPT_AND_FILE_STRING(); 974 PDUMP_GET_SCRIPT_AND_FILE_STRING();
971 ui32Flags |= ( _PDumpIsPersistent() ) ? PDUMP_FLAGS_PERSISTENT : 0; 975 ui32Flags |= ( _PDumpIsPersistent() ) ? PDUMP_FLAGS_PERSISTENT : 0;
972 976
977 if (PDumpOSIsSuspended())
978 {
979 return PVRSRV_OK;
980 }
981
973 if (!PDumpOSJTInitialised()) 982 if (!PDumpOSJTInitialised())
974 { 983 {
975 return PVRSRV_ERROR_PDUMP_NOT_AVAILABLE; 984 return PVRSRV_ERROR_PDUMP_NOT_AVAILABLE;
@@ -980,11 +989,6 @@ PVRSRV_ERROR PDumpMemPTEntriesKM(PDUMP_MMU_ATTRIB *psMMUAttrib,
980 return PVRSRV_ERROR_INVALID_PARAMS; 989 return PVRSRV_ERROR_INVALID_PARAMS;
981 } 990 }
982 991
983 if (PDumpOSIsSuspended())
984 {
985 return PVRSRV_OK;
986 }
987
988 PDumpOSCheckForSplitting(PDumpOSGetStream(PDUMP_STREAM_PARAM2), ui32Bytes, ui32Flags); 992 PDumpOSCheckForSplitting(PDumpOSGetStream(PDUMP_STREAM_PARAM2), ui32Bytes, ui32Flags);
989 993
990 ui32ParamOutPos = PDumpOSGetStreamOffset(PDUMP_STREAM_PARAM2); 994 ui32ParamOutPos = PDumpOSGetStreamOffset(PDUMP_STREAM_PARAM2);
@@ -1079,7 +1083,7 @@ PVRSRV_ERROR PDumpMemPTEntriesKM(PDUMP_MMU_ATTRIB *psMMUAttrib,
1079 { 1083 {
1080 for (ui32Offset = 0; ui32Offset < ui32BlockBytes; ui32Offset += sizeof(IMG_UINT32)) 1084 for (ui32Offset = 0; ui32Offset < ui32BlockBytes; ui32Offset += sizeof(IMG_UINT32))
1081 { 1085 {
1082 IMG_UINT32 ui32PTE = *((IMG_UINT32 *) (pui8LinAddr + ui32Offset)); 1086 IMG_UINT32 ui32PTE = *((IMG_UINT32 *)(IMG_UINTPTR_T)(pui8LinAddr + ui32Offset));
1083 1087
1084 if ((ui32PTE & psMMUAttrib->ui32PDEMask) != 0) 1088 if ((ui32PTE & psMMUAttrib->ui32PDEMask) != 0)
1085 { 1089 {
@@ -1148,7 +1152,9 @@ PVRSRV_ERROR PDumpMemPTEntriesKM(PDUMP_MMU_ATTRIB *psMMUAttrib,
1148 } 1152 }
1149 else 1153 else
1150 { 1154 {
1155#if !defined(FIX_HW_BRN_31620)
1151 PVR_ASSERT((ui32PTE & psMMUAttrib->ui32PTEValid) == 0UL); 1156 PVR_ASSERT((ui32PTE & psMMUAttrib->ui32PTEValid) == 0UL);
1157#endif
1152 eErr = PDumpOSBufprintf(hScript, 1158 eErr = PDumpOSBufprintf(hScript,
1153 ui32MaxLenScript, 1159 ui32MaxLenScript,
1154 "WRW :%s:PA_%08X%08X:0x%08X 0x%08X%08X\r\n", 1160 "WRW :%s:PA_%08X%08X:0x%08X 0x%08X%08X\r\n",
@@ -1380,20 +1386,38 @@ PVRSRV_ERROR PDumpCommentKM(IMG_CHAR *pszComment, IMG_UINT32 ui32Flags)
1380 ui32LenCommentPrefix = PDumpOSBuflen(pszCommentPrefix, sizeof(pszCommentPrefix)); 1386 ui32LenCommentPrefix = PDumpOSBuflen(pszCommentPrefix, sizeof(pszCommentPrefix));
1381 1387
1382 1388
1389
1383 if (!PDumpOSWriteString(PDumpOSGetStream(PDUMP_STREAM_SCRIPT2), 1390 if (!PDumpOSWriteString(PDumpOSGetStream(PDUMP_STREAM_SCRIPT2),
1384 (IMG_UINT8*)pszCommentPrefix, 1391 (IMG_UINT8*)pszCommentPrefix,
1385 ui32LenCommentPrefix, 1392 ui32LenCommentPrefix,
1386 ui32Flags)) 1393 ui32Flags))
1387 { 1394 {
1395#if defined(PDUMP_DEBUG_OUTFILES)
1388 if(ui32Flags & PDUMP_FLAGS_CONTINUOUS) 1396 if(ui32Flags & PDUMP_FLAGS_CONTINUOUS)
1389 { 1397 {
1398 PVR_DPF((PVR_DBG_WARNING, "Incomplete comment, %d: %s (continuous set)",
1399 g_ui32EveryLineCounter, pszComment));
1390 return PVRSRV_ERROR_PDUMP_BUFFER_FULL; 1400 return PVRSRV_ERROR_PDUMP_BUFFER_FULL;
1391 } 1401 }
1402 else if(ui32Flags & PDUMP_FLAGS_PERSISTENT)
1403 {
1404 PVR_DPF((PVR_DBG_WARNING, "Incomplete comment, %d: %s (persistent set)",
1405 g_ui32EveryLineCounter, pszComment));
1406 return PVRSRV_ERROR_CMD_NOT_PROCESSED;
1407 }
1392 else 1408 else
1393 { 1409 {
1410 PVR_DPF((PVR_DBG_WARNING, "Incomplete comment, %d: %s",
1411 g_ui32EveryLineCounter, pszComment));
1394 return PVRSRV_ERROR_CMD_NOT_PROCESSED; 1412 return PVRSRV_ERROR_CMD_NOT_PROCESSED;
1395 } 1413 }
1414#else
1415 PVR_DPF((PVR_DBG_WARNING, "Incomplete comment, %s",
1416 pszComment));
1417 return PVRSRV_ERROR_CMD_NOT_PROCESSED;
1418#endif
1396 } 1419 }
1420
1397#if defined(PDUMP_DEBUG_OUTFILES) 1421#if defined(PDUMP_DEBUG_OUTFILES)
1398 1422
1399 eErr = PDumpOSSprintf(pszTemp, 256, "%d-%d %s", 1423 eErr = PDumpOSSprintf(pszTemp, 256, "%d-%d %s",
@@ -1501,7 +1525,7 @@ PVRSRV_ERROR PDumpBitmapKM( PVRSRV_DEVICE_NODE *psDeviceNode,
1501 IMG_UINT32 ui32PDumpFlags) 1525 IMG_UINT32 ui32PDumpFlags)
1502{ 1526{
1503 PVRSRV_DEVICE_IDENTIFIER *psDevId = &psDeviceNode->sDevId; 1527 PVRSRV_DEVICE_IDENTIFIER *psDevId = &psDeviceNode->sDevId;
1504 1528 IMG_UINT32 ui32MMUContextID;
1505 PVRSRV_ERROR eErr; 1529 PVRSRV_ERROR eErr;
1506 PDUMP_GET_SCRIPT_STRING(); 1530 PDUMP_GET_SCRIPT_STRING();
1507 1531
@@ -1513,34 +1537,15 @@ PVRSRV_ERROR PDumpBitmapKM( PVRSRV_DEVICE_NODE *psDeviceNode,
1513 PDumpCommentWithFlags(ui32PDumpFlags, "\r\n-- Dump bitmap of render\r\n"); 1537 PDumpCommentWithFlags(ui32PDumpFlags, "\r\n-- Dump bitmap of render\r\n");
1514 1538
1515 1539
1516 1540 ui32MMUContextID = psDeviceNode->pfnMMUGetContextID( hDevMemContext );
1517 1541
1518 PVR_UNREFERENCED_PARAMETER(hDevMemContext);
1519
1520#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
1521
1522 eErr = PDumpOSBufprintf(hScript, 1542 eErr = PDumpOSBufprintf(hScript,
1523 ui32MaxLen, 1543 ui32MaxLen,
1524 "SII %s %s.bin :%s:v%x:0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\r\n", 1544 "SII %s %s.bin :%s:v%x:0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\r\n",
1525 pszFileName, 1545 pszFileName,
1526 pszFileName, 1546 pszFileName,
1527 psDevId->pszPDumpDevName, 1547 psDevId->pszPDumpDevName,
1528 PDUMP_DATAMASTER_PIXEL, 1548 ui32MMUContextID,
1529 sDevBaseAddr.uiAddr,
1530 ui32Size,
1531 ui32FileOffset,
1532 ePixelFormat,
1533 ui32Width,
1534 ui32Height,
1535 ui32StrideInBytes,
1536 eMemFormat);
1537#else
1538 eErr = PDumpOSBufprintf(hScript,
1539 ui32MaxLen,
1540 "SII %s %s.bin :%s:v:0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\r\n",
1541 pszFileName,
1542 pszFileName,
1543 psDevId->pszPDumpDevName,
1544 sDevBaseAddr.uiAddr, 1549 sDevBaseAddr.uiAddr,
1545 ui32Size, 1550 ui32Size,
1546 ui32FileOffset, 1551 ui32FileOffset,
@@ -1549,7 +1554,6 @@ PVRSRV_ERROR PDumpBitmapKM( PVRSRV_DEVICE_NODE *psDeviceNode,
1549 ui32Height, 1554 ui32Height,
1550 ui32StrideInBytes, 1555 ui32StrideInBytes,
1551 eMemFormat); 1556 eMemFormat);
1552#endif
1553 if(eErr != PVRSRV_OK) 1557 if(eErr != PVRSRV_OK)
1554 { 1558 {
1555 return eErr; 1559 return eErr;
@@ -1762,26 +1766,17 @@ PVRSRV_ERROR PDumpSaveMemKM (PVRSRV_DEVICE_IDENTIFIER *psDevId,
1762 IMG_UINT32 ui32FileOffset, 1766 IMG_UINT32 ui32FileOffset,
1763 IMG_DEV_VIRTADDR sDevBaseAddr, 1767 IMG_DEV_VIRTADDR sDevBaseAddr,
1764 IMG_UINT32 ui32Size, 1768 IMG_UINT32 ui32Size,
1765 IMG_UINT32 ui32DataMaster, 1769 IMG_UINT32 ui32MMUContextID,
1766 IMG_UINT32 ui32PDumpFlags) 1770 IMG_UINT32 ui32PDumpFlags)
1767{ 1771{
1768 PVRSRV_ERROR eErr; 1772 PVRSRV_ERROR eErr;
1769 PDUMP_GET_SCRIPT_STRING(); 1773 PDUMP_GET_SCRIPT_STRING();
1770 1774
1771#if !defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
1772 PVR_UNREFERENCED_PARAMETER(ui32DataMaster);
1773#endif
1774
1775 eErr = PDumpOSBufprintf(hScript, 1775 eErr = PDumpOSBufprintf(hScript,
1776 ui32MaxLen, 1776 ui32MaxLen,
1777#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
1778 "SAB :%s:v%x:0x%08X 0x%08X 0x%08X %s.bin\r\n", 1777 "SAB :%s:v%x:0x%08X 0x%08X 0x%08X %s.bin\r\n",
1779 psDevId->pszPDumpDevName, 1778 psDevId->pszPDumpDevName,
1780 ui32DataMaster, 1779 ui32MMUContextID,
1781#else
1782 "SAB :%s:v:0x%08X 0x%08X 0x%08X %s.bin\r\n",
1783 psDevId->pszPDumpDevName,
1784#endif
1785 sDevBaseAddr.uiAddr, 1780 sDevBaseAddr.uiAddr,
1786 ui32Size, 1781 ui32Size,
1787 ui32FileOffset, 1782 ui32FileOffset,
@@ -1820,6 +1815,7 @@ PVRSRV_ERROR PDumpSignatureBuffer (PVRSRV_DEVICE_IDENTIFIER *psDevId,
1820 IMG_UINT32 ui32FileOffset, 1815 IMG_UINT32 ui32FileOffset,
1821 IMG_DEV_VIRTADDR sDevBaseAddr, 1816 IMG_DEV_VIRTADDR sDevBaseAddr,
1822 IMG_UINT32 ui32Size, 1817 IMG_UINT32 ui32Size,
1818 IMG_UINT32 ui32MMUContextID,
1823 IMG_UINT32 ui32PDumpFlags) 1819 IMG_UINT32 ui32PDumpFlags)
1824{ 1820{
1825 PDumpCommentWithFlags(ui32PDumpFlags, "\r\n-- Dump microkernel %s signature Buffer\r\n", 1821 PDumpCommentWithFlags(ui32PDumpFlags, "\r\n-- Dump microkernel %s signature Buffer\r\n",
@@ -1831,7 +1827,7 @@ PVRSRV_ERROR PDumpSignatureBuffer (PVRSRV_DEVICE_IDENTIFIER *psDevId,
1831 PDumpCommentWithFlags(ui32PDumpFlags, "\tSignature sample values (number of samples * number of signatures)\r\n"); 1827 PDumpCommentWithFlags(ui32PDumpFlags, "\tSignature sample values (number of samples * number of signatures)\r\n");
1832 PDumpCommentWithFlags(ui32PDumpFlags, "Note: If buffer is full, last sample is final state after test completed\r\n"); 1828 PDumpCommentWithFlags(ui32PDumpFlags, "Note: If buffer is full, last sample is final state after test completed\r\n");
1833 return PDumpSaveMemKM(psDevId, pszFileName, ui32FileOffset, sDevBaseAddr, ui32Size, 1829 return PDumpSaveMemKM(psDevId, pszFileName, ui32FileOffset, sDevBaseAddr, ui32Size,
1834 PDUMP_DATAMASTER_EDM, ui32PDumpFlags); 1830 ui32MMUContextID, ui32PDumpFlags);
1835} 1831}
1836 1832
1837 1833
@@ -1840,11 +1836,12 @@ PVRSRV_ERROR PDumpHWPerfCBKM (PVRSRV_DEVICE_IDENTIFIER *psDevId,
1840 IMG_UINT32 ui32FileOffset, 1836 IMG_UINT32 ui32FileOffset,
1841 IMG_DEV_VIRTADDR sDevBaseAddr, 1837 IMG_DEV_VIRTADDR sDevBaseAddr,
1842 IMG_UINT32 ui32Size, 1838 IMG_UINT32 ui32Size,
1839 IMG_UINT32 ui32MMUContextID,
1843 IMG_UINT32 ui32PDumpFlags) 1840 IMG_UINT32 ui32PDumpFlags)
1844{ 1841{
1845 PDumpCommentWithFlags(ui32PDumpFlags, "\r\n-- Dump Hardware Performance Circular Buffer\r\n"); 1842 PDumpCommentWithFlags(ui32PDumpFlags, "\r\n-- Dump Hardware Performance Circular Buffer\r\n");
1846 return PDumpSaveMemKM(psDevId, pszFileName, ui32FileOffset, sDevBaseAddr, ui32Size, 1843 return PDumpSaveMemKM(psDevId, pszFileName, ui32FileOffset, sDevBaseAddr, ui32Size,
1847 PDUMP_DATAMASTER_EDM, ui32PDumpFlags); 1844 ui32MMUContextID, ui32PDumpFlags);
1848} 1845}
1849 1846
1850 1847
@@ -1870,7 +1867,7 @@ PVRSRV_ERROR PDumpCBP(PPVRSRV_KERNEL_MEM_INFO psROffMemInfo,
1870 psMMUAttrib = ((BM_BUF*)psROffMemInfo->sMemBlk.hBuffer)->pMapping->pBMHeap->psMMUAttrib; 1867 psMMUAttrib = ((BM_BUF*)psROffMemInfo->sMemBlk.hBuffer)->pMapping->pBMHeap->psMMUAttrib;
1871 1868
1872 1869
1873 PVR_ASSERT((ui32ROffOffset + sizeof(IMG_UINT32)) <= psROffMemInfo->ui32AllocSize); 1870 PVR_ASSERT((ui32ROffOffset + sizeof(IMG_UINT32)) <= psROffMemInfo->uAllocSize);
1874 1871
1875 pui8LinAddr = psROffMemInfo->pvLinAddrKM; 1872 pui8LinAddr = psROffMemInfo->pvLinAddrKM;
1876 sDevVAddr = psROffMemInfo->sDevVAddr; 1873 sDevVAddr = psROffMemInfo->sDevVAddr;
@@ -2073,13 +2070,14 @@ PVRSRV_ERROR PDumpSetMMUContext(PVRSRV_DEVICE_TYPE eDeviceType,
2073 IMG_CPU_PHYADDR sCpuPAddr; 2070 IMG_CPU_PHYADDR sCpuPAddr;
2074 IMG_DEV_PHYADDR sDevPAddr; 2071 IMG_DEV_PHYADDR sDevPAddr;
2075 IMG_UINT32 ui32MMUContextID; 2072 IMG_UINT32 ui32MMUContextID;
2076 PVRSRV_ERROR eError; 2073 PVRSRV_ERROR eErr;
2074 PDUMP_GET_SCRIPT_STRING();
2077 2075
2078 eError = _PdumpAllocMMUContext(&ui32MMUContextID); 2076 eErr = _PdumpAllocMMUContext(&ui32MMUContextID);
2079 if(eError != PVRSRV_OK) 2077 if(eErr != PVRSRV_OK)
2080 { 2078 {
2081 PVR_DPF((PVR_DBG_ERROR, "PDumpSetMMUContext: _PdumpAllocMMUContext failed: %d", eError)); 2079 PVR_DPF((PVR_DBG_ERROR, "PDumpSetMMUContext: _PdumpAllocMMUContext failed: %d", eErr));
2082 return eError; 2080 return eErr;
2083 } 2081 }
2084 2082
2085 2083
@@ -2089,15 +2087,20 @@ PVRSRV_ERROR PDumpSetMMUContext(PVRSRV_DEVICE_TYPE eDeviceType,
2089 2087
2090 sDevPAddr.uiAddr &= ~((PVRSRV_4K_PAGE_SIZE) -1); 2088 sDevPAddr.uiAddr &= ~((PVRSRV_4K_PAGE_SIZE) -1);
2091 2089
2092 PDumpComment("Set MMU Context\r\n"); 2090 eErr = PDumpOSBufprintf(hScript,
2093 2091 ui32MaxLen,
2094 PDumpComment("MMU :%s:v%d %d :%s:PA_%08X%08X\r\n", 2092 "MMU :%s:v%d %d :%s:PA_%08X%08X\r\n",
2095 pszMemSpace, 2093 pszMemSpace,
2096 ui32MMUContextID, 2094 ui32MMUContextID,
2097 ui32MMUType, 2095 ui32MMUType,
2098 pszMemSpace, 2096 pszMemSpace,
2099 (IMG_UINT32)(IMG_UINTPTR_T)hUniqueTag1, 2097 (IMG_UINT32)(IMG_UINTPTR_T)hUniqueTag1,
2100 sDevPAddr.uiAddr); 2098 sDevPAddr.uiAddr);
2099 if(eErr != PVRSRV_OK)
2100 {
2101 return eErr;
2102 }
2103 PDumpOSWriteString2(hScript, PDUMP_FLAGS_CONTINUOUS);
2101 2104
2102 2105
2103 *pui32MMUContextID = ui32MMUContextID; 2106 *pui32MMUContextID = ui32MMUContextID;
@@ -2111,23 +2114,29 @@ PVRSRV_ERROR PDumpClearMMUContext(PVRSRV_DEVICE_TYPE eDeviceType,
2111 IMG_UINT32 ui32MMUContextID, 2114 IMG_UINT32 ui32MMUContextID,
2112 IMG_UINT32 ui32MMUType) 2115 IMG_UINT32 ui32MMUType)
2113{ 2116{
2114 PVRSRV_ERROR eError; 2117 PVRSRV_ERROR eErr;
2115 2118 PDUMP_GET_SCRIPT_STRING();
2116 PVR_UNREFERENCED_PARAMETER(eDeviceType); 2119 PVR_UNREFERENCED_PARAMETER(eDeviceType);
2120 PVR_UNREFERENCED_PARAMETER(ui32MMUType);
2117 2121
2118 2122
2119 PDumpComment("Clear MMU Context for memory space %s\r\n", pszMemSpace); 2123 PDumpComment("Clear MMU Context for memory space %s\r\n", pszMemSpace);
2120 2124 eErr = PDumpOSBufprintf(hScript,
2121 PDumpComment("MMU :%s:v%d %d\r\n", 2125 ui32MaxLen,
2126 "MMU :%s:v%d\r\n",
2122 pszMemSpace, 2127 pszMemSpace,
2123 ui32MMUContextID, 2128 ui32MMUContextID);
2124 ui32MMUType); 2129 if(eErr != PVRSRV_OK)
2130 {
2131 return eErr;
2132 }
2133 PDumpOSWriteString2(hScript, PDUMP_FLAGS_CONTINUOUS);
2125 2134
2126 eError = _PdumpFreeMMUContext(ui32MMUContextID); 2135 eErr = _PdumpFreeMMUContext(ui32MMUContextID);
2127 if(eError != PVRSRV_OK) 2136 if(eErr != PVRSRV_OK)
2128 { 2137 {
2129 PVR_DPF((PVR_DBG_ERROR, "PDumpClearMMUContext: _PdumpFreeMMUContext failed: %d", eError)); 2138 PVR_DPF((PVR_DBG_ERROR, "PDumpClearMMUContext: _PdumpFreeMMUContext failed: %d", eErr));
2130 return eError; 2139 return eErr;
2131 } 2140 }
2132 2141
2133 return PVRSRV_OK; 2142 return PVRSRV_OK;
@@ -2151,7 +2160,7 @@ PVRSRV_ERROR PDumpStoreMemToFile(PDUMP_MMU_ATTRIB *psMMUAttrib,
2151 2160
2152 2161
2153 2162
2154 ui32PageOffset = (IMG_UINT32)psMemInfo->pvLinAddrKM & psMMUAttrib->ui32DataPageMask; 2163 ui32PageOffset = (IMG_UINT32)((IMG_UINTPTR_T)psMemInfo->pvLinAddrKM & psMMUAttrib->ui32DataPageMask);
2155 2164
2156 2165
2157 sDevVPageAddr.uiAddr = uiAddr - ui32PageOffset; 2166 sDevVPageAddr.uiAddr = uiAddr - ui32PageOffset;
@@ -2201,6 +2210,7 @@ PVRSRV_ERROR PDumpRegBasedCBP(IMG_CHAR *pszPDumpRegName,
2201} 2210}
2202 2211
2203 2212
2213
2204#include "syscommon.h" 2214#include "syscommon.h"
2205 2215
2206IMG_EXPORT IMG_VOID PDumpConnectionNotify(IMG_VOID) 2216IMG_EXPORT IMG_VOID PDumpConnectionNotify(IMG_VOID)
@@ -2235,9 +2245,9 @@ IMG_UINT32 DbgWrite(PDBG_STREAM psStream, IMG_UINT8 *pui8Data, IMG_UINT32 ui32BC
2235 { 2245 {
2236 return ui32BCount; 2246 return ui32BCount;
2237 } 2247 }
2238 2248
2239#if defined(SUPPORT_PDUMP_MULTI_PROCESS) 2249#if defined(SUPPORT_PDUMP_MULTI_PROCESS)
2240 2250
2241 if ( (_PDumpIsProcessActive() == IMG_FALSE ) && 2251 if ( (_PDumpIsProcessActive() == IMG_FALSE ) &&
2242 ((ui32Flags & PDUMP_FLAGS_PERSISTENT) == 0) ) 2252 ((ui32Flags & PDUMP_FLAGS_PERSISTENT) == 0) )
2243 { 2253 {
@@ -2245,10 +2255,10 @@ IMG_UINT32 DbgWrite(PDBG_STREAM psStream, IMG_UINT8 *pui8Data, IMG_UINT32 ui32BC
2245 } 2255 }
2246#endif 2256#endif
2247 2257
2248 2258
2249 if ( ((ui32Flags & PDUMP_FLAGS_PERSISTENT) != 0) && (psCtrl->bInitPhaseComplete) ) 2259 if ( ((ui32Flags & PDUMP_FLAGS_PERSISTENT) != 0) && (psCtrl->bInitPhaseComplete) )
2250 { 2260 {
2251 while (((IMG_UINT32) ui32BCount > 0) && (ui32BytesWritten != 0xFFFFFFFFU)) 2261 while (ui32BCount > 0)
2252 { 2262 {
2253 2263
2254 2264
@@ -2272,14 +2282,14 @@ IMG_UINT32 DbgWrite(PDBG_STREAM psStream, IMG_UINT8 *pui8Data, IMG_UINT32 ui32BC
2272 PVR_DPF((PVR_DBG_ERROR, "DbgWrite: Failed to send persistent data")); 2282 PVR_DPF((PVR_DBG_ERROR, "DbgWrite: Failed to send persistent data"));
2273 if( (psCtrl->ui32Flags & DEBUG_FLAGS_READONLY) != 0) 2283 if( (psCtrl->ui32Flags & DEBUG_FLAGS_READONLY) != 0)
2274 { 2284 {
2275 2285
2276 PDumpSuspendKM(); 2286 PDumpSuspendKM();
2277 } 2287 }
2278 return 0xFFFFFFFFU; 2288 return 0xFFFFFFFFU;
2279 } 2289 }
2280 } 2290 }
2281 2291
2282 2292
2283 ui32BCount = ui32Off; ui32Off = 0; ui32BytesWritten = 0; 2293 ui32BCount = ui32Off; ui32Off = 0; ui32BytesWritten = 0;
2284 } 2294 }
2285 2295
diff --git a/drivers/gpu/pvr/pdump_km.h b/drivers/gpu/pvr/pdump_km.h
index 1be14d64de7..f51910daf1e 100644
--- a/drivers/gpu/pvr/pdump_km.h
+++ b/drivers/gpu/pvr/pdump_km.h
@@ -54,7 +54,7 @@ extern IMG_UINT32 g_ui32EveryLineCounter;
54 54
55#ifdef PDUMP 55#ifdef PDUMP
56 56
57#define MAKEUNIQUETAG(hMemInfo) (((BM_BUF *)(((PVRSRV_KERNEL_MEM_INFO *)(hMemInfo))->sMemBlk.hBuffer))->pMapping) 57#define MAKEUNIQUETAG(hMemInfo) ((PDumpOSIsSuspended()) ? 0 : ((BM_BUF *)(((PVRSRV_KERNEL_MEM_INFO *)(hMemInfo))->sMemBlk.hBuffer))->pMapping)
58 58
59 IMG_IMPORT PVRSRV_ERROR PDumpMemPolKM(PVRSRV_KERNEL_MEM_INFO *psMemInfo, 59 IMG_IMPORT PVRSRV_ERROR PDumpMemPolKM(PVRSRV_KERNEL_MEM_INFO *psMemInfo,
60 IMG_UINT32 ui32Offset, 60 IMG_UINT32 ui32Offset,
@@ -79,7 +79,7 @@ extern IMG_UINT32 g_ui32EveryLineCounter;
79 IMG_UINT32 ui32Bytes, 79 IMG_UINT32 ui32Bytes,
80 IMG_UINT32 ui32Flags, 80 IMG_UINT32 ui32Flags,
81 IMG_HANDLE hUniqueTag); 81 IMG_HANDLE hUniqueTag);
82 PVRSRV_ERROR PDumpMemPagesKM(PVRSRV_DEVICE_TYPE eDeviceType, 82 PVRSRV_ERROR PDumpMemPagesKM(PVRSRV_DEVICE_IDENTIFIER *psDevID,
83 IMG_DEV_PHYADDR *pPages, 83 IMG_DEV_PHYADDR *pPages,
84 IMG_UINT32 ui32NumPages, 84 IMG_UINT32 ui32NumPages,
85 IMG_DEV_VIRTADDR sDevAddr, 85 IMG_DEV_VIRTADDR sDevAddr,
@@ -124,11 +124,13 @@ extern IMG_UINT32 g_ui32EveryLineCounter;
124 IMG_UINT32 ui32RegAddr, 124 IMG_UINT32 ui32RegAddr,
125 IMG_UINT32 ui32RegValue, 125 IMG_UINT32 ui32RegValue,
126 IMG_UINT32 ui32Mask, 126 IMG_UINT32 ui32Mask,
127 IMG_UINT32 ui32Flags); 127 IMG_UINT32 ui32Flags,
128 PDUMP_POLL_OPERATOR eOperator);
128 PVRSRV_ERROR PDumpRegPolKM(IMG_CHAR *pszPDumpRegName, 129 PVRSRV_ERROR PDumpRegPolKM(IMG_CHAR *pszPDumpRegName,
129 IMG_UINT32 ui32RegAddr, 130 IMG_UINT32 ui32RegAddr,
130 IMG_UINT32 ui32RegValue, 131 IMG_UINT32 ui32RegValue,
131 IMG_UINT32 ui32Mask); 132 IMG_UINT32 ui32Mask,
133 PDUMP_POLL_OPERATOR eOperator);
132 134
133 IMG_IMPORT PVRSRV_ERROR PDumpBitmapKM(PVRSRV_DEVICE_NODE *psDeviceNode, 135 IMG_IMPORT PVRSRV_ERROR PDumpBitmapKM(PVRSRV_DEVICE_NODE *psDeviceNode,
134 IMG_CHAR *pszFileName, 136 IMG_CHAR *pszFileName,
@@ -171,7 +173,7 @@ extern IMG_UINT32 g_ui32EveryLineCounter;
171 IMG_BOOL PDumpIsLastCaptureFrameKM(IMG_VOID); 173 IMG_BOOL PDumpIsLastCaptureFrameKM(IMG_VOID);
172 IMG_IMPORT IMG_BOOL PDumpIsCaptureFrameKM(IMG_VOID); 174 IMG_IMPORT IMG_BOOL PDumpIsCaptureFrameKM(IMG_VOID);
173 175
174 IMG_VOID PDumpMallocPagesPhys(PVRSRV_DEVICE_TYPE eDeviceType, 176 IMG_VOID PDumpMallocPagesPhys(PVRSRV_DEVICE_IDENTIFIER *psDevID,
175 IMG_UINT32 ui32DevVAddr, 177 IMG_UINT32 ui32DevVAddr,
176 IMG_PUINT32 pui32PhysPages, 178 IMG_PUINT32 pui32PhysPages,
177 IMG_UINT32 ui32NumPages, 179 IMG_UINT32 ui32NumPages,
@@ -267,6 +269,7 @@ extern IMG_UINT32 g_ui32EveryLineCounter;
267 IMG_UINT32 ui32FileOffset, 269 IMG_UINT32 ui32FileOffset,
268 IMG_DEV_VIRTADDR sDevBaseAddr, 270 IMG_DEV_VIRTADDR sDevBaseAddr,
269 IMG_UINT32 ui32Size, 271 IMG_UINT32 ui32Size,
272 IMG_UINT32 ui32MMUContextID,
270 IMG_UINT32 ui32PDumpFlags); 273 IMG_UINT32 ui32PDumpFlags);
271 274
272 PVRSRV_ERROR PDumpSignatureBuffer(PVRSRV_DEVICE_IDENTIFIER *psDevId, 275 PVRSRV_ERROR PDumpSignatureBuffer(PVRSRV_DEVICE_IDENTIFIER *psDevId,
@@ -275,6 +278,7 @@ extern IMG_UINT32 g_ui32EveryLineCounter;
275 IMG_UINT32 ui32FileOffset, 278 IMG_UINT32 ui32FileOffset,
276 IMG_DEV_VIRTADDR sDevBaseAddr, 279 IMG_DEV_VIRTADDR sDevBaseAddr,
277 IMG_UINT32 ui32Size, 280 IMG_UINT32 ui32Size,
281 IMG_UINT32 ui32MMUContextID,
278 IMG_UINT32 ui32PDumpFlags); 282 IMG_UINT32 ui32PDumpFlags);
279 283
280 PVRSRV_ERROR PDumpCBP(PPVRSRV_KERNEL_MEM_INFO psROffMemInfo, 284 PVRSRV_ERROR PDumpCBP(PPVRSRV_KERNEL_MEM_INFO psROffMemInfo,
diff --git a/drivers/gpu/pvr/pdumpdefs.h b/drivers/gpu/pvr/pdumpdefs.h
index 83ccbb2c80c..0efe3031d75 100644
--- a/drivers/gpu/pvr/pdumpdefs.h
+++ b/drivers/gpu/pvr/pdumpdefs.h
@@ -68,6 +68,15 @@ typedef enum _PDUMP_PIXEL_FORMAT_
68 PVRSRV_PDUMP_PIXEL_FORMAT_F32 = 36, 68 PVRSRV_PDUMP_PIXEL_FORMAT_F32 = 36,
69 PVRSRV_PDUMP_PIXEL_FORMAT_L16 = 37, 69 PVRSRV_PDUMP_PIXEL_FORMAT_L16 = 37,
70 PVRSRV_PDUMP_PIXEL_FORMAT_L32 = 38, 70 PVRSRV_PDUMP_PIXEL_FORMAT_L32 = 38,
71 PVRSRV_PDUMP_PIXEL_FORMAT_RGBA8888 = 39,
72 PVRSRV_PDUMP_PIXEL_FORMAT_ABGR4444 = 40,
73 PVRSRV_PDUMP_PIXEL_FORMAT_RGBA4444 = 41,
74 PVRSRV_PDUMP_PIXEL_FORMAT_BGRA4444 = 42,
75 PVRSRV_PDUMP_PIXEL_FORMAT_ABGR1555 = 43,
76 PVRSRV_PDUMP_PIXEL_FORMAT_RGBA5551 = 44,
77 PVRSRV_PDUMP_PIXEL_FORMAT_BGRA5551 = 45,
78 PVRSRV_PDUMP_PIXEL_FORMAT_BGR565 = 46,
79 PVRSRV_PDUMP_PIXEL_FORMAT_A8 = 47,
71 80
72 PVRSRV_PDUMP_PIXEL_FORMAT_FORCE_I32 = 0x7fffffff 81 PVRSRV_PDUMP_PIXEL_FORMAT_FORCE_I32 = 0x7fffffff
73 82
diff --git a/drivers/gpu/pvr/perproc.c b/drivers/gpu/pvr/perproc.c
index 52d9980b489..7eb46a14484 100644
--- a/drivers/gpu/pvr/perproc.c
+++ b/drivers/gpu/pvr/perproc.c
@@ -29,6 +29,9 @@
29#include "handle.h" 29#include "handle.h"
30#include "perproc.h" 30#include "perproc.h"
31#include "osperproc.h" 31#include "osperproc.h"
32#if defined(TTRACE)
33#include "ttrace.h"
34#endif
32 35
33#define HASH_TAB_INIT_SIZE 32 36#define HASH_TAB_INIT_SIZE 32
34 37
@@ -207,6 +210,9 @@ PVRSRV_ERROR PVRSRVPerProcessDataConnect(IMG_UINT32 ui32PID, IMG_UINT32 ui32Flag
207 PVR_DPF((PVR_DBG_ERROR, "PVRSRVPerProcessDataConnect: Couldn't register with the resource manager")); 210 PVR_DPF((PVR_DBG_ERROR, "PVRSRVPerProcessDataConnect: Couldn't register with the resource manager"));
208 goto failure; 211 goto failure;
209 } 212 }
213#if defined (TTRACE)
214 PVRSRVTimeTraceBufferCreate(ui32PID);
215#endif
210 } 216 }
211 217
212 psPerProc->ui32RefCount++; 218 psPerProc->ui32RefCount++;
@@ -242,6 +248,10 @@ IMG_VOID PVRSRVPerProcessDataDisconnect(IMG_UINT32 ui32PID)
242 PVR_DPF((PVR_DBG_MESSAGE, "PVRSRVPerProcessDataDisconnect: " 248 PVR_DPF((PVR_DBG_MESSAGE, "PVRSRVPerProcessDataDisconnect: "
243 "Last close from process 0x%x received", ui32PID)); 249 "Last close from process 0x%x received", ui32PID));
244 250
251#if defined (TTRACE)
252 PVRSRVTimeTraceBufferDestroy(ui32PID);
253#endif
254
245 255
246 PVRSRVResManDisconnect(psPerProc->hResManContext, IMG_FALSE); 256 PVRSRVResManDisconnect(psPerProc->hResManContext, IMG_FALSE);
247 257
diff --git a/drivers/gpu/pvr/perproc.h b/drivers/gpu/pvr/perproc.h
index 37359d50e05..e416b5a629e 100644
--- a/drivers/gpu/pvr/perproc.h
+++ b/drivers/gpu/pvr/perproc.h
@@ -41,12 +41,21 @@ typedef struct _PVRSRV_PER_PROCESS_DATA_
41 IMG_UINT32 ui32PID; 41 IMG_UINT32 ui32PID;
42 IMG_HANDLE hBlockAlloc; 42 IMG_HANDLE hBlockAlloc;
43 PRESMAN_CONTEXT hResManContext; 43 PRESMAN_CONTEXT hResManContext;
44#if defined (SUPPORT_SID_INTERFACE)
45 IMG_SID hPerProcData;
46#else
44 IMG_HANDLE hPerProcData; 47 IMG_HANDLE hPerProcData;
48#endif
45 PVRSRV_HANDLE_BASE *psHandleBase; 49 PVRSRV_HANDLE_BASE *psHandleBase;
50#if defined (SUPPORT_SID_INTERFACE)
51
52 IMG_BOOL bHandlesBatched;
53#else
46#if defined (PVR_SECURE_HANDLES) 54#if defined (PVR_SECURE_HANDLES)
47 55
48 IMG_BOOL bHandlesBatched; 56 IMG_BOOL bHandlesBatched;
49#endif 57#endif
58#endif
50 IMG_UINT32 ui32RefCount; 59 IMG_UINT32 ui32RefCount;
51 60
52 61
@@ -55,9 +64,9 @@ typedef struct _PVRSRV_PER_PROCESS_DATA_
55 64
56 IMG_BOOL bPDumpPersistent; 65 IMG_BOOL bPDumpPersistent;
57#if defined(SUPPORT_PDUMP_MULTI_PROCESS) 66#if defined(SUPPORT_PDUMP_MULTI_PROCESS)
58 67
59 IMG_BOOL bPDumpActive; 68 IMG_BOOL bPDumpActive;
60#endif 69#endif
61#endif 70#endif
62 71
63 IMG_HANDLE hOsPrivateData; 72 IMG_HANDLE hOsPrivateData;
diff --git a/drivers/gpu/pvr/power.c b/drivers/gpu/pvr/power.c
index ba0eced9ba1..ba203aba3c4 100644
--- a/drivers/gpu/pvr/power.c
+++ b/drivers/gpu/pvr/power.c
@@ -96,20 +96,14 @@ PVRSRV_ERROR PVRSRVPowerLock(IMG_UINT32 ui32CallerID,
96 SYS_DATA *psSysData; 96 SYS_DATA *psSysData;
97 IMG_UINT32 ui32Timeout = 1000000; 97 IMG_UINT32 ui32Timeout = 1000000;
98 98
99#if defined(SUPPORT_LMA)
100
101 ui32Timeout *= 60;
102#endif
103
104 SysAcquireData(&psSysData); 99 SysAcquireData(&psSysData);
105 100
106#if defined(SYS_CUSTOM_POWERLOCK_WRAP) 101 eError = OSPowerLockWrap();
107 eError = SysPowerLockWrap(psSysData);
108 if (eError != PVRSRV_OK) 102 if (eError != PVRSRV_OK)
109 { 103 {
110 return eError; 104 return eError;
111 } 105 }
112#endif 106
113 do 107 do
114 { 108 {
115 eError = OSLockResource(&psSysData->sPowerStateChangeResource, 109 eError = OSLockResource(&psSysData->sPowerStateChangeResource,
@@ -130,12 +124,11 @@ PVRSRV_ERROR PVRSRVPowerLock(IMG_UINT32 ui32CallerID,
130 ui32Timeout--; 124 ui32Timeout--;
131 } while (ui32Timeout > 0); 125 } while (ui32Timeout > 0);
132 126
133#if defined(SYS_CUSTOM_POWERLOCK_WRAP)
134 if (eError != PVRSRV_OK) 127 if (eError != PVRSRV_OK)
135 { 128 {
136 SysPowerLockUnwrap(psSysData); 129 OSPowerLockUnwrap();
137 } 130 }
138#endif 131
139 132
140 if ((eError == PVRSRV_OK) && 133 if ((eError == PVRSRV_OK) &&
141 !bSystemPowerEvent && 134 !bSystemPowerEvent &&
@@ -154,9 +147,7 @@ IMG_EXPORT
154IMG_VOID PVRSRVPowerUnlock(IMG_UINT32 ui32CallerID) 147IMG_VOID PVRSRVPowerUnlock(IMG_UINT32 ui32CallerID)
155{ 148{
156 OSUnlockResource(&gpsSysData->sPowerStateChangeResource, ui32CallerID); 149 OSUnlockResource(&gpsSysData->sPowerStateChangeResource, ui32CallerID);
157#if defined(SYS_CUSTOM_POWERLOCK_WRAP) 150 OSPowerLockUnwrap();
158 SysPowerLockUnwrap(gpsSysData);
159#endif
160} 151}
161 152
162 153
@@ -560,7 +551,7 @@ PVRSRV_ERROR PVRSRVRegisterPowerDevice(IMG_UINT32 ui32DeviceIndex,
560 551
561 SysAcquireData(&psSysData); 552 SysAcquireData(&psSysData);
562 553
563 eError = OSAllocMem( PVRSRV_OS_PAGEABLE_HEAP, 554 eError = OSAllocMem( PVRSRV_OS_NON_PAGEABLE_HEAP,
564 sizeof(PVRSRV_POWER_DEV), 555 sizeof(PVRSRV_POWER_DEV),
565 (IMG_VOID **)&psPowerDevice, IMG_NULL, 556 (IMG_VOID **)&psPowerDevice, IMG_NULL,
566 "Power Device"); 557 "Power Device");
diff --git a/drivers/gpu/pvr/private_data.h b/drivers/gpu/pvr/private_data.h
index df9f6ade53a..0c55499220a 100644
--- a/drivers/gpu/pvr/private_data.h
+++ b/drivers/gpu/pvr/private_data.h
@@ -32,35 +32,23 @@
32#include <drm/drmP.h> 32#include <drm/drmP.h>
33#endif 33#endif
34 34
35#if defined(SUPPORT_DRI_DRM) && defined(PVR_LINUX_USING_WORKQUEUES)
36#include <linux/workqueue.h>
37#endif
38
39typedef struct 35typedef struct
40{ 36{
41 37
42 IMG_UINT32 ui32OpenPID; 38 IMG_UINT32 ui32OpenPID;
43 39
44#if defined(PVR_SECURE_FD_EXPORT)
45 40
41#if defined (SUPPORT_SID_INTERFACE)
42 IMG_SID hKernelMemInfo;
43#else
46 IMG_HANDLE hKernelMemInfo; 44 IMG_HANDLE hKernelMemInfo;
47#endif 45#endif
48
49#if defined(SUPPORT_DRI_DRM)
50#if defined(PVR_SECURE_DRM_AUTH_EXPORT)
51 struct drm_file *psDRMFile;
52 46
47#if defined(SUPPORT_DRI_DRM) && defined(PVR_SECURE_DRM_AUTH_EXPORT)
53 48
54 struct list_head sDRMAuthListItem; 49 struct list_head sDRMAuthListItem;
55#endif
56 50
57#if defined(PVR_LINUX_USING_WORKQUEUES) 51 struct drm_file *psDRMFile;
58 struct work_struct sReleaseWork;
59#endif
60
61#if defined(SUPPORT_DRI_DRM_EXT)
62 IMG_PVOID pPriv;
63#endif
64#endif 52#endif
65 53
66#if defined(SUPPORT_MEMINFO_IDS) 54#if defined(SUPPORT_MEMINFO_IDS)
@@ -70,6 +58,10 @@ typedef struct
70 58
71 59
72 IMG_HANDLE hBlockAlloc; 60 IMG_HANDLE hBlockAlloc;
61
62#if defined(SUPPORT_DRI_DRM_EXT)
63 IMG_PVOID pPriv;
64#endif
73} 65}
74PVRSRV_FILE_PRIVATE_DATA; 66PVRSRV_FILE_PRIVATE_DATA;
75 67
diff --git a/drivers/gpu/pvr/pvr_bridge.h b/drivers/gpu/pvr/pvr_bridge.h
index 82c3aa66ef2..93f1bb10a8b 100644
--- a/drivers/gpu/pvr/pvr_bridge.h
+++ b/drivers/gpu/pvr/pvr_bridge.h
@@ -68,7 +68,7 @@ extern "C" {
68#define PVRSRV_BRIDGE_GETFREE_DEVICEMEM PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+8) 68#define PVRSRV_BRIDGE_GETFREE_DEVICEMEM PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+8)
69#define PVRSRV_BRIDGE_CREATE_COMMANDQUEUE PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+9) 69#define PVRSRV_BRIDGE_CREATE_COMMANDQUEUE PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+9)
70#define PVRSRV_BRIDGE_DESTROY_COMMANDQUEUE PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+10) 70#define PVRSRV_BRIDGE_DESTROY_COMMANDQUEUE PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+10)
71#define PVRSRV_BRIDGE_MHANDLE_TO_MMAP_DATA PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+11) 71#define PVRSRV_BRIDGE_MHANDLE_TO_MMAP_DATA PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+11)
72#define PVRSRV_BRIDGE_CONNECT_SERVICES PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+12) 72#define PVRSRV_BRIDGE_CONNECT_SERVICES PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+12)
73#define PVRSRV_BRIDGE_DISCONNECT_SERVICES PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+13) 73#define PVRSRV_BRIDGE_DISCONNECT_SERVICES PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+13)
74#define PVRSRV_BRIDGE_WRAP_DEVICE_MEM PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+14) 74#define PVRSRV_BRIDGE_WRAP_DEVICE_MEM PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+14)
@@ -85,7 +85,10 @@ extern "C" {
85#define PVRSRV_BRIDGE_UNMAP_MEM_INFO_FROM_USER PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+25) 85#define PVRSRV_BRIDGE_UNMAP_MEM_INFO_FROM_USER PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+25)
86#define PVRSRV_BRIDGE_EXPORT_DEVICEMEM PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+26) 86#define PVRSRV_BRIDGE_EXPORT_DEVICEMEM PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+26)
87#define PVRSRV_BRIDGE_RELEASE_MMAP_DATA PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+27) 87#define PVRSRV_BRIDGE_RELEASE_MMAP_DATA PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+27)
88#define PVRSRV_BRIDGE_CORE_CMD_LAST (PVRSRV_BRIDGE_CORE_CMD_FIRST+27) 88#define PVRSRV_BRIDGE_CHG_DEV_MEM_ATTRIBS PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+28)
89#define PVRSRV_BRIDGE_MAP_DEV_MEMORY_2 PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+29)
90#define PVRSRV_BRIDGE_EXPORT_DEVICEMEM_2 PVRSRV_IOWR(PVRSRV_BRIDGE_CORE_CMD_FIRST+30)
91#define PVRSRV_BRIDGE_CORE_CMD_LAST (PVRSRV_BRIDGE_CORE_CMD_FIRST+30)
89 92
90#define PVRSRV_BRIDGE_SIM_CMD_FIRST (PVRSRV_BRIDGE_CORE_CMD_LAST+1) 93#define PVRSRV_BRIDGE_SIM_CMD_FIRST (PVRSRV_BRIDGE_CORE_CMD_LAST+1)
91#define PVRSRV_BRIDGE_PROCESS_SIMISR_EVENT PVRSRV_IOWR(PVRSRV_BRIDGE_SIM_CMD_FIRST+0) 94#define PVRSRV_BRIDGE_PROCESS_SIMISR_EVENT PVRSRV_IOWR(PVRSRV_BRIDGE_SIM_CMD_FIRST+0)
@@ -168,7 +171,6 @@ extern "C" {
168#define PVRSRV_BRIDGE_SWAP_DISPCLASS_TO_SYSTEM PVRSRV_IOWR(PVRSRV_BRIDGE_DISPCLASS_CMD_FIRST+14) 171#define PVRSRV_BRIDGE_SWAP_DISPCLASS_TO_SYSTEM PVRSRV_IOWR(PVRSRV_BRIDGE_DISPCLASS_CMD_FIRST+14)
169#define PVRSRV_BRIDGE_DISPCLASS_CMD_LAST (PVRSRV_BRIDGE_DISPCLASS_CMD_FIRST+14) 172#define PVRSRV_BRIDGE_DISPCLASS_CMD_LAST (PVRSRV_BRIDGE_DISPCLASS_CMD_FIRST+14)
170 173
171
172#define PVRSRV_BRIDGE_BUFCLASS_CMD_FIRST (PVRSRV_BRIDGE_DISPCLASS_CMD_LAST+1) 174#define PVRSRV_BRIDGE_BUFCLASS_CMD_FIRST (PVRSRV_BRIDGE_DISPCLASS_CMD_LAST+1)
173#define PVRSRV_BRIDGE_OPEN_BUFFERCLASS_DEVICE PVRSRV_IOWR(PVRSRV_BRIDGE_BUFCLASS_CMD_FIRST+0) 175#define PVRSRV_BRIDGE_OPEN_BUFFERCLASS_DEVICE PVRSRV_IOWR(PVRSRV_BRIDGE_BUFCLASS_CMD_FIRST+0)
174#define PVRSRV_BRIDGE_CLOSE_BUFFERCLASS_DEVICE PVRSRV_IOWR(PVRSRV_BRIDGE_BUFCLASS_CMD_FIRST+1) 176#define PVRSRV_BRIDGE_CLOSE_BUFFERCLASS_DEVICE PVRSRV_IOWR(PVRSRV_BRIDGE_BUFCLASS_CMD_FIRST+1)
@@ -197,7 +199,7 @@ extern "C" {
197#define PVRSRV_BRIDGE_INITSRV_DISCONNECT PVRSRV_IOWR(PVRSRV_BRIDGE_INITSRV_CMD_FIRST+1) 199#define PVRSRV_BRIDGE_INITSRV_DISCONNECT PVRSRV_IOWR(PVRSRV_BRIDGE_INITSRV_CMD_FIRST+1)
198#define PVRSRV_BRIDGE_INITSRV_CMD_LAST (PVRSRV_BRIDGE_INITSRV_CMD_FIRST+1) 200#define PVRSRV_BRIDGE_INITSRV_CMD_LAST (PVRSRV_BRIDGE_INITSRV_CMD_FIRST+1)
199 201
200#define PVRSRV_BRIDGE_EVENT_OBJECT_CMD_FIRST (PVRSRV_BRIDGE_INITSRV_CMD_LAST+1) 202#define PVRSRV_BRIDGE_EVENT_OBJECT_CMD_FIRST (PVRSRV_BRIDGE_INITSRV_CMD_LAST+1)
201#define PVRSRV_BRIDGE_EVENT_OBJECT_WAIT PVRSRV_IOWR(PVRSRV_BRIDGE_EVENT_OBJECT_CMD_FIRST+0) 203#define PVRSRV_BRIDGE_EVENT_OBJECT_WAIT PVRSRV_IOWR(PVRSRV_BRIDGE_EVENT_OBJECT_CMD_FIRST+0)
202#define PVRSRV_BRIDGE_EVENT_OBJECT_OPEN PVRSRV_IOWR(PVRSRV_BRIDGE_EVENT_OBJECT_CMD_FIRST+1) 204#define PVRSRV_BRIDGE_EVENT_OBJECT_OPEN PVRSRV_IOWR(PVRSRV_BRIDGE_EVENT_OBJECT_CMD_FIRST+1)
203#define PVRSRV_BRIDGE_EVENT_OBJECT_CLOSE PVRSRV_IOWR(PVRSRV_BRIDGE_EVENT_OBJECT_CMD_FIRST+2) 205#define PVRSRV_BRIDGE_EVENT_OBJECT_CLOSE PVRSRV_IOWR(PVRSRV_BRIDGE_EVENT_OBJECT_CMD_FIRST+2)
@@ -208,12 +210,14 @@ extern "C" {
208#define PVRSRV_BRIDGE_DESTROY_SYNC_INFO_MOD_OBJ PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+1) 210#define PVRSRV_BRIDGE_DESTROY_SYNC_INFO_MOD_OBJ PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+1)
209#define PVRSRV_BRIDGE_MODIFY_PENDING_SYNC_OPS PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+2) 211#define PVRSRV_BRIDGE_MODIFY_PENDING_SYNC_OPS PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+2)
210#define PVRSRV_BRIDGE_MODIFY_COMPLETE_SYNC_OPS PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+3) 212#define PVRSRV_BRIDGE_MODIFY_COMPLETE_SYNC_OPS PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+3)
211#define PVRSRV_BRIDGE_SYNC_OPS_FLUSH_TO_MOD_OBJ PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+4) 213#define PVRSRV_BRIDGE_SYNC_OPS_TAKE_TOKEN PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+4)
212#define PVRSRV_BRIDGE_SYNC_OPS_FLUSH_TO_DELTA PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+5) 214#define PVRSRV_BRIDGE_SYNC_OPS_FLUSH_TO_TOKEN PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+5)
213#define PVRSRV_BRIDGE_ALLOC_SYNC_INFO PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+6) 215#define PVRSRV_BRIDGE_SYNC_OPS_FLUSH_TO_MOD_OBJ PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+6)
214#define PVRSRV_BRIDGE_FREE_SYNC_INFO PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+7) 216#define PVRSRV_BRIDGE_SYNC_OPS_FLUSH_TO_DELTA PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+7)
215#define PVRSRV_BRIDGE_SYNC_OPS_CMD_LAST (PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+7) 217#define PVRSRV_BRIDGE_ALLOC_SYNC_INFO PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+8)
216 218#define PVRSRV_BRIDGE_FREE_SYNC_INFO PVRSRV_IOWR(PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+9)
219#define PVRSRV_BRIDGE_SYNC_OPS_CMD_LAST (PVRSRV_BRIDGE_SYNC_OPS_CMD_FIRST+9)
220
217#define PVRSRV_BRIDGE_LAST_NON_DEVICE_CMD (PVRSRV_BRIDGE_SYNC_OPS_CMD_LAST+1) 221#define PVRSRV_BRIDGE_LAST_NON_DEVICE_CMD (PVRSRV_BRIDGE_SYNC_OPS_CMD_LAST+1)
218 222
219 223
@@ -231,22 +235,22 @@ typedef struct PVRSRV_BRIDGE_PACKAGE_TAG
231{ 235{
232 IMG_UINT32 ui32BridgeID; 236 IMG_UINT32 ui32BridgeID;
233 IMG_UINT32 ui32Size; 237 IMG_UINT32 ui32Size;
234 IMG_VOID *pvParamIn; 238 IMG_VOID *pvParamIn;
235 IMG_UINT32 ui32InBufferSize; 239 IMG_UINT32 ui32InBufferSize;
236 IMG_VOID *pvParamOut; 240 IMG_VOID *pvParamOut;
237 IMG_UINT32 ui32OutBufferSize; 241 IMG_UINT32 ui32OutBufferSize;
238 242
243#if defined (SUPPORT_SID_INTERFACE)
244 IMG_SID hKernelServices;
245#else
239 IMG_HANDLE hKernelServices; 246 IMG_HANDLE hKernelServices;
247#endif
240}PVRSRV_BRIDGE_PACKAGE; 248}PVRSRV_BRIDGE_PACKAGE;
241 249
242 250
243
244
245
246
247typedef struct PVRSRV_BRIDGE_IN_CONNECT_SERVICES_TAG 251typedef struct PVRSRV_BRIDGE_IN_CONNECT_SERVICES_TAG
248{ 252{
249 IMG_UINT32 ui32BridgeFlags; 253 IMG_UINT32 ui32BridgeFlags;
250 IMG_UINT32 ui32Flags; 254 IMG_UINT32 ui32Flags;
251} PVRSRV_BRIDGE_IN_CONNECT_SERVICES; 255} PVRSRV_BRIDGE_IN_CONNECT_SERVICES;
252 256
@@ -268,56 +272,82 @@ typedef struct PVRSRV_BRIDGE_IN_ENUMCLASS_TAG
268 272
269typedef struct PVRSRV_BRIDGE_IN_CLOSE_DISPCLASS_DEVICE_TAG 273typedef struct PVRSRV_BRIDGE_IN_CLOSE_DISPCLASS_DEVICE_TAG
270{ 274{
271 IMG_UINT32 ui32BridgeFlags; 275 IMG_UINT32 ui32BridgeFlags;
276#if defined (SUPPORT_SID_INTERFACE)
277 IMG_SID hDeviceKM;
278#else
272 IMG_HANDLE hDeviceKM; 279 IMG_HANDLE hDeviceKM;
280#endif
273} PVRSRV_BRIDGE_IN_CLOSE_DISPCLASS_DEVICE; 281} PVRSRV_BRIDGE_IN_CLOSE_DISPCLASS_DEVICE;
274 282
275 283
276typedef struct PVRSRV_BRIDGE_IN_ENUM_DISPCLASS_FORMATS_TAG 284typedef struct PVRSRV_BRIDGE_IN_ENUM_DISPCLASS_FORMATS_TAG
277{ 285{
278 IMG_UINT32 ui32BridgeFlags; 286 IMG_UINT32 ui32BridgeFlags;
287#if defined (SUPPORT_SID_INTERFACE)
288 IMG_SID hDeviceKM;
289#else
279 IMG_HANDLE hDeviceKM; 290 IMG_HANDLE hDeviceKM;
291#endif
280} PVRSRV_BRIDGE_IN_ENUM_DISPCLASS_FORMATS; 292} PVRSRV_BRIDGE_IN_ENUM_DISPCLASS_FORMATS;
281 293
282 294
283typedef struct PVRSRV_BRIDGE_IN_GET_DISPCLASS_SYSBUFFER_TAG 295typedef struct PVRSRV_BRIDGE_IN_GET_DISPCLASS_SYSBUFFER_TAG
284{ 296{
285 IMG_UINT32 ui32BridgeFlags; 297 IMG_UINT32 ui32BridgeFlags;
298#if defined (SUPPORT_SID_INTERFACE)
299 IMG_SID hDeviceKM;
300#else
286 IMG_HANDLE hDeviceKM; 301 IMG_HANDLE hDeviceKM;
302#endif
287} PVRSRV_BRIDGE_IN_GET_DISPCLASS_SYSBUFFER; 303} PVRSRV_BRIDGE_IN_GET_DISPCLASS_SYSBUFFER;
288 304
289 305
290typedef struct PVRSRV_BRIDGE_IN_GET_DISPCLASS_INFO_TAG 306typedef struct PVRSRV_BRIDGE_IN_GET_DISPCLASS_INFO_TAG
291{ 307{
292 IMG_UINT32 ui32BridgeFlags; 308 IMG_UINT32 ui32BridgeFlags;
309#if defined (SUPPORT_SID_INTERFACE)
310 IMG_SID hDeviceKM;
311#else
293 IMG_HANDLE hDeviceKM; 312 IMG_HANDLE hDeviceKM;
313#endif
294} PVRSRV_BRIDGE_IN_GET_DISPCLASS_INFO; 314} PVRSRV_BRIDGE_IN_GET_DISPCLASS_INFO;
295 315
296 316
297typedef struct PVRSRV_BRIDGE_IN_CLOSE_BUFFERCLASS_DEVICE_TAG 317typedef struct PVRSRV_BRIDGE_IN_CLOSE_BUFFERCLASS_DEVICE_TAG
298{ 318{
299 IMG_UINT32 ui32BridgeFlags; 319 IMG_UINT32 ui32BridgeFlags;
320#if defined (SUPPORT_SID_INTERFACE)
321 IMG_SID hDeviceKM;
322#else
300 IMG_HANDLE hDeviceKM; 323 IMG_HANDLE hDeviceKM;
324#endif
301} PVRSRV_BRIDGE_IN_CLOSE_BUFFERCLASS_DEVICE; 325} PVRSRV_BRIDGE_IN_CLOSE_BUFFERCLASS_DEVICE;
302 326
303 327
304typedef struct PVRSRV_BRIDGE_IN_GET_BUFFERCLASS_INFO_TAG 328typedef struct PVRSRV_BRIDGE_IN_GET_BUFFERCLASS_INFO_TAG
305{ 329{
306 IMG_UINT32 ui32BridgeFlags; 330 IMG_UINT32 ui32BridgeFlags;
331#if defined (SUPPORT_SID_INTERFACE)
332 IMG_SID hDeviceKM;
333#else
307 IMG_HANDLE hDeviceKM; 334 IMG_HANDLE hDeviceKM;
335#endif
308} PVRSRV_BRIDGE_IN_GET_BUFFERCLASS_INFO; 336} PVRSRV_BRIDGE_IN_GET_BUFFERCLASS_INFO;
309 337
310 338
311
312typedef struct PVRSRV_BRIDGE_IN_RELEASE_DEVICEINFO_TAG 339typedef struct PVRSRV_BRIDGE_IN_RELEASE_DEVICEINFO_TAG
313{ 340{
314 IMG_UINT32 ui32BridgeFlags; 341 IMG_UINT32 ui32BridgeFlags;
342#if defined (SUPPORT_SID_INTERFACE)
343 IMG_SID hDevCookie;
344#else
315 IMG_HANDLE hDevCookie; 345 IMG_HANDLE hDevCookie;
346#endif
316 347
317} PVRSRV_BRIDGE_IN_RELEASE_DEVICEINFO; 348} PVRSRV_BRIDGE_IN_RELEASE_DEVICEINFO;
318 349
319 350
320
321typedef struct PVRSRV_BRIDGE_IN_FREE_CLASSDEVICEINFO_TAG 351typedef struct PVRSRV_BRIDGE_IN_FREE_CLASSDEVICEINFO_TAG
322{ 352{
323 IMG_UINT32 ui32BridgeFlags; 353 IMG_UINT32 ui32BridgeFlags;
@@ -327,85 +357,117 @@ typedef struct PVRSRV_BRIDGE_IN_FREE_CLASSDEVICEINFO_TAG
327}PVRSRV_BRIDGE_IN_FREE_CLASSDEVICEINFO; 357}PVRSRV_BRIDGE_IN_FREE_CLASSDEVICEINFO;
328 358
329 359
330
331typedef struct PVRSRV_BRIDGE_IN_GET_DEVMEM_HEAPINFO_TAG 360typedef struct PVRSRV_BRIDGE_IN_GET_DEVMEM_HEAPINFO_TAG
332{ 361{
333 IMG_UINT32 ui32BridgeFlags; 362 IMG_UINT32 ui32BridgeFlags;
363#if defined (SUPPORT_SID_INTERFACE)
364 IMG_SID hDevCookie;
365 IMG_SID hDevMemContext;
366#else
334 IMG_HANDLE hDevCookie; 367 IMG_HANDLE hDevCookie;
335 IMG_HANDLE hDevMemContext; 368 IMG_HANDLE hDevMemContext;
369#endif
336 370
337}PVRSRV_BRIDGE_IN_GET_DEVMEM_HEAPINFO; 371}PVRSRV_BRIDGE_IN_GET_DEVMEM_HEAPINFO;
338 372
339 373
340
341typedef struct PVRSRV_BRIDGE_IN_CREATE_DEVMEMCONTEXT_TAG 374typedef struct PVRSRV_BRIDGE_IN_CREATE_DEVMEMCONTEXT_TAG
342{ 375{
343 IMG_UINT32 ui32BridgeFlags; 376 IMG_UINT32 ui32BridgeFlags;
377#if defined (SUPPORT_SID_INTERFACE)
378 IMG_SID hDevCookie;
379#else
344 IMG_HANDLE hDevCookie; 380 IMG_HANDLE hDevCookie;
381#endif
345 382
346}PVRSRV_BRIDGE_IN_CREATE_DEVMEMCONTEXT; 383}PVRSRV_BRIDGE_IN_CREATE_DEVMEMCONTEXT;
347 384
348 385
349
350typedef struct PVRSRV_BRIDGE_IN_DESTROY_DEVMEMCONTEXT_TAG 386typedef struct PVRSRV_BRIDGE_IN_DESTROY_DEVMEMCONTEXT_TAG
351{ 387{
352 IMG_UINT32 ui32BridgeFlags; 388 IMG_UINT32 ui32BridgeFlags;
389#if defined (SUPPORT_SID_INTERFACE)
390 IMG_SID hDevCookie;
391 IMG_SID hDevMemContext;
392#else
353 IMG_HANDLE hDevCookie; 393 IMG_HANDLE hDevCookie;
354 IMG_HANDLE hDevMemContext; 394 IMG_HANDLE hDevMemContext;
395#endif
355 396
356}PVRSRV_BRIDGE_IN_DESTROY_DEVMEMCONTEXT; 397}PVRSRV_BRIDGE_IN_DESTROY_DEVMEMCONTEXT;
357 398
358 399
359
360typedef struct PVRSRV_BRIDGE_IN_ALLOCDEVICEMEM_TAG 400typedef struct PVRSRV_BRIDGE_IN_ALLOCDEVICEMEM_TAG
361{ 401{
362 IMG_UINT32 ui32BridgeFlags; 402 IMG_UINT32 ui32BridgeFlags;
403#if defined (SUPPORT_SID_INTERFACE)
404 IMG_SID hDevCookie;
405 IMG_SID hDevMemHeap;
406#else
363 IMG_HANDLE hDevCookie; 407 IMG_HANDLE hDevCookie;
364 IMG_HANDLE hDevMemHeap; 408 IMG_HANDLE hDevMemHeap;
409#endif
365 IMG_UINT32 ui32Attribs; 410 IMG_UINT32 ui32Attribs;
366 IMG_SIZE_T ui32Size; 411 IMG_SIZE_T ui32Size;
367 IMG_SIZE_T ui32Alignment; 412 IMG_SIZE_T ui32Alignment;
368 413
369}PVRSRV_BRIDGE_IN_ALLOCDEVICEMEM; 414}PVRSRV_BRIDGE_IN_ALLOCDEVICEMEM;
370 415
371
372typedef struct PVRSRV_BRIDGE_IN_MAPMEMINFOTOUSER_TAG 416typedef struct PVRSRV_BRIDGE_IN_MAPMEMINFOTOUSER_TAG
373{ 417{
374 IMG_UINT32 ui32BridgeFlags; 418 IMG_UINT32 ui32BridgeFlags;
419#if defined (SUPPORT_SID_INTERFACE)
420 IMG_SID hKernelMemInfo;
421#else
375 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 422 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
423#endif
376 424
377}PVRSRV_BRIDGE_IN_MAPMEMINFOTOUSER; 425}PVRSRV_BRIDGE_IN_MAPMEMINFOTOUSER;
378 426
379
380typedef struct PVRSRV_BRIDGE_IN_UNMAPMEMINFOFROMUSER_TAG 427typedef struct PVRSRV_BRIDGE_IN_UNMAPMEMINFOFROMUSER_TAG
381{ 428{
382 IMG_UINT32 ui32BridgeFlags; 429 IMG_UINT32 ui32BridgeFlags;
430#if defined (SUPPORT_SID_INTERFACE)
431 IMG_SID hKernelMemInfo;
432#else
383 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 433 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
434#endif
384 IMG_PVOID pvLinAddr; 435 IMG_PVOID pvLinAddr;
436#if defined (SUPPORT_SID_INTERFACE)
437 IMG_SID hMappingInfo;
438#else
385 IMG_HANDLE hMappingInfo; 439 IMG_HANDLE hMappingInfo;
440#endif
386 441
387}PVRSRV_BRIDGE_IN_UNMAPMEMINFOFROMUSER; 442}PVRSRV_BRIDGE_IN_UNMAPMEMINFOFROMUSER;
388 443
389
390typedef struct PVRSRV_BRIDGE_IN_FREEDEVICEMEM_TAG 444typedef struct PVRSRV_BRIDGE_IN_FREEDEVICEMEM_TAG
391{ 445{
392 IMG_UINT32 ui32BridgeFlags; 446 IMG_UINT32 ui32BridgeFlags;
447#if defined (SUPPORT_SID_INTERFACE)
448 IMG_SID hDevCookie;
449 IMG_SID hKernelMemInfo;
450#else
393 IMG_HANDLE hDevCookie; 451 IMG_HANDLE hDevCookie;
394 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 452 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
395 PVRSRV_CLIENT_MEM_INFO sClientMemInfo; 453#endif
454 PVRSRV_CLIENT_MEM_INFO sClientMemInfo;
396 455
397}PVRSRV_BRIDGE_IN_FREEDEVICEMEM; 456}PVRSRV_BRIDGE_IN_FREEDEVICEMEM;
398 457
399
400typedef struct PVRSRV_BRIDGE_IN_EXPORTDEVICEMEM_TAG 458typedef struct PVRSRV_BRIDGE_IN_EXPORTDEVICEMEM_TAG
401{ 459{
402 IMG_UINT32 ui32BridgeFlags; 460 IMG_UINT32 ui32BridgeFlags;
461#if defined (SUPPORT_SID_INTERFACE)
462 IMG_SID hDevCookie;
463 IMG_SID hKernelMemInfo;
464#else
403 IMG_HANDLE hDevCookie; 465 IMG_HANDLE hDevCookie;
404 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 466 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
467#endif
405 468
406}PVRSRV_BRIDGE_IN_EXPORTDEVICEMEM; 469}PVRSRV_BRIDGE_IN_EXPORTDEVICEMEM;
407 470
408
409typedef struct PVRSRV_BRIDGE_IN_GETFREEDEVICEMEM_TAG 471typedef struct PVRSRV_BRIDGE_IN_GETFREEDEVICEMEM_TAG
410{ 472{
411 IMG_UINT32 ui32BridgeFlags; 473 IMG_UINT32 ui32BridgeFlags;
@@ -413,126 +475,163 @@ typedef struct PVRSRV_BRIDGE_IN_GETFREEDEVICEMEM_TAG
413 475
414} PVRSRV_BRIDGE_IN_GETFREEDEVICEMEM; 476} PVRSRV_BRIDGE_IN_GETFREEDEVICEMEM;
415 477
416
417typedef struct PVRSRV_BRIDGE_IN_CREATECOMMANDQUEUE_TAG 478typedef struct PVRSRV_BRIDGE_IN_CREATECOMMANDQUEUE_TAG
418{ 479{
419 IMG_UINT32 ui32BridgeFlags; 480 IMG_UINT32 ui32BridgeFlags;
481#if defined (SUPPORT_SID_INTERFACE)
482 IMG_SID hDevCookie;
483#else
420 IMG_HANDLE hDevCookie; 484 IMG_HANDLE hDevCookie;
485#endif
421 IMG_SIZE_T ui32QueueSize; 486 IMG_SIZE_T ui32QueueSize;
422 487
423}PVRSRV_BRIDGE_IN_CREATECOMMANDQUEUE; 488}PVRSRV_BRIDGE_IN_CREATECOMMANDQUEUE;
424 489
425 490
426
427typedef struct PVRSRV_BRIDGE_IN_DESTROYCOMMANDQUEUE_TAG 491typedef struct PVRSRV_BRIDGE_IN_DESTROYCOMMANDQUEUE_TAG
428{ 492{
429 IMG_UINT32 ui32BridgeFlags; 493 IMG_UINT32 ui32BridgeFlags;
494#if defined (SUPPORT_SID_INTERFACE)
495 IMG_SID hDevCookie;
496#else
430 IMG_HANDLE hDevCookie; 497 IMG_HANDLE hDevCookie;
498#endif
431 PVRSRV_QUEUE_INFO *psQueueInfo; 499 PVRSRV_QUEUE_INFO *psQueueInfo;
432 500
433}PVRSRV_BRIDGE_IN_DESTROYCOMMANDQUEUE; 501}PVRSRV_BRIDGE_IN_DESTROYCOMMANDQUEUE;
434 502
435 503
436
437typedef struct PVRSRV_BRIDGE_IN_MHANDLE_TO_MMAP_DATA_TAG 504typedef struct PVRSRV_BRIDGE_IN_MHANDLE_TO_MMAP_DATA_TAG
438{ 505{
439 IMG_UINT32 ui32BridgeFlags; 506 IMG_UINT32 ui32BridgeFlags;
507#if defined (SUPPORT_SID_INTERFACE)
508 IMG_SID hMHandle;
509#else
440 IMG_HANDLE hMHandle; 510 IMG_HANDLE hMHandle;
511#endif
441} PVRSRV_BRIDGE_IN_MHANDLE_TO_MMAP_DATA; 512} PVRSRV_BRIDGE_IN_MHANDLE_TO_MMAP_DATA;
442 513
443 514
444
445typedef struct PVRSRV_BRIDGE_IN_RELEASE_MMAP_DATA_TAG 515typedef struct PVRSRV_BRIDGE_IN_RELEASE_MMAP_DATA_TAG
446{ 516{
447 IMG_UINT32 ui32BridgeFlags; 517 IMG_UINT32 ui32BridgeFlags;
518#if defined (SUPPORT_SID_INTERFACE)
519 IMG_SID hMHandle;
520#else
448 IMG_HANDLE hMHandle; 521 IMG_HANDLE hMHandle;
522#endif
449} PVRSRV_BRIDGE_IN_RELEASE_MMAP_DATA; 523} PVRSRV_BRIDGE_IN_RELEASE_MMAP_DATA;
450 524
451 525
452
453typedef struct PVRSRV_BRIDGE_IN_RESERVE_DEV_VIRTMEM_TAG 526typedef struct PVRSRV_BRIDGE_IN_RESERVE_DEV_VIRTMEM_TAG
454{ 527{
455 IMG_UINT32 ui32BridgeFlags; 528 IMG_UINT32 ui32BridgeFlags;
529#if defined (SUPPORT_SID_INTERFACE)
530 IMG_SID hDevMemHeap;
531#else
456 IMG_HANDLE hDevMemHeap; 532 IMG_HANDLE hDevMemHeap;
533#endif
457 IMG_DEV_VIRTADDR *psDevVAddr; 534 IMG_DEV_VIRTADDR *psDevVAddr;
458 IMG_SIZE_T ui32Size; 535 IMG_SIZE_T ui32Size;
459 IMG_SIZE_T ui32Alignment; 536 IMG_SIZE_T ui32Alignment;
460 537
461}PVRSRV_BRIDGE_IN_RESERVE_DEV_VIRTMEM; 538}PVRSRV_BRIDGE_IN_RESERVE_DEV_VIRTMEM;
462 539
463
464typedef struct PVRSRV_BRIDGE_OUT_CONNECT_SERVICES_TAG 540typedef struct PVRSRV_BRIDGE_OUT_CONNECT_SERVICES_TAG
465{ 541{
466 PVRSRV_ERROR eError; 542 PVRSRV_ERROR eError;
543#if defined (SUPPORT_SID_INTERFACE)
544 IMG_SID hKernelServices;
545#else
467 IMG_HANDLE hKernelServices; 546 IMG_HANDLE hKernelServices;
547#endif
468}PVRSRV_BRIDGE_OUT_CONNECT_SERVICES; 548}PVRSRV_BRIDGE_OUT_CONNECT_SERVICES;
469 549
470
471typedef struct PVRSRV_BRIDGE_OUT_RESERVE_DEV_VIRTMEM_TAG 550typedef struct PVRSRV_BRIDGE_OUT_RESERVE_DEV_VIRTMEM_TAG
472{ 551{
473 PVRSRV_ERROR eError; 552 PVRSRV_ERROR eError;
553#if defined (SUPPORT_SID_INTERFACE)
554 IMG_SID hKernelMemInfo;
555 IMG_SID hKernelSyncInfo;
556#else
474 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 557 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
475 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo; 558 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo;
476 PVRSRV_CLIENT_MEM_INFO sClientMemInfo; 559#endif
477 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo; 560 PVRSRV_CLIENT_MEM_INFO sClientMemInfo;
561 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo;
478 562
479}PVRSRV_BRIDGE_OUT_RESERVE_DEV_VIRTMEM; 563}PVRSRV_BRIDGE_OUT_RESERVE_DEV_VIRTMEM;
480 564
481 565
482
483typedef struct PVRSRV_BRIDGE_IN_FREE_DEV_VIRTMEM_TAG 566typedef struct PVRSRV_BRIDGE_IN_FREE_DEV_VIRTMEM_TAG
484{ 567{
485 IMG_UINT32 ui32BridgeFlags; 568 IMG_UINT32 ui32BridgeFlags;
569#if defined (SUPPORT_SID_INTERFACE)
570 IMG_SID hKernelMemInfo;
571#else
486 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 572 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
487 PVRSRV_CLIENT_MEM_INFO sClientMemInfo; 573#endif
488 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo; 574 PVRSRV_CLIENT_MEM_INFO sClientMemInfo;
575 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo;
489 576
490}PVRSRV_BRIDGE_IN_FREE_DEV_VIRTMEM; 577}PVRSRV_BRIDGE_IN_FREE_DEV_VIRTMEM;
491 578
492 579
493
494typedef struct PVRSRV_BRIDGE_IN_MAP_DEV_MEMORY_TAG 580typedef struct PVRSRV_BRIDGE_IN_MAP_DEV_MEMORY_TAG
495{ 581{
496 IMG_UINT32 ui32BridgeFlags; 582 IMG_UINT32 ui32BridgeFlags;
583#if defined (SUPPORT_SID_INTERFACE)
584 IMG_SID hKernelMemInfo;
585 IMG_SID hDstDevMemHeap;
586#else
497 IMG_HANDLE hKernelMemInfo; 587 IMG_HANDLE hKernelMemInfo;
498 IMG_HANDLE hDstDevMemHeap; 588 IMG_HANDLE hDstDevMemHeap;
589#endif
499 590
500}PVRSRV_BRIDGE_IN_MAP_DEV_MEMORY; 591}PVRSRV_BRIDGE_IN_MAP_DEV_MEMORY;
501 592
502 593
503
504typedef struct PVRSRV_BRIDGE_OUT_MAP_DEV_MEMORY_TAG 594typedef struct PVRSRV_BRIDGE_OUT_MAP_DEV_MEMORY_TAG
505{ 595{
506 PVRSRV_ERROR eError; 596 PVRSRV_ERROR eError;
597#if defined (SUPPORT_SID_INTERFACE)
598 IMG_SID hDstKernelMemInfo;
599#else
507 PVRSRV_KERNEL_MEM_INFO *psDstKernelMemInfo; 600 PVRSRV_KERNEL_MEM_INFO *psDstKernelMemInfo;
508 PVRSRV_CLIENT_MEM_INFO sDstClientMemInfo; 601#endif
509 PVRSRV_CLIENT_SYNC_INFO sDstClientSyncInfo; 602 PVRSRV_CLIENT_MEM_INFO sDstClientMemInfo;
603 PVRSRV_CLIENT_SYNC_INFO sDstClientSyncInfo;
510 604
511}PVRSRV_BRIDGE_OUT_MAP_DEV_MEMORY; 605}PVRSRV_BRIDGE_OUT_MAP_DEV_MEMORY;
512 606
513 607
514
515typedef struct PVRSRV_BRIDGE_IN_UNMAP_DEV_MEMORY_TAG 608typedef struct PVRSRV_BRIDGE_IN_UNMAP_DEV_MEMORY_TAG
516{ 609{
517 IMG_UINT32 ui32BridgeFlags; 610 IMG_UINT32 ui32BridgeFlags;
611#if defined (SUPPORT_SID_INTERFACE)
612 IMG_SID hKernelMemInfo;
613#else
518 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 614 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
519 PVRSRV_CLIENT_MEM_INFO sClientMemInfo; 615#endif
520 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo; 616 PVRSRV_CLIENT_MEM_INFO sClientMemInfo;
617 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo;
521 618
522}PVRSRV_BRIDGE_IN_UNMAP_DEV_MEMORY; 619}PVRSRV_BRIDGE_IN_UNMAP_DEV_MEMORY;
523 620
524 621
525
526typedef struct PVRSRV_BRIDGE_IN_MAP_EXT_MEMORY_TAG 622typedef struct PVRSRV_BRIDGE_IN_MAP_EXT_MEMORY_TAG
527{ 623{
528 IMG_UINT32 ui32BridgeFlags; 624 IMG_UINT32 ui32BridgeFlags;
625#if defined (SUPPORT_SID_INTERFACE)
626 IMG_SID hKernelMemInfo;
627#else
529 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 628 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
530 IMG_SYS_PHYADDR *psSysPAddr; 629#endif
531 IMG_UINT32 ui32Flags; 630 IMG_SYS_PHYADDR *psSysPAddr;
631 IMG_UINT32 ui32Flags;
532 632
533}PVRSRV_BRIDGE_IN_MAP_EXT_MEMORY; 633}PVRSRV_BRIDGE_IN_MAP_EXT_MEMORY;
534 634
535
536typedef struct PVRSRV_BRIDGE_IN_UNMAP_EXT_MEMORY_TAG 635typedef struct PVRSRV_BRIDGE_IN_UNMAP_EXT_MEMORY_TAG
537{ 636{
538 IMG_UINT32 ui32BridgeFlags; 637 IMG_UINT32 ui32BridgeFlags;
@@ -542,44 +641,58 @@ typedef struct PVRSRV_BRIDGE_IN_UNMAP_EXT_MEMORY_TAG
542 641
543}PVRSRV_BRIDGE_IN_UNMAP_EXT_MEMORY; 642}PVRSRV_BRIDGE_IN_UNMAP_EXT_MEMORY;
544 643
545
546typedef struct PVRSRV_BRIDGE_IN_MAP_DEVICECLASS_MEMORY_TAG 644typedef struct PVRSRV_BRIDGE_IN_MAP_DEVICECLASS_MEMORY_TAG
547{ 645{
548 IMG_UINT32 ui32BridgeFlags; 646 IMG_UINT32 ui32BridgeFlags;
647#if defined (SUPPORT_SID_INTERFACE)
648 IMG_SID hDeviceClassBuffer;
649 IMG_SID hDevMemContext;
650#else
549 IMG_HANDLE hDeviceClassBuffer; 651 IMG_HANDLE hDeviceClassBuffer;
550 IMG_HANDLE hDevMemContext; 652 IMG_HANDLE hDevMemContext;
653#endif
551 654
552}PVRSRV_BRIDGE_IN_MAP_DEVICECLASS_MEMORY; 655}PVRSRV_BRIDGE_IN_MAP_DEVICECLASS_MEMORY;
553 656
554 657
555
556typedef struct PVRSRV_BRIDGE_OUT_MAP_DEVICECLASS_MEMORY_TAG 658typedef struct PVRSRV_BRIDGE_OUT_MAP_DEVICECLASS_MEMORY_TAG
557{ 659{
558 PVRSRV_ERROR eError; 660 PVRSRV_ERROR eError;
559 PVRSRV_CLIENT_MEM_INFO sClientMemInfo; 661 PVRSRV_CLIENT_MEM_INFO sClientMemInfo;
560 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo; 662 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo;
663#if defined (SUPPORT_SID_INTERFACE)
664 IMG_SID hKernelMemInfo;
665 IMG_SID hMappingInfo;
666#else
561 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 667 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
562 IMG_HANDLE hMappingInfo; 668 IMG_HANDLE hMappingInfo;
669#endif
563 670
564}PVRSRV_BRIDGE_OUT_MAP_DEVICECLASS_MEMORY; 671}PVRSRV_BRIDGE_OUT_MAP_DEVICECLASS_MEMORY;
565 672
566 673
567
568typedef struct PVRSRV_BRIDGE_IN_UNMAP_DEVICECLASS_MEMORY_TAG 674typedef struct PVRSRV_BRIDGE_IN_UNMAP_DEVICECLASS_MEMORY_TAG
569{ 675{
570 IMG_UINT32 ui32BridgeFlags; 676 IMG_UINT32 ui32BridgeFlags;
677#if defined (SUPPORT_SID_INTERFACE)
678 IMG_SID hKernelMemInfo;
679#else
571 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 680 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
572 PVRSRV_CLIENT_MEM_INFO sClientMemInfo; 681#endif
573 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo; 682 PVRSRV_CLIENT_MEM_INFO sClientMemInfo;
683 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo;
574 684
575}PVRSRV_BRIDGE_IN_UNMAP_DEVICECLASS_MEMORY; 685}PVRSRV_BRIDGE_IN_UNMAP_DEVICECLASS_MEMORY;
576 686
577 687
578
579typedef struct PVRSRV_BRIDGE_IN_PDUMP_MEMPOL_TAG 688typedef struct PVRSRV_BRIDGE_IN_PDUMP_MEMPOL_TAG
580{ 689{
581 IMG_UINT32 ui32BridgeFlags; 690 IMG_UINT32 ui32BridgeFlags;
691#if defined (SUPPORT_SID_INTERFACE)
692 IMG_SID hKernelMemInfo;
693#else
582 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 694 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
695#endif
583 IMG_UINT32 ui32Offset; 696 IMG_UINT32 ui32Offset;
584 IMG_UINT32 ui32Value; 697 IMG_UINT32 ui32Value;
585 IMG_UINT32 ui32Mask; 698 IMG_UINT32 ui32Mask;
@@ -588,25 +701,32 @@ typedef struct PVRSRV_BRIDGE_IN_PDUMP_MEMPOL_TAG
588 701
589}PVRSRV_BRIDGE_IN_PDUMP_MEMPOL; 702}PVRSRV_BRIDGE_IN_PDUMP_MEMPOL;
590 703
591
592typedef struct PVRSRV_BRIDGE_IN_PDUMP_SYNCPOL_TAG 704typedef struct PVRSRV_BRIDGE_IN_PDUMP_SYNCPOL_TAG
593{ 705{
594 IMG_UINT32 ui32BridgeFlags; 706 IMG_UINT32 ui32BridgeFlags;
707#if defined (SUPPORT_SID_INTERFACE)
708 IMG_SID hKernelSyncInfo;
709#else
595 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo; 710 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo;
596 IMG_BOOL bIsRead; 711#endif
712 IMG_BOOL bIsRead;
713 IMG_BOOL bUseLastOpDumpVal;
597 IMG_UINT32 ui32Value; 714 IMG_UINT32 ui32Value;
598 IMG_UINT32 ui32Mask; 715 IMG_UINT32 ui32Mask;
599 716
600}PVRSRV_BRIDGE_IN_PDUMP_SYNCPOL; 717}PVRSRV_BRIDGE_IN_PDUMP_SYNCPOL;
601 718
602 719
603
604typedef struct PVRSRV_BRIDGE_IN_PDUMP_DUMPMEM_TAG 720typedef struct PVRSRV_BRIDGE_IN_PDUMP_DUMPMEM_TAG
605{ 721{
606 IMG_UINT32 ui32BridgeFlags; 722 IMG_UINT32 ui32BridgeFlags;
607 IMG_PVOID pvLinAddr; 723 IMG_PVOID pvLinAddr;
608 IMG_PVOID pvAltLinAddr; 724 IMG_PVOID pvAltLinAddr;
725#if defined (SUPPORT_SID_INTERFACE)
726 IMG_SID hKernelMemInfo;
727#else
609 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 728 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
729#endif
610 IMG_UINT32 ui32Offset; 730 IMG_UINT32 ui32Offset;
611 IMG_UINT32 ui32Bytes; 731 IMG_UINT32 ui32Bytes;
612 IMG_UINT32 ui32Flags; 732 IMG_UINT32 ui32Flags;
@@ -614,41 +734,49 @@ typedef struct PVRSRV_BRIDGE_IN_PDUMP_DUMPMEM_TAG
614}PVRSRV_BRIDGE_IN_PDUMP_DUMPMEM; 734}PVRSRV_BRIDGE_IN_PDUMP_DUMPMEM;
615 735
616 736
617
618typedef struct PVRSRV_BRIDGE_IN_PDUMP_DUMPSYNC_TAG 737typedef struct PVRSRV_BRIDGE_IN_PDUMP_DUMPSYNC_TAG
619{ 738{
620 IMG_UINT32 ui32BridgeFlags; 739 IMG_UINT32 ui32BridgeFlags;
621 IMG_PVOID pvAltLinAddr; 740 IMG_PVOID pvAltLinAddr;
741#if defined (SUPPORT_SID_INTERFACE)
742 IMG_SID hKernelSyncInfo;
743#else
622 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo; 744 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo;
745#endif
623 IMG_UINT32 ui32Offset; 746 IMG_UINT32 ui32Offset;
624 IMG_UINT32 ui32Bytes; 747 IMG_UINT32 ui32Bytes;
625 748
626}PVRSRV_BRIDGE_IN_PDUMP_DUMPSYNC; 749}PVRSRV_BRIDGE_IN_PDUMP_DUMPSYNC;
627 750
628 751
629
630typedef struct PVRSRV_BRIDGE_IN_PDUMP_DUMPREG_TAG 752typedef struct PVRSRV_BRIDGE_IN_PDUMP_DUMPREG_TAG
631{ 753{
632 IMG_UINT32 ui32BridgeFlags; 754 IMG_UINT32 ui32BridgeFlags;
755#if defined (SUPPORT_SID_INTERFACE)
756 IMG_SID hDevCookie;
757#else
633 IMG_HANDLE hDevCookie; 758 IMG_HANDLE hDevCookie;
759#endif
634 PVRSRV_HWREG sHWReg; 760 PVRSRV_HWREG sHWReg;
635 IMG_UINT32 ui32Flags; 761 IMG_UINT32 ui32Flags;
636 IMG_CHAR szRegRegion[32]; 762 IMG_CHAR szRegRegion[32];
637 763
638}PVRSRV_BRIDGE_IN_PDUMP_DUMPREG; 764}PVRSRV_BRIDGE_IN_PDUMP_DUMPREG;
639 765
640
641typedef struct PVRSRV_BRIDGE_IN_PDUMP_REGPOL_TAG 766typedef struct PVRSRV_BRIDGE_IN_PDUMP_REGPOL_TAG
642{ 767{
643 IMG_UINT32 ui32BridgeFlags; 768 IMG_UINT32 ui32BridgeFlags;
769#if defined (SUPPORT_SID_INTERFACE)
770 IMG_SID hDevCookie;
771#else
644 IMG_HANDLE hDevCookie; 772 IMG_HANDLE hDevCookie;
773#endif
645 PVRSRV_HWREG sHWReg; 774 PVRSRV_HWREG sHWReg;
646 IMG_UINT32 ui32Mask; 775 IMG_UINT32 ui32Mask;
647 IMG_UINT32 ui32Flags; 776 IMG_UINT32 ui32Flags;
648 IMG_CHAR szRegRegion[32]; 777 IMG_CHAR szRegRegion[32];
649}PVRSRV_BRIDGE_IN_PDUMP_REGPOL; 778}PVRSRV_BRIDGE_IN_PDUMP_REGPOL;
650 779
651
652typedef struct PVRSRV_BRIDGE_IN_PDUMP_DUMPPDREG_TAG 780typedef struct PVRSRV_BRIDGE_IN_PDUMP_DUMPPDREG_TAG
653{ 781{
654 IMG_UINT32 ui32BridgeFlags; 782 IMG_UINT32 ui32BridgeFlags;
@@ -657,21 +785,25 @@ typedef struct PVRSRV_BRIDGE_IN_PDUMP_DUMPPDREG_TAG
657 785
658}PVRSRV_BRIDGE_IN_PDUMP_DUMPPDREG; 786}PVRSRV_BRIDGE_IN_PDUMP_DUMPPDREG;
659 787
660
661typedef struct PVRSRV_BRIDGE_IN_PDUMP_MEMPAGES_TAG 788typedef struct PVRSRV_BRIDGE_IN_PDUMP_MEMPAGES_TAG
662{ 789{
663 IMG_UINT32 ui32BridgeFlags; 790 IMG_UINT32 ui32BridgeFlags;
791#if defined (SUPPORT_SID_INTERFACE)
792 IMG_SID hDevCookie;
793 IMG_SID hKernelMemInfo;
794#else
795 IMG_HANDLE hDevCookie;
664 IMG_HANDLE hKernelMemInfo; 796 IMG_HANDLE hKernelMemInfo;
797#endif
665 IMG_DEV_PHYADDR *pPages; 798 IMG_DEV_PHYADDR *pPages;
666 IMG_UINT32 ui32NumPages; 799 IMG_UINT32 ui32NumPages;
667 IMG_DEV_VIRTADDR sDevAddr; 800 IMG_DEV_VIRTADDR sDevVAddr;
668 IMG_UINT32 ui32Start; 801 IMG_UINT32 ui32Start;
669 IMG_UINT32 ui32Length; 802 IMG_UINT32 ui32Length;
670 IMG_BOOL bContinuous; 803 IMG_UINT32 ui32Flags;
671 804
672}PVRSRV_BRIDGE_IN_PDUMP_MEMPAGES; 805}PVRSRV_BRIDGE_IN_PDUMP_MEMPAGES;
673 806
674
675typedef struct PVRSRV_BRIDGE_IN_PDUMP_COMMENT_TAG 807typedef struct PVRSRV_BRIDGE_IN_PDUMP_COMMENT_TAG
676{ 808{
677 IMG_UINT32 ui32BridgeFlags; 809 IMG_UINT32 ui32BridgeFlags;
@@ -681,7 +813,6 @@ typedef struct PVRSRV_BRIDGE_IN_PDUMP_COMMENT_TAG
681}PVRSRV_BRIDGE_IN_PDUMP_COMMENT; 813}PVRSRV_BRIDGE_IN_PDUMP_COMMENT;
682 814
683 815
684
685typedef struct PVRSRV_BRIDGE_IN_PDUMP_SETFRAME_TAG 816typedef struct PVRSRV_BRIDGE_IN_PDUMP_SETFRAME_TAG
686{ 817{
687 IMG_UINT32 ui32BridgeFlags; 818 IMG_UINT32 ui32BridgeFlags;
@@ -690,19 +821,25 @@ typedef struct PVRSRV_BRIDGE_IN_PDUMP_SETFRAME_TAG
690}PVRSRV_BRIDGE_IN_PDUMP_SETFRAME; 821}PVRSRV_BRIDGE_IN_PDUMP_SETFRAME;
691 822
692 823
693
694
695typedef struct PVRSRV_BRIDGE_IN_PDUMP_BITMAP_TAG 824typedef struct PVRSRV_BRIDGE_IN_PDUMP_BITMAP_TAG
696{ 825{
697 IMG_UINT32 ui32BridgeFlags; 826 IMG_UINT32 ui32BridgeFlags;
827#if defined (SUPPORT_SID_INTERFACE)
828 IMG_SID hDevCookie;
829#else
698 IMG_HANDLE hDevCookie; 830 IMG_HANDLE hDevCookie;
699 IMG_CHAR szFileName[PVRSRV_PDUMP_MAX_FILENAME_SIZE]; 831#endif
832 IMG_CHAR szFileName[PVRSRV_PDUMP_MAX_FILENAME_SIZE];
700 IMG_UINT32 ui32FileOffset; 833 IMG_UINT32 ui32FileOffset;
701 IMG_UINT32 ui32Width; 834 IMG_UINT32 ui32Width;
702 IMG_UINT32 ui32Height; 835 IMG_UINT32 ui32Height;
703 IMG_UINT32 ui32StrideInBytes; 836 IMG_UINT32 ui32StrideInBytes;
704 IMG_DEV_VIRTADDR sDevBaseAddr; 837 IMG_DEV_VIRTADDR sDevBaseAddr;
838#if defined (SUPPORT_SID_INTERFACE)
839 IMG_SID hDevMemContext;
840#else
705 IMG_HANDLE hDevMemContext; 841 IMG_HANDLE hDevMemContext;
842#endif
706 IMG_UINT32 ui32Size; 843 IMG_UINT32 ui32Size;
707 PDUMP_PIXEL_FORMAT ePixelFormat; 844 PDUMP_PIXEL_FORMAT ePixelFormat;
708 PDUMP_MEM_FORMAT eMemFormat; 845 PDUMP_MEM_FORMAT eMemFormat;
@@ -711,21 +848,23 @@ typedef struct PVRSRV_BRIDGE_IN_PDUMP_BITMAP_TAG
711}PVRSRV_BRIDGE_IN_PDUMP_BITMAP; 848}PVRSRV_BRIDGE_IN_PDUMP_BITMAP;
712 849
713 850
714
715typedef struct PVRSRV_BRIDGE_IN_PDUMP_READREG_TAG 851typedef struct PVRSRV_BRIDGE_IN_PDUMP_READREG_TAG
716{ 852{
717 IMG_UINT32 ui32BridgeFlags; 853 IMG_UINT32 ui32BridgeFlags;
854#if defined (SUPPORT_SID_INTERFACE)
855 IMG_SID hDevCookie;
856#else
718 IMG_HANDLE hDevCookie; 857 IMG_HANDLE hDevCookie;
719 IMG_CHAR szFileName[PVRSRV_PDUMP_MAX_FILENAME_SIZE]; 858#endif
859 IMG_CHAR szFileName[PVRSRV_PDUMP_MAX_FILENAME_SIZE];
720 IMG_UINT32 ui32FileOffset; 860 IMG_UINT32 ui32FileOffset;
721 IMG_UINT32 ui32Address; 861 IMG_UINT32 ui32Address;
722 IMG_UINT32 ui32Size; 862 IMG_UINT32 ui32Size;
723 IMG_UINT32 ui32Flags; 863 IMG_UINT32 ui32Flags;
724 IMG_CHAR szRegRegion[32]; 864 IMG_CHAR szRegRegion[32];
725 865
726}PVRSRV_BRIDGE_IN_PDUMP_READREG; 866}PVRSRV_BRIDGE_IN_PDUMP_READREG;
727 867
728
729typedef struct PVRSRV_BRIDGE_IN_PDUMP_DRIVERINFO_TAG 868typedef struct PVRSRV_BRIDGE_IN_PDUMP_DRIVERINFO_TAG
730{ 869{
731 IMG_UINT32 ui32BridgeFlags; 870 IMG_UINT32 ui32BridgeFlags;
@@ -737,21 +876,27 @@ typedef struct PVRSRV_BRIDGE_IN_PDUMP_DRIVERINFO_TAG
737typedef struct PVRSRV_BRIDGE_IN_PDUMP_DUMPPDDEVPADDR_TAG 876typedef struct PVRSRV_BRIDGE_IN_PDUMP_DUMPPDDEVPADDR_TAG
738{ 877{
739 IMG_UINT32 ui32BridgeFlags; 878 IMG_UINT32 ui32BridgeFlags;
879#if defined (SUPPORT_SID_INTERFACE)
880 IMG_SID hKernelMemInfo;
881#else
740 IMG_HANDLE hKernelMemInfo; 882 IMG_HANDLE hKernelMemInfo;
883#endif
741 IMG_UINT32 ui32Offset; 884 IMG_UINT32 ui32Offset;
742 IMG_DEV_PHYADDR sPDDevPAddr; 885 IMG_DEV_PHYADDR sPDDevPAddr;
743}PVRSRV_BRIDGE_IN_PDUMP_DUMPPDDEVPADDR; 886}PVRSRV_BRIDGE_IN_PDUMP_DUMPPDDEVPADDR;
744 887
745
746typedef struct PVRSRV_BRIDGE_PDUM_IN_CYCLE_COUNT_REG_READ_TAG 888typedef struct PVRSRV_BRIDGE_PDUM_IN_CYCLE_COUNT_REG_READ_TAG
747{ 889{
748 IMG_UINT32 ui32BridgeFlags; 890 IMG_UINT32 ui32BridgeFlags;
891#if defined (SUPPORT_SID_INTERFACE)
892 IMG_SID hDevCookie;
893#else
749 IMG_HANDLE hDevCookie; 894 IMG_HANDLE hDevCookie;
895#endif
750 IMG_UINT32 ui32RegOffset; 896 IMG_UINT32 ui32RegOffset;
751 IMG_BOOL bLastFrame; 897 IMG_BOOL bLastFrame;
752}PVRSRV_BRIDGE_IN_PDUMP_CYCLE_COUNT_REG_READ; 898}PVRSRV_BRIDGE_IN_PDUMP_CYCLE_COUNT_REG_READ;
753 899
754
755typedef struct PVRSRV_BRIDGE_OUT_ENUMDEVICE_TAG 900typedef struct PVRSRV_BRIDGE_OUT_ENUMDEVICE_TAG
756{ 901{
757 PVRSRV_ERROR eError; 902 PVRSRV_ERROR eError;
@@ -761,17 +906,19 @@ typedef struct PVRSRV_BRIDGE_OUT_ENUMDEVICE_TAG
761}PVRSRV_BRIDGE_OUT_ENUMDEVICE; 906}PVRSRV_BRIDGE_OUT_ENUMDEVICE;
762 907
763 908
764
765typedef struct PVRSRV_BRIDGE_OUT_ACQUIRE_DEVICEINFO_TAG 909typedef struct PVRSRV_BRIDGE_OUT_ACQUIRE_DEVICEINFO_TAG
766{ 910{
767 911
768 PVRSRV_ERROR eError; 912 PVRSRV_ERROR eError;
913#if defined (SUPPORT_SID_INTERFACE)
914 IMG_SID hDevCookie;
915#else
769 IMG_HANDLE hDevCookie; 916 IMG_HANDLE hDevCookie;
917#endif
770 918
771} PVRSRV_BRIDGE_OUT_ACQUIRE_DEVICEINFO; 919} PVRSRV_BRIDGE_OUT_ACQUIRE_DEVICEINFO;
772 920
773 921
774
775typedef struct PVRSRV_BRIDGE_OUT_ENUMCLASS_TAG 922typedef struct PVRSRV_BRIDGE_OUT_ENUMCLASS_TAG
776{ 923{
777 PVRSRV_ERROR eError; 924 PVRSRV_ERROR eError;
@@ -781,30 +928,40 @@ typedef struct PVRSRV_BRIDGE_OUT_ENUMCLASS_TAG
781}PVRSRV_BRIDGE_OUT_ENUMCLASS; 928}PVRSRV_BRIDGE_OUT_ENUMCLASS;
782 929
783 930
784
785typedef struct PVRSRV_BRIDGE_IN_OPEN_DISPCLASS_DEVICE_TAG 931typedef struct PVRSRV_BRIDGE_IN_OPEN_DISPCLASS_DEVICE_TAG
786{ 932{
787 IMG_UINT32 ui32BridgeFlags; 933 IMG_UINT32 ui32BridgeFlags;
788 IMG_UINT32 ui32DeviceID; 934 IMG_UINT32 ui32DeviceID;
935#if defined (SUPPORT_SID_INTERFACE)
936 IMG_SID hDevCookie;
937#else
789 IMG_HANDLE hDevCookie; 938 IMG_HANDLE hDevCookie;
790 939#endif
940
791}PVRSRV_BRIDGE_IN_OPEN_DISPCLASS_DEVICE; 941}PVRSRV_BRIDGE_IN_OPEN_DISPCLASS_DEVICE;
792 942
793
794typedef struct PVRSRV_BRIDGE_OUT_OPEN_DISPCLASS_DEVICE_TAG 943typedef struct PVRSRV_BRIDGE_OUT_OPEN_DISPCLASS_DEVICE_TAG
795{ 944{
796 PVRSRV_ERROR eError; 945 PVRSRV_ERROR eError;
946#if defined (SUPPORT_SID_INTERFACE)
947 IMG_SID hDeviceKM;
948#else
797 IMG_HANDLE hDeviceKM; 949 IMG_HANDLE hDeviceKM;
950#endif
798 951
799}PVRSRV_BRIDGE_OUT_OPEN_DISPCLASS_DEVICE; 952}PVRSRV_BRIDGE_OUT_OPEN_DISPCLASS_DEVICE;
800 953
801 954
802
803typedef struct PVRSRV_BRIDGE_IN_WRAP_EXT_MEMORY_TAG 955typedef struct PVRSRV_BRIDGE_IN_WRAP_EXT_MEMORY_TAG
804{ 956{
805 IMG_UINT32 ui32BridgeFlags; 957 IMG_UINT32 ui32BridgeFlags;
958#if defined (SUPPORT_SID_INTERFACE)
959 IMG_SID hDevCookie;
960 IMG_SID hDevMemContext;
961#else
806 IMG_HANDLE hDevCookie; 962 IMG_HANDLE hDevCookie;
807 IMG_HANDLE hDevMemContext; 963 IMG_HANDLE hDevMemContext;
964#endif
808 IMG_VOID *pvLinAddr; 965 IMG_VOID *pvLinAddr;
809 IMG_SIZE_T ui32ByteSize; 966 IMG_SIZE_T ui32ByteSize;
810 IMG_SIZE_T ui32PageOffset; 967 IMG_SIZE_T ui32PageOffset;
@@ -815,7 +972,6 @@ typedef struct PVRSRV_BRIDGE_IN_WRAP_EXT_MEMORY_TAG
815 972
816}PVRSRV_BRIDGE_IN_WRAP_EXT_MEMORY; 973}PVRSRV_BRIDGE_IN_WRAP_EXT_MEMORY;
817 974
818
819typedef struct PVRSRV_BRIDGE_OUT_WRAP_EXT_MEMORY_TAG 975typedef struct PVRSRV_BRIDGE_OUT_WRAP_EXT_MEMORY_TAG
820{ 976{
821 PVRSRV_ERROR eError; 977 PVRSRV_ERROR eError;
@@ -824,11 +980,14 @@ typedef struct PVRSRV_BRIDGE_OUT_WRAP_EXT_MEMORY_TAG
824 980
825}PVRSRV_BRIDGE_OUT_WRAP_EXT_MEMORY; 981}PVRSRV_BRIDGE_OUT_WRAP_EXT_MEMORY;
826 982
827
828typedef struct PVRSRV_BRIDGE_IN_UNWRAP_EXT_MEMORY_TAG 983typedef struct PVRSRV_BRIDGE_IN_UNWRAP_EXT_MEMORY_TAG
829{ 984{
830 IMG_UINT32 ui32BridgeFlags; 985 IMG_UINT32 ui32BridgeFlags;
986#if defined (SUPPORT_SID_INTERFACE)
987 IMG_SID hKernelMemInfo;
988#else
831 IMG_HANDLE hKernelMemInfo; 989 IMG_HANDLE hKernelMemInfo;
990#endif
832 PVRSRV_CLIENT_MEM_INFO sClientMemInfo; 991 PVRSRV_CLIENT_MEM_INFO sClientMemInfo;
833 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo; 992 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo;
834 993
@@ -840,7 +999,6 @@ typedef struct PVRSRV_BRIDGE_IN_UNWRAP_EXT_MEMORY_TAG
840#define PVRSRV_MAX_DC_SWAPCHAIN_BUFFERS 4 999#define PVRSRV_MAX_DC_SWAPCHAIN_BUFFERS 4
841#define PVRSRV_MAX_DC_CLIP_RECTS 32 1000#define PVRSRV_MAX_DC_CLIP_RECTS 32
842 1001
843
844typedef struct PVRSRV_BRIDGE_OUT_ENUM_DISPCLASS_FORMATS_TAG 1002typedef struct PVRSRV_BRIDGE_OUT_ENUM_DISPCLASS_FORMATS_TAG
845{ 1003{
846 PVRSRV_ERROR eError; 1004 PVRSRV_ERROR eError;
@@ -850,17 +1008,19 @@ typedef struct PVRSRV_BRIDGE_OUT_ENUM_DISPCLASS_FORMATS_TAG
850}PVRSRV_BRIDGE_OUT_ENUM_DISPCLASS_FORMATS; 1008}PVRSRV_BRIDGE_OUT_ENUM_DISPCLASS_FORMATS;
851 1009
852 1010
853
854typedef struct PVRSRV_BRIDGE_IN_ENUM_DISPCLASS_DIMS_TAG 1011typedef struct PVRSRV_BRIDGE_IN_ENUM_DISPCLASS_DIMS_TAG
855{ 1012{
856 IMG_UINT32 ui32BridgeFlags; 1013 IMG_UINT32 ui32BridgeFlags;
1014#if defined (SUPPORT_SID_INTERFACE)
1015 IMG_SID hDeviceKM;
1016#else
857 IMG_HANDLE hDeviceKM; 1017 IMG_HANDLE hDeviceKM;
1018#endif
858 DISPLAY_FORMAT sFormat; 1019 DISPLAY_FORMAT sFormat;
859 1020
860}PVRSRV_BRIDGE_IN_ENUM_DISPCLASS_DIMS; 1021}PVRSRV_BRIDGE_IN_ENUM_DISPCLASS_DIMS;
861 1022
862 1023
863
864typedef struct PVRSRV_BRIDGE_OUT_ENUM_DISPCLASS_DIMS_TAG 1024typedef struct PVRSRV_BRIDGE_OUT_ENUM_DISPCLASS_DIMS_TAG
865{ 1025{
866 PVRSRV_ERROR eError; 1026 PVRSRV_ERROR eError;
@@ -870,7 +1030,6 @@ typedef struct PVRSRV_BRIDGE_OUT_ENUM_DISPCLASS_DIMS_TAG
870}PVRSRV_BRIDGE_OUT_ENUM_DISPCLASS_DIMS; 1030}PVRSRV_BRIDGE_OUT_ENUM_DISPCLASS_DIMS;
871 1031
872 1032
873
874typedef struct PVRSRV_BRIDGE_OUT_GET_DISPCLASS_INFO_TAG 1033typedef struct PVRSRV_BRIDGE_OUT_GET_DISPCLASS_INFO_TAG
875{ 1034{
876 PVRSRV_ERROR eError; 1035 PVRSRV_ERROR eError;
@@ -879,20 +1038,26 @@ typedef struct PVRSRV_BRIDGE_OUT_GET_DISPCLASS_INFO_TAG
879}PVRSRV_BRIDGE_OUT_GET_DISPCLASS_INFO; 1038}PVRSRV_BRIDGE_OUT_GET_DISPCLASS_INFO;
880 1039
881 1040
882
883typedef struct PVRSRV_BRIDGE_OUT_GET_DISPCLASS_SYSBUFFER_TAG 1041typedef struct PVRSRV_BRIDGE_OUT_GET_DISPCLASS_SYSBUFFER_TAG
884{ 1042{
885 PVRSRV_ERROR eError; 1043 PVRSRV_ERROR eError;
1044#if defined (SUPPORT_SID_INTERFACE)
1045 IMG_SID hBuffer;
1046#else
886 IMG_HANDLE hBuffer; 1047 IMG_HANDLE hBuffer;
1048#endif
887 1049
888}PVRSRV_BRIDGE_OUT_GET_DISPCLASS_SYSBUFFER; 1050}PVRSRV_BRIDGE_OUT_GET_DISPCLASS_SYSBUFFER;
889 1051
890 1052
891
892typedef struct PVRSRV_BRIDGE_IN_CREATE_DISPCLASS_SWAPCHAIN_TAG 1053typedef struct PVRSRV_BRIDGE_IN_CREATE_DISPCLASS_SWAPCHAIN_TAG
893{ 1054{
894 IMG_UINT32 ui32BridgeFlags; 1055 IMG_UINT32 ui32BridgeFlags;
1056#if defined (SUPPORT_SID_INTERFACE)
1057 IMG_SID hDeviceKM;
1058#else
895 IMG_HANDLE hDeviceKM; 1059 IMG_HANDLE hDeviceKM;
1060#endif
896 IMG_UINT32 ui32Flags; 1061 IMG_UINT32 ui32Flags;
897 DISPLAY_SURF_ATTRIBUTES sDstSurfAttrib; 1062 DISPLAY_SURF_ATTRIBUTES sDstSurfAttrib;
898 DISPLAY_SURF_ATTRIBUTES sSrcSurfAttrib; 1063 DISPLAY_SURF_ATTRIBUTES sSrcSurfAttrib;
@@ -903,112 +1068,151 @@ typedef struct PVRSRV_BRIDGE_IN_CREATE_DISPCLASS_SWAPCHAIN_TAG
903} PVRSRV_BRIDGE_IN_CREATE_DISPCLASS_SWAPCHAIN; 1068} PVRSRV_BRIDGE_IN_CREATE_DISPCLASS_SWAPCHAIN;
904 1069
905 1070
906
907typedef struct PVRSRV_BRIDGE_OUT_CREATE_DISPCLASS_SWAPCHAIN_TAG 1071typedef struct PVRSRV_BRIDGE_OUT_CREATE_DISPCLASS_SWAPCHAIN_TAG
908{ 1072{
909 PVRSRV_ERROR eError; 1073 PVRSRV_ERROR eError;
1074#if defined (SUPPORT_SID_INTERFACE)
1075 IMG_SID hSwapChain;
1076#else
910 IMG_HANDLE hSwapChain; 1077 IMG_HANDLE hSwapChain;
1078#endif
911 IMG_UINT32 ui32SwapChainID; 1079 IMG_UINT32 ui32SwapChainID;
912 1080
913} PVRSRV_BRIDGE_OUT_CREATE_DISPCLASS_SWAPCHAIN; 1081} PVRSRV_BRIDGE_OUT_CREATE_DISPCLASS_SWAPCHAIN;
914 1082
915 1083
916
917typedef struct PVRSRV_BRIDGE_IN_DESTROY_DISPCLASS_SWAPCHAIN_TAG 1084typedef struct PVRSRV_BRIDGE_IN_DESTROY_DISPCLASS_SWAPCHAIN_TAG
918{ 1085{
919 IMG_UINT32 ui32BridgeFlags; 1086 IMG_UINT32 ui32BridgeFlags;
1087#if defined (SUPPORT_SID_INTERFACE)
1088 IMG_SID hDeviceKM;
1089 IMG_SID hSwapChain;
1090#else
920 IMG_HANDLE hDeviceKM; 1091 IMG_HANDLE hDeviceKM;
921 IMG_HANDLE hSwapChain; 1092 IMG_HANDLE hSwapChain;
1093#endif
922 1094
923} PVRSRV_BRIDGE_IN_DESTROY_DISPCLASS_SWAPCHAIN; 1095} PVRSRV_BRIDGE_IN_DESTROY_DISPCLASS_SWAPCHAIN;
924 1096
925 1097
926
927typedef struct PVRSRV_BRIDGE_IN_SET_DISPCLASS_RECT_TAG 1098typedef struct PVRSRV_BRIDGE_IN_SET_DISPCLASS_RECT_TAG
928{ 1099{
929 IMG_UINT32 ui32BridgeFlags; 1100 IMG_UINT32 ui32BridgeFlags;
1101#if defined (SUPPORT_SID_INTERFACE)
1102 IMG_SID hDeviceKM;
1103 IMG_SID hSwapChain;
1104#else
930 IMG_HANDLE hDeviceKM; 1105 IMG_HANDLE hDeviceKM;
931 IMG_HANDLE hSwapChain; 1106 IMG_HANDLE hSwapChain;
1107#endif
932 IMG_RECT sRect; 1108 IMG_RECT sRect;
933 1109
934} PVRSRV_BRIDGE_IN_SET_DISPCLASS_RECT; 1110} PVRSRV_BRIDGE_IN_SET_DISPCLASS_RECT;
935 1111
936 1112
937
938typedef struct PVRSRV_BRIDGE_IN_SET_DISPCLASS_COLOURKEY_TAG 1113typedef struct PVRSRV_BRIDGE_IN_SET_DISPCLASS_COLOURKEY_TAG
939{ 1114{
940 IMG_UINT32 ui32BridgeFlags; 1115 IMG_UINT32 ui32BridgeFlags;
1116#if defined (SUPPORT_SID_INTERFACE)
1117 IMG_SID hDeviceKM;
1118 IMG_SID hSwapChain;
1119#else
941 IMG_HANDLE hDeviceKM; 1120 IMG_HANDLE hDeviceKM;
942 IMG_HANDLE hSwapChain; 1121 IMG_HANDLE hSwapChain;
1122#endif
943 IMG_UINT32 ui32CKColour; 1123 IMG_UINT32 ui32CKColour;
944 1124
945} PVRSRV_BRIDGE_IN_SET_DISPCLASS_COLOURKEY; 1125} PVRSRV_BRIDGE_IN_SET_DISPCLASS_COLOURKEY;
946 1126
947 1127
948
949typedef struct PVRSRV_BRIDGE_IN_GET_DISPCLASS_BUFFERS_TAG 1128typedef struct PVRSRV_BRIDGE_IN_GET_DISPCLASS_BUFFERS_TAG
950{ 1129{
951 IMG_UINT32 ui32BridgeFlags; 1130 IMG_UINT32 ui32BridgeFlags;
1131#if defined (SUPPORT_SID_INTERFACE)
1132 IMG_SID hDeviceKM;
1133 IMG_SID hSwapChain;
1134#else
952 IMG_HANDLE hDeviceKM; 1135 IMG_HANDLE hDeviceKM;
953 IMG_HANDLE hSwapChain; 1136 IMG_HANDLE hSwapChain;
1137#endif
954 1138
955} PVRSRV_BRIDGE_IN_GET_DISPCLASS_BUFFERS; 1139} PVRSRV_BRIDGE_IN_GET_DISPCLASS_BUFFERS;
956 1140
957 1141
958
959typedef struct PVRSRV_BRIDGE_OUT_GET_DISPCLASS_BUFFERS_TAG 1142typedef struct PVRSRV_BRIDGE_OUT_GET_DISPCLASS_BUFFERS_TAG
960{ 1143{
961 PVRSRV_ERROR eError; 1144 PVRSRV_ERROR eError;
962 IMG_UINT32 ui32BufferCount; 1145 IMG_UINT32 ui32BufferCount;
1146#if defined (SUPPORT_SID_INTERFACE)
1147 IMG_SID ahBuffer[PVRSRV_MAX_DC_SWAPCHAIN_BUFFERS];
1148#else
963 IMG_HANDLE ahBuffer[PVRSRV_MAX_DC_SWAPCHAIN_BUFFERS]; 1149 IMG_HANDLE ahBuffer[PVRSRV_MAX_DC_SWAPCHAIN_BUFFERS];
1150#endif
964 1151
965} PVRSRV_BRIDGE_OUT_GET_DISPCLASS_BUFFERS; 1152} PVRSRV_BRIDGE_OUT_GET_DISPCLASS_BUFFERS;
966 1153
967 1154
968
969typedef struct PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_BUFFER_TAG 1155typedef struct PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_BUFFER_TAG
970{ 1156{
971 IMG_UINT32 ui32BridgeFlags; 1157 IMG_UINT32 ui32BridgeFlags;
1158#if defined (SUPPORT_SID_INTERFACE)
1159 IMG_SID hDeviceKM;
1160 IMG_SID hBuffer;
1161#else
972 IMG_HANDLE hDeviceKM; 1162 IMG_HANDLE hDeviceKM;
973 IMG_HANDLE hBuffer; 1163 IMG_HANDLE hBuffer;
1164#endif
974 IMG_UINT32 ui32SwapInterval; 1165 IMG_UINT32 ui32SwapInterval;
1166#if defined (SUPPORT_SID_INTERFACE)
1167 IMG_SID hPrivateTag;
1168#else
975 IMG_HANDLE hPrivateTag; 1169 IMG_HANDLE hPrivateTag;
1170#endif
976 IMG_UINT32 ui32ClipRectCount; 1171 IMG_UINT32 ui32ClipRectCount;
977 IMG_RECT sClipRect[PVRSRV_MAX_DC_CLIP_RECTS]; 1172 IMG_RECT sClipRect[PVRSRV_MAX_DC_CLIP_RECTS];
978 1173
979} PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_BUFFER; 1174} PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_BUFFER;
980 1175
981 1176
982
983typedef struct PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_SYSTEM_TAG 1177typedef struct PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_SYSTEM_TAG
984{ 1178{
985 IMG_UINT32 ui32BridgeFlags; 1179 IMG_UINT32 ui32BridgeFlags;
1180#if defined (SUPPORT_SID_INTERFACE)
1181 IMG_SID hDeviceKM;
1182 IMG_SID hSwapChain;
1183#else
986 IMG_HANDLE hDeviceKM; 1184 IMG_HANDLE hDeviceKM;
987 IMG_HANDLE hSwapChain; 1185 IMG_HANDLE hSwapChain;
1186#endif
988 1187
989} PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_SYSTEM; 1188} PVRSRV_BRIDGE_IN_SWAP_DISPCLASS_TO_SYSTEM;
990 1189
991 1190
992
993typedef struct PVRSRV_BRIDGE_IN_OPEN_BUFFERCLASS_DEVICE_TAG 1191typedef struct PVRSRV_BRIDGE_IN_OPEN_BUFFERCLASS_DEVICE_TAG
994{ 1192{
995 IMG_UINT32 ui32BridgeFlags; 1193 IMG_UINT32 ui32BridgeFlags;
996 IMG_UINT32 ui32DeviceID; 1194 IMG_UINT32 ui32DeviceID;
1195#if defined (SUPPORT_SID_INTERFACE)
1196 IMG_SID hDevCookie;
1197#else
997 IMG_HANDLE hDevCookie; 1198 IMG_HANDLE hDevCookie;
998 1199#endif
1200
999} PVRSRV_BRIDGE_IN_OPEN_BUFFERCLASS_DEVICE; 1201} PVRSRV_BRIDGE_IN_OPEN_BUFFERCLASS_DEVICE;
1000 1202
1001 1203
1002
1003typedef struct PVRSRV_BRIDGE_OUT_OPEN_BUFFERCLASS_DEVICE_TAG 1204typedef struct PVRSRV_BRIDGE_OUT_OPEN_BUFFERCLASS_DEVICE_TAG
1004{ 1205{
1005 PVRSRV_ERROR eError; 1206 PVRSRV_ERROR eError;
1207#if defined (SUPPORT_SID_INTERFACE)
1208 IMG_SID hDeviceKM;
1209#else
1006 IMG_HANDLE hDeviceKM; 1210 IMG_HANDLE hDeviceKM;
1211#endif
1007 1212
1008} PVRSRV_BRIDGE_OUT_OPEN_BUFFERCLASS_DEVICE; 1213} PVRSRV_BRIDGE_OUT_OPEN_BUFFERCLASS_DEVICE;
1009 1214
1010 1215
1011
1012typedef struct PVRSRV_BRIDGE_OUT_GET_BUFFERCLASS_INFO_TAG 1216typedef struct PVRSRV_BRIDGE_OUT_GET_BUFFERCLASS_INFO_TAG
1013{ 1217{
1014 PVRSRV_ERROR eError; 1218 PVRSRV_ERROR eError;
@@ -1017,26 +1221,31 @@ typedef struct PVRSRV_BRIDGE_OUT_GET_BUFFERCLASS_INFO_TAG
1017} PVRSRV_BRIDGE_OUT_GET_BUFFERCLASS_INFO; 1221} PVRSRV_BRIDGE_OUT_GET_BUFFERCLASS_INFO;
1018 1222
1019 1223
1020
1021typedef struct PVRSRV_BRIDGE_IN_GET_BUFFERCLASS_BUFFER_TAG 1224typedef struct PVRSRV_BRIDGE_IN_GET_BUFFERCLASS_BUFFER_TAG
1022{ 1225{
1023 IMG_UINT32 ui32BridgeFlags; 1226 IMG_UINT32 ui32BridgeFlags;
1227#if defined (SUPPORT_SID_INTERFACE)
1228 IMG_SID hDeviceKM;
1229#else
1024 IMG_HANDLE hDeviceKM; 1230 IMG_HANDLE hDeviceKM;
1025 IMG_UINT32 ui32BufferIndex; 1231#endif
1232 IMG_UINT32 ui32BufferIndex;
1026 1233
1027} PVRSRV_BRIDGE_IN_GET_BUFFERCLASS_BUFFER; 1234} PVRSRV_BRIDGE_IN_GET_BUFFERCLASS_BUFFER;
1028 1235
1029 1236
1030
1031typedef struct PVRSRV_BRIDGE_OUT_GET_BUFFERCLASS_BUFFER_TAG 1237typedef struct PVRSRV_BRIDGE_OUT_GET_BUFFERCLASS_BUFFER_TAG
1032{ 1238{
1033 PVRSRV_ERROR eError; 1239 PVRSRV_ERROR eError;
1240#if defined (SUPPORT_SID_INTERFACE)
1241 IMG_SID hBuffer;
1242#else
1034 IMG_HANDLE hBuffer; 1243 IMG_HANDLE hBuffer;
1244#endif
1035 1245
1036} PVRSRV_BRIDGE_OUT_GET_BUFFERCLASS_BUFFER; 1246} PVRSRV_BRIDGE_OUT_GET_BUFFERCLASS_BUFFER;
1037 1247
1038 1248
1039
1040typedef struct PVRSRV_BRIDGE_OUT_GET_DEVMEM_HEAPINFO_TAG 1249typedef struct PVRSRV_BRIDGE_OUT_GET_DEVMEM_HEAPINFO_TAG
1041{ 1250{
1042 PVRSRV_ERROR eError; 1251 PVRSRV_ERROR eError;
@@ -1046,42 +1255,54 @@ typedef struct PVRSRV_BRIDGE_OUT_GET_DEVMEM_HEAPINFO_TAG
1046} PVRSRV_BRIDGE_OUT_GET_DEVMEM_HEAPINFO; 1255} PVRSRV_BRIDGE_OUT_GET_DEVMEM_HEAPINFO;
1047 1256
1048 1257
1049
1050typedef struct PVRSRV_BRIDGE_OUT_CREATE_DEVMEMCONTEXT_TAG 1258typedef struct PVRSRV_BRIDGE_OUT_CREATE_DEVMEMCONTEXT_TAG
1051{ 1259{
1052 PVRSRV_ERROR eError; 1260 PVRSRV_ERROR eError;
1261#if defined (SUPPORT_SID_INTERFACE)
1262 IMG_SID hDevMemContext;
1263#else
1053 IMG_HANDLE hDevMemContext; 1264 IMG_HANDLE hDevMemContext;
1265#endif
1054 IMG_UINT32 ui32ClientHeapCount; 1266 IMG_UINT32 ui32ClientHeapCount;
1055 PVRSRV_HEAP_INFO sHeapInfo[PVRSRV_MAX_CLIENT_HEAPS]; 1267 PVRSRV_HEAP_INFO sHeapInfo[PVRSRV_MAX_CLIENT_HEAPS];
1056 1268
1057} PVRSRV_BRIDGE_OUT_CREATE_DEVMEMCONTEXT; 1269} PVRSRV_BRIDGE_OUT_CREATE_DEVMEMCONTEXT;
1058 1270
1059 1271
1060
1061typedef struct PVRSRV_BRIDGE_OUT_CREATE_DEVMEMHEAP_TAG 1272typedef struct PVRSRV_BRIDGE_OUT_CREATE_DEVMEMHEAP_TAG
1062{ 1273{
1063 PVRSRV_ERROR eError; 1274 PVRSRV_ERROR eError;
1275#if defined (SUPPORT_SID_INTERFACE)
1276 IMG_SID hDevMemHeap;
1277#else
1064 IMG_HANDLE hDevMemHeap; 1278 IMG_HANDLE hDevMemHeap;
1279#endif
1065 1280
1066} PVRSRV_BRIDGE_OUT_CREATE_DEVMEMHEAP; 1281} PVRSRV_BRIDGE_OUT_CREATE_DEVMEMHEAP;
1067 1282
1068 1283
1069
1070typedef struct PVRSRV_BRIDGE_OUT_ALLOCDEVICEMEM_TAG 1284typedef struct PVRSRV_BRIDGE_OUT_ALLOCDEVICEMEM_TAG
1071{ 1285{
1072 PVRSRV_ERROR eError; 1286 PVRSRV_ERROR eError;
1287#if defined (SUPPORT_SID_INTERFACE)
1288 IMG_SID hKernelMemInfo;
1289#else
1073 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 1290 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
1074 PVRSRV_CLIENT_MEM_INFO sClientMemInfo; 1291#endif
1075 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo; 1292 PVRSRV_CLIENT_MEM_INFO sClientMemInfo;
1293 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo;
1076 1294
1077} PVRSRV_BRIDGE_OUT_ALLOCDEVICEMEM; 1295} PVRSRV_BRIDGE_OUT_ALLOCDEVICEMEM;
1078 1296
1079 1297
1080
1081typedef struct PVRSRV_BRIDGE_OUT_EXPORTDEVICEMEM_TAG 1298typedef struct PVRSRV_BRIDGE_OUT_EXPORTDEVICEMEM_TAG
1082{ 1299{
1083 PVRSRV_ERROR eError; 1300 PVRSRV_ERROR eError;
1301#if defined (SUPPORT_SID_INTERFACE)
1302 IMG_SID hMemInfo;
1303#else
1084 IMG_HANDLE hMemInfo; 1304 IMG_HANDLE hMemInfo;
1305#endif
1085#if defined(SUPPORT_MEMINFO_IDS) 1306#if defined(SUPPORT_MEMINFO_IDS)
1086 IMG_UINT64 ui64Stamp; 1307 IMG_UINT64 ui64Stamp;
1087#endif 1308#endif
@@ -1093,12 +1314,15 @@ typedef struct PVRSRV_BRIDGE_OUT_MAPMEMINFOTOUSER_TAG
1093{ 1314{
1094 PVRSRV_ERROR eError; 1315 PVRSRV_ERROR eError;
1095 IMG_PVOID pvLinAddr; 1316 IMG_PVOID pvLinAddr;
1317#if defined (SUPPORT_SID_INTERFACE)
1318 IMG_SID hMappingInfo;
1319#else
1096 IMG_HANDLE hMappingInfo; 1320 IMG_HANDLE hMappingInfo;
1321#endif
1097 1322
1098}PVRSRV_BRIDGE_OUT_MAPMEMINFOTOUSER; 1323}PVRSRV_BRIDGE_OUT_MAPMEMINFOTOUSER;
1099 1324
1100 1325
1101
1102typedef struct PVRSRV_BRIDGE_OUT_GETFREEDEVICEMEM_TAG 1326typedef struct PVRSRV_BRIDGE_OUT_GETFREEDEVICEMEM_TAG
1103{ 1327{
1104 PVRSRV_ERROR eError; 1328 PVRSRV_ERROR eError;
@@ -1113,7 +1337,7 @@ typedef struct PVRSRV_BRIDGE_OUT_GETFREEDEVICEMEM_TAG
1113typedef struct PVRSRV_BRIDGE_OUT_MHANDLE_TO_MMAP_DATA_TAG 1337typedef struct PVRSRV_BRIDGE_OUT_MHANDLE_TO_MMAP_DATA_TAG
1114{ 1338{
1115 PVRSRV_ERROR eError; 1339 PVRSRV_ERROR eError;
1116 1340
1117 1341
1118 IMG_UINT32 ui32MMapOffset; 1342 IMG_UINT32 ui32MMapOffset;
1119 1343
@@ -1131,7 +1355,7 @@ typedef struct PVRSRV_BRIDGE_OUT_MHANDLE_TO_MMAP_DATA_TAG
1131typedef struct PVRSRV_BRIDGE_OUT_RELEASE_MMAP_DATA_TAG 1355typedef struct PVRSRV_BRIDGE_OUT_RELEASE_MMAP_DATA_TAG
1132{ 1356{
1133 PVRSRV_ERROR eError; 1357 PVRSRV_ERROR eError;
1134 1358
1135 1359
1136 IMG_BOOL bMUnmap; 1360 IMG_BOOL bMUnmap;
1137 1361
@@ -1141,7 +1365,6 @@ typedef struct PVRSRV_BRIDGE_OUT_RELEASE_MMAP_DATA_TAG
1141 1365
1142 IMG_UINT32 ui32RealByteSize; 1366 IMG_UINT32 ui32RealByteSize;
1143} PVRSRV_BRIDGE_OUT_RELEASE_MMAP_DATA; 1367} PVRSRV_BRIDGE_OUT_RELEASE_MMAP_DATA;
1144
1145typedef struct PVRSRV_BRIDGE_IN_GET_MISC_INFO_TAG 1368typedef struct PVRSRV_BRIDGE_IN_GET_MISC_INFO_TAG
1146{ 1369{
1147 IMG_UINT32 ui32BridgeFlags; 1370 IMG_UINT32 ui32BridgeFlags;
@@ -1150,7 +1373,6 @@ typedef struct PVRSRV_BRIDGE_IN_GET_MISC_INFO_TAG
1150}PVRSRV_BRIDGE_IN_GET_MISC_INFO; 1373}PVRSRV_BRIDGE_IN_GET_MISC_INFO;
1151 1374
1152 1375
1153
1154typedef struct PVRSRV_BRIDGE_OUT_GET_MISC_INFO_TAG 1376typedef struct PVRSRV_BRIDGE_OUT_GET_MISC_INFO_TAG
1155{ 1377{
1156 PVRSRV_ERROR eError; 1378 PVRSRV_ERROR eError;
@@ -1159,7 +1381,6 @@ typedef struct PVRSRV_BRIDGE_OUT_GET_MISC_INFO_TAG
1159}PVRSRV_BRIDGE_OUT_GET_MISC_INFO; 1381}PVRSRV_BRIDGE_OUT_GET_MISC_INFO;
1160 1382
1161 1383
1162
1163typedef struct PVRSRV_BRIDGE_IN_RELEASE_MISC_INFO_TAG 1384typedef struct PVRSRV_BRIDGE_IN_RELEASE_MISC_INFO_TAG
1164{ 1385{
1165 IMG_UINT32 ui32BridgeFlags; 1386 IMG_UINT32 ui32BridgeFlags;
@@ -1168,7 +1389,6 @@ typedef struct PVRSRV_BRIDGE_IN_RELEASE_MISC_INFO_TAG
1168}PVRSRV_BRIDGE_IN_RELEASE_MISC_INFO; 1389}PVRSRV_BRIDGE_IN_RELEASE_MISC_INFO;
1169 1390
1170 1391
1171
1172typedef struct PVRSRV_BRIDGE_OUT_RELEASE_MISC_INFO_TAG 1392typedef struct PVRSRV_BRIDGE_OUT_RELEASE_MISC_INFO_TAG
1173{ 1393{
1174 PVRSRV_ERROR eError; 1394 PVRSRV_ERROR eError;
@@ -1177,8 +1397,6 @@ typedef struct PVRSRV_BRIDGE_OUT_RELEASE_MISC_INFO_TAG
1177}PVRSRV_BRIDGE_OUT_RELEASE_MISC_INFO; 1397}PVRSRV_BRIDGE_OUT_RELEASE_MISC_INFO;
1178 1398
1179 1399
1180
1181
1182typedef struct PVRSRV_BRIDGE_OUT_PDUMP_ISCAPTURING_TAG 1400typedef struct PVRSRV_BRIDGE_OUT_PDUMP_ISCAPTURING_TAG
1183{ 1401{
1184 PVRSRV_ERROR eError; 1402 PVRSRV_ERROR eError;
@@ -1186,8 +1404,7 @@ typedef struct PVRSRV_BRIDGE_OUT_PDUMP_ISCAPTURING_TAG
1186 1404
1187} PVRSRV_BRIDGE_OUT_PDUMP_ISCAPTURING; 1405} PVRSRV_BRIDGE_OUT_PDUMP_ISCAPTURING;
1188 1406
1189 1407typedef struct PVRSRV_BRIDGE_IN_GET_FB_STATS_TAG
1190typedef struct PVRSRV_BRIDGE_IN_GET_FB_STATS_TAG
1191{ 1408{
1192 IMG_UINT32 ui32BridgeFlags; 1409 IMG_UINT32 ui32BridgeFlags;
1193 IMG_SIZE_T ui32Total; 1410 IMG_SIZE_T ui32Total;
@@ -1196,18 +1413,20 @@ typedef struct PVRSRV_BRIDGE_IN_GET_FB_STATS_TAG
1196} PVRSRV_BRIDGE_IN_GET_FB_STATS; 1413} PVRSRV_BRIDGE_IN_GET_FB_STATS;
1197 1414
1198 1415
1199
1200typedef struct PVRSRV_BRIDGE_IN_MAPPHYSTOUSERSPACE_TAG 1416typedef struct PVRSRV_BRIDGE_IN_MAPPHYSTOUSERSPACE_TAG
1201{ 1417{
1202 IMG_UINT32 ui32BridgeFlags; 1418 IMG_UINT32 ui32BridgeFlags;
1419#if defined (SUPPORT_SID_INTERFACE)
1420 IMG_SID hDevCookie;
1421#else
1203 IMG_HANDLE hDevCookie; 1422 IMG_HANDLE hDevCookie;
1423#endif
1204 IMG_SYS_PHYADDR sSysPhysAddr; 1424 IMG_SYS_PHYADDR sSysPhysAddr;
1205 IMG_UINT32 uiSizeInBytes; 1425 IMG_UINT32 uiSizeInBytes;
1206 1426
1207} PVRSRV_BRIDGE_IN_MAPPHYSTOUSERSPACE; 1427} PVRSRV_BRIDGE_IN_MAPPHYSTOUSERSPACE;
1208 1428
1209 1429
1210
1211typedef struct PVRSRV_BRIDGE_OUT_MAPPHYSTOUSERSPACE_TAG 1430typedef struct PVRSRV_BRIDGE_OUT_MAPPHYSTOUSERSPACE_TAG
1212{ 1431{
1213 IMG_PVOID pvUserAddr; 1432 IMG_PVOID pvUserAddr;
@@ -1217,18 +1436,20 @@ typedef struct PVRSRV_BRIDGE_OUT_MAPPHYSTOUSERSPACE_TAG
1217} PVRSRV_BRIDGE_OUT_MAPPHYSTOUSERSPACE; 1436} PVRSRV_BRIDGE_OUT_MAPPHYSTOUSERSPACE;
1218 1437
1219 1438
1220
1221typedef struct PVRSRV_BRIDGE_IN_UNMAPPHYSTOUSERSPACE_TAG 1439typedef struct PVRSRV_BRIDGE_IN_UNMAPPHYSTOUSERSPACE_TAG
1222{ 1440{
1223 IMG_UINT32 ui32BridgeFlags; 1441 IMG_UINT32 ui32BridgeFlags;
1442#if defined (SUPPORT_SID_INTERFACE)
1443 IMG_SID hDevCookie;
1444#else
1224 IMG_HANDLE hDevCookie; 1445 IMG_HANDLE hDevCookie;
1446#endif
1225 IMG_PVOID pvUserAddr; 1447 IMG_PVOID pvUserAddr;
1226 IMG_PVOID pvProcess; 1448 IMG_PVOID pvProcess;
1227 1449
1228} PVRSRV_BRIDGE_IN_UNMAPPHYSTOUSERSPACE; 1450} PVRSRV_BRIDGE_IN_UNMAPPHYSTOUSERSPACE;
1229 1451
1230 1452
1231
1232typedef struct PVRSRV_BRIDGE_OUT_GETPHYSTOUSERSPACEMAP_TAG 1453typedef struct PVRSRV_BRIDGE_OUT_GETPHYSTOUSERSPACEMAP_TAG
1233{ 1454{
1234 IMG_PVOID *ppvTbl; 1455 IMG_PVOID *ppvTbl;
@@ -1237,7 +1458,7 @@ typedef struct PVRSRV_BRIDGE_OUT_GETPHYSTOUSERSPACEMAP_TAG
1237} PVRSRV_BRIDGE_OUT_GETPHYSTOUSERSPACEMAP; 1458} PVRSRV_BRIDGE_OUT_GETPHYSTOUSERSPACEMAP;
1238 1459
1239 1460
1240 1461#if !defined (SUPPORT_SID_INTERFACE)
1241typedef struct PVRSRV_BRIDGE_IN_REGISTER_SIM_PROCESS_TAG 1462typedef struct PVRSRV_BRIDGE_IN_REGISTER_SIM_PROCESS_TAG
1242{ 1463{
1243 IMG_UINT32 ui32BridgeFlags; 1464 IMG_UINT32 ui32BridgeFlags;
@@ -1275,6 +1496,7 @@ typedef struct PVRSRV_BRIDGE_IN_PROCESS_SIMISR_EVENT_TAG
1275 PVRSRV_ERROR eError; 1496 PVRSRV_ERROR eError;
1276 1497
1277} PVRSRV_BRIDGE_IN_PROCESS_SIMISR_EVENT; 1498} PVRSRV_BRIDGE_IN_PROCESS_SIMISR_EVENT;
1499#endif
1278 1500
1279typedef struct PVRSRV_BRIDGE_IN_INITSRV_DISCONNECT_TAG 1501typedef struct PVRSRV_BRIDGE_IN_INITSRV_DISCONNECT_TAG
1280{ 1502{
@@ -1292,16 +1514,24 @@ typedef struct PVRSRV_BRIDGE_IN_ALLOC_SHARED_SYS_MEM_TAG
1292 1514
1293typedef struct PVRSRV_BRIDGE_OUT_ALLOC_SHARED_SYS_MEM_TAG 1515typedef struct PVRSRV_BRIDGE_OUT_ALLOC_SHARED_SYS_MEM_TAG
1294{ 1516{
1295 PVRSRV_ERROR eError; 1517 PVRSRV_ERROR eError;
1518#if defined (SUPPORT_SID_INTERFACE)
1519#else
1296 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 1520 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
1297 PVRSRV_CLIENT_MEM_INFO sClientMemInfo; 1521#endif
1522 PVRSRV_CLIENT_MEM_INFO sClientMemInfo;
1298}PVRSRV_BRIDGE_OUT_ALLOC_SHARED_SYS_MEM; 1523}PVRSRV_BRIDGE_OUT_ALLOC_SHARED_SYS_MEM;
1299 1524
1300typedef struct PVRSRV_BRIDGE_IN_FREE_SHARED_SYS_MEM_TAG 1525typedef struct PVRSRV_BRIDGE_IN_FREE_SHARED_SYS_MEM_TAG
1301{ 1526{
1302 IMG_UINT32 ui32BridgeFlags; 1527#if defined (SUPPORT_SID_INTERFACE)
1528 IMG_SID hKernelMemInfo;
1529 IMG_SID hMappingInfo;
1530#else
1531 IMG_UINT32 ui32BridgeFlags;
1303 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 1532 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
1304 PVRSRV_CLIENT_MEM_INFO sClientMemInfo; 1533#endif
1534 PVRSRV_CLIENT_MEM_INFO sClientMemInfo;
1305}PVRSRV_BRIDGE_IN_FREE_SHARED_SYS_MEM; 1535}PVRSRV_BRIDGE_IN_FREE_SHARED_SYS_MEM;
1306 1536
1307typedef struct PVRSRV_BRIDGE_OUT_FREE_SHARED_SYS_MEM_TAG 1537typedef struct PVRSRV_BRIDGE_OUT_FREE_SHARED_SYS_MEM_TAG
@@ -1312,14 +1542,22 @@ typedef struct PVRSRV_BRIDGE_OUT_FREE_SHARED_SYS_MEM_TAG
1312typedef struct PVRSRV_BRIDGE_IN_MAP_MEMINFO_MEM_TAG 1542typedef struct PVRSRV_BRIDGE_IN_MAP_MEMINFO_MEM_TAG
1313{ 1543{
1314 IMG_UINT32 ui32BridgeFlags; 1544 IMG_UINT32 ui32BridgeFlags;
1545#if defined (SUPPORT_SID_INTERFACE)
1546 IMG_SID hKernelMemInfo;
1547#else
1315 IMG_HANDLE hKernelMemInfo; 1548 IMG_HANDLE hKernelMemInfo;
1549#endif
1316}PVRSRV_BRIDGE_IN_MAP_MEMINFO_MEM; 1550}PVRSRV_BRIDGE_IN_MAP_MEMINFO_MEM;
1317 1551
1318typedef struct PVRSRV_BRIDGE_OUT_MAP_MEMINFO_MEM_TAG 1552typedef struct PVRSRV_BRIDGE_OUT_MAP_MEMINFO_MEM_TAG
1319{ 1553{
1320 PVRSRV_CLIENT_MEM_INFO sClientMemInfo; 1554 PVRSRV_CLIENT_MEM_INFO sClientMemInfo;
1321 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo; 1555 PVRSRV_CLIENT_SYNC_INFO sClientSyncInfo;
1556#if defined (SUPPORT_SID_INTERFACE)
1557 IMG_SID hKernelMemInfo;
1558#else
1322 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 1559 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
1560#endif
1323 PVRSRV_ERROR eError; 1561 PVRSRV_ERROR eError;
1324}PVRSRV_BRIDGE_OUT_MAP_MEMINFO_MEM; 1562}PVRSRV_BRIDGE_OUT_MAP_MEMINFO_MEM;
1325 1563
@@ -1337,7 +1575,11 @@ typedef struct PVRSRV_BRIDGE_OUT_UNMAP_MEMINFO_MEM_TAG
1337typedef struct PVRSRV_BRIDGE_IN_GETMMU_PD_DEVPADDR_TAG 1575typedef struct PVRSRV_BRIDGE_IN_GETMMU_PD_DEVPADDR_TAG
1338{ 1576{
1339 IMG_UINT32 ui32BridgeFlags; 1577 IMG_UINT32 ui32BridgeFlags;
1578#if defined (SUPPORT_SID_INTERFACE)
1579 IMG_SID hDevMemContext;
1580#else
1340 IMG_HANDLE hDevMemContext; 1581 IMG_HANDLE hDevMemContext;
1582#endif
1341}PVRSRV_BRIDGE_IN_GETMMU_PD_DEVPADDR; 1583}PVRSRV_BRIDGE_IN_GETMMU_PD_DEVPADDR;
1342 1584
1343typedef struct PVRSRV_BRIDGE_OUT_GETMMU_PD_DEVPADDR_TAG 1585typedef struct PVRSRV_BRIDGE_OUT_GETMMU_PD_DEVPADDR_TAG
@@ -1349,7 +1591,11 @@ typedef struct PVRSRV_BRIDGE_OUT_GETMMU_PD_DEVPADDR_TAG
1349typedef struct PVRSRV_BRIDGE_IN_EVENT_OBJECT_WAI_TAG 1591typedef struct PVRSRV_BRIDGE_IN_EVENT_OBJECT_WAI_TAG
1350{ 1592{
1351 IMG_UINT32 ui32BridgeFlags; 1593 IMG_UINT32 ui32BridgeFlags;
1594#if defined (SUPPORT_SID_INTERFACE)
1595 IMG_SID hOSEventKM;
1596#else
1352 IMG_HANDLE hOSEventKM; 1597 IMG_HANDLE hOSEventKM;
1598#endif
1353} PVRSRV_BRIDGE_IN_EVENT_OBJECT_WAIT; 1599} PVRSRV_BRIDGE_IN_EVENT_OBJECT_WAIT;
1354 1600
1355typedef struct PVRSRV_BRIDGE_IN_EVENT_OBJECT_OPEN_TAG 1601typedef struct PVRSRV_BRIDGE_IN_EVENT_OBJECT_OPEN_TAG
@@ -1359,35 +1605,56 @@ typedef struct PVRSRV_BRIDGE_IN_EVENT_OBJECT_OPEN_TAG
1359 1605
1360typedef struct PVRSRV_BRIDGE_OUT_EVENT_OBJECT_OPEN_TAG 1606typedef struct PVRSRV_BRIDGE_OUT_EVENT_OBJECT_OPEN_TAG
1361{ 1607{
1608#if defined (SUPPORT_SID_INTERFACE)
1609 IMG_UINT32 hOSEvent;
1610#else
1362 IMG_HANDLE hOSEvent; 1611 IMG_HANDLE hOSEvent;
1612#endif
1363 PVRSRV_ERROR eError; 1613 PVRSRV_ERROR eError;
1364} PVRSRV_BRIDGE_OUT_EVENT_OBJECT_OPEN; 1614} PVRSRV_BRIDGE_OUT_EVENT_OBJECT_OPEN;
1365 1615
1366typedef struct PVRSRV_BRIDGE_IN_EVENT_OBJECT_CLOSE_TAG 1616typedef struct PVRSRV_BRIDGE_IN_EVENT_OBJECT_CLOSE_TAG
1367{ 1617{
1368 PVRSRV_EVENTOBJECT sEventObject; 1618 PVRSRV_EVENTOBJECT sEventObject;
1619#if defined (SUPPORT_SID_INTERFACE)
1620 IMG_SID hOSEventKM;
1621#else
1369 IMG_HANDLE hOSEventKM; 1622 IMG_HANDLE hOSEventKM;
1623#endif
1370} PVRSRV_BRIDGE_IN_EVENT_OBJECT_CLOSE; 1624} PVRSRV_BRIDGE_IN_EVENT_OBJECT_CLOSE;
1371 1625
1372typedef struct PVRSRV_BRIDGE_OUT_CREATE_SYNC_INFO_MOD_OBJ_TAG 1626typedef struct PVRSRV_BRIDGE_OUT_CREATE_SYNC_INFO_MOD_OBJ_TAG
1373{ 1627{
1374 PVRSRV_ERROR eError; 1628 PVRSRV_ERROR eError;
1375 1629
1630#if defined (SUPPORT_SID_INTERFACE)
1631 IMG_SID hKernelSyncInfoModObj;
1632#else
1376 IMG_HANDLE hKernelSyncInfoModObj; 1633 IMG_HANDLE hKernelSyncInfoModObj;
1634#endif
1377 1635
1378} PVRSRV_BRIDGE_OUT_CREATE_SYNC_INFO_MOD_OBJ; 1636} PVRSRV_BRIDGE_OUT_CREATE_SYNC_INFO_MOD_OBJ;
1379 1637
1380typedef struct PVRSRV_BRIDGE_IN_DESTROY_SYNC_INFO_MOD_OBJ 1638typedef struct PVRSRV_BRIDGE_IN_DESTROY_SYNC_INFO_MOD_OBJ
1381{ 1639{
1382 IMG_UINT32 ui32BridgeFlags; 1640 IMG_UINT32 ui32BridgeFlags;
1641#if defined (SUPPORT_SID_INTERFACE)
1642 IMG_SID hKernelSyncInfoModObj;
1643#else
1383 IMG_HANDLE hKernelSyncInfoModObj; 1644 IMG_HANDLE hKernelSyncInfoModObj;
1645#endif
1384} PVRSRV_BRIDGE_IN_DESTROY_SYNC_INFO_MOD_OBJ; 1646} PVRSRV_BRIDGE_IN_DESTROY_SYNC_INFO_MOD_OBJ;
1385 1647
1386typedef struct PVRSRV_BRIDGE_IN_MODIFY_PENDING_SYNC_OPS_TAG 1648typedef struct PVRSRV_BRIDGE_IN_MODIFY_PENDING_SYNC_OPS_TAG
1387{ 1649{
1388 IMG_UINT32 ui32BridgeFlags; 1650 IMG_UINT32 ui32BridgeFlags;
1651#if defined (SUPPORT_SID_INTERFACE)
1652 IMG_SID hKernelSyncInfoModObj;
1653 IMG_SID hKernelSyncInfo;
1654#else
1389 IMG_HANDLE hKernelSyncInfoModObj; 1655 IMG_HANDLE hKernelSyncInfoModObj;
1390 IMG_HANDLE hKernelSyncInfo; 1656 IMG_HANDLE hKernelSyncInfo;
1657#endif
1391 IMG_UINT32 ui32ModifyFlags; 1658 IMG_UINT32 ui32ModifyFlags;
1392 1659
1393} PVRSRV_BRIDGE_IN_MODIFY_PENDING_SYNC_OPS; 1660} PVRSRV_BRIDGE_IN_MODIFY_PENDING_SYNC_OPS;
@@ -1395,7 +1662,11 @@ typedef struct PVRSRV_BRIDGE_IN_MODIFY_PENDING_SYNC_OPS_TAG
1395typedef struct PVRSRV_BRIDGE_IN_MODIFY_COMPLETE_SYNC_OPS_TAG 1662typedef struct PVRSRV_BRIDGE_IN_MODIFY_COMPLETE_SYNC_OPS_TAG
1396{ 1663{
1397 IMG_UINT32 ui32BridgeFlags; 1664 IMG_UINT32 ui32BridgeFlags;
1665#if defined (SUPPORT_SID_INTERFACE)
1666 IMG_SID hKernelSyncInfoModObj;
1667#else
1398 IMG_HANDLE hKernelSyncInfoModObj; 1668 IMG_HANDLE hKernelSyncInfoModObj;
1669#endif
1399} PVRSRV_BRIDGE_IN_MODIFY_COMPLETE_SYNC_OPS; 1670} PVRSRV_BRIDGE_IN_MODIFY_COMPLETE_SYNC_OPS;
1400 1671
1401typedef struct PVRSRV_BRIDGE_OUT_MODIFY_PENDING_SYNC_OPS_TAG 1672typedef struct PVRSRV_BRIDGE_OUT_MODIFY_PENDING_SYNC_OPS_TAG
@@ -1408,16 +1679,56 @@ typedef struct PVRSRV_BRIDGE_OUT_MODIFY_PENDING_SYNC_OPS_TAG
1408 1679
1409} PVRSRV_BRIDGE_OUT_MODIFY_PENDING_SYNC_OPS; 1680} PVRSRV_BRIDGE_OUT_MODIFY_PENDING_SYNC_OPS;
1410 1681
1682typedef struct PVRSRV_BRIDGE_IN_SYNC_OPS_TAKE_TOKEN_TAG
1683{
1684 IMG_UINT32 ui32BridgeFlags;
1685#if defined (SUPPORT_SID_INTERFACE)
1686 IMG_SID hKernelSyncInfo;
1687#else
1688 IMG_HANDLE hKernelSyncInfo;
1689#endif
1690
1691} PVRSRV_BRIDGE_IN_SYNC_OPS_TAKE_TOKEN;
1692
1693typedef struct PVRSRV_BRIDGE_OUT_SYNC_OPS_TAKE_TOKEN_TAG
1694{
1695 PVRSRV_ERROR eError;
1696
1697 IMG_UINT32 ui32ReadOpsPending;
1698 IMG_UINT32 ui32WriteOpsPending;
1699
1700} PVRSRV_BRIDGE_OUT_SYNC_OPS_TAKE_TOKEN;
1701
1702typedef struct PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_TOKEN_TAG
1703{
1704 IMG_UINT32 ui32BridgeFlags;
1705#if defined (SUPPORT_SID_INTERFACE)
1706 IMG_SID hKernelSyncInfo;
1707#else
1708 IMG_HANDLE hKernelSyncInfo;
1709#endif
1710 IMG_UINT32 ui32ReadOpsPendingSnapshot;
1711 IMG_UINT32 ui32WriteOpsPendingSnapshot;
1712} PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_TOKEN;
1713
1411typedef struct PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_MOD_OBJ_TAG 1714typedef struct PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_MOD_OBJ_TAG
1412{ 1715{
1413 IMG_UINT32 ui32BridgeFlags; 1716 IMG_UINT32 ui32BridgeFlags;
1717#if defined (SUPPORT_SID_INTERFACE)
1718 IMG_SID hKernelSyncInfoModObj;
1719#else
1414 IMG_HANDLE hKernelSyncInfoModObj; 1720 IMG_HANDLE hKernelSyncInfoModObj;
1721#endif
1415} PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_MOD_OBJ; 1722} PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_MOD_OBJ;
1416 1723
1417typedef struct PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_DELTA_TAG 1724typedef struct PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_DELTA_TAG
1418{ 1725{
1419 IMG_UINT32 ui32BridgeFlags; 1726 IMG_UINT32 ui32BridgeFlags;
1727#if defined (SUPPORT_SID_INTERFACE)
1728 IMG_SID hKernelSyncInfo;
1729#else
1420 IMG_HANDLE hKernelSyncInfo; 1730 IMG_HANDLE hKernelSyncInfo;
1731#endif
1421 IMG_UINT32 ui32Delta; 1732 IMG_UINT32 ui32Delta;
1422} PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_DELTA; 1733} PVRSRV_BRIDGE_IN_SYNC_OPS_FLUSH_TO_DELTA;
1423 1734
@@ -1425,23 +1736,41 @@ typedef struct PVRSRV_BRIDGE_IN_ALLOC_SYNC_INFO_TAG
1425{ 1736{
1426 IMG_UINT32 ui32BridgeFlags; 1737 IMG_UINT32 ui32BridgeFlags;
1427 1738
1739#if defined (SUPPORT_SID_INTERFACE)
1740 IMG_SID hDevCookie;
1741#else
1428 IMG_HANDLE hDevCookie; 1742 IMG_HANDLE hDevCookie;
1743#endif
1429} PVRSRV_BRIDGE_IN_ALLOC_SYNC_INFO; 1744} PVRSRV_BRIDGE_IN_ALLOC_SYNC_INFO;
1430 1745
1431typedef struct PVRSRV_BRIDGE_OUT_ALLOC_SYNC_INFO_TAG 1746typedef struct PVRSRV_BRIDGE_OUT_ALLOC_SYNC_INFO_TAG
1432{ 1747{
1433 PVRSRV_ERROR eError; 1748 PVRSRV_ERROR eError;
1434 1749
1750#if defined (SUPPORT_SID_INTERFACE)
1751 IMG_SID hKernelSyncInfo;
1752#else
1435 IMG_HANDLE hKernelSyncInfo; 1753 IMG_HANDLE hKernelSyncInfo;
1754#endif
1436} PVRSRV_BRIDGE_OUT_ALLOC_SYNC_INFO; 1755} PVRSRV_BRIDGE_OUT_ALLOC_SYNC_INFO;
1437 1756
1438typedef struct PVRSRV_BRIDGE_IN_FREE_SYNC_INFO_TAG 1757typedef struct PVRSRV_BRIDGE_IN_FREE_SYNC_INFO_TAG
1439{ 1758{
1440 IMG_UINT32 ui32BridgeFlags; 1759 IMG_UINT32 ui32BridgeFlags;
1441 1760
1761#if defined (SUPPORT_SID_INTERFACE)
1762 IMG_SID hKernelSyncInfo;
1763#else
1442 IMG_HANDLE hKernelSyncInfo; 1764 IMG_HANDLE hKernelSyncInfo;
1765#endif
1443} PVRSRV_BRIDGE_IN_FREE_SYNC_INFO; 1766} PVRSRV_BRIDGE_IN_FREE_SYNC_INFO;
1444 1767
1768typedef struct PVRSRV_BRIDGE_IN_CHG_DEV_MEM_ATTRIBS_TAG
1769{
1770 IMG_SID hKernelMemInfo;
1771 IMG_UINT32 ui32Attribs;
1772} PVRSRV_BRIDGE_IN_CHG_DEV_MEM_ATTRIBS;
1773
1445 1774
1446#if defined (__cplusplus) 1775#if defined (__cplusplus)
1447} 1776}
diff --git a/drivers/gpu/pvr/pvr_bridge_k.c b/drivers/gpu/pvr/pvr_bridge_k.c
index 3abf6048fde..4b639039566 100644
--- a/drivers/gpu/pvr/pvr_bridge_k.c
+++ b/drivers/gpu/pvr/pvr_bridge_k.c
@@ -54,12 +54,6 @@
54 54
55#include "bridged_pvr_bridge.h" 55#include "bridged_pvr_bridge.h"
56 56
57#ifdef MODULE_TEST
58#include "pvr_test_bridge.h"
59#include "kern_test.h"
60#endif
61
62
63#if defined(SUPPORT_DRI_DRM) 57#if defined(SUPPORT_DRI_DRM)
64#define PRIVATE_DATA(pFile) ((pFile)->driver_priv) 58#define PRIVATE_DATA(pFile) ((pFile)->driver_priv)
65#else 59#else
@@ -234,150 +228,6 @@ PVRSRV_BridgeDispatchKM(struct file *pFile, unsigned int unref__ ioctlCmd, unsig
234#endif 228#endif
235 229
236 cmd = psBridgePackageKM->ui32BridgeID; 230 cmd = psBridgePackageKM->ui32BridgeID;
237
238#if defined(MODULE_TEST)
239 switch (cmd)
240 {
241 case PVRSRV_BRIDGE_SERVICES_TEST_MEM1:
242 {
243 PVRSRV_ERROR eError = MemTest1();
244 if (psBridgePackageKM->ui32OutBufferSize == sizeof(PVRSRV_BRIDGE_RETURN))
245 {
246 PVRSRV_BRIDGE_RETURN* pReturn = (PVRSRV_BRIDGE_RETURN*)psBridgePackageKM->pvParamOut ;
247 pReturn->eError = eError;
248 }
249 }
250 err = 0;
251 goto unlock_and_return;
252 case PVRSRV_BRIDGE_SERVICES_TEST_MEM2:
253 {
254 PVRSRV_ERROR eError = MemTest2();
255 if (psBridgePackageKM->ui32OutBufferSize == sizeof(PVRSRV_BRIDGE_RETURN))
256 {
257 PVRSRV_BRIDGE_RETURN* pReturn = (PVRSRV_BRIDGE_RETURN*)psBridgePackageKM->pvParamOut ;
258 pReturn->eError = eError;
259 }
260 }
261 err = 0;
262 goto unlock_and_return;
263
264 case PVRSRV_BRIDGE_SERVICES_TEST_RESOURCE:
265 {
266 PVRSRV_ERROR eError = ResourceTest();
267 if (psBridgePackageKM->ui32OutBufferSize == sizeof(PVRSRV_BRIDGE_RETURN))
268 {
269 PVRSRV_BRIDGE_RETURN* pReturn = (PVRSRV_BRIDGE_RETURN*)psBridgePackageKM->pvParamOut ;
270 pReturn->eError = eError;
271 }
272 }
273 err = 0;
274 goto unlock_and_return;
275
276 case PVRSRV_BRIDGE_SERVICES_TEST_EVENTOBJECT:
277 {
278 PVRSRV_ERROR eError = EventObjectTest();
279 if (psBridgePackageKM->ui32OutBufferSize == sizeof(PVRSRV_BRIDGE_RETURN))
280 {
281 PVRSRV_BRIDGE_RETURN* pReturn = (PVRSRV_BRIDGE_RETURN*)psBridgePackageKM->pvParamOut ;
282 pReturn->eError = eError;
283 }
284 }
285 err = 0;
286 goto unlock_and_return;
287
288 case PVRSRV_BRIDGE_SERVICES_TEST_MEMMAPPING:
289 {
290 PVRSRV_ERROR eError = MemMappingTest();
291 if (psBridgePackageKM->ui32OutBufferSize == sizeof(PVRSRV_BRIDGE_RETURN))
292 {
293 PVRSRV_BRIDGE_RETURN* pReturn = (PVRSRV_BRIDGE_RETURN*)psBridgePackageKM->pvParamOut ;
294 pReturn->eError = eError;
295 }
296 }
297 err = 0;
298 goto unlock_and_return;
299
300 case PVRSRV_BRIDGE_SERVICES_TEST_PROCESSID:
301 {
302 PVRSRV_ERROR eError = ProcessIDTest();
303 if (psBridgePackageKM->ui32OutBufferSize == sizeof(PVRSRV_BRIDGE_RETURN))
304 {
305 PVRSRV_BRIDGE_RETURN* pReturn = (PVRSRV_BRIDGE_RETURN*)psBridgePackageKM->pvParamOut ;
306 pReturn->eError = eError;
307 }
308 }
309 err = 0;
310 goto unlock_and_return;
311
312 case PVRSRV_BRIDGE_SERVICES_TEST_CLOCKUSWAITUS:
313 {
314 PVRSRV_ERROR eError = ClockusWaitusTest();
315 if (psBridgePackageKM->ui32OutBufferSize == sizeof(PVRSRV_BRIDGE_RETURN))
316 {
317 PVRSRV_BRIDGE_RETURN* pReturn = (PVRSRV_BRIDGE_RETURN*)psBridgePackageKM->pvParamOut ;
318 pReturn->eError = eError;
319 }
320 }
321 err = 0;
322 goto unlock_and_return;
323
324 case PVRSRV_BRIDGE_SERVICES_TEST_TIMER:
325 {
326 PVRSRV_ERROR eError = TimerTest();
327 if (psBridgePackageKM->ui32OutBufferSize == sizeof(PVRSRV_BRIDGE_RETURN))
328 {
329 PVRSRV_BRIDGE_RETURN* pReturn = (PVRSRV_BRIDGE_RETURN*)psBridgePackageKM->pvParamOut ;
330 pReturn->eError = eError;
331 }
332 }
333 err = 0;
334 goto unlock_and_return;
335
336 case PVRSRV_BRIDGE_SERVICES_TEST_PRIVSRV:
337 {
338 PVRSRV_ERROR eError = PrivSrvTest();
339 if (psBridgePackageKM->ui32OutBufferSize == sizeof(PVRSRV_BRIDGE_RETURN))
340 {
341 PVRSRV_BRIDGE_RETURN* pReturn = (PVRSRV_BRIDGE_RETURN*)psBridgePackageKM->pvParamOut ;
342 pReturn->eError = eError;
343 }
344 }
345 err = 0;
346 goto unlock_and_return;
347 case PVRSRV_BRIDGE_SERVICES_TEST_COPYDATA:
348 {
349 IMG_UINT32 ui32PID;
350 PVRSRV_PER_PROCESS_DATA *psPerProc;
351 PVRSRV_ERROR eError;
352
353 ui32PID = OSGetCurrentProcessIDKM();
354
355 PVRSRVTrace("PVRSRV_BRIDGE_SERVICES_TEST_COPYDATA %d", ui32PID);
356
357 psPerProc = PVRSRVPerProcessData(ui32PID);
358
359 eError = CopyDataTest(psBridgePackageKM->pvParamIn, psBridgePackageKM->pvParamOut, psPerProc);
360
361 *(PVRSRV_ERROR*)psBridgePackageKM->pvParamOut = eError;
362 err = 0;
363 goto unlock_and_return;
364 }
365
366
367 case PVRSRV_BRIDGE_SERVICES_TEST_POWERMGMT:
368 {
369 PVRSRV_ERROR eError = PowerMgmtTest();
370 if (psBridgePackageKM->ui32OutBufferSize == sizeof(PVRSRV_BRIDGE_RETURN))
371 {
372 PVRSRV_BRIDGE_RETURN* pReturn = (PVRSRV_BRIDGE_RETURN*)psBridgePackageKM->pvParamOut ;
373 pReturn->eError = eError;
374 }
375 }
376 err = 0;
377 goto unlock_and_return;
378
379 }
380#endif
381 231
382 if(cmd != PVRSRV_BRIDGE_CONNECT_SERVICES) 232 if(cmd != PVRSRV_BRIDGE_CONNECT_SERVICES)
383 { 233 {
@@ -416,10 +266,9 @@ PVRSRV_BridgeDispatchKM(struct file *pFile, unsigned int unref__ ioctlCmd, unsig
416 266
417 psBridgePackageKM->ui32BridgeID = PVRSRV_GET_BRIDGE_ID(psBridgePackageKM->ui32BridgeID); 267 psBridgePackageKM->ui32BridgeID = PVRSRV_GET_BRIDGE_ID(psBridgePackageKM->ui32BridgeID);
418 268
419#if defined(PVR_SECURE_FD_EXPORT)
420 switch(cmd) 269 switch(cmd)
421 { 270 {
422 case PVRSRV_BRIDGE_EXPORT_DEVICEMEM: 271 case PVRSRV_BRIDGE_EXPORT_DEVICEMEM_2:
423 { 272 {
424 PVRSRV_FILE_PRIVATE_DATA *psPrivateData = PRIVATE_DATA(pFile); 273 PVRSRV_FILE_PRIVATE_DATA *psPrivateData = PRIVATE_DATA(pFile);
425 274
@@ -433,7 +282,7 @@ PVRSRV_BridgeDispatchKM(struct file *pFile, unsigned int unref__ ioctlCmd, unsig
433 break; 282 break;
434 } 283 }
435 284
436 case PVRSRV_BRIDGE_MAP_DEV_MEMORY: 285 case PVRSRV_BRIDGE_MAP_DEV_MEMORY_2:
437 { 286 {
438 PVRSRV_BRIDGE_IN_MAP_DEV_MEMORY *psMapDevMemIN = 287 PVRSRV_BRIDGE_IN_MAP_DEV_MEMORY *psMapDevMemIN =
439 (PVRSRV_BRIDGE_IN_MAP_DEV_MEMORY *)psBridgePackageKM->pvParamIn; 288 (PVRSRV_BRIDGE_IN_MAP_DEV_MEMORY *)psBridgePackageKM->pvParamIn;
@@ -464,7 +313,7 @@ PVRSRV_BridgeDispatchKM(struct file *pFile, unsigned int unref__ ioctlCmd, unsig
464 break; 313 break;
465 } 314 }
466 } 315 }
467#endif 316
468#if defined(SUPPORT_DRI_DRM) && defined(PVR_SECURE_DRM_AUTH_EXPORT) 317#if defined(SUPPORT_DRI_DRM) && defined(PVR_SECURE_DRM_AUTH_EXPORT)
469 switch(cmd) 318 switch(cmd)
470 { 319 {
@@ -522,8 +371,7 @@ PVRSRV_BridgeDispatchKM(struct file *pFile, unsigned int unref__ ioctlCmd, unsig
522 371
523 switch(cmd) 372 switch(cmd)
524 { 373 {
525#if defined(PVR_SECURE_FD_EXPORT) 374 case PVRSRV_BRIDGE_EXPORT_DEVICEMEM_2:
526 case PVRSRV_BRIDGE_EXPORT_DEVICEMEM:
527 { 375 {
528 PVRSRV_BRIDGE_OUT_EXPORTDEVICEMEM *psExportDeviceMemOUT = 376 PVRSRV_BRIDGE_OUT_EXPORTDEVICEMEM *psExportDeviceMemOUT =
529 (PVRSRV_BRIDGE_OUT_EXPORTDEVICEMEM *)psBridgePackageKM->pvParamOut; 377 (PVRSRV_BRIDGE_OUT_EXPORTDEVICEMEM *)psBridgePackageKM->pvParamOut;
@@ -535,7 +383,6 @@ PVRSRV_BridgeDispatchKM(struct file *pFile, unsigned int unref__ ioctlCmd, unsig
535#endif 383#endif
536 break; 384 break;
537 } 385 }
538#endif
539 386
540#if defined(SUPPORT_MEMINFO_IDS) 387#if defined(SUPPORT_MEMINFO_IDS)
541 case PVRSRV_BRIDGE_MAP_DEV_MEMORY: 388 case PVRSRV_BRIDGE_MAP_DEV_MEMORY:
diff --git a/drivers/gpu/pvr/pvr_bridge_km.h b/drivers/gpu/pvr/pvr_bridge_km.h
index d5592c2ecf5..fe6b22687ce 100644
--- a/drivers/gpu/pvr/pvr_bridge_km.h
+++ b/drivers/gpu/pvr/pvr_bridge_km.h
@@ -57,14 +57,22 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVDestroyCommandQueueKM(PVRSRV_QUEUE_INFO *psQueue
57 57
58IMG_IMPORT 58IMG_IMPORT
59PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDeviceMemHeapsKM(IMG_HANDLE hDevCookie, 59PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDeviceMemHeapsKM(IMG_HANDLE hDevCookie,
60#if defined (SUPPORT_SID_INTERFACE)
61 PVRSRV_HEAP_INFO_KM *psHeapInfo);
62#else
60 PVRSRV_HEAP_INFO *psHeapInfo); 63 PVRSRV_HEAP_INFO *psHeapInfo);
64#endif
61 65
62IMG_IMPORT 66IMG_IMPORT
63PVRSRV_ERROR IMG_CALLCONV PVRSRVCreateDeviceMemContextKM(IMG_HANDLE hDevCookie, 67PVRSRV_ERROR IMG_CALLCONV PVRSRVCreateDeviceMemContextKM(IMG_HANDLE hDevCookie,
64 PVRSRV_PER_PROCESS_DATA *psPerProc, 68 PVRSRV_PER_PROCESS_DATA *psPerProc,
65 IMG_HANDLE *phDevMemContext, 69 IMG_HANDLE *phDevMemContext,
66 IMG_UINT32 *pui32ClientHeapCount, 70 IMG_UINT32 *pui32ClientHeapCount,
71#if defined (SUPPORT_SID_INTERFACE)
72 PVRSRV_HEAP_INFO_KM *psHeapInfo,
73#else
67 PVRSRV_HEAP_INFO *psHeapInfo, 74 PVRSRV_HEAP_INFO *psHeapInfo,
75#endif
68 IMG_BOOL *pbCreated, 76 IMG_BOOL *pbCreated,
69 IMG_BOOL *pbShared); 77 IMG_BOOL *pbShared);
70 78
@@ -79,7 +87,11 @@ IMG_IMPORT
79PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDeviceMemHeapInfoKM(IMG_HANDLE hDevCookie, 87PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDeviceMemHeapInfoKM(IMG_HANDLE hDevCookie,
80 IMG_HANDLE hDevMemContext, 88 IMG_HANDLE hDevMemContext,
81 IMG_UINT32 *pui32ClientHeapCount, 89 IMG_UINT32 *pui32ClientHeapCount,
90#if defined (SUPPORT_SID_INTERFACE)
91 PVRSRV_HEAP_INFO_KM *psHeapInfo,
92#else
82 PVRSRV_HEAP_INFO *psHeapInfo, 93 PVRSRV_HEAP_INFO *psHeapInfo,
94#endif
83 IMG_BOOL *pbShared 95 IMG_BOOL *pbShared
84 ); 96 );
85 97
@@ -247,6 +259,10 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceClassMemoryKM(PVRSRV_PER_PROCESS_DATA *
247 PVRSRV_KERNEL_MEM_INFO **ppsMemInfo, 259 PVRSRV_KERNEL_MEM_INFO **ppsMemInfo,
248 IMG_HANDLE *phOSMapInfo); 260 IMG_HANDLE *phOSMapInfo);
249 261
262IMG_EXPORT
263PVRSRV_ERROR IMG_CALLCONV PVRSRVChangeDeviceMemoryAttributesKM(IMG_HANDLE hKernelMemInfo,
264 IMG_UINT32 ui32Attribs);
265
250IMG_IMPORT 266IMG_IMPORT
251PVRSRV_ERROR IMG_CALLCONV PVRSRVUnmapDeviceClassMemoryKM(PVRSRV_KERNEL_MEM_INFO *psMemInfo); 267PVRSRV_ERROR IMG_CALLCONV PVRSRVUnmapDeviceClassMemoryKM(PVRSRV_KERNEL_MEM_INFO *psMemInfo);
252 268
@@ -263,7 +279,11 @@ IMG_IMPORT
263PVRSRV_ERROR IMG_CALLCONV PVRSRVFreeSyncInfoKM(PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo); 279PVRSRV_ERROR IMG_CALLCONV PVRSRVFreeSyncInfoKM(PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo);
264 280
265IMG_IMPORT 281IMG_IMPORT
282#if defined (SUPPORT_SID_INTERFACE)
283PVRSRV_ERROR IMG_CALLCONV PVRSRVGetMiscInfoKM(PVRSRV_MISC_INFO_KM *psMiscInfo);
284#else
266PVRSRV_ERROR IMG_CALLCONV PVRSRVGetMiscInfoKM(PVRSRV_MISC_INFO *psMiscInfo); 285PVRSRV_ERROR IMG_CALLCONV PVRSRVGetMiscInfoKM(PVRSRV_MISC_INFO *psMiscInfo);
286#endif
267 287
268IMG_IMPORT PVRSRV_ERROR 288IMG_IMPORT PVRSRV_ERROR
269PVRSRVAllocSharedSysMemoryKM(PVRSRV_PER_PROCESS_DATA *psPerProc, 289PVRSRVAllocSharedSysMemoryKM(PVRSRV_PER_PROCESS_DATA *psPerProc,
diff --git a/drivers/gpu/pvr/pvr_debug.h b/drivers/gpu/pvr/pvr_debug.h
index 21fa2cdfbe3..5e7c77c8a39 100644
--- a/drivers/gpu/pvr/pvr_debug.h
+++ b/drivers/gpu/pvr/pvr_debug.h
@@ -30,6 +30,7 @@
30 30
31#include "img_types.h" 31#include "img_types.h"
32 32
33
33#if defined (__cplusplus) 34#if defined (__cplusplus)
34extern "C" { 35extern "C" {
35#endif 36#endif
diff --git a/drivers/gpu/pvr/pvrmmap.h b/drivers/gpu/pvr/pvrmmap.h
index 4404d8852af..af3369aae23 100644
--- a/drivers/gpu/pvr/pvrmmap.h
+++ b/drivers/gpu/pvr/pvrmmap.h
@@ -27,10 +27,18 @@
27#ifndef __PVRMMAP_H__ 27#ifndef __PVRMMAP_H__
28#define __PVRMMAP_H__ 28#define __PVRMMAP_H__
29 29
30#if defined (SUPPORT_SID_INTERFACE)
31PVRSRV_ERROR PVRPMapKMem(IMG_HANDLE hModule, IMG_VOID **ppvLinAddr, IMG_VOID *pvLinAddrKM, IMG_SID *phMappingInfo, IMG_SID hMHandle);
32#else
30PVRSRV_ERROR PVRPMapKMem(IMG_HANDLE hModule, IMG_VOID **ppvLinAddr, IMG_VOID *pvLinAddrKM, IMG_HANDLE *phMappingInfo, IMG_HANDLE hMHandle); 33PVRSRV_ERROR PVRPMapKMem(IMG_HANDLE hModule, IMG_VOID **ppvLinAddr, IMG_VOID *pvLinAddrKM, IMG_HANDLE *phMappingInfo, IMG_HANDLE hMHandle);
34#endif
31 35
32 36
37#if defined (SUPPORT_SID_INTERFACE)
38IMG_BOOL PVRUnMapKMem(IMG_HANDLE hModule, IMG_SID hMappingInfo, IMG_SID hMHandle);
39#else
33IMG_BOOL PVRUnMapKMem(IMG_HANDLE hModule, IMG_HANDLE hMappingInfo, IMG_HANDLE hMHandle); 40IMG_BOOL PVRUnMapKMem(IMG_HANDLE hModule, IMG_HANDLE hMappingInfo, IMG_HANDLE hMHandle);
41#endif
34 42
35#endif 43#endif
36 44
diff --git a/drivers/gpu/pvr/pvrsrv.c b/drivers/gpu/pvr/pvrsrv.c
index 5862fb925f8..cb05a59e8aa 100644
--- a/drivers/gpu/pvr/pvrsrv.c
+++ b/drivers/gpu/pvr/pvrsrv.c
@@ -32,6 +32,9 @@
32#include "pdump_km.h" 32#include "pdump_km.h"
33#include "deviceid.h" 33#include "deviceid.h"
34#include "ra.h" 34#include "ra.h"
35#if defined(TTRACE)
36#include "ttrace.h"
37#endif
35 38
36#include "pvrversion.h" 39#include "pvrversion.h"
37 40
@@ -40,6 +43,7 @@
40IMG_UINT32 g_ui32InitFlags; 43IMG_UINT32 g_ui32InitFlags;
41 44
42#define INIT_DATA_ENABLE_PDUMPINIT 0x1U 45#define INIT_DATA_ENABLE_PDUMPINIT 0x1U
46#define INIT_DATA_ENABLE_TTARCE 0x2U
43 47
44PVRSRV_ERROR AllocateDeviceID(SYS_DATA *psSysData, IMG_UINT32 *pui32DevID) 48PVRSRV_ERROR AllocateDeviceID(SYS_DATA *psSysData, IMG_UINT32 *pui32DevID)
45{ 49{
@@ -238,12 +242,24 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVInit(PSYS_DATA psSysData)
238 goto Error; 242 goto Error;
239 } 243 }
240 244
241 if(OSEventObjectCreate("PVRSRV_GLOBAL_EVENTOBJECT", psSysData->psGlobalEventObject) != PVRSRV_OK) 245 if(OSEventObjectCreateKM("PVRSRV_GLOBAL_EVENTOBJECT", psSysData->psGlobalEventObject) != PVRSRV_OK)
242 { 246 {
243 goto Error; 247 goto Error;
244 } 248 }
245 249
246 250
251 psSysData->pfnHighResTimerCreate = OSFuncHighResTimerCreate;
252 psSysData->pfnHighResTimerGetus = OSFuncHighResTimerGetus;
253 psSysData->pfnHighResTimerDestroy = OSFuncHighResTimerDestroy;
254
255#if defined(TTRACE)
256 eError = PVRSRVTimeTraceInit();
257 if (eError != PVRSRV_OK)
258 goto Error;
259 g_ui32InitFlags |= INIT_DATA_ENABLE_TTARCE;
260#endif
261
262
247 PDUMPINIT(); 263 PDUMPINIT();
248 g_ui32InitFlags |= INIT_DATA_ENABLE_PDUMPINIT; 264 g_ui32InitFlags |= INIT_DATA_ENABLE_PDUMPINIT;
249 265
@@ -267,7 +283,13 @@ IMG_VOID IMG_CALLCONV PVRSRVDeInit(PSYS_DATA psSysData)
267 PVR_DPF((PVR_DBG_ERROR,"PVRSRVDeInit: PVRSRVHandleDeInit failed - invalid param")); 283 PVR_DPF((PVR_DBG_ERROR,"PVRSRVDeInit: PVRSRVHandleDeInit failed - invalid param"));
268 return; 284 return;
269 } 285 }
270 286#if defined(TTRACE)
287
288 if ((g_ui32InitFlags & INIT_DATA_ENABLE_TTARCE) > 0)
289 {
290 PVRSRVTimeTraceDeinit();
291 }
292#endif
271 293
272 if( (g_ui32InitFlags & INIT_DATA_ENABLE_PDUMPINIT) > 0) 294 if( (g_ui32InitFlags & INIT_DATA_ENABLE_PDUMPINIT) > 0)
273 { 295 {
@@ -277,7 +299,7 @@ IMG_VOID IMG_CALLCONV PVRSRVDeInit(PSYS_DATA psSysData)
277 299
278 if(psSysData->psGlobalEventObject) 300 if(psSysData->psGlobalEventObject)
279 { 301 {
280 OSEventObjectDestroy(psSysData->psGlobalEventObject); 302 OSEventObjectDestroyKM(psSysData->psGlobalEventObject);
281 OSFreeMem( PVRSRV_PAGEABLE_SELECT, 303 OSFreeMem( PVRSRV_PAGEABLE_SELECT,
282 sizeof(PVRSRV_EVENTOBJECT), 304 sizeof(PVRSRV_EVENTOBJECT),
283 psSysData->psGlobalEventObject, 305 psSysData->psGlobalEventObject,
@@ -621,14 +643,14 @@ PVRSRV_ERROR IMG_CALLCONV PollForValueKM (volatile IMG_UINT32* pui32LinMemAddr,
621 IMG_BOOL bAllowPreemption) 643 IMG_BOOL bAllowPreemption)
622{ 644{
623 { 645 {
624 IMG_UINT32 ui32ActualValue = 0xFFFFFFFFU; 646 IMG_UINT32 ui32ActualValue = 0xFFFFFFFFU;
625 647
626 if (bAllowPreemption) 648 if (bAllowPreemption)
627 { 649 {
628 PVR_ASSERT(ui32PollPeriodus >= 1000); 650 PVR_ASSERT(ui32PollPeriodus >= 1000);
629 } 651 }
630 652
631 653
632 LOOP_UNTIL_TIMEOUT(ui32Timeoutus) 654 LOOP_UNTIL_TIMEOUT(ui32Timeoutus)
633 { 655 {
634 ui32ActualValue = (*pui32LinMemAddr & ui32Mask); 656 ui32ActualValue = (*pui32LinMemAddr & ui32Mask);
@@ -636,7 +658,7 @@ PVRSRV_ERROR IMG_CALLCONV PollForValueKM (volatile IMG_UINT32* pui32LinMemAddr,
636 { 658 {
637 return PVRSRV_OK; 659 return PVRSRV_OK;
638 } 660 }
639 661
640 if (bAllowPreemption) 662 if (bAllowPreemption)
641 { 663 {
642 OSSleepms(ui32PollPeriodus / 1000); 664 OSSleepms(ui32PollPeriodus / 1000);
@@ -646,7 +668,7 @@ PVRSRV_ERROR IMG_CALLCONV PollForValueKM (volatile IMG_UINT32* pui32LinMemAddr,
646 OSWaitus(ui32PollPeriodus); 668 OSWaitus(ui32PollPeriodus);
647 } 669 }
648 } END_LOOP_UNTIL_TIMEOUT(); 670 } END_LOOP_UNTIL_TIMEOUT();
649 671
650 PVR_DPF((PVR_DBG_ERROR,"PollForValueKM: Timeout. Expected 0x%x but found 0x%x (mask 0x%x).", 672 PVR_DPF((PVR_DBG_ERROR,"PollForValueKM: Timeout. Expected 0x%x but found 0x%x (mask 0x%x).",
651 ui32Value, ui32ActualValue, ui32Mask)); 673 ui32Value, ui32ActualValue, ui32Mask));
652 } 674 }
@@ -666,7 +688,7 @@ static IMG_VOID PVRSRVGetMiscInfoKM_RA_GetStats_ForEachVaCb(BM_HEAP *psBMHeap, v
666 pui32StrLen = va_arg(va, IMG_UINT32*); 688 pui32StrLen = va_arg(va, IMG_UINT32*);
667 ui32Mode = va_arg(va, IMG_UINT32); 689 ui32Mode = va_arg(va, IMG_UINT32);
668 690
669 691
670 switch(ui32Mode) 692 switch(ui32Mode)
671 { 693 {
672 case PVRSRV_MISC_INFO_MEMSTATS_PRESENT: 694 case PVRSRV_MISC_INFO_MEMSTATS_PRESENT:
@@ -762,7 +784,11 @@ static PVRSRV_ERROR PVRSRVGetMiscInfoKM_Device_AnyVaCb(PVRSRV_DEVICE_NODE *psDev
762 784
763 785
764IMG_EXPORT 786IMG_EXPORT
787#if defined (SUPPORT_SID_INTERFACE)
788PVRSRV_ERROR IMG_CALLCONV PVRSRVGetMiscInfoKM(PVRSRV_MISC_INFO_KM *psMiscInfo)
789#else
765PVRSRV_ERROR IMG_CALLCONV PVRSRVGetMiscInfoKM(PVRSRV_MISC_INFO *psMiscInfo) 790PVRSRV_ERROR IMG_CALLCONV PVRSRVGetMiscInfoKM(PVRSRV_MISC_INFO *psMiscInfo)
791#endif
766{ 792{
767 SYS_DATA *psSysData; 793 SYS_DATA *psSysData;
768 794
@@ -857,7 +883,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVGetMiscInfoKM(PVRSRV_MISC_INFO *psMiscInfo)
857 } 883 }
858 884
859 885
860 if((psMiscInfo->ui32StateRequest & PVRSRV_MISC_INFO_FREEMEM_PRESENT) 886 if(((psMiscInfo->ui32StateRequest & PVRSRV_MISC_INFO_FREEMEM_PRESENT) != 0)
861 && psMiscInfo->pszMemoryStr) 887 && psMiscInfo->pszMemoryStr)
862 { 888 {
863 IMG_CHAR *pszStr; 889 IMG_CHAR *pszStr;
@@ -929,6 +955,8 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVGetMiscInfoKM(PVRSRV_MISC_INFO *psMiscInfo)
929 955
930 if((psMiscInfo->ui32StateRequest & PVRSRV_MISC_INFO_CPUCACHEOP_PRESENT) != 0UL) 956 if((psMiscInfo->ui32StateRequest & PVRSRV_MISC_INFO_CPUCACHEOP_PRESENT) != 0UL)
931 { 957 {
958 psMiscInfo->ui32StatePresent |= PVRSRV_MISC_INFO_CPUCACHEOP_PRESENT;
959
932 if(psMiscInfo->sCacheOpCtl.bDeferOp) 960 if(psMiscInfo->sCacheOpCtl.bDeferOp)
933 { 961 {
934 962
@@ -936,10 +964,16 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVGetMiscInfoKM(PVRSRV_MISC_INFO *psMiscInfo)
936 } 964 }
937 else 965 else
938 { 966 {
967#if defined (SUPPORT_SID_INTERFACE)
968 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo = psMiscInfo->sCacheOpCtl.psKernelMemInfo;
969
970 if(!psMiscInfo->sCacheOpCtl.psKernelMemInfo)
971#else
939 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo; 972 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
940 PVRSRV_PER_PROCESS_DATA *psPerProc; 973 PVRSRV_PER_PROCESS_DATA *psPerProc;
941 974
942 if(!psMiscInfo->sCacheOpCtl.u.psKernelMemInfo) 975 if(!psMiscInfo->sCacheOpCtl.u.psKernelMemInfo)
976#endif
943 { 977 {
944 PVR_DPF((PVR_DBG_WARNING, "PVRSRVGetMiscInfoKM: " 978 PVR_DPF((PVR_DBG_WARNING, "PVRSRVGetMiscInfoKM: "
945 "Ignoring non-deferred cache op with no meminfo")); 979 "Ignoring non-deferred cache op with no meminfo"));
@@ -953,6 +987,9 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVGetMiscInfoKM(PVRSRV_MISC_INFO *psMiscInfo)
953 "to combine deferred cache ops with immediate ones")); 987 "to combine deferred cache ops with immediate ones"));
954 } 988 }
955 989
990#if defined (SUPPORT_SID_INTERFACE)
991 PVR_DBG_BREAK
992#else
956 993
957 psPerProc = PVRSRVFindPerProcessData(); 994 psPerProc = PVRSRVFindPerProcessData();
958 995
@@ -965,6 +1002,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVGetMiscInfoKM(PVRSRV_MISC_INFO *psMiscInfo)
965 "Can't find kernel meminfo")); 1002 "Can't find kernel meminfo"));
966 return PVRSRV_ERROR_INVALID_PARAMS; 1003 return PVRSRV_ERROR_INVALID_PARAMS;
967 } 1004 }
1005#endif
968 1006
969 if(psMiscInfo->sCacheOpCtl.eCacheOpType == PVRSRV_MISC_INFO_CPUCACHEOP_FLUSH) 1007 if(psMiscInfo->sCacheOpCtl.eCacheOpType == PVRSRV_MISC_INFO_CPUCACHEOP_FLUSH)
970 { 1008 {
@@ -1109,9 +1147,9 @@ IMG_VOID IMG_CALLCONV PVRSRVMISR(IMG_VOID *pvSysData)
1109 &PVRSRVMISR_ForEachCb); 1147 &PVRSRVMISR_ForEachCb);
1110 1148
1111 1149
1112 if (PVRSRVProcessQueues(ISR_ID, IMG_FALSE) == PVRSRV_ERROR_PROCESSING_BLOCKED) 1150 if (PVRSRVProcessQueues(IMG_FALSE) == PVRSRV_ERROR_PROCESSING_BLOCKED)
1113 { 1151 {
1114 PVRSRVProcessQueues(ISR_ID, IMG_FALSE); 1152 PVRSRVProcessQueues(IMG_FALSE);
1115 } 1153 }
1116 1154
1117 1155
@@ -1120,7 +1158,7 @@ IMG_VOID IMG_CALLCONV PVRSRVMISR(IMG_VOID *pvSysData)
1120 IMG_HANDLE hOSEventKM = psSysData->psGlobalEventObject->hOSEventKM; 1158 IMG_HANDLE hOSEventKM = psSysData->psGlobalEventObject->hOSEventKM;
1121 if(hOSEventKM) 1159 if(hOSEventKM)
1122 { 1160 {
1123 OSEventObjectSignal(hOSEventKM); 1161 OSEventObjectSignalKM(hOSEventKM);
1124 } 1162 }
1125 } 1163 }
1126} 1164}
diff --git a/drivers/gpu/pvr/pvrsrv_errors.h b/drivers/gpu/pvr/pvrsrv_errors.h
index 56c7184fe2c..7c946bc2cfb 100644
--- a/drivers/gpu/pvr/pvrsrv_errors.h
+++ b/drivers/gpu/pvr/pvrsrv_errors.h
@@ -88,6 +88,8 @@ extern "C" {
88 88
89 case PVRSRV_ERROR_REGISTER_BASE_NOT_SET: return "PVRSRV_ERROR_REGISTER_BASE_NOT_SET"; 89 case PVRSRV_ERROR_REGISTER_BASE_NOT_SET: return "PVRSRV_ERROR_REGISTER_BASE_NOT_SET";
90 90
91 case PVRSRV_ERROR_BM_BAD_SHAREMEM_HANDLE: return "PVRSRV_ERROR_BM_BAD_SHAREMEM_HANDLE";
92
91 case PVRSRV_ERROR_FAILED_TO_ALLOC_USER_MEM: return "PVRSRV_ERROR_FAILED_TO_ALLOC_USER_MEM"; 93 case PVRSRV_ERROR_FAILED_TO_ALLOC_USER_MEM: return "PVRSRV_ERROR_FAILED_TO_ALLOC_USER_MEM";
92 case PVRSRV_ERROR_FAILED_TO_ALLOC_VP_MEMORY: return "PVRSRV_ERROR_FAILED_TO_ALLOC_VP_MEMORY"; 94 case PVRSRV_ERROR_FAILED_TO_ALLOC_VP_MEMORY: return "PVRSRV_ERROR_FAILED_TO_ALLOC_VP_MEMORY";
93 case PVRSRV_ERROR_FAILED_TO_MAP_SHARED_PBDESC: return "PVRSRV_ERROR_FAILED_TO_MAP_SHARED_PBDESC"; 95 case PVRSRV_ERROR_FAILED_TO_MAP_SHARED_PBDESC: return "PVRSRV_ERROR_FAILED_TO_MAP_SHARED_PBDESC";
diff --git a/drivers/gpu/pvr/pvrversion.h b/drivers/gpu/pvr/pvrversion.h
index 5a431d5ee15..6b736c5dd4c 100644
--- a/drivers/gpu/pvr/pvrversion.h
+++ b/drivers/gpu/pvr/pvrversion.h
@@ -28,10 +28,10 @@
28#define _PVRVERSION_H_ 28#define _PVRVERSION_H_
29 29
30#define PVRVERSION_MAJ 1 30#define PVRVERSION_MAJ 1
31#define PVRVERSION_MIN 6 31#define PVRVERSION_MIN 7
32#define PVRVERSION_BRANCH 16 32#define PVRVERSION_BRANCH 17
33#define PVRVERSION_BUILD 4061 33#define PVRVERSION_BUILD 3556
34#define PVRVERSION_STRING "1.6.16.4061" 34#define PVRVERSION_STRING "1.7.17.3556"
35#define PVRVERSION_FILE "eurasiacon.pj" 35#define PVRVERSION_FILE "eurasiacon.pj"
36 36
37#endif 37#endif
diff --git a/drivers/gpu/pvr/queue.c b/drivers/gpu/pvr/queue.c
index 83185f31814..9bc6186d6e4 100644
--- a/drivers/gpu/pvr/queue.c
+++ b/drivers/gpu/pvr/queue.c
@@ -27,7 +27,7 @@
27#include "services_headers.h" 27#include "services_headers.h"
28 28
29#include "lists.h" 29#include "lists.h"
30 30#include "ttrace.h"
31 31
32#define DC_NUM_COMMANDS_PER_TYPE 1 32#define DC_NUM_COMMANDS_PER_TYPE 1
33 33
@@ -71,13 +71,29 @@ void ProcSeqShowQueue(struct seq_file *sfile,void* el)
71 (IMG_UINTPTR_T)psCmd, 71 (IMG_UINTPTR_T)psCmd,
72 psCmd->ui32ProcessID, 72 psCmd->ui32ProcessID,
73 psCmd->CommandType, 73 psCmd->CommandType,
74 psCmd->ui32CmdSize, 74 psCmd->uCmdSize,
75 psCmd->ui32DevIndex, 75 psCmd->ui32DevIndex,
76 psCmd->ui32DstSyncCount, 76 psCmd->ui32DstSyncCount,
77 psCmd->ui32SrcSyncCount, 77 psCmd->ui32SrcSyncCount,
78 psCmd->ui32DataSize); 78 psCmd->uDataSize);
79 {
80 IMG_UINT32 i;
81 for (i = 0; i < psCmd->ui32SrcSyncCount; i++)
82 {
83 PVRSRV_SYNC_DATA *psSyncData = psCmd->psSrcSync[i].psKernelSyncInfoKM->psSyncData;
84 seq_printf(sfile, " Sync %u: ROP/ROC: 0x%x/0x%x WOP/WOC: 0x%x/0x%x ROC-VA: 0x%x WOC-VA: 0x%x\n",
85 i,
86 psCmd->psSrcSync[i].ui32ReadOpsPending,
87 psSyncData->ui32ReadOpsComplete,
88 psCmd->psSrcSync[i].ui32WriteOpsPending,
89 psSyncData->ui32WriteOpsComplete,
90 psCmd->psSrcSync[i].psKernelSyncInfoKM->sReadOpsCompleteDevVAddr.uiAddr,
91 psCmd->psSrcSync[i].psKernelSyncInfoKM->sWriteOpsCompleteDevVAddr.uiAddr);
92 }
93 }
94
79 95
80 ui32ReadOffset += psCmd->ui32CmdSize; 96 ui32ReadOffset += psCmd->uCmdSize;
81 ui32ReadOffset &= psQueue->ui32QueueSize - 1; 97 ui32ReadOffset &= psQueue->ui32QueueSize - 1;
82 cmds++; 98 cmds++;
83 } 99 }
@@ -512,7 +528,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVInsertCommandKM(PVRSRV_QUEUE_INFO *psQueue,
512 psCommand->ui32ProcessID = OSGetCurrentProcessIDKM(); 528 psCommand->ui32ProcessID = OSGetCurrentProcessIDKM();
513 529
514 530
515 psCommand->ui32CmdSize = ui32CommandSize; 531 psCommand->uCmdSize = ui32CommandSize;
516 psCommand->ui32DevIndex = ui32DevIndex; 532 psCommand->ui32DevIndex = ui32DevIndex;
517 psCommand->CommandType = CommandType; 533 psCommand->CommandType = CommandType;
518 psCommand->ui32DstSyncCount = ui32DstSyncCount; 534 psCommand->ui32DstSyncCount = ui32DstSyncCount;
@@ -527,11 +543,18 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVInsertCommandKM(PVRSRV_QUEUE_INFO *psQueue,
527 543
528 psCommand->pvData = (PVRSRV_SYNC_OBJECT*)(((IMG_UINTPTR_T)psCommand->psSrcSync) 544 psCommand->pvData = (PVRSRV_SYNC_OBJECT*)(((IMG_UINTPTR_T)psCommand->psSrcSync)
529 + (ui32SrcSyncCount * sizeof(PVRSRV_SYNC_OBJECT))); 545 + (ui32SrcSyncCount * sizeof(PVRSRV_SYNC_OBJECT)));
530 psCommand->ui32DataSize = ui32DataByteSize; 546 psCommand->uDataSize = ui32DataByteSize;
547
548 PVR_TTRACE(PVRSRV_TRACE_GROUP_QUEUE, PVRSRV_TRACE_CLASS_CMD_START, QUEUE_TOKEN_INSERTKM);
549 PVR_TTRACE_UI32(PVRSRV_TRACE_GROUP_QUEUE, PVRSRV_TRACE_CLASS_NONE,
550 QUEUE_TOKEN_COMMAND_TYPE, CommandType);
531 551
532 552
533 for (i=0; i<ui32DstSyncCount; i++) 553 for (i=0; i<ui32DstSyncCount; i++)
534 { 554 {
555 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_QUEUE, QUEUE_TOKEN_DST_SYNC,
556 apsDstSync[i], PVRSRV_SYNCOP_SAMPLE);
557
535 psCommand->psDstSync[i].psKernelSyncInfoKM = apsDstSync[i]; 558 psCommand->psDstSync[i].psKernelSyncInfoKM = apsDstSync[i];
536 psCommand->psDstSync[i].ui32WriteOpsPending = PVRSRVGetWriteOpsPending(apsDstSync[i], IMG_FALSE); 559 psCommand->psDstSync[i].ui32WriteOpsPending = PVRSRVGetWriteOpsPending(apsDstSync[i], IMG_FALSE);
537 psCommand->psDstSync[i].ui32ReadOpsPending = PVRSRVGetReadOpsPending(apsDstSync[i], IMG_FALSE); 560 psCommand->psDstSync[i].ui32ReadOpsPending = PVRSRVGetReadOpsPending(apsDstSync[i], IMG_FALSE);
@@ -546,6 +569,9 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVInsertCommandKM(PVRSRV_QUEUE_INFO *psQueue,
546 569
547 for (i=0; i<ui32SrcSyncCount; i++) 570 for (i=0; i<ui32SrcSyncCount; i++)
548 { 571 {
572 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_QUEUE, QUEUE_TOKEN_DST_SYNC,
573 apsSrcSync[i], PVRSRV_SYNCOP_SAMPLE);
574
549 psCommand->psSrcSync[i].psKernelSyncInfoKM = apsSrcSync[i]; 575 psCommand->psSrcSync[i].psKernelSyncInfoKM = apsSrcSync[i];
550 psCommand->psSrcSync[i].ui32WriteOpsPending = PVRSRVGetWriteOpsPending(apsSrcSync[i], IMG_TRUE); 576 psCommand->psSrcSync[i].ui32WriteOpsPending = PVRSRVGetWriteOpsPending(apsSrcSync[i], IMG_TRUE);
551 psCommand->psSrcSync[i].ui32ReadOpsPending = PVRSRVGetReadOpsPending(apsSrcSync[i], IMG_TRUE); 577 psCommand->psSrcSync[i].ui32ReadOpsPending = PVRSRVGetReadOpsPending(apsSrcSync[i], IMG_TRUE);
@@ -556,6 +582,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVInsertCommandKM(PVRSRV_QUEUE_INFO *psQueue,
556 psCommand->psSrcSync[i].ui32ReadOpsPending, 582 psCommand->psSrcSync[i].ui32ReadOpsPending,
557 psCommand->psSrcSync[i].ui32WriteOpsPending)); 583 psCommand->psSrcSync[i].ui32WriteOpsPending));
558 } 584 }
585 PVR_TTRACE(PVRSRV_TRACE_GROUP_QUEUE, PVRSRV_TRACE_CLASS_CMD_END, QUEUE_TOKEN_INSERTKM);
559 586
560 587
561 *ppsCommand = psCommand; 588 *ppsCommand = psCommand;
@@ -590,7 +617,7 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVSubmitCommandKM(PVRSRV_QUEUE_INFO *psQueue,
590 + (psCommand->ui32SrcSyncCount * sizeof(PVRSRV_SYNC_OBJECT))); 617 + (psCommand->ui32SrcSyncCount * sizeof(PVRSRV_SYNC_OBJECT)));
591 618
592 619
593 UPDATE_QUEUE_WOFF(psQueue, psCommand->ui32CmdSize); 620 UPDATE_QUEUE_WOFF(psQueue, psCommand->uCmdSize);
594 621
595 return PVRSRV_OK; 622 return PVRSRV_OK;
596} 623}
@@ -730,14 +757,17 @@ PVRSRV_ERROR PVRSRVProcessCommand(SYS_DATA *psSysData,
730 757
731 758
732 if (psDeviceCommandData[psCommand->CommandType].pfnCmdProc((IMG_HANDLE)psCmdCompleteData, 759 if (psDeviceCommandData[psCommand->CommandType].pfnCmdProc((IMG_HANDLE)psCmdCompleteData,
733 psCommand->ui32DataSize, 760 (IMG_UINT32)psCommand->uDataSize,
734 psCommand->pvData) == IMG_FALSE) 761 psCommand->pvData) == IMG_FALSE)
735 { 762 {
763
764
736 765
737 psCmdCompleteData->bInUse = IMG_FALSE; 766 psCmdCompleteData->bInUse = IMG_FALSE;
738 eError = PVRSRV_ERROR_CMD_NOT_PROCESSED; 767 eError = PVRSRV_ERROR_CMD_NOT_PROCESSED;
739 } 768 }
740 769
770
741 psDeviceCommandData[psCommand->CommandType].ui32CCBOffset = (ui32CCBOffset + 1) % DC_NUM_COMMANDS_PER_TYPE; 771 psDeviceCommandData[psCommand->CommandType].ui32CCBOffset = (ui32CCBOffset + 1) % DC_NUM_COMMANDS_PER_TYPE;
742 772
743 return eError; 773 return eError;
@@ -754,48 +784,20 @@ static IMG_VOID PVRSRVProcessQueues_ForEachCb(PVRSRV_DEVICE_NODE *psDeviceNode)
754} 784}
755 785
756IMG_EXPORT 786IMG_EXPORT
757PVRSRV_ERROR PVRSRVProcessQueues(IMG_UINT32 ui32CallerID, 787PVRSRV_ERROR PVRSRVProcessQueues(IMG_BOOL bFlush)
758 IMG_BOOL bFlush)
759{ 788{
760 PVRSRV_QUEUE_INFO *psQueue; 789 PVRSRV_QUEUE_INFO *psQueue;
761 SYS_DATA *psSysData; 790 SYS_DATA *psSysData;
762 PVRSRV_COMMAND *psCommand; 791 PVRSRV_COMMAND *psCommand;
763 PVRSRV_ERROR eError;
764
765 SysAcquireData(&psSysData); 792 SysAcquireData(&psSysData);
766 793
767 794
768 psSysData->bReProcessQueues = IMG_FALSE;
769 795
770 796 while (OSLockResource(&psSysData->sQProcessResource, ISR_ID) != PVRSRV_OK)
771 eError = OSLockResource(&psSysData->sQProcessResource,
772 ui32CallerID);
773 if(eError != PVRSRV_OK)
774 { 797 {
775 798 OSWaitus(1);
776 psSysData->bReProcessQueues = IMG_TRUE; 799 };
777 800
778
779 if(ui32CallerID == ISR_ID)
780 {
781 if (bFlush)
782 {
783 PVR_DPF((PVR_DBG_ERROR,"PVRSRVProcessQueues: Couldn't acquire queue processing lock for FLUSH"));
784 }
785 else
786 {
787 PVR_DPF((PVR_DBG_MESSAGE,"PVRSRVProcessQueues: Couldn't acquire queue processing lock"));
788 }
789 }
790 else
791 {
792 PVR_DPF((PVR_DBG_MESSAGE,"PVRSRVProcessQueues: Queue processing lock-acquire failed when called from the Services driver."));
793 PVR_DPF((PVR_DBG_MESSAGE," This is due to MISR queue processing being interrupted by the Services driver."));
794 }
795
796 return PVRSRV_OK;
797 }
798
799 psQueue = psSysData->psQueueList; 801 psQueue = psSysData->psQueueList;
800 802
801 if(!psQueue) 803 if(!psQueue)
@@ -817,8 +819,7 @@ PVRSRV_ERROR PVRSRVProcessQueues(IMG_UINT32 ui32CallerID,
817 if (PVRSRVProcessCommand(psSysData, psCommand, bFlush) == PVRSRV_OK) 819 if (PVRSRVProcessCommand(psSysData, psCommand, bFlush) == PVRSRV_OK)
818 { 820 {
819 821
820 UPDATE_QUEUE_ROFF(psQueue, psCommand->ui32CmdSize) 822 UPDATE_QUEUE_ROFF(psQueue, psCommand->uCmdSize)
821
822 continue; 823 continue;
823 } 824 }
824 825
@@ -836,15 +837,7 @@ PVRSRV_ERROR PVRSRVProcessQueues(IMG_UINT32 ui32CallerID,
836 List_PVRSRV_DEVICE_NODE_ForEach(psSysData->psDeviceNodeList, 837 List_PVRSRV_DEVICE_NODE_ForEach(psSysData->psDeviceNodeList,
837 &PVRSRVProcessQueues_ForEachCb); 838 &PVRSRVProcessQueues_ForEachCb);
838 839
839 840 OSUnlockResource(&psSysData->sQProcessResource, ISR_ID);
840
841 OSUnlockResource(&psSysData->sQProcessResource, ui32CallerID);
842
843
844 if(psSysData->bReProcessQueues)
845 {
846 return PVRSRV_ERROR_PROCESSING_BLOCKED;
847 }
848 841
849 return PVRSRV_OK; 842 return PVRSRV_OK;
850} 843}
@@ -884,11 +877,18 @@ IMG_VOID PVRSRVCommandCompleteKM(IMG_HANDLE hCmdCookie,
884 877
885 SysAcquireData(&psSysData); 878 SysAcquireData(&psSysData);
886 879
880 PVR_TTRACE(PVRSRV_TRACE_GROUP_QUEUE, PVRSRV_TRACE_CLASS_CMD_COMP_START,
881 QUEUE_TOKEN_COMMAND_COMPLETE);
882
887 883
888 for (i=0; i<psCmdCompleteData->ui32DstSyncCount; i++) 884 for (i=0; i<psCmdCompleteData->ui32DstSyncCount; i++)
889 { 885 {
890 psCmdCompleteData->psDstSync[i].psKernelSyncInfoKM->psSyncData->ui32WriteOpsComplete++; 886 psCmdCompleteData->psDstSync[i].psKernelSyncInfoKM->psSyncData->ui32WriteOpsComplete++;
891 887
888 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_QUEUE, QUEUE_TOKEN_UPDATE_DST,
889 psCmdCompleteData->psDstSync[i].psKernelSyncInfoKM,
890 PVRSRV_SYNCOP_COMPLETE);
891
892 PVR_DPF((PVR_DBG_MESSAGE, "PVRSRVCommandCompleteKM: Dst %u RO-VA:0x%x WO-VA:0x%x ROP:0x%x WOP:0x%x", 892 PVR_DPF((PVR_DBG_MESSAGE, "PVRSRVCommandCompleteKM: Dst %u RO-VA:0x%x WO-VA:0x%x ROP:0x%x WOP:0x%x",
893 i, psCmdCompleteData->psDstSync[i].psKernelSyncInfoKM->sReadOpsCompleteDevVAddr.uiAddr, 893 i, psCmdCompleteData->psDstSync[i].psKernelSyncInfoKM->sReadOpsCompleteDevVAddr.uiAddr,
894 psCmdCompleteData->psDstSync[i].psKernelSyncInfoKM->sWriteOpsCompleteDevVAddr.uiAddr, 894 psCmdCompleteData->psDstSync[i].psKernelSyncInfoKM->sWriteOpsCompleteDevVAddr.uiAddr,
@@ -901,6 +901,10 @@ IMG_VOID PVRSRVCommandCompleteKM(IMG_HANDLE hCmdCookie,
901 { 901 {
902 psCmdCompleteData->psSrcSync[i].psKernelSyncInfoKM->psSyncData->ui32ReadOpsComplete++; 902 psCmdCompleteData->psSrcSync[i].psKernelSyncInfoKM->psSyncData->ui32ReadOpsComplete++;
903 903
904 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_QUEUE, QUEUE_TOKEN_UPDATE_SRC,
905 psCmdCompleteData->psSrcSync[i].psKernelSyncInfoKM,
906 PVRSRV_SYNCOP_COMPLETE);
907
904 PVR_DPF((PVR_DBG_MESSAGE, "PVRSRVCommandCompleteKM: Src %u RO-VA:0x%x WO-VA:0x%x ROP:0x%x WOP:0x%x", 908 PVR_DPF((PVR_DBG_MESSAGE, "PVRSRVCommandCompleteKM: Src %u RO-VA:0x%x WO-VA:0x%x ROP:0x%x WOP:0x%x",
905 i, psCmdCompleteData->psSrcSync[i].psKernelSyncInfoKM->sReadOpsCompleteDevVAddr.uiAddr, 909 i, psCmdCompleteData->psSrcSync[i].psKernelSyncInfoKM->sReadOpsCompleteDevVAddr.uiAddr,
906 psCmdCompleteData->psSrcSync[i].psKernelSyncInfoKM->sWriteOpsCompleteDevVAddr.uiAddr, 910 psCmdCompleteData->psSrcSync[i].psKernelSyncInfoKM->sWriteOpsCompleteDevVAddr.uiAddr,
@@ -908,6 +912,9 @@ IMG_VOID PVRSRVCommandCompleteKM(IMG_HANDLE hCmdCookie,
908 psCmdCompleteData->psSrcSync[i].ui32WriteOpsPending)); 912 psCmdCompleteData->psSrcSync[i].ui32WriteOpsPending));
909 } 913 }
910 914
915 PVR_TTRACE(PVRSRV_TRACE_GROUP_QUEUE, PVRSRV_TRACE_CLASS_CMD_COMP_END,
916 QUEUE_TOKEN_COMMAND_COMPLETE);
917
911 918
912 psCmdCompleteData->bInUse = IMG_FALSE; 919 psCmdCompleteData->bInUse = IMG_FALSE;
913 920
@@ -966,15 +973,15 @@ PVRSRV_ERROR PVRSRVRegisterCmdProcListKM(IMG_UINT32 ui32DevIndex,
966 { 973 {
967 psDeviceCommandData[ui32CmdTypeCounter].pfnCmdProc = ppfnCmdProcList[ui32CmdTypeCounter]; 974 psDeviceCommandData[ui32CmdTypeCounter].pfnCmdProc = ppfnCmdProcList[ui32CmdTypeCounter];
968 psDeviceCommandData[ui32CmdTypeCounter].ui32CCBOffset = 0; 975 psDeviceCommandData[ui32CmdTypeCounter].ui32CCBOffset = 0;
969 976
970 for (ui32CmdCounter = 0; ui32CmdCounter < DC_NUM_COMMANDS_PER_TYPE; ui32CmdCounter++) 977 for (ui32CmdCounter = 0; ui32CmdCounter < DC_NUM_COMMANDS_PER_TYPE; ui32CmdCounter++)
971 { 978 {
979
972 980
973 981 ui32AllocSize = sizeof(COMMAND_COMPLETE_DATA)
974 ui32AllocSize = sizeof(COMMAND_COMPLETE_DATA)
975 + ((ui32MaxSyncsPerCmd[ui32CmdTypeCounter][0] 982 + ((ui32MaxSyncsPerCmd[ui32CmdTypeCounter][0]
976 + ui32MaxSyncsPerCmd[ui32CmdTypeCounter][1]) 983 + ui32MaxSyncsPerCmd[ui32CmdTypeCounter][1])
977 * sizeof(PVRSRV_SYNC_OBJECT)); 984 * sizeof(PVRSRV_SYNC_OBJECT));
978 985
979 eError = OSAllocMem(PVRSRV_OS_NON_PAGEABLE_HEAP, 986 eError = OSAllocMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
980 ui32AllocSize, 987 ui32AllocSize,
@@ -986,13 +993,13 @@ PVRSRV_ERROR PVRSRVRegisterCmdProcListKM(IMG_UINT32 ui32DevIndex,
986 PVR_DPF((PVR_DBG_ERROR,"PVRSRVRegisterCmdProcListKM: Failed to alloc cmd %d", ui32CmdTypeCounter)); 993 PVR_DPF((PVR_DBG_ERROR,"PVRSRVRegisterCmdProcListKM: Failed to alloc cmd %d", ui32CmdTypeCounter));
987 goto ErrorExit; 994 goto ErrorExit;
988 } 995 }
989 996
990 psDeviceCommandData[ui32CmdTypeCounter].apsCmdCompleteData[ui32CmdCounter] = psCmdCompleteData; 997 psDeviceCommandData[ui32CmdTypeCounter].apsCmdCompleteData[ui32CmdCounter] = psCmdCompleteData;
991 998
992 999
993 OSMemSet(psCmdCompleteData, 0x00, ui32AllocSize); 1000 OSMemSet(psCmdCompleteData, 0x00, ui32AllocSize);
994 1001
995 1002
996 psCmdCompleteData->psDstSync = (PVRSRV_SYNC_OBJECT*) 1003 psCmdCompleteData->psDstSync = (PVRSRV_SYNC_OBJECT*)
997 (((IMG_UINTPTR_T)psCmdCompleteData) 1004 (((IMG_UINTPTR_T)psCmdCompleteData)
998 + sizeof(COMMAND_COMPLETE_DATA)); 1005 + sizeof(COMMAND_COMPLETE_DATA));
@@ -1000,7 +1007,7 @@ PVRSRV_ERROR PVRSRVRegisterCmdProcListKM(IMG_UINT32 ui32DevIndex,
1000 (((IMG_UINTPTR_T)psCmdCompleteData->psDstSync) 1007 (((IMG_UINTPTR_T)psCmdCompleteData->psDstSync)
1001 + (sizeof(PVRSRV_SYNC_OBJECT) * ui32MaxSyncsPerCmd[ui32CmdTypeCounter][0])); 1008 + (sizeof(PVRSRV_SYNC_OBJECT) * ui32MaxSyncsPerCmd[ui32CmdTypeCounter][0]));
1002 1009
1003 psCmdCompleteData->ui32AllocSize = ui32AllocSize; 1010 psCmdCompleteData->ui32AllocSize = (IMG_UINT32)ui32AllocSize;
1004 } 1011 }
1005 } 1012 }
1006 1013
@@ -1008,15 +1015,14 @@ PVRSRV_ERROR PVRSRVRegisterCmdProcListKM(IMG_UINT32 ui32DevIndex,
1008 1015
1009ErrorExit: 1016ErrorExit:
1010 1017
1011 1018
1012
1013 if (PVRSRVRemoveCmdProcListKM(ui32DevIndex, ui32CmdCount) != PVRSRV_OK) 1019 if (PVRSRVRemoveCmdProcListKM(ui32DevIndex, ui32CmdCount) != PVRSRV_OK)
1014 { 1020 {
1015 PVR_DPF((PVR_DBG_ERROR, 1021 PVR_DPF((PVR_DBG_ERROR,
1016 "PVRSRVRegisterCmdProcListKM: Failed to clean up after error, device 0x%x", 1022 "PVRSRVRegisterCmdProcListKM: Failed to clean up after error, device 0x%x",
1017 ui32DevIndex)); 1023 ui32DevIndex));
1018 } 1024 }
1019 1025
1020 return eError; 1026 return eError;
1021} 1027}
1022 1028
@@ -1031,7 +1037,7 @@ PVRSRV_ERROR PVRSRVRemoveCmdProcListKM(IMG_UINT32 ui32DevIndex,
1031 COMMAND_COMPLETE_DATA *psCmdCompleteData; 1037 COMMAND_COMPLETE_DATA *psCmdCompleteData;
1032 IMG_SIZE_T ui32AllocSize; 1038 IMG_SIZE_T ui32AllocSize;
1033 1039
1034 1040
1035 if(ui32DevIndex >= SYS_DEVICE_COUNT) 1041 if(ui32DevIndex >= SYS_DEVICE_COUNT)
1036 { 1042 {
1037 PVR_DPF((PVR_DBG_ERROR, 1043 PVR_DPF((PVR_DBG_ERROR,
@@ -1040,7 +1046,7 @@ PVRSRV_ERROR PVRSRVRemoveCmdProcListKM(IMG_UINT32 ui32DevIndex,
1040 return PVRSRV_ERROR_INVALID_PARAMS; 1046 return PVRSRV_ERROR_INVALID_PARAMS;
1041 } 1047 }
1042 1048
1043 1049
1044 SysAcquireData(&psSysData); 1050 SysAcquireData(&psSysData);
1045 1051
1046 psDeviceCommandData = psSysData->apsDeviceCommandData[ui32DevIndex]; 1052 psDeviceCommandData = psSysData->apsDeviceCommandData[ui32DevIndex];
@@ -1051,8 +1057,8 @@ PVRSRV_ERROR PVRSRVRemoveCmdProcListKM(IMG_UINT32 ui32DevIndex,
1051 for (ui32CmdCounter = 0; ui32CmdCounter < DC_NUM_COMMANDS_PER_TYPE; ui32CmdCounter++) 1057 for (ui32CmdCounter = 0; ui32CmdCounter < DC_NUM_COMMANDS_PER_TYPE; ui32CmdCounter++)
1052 { 1058 {
1053 psCmdCompleteData = psDeviceCommandData[ui32CmdTypeCounter].apsCmdCompleteData[ui32CmdCounter]; 1059 psCmdCompleteData = psDeviceCommandData[ui32CmdTypeCounter].apsCmdCompleteData[ui32CmdCounter];
1054 1060
1055 1061
1056 if (psCmdCompleteData != IMG_NULL) 1062 if (psCmdCompleteData != IMG_NULL)
1057 { 1063 {
1058 OSFreeMem(PVRSRV_OS_NON_PAGEABLE_HEAP, psCmdCompleteData->ui32AllocSize, 1064 OSFreeMem(PVRSRV_OS_NON_PAGEABLE_HEAP, psCmdCompleteData->ui32AllocSize,
@@ -1062,7 +1068,7 @@ PVRSRV_ERROR PVRSRVRemoveCmdProcListKM(IMG_UINT32 ui32DevIndex,
1062 } 1068 }
1063 } 1069 }
1064 1070
1065 1071
1066 ui32AllocSize = ui32CmdCount * sizeof(*psDeviceCommandData); 1072 ui32AllocSize = ui32CmdCount * sizeof(*psDeviceCommandData);
1067 OSFreeMem(PVRSRV_OS_NON_PAGEABLE_HEAP, ui32AllocSize, psDeviceCommandData, IMG_NULL); 1073 OSFreeMem(PVRSRV_OS_NON_PAGEABLE_HEAP, ui32AllocSize, psDeviceCommandData, IMG_NULL);
1068 psSysData->apsDeviceCommandData[ui32DevIndex] = IMG_NULL; 1074 psSysData->apsDeviceCommandData[ui32DevIndex] = IMG_NULL;
diff --git a/drivers/gpu/pvr/queue.h b/drivers/gpu/pvr/queue.h
index 9437f0987c8..edafaff02fd 100644
--- a/drivers/gpu/pvr/queue.h
+++ b/drivers/gpu/pvr/queue.h
@@ -51,8 +51,7 @@ extern "C" {
51IMG_VOID QueueDumpDebugInfo(IMG_VOID); 51IMG_VOID QueueDumpDebugInfo(IMG_VOID);
52 52
53IMG_IMPORT 53IMG_IMPORT
54PVRSRV_ERROR PVRSRVProcessQueues (IMG_UINT32 ui32CallerID, 54PVRSRV_ERROR PVRSRVProcessQueues (IMG_BOOL bFlush);
55 IMG_BOOL bFlush);
56 55
57#if defined(__linux__) && defined(__KERNEL__) 56#if defined(__linux__) && defined(__KERNEL__)
58#include <linux/types.h> 57#include <linux/types.h>
diff --git a/drivers/gpu/pvr/ra.c b/drivers/gpu/pvr/ra.c
index 191be844004..2bd5efbdb00 100644
--- a/drivers/gpu/pvr/ra.c
+++ b/drivers/gpu/pvr/ra.c
@@ -142,7 +142,7 @@ struct _RA_ARENA_
142#endif 142#endif
143 143
144#if defined(CONFIG_PROC_FS) && defined(DEBUG) 144#if defined(CONFIG_PROC_FS) && defined(DEBUG)
145#define PROC_NAME_SIZE 32 145#define PROC_NAME_SIZE 64
146 146
147 struct proc_dir_entry* pProcInfo; 147 struct proc_dir_entry* pProcInfo;
148 struct proc_dir_entry* pProcSegs; 148 struct proc_dir_entry* pProcSegs;
diff --git a/drivers/gpu/pvr/resman.c b/drivers/gpu/pvr/resman.c
index 5d865a7d2c1..2daebf67317 100644
--- a/drivers/gpu/pvr/resman.c
+++ b/drivers/gpu/pvr/resman.c
@@ -249,6 +249,9 @@ IMG_VOID PVRSRVResManDisconnect(PRESMAN_CONTEXT psResManContext,
249 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_OS_USERMODE_MAPPING, 0, 0, IMG_TRUE); 249 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_OS_USERMODE_MAPPING, 0, 0, IMG_TRUE);
250 250
251 251
252 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_DMA_CLIENT_FIFO_DATA, 0, 0, IMG_TRUE);
253
254
252 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_EVENT_OBJECT, 0, 0, IMG_TRUE); 255 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_EVENT_OBJECT, 0, 0, IMG_TRUE);
253 256
254 257
@@ -264,15 +267,8 @@ IMG_VOID PVRSRVResManDisconnect(PRESMAN_CONTEXT psResManContext,
264 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_TRANSFER_CONTEXT, 0, 0, IMG_TRUE); 267 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_TRANSFER_CONTEXT, 0, 0, IMG_TRUE);
265 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_SHARED_PB_DESC_CREATE_LOCK, 0, 0, IMG_TRUE); 268 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_SHARED_PB_DESC_CREATE_LOCK, 0, 0, IMG_TRUE);
266 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_SHARED_PB_DESC, 0, 0, IMG_TRUE); 269 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_SHARED_PB_DESC, 0, 0, IMG_TRUE);
267
268
269
270 270
271 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_DISPLAYCLASS_SWAPCHAIN_REF, 0, 0, IMG_TRUE);
272 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_DISPLAYCLASS_DEVICE, 0, 0, IMG_TRUE);
273
274 271
275 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_BUFFERCLASS_DEVICE, 0, 0, IMG_TRUE);
276 272
277 273
278 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_SYNC_INFO, 0, 0, IMG_TRUE); 274 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_SYNC_INFO, 0, 0, IMG_TRUE);
@@ -283,6 +279,13 @@ IMG_VOID PVRSRVResManDisconnect(PRESMAN_CONTEXT psResManContext,
283 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_DEVICEMEM_ALLOCATION, 0, 0, IMG_TRUE); 279 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_DEVICEMEM_ALLOCATION, 0, 0, IMG_TRUE);
284 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_DEVICEMEM_CONTEXT, 0, 0, IMG_TRUE); 280 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_DEVICEMEM_CONTEXT, 0, 0, IMG_TRUE);
285 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_SHARED_MEM_INFO, 0, 0, IMG_TRUE); 281 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_SHARED_MEM_INFO, 0, 0, IMG_TRUE);
282
283
284 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_DISPLAYCLASS_SWAPCHAIN_REF, 0, 0, IMG_TRUE);
285 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_DISPLAYCLASS_DEVICE, 0, 0, IMG_TRUE);
286
287
288 FreeResourceByCriteria(psResManContext, RESMAN_CRITERIA_RESTYPE, RESMAN_TYPE_BUFFERCLASS_DEVICE, 0, 0, IMG_TRUE);
286 } 289 }
287 290
288 291
diff --git a/drivers/gpu/pvr/resman.h b/drivers/gpu/pvr/resman.h
index eebec57c9d6..06eb24a97b6 100644
--- a/drivers/gpu/pvr/resman.h
+++ b/drivers/gpu/pvr/resman.h
@@ -41,6 +41,9 @@ enum {
41 RESMAN_TYPE_TRANSFER_CONTEXT, 41 RESMAN_TYPE_TRANSFER_CONTEXT,
42 42
43 43
44 RESMAN_TYPE_DMA_CLIENT_FIFO_DATA,
45
46
44 47
45 48
46 49
diff --git a/drivers/gpu/pvr/services.h b/drivers/gpu/pvr/services.h
index d1afe284912..595b52ffe7a 100644
--- a/drivers/gpu/pvr/services.h
+++ b/drivers/gpu/pvr/services.h
@@ -80,6 +80,7 @@ extern "C" {
80#define PVRSRV_MEM_BACKINGSTORE_FIELD_SHIFT (24) 80#define PVRSRV_MEM_BACKINGSTORE_FIELD_SHIFT (24)
81 81
82#define PVRSRV_MAP_NOUSERVIRTUAL (1UL<<27) 82#define PVRSRV_MAP_NOUSERVIRTUAL (1UL<<27)
83#define PVRSRV_MEM_XPROC (1U<<28)
83 84
84#define PVRSRV_NO_CONTEXT_LOSS 0 85#define PVRSRV_NO_CONTEXT_LOSS 0
85#define PVRSRV_SEVERE_LOSS_OF_CONTEXT 1 86#define PVRSRV_SEVERE_LOSS_OF_CONTEXT 1
@@ -162,8 +163,11 @@ typedef enum
162 IMG_VISTAVPBNODE = 0x0000000B, 163 IMG_VISTAVPBNODE = 0x0000000B,
163 IMG_OPENGL = 0x0000000C, 164 IMG_OPENGL = 0x0000000C,
164 IMG_D3D = 0x0000000D, 165 IMG_D3D = 0x0000000D,
165#if defined(SUPPORT_GRAPHICS_HAL) 166#if defined(SUPPORT_GRAPHICS_HAL) || defined(SUPPORT_COMPOSER_HAL)
166 IMG_GRAPHICS_HAL = 0x0000000E 167 IMG_ANDROID_HAL = 0x0000000E,
168#endif
169#if defined(SUPPORT_OPENCL)
170 IMG_OPENCL = 0x0000000F,
167#endif 171#endif
168 172
169} IMG_MODULE_ID; 173} IMG_MODULE_ID;
@@ -207,7 +211,7 @@ typedef struct _PVRSRV_CLIENT_DEV_DATA_
207typedef struct _PVRSRV_CONNECTION_ 211typedef struct _PVRSRV_CONNECTION_
208{ 212{
209 IMG_HANDLE hServices; 213 IMG_HANDLE hServices;
210 IMG_UINTPTR_T ui32ProcessID; 214 IMG_UINT32 ui32ProcessID;
211 PVRSRV_CLIENT_DEV_DATA sClientDevData; 215 PVRSRV_CLIENT_DEV_DATA sClientDevData;
212 IMG_UINT32 ui32SrvFlags; 216 IMG_UINT32 ui32SrvFlags;
213}PVRSRV_CONNECTION; 217}PVRSRV_CONNECTION;
@@ -216,13 +220,17 @@ typedef struct _PVRSRV_CONNECTION_
216typedef struct _PVRSRV_DEV_DATA_ 220typedef struct _PVRSRV_DEV_DATA_
217{ 221{
218 IMG_CONST PVRSRV_CONNECTION *psConnection; 222 IMG_CONST PVRSRV_CONNECTION *psConnection;
223#if defined (SUPPORT_SID_INTERFACE)
224 IMG_SID hDevCookie;
225#else
219 IMG_HANDLE hDevCookie; 226 IMG_HANDLE hDevCookie;
227#endif
220 228
221} PVRSRV_DEV_DATA; 229} PVRSRV_DEV_DATA;
222 230
223typedef struct _PVRSRV_MEMUPDATE_ 231typedef struct _PVRSRV_MEMUPDATE_
224{ 232{
225 IMG_UINTPTR_T ui32UpdateAddr; 233 IMG_UINT32 ui32UpdateAddr;
226 IMG_UINT32 ui32UpdateVal; 234 IMG_UINT32 ui32UpdateVal;
227} PVRSRV_MEMUPDATE; 235} PVRSRV_MEMUPDATE;
228 236
@@ -272,12 +280,22 @@ typedef struct _PVRSRV_CLIENT_MEM_INFO_
272 IMG_UINT32 ui32ClientFlags; 280 IMG_UINT32 ui32ClientFlags;
273 281
274 282
275 IMG_SIZE_T ui32AllocSize; 283 IMG_SIZE_T uAllocSize;
276 284
277 285
278 286
279 struct _PVRSRV_CLIENT_SYNC_INFO_ *psClientSyncInfo; 287 struct _PVRSRV_CLIENT_SYNC_INFO_ *psClientSyncInfo;
280 288
289#if defined (SUPPORT_SID_INTERFACE)
290
291 IMG_SID hMappingInfo;
292
293
294 IMG_SID hKernelMemInfo;
295
296
297 IMG_SID hResItem;
298#else
281 299
282 IMG_HANDLE hMappingInfo; 300 IMG_HANDLE hMappingInfo;
283 301
@@ -286,6 +304,7 @@ typedef struct _PVRSRV_CLIENT_MEM_INFO_
286 304
287 305
288 IMG_HANDLE hResItem; 306 IMG_HANDLE hResItem;
307#endif
289 308
290#if defined(SUPPORT_MEMINFO_IDS) 309#if defined(SUPPORT_MEMINFO_IDS)
291 #if !defined(USE_CODE) 310 #if !defined(USE_CODE)
@@ -309,7 +328,11 @@ typedef struct _PVRSRV_CLIENT_MEM_INFO_
309typedef struct _PVRSRV_HEAP_INFO_ 328typedef struct _PVRSRV_HEAP_INFO_
310{ 329{
311 IMG_UINT32 ui32HeapID; 330 IMG_UINT32 ui32HeapID;
331#if defined (SUPPORT_SID_INTERFACE)
332 IMG_SID hDevMemHeap;
333#else
312 IMG_HANDLE hDevMemHeap; 334 IMG_HANDLE hDevMemHeap;
335#endif
313 IMG_DEV_VIRTADDR sDevVAddrBase; 336 IMG_DEV_VIRTADDR sDevVAddrBase;
314 IMG_UINT32 ui32HeapByteSize; 337 IMG_UINT32 ui32HeapByteSize;
315 IMG_UINT32 ui32Attribs; 338 IMG_UINT32 ui32Attribs;
@@ -324,7 +347,11 @@ typedef struct _PVRSRV_EVENTOBJECT_
324 347
325 IMG_CHAR szName[EVENTOBJNAME_MAXLENGTH]; 348 IMG_CHAR szName[EVENTOBJNAME_MAXLENGTH];
326 349
350#if defined (SUPPORT_SID_INTERFACE)
351 IMG_SID hOSEventKM;
352#else
327 IMG_HANDLE hOSEventKM; 353 IMG_HANDLE hOSEventKM;
354#endif
328 355
329} PVRSRV_EVENTOBJECT; 356} PVRSRV_EVENTOBJECT;
330 357
@@ -343,8 +370,13 @@ typedef struct _PVRSRV_MISC_INFO_
343 370
344 IMG_VOID *pvSOCTimerRegisterKM; 371 IMG_VOID *pvSOCTimerRegisterKM;
345 IMG_VOID *pvSOCTimerRegisterUM; 372 IMG_VOID *pvSOCTimerRegisterUM;
373#if defined (SUPPORT_SID_INTERFACE)
374 IMG_SID hSOCTimerRegisterOSMemHandle;
375 IMG_SID hSOCTimerRegisterMappingInfo;
376#else
346 IMG_HANDLE hSOCTimerRegisterOSMemHandle; 377 IMG_HANDLE hSOCTimerRegisterOSMemHandle;
347 IMG_HANDLE hSOCTimerRegisterMappingInfo; 378 IMG_HANDLE hSOCTimerRegisterMappingInfo;
379#endif
348 380
349 381
350 IMG_VOID *pvSOCClockGateRegs; 382 IMG_VOID *pvSOCClockGateRegs;
@@ -356,7 +388,11 @@ typedef struct _PVRSRV_MISC_INFO_
356 388
357 389
358 PVRSRV_EVENTOBJECT sGlobalEventObject; 390 PVRSRV_EVENTOBJECT sGlobalEventObject;
391#if defined (SUPPORT_SID_INTERFACE)
392 IMG_EVENTSID hOSGlobalEvent;
393#else
359 IMG_HANDLE hOSGlobalEvent; 394 IMG_HANDLE hOSGlobalEvent;
395#endif
360 396
361 397
362 IMG_UINT32 aui32DDKVersion[4]; 398 IMG_UINT32 aui32DDKVersion[4];
@@ -371,6 +407,7 @@ typedef struct _PVRSRV_MISC_INFO_
371 PVRSRV_MISC_INFO_CPUCACHEOP_TYPE eCacheOpType; 407 PVRSRV_MISC_INFO_CPUCACHEOP_TYPE eCacheOpType;
372 408
373 409
410#if !defined (SUPPORT_SID_INTERFACE)
374 union 411 union
375 { 412 {
376 413
@@ -379,6 +416,7 @@ typedef struct _PVRSRV_MISC_INFO_
379 416
380 struct _PVRSRV_KERNEL_MEM_INFO_ *psKernelMemInfo; 417 struct _PVRSRV_KERNEL_MEM_INFO_ *psKernelMemInfo;
381 } u; 418 } u;
419#endif
382 420
383 421
384 IMG_VOID *pvBaseVAddr; 422 IMG_VOID *pvBaseVAddr;
@@ -388,6 +426,22 @@ typedef struct _PVRSRV_MISC_INFO_
388 } sCacheOpCtl; 426 } sCacheOpCtl;
389} PVRSRV_MISC_INFO; 427} PVRSRV_MISC_INFO;
390 428
429typedef struct _PVRSRV_SYNC_TOKEN_
430{
431
432
433 struct
434 {
435#if defined (SUPPORT_SID_INTERFACE)
436 IMG_SID hKernelSyncInfo;
437#else
438 IMG_HANDLE hKernelSyncInfo;
439#endif
440 IMG_UINT32 ui32ReadOpsPendingSnapshot;
441 IMG_UINT32 ui32WriteOpsPendingSnapshot;
442 } sPrivate;
443} PVRSRV_SYNC_TOKEN;
444
391 445
392typedef enum _PVRSRV_CLIENT_EVENT_ 446typedef enum _PVRSRV_CLIENT_EVENT_
393{ 447{
@@ -432,7 +486,11 @@ IMG_IMPORT IMG_VOID WriteHWRegs(IMG_PVOID pvLinRegBaseAddr, IMG_UINT32 ui32Count
432 486
433IMG_IMPORT 487IMG_IMPORT
434PVRSRV_ERROR PVRSRVPollForValue ( const PVRSRV_CONNECTION *psConnection, 488PVRSRV_ERROR PVRSRVPollForValue ( const PVRSRV_CONNECTION *psConnection,
489#if defined (SUPPORT_SID_INTERFACE)
490 IMG_SID hOSEvent,
491#else
435 IMG_HANDLE hOSEvent, 492 IMG_HANDLE hOSEvent,
493#endif
436 volatile IMG_UINT32 *pui32LinMemAddr, 494 volatile IMG_UINT32 *pui32LinMemAddr,
437 IMG_UINT32 ui32Value, 495 IMG_UINT32 ui32Value,
438 IMG_UINT32 ui32Mask, 496 IMG_UINT32 ui32Mask,
@@ -441,17 +499,29 @@ PVRSRV_ERROR PVRSRVPollForValue ( const PVRSRV_CONNECTION *psConnection,
441 499
442IMG_IMPORT 500IMG_IMPORT
443PVRSRV_ERROR IMG_CALLCONV PVRSRVCreateDeviceMemContext(IMG_CONST PVRSRV_DEV_DATA *psDevData, 501PVRSRV_ERROR IMG_CALLCONV PVRSRVCreateDeviceMemContext(IMG_CONST PVRSRV_DEV_DATA *psDevData,
502#if defined (SUPPORT_SID_INTERFACE)
503 IMG_SID *phDevMemContext,
504#else
444 IMG_HANDLE *phDevMemContext, 505 IMG_HANDLE *phDevMemContext,
506#endif
445 IMG_UINT32 *pui32SharedHeapCount, 507 IMG_UINT32 *pui32SharedHeapCount,
446 PVRSRV_HEAP_INFO *psHeapInfo); 508 PVRSRV_HEAP_INFO *psHeapInfo);
447 509
448IMG_IMPORT 510IMG_IMPORT
449PVRSRV_ERROR IMG_CALLCONV PVRSRVDestroyDeviceMemContext(IMG_CONST PVRSRV_DEV_DATA *psDevData, 511PVRSRV_ERROR IMG_CALLCONV PVRSRVDestroyDeviceMemContext(IMG_CONST PVRSRV_DEV_DATA *psDevData,
512#if defined (SUPPORT_SID_INTERFACE)
513 IMG_SID hDevMemContext);
514#else
450 IMG_HANDLE hDevMemContext); 515 IMG_HANDLE hDevMemContext);
516#endif
451 517
452IMG_IMPORT 518IMG_IMPORT
453PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDeviceMemHeapInfo(IMG_CONST PVRSRV_DEV_DATA *psDevData, 519PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDeviceMemHeapInfo(IMG_CONST PVRSRV_DEV_DATA *psDevData,
520#if defined (SUPPORT_SID_INTERFACE)
521 IMG_SID hDevMemContext,
522#else
454 IMG_HANDLE hDevMemContext, 523 IMG_HANDLE hDevMemContext,
524#endif
455 IMG_UINT32 *pui32SharedHeapCount, 525 IMG_UINT32 *pui32SharedHeapCount,
456 PVRSRV_HEAP_INFO *psHeapInfo); 526 PVRSRV_HEAP_INFO *psHeapInfo);
457 527
@@ -468,7 +538,11 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDeviceMemHeapInfo(IMG_CONST PVRSRV_DEV_DATA *
468 538
469IMG_IMPORT 539IMG_IMPORT
470PVRSRV_ERROR IMG_CALLCONV PVRSRVAllocDeviceMem(IMG_CONST PVRSRV_DEV_DATA *psDevData, 540PVRSRV_ERROR IMG_CALLCONV PVRSRVAllocDeviceMem(IMG_CONST PVRSRV_DEV_DATA *psDevData,
541#if defined (SUPPORT_SID_INTERFACE)
542 IMG_SID hDevMemHeap,
543#else
471 IMG_HANDLE hDevMemHeap, 544 IMG_HANDLE hDevMemHeap,
545#endif
472 IMG_UINT32 ui32Attribs, 546 IMG_UINT32 ui32Attribs,
473 IMG_SIZE_T ui32Size, 547 IMG_SIZE_T ui32Size,
474 IMG_SIZE_T ui32Alignment, 548 IMG_SIZE_T ui32Alignment,
@@ -481,11 +555,19 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVFreeDeviceMem(IMG_CONST PVRSRV_DEV_DATA *psDevDa
481IMG_IMPORT 555IMG_IMPORT
482PVRSRV_ERROR IMG_CALLCONV PVRSRVExportDeviceMem(IMG_CONST PVRSRV_DEV_DATA *psDevData, 556PVRSRV_ERROR IMG_CALLCONV PVRSRVExportDeviceMem(IMG_CONST PVRSRV_DEV_DATA *psDevData,
483 PVRSRV_CLIENT_MEM_INFO *psMemInfo, 557 PVRSRV_CLIENT_MEM_INFO *psMemInfo,
558#if defined (SUPPORT_SID_INTERFACE)
559 IMG_SID *phMemInfo);
560#else
484 IMG_HANDLE *phMemInfo); 561 IMG_HANDLE *phMemInfo);
562#endif
485 563
486IMG_IMPORT 564IMG_IMPORT
487PVRSRV_ERROR IMG_CALLCONV PVRSRVReserveDeviceVirtualMem(IMG_CONST PVRSRV_DEV_DATA *psDevData, 565PVRSRV_ERROR IMG_CALLCONV PVRSRVReserveDeviceVirtualMem(IMG_CONST PVRSRV_DEV_DATA *psDevData,
566#if defined (SUPPORT_SID_INTERFACE)
567 IMG_SID hDevMemHeap,
568#else
488 IMG_HANDLE hDevMemHeap, 569 IMG_HANDLE hDevMemHeap,
570#endif
489 IMG_DEV_VIRTADDR *psDevVAddr, 571 IMG_DEV_VIRTADDR *psDevVAddr,
490 IMG_SIZE_T ui32Size, 572 IMG_SIZE_T ui32Size,
491 IMG_SIZE_T ui32Alignment, 573 IMG_SIZE_T ui32Alignment,
@@ -496,8 +578,13 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVFreeDeviceVirtualMem(IMG_CONST PVRSRV_DEV_DATA *
496 578
497IMG_IMPORT 579IMG_IMPORT
498PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceMemory (IMG_CONST PVRSRV_DEV_DATA *psDevData, 580PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceMemory (IMG_CONST PVRSRV_DEV_DATA *psDevData,
581#if defined (SUPPORT_SID_INTERFACE)
582 IMG_SID hKernelMemInfo,
583 IMG_SID hDstDevMemHeap,
584#else
499 IMG_HANDLE hKernelMemInfo, 585 IMG_HANDLE hKernelMemInfo,
500 IMG_HANDLE hDstDevMemHeap, 586 IMG_HANDLE hDstDevMemHeap,
587#endif
501 PVRSRV_CLIENT_MEM_INFO **ppsDstMemInfo); 588 PVRSRV_CLIENT_MEM_INFO **ppsDstMemInfo);
502 589
503IMG_IMPORT 590IMG_IMPORT
@@ -516,7 +603,11 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVUnmapExtMemory (IMG_CONST PVRSRV_DEV_DATA *psDev
516 603
517IMG_IMPORT 604IMG_IMPORT
518PVRSRV_ERROR IMG_CALLCONV PVRSRVWrapExtMemory(IMG_CONST PVRSRV_DEV_DATA *psDevData, 605PVRSRV_ERROR IMG_CALLCONV PVRSRVWrapExtMemory(IMG_CONST PVRSRV_DEV_DATA *psDevData,
606#if defined (SUPPORT_SID_INTERFACE)
607 IMG_SID hDevMemContext,
608#else
519 IMG_HANDLE hDevMemContext, 609 IMG_HANDLE hDevMemContext,
610#endif
520 IMG_SIZE_T ui32ByteSize, 611 IMG_SIZE_T ui32ByteSize,
521 IMG_SIZE_T ui32PageOffset, 612 IMG_SIZE_T ui32PageOffset,
522 IMG_BOOL bPhysContig, 613 IMG_BOOL bPhysContig,
@@ -534,8 +625,13 @@ PVRSRV_ERROR PVRSRVChangeDeviceMemoryAttributes(IMG_CONST PVRSRV_DEV_DATA *psD
534 625
535IMG_IMPORT 626IMG_IMPORT
536PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceClassMemory (IMG_CONST PVRSRV_DEV_DATA *psDevData, 627PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceClassMemory (IMG_CONST PVRSRV_DEV_DATA *psDevData,
628#if defined (SUPPORT_SID_INTERFACE)
629 IMG_SID hDevMemContext,
630 IMG_SID hDeviceClassBuffer,
631#else
537 IMG_HANDLE hDevMemContext, 632 IMG_HANDLE hDevMemContext,
538 IMG_HANDLE hDeviceClassBuffer, 633 IMG_HANDLE hDeviceClassBuffer,
634#endif
539 PVRSRV_CLIENT_MEM_INFO **ppsMemInfo); 635 PVRSRV_CLIENT_MEM_INFO **ppsMemInfo);
540IMG_IMPORT 636IMG_IMPORT
541PVRSRV_ERROR IMG_CALLCONV PVRSRVUnmapDeviceClassMemory (IMG_CONST PVRSRV_DEV_DATA *psDevData, 637PVRSRV_ERROR IMG_CALLCONV PVRSRVUnmapDeviceClassMemory (IMG_CONST PVRSRV_DEV_DATA *psDevData,
@@ -554,6 +650,23 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVUnmapPhysToUserSpace(IMG_CONST PVRSRV_DEV_DATA *
554 IMG_PVOID pvUserAddr, 650 IMG_PVOID pvUserAddr,
555 IMG_PVOID pvProcess); 651 IMG_PVOID pvProcess);
556 652
653#if defined(LINUX)
654IMG_IMPORT
655PVRSRV_ERROR IMG_CALLCONV PVRSRVExportDeviceMem2(IMG_CONST PVRSRV_DEV_DATA *psDevData,
656 PVRSRV_CLIENT_MEM_INFO *psMemInfo,
657 IMG_INT *iFd);
658
659IMG_IMPORT
660PVRSRV_ERROR IMG_CALLCONV PVRSRVMapDeviceMemory2(IMG_CONST PVRSRV_DEV_DATA *psDevData,
661 IMG_INT iFd,
662#if defined (SUPPORT_SID_INTERFACE)
663 IMG_SID hDstDevMemHeap,
664#else
665 IMG_HANDLE hDstDevMemHeap,
666#endif
667 PVRSRV_CLIENT_MEM_INFO **ppsDstMemInfo);
668#endif
669
557typedef enum _PVRSRV_SYNCVAL_MODE_ 670typedef enum _PVRSRV_SYNCVAL_MODE_
558{ 671{
559 PVRSRV_SYNCVAL_READ = IMG_TRUE, 672 PVRSRV_SYNCVAL_READ = IMG_TRUE,
@@ -611,7 +724,11 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVEnumDCDims (IMG_HANDLE hDevice,
611 724
612IMG_IMPORT 725IMG_IMPORT
613PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDCSystemBuffer(IMG_HANDLE hDevice, 726PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDCSystemBuffer(IMG_HANDLE hDevice,
727#if defined (SUPPORT_SID_INTERFACE)
728 IMG_SID *phBuffer);
729#else
614 IMG_HANDLE *phBuffer); 730 IMG_HANDLE *phBuffer);
731#endif
615 732
616IMG_IMPORT 733IMG_IMPORT
617PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDCInfo(IMG_HANDLE hDevice, 734PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDCInfo(IMG_HANDLE hDevice,
@@ -625,48 +742,89 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVCreateDCSwapChain (IMG_HANDLE hDevice,
625 IMG_UINT32 ui32BufferCount, 742 IMG_UINT32 ui32BufferCount,
626 IMG_UINT32 ui32OEMFlags, 743 IMG_UINT32 ui32OEMFlags,
627 IMG_UINT32 *pui32SwapChainID, 744 IMG_UINT32 *pui32SwapChainID,
745#if defined (SUPPORT_SID_INTERFACE)
746 IMG_SID *phSwapChain);
747#else
628 IMG_HANDLE *phSwapChain); 748 IMG_HANDLE *phSwapChain);
749#endif
629 750
630IMG_IMPORT 751IMG_IMPORT
631PVRSRV_ERROR IMG_CALLCONV PVRSRVDestroyDCSwapChain (IMG_HANDLE hDevice, 752PVRSRV_ERROR IMG_CALLCONV PVRSRVDestroyDCSwapChain (IMG_HANDLE hDevice,
753#if defined (SUPPORT_SID_INTERFACE)
754 IMG_SID hSwapChain);
755#else
632 IMG_HANDLE hSwapChain); 756 IMG_HANDLE hSwapChain);
757#endif
633 758
634IMG_IMPORT 759IMG_IMPORT
635PVRSRV_ERROR IMG_CALLCONV PVRSRVSetDCDstRect (IMG_HANDLE hDevice, 760PVRSRV_ERROR IMG_CALLCONV PVRSRVSetDCDstRect (IMG_HANDLE hDevice,
761#if defined (SUPPORT_SID_INTERFACE)
762 IMG_SID hSwapChain,
763#else
636 IMG_HANDLE hSwapChain, 764 IMG_HANDLE hSwapChain,
765#endif
637 IMG_RECT *psDstRect); 766 IMG_RECT *psDstRect);
638 767
639IMG_IMPORT 768IMG_IMPORT
640PVRSRV_ERROR IMG_CALLCONV PVRSRVSetDCSrcRect (IMG_HANDLE hDevice, 769PVRSRV_ERROR IMG_CALLCONV PVRSRVSetDCSrcRect (IMG_HANDLE hDevice,
770#if defined (SUPPORT_SID_INTERFACE)
771 IMG_SID hSwapChain,
772#else
641 IMG_HANDLE hSwapChain, 773 IMG_HANDLE hSwapChain,
774#endif
642 IMG_RECT *psSrcRect); 775 IMG_RECT *psSrcRect);
643 776
644IMG_IMPORT 777IMG_IMPORT
645PVRSRV_ERROR IMG_CALLCONV PVRSRVSetDCDstColourKey (IMG_HANDLE hDevice, 778PVRSRV_ERROR IMG_CALLCONV PVRSRVSetDCDstColourKey (IMG_HANDLE hDevice,
779#if defined (SUPPORT_SID_INTERFACE)
780 IMG_SID hSwapChain,
781#else
646 IMG_HANDLE hSwapChain, 782 IMG_HANDLE hSwapChain,
783#endif
647 IMG_UINT32 ui32CKColour); 784 IMG_UINT32 ui32CKColour);
648 785
649IMG_IMPORT 786IMG_IMPORT
650PVRSRV_ERROR IMG_CALLCONV PVRSRVSetDCSrcColourKey (IMG_HANDLE hDevice, 787PVRSRV_ERROR IMG_CALLCONV PVRSRVSetDCSrcColourKey (IMG_HANDLE hDevice,
788#if defined (SUPPORT_SID_INTERFACE)
789 IMG_SID hSwapChain,
790#else
651 IMG_HANDLE hSwapChain, 791 IMG_HANDLE hSwapChain,
792#endif
652 IMG_UINT32 ui32CKColour); 793 IMG_UINT32 ui32CKColour);
653 794
654IMG_IMPORT 795IMG_IMPORT
655PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDCBuffers(IMG_HANDLE hDevice, 796PVRSRV_ERROR IMG_CALLCONV PVRSRVGetDCBuffers(IMG_HANDLE hDevice,
797#if defined (SUPPORT_SID_INTERFACE)
798 IMG_SID hSwapChain,
799 IMG_SID *phBuffer);
800#else
656 IMG_HANDLE hSwapChain, 801 IMG_HANDLE hSwapChain,
657 IMG_HANDLE *phBuffer); 802 IMG_HANDLE *phBuffer);
803#endif
658 804
659IMG_IMPORT 805IMG_IMPORT
660PVRSRV_ERROR IMG_CALLCONV PVRSRVSwapToDCBuffer (IMG_HANDLE hDevice, 806PVRSRV_ERROR IMG_CALLCONV PVRSRVSwapToDCBuffer (IMG_HANDLE hDevice,
807#if defined (SUPPORT_SID_INTERFACE)
808 IMG_SID hBuffer,
809#else
661 IMG_HANDLE hBuffer, 810 IMG_HANDLE hBuffer,
811#endif
662 IMG_UINT32 ui32ClipRectCount, 812 IMG_UINT32 ui32ClipRectCount,
663 IMG_RECT *psClipRect, 813 IMG_RECT *psClipRect,
664 IMG_UINT32 ui32SwapInterval, 814 IMG_UINT32 ui32SwapInterval,
815#if defined (SUPPORT_SID_INTERFACE)
816 IMG_SID hPrivateTag);
817#else
665 IMG_HANDLE hPrivateTag); 818 IMG_HANDLE hPrivateTag);
819#endif
666 820
667IMG_IMPORT 821IMG_IMPORT
668PVRSRV_ERROR IMG_CALLCONV PVRSRVSwapToDCSystem (IMG_HANDLE hDevice, 822PVRSRV_ERROR IMG_CALLCONV PVRSRVSwapToDCSystem (IMG_HANDLE hDevice,
823#if defined (SUPPORT_SID_INTERFACE)
824 IMG_SID hSwapChain);
825#else
669 IMG_HANDLE hSwapChain); 826 IMG_HANDLE hSwapChain);
827#endif
670 828
671 829
672IMG_IMPORT 830IMG_IMPORT
@@ -684,7 +842,11 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVGetBCBufferInfo(IMG_HANDLE hDevice,
684IMG_IMPORT 842IMG_IMPORT
685PVRSRV_ERROR IMG_CALLCONV PVRSRVGetBCBuffer(IMG_HANDLE hDevice, 843PVRSRV_ERROR IMG_CALLCONV PVRSRVGetBCBuffer(IMG_HANDLE hDevice,
686 IMG_UINT32 ui32BufferIndex, 844 IMG_UINT32 ui32BufferIndex,
845#if defined (SUPPORT_SID_INTERFACE)
846 IMG_SID *phBuffer);
847#else
687 IMG_HANDLE *phBuffer); 848 IMG_HANDLE *phBuffer);
849#endif
688 850
689 851
690IMG_IMPORT 852IMG_IMPORT
@@ -698,7 +860,11 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVPDumpStopInitPhase(IMG_CONST PVRSRV_CONNECTION *
698 860
699IMG_IMPORT 861IMG_IMPORT
700PVRSRV_ERROR IMG_CALLCONV PVRSRVPDumpMemPol(IMG_CONST PVRSRV_CONNECTION *psConnection, 862PVRSRV_ERROR IMG_CALLCONV PVRSRVPDumpMemPol(IMG_CONST PVRSRV_CONNECTION *psConnection,
863#if defined (SUPPORT_SID_INTERFACE)
864 IMG_SID hKernelMemInfo,
865#else
701 PVRSRV_CLIENT_MEM_INFO *psMemInfo, 866 PVRSRV_CLIENT_MEM_INFO *psMemInfo,
867#endif
702 IMG_UINT32 ui32Offset, 868 IMG_UINT32 ui32Offset,
703 IMG_UINT32 ui32Value, 869 IMG_UINT32 ui32Value,
704 IMG_UINT32 ui32Mask, 870 IMG_UINT32 ui32Mask,
@@ -707,10 +873,23 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVPDumpMemPol(IMG_CONST PVRSRV_CONNECTION *psConne
707 873
708IMG_IMPORT 874IMG_IMPORT
709PVRSRV_ERROR IMG_CALLCONV PVRSRVPDumpSyncPol(IMG_CONST PVRSRV_CONNECTION *psConnection, 875PVRSRV_ERROR IMG_CALLCONV PVRSRVPDumpSyncPol(IMG_CONST PVRSRV_CONNECTION *psConnection,
710 PVRSRV_CLIENT_SYNC_INFO *psClientSyncInfo, 876#if defined (SUPPORT_SID_INTERFACE)
711 IMG_BOOL bIsRead, 877 IMG_SID hKernelSyncInfo,
712 IMG_UINT32 ui32Value, 878#else
713 IMG_UINT32 ui32Mask); 879 PVRSRV_CLIENT_SYNC_INFO *psClientSyncInfo,
880#endif
881 IMG_BOOL bIsRead,
882 IMG_UINT32 ui32Value,
883 IMG_UINT32 ui32Mask);
884
885IMG_IMPORT
886PVRSRV_ERROR IMG_CALLCONV PVRSRVPDumpSyncPol2(IMG_CONST PVRSRV_CONNECTION *psConnection,
887#if defined (SUPPORT_SID_INTERFACE)
888 IMG_SID hKernelSyncInfo,
889#else
890 PVRSRV_CLIENT_SYNC_INFO *psClientSyncInfo,
891#endif
892 IMG_BOOL bIsRead);
714 893
715IMG_IMPORT 894IMG_IMPORT
716PVRSRV_ERROR IMG_CALLCONV PVRSRVPDumpMem(IMG_CONST PVRSRV_CONNECTION *psConnection, 895PVRSRV_ERROR IMG_CALLCONV PVRSRVPDumpMem(IMG_CONST PVRSRV_CONNECTION *psConnection,
@@ -758,15 +937,21 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVPDumpPDDevPAddr(IMG_CONST PVRSRV_CONNECTION *psC
758 IMG_UINT32 ui32Offset, 937 IMG_UINT32 ui32Offset,
759 IMG_DEV_PHYADDR sPDDevPAddr); 938 IMG_DEV_PHYADDR sPDDevPAddr);
760 939
940#if !defined(USE_CODE)
761IMG_IMPORT 941IMG_IMPORT
762PVRSRV_ERROR IMG_CALLCONV PVRSRVPDumpMemPages(IMG_CONST PVRSRV_CONNECTION *psConnection, 942PVRSRV_ERROR IMG_CALLCONV PVRSRVPDumpMemPages(IMG_CONST PVRSRV_DEV_DATA *psDevData,
763 IMG_HANDLE hKernelMemInfo, 943#if defined (SUPPORT_SID_INTERFACE)
764 IMG_DEV_PHYADDR *pPages, 944 IMG_SID hKernelMemInfo,
765 IMG_UINT32 ui32NumPages, 945#else
766 IMG_DEV_VIRTADDR sDevAddr, 946 IMG_HANDLE hKernelMemInfo,
767 IMG_UINT32 ui32Start, 947#endif
768 IMG_UINT32 ui32Length, 948 IMG_DEV_PHYADDR *pPages,
769 IMG_BOOL bContinuous); 949 IMG_UINT32 ui32NumPages,
950 IMG_DEV_VIRTADDR sDevVAddr,
951 IMG_UINT32 ui32Start,
952 IMG_UINT32 ui32Length,
953 IMG_UINT32 ui32Flags);
954#endif
770 955
771IMG_IMPORT 956IMG_IMPORT
772PVRSRV_ERROR IMG_CALLCONV PVRSRVPDumpSetFrame(IMG_CONST PVRSRV_CONNECTION *psConnection, 957PVRSRV_ERROR IMG_CALLCONV PVRSRVPDumpSetFrame(IMG_CONST PVRSRV_CONNECTION *psConnection,
@@ -812,7 +997,11 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVPDumpBitmap(IMG_CONST PVRSRV_DEV_DATA *psDevData
812 IMG_UINT32 ui32Height, 997 IMG_UINT32 ui32Height,
813 IMG_UINT32 ui32StrideInBytes, 998 IMG_UINT32 ui32StrideInBytes,
814 IMG_DEV_VIRTADDR sDevBaseAddr, 999 IMG_DEV_VIRTADDR sDevBaseAddr,
1000#if defined (SUPPORT_SID_INTERFACE)
1001 IMG_SID hDevMemContext,
1002#else
815 IMG_HANDLE hDevMemContext, 1003 IMG_HANDLE hDevMemContext,
1004#endif
816 IMG_UINT32 ui32Size, 1005 IMG_UINT32 ui32Size,
817 PDUMP_PIXEL_FORMAT ePixelFormat, 1006 PDUMP_PIXEL_FORMAT ePixelFormat,
818 PDUMP_MEM_FORMAT eMemFormat, 1007 PDUMP_MEM_FORMAT eMemFormat,
@@ -843,7 +1032,7 @@ IMG_IMPORT PVRSRV_ERROR PVRSRVGetLibFuncAddr(IMG_HANDLE hExtDrv, const IMG_CHAR
843IMG_IMPORT IMG_UINT32 PVRSRVClockus (void); 1032IMG_IMPORT IMG_UINT32 PVRSRVClockus (void);
844IMG_IMPORT IMG_VOID PVRSRVWaitus (IMG_UINT32 ui32Timeus); 1033IMG_IMPORT IMG_VOID PVRSRVWaitus (IMG_UINT32 ui32Timeus);
845IMG_IMPORT IMG_VOID PVRSRVReleaseThreadQuanta (void); 1034IMG_IMPORT IMG_VOID PVRSRVReleaseThreadQuanta (void);
846IMG_IMPORT IMG_UINTPTR_T IMG_CALLCONV PVRSRVGetCurrentProcessID(void); 1035IMG_IMPORT IMG_UINT32 IMG_CALLCONV PVRSRVGetCurrentProcessID(void);
847IMG_IMPORT IMG_CHAR * IMG_CALLCONV PVRSRVSetLocale(const IMG_CHAR *pszLocale); 1036IMG_IMPORT IMG_CHAR * IMG_CALLCONV PVRSRVSetLocale(const IMG_CHAR *pszLocale);
848 1037
849 1038
@@ -939,21 +1128,37 @@ IMG_IMPORT IMG_PVOID IMG_CALLCONV PVRSRVReallocUserModeMemTracking(IMG_VOID *pvM
939#endif 1128#endif
940 1129
941IMG_IMPORT PVRSRV_ERROR PVRSRVEventObjectWait(const PVRSRV_CONNECTION *psConnection, 1130IMG_IMPORT PVRSRV_ERROR PVRSRVEventObjectWait(const PVRSRV_CONNECTION *psConnection,
1131#if defined (SUPPORT_SID_INTERFACE)
1132 IMG_EVENTSID hOSEvent);
1133#else
942 IMG_HANDLE hOSEvent); 1134 IMG_HANDLE hOSEvent);
1135#endif
943 1136
944IMG_IMPORT 1137IMG_IMPORT
945PVRSRV_ERROR IMG_CALLCONV PVRSRVCreateSyncInfoModObj(const PVRSRV_CONNECTION *psConnection, 1138PVRSRV_ERROR IMG_CALLCONV PVRSRVCreateSyncInfoModObj(const PVRSRV_CONNECTION *psConnection,
1139#if defined (SUPPORT_SID_INTERFACE)
1140 IMG_SID *phKernelSyncInfoModObj);
1141#else
946 IMG_HANDLE *phKernelSyncInfoModObj); 1142 IMG_HANDLE *phKernelSyncInfoModObj);
1143#endif
947 1144
948IMG_IMPORT 1145IMG_IMPORT
949PVRSRV_ERROR IMG_CALLCONV PVRSRVDestroySyncInfoModObj(const PVRSRV_CONNECTION *psConnection, 1146PVRSRV_ERROR IMG_CALLCONV PVRSRVDestroySyncInfoModObj(const PVRSRV_CONNECTION *psConnection,
1147#if defined (SUPPORT_SID_INTERFACE)
1148 IMG_SID hKernelSyncInfoModObj);
1149#else
950 IMG_HANDLE hKernelSyncInfoModObj); 1150 IMG_HANDLE hKernelSyncInfoModObj);
1151#endif
951 1152
952 1153
953 1154
954IMG_IMPORT 1155IMG_IMPORT
955PVRSRV_ERROR IMG_CALLCONV PVRSRVModifyPendingSyncOps(const PVRSRV_CONNECTION *psConnection, 1156PVRSRV_ERROR IMG_CALLCONV PVRSRVModifyPendingSyncOps(const PVRSRV_CONNECTION *psConnection,
1157#if defined (SUPPORT_SID_INTERFACE)
1158 IMG_SID hKernelSyncInfoModObj,
1159#else
956 IMG_HANDLE hKernelSyncInfoModObj, 1160 IMG_HANDLE hKernelSyncInfoModObj,
1161#endif
957 PVRSRV_CLIENT_SYNC_INFO *psSyncInfo, 1162 PVRSRV_CLIENT_SYNC_INFO *psSyncInfo,
958 IMG_UINT32 ui32ModifyFlags, 1163 IMG_UINT32 ui32ModifyFlags,
959 IMG_UINT32 *pui32ReadOpsPending, 1164 IMG_UINT32 *pui32ReadOpsPending,
@@ -961,11 +1166,36 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVModifyPendingSyncOps(const PVRSRV_CONNECTION *ps
961 1166
962IMG_IMPORT 1167IMG_IMPORT
963PVRSRV_ERROR IMG_CALLCONV PVRSRVModifyCompleteSyncOps(const PVRSRV_CONNECTION *psConnection, 1168PVRSRV_ERROR IMG_CALLCONV PVRSRVModifyCompleteSyncOps(const PVRSRV_CONNECTION *psConnection,
1169#if defined (SUPPORT_SID_INTERFACE)
1170 IMG_SID hKernelSyncInfoModObj);
1171#else
964 IMG_HANDLE hKernelSyncInfoModObj); 1172 IMG_HANDLE hKernelSyncInfoModObj);
1173#endif
965 1174
966IMG_IMPORT 1175IMG_IMPORT
1176PVRSRV_ERROR IMG_CALLCONV PVRSRVSyncOpsTakeToken(const PVRSRV_CONNECTION *psConnection,
1177#if defined (SUPPORT_SID_INTERFACE)
1178 const IMG_SID hKernelSyncInfo,
1179#else
1180 const PVRSRV_CLIENT_SYNC_INFO *psSyncInfo,
1181#endif
1182 PVRSRV_SYNC_TOKEN *psSyncToken);
1183IMG_IMPORT
1184PVRSRV_ERROR IMG_CALLCONV PVRSRVSyncOpsFlushToToken(const PVRSRV_CONNECTION *psConnection,
1185#if defined (SUPPORT_SID_INTERFACE)
1186 const IMG_SID hKernelSyncInfo,
1187#else
1188 const PVRSRV_CLIENT_SYNC_INFO *psSyncInfo,
1189#endif
1190 const PVRSRV_SYNC_TOKEN *psSyncToken,
1191 IMG_BOOL bWait);
1192IMG_IMPORT
967PVRSRV_ERROR IMG_CALLCONV PVRSRVSyncOpsFlushToModObj(const PVRSRV_CONNECTION *psConnection, 1193PVRSRV_ERROR IMG_CALLCONV PVRSRVSyncOpsFlushToModObj(const PVRSRV_CONNECTION *psConnection,
1194#if defined (SUPPORT_SID_INTERFACE)
1195 IMG_SID hKernelSyncInfoModObj,
1196#else
968 IMG_HANDLE hKernelSyncInfoModObj, 1197 IMG_HANDLE hKernelSyncInfoModObj,
1198#endif
969 IMG_BOOL bWait); 1199 IMG_BOOL bWait);
970 1200
971IMG_IMPORT 1201IMG_IMPORT
diff --git a/drivers/gpu/pvr/servicesext.h b/drivers/gpu/pvr/servicesext.h
index 6f7270561a8..609df3138fc 100644
--- a/drivers/gpu/pvr/servicesext.h
+++ b/drivers/gpu/pvr/servicesext.h
@@ -86,6 +86,8 @@ typedef enum _PVRSRV_ERROR_
86 86
87 PVRSRV_ERROR_REGISTER_BASE_NOT_SET, 87 PVRSRV_ERROR_REGISTER_BASE_NOT_SET,
88 88
89 PVRSRV_ERROR_BM_BAD_SHAREMEM_HANDLE,
90
89 PVRSRV_ERROR_FAILED_TO_ALLOC_USER_MEM, 91 PVRSRV_ERROR_FAILED_TO_ALLOC_USER_MEM,
90 PVRSRV_ERROR_FAILED_TO_ALLOC_VP_MEMORY, 92 PVRSRV_ERROR_FAILED_TO_ALLOC_VP_MEMORY,
91 PVRSRV_ERROR_FAILED_TO_MAP_SHARED_PBDESC, 93 PVRSRV_ERROR_FAILED_TO_MAP_SHARED_PBDESC,
@@ -434,62 +436,62 @@ typedef enum _PVRSRV_PIXEL_FORMAT_ {
434 436
435 437
436 PVRSRV_PIXEL_FORMAT_G16R16 = 101, 438 PVRSRV_PIXEL_FORMAT_G16R16 = 101,
437 PVRSRV_PIXEL_FORMAT_G16R16F = 102, 439 PVRSRV_PIXEL_FORMAT_G16R16F = 102,
438 PVRSRV_PIXEL_FORMAT_G16R16_UINT = 103, 440 PVRSRV_PIXEL_FORMAT_G16R16_UINT = 103,
439 PVRSRV_PIXEL_FORMAT_G16R16_UNORM = 104, 441 PVRSRV_PIXEL_FORMAT_G16R16_UNORM = 104,
440 PVRSRV_PIXEL_FORMAT_G16R16_SINT = 105, 442 PVRSRV_PIXEL_FORMAT_G16R16_SINT = 105,
441 PVRSRV_PIXEL_FORMAT_G16R16_SNORM = 106, 443 PVRSRV_PIXEL_FORMAT_G16R16_SNORM = 106,
442
443
444 PVRSRV_PIXEL_FORMAT_R16 = 107,
445 PVRSRV_PIXEL_FORMAT_R16F = 108,
446 PVRSRV_PIXEL_FORMAT_R16_UINT = 109,
447 PVRSRV_PIXEL_FORMAT_R16_UNORM = 110,
448 PVRSRV_PIXEL_FORMAT_R16_SINT = 111,
449 PVRSRV_PIXEL_FORMAT_R16_SNORM = 112,
450
451
452 PVRSRV_PIXEL_FORMAT_X8R8G8B8 = 113,
453 PVRSRV_PIXEL_FORMAT_X8R8G8B8_UNORM = 114,
454 PVRSRV_PIXEL_FORMAT_X8R8G8B8_UNORM_SRGB = 115,
455
456 PVRSRV_PIXEL_FORMAT_A8R8G8B8 = 116,
457 PVRSRV_PIXEL_FORMAT_A8R8G8B8_UNORM = 117,
458 PVRSRV_PIXEL_FORMAT_A8R8G8B8_UNORM_SRGB = 118,
459 444
460 PVRSRV_PIXEL_FORMAT_A8B8G8R8 = 119, 445
461 PVRSRV_PIXEL_FORMAT_A8B8G8R8_UINT = 120, 446 PVRSRV_PIXEL_FORMAT_R16 = 107,
462 PVRSRV_PIXEL_FORMAT_A8B8G8R8_UNORM = 121, 447 PVRSRV_PIXEL_FORMAT_R16F = 108,
463 PVRSRV_PIXEL_FORMAT_A8B8G8R8_UNORM_SRGB = 122, 448 PVRSRV_PIXEL_FORMAT_R16_UINT = 109,
464 PVRSRV_PIXEL_FORMAT_A8B8G8R8_SINT = 123, 449 PVRSRV_PIXEL_FORMAT_R16_UNORM = 110,
465 PVRSRV_PIXEL_FORMAT_A8B8G8R8_SNORM = 124, 450 PVRSRV_PIXEL_FORMAT_R16_SINT = 111,
466 451 PVRSRV_PIXEL_FORMAT_R16_SNORM = 112,
467
468 PVRSRV_PIXEL_FORMAT_G8R8 = 125,
469 PVRSRV_PIXEL_FORMAT_G8R8_UINT = 126,
470 PVRSRV_PIXEL_FORMAT_G8R8_UNORM = 127,
471 PVRSRV_PIXEL_FORMAT_G8R8_SINT = 128,
472 PVRSRV_PIXEL_FORMAT_G8R8_SNORM = 129,
473 452
453
454 PVRSRV_PIXEL_FORMAT_X8R8G8B8 = 113,
455 PVRSRV_PIXEL_FORMAT_X8R8G8B8_UNORM = 114,
456 PVRSRV_PIXEL_FORMAT_X8R8G8B8_UNORM_SRGB = 115,
474 457
475 PVRSRV_PIXEL_FORMAT_A8 = 130, 458 PVRSRV_PIXEL_FORMAT_A8R8G8B8 = 116,
476 PVRSRV_PIXEL_FORMAT_R8 = 131, 459 PVRSRV_PIXEL_FORMAT_A8R8G8B8_UNORM = 117,
477 PVRSRV_PIXEL_FORMAT_R8_UINT = 132, 460 PVRSRV_PIXEL_FORMAT_A8R8G8B8_UNORM_SRGB = 118,
478 PVRSRV_PIXEL_FORMAT_R8_UNORM = 133,
479 PVRSRV_PIXEL_FORMAT_R8_SINT = 134,
480 PVRSRV_PIXEL_FORMAT_R8_SNORM = 135,
481 461
462 PVRSRV_PIXEL_FORMAT_A8B8G8R8 = 119,
463 PVRSRV_PIXEL_FORMAT_A8B8G8R8_UINT = 120,
464 PVRSRV_PIXEL_FORMAT_A8B8G8R8_UNORM = 121,
465 PVRSRV_PIXEL_FORMAT_A8B8G8R8_UNORM_SRGB = 122,
466 PVRSRV_PIXEL_FORMAT_A8B8G8R8_SINT = 123,
467 PVRSRV_PIXEL_FORMAT_A8B8G8R8_SNORM = 124,
482 468
483 PVRSRV_PIXEL_FORMAT_A2B10G10R10 = 136, 469
484 PVRSRV_PIXEL_FORMAT_A2B10G10R10_UNORM = 137, 470 PVRSRV_PIXEL_FORMAT_G8R8 = 125,
485 PVRSRV_PIXEL_FORMAT_A2B10G10R10_UINT = 138, 471 PVRSRV_PIXEL_FORMAT_G8R8_UINT = 126,
472 PVRSRV_PIXEL_FORMAT_G8R8_UNORM = 127,
473 PVRSRV_PIXEL_FORMAT_G8R8_SINT = 128,
474 PVRSRV_PIXEL_FORMAT_G8R8_SNORM = 129,
486 475
476
477 PVRSRV_PIXEL_FORMAT_A8 = 130,
478 PVRSRV_PIXEL_FORMAT_R8 = 131,
479 PVRSRV_PIXEL_FORMAT_R8_UINT = 132,
480 PVRSRV_PIXEL_FORMAT_R8_UNORM = 133,
481 PVRSRV_PIXEL_FORMAT_R8_SINT = 134,
482 PVRSRV_PIXEL_FORMAT_R8_SNORM = 135,
487 483
488 PVRSRV_PIXEL_FORMAT_B10G11R11 = 139, 484
489 PVRSRV_PIXEL_FORMAT_B10G11R11F = 140, 485 PVRSRV_PIXEL_FORMAT_A2B10G10R10 = 136,
486 PVRSRV_PIXEL_FORMAT_A2B10G10R10_UNORM = 137,
487 PVRSRV_PIXEL_FORMAT_A2B10G10R10_UINT = 138,
490 488
489
490 PVRSRV_PIXEL_FORMAT_B10G11R11 = 139,
491 PVRSRV_PIXEL_FORMAT_B10G11R11F = 140,
491 492
492 PVRSRV_PIXEL_FORMAT_X24G8R32 = 141, 493
494 PVRSRV_PIXEL_FORMAT_X24G8R32 = 141,
493 PVRSRV_PIXEL_FORMAT_G8R24 = 142, 495 PVRSRV_PIXEL_FORMAT_G8R24 = 142,
494 PVRSRV_PIXEL_FORMAT_X8R24 = 143, 496 PVRSRV_PIXEL_FORMAT_X8R24 = 143,
495 PVRSRV_PIXEL_FORMAT_E5B9G9R9 = 144, 497 PVRSRV_PIXEL_FORMAT_E5B9G9R9 = 144,
@@ -511,20 +513,20 @@ typedef enum _PVRSRV_PIXEL_FORMAT_ {
511 PVRSRV_PIXEL_FORMAT_RESERVED19 = 159, 513 PVRSRV_PIXEL_FORMAT_RESERVED19 = 159,
512 PVRSRV_PIXEL_FORMAT_RESERVED20 = 160, 514 PVRSRV_PIXEL_FORMAT_RESERVED20 = 160,
513 515
516
517 PVRSRV_PIXEL_FORMAT_UBYTE4 = 161,
518 PVRSRV_PIXEL_FORMAT_SHORT4 = 162,
519 PVRSRV_PIXEL_FORMAT_SHORT4N = 163,
520 PVRSRV_PIXEL_FORMAT_USHORT4N = 164,
521 PVRSRV_PIXEL_FORMAT_SHORT2N = 165,
522 PVRSRV_PIXEL_FORMAT_SHORT2 = 166,
523 PVRSRV_PIXEL_FORMAT_USHORT2N = 167,
524 PVRSRV_PIXEL_FORMAT_UDEC3 = 168,
525 PVRSRV_PIXEL_FORMAT_DEC3N = 169,
526 PVRSRV_PIXEL_FORMAT_F16_2 = 170,
527 PVRSRV_PIXEL_FORMAT_F16_4 = 171,
514 528
515 PVRSRV_PIXEL_FORMAT_UBYTE4 = 161, 529
516 PVRSRV_PIXEL_FORMAT_SHORT4 = 162,
517 PVRSRV_PIXEL_FORMAT_SHORT4N = 163,
518 PVRSRV_PIXEL_FORMAT_USHORT4N = 164,
519 PVRSRV_PIXEL_FORMAT_SHORT2N = 165,
520 PVRSRV_PIXEL_FORMAT_SHORT2 = 166,
521 PVRSRV_PIXEL_FORMAT_USHORT2N = 167,
522 PVRSRV_PIXEL_FORMAT_UDEC3 = 168,
523 PVRSRV_PIXEL_FORMAT_DEC3N = 169,
524 PVRSRV_PIXEL_FORMAT_F16_2 = 170,
525 PVRSRV_PIXEL_FORMAT_F16_4 = 171,
526
527
528 PVRSRV_PIXEL_FORMAT_L_F16 = 172, 530 PVRSRV_PIXEL_FORMAT_L_F16 = 172,
529 PVRSRV_PIXEL_FORMAT_L_F16_REP = 173, 531 PVRSRV_PIXEL_FORMAT_L_F16_REP = 173,
530 PVRSRV_PIXEL_FORMAT_L_F16_A_F16 = 174, 532 PVRSRV_PIXEL_FORMAT_L_F16_A_F16 = 174,
@@ -535,7 +537,7 @@ typedef enum _PVRSRV_PIXEL_FORMAT_ {
535 PVRSRV_PIXEL_FORMAT_A_F32 = 178, 537 PVRSRV_PIXEL_FORMAT_A_F32 = 178,
536 PVRSRV_PIXEL_FORMAT_L_F32_A_F32 = 179, 538 PVRSRV_PIXEL_FORMAT_L_F32_A_F32 = 179,
537 539
538 540
539 PVRSRV_PIXEL_FORMAT_PVRTC2 = 180, 541 PVRSRV_PIXEL_FORMAT_PVRTC2 = 180,
540 PVRSRV_PIXEL_FORMAT_PVRTC4 = 181, 542 PVRSRV_PIXEL_FORMAT_PVRTC4 = 181,
541 PVRSRV_PIXEL_FORMAT_PVRTCII2 = 182, 543 PVRSRV_PIXEL_FORMAT_PVRTCII2 = 182,
@@ -552,7 +554,7 @@ typedef enum _PVRSRV_PIXEL_FORMAT_ {
552 PVRSRV_PIXEL_FORMAT_MONO8 = 193, 554 PVRSRV_PIXEL_FORMAT_MONO8 = 193,
553 PVRSRV_PIXEL_FORMAT_MONO16 = 194, 555 PVRSRV_PIXEL_FORMAT_MONO16 = 194,
554 556
555 557
556 PVRSRV_PIXEL_FORMAT_C0_YUYV = 195, 558 PVRSRV_PIXEL_FORMAT_C0_YUYV = 195,
557 PVRSRV_PIXEL_FORMAT_C0_UYVY = 196, 559 PVRSRV_PIXEL_FORMAT_C0_UYVY = 196,
558 PVRSRV_PIXEL_FORMAT_C0_YVYU = 197, 560 PVRSRV_PIXEL_FORMAT_C0_YVYU = 197,
@@ -562,7 +564,7 @@ typedef enum _PVRSRV_PIXEL_FORMAT_ {
562 PVRSRV_PIXEL_FORMAT_C1_YVYU = 201, 564 PVRSRV_PIXEL_FORMAT_C1_YVYU = 201,
563 PVRSRV_PIXEL_FORMAT_C1_VYUY = 202, 565 PVRSRV_PIXEL_FORMAT_C1_VYUY = 202,
564 566
565 567
566 PVRSRV_PIXEL_FORMAT_C0_YUV420_2P_UV = 203, 568 PVRSRV_PIXEL_FORMAT_C0_YUV420_2P_UV = 203,
567 PVRSRV_PIXEL_FORMAT_C0_YUV420_2P_VU = 204, 569 PVRSRV_PIXEL_FORMAT_C0_YUV420_2P_VU = 204,
568 PVRSRV_PIXEL_FORMAT_C0_YUV420_3P = 205, 570 PVRSRV_PIXEL_FORMAT_C0_YUV420_3P = 205,
@@ -573,11 +575,19 @@ typedef enum _PVRSRV_PIXEL_FORMAT_ {
573 PVRSRV_PIXEL_FORMAT_A2B10G10R10F = 209, 575 PVRSRV_PIXEL_FORMAT_A2B10G10R10F = 209,
574 PVRSRV_PIXEL_FORMAT_B8G8R8_SINT = 210, 576 PVRSRV_PIXEL_FORMAT_B8G8R8_SINT = 210,
575 PVRSRV_PIXEL_FORMAT_PVRF32SIGNMASK = 211, 577 PVRSRV_PIXEL_FORMAT_PVRF32SIGNMASK = 211,
576 578
577 PVRSRV_PIXEL_FORMAT_ABGR4444 = 212, 579 PVRSRV_PIXEL_FORMAT_ABGR4444 = 212,
578 PVRSRV_PIXEL_FORMAT_ABGR1555 = 213, 580 PVRSRV_PIXEL_FORMAT_ABGR1555 = 213,
579 PVRSRV_PIXEL_FORMAT_BGR565 = 214, 581 PVRSRV_PIXEL_FORMAT_BGR565 = 214,
580 582
583
584 PVRSRV_PIXEL_FORMAT_C0_4KYUV420_2P_UV = 215,
585 PVRSRV_PIXEL_FORMAT_C0_4KYUV420_2P_VU = 216,
586 PVRSRV_PIXEL_FORMAT_C1_4KYUV420_2P_UV = 217,
587 PVRSRV_PIXEL_FORMAT_C1_4KYUV420_2P_VU = 218,
588 PVRSRV_PIXEL_FORMAT_P208 = 219,
589 PVRSRV_PIXEL_FORMAT_A8P8 = 220,
590
581 PVRSRV_PIXEL_FORMAT_FORCE_I32 = 0x7fffffff 591 PVRSRV_PIXEL_FORMAT_FORCE_I32 = 0x7fffffff
582 592
583} PVRSRV_PIXEL_FORMAT; 593} PVRSRV_PIXEL_FORMAT;
@@ -612,15 +622,15 @@ typedef enum _PVRSRV_ROTATION_ {
612 622
613typedef struct _PVRSRV_SYNC_DATA_ 623typedef struct _PVRSRV_SYNC_DATA_
614{ 624{
615 625
616 IMG_UINT32 ui32WriteOpsPending; 626 IMG_UINT32 ui32WriteOpsPending;
617 volatile IMG_UINT32 ui32WriteOpsComplete; 627 volatile IMG_UINT32 ui32WriteOpsComplete;
618 628
619 629
620 IMG_UINT32 ui32ReadOpsPending; 630 IMG_UINT32 ui32ReadOpsPending;
621 volatile IMG_UINT32 ui32ReadOpsComplete; 631 volatile IMG_UINT32 ui32ReadOpsComplete;
622 632
623 633
624 IMG_UINT32 ui32LastOpDumpVal; 634 IMG_UINT32 ui32LastOpDumpVal;
625 IMG_UINT32 ui32LastReadOpDumpVal; 635 IMG_UINT32 ui32LastReadOpDumpVal;
626 636
@@ -628,30 +638,37 @@ typedef struct _PVRSRV_SYNC_DATA_
628 638
629typedef struct _PVRSRV_CLIENT_SYNC_INFO_ 639typedef struct _PVRSRV_CLIENT_SYNC_INFO_
630{ 640{
641
642 PVRSRV_SYNC_DATA *psSyncData;
631 643
632 PVRSRV_SYNC_DATA *psSyncData; 644
633
634
635
636 645
637 646
647
638 IMG_DEV_VIRTADDR sWriteOpsCompleteDevVAddr; 648 IMG_DEV_VIRTADDR sWriteOpsCompleteDevVAddr;
639 649
640 650
641 IMG_DEV_VIRTADDR sReadOpsCompleteDevVAddr; 651 IMG_DEV_VIRTADDR sReadOpsCompleteDevVAddr;
642 652
653
654#if defined (SUPPORT_SID_INTERFACE)
655 IMG_SID hMappingInfo;
643 656
657
658 IMG_SID hKernelSyncInfo;
659#else
644 IMG_HANDLE hMappingInfo; 660 IMG_HANDLE hMappingInfo;
645 661
646 662
647 IMG_HANDLE hKernelSyncInfo; 663 IMG_HANDLE hKernelSyncInfo;
664#endif
648 665
649} PVRSRV_CLIENT_SYNC_INFO, *PPVRSRV_CLIENT_SYNC_INFO; 666} PVRSRV_CLIENT_SYNC_INFO, *PPVRSRV_CLIENT_SYNC_INFO;
650 667
651typedef struct PVRSRV_RESOURCE_TAG 668typedef struct PVRSRV_RESOURCE_TAG
652{ 669{
653 volatile IMG_UINT32 ui32Lock; 670 volatile IMG_UINT32 ui32Lock;
654 IMG_UINT32 ui32ID; 671 IMG_UINT32 ui32ID;
655}PVRSRV_RESOURCE; 672}PVRSRV_RESOURCE;
656typedef PVRSRV_RESOURCE PVRSRV_RES_HANDLE; 673typedef PVRSRV_RESOURCE PVRSRV_RES_HANDLE;
657 674
@@ -700,52 +717,52 @@ typedef struct DISPLAY_DIMS_TAG
700 717
701typedef struct DISPLAY_FORMAT_TAG 718typedef struct DISPLAY_FORMAT_TAG
702{ 719{
703 720
704 PVRSRV_PIXEL_FORMAT pixelformat; 721 PVRSRV_PIXEL_FORMAT pixelformat;
705} DISPLAY_FORMAT; 722} DISPLAY_FORMAT;
706 723
707typedef struct DISPLAY_SURF_ATTRIBUTES_TAG 724typedef struct DISPLAY_SURF_ATTRIBUTES_TAG
708{ 725{
709 726
710 PVRSRV_PIXEL_FORMAT pixelformat; 727 PVRSRV_PIXEL_FORMAT pixelformat;
711 728
712 DISPLAY_DIMS sDims; 729 DISPLAY_DIMS sDims;
713} DISPLAY_SURF_ATTRIBUTES; 730} DISPLAY_SURF_ATTRIBUTES;
714 731
715 732
716typedef struct DISPLAY_MODE_INFO_TAG 733typedef struct DISPLAY_MODE_INFO_TAG
717{ 734{
718 735
719 PVRSRV_PIXEL_FORMAT pixelformat; 736 PVRSRV_PIXEL_FORMAT pixelformat;
720 737
721 DISPLAY_DIMS sDims; 738 DISPLAY_DIMS sDims;
722 739
723 IMG_UINT32 ui32RefreshHZ; 740 IMG_UINT32 ui32RefreshHZ;
724 741
725 IMG_UINT32 ui32OEMFlags; 742 IMG_UINT32 ui32OEMFlags;
726} DISPLAY_MODE_INFO; 743} DISPLAY_MODE_INFO;
727 744
728 745
729 746
730#define MAX_DISPLAY_NAME_SIZE (50) 747#define MAX_DISPLAY_NAME_SIZE (50)
731 748
732typedef struct DISPLAY_INFO_TAG 749typedef struct DISPLAY_INFO_TAG
733{ 750{
734 751
735 IMG_UINT32 ui32MaxSwapChains; 752 IMG_UINT32 ui32MaxSwapChains;
736 753
737 IMG_UINT32 ui32MaxSwapChainBuffers; 754 IMG_UINT32 ui32MaxSwapChainBuffers;
738 755
739 IMG_UINT32 ui32MinSwapInterval; 756 IMG_UINT32 ui32MinSwapInterval;
740 757
741 IMG_UINT32 ui32MaxSwapInterval; 758 IMG_UINT32 ui32MaxSwapInterval;
742 759
743 IMG_UINT32 ui32PhysicalWidthmm; 760 IMG_UINT32 ui32PhysicalWidthmm;
744 IMG_UINT32 ui32PhysicalHeightmm; 761 IMG_UINT32 ui32PhysicalHeightmm;
745 762
746 IMG_CHAR szDisplayName[MAX_DISPLAY_NAME_SIZE]; 763 IMG_CHAR szDisplayName[MAX_DISPLAY_NAME_SIZE];
747#if defined(SUPPORT_HW_CURSOR) 764#if defined(SUPPORT_HW_CURSOR)
748 765
749 IMG_UINT16 ui32CursorWidth; 766 IMG_UINT16 ui32CursorWidth;
750 IMG_UINT16 ui32CursorHeight; 767 IMG_UINT16 ui32CursorHeight;
751#endif 768#endif
@@ -754,9 +771,9 @@ typedef struct DISPLAY_INFO_TAG
754typedef struct ACCESS_INFO_TAG 771typedef struct ACCESS_INFO_TAG
755{ 772{
756 IMG_UINT32 ui32Size; 773 IMG_UINT32 ui32Size;
757 IMG_UINT32 ui32FBPhysBaseAddress; 774 IMG_UINT32 ui32FBPhysBaseAddress;
758 IMG_UINT32 ui32FBMemAvailable; 775 IMG_UINT32 ui32FBMemAvailable;
759 IMG_UINT32 ui32SysPhysBaseAddress; 776 IMG_UINT32 ui32SysPhysBaseAddress;
760 IMG_UINT32 ui32SysSize; 777 IMG_UINT32 ui32SysSize;
761 IMG_UINT32 ui32DevIRQ; 778 IMG_UINT32 ui32DevIRQ;
762}ACCESS_INFO; 779}ACCESS_INFO;
@@ -769,11 +786,11 @@ typedef struct PVRSRV_CURSOR_SHAPE_TAG
769 IMG_INT16 i16XHot; 786 IMG_INT16 i16XHot;
770 IMG_INT16 i16YHot; 787 IMG_INT16 i16YHot;
771 788
789
790 IMG_VOID* pvMask;
791 IMG_INT16 i16MaskByteStride;
772 792
773 IMG_VOID* pvMask; 793
774 IMG_INT16 i16MaskByteStride;
775
776
777 IMG_VOID* pvColour; 794 IMG_VOID* pvColour;
778 IMG_INT16 i16ColourByteStride; 795 IMG_INT16 i16ColourByteStride;
779 PVRSRV_PIXEL_FORMAT eColourPixelFormat; 796 PVRSRV_PIXEL_FORMAT eColourPixelFormat;
@@ -786,20 +803,20 @@ typedef struct PVRSRV_CURSOR_SHAPE_TAG
786 803
787typedef struct PVRSRV_CURSOR_INFO_TAG 804typedef struct PVRSRV_CURSOR_INFO_TAG
788{ 805{
789 806
790 IMG_UINT32 ui32Flags; 807 IMG_UINT32 ui32Flags;
791 808
792 809
793 IMG_BOOL bVisible; 810 IMG_BOOL bVisible;
794 811
795 812
796 IMG_INT16 i16XPos; 813 IMG_INT16 i16XPos;
797 IMG_INT16 i16YPos; 814 IMG_INT16 i16YPos;
798 815
799 816
800 PVRSRV_CURSOR_SHAPE sCursorShape; 817 PVRSRV_CURSOR_SHAPE sCursorShape;
801 818
802 819
803 IMG_UINT32 ui32Rotation; 820 IMG_UINT32 ui32Rotation;
804 821
805} PVRSRV_CURSOR_INFO; 822} PVRSRV_CURSOR_INFO;
@@ -807,13 +824,14 @@ typedef struct PVRSRV_CURSOR_INFO_TAG
807#if defined(PDUMP_SUSPEND_IS_PER_THREAD) 824#if defined(PDUMP_SUSPEND_IS_PER_THREAD)
808typedef struct { 825typedef struct {
809 IMG_UINT32 threadId; 826 IMG_UINT32 threadId;
810 int suspendCount; 827 IMG_INT suspendCount;
811} PVRSRV_THREAD_SUSPEND_COUNT; 828} PVRSRV_THREAD_SUSPEND_COUNT;
812 829
813#define PVRSRV_PDUMP_SUSPEND_Q_NAME "PVRSRVPDumpSuspendMsgQ" 830#define PVRSRV_PDUMP_SUSPEND_Q_NAME "PVRSRVPDumpSuspendMsgQ"
814#define PVRSRV_PDUMP_SUSPEND_Q_LENGTH 8 831#define PVRSRV_PDUMP_SUSPEND_Q_LENGTH 8
815 832
816#endif 833#endif
834
817 835
818typedef struct _PVRSRV_REGISTRY_INFO_ 836typedef struct _PVRSRV_REGISTRY_INFO_
819{ 837{
@@ -835,11 +853,11 @@ PVRSRV_ERROR IMG_CALLCONV PVRSRVWriteRegistryString (PPVRSRV_REGISTRY_INFO psReg
835#define PVRSRV_BC_FLAGS_YUVCSC_BT601 (0 << 1) 853#define PVRSRV_BC_FLAGS_YUVCSC_BT601 (0 << 1)
836#define PVRSRV_BC_FLAGS_YUVCSC_BT709 (1 << 1) 854#define PVRSRV_BC_FLAGS_YUVCSC_BT709 (1 << 1)
837 855
838#define MAX_BUFFER_DEVICE_NAME_SIZE (50) 856#define MAX_BUFFER_DEVICE_NAME_SIZE (50)
839 857
840typedef struct BUFFER_INFO_TAG 858typedef struct BUFFER_INFO_TAG
841{ 859{
842 IMG_UINT32 ui32BufferCount; 860 IMG_UINT32 ui32BufferCount;
843 IMG_UINT32 ui32BufferDeviceID; 861 IMG_UINT32 ui32BufferDeviceID;
844 PVRSRV_PIXEL_FORMAT pixelformat; 862 PVRSRV_PIXEL_FORMAT pixelformat;
845 IMG_UINT32 ui32ByteStride; 863 IMG_UINT32 ui32ByteStride;
@@ -857,4 +875,4 @@ typedef enum _OVERLAY_DEINTERLACE_MODE_
857 BOB_EVEN_NONINTERLEAVED 875 BOB_EVEN_NONINTERLEAVED
858} OVERLAY_DEINTERLACE_MODE; 876} OVERLAY_DEINTERLACE_MODE;
859 877
860#endif 878#endif
diff --git a/drivers/gpu/pvr/servicesint.h b/drivers/gpu/pvr/servicesint.h
index bc5aeb8dc0b..de404249054 100644
--- a/drivers/gpu/pvr/servicesint.h
+++ b/drivers/gpu/pvr/servicesint.h
@@ -68,7 +68,7 @@ typedef struct _PVRSRV_KERNEL_MEM_INFO_
68 IMG_UINT32 ui32Flags; 68 IMG_UINT32 ui32Flags;
69 69
70 70
71 IMG_SIZE_T ui32AllocSize; 71 IMG_SIZE_T uAllocSize;
72 72
73 73
74 PVRSRV_MEMBLK sMemBlk; 74 PVRSRV_MEMBLK sMemBlk;
@@ -97,6 +97,31 @@ typedef struct _PVRSRV_KERNEL_MEM_INFO_
97 struct _PVRSRV_KERNEL_SYNC_INFO_ *psKernelSyncInfo; 97 struct _PVRSRV_KERNEL_SYNC_INFO_ *psKernelSyncInfo;
98 98
99 PVRSRV_MEMTYPE memType; 99 PVRSRV_MEMTYPE memType;
100
101
102
103
104
105
106
107
108 struct {
109
110
111 IMG_BOOL bInUse;
112
113
114 IMG_HANDLE hDevCookieInt;
115
116
117 IMG_UINT32 ui32ShareIndex;
118
119
120
121 IMG_UINT32 ui32OrigReqAttribs;
122 IMG_UINT32 ui32OrigReqSize;
123 IMG_UINT32 ui32OrigReqAlignment;
124 } sShareMemWorkaround;
100} PVRSRV_KERNEL_MEM_INFO; 125} PVRSRV_KERNEL_MEM_INFO;
101 126
102 127
@@ -120,6 +145,9 @@ typedef struct _PVRSRV_KERNEL_SYNC_INFO_
120 145
121 146
122 IMG_HANDLE hResItem; 147 IMG_HANDLE hResItem;
148
149
150 IMG_UINT32 ui32UID;
123} PVRSRV_KERNEL_SYNC_INFO; 151} PVRSRV_KERNEL_SYNC_INFO;
124 152
125typedef struct _PVRSRV_DEVICE_SYNC_OBJECT_ 153typedef struct _PVRSRV_DEVICE_SYNC_OBJECT_
@@ -141,14 +169,14 @@ typedef struct _PVRSRV_SYNC_OBJECT
141 169
142typedef struct _PVRSRV_COMMAND 170typedef struct _PVRSRV_COMMAND
143{ 171{
144 IMG_SIZE_T ui32CmdSize; 172 IMG_SIZE_T uCmdSize;
145 IMG_UINT32 ui32DevIndex; 173 IMG_UINT32 ui32DevIndex;
146 IMG_UINT32 CommandType; 174 IMG_UINT32 CommandType;
147 IMG_UINT32 ui32DstSyncCount; 175 IMG_UINT32 ui32DstSyncCount;
148 IMG_UINT32 ui32SrcSyncCount; 176 IMG_UINT32 ui32SrcSyncCount;
149 PVRSRV_SYNC_OBJECT *psDstSync; 177 PVRSRV_SYNC_OBJECT *psDstSync;
150 PVRSRV_SYNC_OBJECT *psSrcSync; 178 PVRSRV_SYNC_OBJECT *psSrcSync;
151 IMG_SIZE_T ui32DataSize; 179 IMG_SIZE_T uDataSize;
152 IMG_UINT32 ui32ProcessID; 180 IMG_UINT32 ui32ProcessID;
153 IMG_VOID *pvData; 181 IMG_VOID *pvData;
154}PVRSRV_COMMAND, *PPVRSRV_COMMAND; 182}PVRSRV_COMMAND, *PPVRSRV_COMMAND;
@@ -171,6 +199,75 @@ typedef struct _PVRSRV_QUEUE_INFO_
171 struct _PVRSRV_QUEUE_INFO_ *psNextKM; 199 struct _PVRSRV_QUEUE_INFO_ *psNextKM;
172}PVRSRV_QUEUE_INFO; 200}PVRSRV_QUEUE_INFO;
173 201
202
203typedef struct _PVRSRV_HEAP_INFO_KM_
204{
205 IMG_UINT32 ui32HeapID;
206 IMG_DEV_VIRTADDR sDevVAddrBase;
207
208 IMG_HANDLE hDevMemHeap;
209 IMG_UINT32 ui32HeapByteSize;
210 IMG_UINT32 ui32Attribs;
211 IMG_UINT32 ui32XTileStride;
212}PVRSRV_HEAP_INFO_KM;
213
214
215typedef struct _PVRSRV_EVENTOBJECT_KM_
216{
217
218 IMG_CHAR szName[EVENTOBJNAME_MAXLENGTH];
219
220 IMG_HANDLE hOSEventKM;
221
222} PVRSRV_EVENTOBJECT_KM;
223
224
225typedef struct _PVRSRV_MISC_INFO_KM_
226{
227 IMG_UINT32 ui32StateRequest;
228 IMG_UINT32 ui32StatePresent;
229
230
231 IMG_VOID *pvSOCTimerRegisterKM;
232 IMG_VOID *pvSOCTimerRegisterUM;
233 IMG_HANDLE hSOCTimerRegisterOSMemHandle;
234 IMG_HANDLE hSOCTimerRegisterMappingInfo;
235
236
237 IMG_VOID *pvSOCClockGateRegs;
238 IMG_UINT32 ui32SOCClockGateRegsSize;
239
240
241 IMG_CHAR *pszMemoryStr;
242 IMG_UINT32 ui32MemoryStrLen;
243
244
245 PVRSRV_EVENTOBJECT_KM sGlobalEventObject;
246 IMG_HANDLE hOSGlobalEvent;
247
248
249 IMG_UINT32 aui32DDKVersion[4];
250
251
252 struct
253 {
254
255 IMG_BOOL bDeferOp;
256
257
258 PVRSRV_MISC_INFO_CPUCACHEOP_TYPE eCacheOpType;
259
260 PVRSRV_KERNEL_MEM_INFO *psKernelMemInfo;
261
262
263 IMG_VOID *pvBaseVAddr;
264
265
266 IMG_UINT32 ui32Length;
267 } sCacheOpCtl;
268} PVRSRV_MISC_INFO_KM;
269
270
174typedef PVRSRV_ERROR (*PFN_INSERT_CMD) (PVRSRV_QUEUE_INFO*, 271typedef PVRSRV_ERROR (*PFN_INSERT_CMD) (PVRSRV_QUEUE_INFO*,
175 PVRSRV_COMMAND**, 272 PVRSRV_COMMAND**,
176 IMG_UINT32, 273 IMG_UINT32,
@@ -190,13 +287,17 @@ typedef struct PVRSRV_DEVICECLASS_BUFFER_TAG
190 IMG_HANDLE hExtDevice; 287 IMG_HANDLE hExtDevice;
191 IMG_HANDLE hExtBuffer; 288 IMG_HANDLE hExtBuffer;
192 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo; 289 PVRSRV_KERNEL_SYNC_INFO *psKernelSyncInfo;
193 290 IMG_UINT32 ui32MemMapRefCount;
194} PVRSRV_DEVICECLASS_BUFFER; 291} PVRSRV_DEVICECLASS_BUFFER;
195 292
196 293
197typedef struct PVRSRV_CLIENT_DEVICECLASS_INFO_TAG 294typedef struct PVRSRV_CLIENT_DEVICECLASS_INFO_TAG
198{ 295{
296#if defined (SUPPORT_SID_INTERFACE)
297 IMG_SID hDeviceKM;
298#else
199 IMG_HANDLE hDeviceKM; 299 IMG_HANDLE hDeviceKM;
300#endif
200 IMG_HANDLE hServices; 301 IMG_HANDLE hServices;
201} PVRSRV_CLIENT_DEVICECLASS_INFO; 302} PVRSRV_CLIENT_DEVICECLASS_INFO;
202 303
@@ -252,7 +353,11 @@ PVRSRV_ERROR PVRSRVQueueCommand(IMG_HANDLE hQueueInfo,
252 353
253IMG_IMPORT PVRSRV_ERROR IMG_CALLCONV 354IMG_IMPORT PVRSRV_ERROR IMG_CALLCONV
254PVRSRVGetMMUContextPDDevPAddr(const PVRSRV_CONNECTION *psConnection, 355PVRSRVGetMMUContextPDDevPAddr(const PVRSRV_CONNECTION *psConnection,
356#if defined (SUPPORT_SID_INTERFACE)
357 IMG_SID hDevMemContext,
358#else
255 IMG_HANDLE hDevMemContext, 359 IMG_HANDLE hDevMemContext,
360#endif
256 IMG_DEV_PHYADDR *sPDDevPAddr); 361 IMG_DEV_PHYADDR *sPDDevPAddr);
257 362
258IMG_IMPORT PVRSRV_ERROR IMG_CALLCONV 363IMG_IMPORT PVRSRV_ERROR IMG_CALLCONV
@@ -271,7 +376,11 @@ PVRSRVUnrefSharedSysMem(const PVRSRV_CONNECTION *psConnection,
271 376
272IMG_IMPORT PVRSRV_ERROR IMG_CALLCONV 377IMG_IMPORT PVRSRV_ERROR IMG_CALLCONV
273PVRSRVMapMemInfoMem(const PVRSRV_CONNECTION *psConnection, 378PVRSRVMapMemInfoMem(const PVRSRV_CONNECTION *psConnection,
379#if defined (SUPPORT_SID_INTERFACE)
380 IMG_SID hKernelMemInfo,
381#else
274 IMG_HANDLE hKernelMemInfo, 382 IMG_HANDLE hKernelMemInfo,
383#endif
275 PVRSRV_CLIENT_MEM_INFO **ppsClientMemInfo); 384 PVRSRV_CLIENT_MEM_INFO **ppsClientMemInfo);
276 385
277 386
diff --git a/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c b/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c
index e1b73201a12..c1d6979e3a3 100644
--- a/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c
+++ b/drivers/gpu/pvr/sgx/bridged_sgx_bridge.c
@@ -40,6 +40,7 @@
40#include "power.h" 40#include "power.h"
41#include "pvr_bridge_km.h" 41#include "pvr_bridge_km.h"
42#include "sgx_bridge_km.h" 42#include "sgx_bridge_km.h"
43#include "sgx_options.h"
43 44
44#if defined(SUPPORT_MSVDX) 45#if defined(SUPPORT_MSVDX)
45 #include "msvdx_bridge.h" 46 #include "msvdx_bridge.h"
@@ -61,7 +62,8 @@ SGXGetClientInfoBW(IMG_UINT32 ui32BridgeID,
61 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_GETCLIENTINFO); 62 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_GETCLIENTINFO);
62 63
63 psGetClientInfoOUT->eError = 64 psGetClientInfoOUT->eError =
64 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt, 65 PVRSRVLookupHandle(psPerProc->psHandleBase,
66 &hDevCookieInt,
65 psGetClientInfoIN->hDevCookie, 67 psGetClientInfoIN->hDevCookie,
66 PVRSRV_HANDLE_TYPE_DEV_NODE); 68 PVRSRV_HANDLE_TYPE_DEV_NODE);
67 if(psGetClientInfoOUT->eError != PVRSRV_OK) 69 if(psGetClientInfoOUT->eError != PVRSRV_OK)
@@ -87,7 +89,8 @@ SGXReleaseClientInfoBW(IMG_UINT32 ui32BridgeID,
87 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_RELEASECLIENTINFO); 89 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_RELEASECLIENTINFO);
88 90
89 psRetOUT->eError = 91 psRetOUT->eError =
90 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt, 92 PVRSRVLookupHandle(psPerProc->psHandleBase,
93 &hDevCookieInt,
91 psReleaseClientInfoIN->hDevCookie, 94 psReleaseClientInfoIN->hDevCookie,
92 PVRSRV_HANDLE_TYPE_DEV_NODE); 95 PVRSRV_HANDLE_TYPE_DEV_NODE);
93 if(psRetOUT->eError != PVRSRV_OK) 96 if(psRetOUT->eError != PVRSRV_OK)
@@ -99,8 +102,12 @@ SGXReleaseClientInfoBW(IMG_UINT32 ui32BridgeID,
99 102
100 PVR_ASSERT(psDevInfo->ui32ClientRefCount > 0); 103 PVR_ASSERT(psDevInfo->ui32ClientRefCount > 0);
101 104
102 psDevInfo->ui32ClientRefCount--; 105
103 106 if (psDevInfo->ui32ClientRefCount > 0)
107 {
108 psDevInfo->ui32ClientRefCount--;
109 }
110
104 psRetOUT->eError = PVRSRV_OK; 111 psRetOUT->eError = PVRSRV_OK;
105 112
106 return 0; 113 return 0;
@@ -114,11 +121,15 @@ SGXGetInternalDevInfoBW(IMG_UINT32 ui32BridgeID,
114 PVRSRV_PER_PROCESS_DATA *psPerProc) 121 PVRSRV_PER_PROCESS_DATA *psPerProc)
115{ 122{
116 IMG_HANDLE hDevCookieInt; 123 IMG_HANDLE hDevCookieInt;
124#if defined (SUPPORT_SID_INTERFACE)
125 SGX_INTERNAL_DEVINFO_KM sSGXInternalDevInfo;
126#endif
117 127
118 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_GETINTERNALDEVINFO); 128 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_GETINTERNALDEVINFO);
119 129
120 psSGXGetInternalDevInfoOUT->eError = 130 psSGXGetInternalDevInfoOUT->eError =
121 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt, 131 PVRSRVLookupHandle(psPerProc->psHandleBase,
132 &hDevCookieInt,
122 psSGXGetInternalDevInfoIN->hDevCookie, 133 psSGXGetInternalDevInfoIN->hDevCookie,
123 PVRSRV_HANDLE_TYPE_DEV_NODE); 134 PVRSRV_HANDLE_TYPE_DEV_NODE);
124 if(psSGXGetInternalDevInfoOUT->eError != PVRSRV_OK) 135 if(psSGXGetInternalDevInfoOUT->eError != PVRSRV_OK)
@@ -128,13 +139,21 @@ SGXGetInternalDevInfoBW(IMG_UINT32 ui32BridgeID,
128 139
129 psSGXGetInternalDevInfoOUT->eError = 140 psSGXGetInternalDevInfoOUT->eError =
130 SGXGetInternalDevInfoKM(hDevCookieInt, 141 SGXGetInternalDevInfoKM(hDevCookieInt,
142#if defined (SUPPORT_SID_INTERFACE)
143 &sSGXInternalDevInfo);
144#else
131 &psSGXGetInternalDevInfoOUT->sSGXInternalDevInfo); 145 &psSGXGetInternalDevInfoOUT->sSGXInternalDevInfo);
146#endif
132 147
133 148
134 psSGXGetInternalDevInfoOUT->eError = 149 psSGXGetInternalDevInfoOUT->eError =
135 PVRSRVAllocHandle(psPerProc->psHandleBase, 150 PVRSRVAllocHandle(psPerProc->psHandleBase,
136 &psSGXGetInternalDevInfoOUT->sSGXInternalDevInfo.hHostCtlKernelMemInfoHandle, 151 &psSGXGetInternalDevInfoOUT->sSGXInternalDevInfo.hHostCtlKernelMemInfoHandle,
152#if defined (SUPPORT_SID_INTERFACE)
153 sSGXInternalDevInfo.hHostCtlKernelMemInfoHandle,
154#else
137 psSGXGetInternalDevInfoOUT->sSGXInternalDevInfo.hHostCtlKernelMemInfoHandle, 155 psSGXGetInternalDevInfoOUT->sSGXInternalDevInfo.hHostCtlKernelMemInfoHandle,
156#endif
138 PVRSRV_HANDLE_TYPE_MEM_INFO, 157 PVRSRV_HANDLE_TYPE_MEM_INFO,
139 PVRSRV_HANDLE_ALLOC_FLAG_SHARED); 158 PVRSRV_HANDLE_ALLOC_FLAG_SHARED);
140 159
@@ -152,7 +171,12 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
152 IMG_UINT32 i; 171 IMG_UINT32 i;
153 IMG_INT ret = 0; 172 IMG_INT ret = 0;
154 IMG_UINT32 ui32NumDstSyncs; 173 IMG_UINT32 ui32NumDstSyncs;
174#if defined (SUPPORT_SID_INTERFACE)
175 SGX_CCB_KICK_KM sCCBKickKM = {{0}};
176 IMG_HANDLE ahSyncInfoHandles[16];
177#else
155 IMG_HANDLE *phKernelSyncInfoHandles = IMG_NULL; 178 IMG_HANDLE *phKernelSyncInfoHandles = IMG_NULL;
179#endif
156 180
157 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_DOKICK); 181 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_DOKICK);
158 182
@@ -169,7 +193,11 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
169 193
170 psRetOUT->eError = 194 psRetOUT->eError =
171 PVRSRVLookupHandle(psPerProc->psHandleBase, 195 PVRSRVLookupHandle(psPerProc->psHandleBase,
196#if defined (SUPPORT_SID_INTERFACE)
197 &sCCBKickKM.hCCBKernelMemInfo,
198#else
172 &psDoKickIN->sCCBKick.hCCBKernelMemInfo, 199 &psDoKickIN->sCCBKick.hCCBKernelMemInfo,
200#endif
173 psDoKickIN->sCCBKick.hCCBKernelMemInfo, 201 psDoKickIN->sCCBKick.hCCBKernelMemInfo,
174 PVRSRV_HANDLE_TYPE_MEM_INFO); 202 PVRSRV_HANDLE_TYPE_MEM_INFO);
175 203
@@ -178,11 +206,24 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
178 return 0; 206 return 0;
179 } 207 }
180 208
209#if defined (SUPPORT_SID_INTERFACE)
210 if (psDoKickIN->sCCBKick.ui32NumDstSyncObjects > 16)
211 {
212 return 0;
213 }
214
215 if(psDoKickIN->sCCBKick.hTA3DSyncInfo != 0)
216#else
181 if(psDoKickIN->sCCBKick.hTA3DSyncInfo != IMG_NULL) 217 if(psDoKickIN->sCCBKick.hTA3DSyncInfo != IMG_NULL)
218#endif
182 { 219 {
183 psRetOUT->eError = 220 psRetOUT->eError =
184 PVRSRVLookupHandle(psPerProc->psHandleBase, 221 PVRSRVLookupHandle(psPerProc->psHandleBase,
222#if defined (SUPPORT_SID_INTERFACE)
223 &sCCBKickKM.hTA3DSyncInfo,
224#else
185 &psDoKickIN->sCCBKick.hTA3DSyncInfo, 225 &psDoKickIN->sCCBKick.hTA3DSyncInfo,
226#endif
186 psDoKickIN->sCCBKick.hTA3DSyncInfo, 227 psDoKickIN->sCCBKick.hTA3DSyncInfo,
187 PVRSRV_HANDLE_TYPE_SYNC_INFO); 228 PVRSRV_HANDLE_TYPE_SYNC_INFO);
188 229
@@ -192,11 +233,19 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
192 } 233 }
193 } 234 }
194 235
236#if defined (SUPPORT_SID_INTERFACE)
237 if(psDoKickIN->sCCBKick.hTASyncInfo != 0)
238#else
195 if(psDoKickIN->sCCBKick.hTASyncInfo != IMG_NULL) 239 if(psDoKickIN->sCCBKick.hTASyncInfo != IMG_NULL)
240#endif
196 { 241 {
197 psRetOUT->eError = 242 psRetOUT->eError =
198 PVRSRVLookupHandle(psPerProc->psHandleBase, 243 PVRSRVLookupHandle(psPerProc->psHandleBase,
244#if defined (SUPPORT_SID_INTERFACE)
245 &sCCBKickKM.hTASyncInfo,
246#else
199 &psDoKickIN->sCCBKick.hTASyncInfo, 247 &psDoKickIN->sCCBKick.hTASyncInfo,
248#endif
200 psDoKickIN->sCCBKick.hTASyncInfo, 249 psDoKickIN->sCCBKick.hTASyncInfo,
201 PVRSRV_HANDLE_TYPE_SYNC_INFO); 250 PVRSRV_HANDLE_TYPE_SYNC_INFO);
202 251
@@ -206,11 +255,33 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
206 } 255 }
207 } 256 }
208 257
258#if defined(FIX_HW_BRN_31620)
259
260 psRetOUT->eError =
261 PVRSRVLookupHandle(psPerProc->psHandleBase,
262 &psDoKickIN->sCCBKick.hDevMemContext,
263 psDoKickIN->sCCBKick.hDevMemContext,
264 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT);
265
266 if(psRetOUT->eError != PVRSRV_OK)
267 {
268 return 0;
269 }
270#endif
271
272#if defined (SUPPORT_SID_INTERFACE)
273 if(psDoKickIN->sCCBKick.h3DSyncInfo != 0)
274#else
209 if(psDoKickIN->sCCBKick.h3DSyncInfo != IMG_NULL) 275 if(psDoKickIN->sCCBKick.h3DSyncInfo != IMG_NULL)
276#endif
210 { 277 {
211 psRetOUT->eError = 278 psRetOUT->eError =
212 PVRSRVLookupHandle(psPerProc->psHandleBase, 279 PVRSRVLookupHandle(psPerProc->psHandleBase,
280#if defined (SUPPORT_SID_INTERFACE)
281 &sCCBKickKM.h3DSyncInfo,
282#else
213 &psDoKickIN->sCCBKick.h3DSyncInfo, 283 &psDoKickIN->sCCBKick.h3DSyncInfo,
284#endif
214 psDoKickIN->sCCBKick.h3DSyncInfo, 285 psDoKickIN->sCCBKick.h3DSyncInfo,
215 PVRSRV_HANDLE_TYPE_SYNC_INFO); 286 PVRSRV_HANDLE_TYPE_SYNC_INFO);
216 287
@@ -229,11 +300,18 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
229 return 0; 300 return 0;
230 } 301 }
231 302
303#if defined (SUPPORT_SID_INTERFACE)
304 sCCBKickKM.ui32NumTASrcSyncs = psDoKickIN->sCCBKick.ui32NumTASrcSyncs;
305#endif
232 for(i=0; i<psDoKickIN->sCCBKick.ui32NumTASrcSyncs; i++) 306 for(i=0; i<psDoKickIN->sCCBKick.ui32NumTASrcSyncs; i++)
233 { 307 {
234 psRetOUT->eError = 308 psRetOUT->eError =
235 PVRSRVLookupHandle(psPerProc->psHandleBase, 309 PVRSRVLookupHandle(psPerProc->psHandleBase,
310#if defined (SUPPORT_SID_INTERFACE)
311 &sCCBKickKM.ahTASrcKernelSyncInfo[i],
312#else
236 &psDoKickIN->sCCBKick.ahTASrcKernelSyncInfo[i], 313 &psDoKickIN->sCCBKick.ahTASrcKernelSyncInfo[i],
314#endif
237 psDoKickIN->sCCBKick.ahTASrcKernelSyncInfo[i], 315 psDoKickIN->sCCBKick.ahTASrcKernelSyncInfo[i],
238 PVRSRV_HANDLE_TYPE_SYNC_INFO); 316 PVRSRV_HANDLE_TYPE_SYNC_INFO);
239 317
@@ -249,11 +327,18 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
249 return 0; 327 return 0;
250 } 328 }
251 329
330#if defined (SUPPORT_SID_INTERFACE)
331 sCCBKickKM.ui32NumTADstSyncs = psDoKickIN->sCCBKick.ui32NumTADstSyncs;
332#endif
252 for(i=0; i<psDoKickIN->sCCBKick.ui32NumTADstSyncs; i++) 333 for(i=0; i<psDoKickIN->sCCBKick.ui32NumTADstSyncs; i++)
253 { 334 {
254 psRetOUT->eError = 335 psRetOUT->eError =
255 PVRSRVLookupHandle(psPerProc->psHandleBase, 336 PVRSRVLookupHandle(psPerProc->psHandleBase,
337#if defined (SUPPORT_SID_INTERFACE)
338 &sCCBKickKM.ahTADstKernelSyncInfo[i],
339#else
256 &psDoKickIN->sCCBKick.ahTADstKernelSyncInfo[i], 340 &psDoKickIN->sCCBKick.ahTADstKernelSyncInfo[i],
341#endif
257 psDoKickIN->sCCBKick.ahTADstKernelSyncInfo[i], 342 psDoKickIN->sCCBKick.ahTADstKernelSyncInfo[i],
258 PVRSRV_HANDLE_TYPE_SYNC_INFO); 343 PVRSRV_HANDLE_TYPE_SYNC_INFO);
259 344
@@ -269,11 +354,18 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
269 return 0; 354 return 0;
270 } 355 }
271 356
357#if defined (SUPPORT_SID_INTERFACE)
358 sCCBKickKM.ui32Num3DSrcSyncs = psDoKickIN->sCCBKick.ui32Num3DSrcSyncs;
359#endif
272 for(i=0; i<psDoKickIN->sCCBKick.ui32Num3DSrcSyncs; i++) 360 for(i=0; i<psDoKickIN->sCCBKick.ui32Num3DSrcSyncs; i++)
273 { 361 {
274 psRetOUT->eError = 362 psRetOUT->eError =
275 PVRSRVLookupHandle(psPerProc->psHandleBase, 363 PVRSRVLookupHandle(psPerProc->psHandleBase,
364#if defined (SUPPORT_SID_INTERFACE)
365 &sCCBKickKM.ah3DSrcKernelSyncInfo[i],
366#else
276 &psDoKickIN->sCCBKick.ah3DSrcKernelSyncInfo[i], 367 &psDoKickIN->sCCBKick.ah3DSrcKernelSyncInfo[i],
368#endif
277 psDoKickIN->sCCBKick.ah3DSrcKernelSyncInfo[i], 369 psDoKickIN->sCCBKick.ah3DSrcKernelSyncInfo[i],
278 PVRSRV_HANDLE_TYPE_SYNC_INFO); 370 PVRSRV_HANDLE_TYPE_SYNC_INFO);
279 371
@@ -289,11 +381,19 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
289 psRetOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; 381 psRetOUT->eError = PVRSRV_ERROR_INVALID_PARAMS;
290 return 0; 382 return 0;
291 } 383 }
384
385#if defined (SUPPORT_SID_INTERFACE)
386 sCCBKickKM.ui32NumSrcSyncs = psDoKickIN->sCCBKick.ui32NumSrcSyncs;
387#endif
292 for(i=0; i<psDoKickIN->sCCBKick.ui32NumSrcSyncs; i++) 388 for(i=0; i<psDoKickIN->sCCBKick.ui32NumSrcSyncs; i++)
293 { 389 {
294 psRetOUT->eError = 390 psRetOUT->eError =
295 PVRSRVLookupHandle(psPerProc->psHandleBase, 391 PVRSRVLookupHandle(psPerProc->psHandleBase,
392#if defined (SUPPORT_SID_INTERFACE)
393 &sCCBKickKM.ahSrcKernelSyncInfo[i],
394#else
296 &psDoKickIN->sCCBKick.ahSrcKernelSyncInfo[i], 395 &psDoKickIN->sCCBKick.ahSrcKernelSyncInfo[i],
396#endif
297 psDoKickIN->sCCBKick.ahSrcKernelSyncInfo[i], 397 psDoKickIN->sCCBKick.ahSrcKernelSyncInfo[i],
298 PVRSRV_HANDLE_TYPE_SYNC_INFO); 398 PVRSRV_HANDLE_TYPE_SYNC_INFO);
299 399
@@ -314,12 +414,25 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
314 psRetOUT->eError = 414 psRetOUT->eError =
315#if defined(SUPPORT_SGX_NEW_STATUS_VALS) 415#if defined(SUPPORT_SGX_NEW_STATUS_VALS)
316 PVRSRVLookupHandle(psPerProc->psHandleBase, 416 PVRSRVLookupHandle(psPerProc->psHandleBase,
417#if defined (SUPPORT_SID_INTERFACE)
418 &sCCBKickKM.asTAStatusUpdate[i].hKernelMemInfo,
419#else
317 &psDoKickIN->sCCBKick.asTAStatusUpdate[i].hKernelMemInfo, 420 &psDoKickIN->sCCBKick.asTAStatusUpdate[i].hKernelMemInfo,
421#endif
318 psDoKickIN->sCCBKick.asTAStatusUpdate[i].hKernelMemInfo, 422 psDoKickIN->sCCBKick.asTAStatusUpdate[i].hKernelMemInfo,
319 PVRSRV_HANDLE_TYPE_MEM_INFO); 423 PVRSRV_HANDLE_TYPE_MEM_INFO);
424
425#if defined (SUPPORT_SID_INTERFACE)
426 sCCBKickKM.asTAStatusUpdate[i].sCtlStatus = psDoKickIN->sCCBKick.asTAStatusUpdate[i].sCtlStatus;
427#endif
428
320#else 429#else
321 PVRSRVLookupHandle(psPerProc->psHandleBase, 430 PVRSRVLookupHandle(psPerProc->psHandleBase,
431#if defined (SUPPORT_SID_INTERFACE)
432 &sCCBKickKM.ahTAStatusSyncInfo[i],
433#else
322 &psDoKickIN->sCCBKick.ahTAStatusSyncInfo[i], 434 &psDoKickIN->sCCBKick.ahTAStatusSyncInfo[i],
435#endif
323 psDoKickIN->sCCBKick.ahTAStatusSyncInfo[i], 436 psDoKickIN->sCCBKick.ahTAStatusSyncInfo[i],
324 PVRSRV_HANDLE_TYPE_SYNC_INFO); 437 PVRSRV_HANDLE_TYPE_SYNC_INFO);
325#endif 438#endif
@@ -339,12 +452,24 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
339 psRetOUT->eError = 452 psRetOUT->eError =
340#if defined(SUPPORT_SGX_NEW_STATUS_VALS) 453#if defined(SUPPORT_SGX_NEW_STATUS_VALS)
341 PVRSRVLookupHandle(psPerProc->psHandleBase, 454 PVRSRVLookupHandle(psPerProc->psHandleBase,
455#if defined (SUPPORT_SID_INTERFACE)
456 &sCCBKickKM.as3DStatusUpdate[i].hKernelMemInfo,
457#else
342 &psDoKickIN->sCCBKick.as3DStatusUpdate[i].hKernelMemInfo, 458 &psDoKickIN->sCCBKick.as3DStatusUpdate[i].hKernelMemInfo,
459#endif
343 psDoKickIN->sCCBKick.as3DStatusUpdate[i].hKernelMemInfo, 460 psDoKickIN->sCCBKick.as3DStatusUpdate[i].hKernelMemInfo,
344 PVRSRV_HANDLE_TYPE_MEM_INFO); 461 PVRSRV_HANDLE_TYPE_MEM_INFO);
462
463#if defined (SUPPORT_SID_INTERFACE)
464 sCCBKickKM.as3DStatusUpdate[i].sCtlStatus = psDoKickIN->sCCBKick.as3DStatusUpdate[i].sCtlStatus;
465#endif
345#else 466#else
346 PVRSRVLookupHandle(psPerProc->psHandleBase, 467 PVRSRVLookupHandle(psPerProc->psHandleBase,
468#if defined (SUPPORT_SID_INTERFACE)
469 &sCCBKickKM.ah3DStatusSyncInfo[i],
470#else
347 &psDoKickIN->sCCBKick.ah3DStatusSyncInfo[i], 471 &psDoKickIN->sCCBKick.ah3DStatusSyncInfo[i],
472#endif
348 psDoKickIN->sCCBKick.ah3DStatusSyncInfo[i], 473 psDoKickIN->sCCBKick.ah3DStatusSyncInfo[i],
349 PVRSRV_HANDLE_TYPE_SYNC_INFO); 474 PVRSRV_HANDLE_TYPE_SYNC_INFO);
350#endif 475#endif
@@ -378,6 +503,9 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
378 return 0; 503 return 0;
379 } 504 }
380 505
506#if defined (SUPPORT_SID_INTERFACE)
507 sCCBKickKM.pahDstSyncHandles = phKernelSyncInfoHandles;
508#else
381 if(CopyFromUserWrapper(psPerProc, 509 if(CopyFromUserWrapper(psPerProc,
382 ui32BridgeID, 510 ui32BridgeID,
383 phKernelSyncInfoHandles, 511 phKernelSyncInfoHandles,
@@ -390,12 +518,17 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
390 518
391 519
392 psDoKickIN->sCCBKick.pahDstSyncHandles = phKernelSyncInfoHandles; 520 psDoKickIN->sCCBKick.pahDstSyncHandles = phKernelSyncInfoHandles;
521#endif
393 522
394 for( i = 0; i < ui32NumDstSyncs; i++) 523 for( i = 0; i < ui32NumDstSyncs; i++)
395 { 524 {
396 psRetOUT->eError = 525 psRetOUT->eError =
397 PVRSRVLookupHandle(psPerProc->psHandleBase, 526 PVRSRVLookupHandle(psPerProc->psHandleBase,
527#if defined (SUPPORT_SID_INTERFACE)
528 &sCCBKickKM.pahDstSyncHandles[i],
529#else
398 &psDoKickIN->sCCBKick.pahDstSyncHandles[i], 530 &psDoKickIN->sCCBKick.pahDstSyncHandles[i],
531#endif
399 psDoKickIN->sCCBKick.pahDstSyncHandles[i], 532 psDoKickIN->sCCBKick.pahDstSyncHandles[i],
400 PVRSRV_HANDLE_TYPE_SYNC_INFO); 533 PVRSRV_HANDLE_TYPE_SYNC_INFO);
401 534
@@ -408,7 +541,11 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
408 541
409 psRetOUT->eError = 542 psRetOUT->eError =
410 PVRSRVLookupHandle(psPerProc->psHandleBase, 543 PVRSRVLookupHandle(psPerProc->psHandleBase,
544#if defined (SUPPORT_SID_INTERFACE)
545 &sCCBKickKM.hKernelHWSyncListMemInfo,
546#else
411 &psDoKickIN->sCCBKick.hKernelHWSyncListMemInfo, 547 &psDoKickIN->sCCBKick.hKernelHWSyncListMemInfo,
548#endif
412 psDoKickIN->sCCBKick.hKernelHWSyncListMemInfo, 549 psDoKickIN->sCCBKick.hKernelHWSyncListMemInfo,
413 PVRSRV_HANDLE_TYPE_MEM_INFO); 550 PVRSRV_HANDLE_TYPE_MEM_INFO);
414 551
@@ -418,9 +555,34 @@ SGXDoKickBW(IMG_UINT32 ui32BridgeID,
418 } 555 }
419 } 556 }
420 557
558#if defined (SUPPORT_SID_INTERFACE)
559 OSMemCopy(&sCCBKickKM.sCommand, &psDoKickIN->sCCBKick.sCommand, sizeof(sCCBKickKM.sCommand));
560
561 sCCBKickKM.ui32NumDstSyncObjects = psDoKickIN->sCCBKick.ui32NumDstSyncObjects;
562 sCCBKickKM.ui32NumTAStatusVals = psDoKickIN->sCCBKick.ui32NumTAStatusVals;
563 sCCBKickKM.ui32Num3DStatusVals = psDoKickIN->sCCBKick.ui32Num3DStatusVals;
564 sCCBKickKM.bFirstKickOrResume = psDoKickIN->sCCBKick.bFirstKickOrResume;
565 sCCBKickKM.ui32CCBOffset = psDoKickIN->sCCBKick.ui32CCBOffset;
566 sCCBKickKM.bTADependency = psDoKickIN->sCCBKick.bTADependency;
567
568#if (defined(NO_HARDWARE) || defined(PDUMP))
569 sCCBKickKM.bTerminateOrAbort = psDoKickIN->sCCBKick.bTerminateOrAbort;
570#endif
571#if defined(PDUMP)
572 sCCBKickKM.ui32CCBDumpWOff = psDoKickIN->sCCBKick.ui32CCBDumpWOff;
573#endif
574
575#if defined(NO_HARDWARE)
576 sCCBKickKM.ui32WriteOpsPendingVal = psDoKickIN->sCCBKick.ui32WriteOpsPendingVal;
577#endif
578#endif
421 psRetOUT->eError = 579 psRetOUT->eError =
422 SGXDoKickKM(hDevCookieInt, 580 SGXDoKickKM(hDevCookieInt,
581#if defined (SUPPORT_SID_INTERFACE)
582 &sCCBKickKM);
583#else
423 &psDoKickIN->sCCBKick); 584 &psDoKickIN->sCCBKick);
585#endif
424 586
425PVRSRV_BRIDGE_SGX_DOKICK_RETURN_RESULT: 587PVRSRV_BRIDGE_SGX_DOKICK_RETURN_RESULT:
426 588
@@ -472,6 +634,9 @@ SGXSubmitTransferBW(IMG_UINT32 ui32BridgeID,
472{ 634{
473 IMG_HANDLE hDevCookieInt; 635 IMG_HANDLE hDevCookieInt;
474 PVRSRV_TRANSFER_SGX_KICK *psKick; 636 PVRSRV_TRANSFER_SGX_KICK *psKick;
637#if defined (SUPPORT_SID_INTERFACE)
638 PVRSRV_TRANSFER_SGX_KICK_KM sKickKM = {0};
639#endif
475 IMG_UINT32 i; 640 IMG_UINT32 i;
476 641
477 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_SUBMITTRANSFER); 642 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_SUBMITTRANSFER);
@@ -479,6 +644,20 @@ SGXSubmitTransferBW(IMG_UINT32 ui32BridgeID,
479 644
480 psKick = &psSubmitTransferIN->sKick; 645 psKick = &psSubmitTransferIN->sKick;
481 646
647#if defined(FIX_HW_BRN_31620)
648
649 psRetOUT->eError =
650 PVRSRVLookupHandle(psPerProc->psHandleBase,
651 &psKick->hDevMemContext,
652 psKick->hDevMemContext,
653 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT);
654
655 if(psRetOUT->eError != PVRSRV_OK)
656 {
657 return 0;
658 }
659#endif
660
482 psRetOUT->eError = 661 psRetOUT->eError =
483 PVRSRVLookupHandle(psPerProc->psHandleBase, 662 PVRSRVLookupHandle(psPerProc->psHandleBase,
484 &hDevCookieInt, 663 &hDevCookieInt,
@@ -491,7 +670,11 @@ SGXSubmitTransferBW(IMG_UINT32 ui32BridgeID,
491 670
492 psRetOUT->eError = 671 psRetOUT->eError =
493 PVRSRVLookupHandle(psPerProc->psHandleBase, 672 PVRSRVLookupHandle(psPerProc->psHandleBase,
673#if defined (SUPPORT_SID_INTERFACE)
674 &sKickKM.hCCBMemInfo,
675#else
494 &psKick->hCCBMemInfo, 676 &psKick->hCCBMemInfo,
677#endif
495 psKick->hCCBMemInfo, 678 psKick->hCCBMemInfo,
496 PVRSRV_HANDLE_TYPE_MEM_INFO); 679 PVRSRV_HANDLE_TYPE_MEM_INFO);
497 if(psRetOUT->eError != PVRSRV_OK) 680 if(psRetOUT->eError != PVRSRV_OK)
@@ -503,7 +686,11 @@ SGXSubmitTransferBW(IMG_UINT32 ui32BridgeID,
503 { 686 {
504 psRetOUT->eError = 687 psRetOUT->eError =
505 PVRSRVLookupHandle(psPerProc->psHandleBase, 688 PVRSRVLookupHandle(psPerProc->psHandleBase,
689#if defined (SUPPORT_SID_INTERFACE)
690 &sKickKM.hTASyncInfo,
691#else
506 &psKick->hTASyncInfo, 692 &psKick->hTASyncInfo,
693#endif
507 psKick->hTASyncInfo, 694 psKick->hTASyncInfo,
508 PVRSRV_HANDLE_TYPE_SYNC_INFO); 695 PVRSRV_HANDLE_TYPE_SYNC_INFO);
509 if(psRetOUT->eError != PVRSRV_OK) 696 if(psRetOUT->eError != PVRSRV_OK)
@@ -516,7 +703,11 @@ SGXSubmitTransferBW(IMG_UINT32 ui32BridgeID,
516 { 703 {
517 psRetOUT->eError = 704 psRetOUT->eError =
518 PVRSRVLookupHandle(psPerProc->psHandleBase, 705 PVRSRVLookupHandle(psPerProc->psHandleBase,
706#if defined (SUPPORT_SID_INTERFACE)
707 &sKickKM.h3DSyncInfo,
708#else
519 &psKick->h3DSyncInfo, 709 &psKick->h3DSyncInfo,
710#endif
520 psKick->h3DSyncInfo, 711 psKick->h3DSyncInfo,
521 PVRSRV_HANDLE_TYPE_SYNC_INFO); 712 PVRSRV_HANDLE_TYPE_SYNC_INFO);
522 if(psRetOUT->eError != PVRSRV_OK) 713 if(psRetOUT->eError != PVRSRV_OK)
@@ -534,7 +725,11 @@ SGXSubmitTransferBW(IMG_UINT32 ui32BridgeID,
534 { 725 {
535 psRetOUT->eError = 726 psRetOUT->eError =
536 PVRSRVLookupHandle(psPerProc->psHandleBase, 727 PVRSRVLookupHandle(psPerProc->psHandleBase,
728#if defined (SUPPORT_SID_INTERFACE)
729 &sKickKM.ahSrcSyncInfo[i],
730#else
537 &psKick->ahSrcSyncInfo[i], 731 &psKick->ahSrcSyncInfo[i],
732#endif
538 psKick->ahSrcSyncInfo[i], 733 psKick->ahSrcSyncInfo[i],
539 PVRSRV_HANDLE_TYPE_SYNC_INFO); 734 PVRSRV_HANDLE_TYPE_SYNC_INFO);
540 if(psRetOUT->eError != PVRSRV_OK) 735 if(psRetOUT->eError != PVRSRV_OK)
@@ -552,7 +747,11 @@ SGXSubmitTransferBW(IMG_UINT32 ui32BridgeID,
552 { 747 {
553 psRetOUT->eError = 748 psRetOUT->eError =
554 PVRSRVLookupHandle(psPerProc->psHandleBase, 749 PVRSRVLookupHandle(psPerProc->psHandleBase,
750#if defined (SUPPORT_SID_INTERFACE)
751 &sKickKM.ahDstSyncInfo[i],
752#else
555 &psKick->ahDstSyncInfo[i], 753 &psKick->ahDstSyncInfo[i],
754#endif
556 psKick->ahDstSyncInfo[i], 755 psKick->ahDstSyncInfo[i],
557 PVRSRV_HANDLE_TYPE_SYNC_INFO); 756 PVRSRV_HANDLE_TYPE_SYNC_INFO);
558 if(psRetOUT->eError != PVRSRV_OK) 757 if(psRetOUT->eError != PVRSRV_OK)
@@ -561,7 +760,21 @@ SGXSubmitTransferBW(IMG_UINT32 ui32BridgeID,
561 } 760 }
562 } 761 }
563 762
763#if defined (SUPPORT_SID_INTERFACE)
764 sKickKM.sHWTransferContextDevVAddr = psKick->sHWTransferContextDevVAddr;
765 sKickKM.ui32SharedCmdCCBOffset = psKick->ui32SharedCmdCCBOffset;
766 sKickKM.ui32NumSrcSync = psKick->ui32NumSrcSync;
767 sKickKM.ui32NumDstSync = psKick->ui32NumDstSync;
768 sKickKM.ui32Flags = psKick->ui32Flags;
769 sKickKM.ui32PDumpFlags = psKick->ui32PDumpFlags;
770#if defined(PDUMP)
771 sKickKM.ui32CCBDumpWOff = psKick->ui32CCBDumpWOff;
772#endif
773
774 psRetOUT->eError = SGXSubmitTransferKM(hDevCookieInt, &sKickKM);
775#else
564 psRetOUT->eError = SGXSubmitTransferKM(hDevCookieInt, psKick); 776 psRetOUT->eError = SGXSubmitTransferKM(hDevCookieInt, psKick);
777#endif
565 778
566 return 0; 779 return 0;
567} 780}
@@ -575,12 +788,32 @@ SGXSubmit2DBW(IMG_UINT32 ui32BridgeID,
575 PVRSRV_PER_PROCESS_DATA *psPerProc) 788 PVRSRV_PER_PROCESS_DATA *psPerProc)
576{ 789{
577 IMG_HANDLE hDevCookieInt; 790 IMG_HANDLE hDevCookieInt;
578 PVRSRV_2D_SGX_KICK *psKick; 791 PVRSRV_2D_SGX_KICK *psKick;
792#if defined (SUPPORT_SID_INTERFACE)
793 PVRSRV_2D_SGX_KICK_KM sKickKM;
794#endif
579 IMG_UINT32 i; 795 IMG_UINT32 i;
580 796
581 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_SUBMIT2D); 797 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_SUBMIT2D);
582 PVR_UNREFERENCED_PARAMETER(ui32BridgeID); 798 PVR_UNREFERENCED_PARAMETER(ui32BridgeID);
583 799
800 psKick = &psSubmit2DIN->sKick;
801
802#if defined(FIX_HW_BRN_31620)
803
804 psRetOUT->eError =
805 PVRSRVLookupHandle(psPerProc->psHandleBase,
806 &psKick->hDevMemContext,
807 psKick->hDevMemContext,
808 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT);
809
810 if(psRetOUT->eError != PVRSRV_OK)
811 {
812 return 0;
813 }
814#endif
815
816
584 psRetOUT->eError = 817 psRetOUT->eError =
585 PVRSRVLookupHandle(psPerProc->psHandleBase, 818 PVRSRVLookupHandle(psPerProc->psHandleBase,
586 &hDevCookieInt, 819 &hDevCookieInt,
@@ -592,11 +825,14 @@ SGXSubmit2DBW(IMG_UINT32 ui32BridgeID,
592 return 0; 825 return 0;
593 } 826 }
594 827
595 psKick = &psSubmit2DIN->sKick;
596 828
597 psRetOUT->eError = 829 psRetOUT->eError =
598 PVRSRVLookupHandle(psPerProc->psHandleBase, 830 PVRSRVLookupHandle(psPerProc->psHandleBase,
831#if defined (SUPPORT_SID_INTERFACE)
832 &sKickKM.hCCBMemInfo,
833#else
599 &psKick->hCCBMemInfo, 834 &psKick->hCCBMemInfo,
835#endif
600 psKick->hCCBMemInfo, 836 psKick->hCCBMemInfo,
601 PVRSRV_HANDLE_TYPE_MEM_INFO); 837 PVRSRV_HANDLE_TYPE_MEM_INFO);
602 if(psRetOUT->eError != PVRSRV_OK) 838 if(psRetOUT->eError != PVRSRV_OK)
@@ -604,11 +840,19 @@ SGXSubmit2DBW(IMG_UINT32 ui32BridgeID,
604 return 0; 840 return 0;
605 } 841 }
606 842
843#if defined (SUPPORT_SID_INTERFACE)
844 if (psKick->hTASyncInfo != 0)
845#else
607 if (psKick->hTASyncInfo != IMG_NULL) 846 if (psKick->hTASyncInfo != IMG_NULL)
847#endif
608 { 848 {
609 psRetOUT->eError = 849 psRetOUT->eError =
610 PVRSRVLookupHandle(psPerProc->psHandleBase, 850 PVRSRVLookupHandle(psPerProc->psHandleBase,
851#if defined (SUPPORT_SID_INTERFACE)
852 &sKickKM.hTASyncInfo,
853#else
611 &psKick->hTASyncInfo, 854 &psKick->hTASyncInfo,
855#endif
612 psKick->hTASyncInfo, 856 psKick->hTASyncInfo,
613 PVRSRV_HANDLE_TYPE_SYNC_INFO); 857 PVRSRV_HANDLE_TYPE_SYNC_INFO);
614 if(psRetOUT->eError != PVRSRV_OK) 858 if(psRetOUT->eError != PVRSRV_OK)
@@ -616,12 +860,22 @@ SGXSubmit2DBW(IMG_UINT32 ui32BridgeID,
616 return 0; 860 return 0;
617 } 861 }
618 } 862 }
863#if defined (SUPPORT_SID_INTERFACE)
864 else
865 {
866 sKickKM.hTASyncInfo = IMG_NULL;
867 }
868#endif
619 869
620 if (psKick->h3DSyncInfo != IMG_NULL) 870 if (psKick->h3DSyncInfo != IMG_NULL)
621 { 871 {
622 psRetOUT->eError = 872 psRetOUT->eError =
623 PVRSRVLookupHandle(psPerProc->psHandleBase, 873 PVRSRVLookupHandle(psPerProc->psHandleBase,
874#if defined (SUPPORT_SID_INTERFACE)
875 &sKickKM.h3DSyncInfo,
876#else
624 &psKick->h3DSyncInfo, 877 &psKick->h3DSyncInfo,
878#endif
625 psKick->h3DSyncInfo, 879 psKick->h3DSyncInfo,
626 PVRSRV_HANDLE_TYPE_SYNC_INFO); 880 PVRSRV_HANDLE_TYPE_SYNC_INFO);
627 if(psRetOUT->eError != PVRSRV_OK) 881 if(psRetOUT->eError != PVRSRV_OK)
@@ -629,12 +883,39 @@ SGXSubmit2DBW(IMG_UINT32 ui32BridgeID,
629 return 0; 883 return 0;
630 } 884 }
631 } 885 }
886#if defined (SUPPORT_SID_INTERFACE)
887 else
888 {
889 sKickKM.h3DSyncInfo = IMG_NULL;
890 }
891#endif
632 892
633 if (psKick->ui32NumSrcSync > SGX_MAX_2D_SRC_SYNC_OPS) 893 if (psKick->ui32NumSrcSync > SGX_MAX_2D_SRC_SYNC_OPS)
634 { 894 {
635 psRetOUT->eError = PVRSRV_ERROR_INVALID_PARAMS; 895 psRetOUT->eError = PVRSRV_ERROR_INVALID_PARAMS;
636 return 0; 896 return 0;
637 } 897 }
898#if defined (SUPPORT_SID_INTERFACE)
899 for (i = 0; i < SGX_MAX_2D_SRC_SYNC_OPS; i++)
900 {
901 if (i < psKick->ui32NumSrcSync)
902 {
903 psRetOUT->eError =
904 PVRSRVLookupHandle(psPerProc->psHandleBase,
905 &sKickKM.ahSrcSyncInfo[i],
906 psKick->ahSrcSyncInfo[i],
907 PVRSRV_HANDLE_TYPE_SYNC_INFO);
908 if(psRetOUT->eError != PVRSRV_OK)
909 {
910 return 0;
911 }
912 }
913 else
914 {
915 sKickKM.ahSrcSyncInfo[i] = IMG_NULL;
916 }
917 }
918#else
638 for (i = 0; i < psKick->ui32NumSrcSync; i++) 919 for (i = 0; i < psKick->ui32NumSrcSync; i++)
639 { 920 {
640 psRetOUT->eError = 921 psRetOUT->eError =
@@ -647,12 +928,17 @@ SGXSubmit2DBW(IMG_UINT32 ui32BridgeID,
647 return 0; 928 return 0;
648 } 929 }
649 } 930 }
931#endif
650 932
651 if (psKick->hDstSyncInfo != IMG_NULL) 933 if (psKick->hDstSyncInfo != IMG_NULL)
652 { 934 {
653 psRetOUT->eError = 935 psRetOUT->eError =
654 PVRSRVLookupHandle(psPerProc->psHandleBase, 936 PVRSRVLookupHandle(psPerProc->psHandleBase,
937#if defined (SUPPORT_SID_INTERFACE)
938 &sKickKM.hDstSyncInfo,
939#else
655 &psKick->hDstSyncInfo, 940 &psKick->hDstSyncInfo,
941#endif
656 psKick->hDstSyncInfo, 942 psKick->hDstSyncInfo,
657 PVRSRV_HANDLE_TYPE_SYNC_INFO); 943 PVRSRV_HANDLE_TYPE_SYNC_INFO);
658 if(psRetOUT->eError != PVRSRV_OK) 944 if(psRetOUT->eError != PVRSRV_OK)
@@ -660,9 +946,28 @@ SGXSubmit2DBW(IMG_UINT32 ui32BridgeID,
660 return 0; 946 return 0;
661 } 947 }
662 } 948 }
949#if defined (SUPPORT_SID_INTERFACE)
950 else
951 {
952 sKickKM.hDstSyncInfo = IMG_NULL;
953 }
954
955
956 sKickKM.ui32SharedCmdCCBOffset = psKick->ui32SharedCmdCCBOffset;
957 sKickKM.ui32NumSrcSync = psKick->ui32NumSrcSync;
958 sKickKM.ui32PDumpFlags = psKick->ui32PDumpFlags;
959 sKickKM.sHW2DContextDevVAddr = psKick->sHW2DContextDevVAddr;
960#if defined(PDUMP)
961 sKickKM.ui32CCBDumpWOff = psKick->ui32CCBDumpWOff;
962#endif
963#endif
663 964
664 psRetOUT->eError = 965 psRetOUT->eError =
966#if defined (SUPPORT_SID_INTERFACE)
967 SGXSubmit2DKM(hDevCookieInt, &sKickKM);
968#else
665 SGXSubmit2DKM(hDevCookieInt, psKick); 969 SGXSubmit2DKM(hDevCookieInt, psKick);
970#endif
666 971
667 return 0; 972 return 0;
668} 973}
@@ -767,7 +1072,7 @@ SGXReadHWPerfCBBW(IMG_UINT32 ui32BridgeID,
767 1072
768 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_READ_HWPERF_CB); 1073 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_READ_HWPERF_CB);
769 1074
770 psSGXReadHWPerfCBOUT->eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 1075 psSGXReadHWPerfCBOUT->eError =PVRSRVLookupHandle(psPerProc->psHandleBase,
771 &hDevCookieInt, 1076 &hDevCookieInt,
772 psSGXReadHWPerfCBIN->hDevCookie, 1077 psSGXReadHWPerfCBIN->hDevCookie,
773 PVRSRV_HANDLE_TYPE_DEV_NODE); 1078 PVRSRV_HANDLE_TYPE_DEV_NODE);
@@ -814,31 +1119,41 @@ SGXReadHWPerfCBBW(IMG_UINT32 ui32BridgeID,
814static IMG_INT 1119static IMG_INT
815SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID, 1120SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
816 PVRSRV_BRIDGE_IN_SGXDEVINITPART2 *psSGXDevInitPart2IN, 1121 PVRSRV_BRIDGE_IN_SGXDEVINITPART2 *psSGXDevInitPart2IN,
817 PVRSRV_BRIDGE_RETURN *psRetOUT, 1122 PVRSRV_BRIDGE_OUT_SGXDEVINITPART2 *psSGXDevInitPart2OUT,
818 PVRSRV_PER_PROCESS_DATA *psPerProc) 1123 PVRSRV_PER_PROCESS_DATA *psPerProc)
819{ 1124{
820 IMG_HANDLE hDevCookieInt; 1125 IMG_HANDLE hDevCookieInt;
1126#if defined (SUPPORT_SID_INTERFACE)
1127 PVRSRV_ERROR eError = PVRSRV_OK;
1128#else
821 PVRSRV_ERROR eError; 1129 PVRSRV_ERROR eError;
1130#endif
822 IMG_BOOL bDissociateFailed = IMG_FALSE; 1131 IMG_BOOL bDissociateFailed = IMG_FALSE;
823 IMG_BOOL bLookupFailed = IMG_FALSE; 1132 IMG_BOOL bLookupFailed = IMG_FALSE;
824 IMG_BOOL bReleaseFailed = IMG_FALSE; 1133 IMG_BOOL bReleaseFailed = IMG_FALSE;
825 IMG_HANDLE hDummy; 1134 IMG_HANDLE hDummy;
826 IMG_UINT32 i; 1135 IMG_UINT32 i;
1136#if defined (SUPPORT_SID_INTERFACE)
1137 SGX_BRIDGE_INIT_INFO_KM asInitInfoKM = {0};
1138#endif
827 1139
828 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_DEVINITPART2); 1140 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_DEVINITPART2);
829 1141
1142
1143 psSGXDevInitPart2OUT->ui32KMBuildOptions = SGX_BUILD_OPTIONS;
1144
830 if(!psPerProc->bInitProcess) 1145 if(!psPerProc->bInitProcess)
831 { 1146 {
832 psRetOUT->eError = PVRSRV_ERROR_PROCESS_NOT_INITIALISED; 1147 psSGXDevInitPart2OUT->eError = PVRSRV_ERROR_PROCESS_NOT_INITIALISED;
833 return 0; 1148 return 0;
834 } 1149 }
835 1150
836 psRetOUT->eError = 1151 psSGXDevInitPart2OUT->eError =
837 PVRSRVLookupHandle(psPerProc->psHandleBase, 1152 PVRSRVLookupHandle(psPerProc->psHandleBase,
838 &hDevCookieInt, 1153 &hDevCookieInt,
839 psSGXDevInitPart2IN->hDevCookie, 1154 psSGXDevInitPart2IN->hDevCookie,
840 PVRSRV_HANDLE_TYPE_DEV_NODE); 1155 PVRSRV_HANDLE_TYPE_DEV_NODE);
841 if(psRetOUT->eError != PVRSRV_OK) 1156 if(psSGXDevInitPart2OUT->eError != PVRSRV_OK)
842 { 1157 {
843 return 0; 1158 return 0;
844 } 1159 }
@@ -961,6 +1276,95 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
961 } 1276 }
962#endif 1277#endif
963 1278
1279
1280#if defined(FIX_HW_BRN_31542)
1281 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
1282 &hDummy,
1283 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAVDMStreamMemInfo,
1284 PVRSRV_HANDLE_TYPE_MEM_INFO);
1285 if (eError != PVRSRV_OK)
1286 {
1287 bLookupFailed = IMG_TRUE;
1288 }
1289 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
1290 &hDummy,
1291 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAIndexStreamMemInfo,
1292 PVRSRV_HANDLE_TYPE_MEM_INFO);
1293 if (eError != PVRSRV_OK)
1294 {
1295 bLookupFailed = IMG_TRUE;
1296 }
1297 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
1298 &hDummy,
1299 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAPDSMemInfo,
1300 PVRSRV_HANDLE_TYPE_MEM_INFO);
1301 if (eError != PVRSRV_OK)
1302 {
1303 bLookupFailed = IMG_TRUE;
1304 }
1305 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
1306 &hDummy,
1307 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAUSEMemInfo,
1308 PVRSRV_HANDLE_TYPE_MEM_INFO);
1309 if (eError != PVRSRV_OK)
1310 {
1311 bLookupFailed = IMG_TRUE;
1312 }
1313 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
1314 &hDummy,
1315 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAParamMemInfo,
1316 PVRSRV_HANDLE_TYPE_MEM_INFO);
1317 if (eError != PVRSRV_OK)
1318 {
1319 bLookupFailed = IMG_TRUE;
1320 }
1321 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
1322 &hDummy,
1323 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAPMPTMemInfo,
1324 PVRSRV_HANDLE_TYPE_MEM_INFO);
1325 if (eError != PVRSRV_OK)
1326 {
1327 bLookupFailed = IMG_TRUE;
1328 }
1329
1330 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
1331 &hDummy,
1332 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWATPCMemInfo,
1333 PVRSRV_HANDLE_TYPE_MEM_INFO);
1334 if (eError != PVRSRV_OK)
1335 {
1336 bLookupFailed = IMG_TRUE;
1337 }
1338 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
1339 &hDummy,
1340 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAPSGRgnHdrMemInfo,
1341 PVRSRV_HANDLE_TYPE_MEM_INFO);
1342 if (eError != PVRSRV_OK)
1343 {
1344 bLookupFailed = IMG_TRUE;
1345 }
1346#endif
1347
1348#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && defined(FIX_HW_BRN_31425)
1349 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
1350 &hDummy,
1351 psSGXDevInitPart2IN->sInitInfo.hKernelVDMSnapShotBufferMemInfo,
1352 PVRSRV_HANDLE_TYPE_MEM_INFO);
1353 if (eError != PVRSRV_OK)
1354 {
1355 bLookupFailed = IMG_TRUE;
1356 }
1357
1358 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
1359 &hDummy,
1360 psSGXDevInitPart2IN->sInitInfo.hKernelVDMCtrlStreamBufferMemInfo,
1361 PVRSRV_HANDLE_TYPE_MEM_INFO);
1362 if (eError != PVRSRV_OK)
1363 {
1364 bLookupFailed = IMG_TRUE;
1365 }
1366#endif
1367
964#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG) 1368#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
965 eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 1369 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
966 &hDummy, 1370 &hDummy,
@@ -985,9 +1389,17 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
985 1389
986 for (i = 0; i < SGX_MAX_INIT_MEM_HANDLES; i++) 1390 for (i = 0; i < SGX_MAX_INIT_MEM_HANDLES; i++)
987 { 1391 {
1392#if defined (SUPPORT_SID_INTERFACE)
1393 IMG_SID hHandle = psSGXDevInitPart2IN->sInitInfo.asInitMemHandles[i];
1394#else
988 IMG_HANDLE hHandle = psSGXDevInitPart2IN->sInitInfo.asInitMemHandles[i]; 1395 IMG_HANDLE hHandle = psSGXDevInitPart2IN->sInitInfo.asInitMemHandles[i];
1396#endif
989 1397
1398#if defined (SUPPORT_SID_INTERFACE)
1399 if (hHandle == 0)
1400#else
990 if (hHandle == IMG_NULL) 1401 if (hHandle == IMG_NULL)
1402#endif
991 { 1403 {
992 continue; 1404 continue;
993 } 1405 }
@@ -1005,13 +1417,17 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1005 if (bLookupFailed) 1417 if (bLookupFailed)
1006 { 1418 {
1007 PVR_DPF((PVR_DBG_ERROR, "DevInitSGXPart2BW: A handle lookup failed")); 1419 PVR_DPF((PVR_DBG_ERROR, "DevInitSGXPart2BW: A handle lookup failed"));
1008 psRetOUT->eError = PVRSRV_ERROR_INIT2_PHASE_FAILED; 1420 psSGXDevInitPart2OUT->eError = PVRSRV_ERROR_INIT2_PHASE_FAILED;
1009 return 0; 1421 return 0;
1010 } 1422 }
1011 1423
1012 1424
1013 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase, 1425 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1426#if defined (SUPPORT_SID_INTERFACE)
1427 &asInitInfoKM.hKernelCCBMemInfo,
1428#else
1014 &psSGXDevInitPart2IN->sInitInfo.hKernelCCBMemInfo, 1429 &psSGXDevInitPart2IN->sInitInfo.hKernelCCBMemInfo,
1430#endif
1015 psSGXDevInitPart2IN->sInitInfo.hKernelCCBMemInfo, 1431 psSGXDevInitPart2IN->sInitInfo.hKernelCCBMemInfo,
1016 PVRSRV_HANDLE_TYPE_MEM_INFO); 1432 PVRSRV_HANDLE_TYPE_MEM_INFO);
1017 if (eError != PVRSRV_OK) 1433 if (eError != PVRSRV_OK)
@@ -1020,7 +1436,11 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1020 } 1436 }
1021 1437
1022 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase, 1438 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1439#if defined (SUPPORT_SID_INTERFACE)
1440 &asInitInfoKM.hKernelCCBCtlMemInfo,
1441#else
1023 &psSGXDevInitPart2IN->sInitInfo.hKernelCCBCtlMemInfo, 1442 &psSGXDevInitPart2IN->sInitInfo.hKernelCCBCtlMemInfo,
1443#endif
1024 psSGXDevInitPart2IN->sInitInfo.hKernelCCBCtlMemInfo, 1444 psSGXDevInitPart2IN->sInitInfo.hKernelCCBCtlMemInfo,
1025 PVRSRV_HANDLE_TYPE_MEM_INFO); 1445 PVRSRV_HANDLE_TYPE_MEM_INFO);
1026 if (eError != PVRSRV_OK) 1446 if (eError != PVRSRV_OK)
@@ -1029,7 +1449,11 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1029 } 1449 }
1030 1450
1031 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase, 1451 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1452#if defined (SUPPORT_SID_INTERFACE)
1453 &asInitInfoKM.hKernelCCBEventKickerMemInfo,
1454#else
1032 &psSGXDevInitPart2IN->sInitInfo.hKernelCCBEventKickerMemInfo, 1455 &psSGXDevInitPart2IN->sInitInfo.hKernelCCBEventKickerMemInfo,
1456#endif
1033 psSGXDevInitPart2IN->sInitInfo.hKernelCCBEventKickerMemInfo, 1457 psSGXDevInitPart2IN->sInitInfo.hKernelCCBEventKickerMemInfo,
1034 PVRSRV_HANDLE_TYPE_MEM_INFO); 1458 PVRSRV_HANDLE_TYPE_MEM_INFO);
1035 if (eError != PVRSRV_OK) 1459 if (eError != PVRSRV_OK)
@@ -1039,7 +1463,11 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1039 1463
1040 1464
1041 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase, 1465 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1466#if defined (SUPPORT_SID_INTERFACE)
1467 &asInitInfoKM.hKernelSGXHostCtlMemInfo,
1468#else
1042 &psSGXDevInitPart2IN->sInitInfo.hKernelSGXHostCtlMemInfo, 1469 &psSGXDevInitPart2IN->sInitInfo.hKernelSGXHostCtlMemInfo,
1470#endif
1043 psSGXDevInitPart2IN->sInitInfo.hKernelSGXHostCtlMemInfo, 1471 psSGXDevInitPart2IN->sInitInfo.hKernelSGXHostCtlMemInfo,
1044 PVRSRV_HANDLE_TYPE_MEM_INFO); 1472 PVRSRV_HANDLE_TYPE_MEM_INFO);
1045 if (eError != PVRSRV_OK) 1473 if (eError != PVRSRV_OK)
@@ -1048,7 +1476,11 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1048 } 1476 }
1049 1477
1050 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase, 1478 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1479#if defined (SUPPORT_SID_INTERFACE)
1480 &asInitInfoKM.hKernelSGXTA3DCtlMemInfo,
1481#else
1051 &psSGXDevInitPart2IN->sInitInfo.hKernelSGXTA3DCtlMemInfo, 1482 &psSGXDevInitPart2IN->sInitInfo.hKernelSGXTA3DCtlMemInfo,
1483#endif
1052 psSGXDevInitPart2IN->sInitInfo.hKernelSGXTA3DCtlMemInfo, 1484 psSGXDevInitPart2IN->sInitInfo.hKernelSGXTA3DCtlMemInfo,
1053 PVRSRV_HANDLE_TYPE_MEM_INFO); 1485 PVRSRV_HANDLE_TYPE_MEM_INFO);
1054 if (eError != PVRSRV_OK) 1486 if (eError != PVRSRV_OK)
@@ -1057,7 +1489,11 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1057 } 1489 }
1058 1490
1059 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase, 1491 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1492#if defined (SUPPORT_SID_INTERFACE)
1493 &asInitInfoKM.hKernelSGXMiscMemInfo,
1494#else
1060 &psSGXDevInitPart2IN->sInitInfo.hKernelSGXMiscMemInfo, 1495 &psSGXDevInitPart2IN->sInitInfo.hKernelSGXMiscMemInfo,
1496#endif
1061 psSGXDevInitPart2IN->sInitInfo.hKernelSGXMiscMemInfo, 1497 psSGXDevInitPart2IN->sInitInfo.hKernelSGXMiscMemInfo,
1062 PVRSRV_HANDLE_TYPE_MEM_INFO); 1498 PVRSRV_HANDLE_TYPE_MEM_INFO);
1063 if (eError != PVRSRV_OK) 1499 if (eError != PVRSRV_OK)
@@ -1066,9 +1502,13 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1066 } 1502 }
1067 1503
1068 1504
1069 #if defined(SGX_SUPPORT_HWPROFILING) 1505#if defined(SGX_SUPPORT_HWPROFILING)
1070 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase, 1506 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1507#if defined (SUPPORT_SID_INTERFACE)
1508 &asInitInfoKM.hKernelHWProfilingMemInfo,
1509#else
1071 &psSGXDevInitPart2IN->sInitInfo.hKernelHWProfilingMemInfo, 1510 &psSGXDevInitPart2IN->sInitInfo.hKernelHWProfilingMemInfo,
1511#endif
1072 psSGXDevInitPart2IN->sInitInfo.hKernelHWProfilingMemInfo, 1512 psSGXDevInitPart2IN->sInitInfo.hKernelHWProfilingMemInfo,
1073 PVRSRV_HANDLE_TYPE_MEM_INFO); 1513 PVRSRV_HANDLE_TYPE_MEM_INFO);
1074 if (eError != PVRSRV_OK) 1514 if (eError != PVRSRV_OK)
@@ -1079,7 +1519,11 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1079 1519
1080#if defined(SUPPORT_SGX_HWPERF) 1520#if defined(SUPPORT_SGX_HWPERF)
1081 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase, 1521 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1522#if defined (SUPPORT_SID_INTERFACE)
1523 &asInitInfoKM.hKernelHWPerfCBMemInfo,
1524#else
1082 &psSGXDevInitPart2IN->sInitInfo.hKernelHWPerfCBMemInfo, 1525 &psSGXDevInitPart2IN->sInitInfo.hKernelHWPerfCBMemInfo,
1526#endif
1083 psSGXDevInitPart2IN->sInitInfo.hKernelHWPerfCBMemInfo, 1527 psSGXDevInitPart2IN->sInitInfo.hKernelHWPerfCBMemInfo,
1084 PVRSRV_HANDLE_TYPE_MEM_INFO); 1528 PVRSRV_HANDLE_TYPE_MEM_INFO);
1085 if (eError != PVRSRV_OK) 1529 if (eError != PVRSRV_OK)
@@ -1089,7 +1533,11 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1089#endif 1533#endif
1090 1534
1091 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase, 1535 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1536#if defined (SUPPORT_SID_INTERFACE)
1537 &asInitInfoKM.hKernelTASigBufferMemInfo,
1538#else
1092 &psSGXDevInitPart2IN->sInitInfo.hKernelTASigBufferMemInfo, 1539 &psSGXDevInitPart2IN->sInitInfo.hKernelTASigBufferMemInfo,
1540#endif
1093 psSGXDevInitPart2IN->sInitInfo.hKernelTASigBufferMemInfo, 1541 psSGXDevInitPart2IN->sInitInfo.hKernelTASigBufferMemInfo,
1094 PVRSRV_HANDLE_TYPE_MEM_INFO); 1542 PVRSRV_HANDLE_TYPE_MEM_INFO);
1095 if (eError != PVRSRV_OK) 1543 if (eError != PVRSRV_OK)
@@ -1098,7 +1546,11 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1098 } 1546 }
1099 1547
1100 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase, 1548 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1549#if defined (SUPPORT_SID_INTERFACE)
1550 &asInitInfoKM.hKernel3DSigBufferMemInfo,
1551#else
1101 &psSGXDevInitPart2IN->sInitInfo.hKernel3DSigBufferMemInfo, 1552 &psSGXDevInitPart2IN->sInitInfo.hKernel3DSigBufferMemInfo,
1553#endif
1102 psSGXDevInitPart2IN->sInitInfo.hKernel3DSigBufferMemInfo, 1554 psSGXDevInitPart2IN->sInitInfo.hKernel3DSigBufferMemInfo,
1103 PVRSRV_HANDLE_TYPE_MEM_INFO); 1555 PVRSRV_HANDLE_TYPE_MEM_INFO);
1104 if (eError != PVRSRV_OK) 1556 if (eError != PVRSRV_OK)
@@ -1108,7 +1560,11 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1108 1560
1109#if defined(FIX_HW_BRN_29702) 1561#if defined(FIX_HW_BRN_29702)
1110 eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 1562 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
1563#if defined (SUPPORT_SID_INTERFACE)
1564 &asInitInfoKM.hKernelCFIMemInfo,
1565#else
1111 &psSGXDevInitPart2IN->sInitInfo.hKernelCFIMemInfo, 1566 &psSGXDevInitPart2IN->sInitInfo.hKernelCFIMemInfo,
1567#endif
1112 psSGXDevInitPart2IN->sInitInfo.hKernelCFIMemInfo, 1568 psSGXDevInitPart2IN->sInitInfo.hKernelCFIMemInfo,
1113 PVRSRV_HANDLE_TYPE_MEM_INFO); 1569 PVRSRV_HANDLE_TYPE_MEM_INFO);
1114 if (eError != PVRSRV_OK) 1570 if (eError != PVRSRV_OK)
@@ -1119,7 +1575,11 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1119 1575
1120#if defined(FIX_HW_BRN_29823) 1576#if defined(FIX_HW_BRN_29823)
1121 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase, 1577 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1578#if defined (SUPPORT_SID_INTERFACE)
1579 &asInitInfoKM.hKernelDummyTermStreamMemInfo,
1580#else
1122 &psSGXDevInitPart2IN->sInitInfo.hKernelDummyTermStreamMemInfo, 1581 &psSGXDevInitPart2IN->sInitInfo.hKernelDummyTermStreamMemInfo,
1582#endif
1123 psSGXDevInitPart2IN->sInitInfo.hKernelDummyTermStreamMemInfo, 1583 psSGXDevInitPart2IN->sInitInfo.hKernelDummyTermStreamMemInfo,
1124 PVRSRV_HANDLE_TYPE_MEM_INFO); 1584 PVRSRV_HANDLE_TYPE_MEM_INFO);
1125 if (eError != PVRSRV_OK) 1585 if (eError != PVRSRV_OK)
@@ -1128,9 +1588,132 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1128 } 1588 }
1129#endif 1589#endif
1130 1590
1591
1592#if defined(FIX_HW_BRN_31542)
1593 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1594#if defined (SUPPORT_SID_INTERFACE)
1595 &asInitInfoKM.hKernelClearClipWAVDMStreamMemInfo,
1596#else
1597 &psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAVDMStreamMemInfo,
1598#endif
1599 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAVDMStreamMemInfo,
1600 PVRSRV_HANDLE_TYPE_MEM_INFO);
1601 if (eError != PVRSRV_OK)
1602 {
1603 bReleaseFailed = IMG_TRUE;
1604 }
1605 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1606#if defined (SUPPORT_SID_INTERFACE)
1607 &asInitInfoKM.hKernelClearClipWAIndexStreamMemInfo,
1608#else
1609 &psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAIndexStreamMemInfo,
1610#endif
1611 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAIndexStreamMemInfo,
1612 PVRSRV_HANDLE_TYPE_MEM_INFO);
1613 if (eError != PVRSRV_OK)
1614 {
1615 bReleaseFailed = IMG_TRUE;
1616 }
1617 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1618#if defined (SUPPORT_SID_INTERFACE)
1619 &asInitInfoKM.hKernelClearClipWAPDSMemInfo,
1620#else
1621 &psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAPDSMemInfo,
1622#endif
1623 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAPDSMemInfo,
1624 PVRSRV_HANDLE_TYPE_MEM_INFO);
1625 if (eError != PVRSRV_OK)
1626 {
1627 bReleaseFailed = IMG_TRUE;
1628 }
1629 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1630#if defined (SUPPORT_SID_INTERFACE)
1631 &asInitInfoKM.hKernelClearClipWAUSEMemInfo,
1632#else
1633 &psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAUSEMemInfo,
1634#endif
1635 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAUSEMemInfo,
1636 PVRSRV_HANDLE_TYPE_MEM_INFO);
1637 if (eError != PVRSRV_OK)
1638 {
1639 bReleaseFailed = IMG_TRUE;
1640 }
1641 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1642#if defined (SUPPORT_SID_INTERFACE)
1643 &asInitInfoKM.hKernelClearClipWAParamMemInfo,
1644#else
1645 &psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAParamMemInfo,
1646#endif
1647 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAParamMemInfo,
1648 PVRSRV_HANDLE_TYPE_MEM_INFO);
1649 if (eError != PVRSRV_OK)
1650 {
1651 bReleaseFailed = IMG_TRUE;
1652 }
1653 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1654#if defined (SUPPORT_SID_INTERFACE)
1655 &asInitInfoKM.hKernelClearClipWAPMPTMemInfo,
1656#else
1657 &psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAPMPTMemInfo,
1658#endif
1659 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAPMPTMemInfo,
1660 PVRSRV_HANDLE_TYPE_MEM_INFO);
1661 if (eError != PVRSRV_OK)
1662 {
1663 bReleaseFailed = IMG_TRUE;
1664 }
1665 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1666#if defined (SUPPORT_SID_INTERFACE)
1667 &asInitInfoKM.hKernelClearClipWATPCMemInfo,
1668#else
1669 &psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWATPCMemInfo,
1670#endif
1671 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWATPCMemInfo,
1672 PVRSRV_HANDLE_TYPE_MEM_INFO);
1673 if (eError != PVRSRV_OK)
1674 {
1675 bReleaseFailed = IMG_TRUE;
1676 }
1677 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1678#if defined (SUPPORT_SID_INTERFACE)
1679 &asInitInfoKM.hKernelClearClipWAPSGRgnHdrMemInfo,
1680#else
1681 &psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAPSGRgnHdrMemInfo,
1682#endif
1683 psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAPSGRgnHdrMemInfo,
1684 PVRSRV_HANDLE_TYPE_MEM_INFO);
1685 if (eError != PVRSRV_OK)
1686 {
1687 bReleaseFailed = IMG_TRUE;
1688 }
1689#endif
1690#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && defined(FIX_HW_BRN_31425)
1691 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1692 &psSGXDevInitPart2IN->sInitInfo.hKernelVDMSnapShotBufferMemInfo,
1693 psSGXDevInitPart2IN->sInitInfo.hKernelVDMSnapShotBufferMemInfo,
1694 PVRSRV_HANDLE_TYPE_MEM_INFO);
1695 if (eError != PVRSRV_OK)
1696 {
1697 bReleaseFailed = IMG_TRUE;
1698 }
1699
1700 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1701 &psSGXDevInitPart2IN->sInitInfo.hKernelVDMCtrlStreamBufferMemInfo,
1702 psSGXDevInitPart2IN->sInitInfo.hKernelVDMCtrlStreamBufferMemInfo,
1703 PVRSRV_HANDLE_TYPE_MEM_INFO);
1704 if (eError != PVRSRV_OK)
1705 {
1706 bReleaseFailed = IMG_TRUE;
1707 }
1708#endif
1709
1131#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG) 1710#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
1132 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase, 1711 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1712#if defined (SUPPORT_SID_INTERFACE)
1713 &asInitInfoKM.hKernelEDMStatusBufferMemInfo,
1714#else
1133 &psSGXDevInitPart2IN->sInitInfo.hKernelEDMStatusBufferMemInfo, 1715 &psSGXDevInitPart2IN->sInitInfo.hKernelEDMStatusBufferMemInfo,
1716#endif
1134 psSGXDevInitPart2IN->sInitInfo.hKernelEDMStatusBufferMemInfo, 1717 psSGXDevInitPart2IN->sInitInfo.hKernelEDMStatusBufferMemInfo,
1135 PVRSRV_HANDLE_TYPE_MEM_INFO); 1718 PVRSRV_HANDLE_TYPE_MEM_INFO);
1136 if (eError != PVRSRV_OK) 1719 if (eError != PVRSRV_OK)
@@ -1141,7 +1724,11 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1141 1724
1142#if defined(SGX_FEATURE_SPM_MODE_0) 1725#if defined(SGX_FEATURE_SPM_MODE_0)
1143 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase, 1726 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1727#if defined (SUPPORT_SID_INTERFACE)
1728 &asInitInfoKM.hKernelTmpDPMStateMemInfo,
1729#else
1144 &psSGXDevInitPart2IN->sInitInfo.hKernelTmpDPMStateMemInfo, 1730 &psSGXDevInitPart2IN->sInitInfo.hKernelTmpDPMStateMemInfo,
1731#endif
1145 psSGXDevInitPart2IN->sInitInfo.hKernelTmpDPMStateMemInfo, 1732 psSGXDevInitPart2IN->sInitInfo.hKernelTmpDPMStateMemInfo,
1146 PVRSRV_HANDLE_TYPE_MEM_INFO); 1733 PVRSRV_HANDLE_TYPE_MEM_INFO);
1147 if (eError != PVRSRV_OK) 1734 if (eError != PVRSRV_OK)
@@ -1153,14 +1740,26 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1153 1740
1154 for (i = 0; i < SGX_MAX_INIT_MEM_HANDLES; i++) 1741 for (i = 0; i < SGX_MAX_INIT_MEM_HANDLES; i++)
1155 { 1742 {
1743#if defined (SUPPORT_SID_INTERFACE)
1744 IMG_SID hHandle = psSGXDevInitPart2IN->sInitInfo.asInitMemHandles[i];
1745 IMG_HANDLE *phHandleKM = &asInitInfoKM.asInitMemHandles[i];
1746
1747 if (hHandle == 0)
1748#else
1156 IMG_HANDLE *phHandle = &psSGXDevInitPart2IN->sInitInfo.asInitMemHandles[i]; 1749 IMG_HANDLE *phHandle = &psSGXDevInitPart2IN->sInitInfo.asInitMemHandles[i];
1157 1750
1158 if (*phHandle == IMG_NULL) 1751 if (*phHandle == IMG_NULL)
1752#endif
1159 continue; 1753 continue;
1160 1754
1161 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase, 1755 eError = PVRSRVLookupAndReleaseHandle(psPerProc->psHandleBase,
1756#if defined (SUPPORT_SID_INTERFACE)
1757 phHandleKM,
1758 hHandle,
1759#else
1162 phHandle, 1760 phHandle,
1163 *phHandle, 1761 *phHandle,
1762#endif
1164 PVRSRV_HANDLE_TYPE_MEM_INFO); 1763 PVRSRV_HANDLE_TYPE_MEM_INFO);
1165 if (eError != PVRSRV_OK) 1764 if (eError != PVRSRV_OK)
1166 { 1765 {
@@ -1171,45 +1770,69 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1171 if (bReleaseFailed) 1770 if (bReleaseFailed)
1172 { 1771 {
1173 PVR_DPF((PVR_DBG_ERROR, "DevInitSGXPart2BW: A handle release failed")); 1772 PVR_DPF((PVR_DBG_ERROR, "DevInitSGXPart2BW: A handle release failed"));
1174 psRetOUT->eError = PVRSRV_ERROR_INIT2_PHASE_FAILED; 1773 psSGXDevInitPart2OUT->eError = PVRSRV_ERROR_INIT2_PHASE_FAILED;
1175 1774
1176 PVR_DBG_BREAK; 1775 PVR_DBG_BREAK;
1177 return 0; 1776 return 0;
1178 } 1777 }
1179 1778
1180 1779
1780#if defined (SUPPORT_SID_INTERFACE)
1781 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelCCBMemInfo);
1782#else
1181 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelCCBMemInfo); 1783 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelCCBMemInfo);
1784#endif
1182 if (eError != PVRSRV_OK) 1785 if (eError != PVRSRV_OK)
1183 { 1786 {
1184 bDissociateFailed = IMG_TRUE; 1787 bDissociateFailed = IMG_TRUE;
1185 } 1788 }
1186 1789
1790#if defined (SUPPORT_SID_INTERFACE)
1791 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelCCBCtlMemInfo);
1792#else
1187 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelCCBCtlMemInfo); 1793 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelCCBCtlMemInfo);
1794#endif
1188 if (eError != PVRSRV_OK) 1795 if (eError != PVRSRV_OK)
1189 { 1796 {
1190 bDissociateFailed = IMG_TRUE; 1797 bDissociateFailed = IMG_TRUE;
1191 } 1798 }
1192 1799
1800#if defined (SUPPORT_SID_INTERFACE)
1801 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelCCBEventKickerMemInfo);
1802#else
1193 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelCCBEventKickerMemInfo); 1803 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelCCBEventKickerMemInfo);
1804#endif
1194 if (eError != PVRSRV_OK) 1805 if (eError != PVRSRV_OK)
1195 { 1806 {
1196 bDissociateFailed = IMG_TRUE; 1807 bDissociateFailed = IMG_TRUE;
1197 } 1808 }
1198 1809
1810#if defined (SUPPORT_SID_INTERFACE)
1811 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelSGXHostCtlMemInfo);
1812#else
1199 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelSGXHostCtlMemInfo); 1813 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelSGXHostCtlMemInfo);
1814#endif
1200 if (eError != PVRSRV_OK) 1815 if (eError != PVRSRV_OK)
1201 { 1816 {
1202 bDissociateFailed = IMG_TRUE; 1817 bDissociateFailed = IMG_TRUE;
1203 } 1818 }
1204 1819
1820#if defined (SUPPORT_SID_INTERFACE)
1821 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelSGXTA3DCtlMemInfo);
1822#else
1205 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelSGXTA3DCtlMemInfo); 1823 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelSGXTA3DCtlMemInfo);
1824#endif
1206 if (eError != PVRSRV_OK) 1825 if (eError != PVRSRV_OK)
1207 { 1826 {
1208 bDissociateFailed = IMG_TRUE; 1827 bDissociateFailed = IMG_TRUE;
1209 } 1828 }
1210 1829
1211 1830
1831#if defined (SUPPORT_SID_INTERFACE)
1832 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelSGXMiscMemInfo);
1833#else
1212 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelSGXMiscMemInfo); 1834 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelSGXMiscMemInfo);
1835#endif
1213 if (eError != PVRSRV_OK) 1836 if (eError != PVRSRV_OK)
1214 { 1837 {
1215 bDissociateFailed = IMG_TRUE; 1838 bDissociateFailed = IMG_TRUE;
@@ -1217,47 +1840,186 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1217 1840
1218 1841
1219#if defined(SGX_SUPPORT_HWPROFILING) 1842#if defined(SGX_SUPPORT_HWPROFILING)
1843#if defined (SUPPORT_SID_INTERFACE)
1844 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelHWProfilingMemInfo);
1845 if (eError != PVRSRV_OK)
1846 {
1847 bDissociateFailed = IMG_TRUE;
1848 }
1849#else
1220 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelHWProfilingMemInfo); 1850 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelHWProfilingMemInfo);
1221 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK); 1851 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
1222#endif 1852#endif
1853#endif
1223 1854
1224#if defined(SUPPORT_SGX_HWPERF) 1855#if defined(SUPPORT_SGX_HWPERF)
1856#if defined (SUPPORT_SID_INTERFACE)
1857 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelHWPerfCBMemInfo);
1858#else
1225 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelHWPerfCBMemInfo); 1859 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelHWPerfCBMemInfo);
1860#endif
1226 if (eError != PVRSRV_OK) 1861 if (eError != PVRSRV_OK)
1227 { 1862 {
1228 bDissociateFailed = IMG_TRUE; 1863 bDissociateFailed = IMG_TRUE;
1229 } 1864 }
1230#endif 1865#endif
1231 1866
1867#if defined (SUPPORT_SID_INTERFACE)
1868 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelTASigBufferMemInfo);
1869#else
1232 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelTASigBufferMemInfo); 1870 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelTASigBufferMemInfo);
1871#endif
1233 if (eError != PVRSRV_OK) 1872 if (eError != PVRSRV_OK)
1234 { 1873 {
1235 bDissociateFailed = IMG_TRUE; 1874 bDissociateFailed = IMG_TRUE;
1236 } 1875 }
1237 1876
1877#if defined (SUPPORT_SID_INTERFACE)
1878 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernel3DSigBufferMemInfo);
1879#else
1238 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernel3DSigBufferMemInfo); 1880 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernel3DSigBufferMemInfo);
1881#endif
1239 if (eError != PVRSRV_OK) 1882 if (eError != PVRSRV_OK)
1240 { 1883 {
1241 bDissociateFailed = IMG_TRUE; 1884 bDissociateFailed = IMG_TRUE;
1242 } 1885 }
1243 1886
1244#if defined(FIX_HW_BRN_29702) 1887#if defined(FIX_HW_BRN_29702)
1888#if defined (SUPPORT_SID_INTERFACE)
1889 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelCFIMemInfo);
1890 if (eError != PVRSRV_OK)
1891 {
1892 bDissociateFailed = IMG_TRUE;
1893 }
1894#else
1245 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelCFIMemInfo); 1895 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelCFIMemInfo);
1246 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK); 1896 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
1247#endif 1897#endif
1898#endif
1248 1899
1249#if defined(FIX_HW_BRN_29823) 1900#if defined(FIX_HW_BRN_29823)
1901#if defined (SUPPORT_SID_INTERFACE)
1902 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelDummyTermStreamMemInfo);
1903 if (eError != PVRSRV_OK)
1904 {
1905 bDissociateFailed = IMG_TRUE;
1906 }
1907#else
1250 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelDummyTermStreamMemInfo); 1908 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelDummyTermStreamMemInfo);
1251 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK); 1909 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
1252#endif 1910#endif
1911#endif
1912
1913#if defined(FIX_HW_BRN_31542)
1914#if defined (SUPPORT_SID_INTERFACE)
1915 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelClearClipWAVDMStreamMemInfo);
1916 if (eError != PVRSRV_OK)
1917 {
1918 bDissociateFailed = IMG_TRUE;
1919 }
1920#else
1921 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAVDMStreamMemInfo);
1922 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
1923#endif
1924#if defined (SUPPORT_SID_INTERFACE)
1925 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelClearClipWAIndexStreamMemInfo);
1926 if (eError != PVRSRV_OK)
1927 {
1928 bDissociateFailed = IMG_TRUE;
1929 }
1930#else
1931 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAIndexStreamMemInfo);
1932 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
1933#endif
1934#if defined (SUPPORT_SID_INTERFACE)
1935 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelClearClipWAPDSMemInfo);
1936 if (eError != PVRSRV_OK)
1937 {
1938 bDissociateFailed = IMG_TRUE;
1939 }
1940#else
1941 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAPDSMemInfo);
1942 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
1943#endif
1944#if defined (SUPPORT_SID_INTERFACE)
1945 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelClearClipWAUSEMemInfo);
1946 if (eError != PVRSRV_OK)
1947 {
1948 bDissociateFailed = IMG_TRUE;
1949 }
1950#else
1951 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAUSEMemInfo);
1952 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
1953#endif
1954#if defined (SUPPORT_SID_INTERFACE)
1955 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelClearClipWAParamMemInfo);
1956 if (eError != PVRSRV_OK)
1957 {
1958 bDissociateFailed = IMG_TRUE;
1959 }
1960#else
1961 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAParamMemInfo);
1962 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
1963#endif
1964#if defined (SUPPORT_SID_INTERFACE)
1965 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelClearClipWAPMPTMemInfo);
1966 if (eError != PVRSRV_OK)
1967 {
1968 bDissociateFailed = IMG_TRUE;
1969 }
1970#else
1971 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAPMPTMemInfo);
1972 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
1973#endif
1974#if defined (SUPPORT_SID_INTERFACE)
1975 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelClearClipWATPCMemInfo);
1976 if (eError != PVRSRV_OK)
1977 {
1978 bDissociateFailed = IMG_TRUE;
1979 }
1980#else
1981 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWATPCMemInfo);
1982 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
1983#endif
1984#if defined (SUPPORT_SID_INTERFACE)
1985 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelClearClipWAPSGRgnHdrMemInfo);
1986 if (eError != PVRSRV_OK)
1987 {
1988 bDissociateFailed = IMG_TRUE;
1989 }
1990#else
1991 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelClearClipWAPSGRgnHdrMemInfo);
1992 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
1993#endif
1994#endif
1995
1996#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && defined(FIX_HW_BRN_31425)
1997 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelVDMSnapShotBufferMemInfo);
1998 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
1999
2000 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelVDMCtrlStreamBufferMemInfo);
2001 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
2002#endif
1253 2003
1254#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG) 2004#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
2005#if defined (SUPPORT_SID_INTERFACE)
2006 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelEDMStatusBufferMemInfo);
2007 if (eError != PVRSRV_OK)
2008 {
2009 bDissociateFailed = IMG_TRUE;
2010 }
2011#else
1255 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelEDMStatusBufferMemInfo); 2012 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelEDMStatusBufferMemInfo);
1256 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK); 2013 bDissociateFailed |= (IMG_BOOL)(eError != PVRSRV_OK);
1257#endif 2014#endif
2015#endif
1258 2016
1259#if defined(SGX_FEATURE_SPM_MODE_0) 2017#if defined(SGX_FEATURE_SPM_MODE_0)
2018#if defined (SUPPORT_SID_INTERFACE)
2019 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelTmpDPMStateMemInfo);
2020#else
1260 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelTmpDPMStateMemInfo); 2021 eError = PVRSRVDissociateDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelTmpDPMStateMemInfo);
2022#endif
1261 if (eError != PVRSRV_OK) 2023 if (eError != PVRSRV_OK)
1262 { 2024 {
1263 bDissociateFailed = IMG_TRUE; 2025 bDissociateFailed = IMG_TRUE;
@@ -1266,7 +2028,11 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1266 2028
1267 for (i = 0; i < SGX_MAX_INIT_MEM_HANDLES; i++) 2029 for (i = 0; i < SGX_MAX_INIT_MEM_HANDLES; i++)
1268 { 2030 {
2031#if defined (SUPPORT_SID_INTERFACE)
2032 IMG_HANDLE hHandle = asInitInfoKM.asInitMemHandles[i];
2033#else
1269 IMG_HANDLE hHandle = psSGXDevInitPart2IN->sInitInfo.asInitMemHandles[i]; 2034 IMG_HANDLE hHandle = psSGXDevInitPart2IN->sInitInfo.asInitMemHandles[i];
2035#endif
1270 2036
1271 if (hHandle == IMG_NULL) 2037 if (hHandle == IMG_NULL)
1272 continue; 2038 continue;
@@ -1281,17 +2047,31 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1281 2047
1282 if(bDissociateFailed) 2048 if(bDissociateFailed)
1283 { 2049 {
2050#if defined (SUPPORT_SID_INTERFACE)
2051 PVRSRVFreeDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelCCBMemInfo);
2052 PVRSRVFreeDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelCCBCtlMemInfo);
2053 PVRSRVFreeDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelSGXHostCtlMemInfo);
2054 PVRSRVFreeDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelSGXTA3DCtlMemInfo);
2055 PVRSRVFreeDeviceMemKM(hDevCookieInt, asInitInfoKM.hKernelSGXMiscMemInfo);
2056#else
1284 PVRSRVFreeDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelCCBMemInfo); 2057 PVRSRVFreeDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelCCBMemInfo);
1285 PVRSRVFreeDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelCCBCtlMemInfo); 2058 PVRSRVFreeDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelCCBCtlMemInfo);
1286 PVRSRVFreeDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelSGXHostCtlMemInfo); 2059 PVRSRVFreeDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelSGXHostCtlMemInfo);
1287 PVRSRVFreeDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelSGXTA3DCtlMemInfo); 2060 PVRSRVFreeDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelSGXTA3DCtlMemInfo);
1288 PVRSRVFreeDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelSGXMiscMemInfo); 2061 PVRSRVFreeDeviceMemKM(hDevCookieInt, psSGXDevInitPart2IN->sInitInfo.hKernelSGXMiscMemInfo);
2062#endif
1289 2063
1290 for (i = 0; i < SGX_MAX_INIT_MEM_HANDLES; i++) 2064 for (i = 0; i < SGX_MAX_INIT_MEM_HANDLES; i++)
1291 { 2065 {
2066#if defined (SUPPORT_SID_INTERFACE)
2067 IMG_HANDLE hHandle = asInitInfoKM.asInitMemHandles[i];
2068
2069 if (hHandle == 0)
2070#else
1292 IMG_HANDLE hHandle = psSGXDevInitPart2IN->sInitInfo.asInitMemHandles[i]; 2071 IMG_HANDLE hHandle = psSGXDevInitPart2IN->sInitInfo.asInitMemHandles[i];
1293 2072
1294 if (hHandle == IMG_NULL) 2073 if (hHandle == IMG_NULL)
2074#endif
1295 continue; 2075 continue;
1296 2076
1297 PVRSRVFreeDeviceMemKM(hDevCookieInt, (PVRSRV_KERNEL_MEM_INFO *)hHandle); 2077 PVRSRVFreeDeviceMemKM(hDevCookieInt, (PVRSRV_KERNEL_MEM_INFO *)hHandle);
@@ -1300,17 +2080,40 @@ SGXDevInitPart2BW(IMG_UINT32 ui32BridgeID,
1300 2080
1301 PVR_DPF((PVR_DBG_ERROR, "DevInitSGXPart2BW: A dissociate failed")); 2081 PVR_DPF((PVR_DBG_ERROR, "DevInitSGXPart2BW: A dissociate failed"));
1302 2082
1303 psRetOUT->eError = PVRSRV_ERROR_INIT2_PHASE_FAILED; 2083 psSGXDevInitPart2OUT->eError = PVRSRV_ERROR_INIT2_PHASE_FAILED;
1304 2084
1305 2085
1306 PVR_DBG_BREAK; 2086 PVR_DBG_BREAK;
1307 return 0; 2087 return 0;
1308 } 2088 }
1309 2089
1310 psRetOUT->eError = 2090#if defined (SUPPORT_SID_INTERFACE)
2091 asInitInfoKM.sScripts = psSGXDevInitPart2IN->sInitInfo.sScripts;
2092 asInitInfoKM.ui32ClientBuildOptions = psSGXDevInitPart2IN->sInitInfo.ui32ClientBuildOptions;
2093 asInitInfoKM.sSGXStructSizes = psSGXDevInitPart2IN->sInitInfo.sSGXStructSizes;
2094 asInitInfoKM.ui32CacheControl = psSGXDevInitPart2IN->sInitInfo.ui32CacheControl;
2095 asInitInfoKM.ui32EDMTaskReg0 = psSGXDevInitPart2IN->sInitInfo.ui32EDMTaskReg0;
2096 asInitInfoKM.ui32EDMTaskReg1 = psSGXDevInitPart2IN->sInitInfo.ui32EDMTaskReg1;
2097 asInitInfoKM.ui32ClkGateStatusReg = psSGXDevInitPart2IN->sInitInfo.ui32ClkGateStatusReg;
2098 asInitInfoKM.ui32ClkGateStatusMask = psSGXDevInitPart2IN->sInitInfo.ui32ClkGateStatusMask;
2099
2100 OSMemCopy(&asInitInfoKM.asInitDevData ,
2101 &psSGXDevInitPart2IN->sInitInfo.asInitDevData,
2102 sizeof(asInitInfoKM.asInitDevData));
2103 OSMemCopy(&asInitInfoKM.aui32HostKickAddr,
2104 &psSGXDevInitPart2IN->sInitInfo.aui32HostKickAddr,
2105 sizeof(asInitInfoKM.aui32HostKickAddr));
2106
2107 psSGXDevInitPart2OUT->eError =
2108 DevInitSGXPart2KM(psPerProc,
2109 hDevCookieInt,
2110 &asInitInfoKM);
2111#else
2112 psSGXDevInitPart2OUT->eError =
1311 DevInitSGXPart2KM(psPerProc, 2113 DevInitSGXPart2KM(psPerProc,
1312 hDevCookieInt, 2114 hDevCookieInt,
1313 &psSGXDevInitPart2IN->sInitInfo); 2115 &psSGXDevInitPart2IN->sInitInfo);
2116#endif
1314 2117
1315 return 0; 2118 return 0;
1316} 2119}
@@ -1449,7 +2252,11 @@ SGXUnregisterHWTransferContextBW(IMG_UINT32 ui32BridgeID,
1449 PVRSRV_BRIDGE_RETURN *psRetOUT, 2252 PVRSRV_BRIDGE_RETURN *psRetOUT,
1450 PVRSRV_PER_PROCESS_DATA *psPerProc) 2253 PVRSRV_PER_PROCESS_DATA *psPerProc)
1451{ 2254{
2255#if defined (SUPPORT_SID_INTERFACE)
2256 IMG_HANDLE hHWTransferContextInt = 0;
2257#else
1452 IMG_HANDLE hHWTransferContextInt; 2258 IMG_HANDLE hHWTransferContextInt;
2259#endif
1453 2260
1454 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_UNREGISTER_HW_TRANSFER_CONTEXT); 2261 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_UNREGISTER_HW_TRANSFER_CONTEXT);
1455 2262
@@ -1598,7 +2405,8 @@ SGX2DQueryBlitsCompleteBW(IMG_UINT32 ui32BridgeID,
1598 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_2DQUERYBLTSCOMPLETE); 2405 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_2DQUERYBLTSCOMPLETE);
1599 2406
1600 psRetOUT->eError = 2407 psRetOUT->eError =
1601 PVRSRVLookupHandle(psPerProc->psHandleBase, &hDevCookieInt, 2408 PVRSRVLookupHandle(psPerProc->psHandleBase,
2409 &hDevCookieInt,
1602 ps2DQueryBltsCompleteIN->hDevCookie, 2410 ps2DQueryBltsCompleteIN->hDevCookie,
1603 PVRSRV_HANDLE_TYPE_DEV_NODE); 2411 PVRSRV_HANDLE_TYPE_DEV_NODE);
1604 if(psRetOUT->eError != PVRSRV_OK) 2412 if(psRetOUT->eError != PVRSRV_OK)
@@ -1607,7 +2415,8 @@ SGX2DQueryBlitsCompleteBW(IMG_UINT32 ui32BridgeID,
1607 } 2415 }
1608 2416
1609 psRetOUT->eError = 2417 psRetOUT->eError =
1610 PVRSRVLookupHandle(psPerProc->psHandleBase, &pvSyncInfo, 2418 PVRSRVLookupHandle(psPerProc->psHandleBase,
2419 &pvSyncInfo,
1611 ps2DQueryBltsCompleteIN->hKernSyncInfo, 2420 ps2DQueryBltsCompleteIN->hKernSyncInfo,
1612 PVRSRV_HANDLE_TYPE_SYNC_INFO); 2421 PVRSRV_HANDLE_TYPE_SYNC_INFO);
1613 if(psRetOUT->eError != PVRSRV_OK) 2422 if(psRetOUT->eError != PVRSRV_OK)
@@ -1808,7 +2617,11 @@ SGXAddSharedPBDescBW(IMG_UINT32 ui32BridgeID,
1808 IMG_UINT32 ui32KernelMemInfoHandlesCount = 2617 IMG_UINT32 ui32KernelMemInfoHandlesCount =
1809 psSGXAddSharedPBDescIN->ui32KernelMemInfoHandlesCount; 2618 psSGXAddSharedPBDescIN->ui32KernelMemInfoHandlesCount;
1810 IMG_INT ret = 0; 2619 IMG_INT ret = 0;
2620#if defined (SUPPORT_SID_INTERFACE)
2621 IMG_SID *phKernelMemInfoHandles = 0;
2622#else
1811 IMG_HANDLE *phKernelMemInfoHandles = IMG_NULL; 2623 IMG_HANDLE *phKernelMemInfoHandles = IMG_NULL;
2624#endif
1812 PVRSRV_KERNEL_MEM_INFO **ppsKernelMemInfos = IMG_NULL; 2625 PVRSRV_KERNEL_MEM_INFO **ppsKernelMemInfos = IMG_NULL;
1813 IMG_UINT32 i; 2626 IMG_UINT32 i;
1814 PVRSRV_ERROR eError; 2627 PVRSRV_ERROR eError;
@@ -1964,7 +2777,8 @@ SGXAddSharedPBDescBW(IMG_UINT32 ui32BridgeID,
1964 psSGXAddSharedPBDescIN->ui32TotalPBSize, 2777 psSGXAddSharedPBDescIN->ui32TotalPBSize,
1965 &hSharedPBDesc, 2778 &hSharedPBDesc,
1966 ppsKernelMemInfos, 2779 ppsKernelMemInfos,
1967 ui32KernelMemInfoHandlesCount); 2780 ui32KernelMemInfoHandlesCount,
2781 psSGXAddSharedPBDescIN->sHWPBDescDevVAddr);
1968 2782
1969 2783
1970 if (eError != PVRSRV_OK) 2784 if (eError != PVRSRV_OK)
@@ -2013,6 +2827,9 @@ SGXGetInfoForSrvinitBW(IMG_UINT32 ui32BridgeID,
2013{ 2827{
2014 IMG_HANDLE hDevCookieInt; 2828 IMG_HANDLE hDevCookieInt;
2015 IMG_UINT32 i; 2829 IMG_UINT32 i;
2830#if defined (SUPPORT_SID_INTERFACE)
2831 PVRSRV_HEAP_INFO_KM asHeapInfo[PVRSRV_MAX_CLIENT_HEAPS];
2832#endif
2016 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGXINFO_FOR_SRVINIT); 2833 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGXINFO_FOR_SRVINIT);
2017 2834
2018 NEW_HANDLE_BATCH_OR_ERROR(psSGXInfoForSrvinitOUT->eError, psPerProc, PVRSRV_MAX_CLIENT_HEAPS); 2835 NEW_HANDLE_BATCH_OR_ERROR(psSGXInfoForSrvinitOUT->eError, psPerProc, PVRSRV_MAX_CLIENT_HEAPS);
@@ -2035,7 +2852,12 @@ SGXGetInfoForSrvinitBW(IMG_UINT32 ui32BridgeID,
2035 2852
2036 psSGXInfoForSrvinitOUT->eError = 2853 psSGXInfoForSrvinitOUT->eError =
2037 SGXGetInfoForSrvinitKM(hDevCookieInt, 2854 SGXGetInfoForSrvinitKM(hDevCookieInt,
2855#if defined (SUPPORT_SID_INTERFACE)
2856 &asHeapInfo[0],
2857 &psSGXInfoForSrvinitOUT->sInitInfo.sPDDevPAddr);
2858#else
2038 &psSGXInfoForSrvinitOUT->sInitInfo); 2859 &psSGXInfoForSrvinitOUT->sInitInfo);
2860#endif
2039 2861
2040 if(psSGXInfoForSrvinitOUT->eError != PVRSRV_OK) 2862 if(psSGXInfoForSrvinitOUT->eError != PVRSRV_OK)
2041 { 2863 {
@@ -2048,6 +2870,28 @@ SGXGetInfoForSrvinitBW(IMG_UINT32 ui32BridgeID,
2048 2870
2049 psHeapInfo = &psSGXInfoForSrvinitOUT->sInitInfo.asHeapInfo[i]; 2871 psHeapInfo = &psSGXInfoForSrvinitOUT->sInitInfo.asHeapInfo[i];
2050 2872
2873#if defined (SUPPORT_SID_INTERFACE)
2874 if ((asHeapInfo[i].ui32HeapID != (IMG_UINT32)SGX_UNDEFINED_HEAP_ID) &&
2875 (asHeapInfo[i].hDevMemHeap != IMG_NULL))
2876 {
2877
2878 PVRSRVAllocHandleNR(psPerProc->psHandleBase,
2879 &psHeapInfo->hDevMemHeap,
2880 asHeapInfo[i].hDevMemHeap,
2881 PVRSRV_HANDLE_TYPE_DEV_MEM_HEAP,
2882 PVRSRV_HANDLE_ALLOC_FLAG_SHARED);
2883 }
2884 else
2885 {
2886 psHeapInfo->hDevMemHeap = 0;
2887 }
2888
2889 psHeapInfo->ui32HeapID = asHeapInfo[i].ui32HeapID;
2890 psHeapInfo->sDevVAddrBase = asHeapInfo[i].sDevVAddrBase;
2891 psHeapInfo->ui32HeapByteSize = asHeapInfo[i].ui32HeapByteSize;
2892 psHeapInfo->ui32Attribs = asHeapInfo[i].ui32Attribs;
2893 psHeapInfo->ui32XTileStride = asHeapInfo[i].ui32XTileStride;
2894#else
2051 if (psHeapInfo->ui32HeapID != (IMG_UINT32)SGX_UNDEFINED_HEAP_ID) 2895 if (psHeapInfo->ui32HeapID != (IMG_UINT32)SGX_UNDEFINED_HEAP_ID)
2052 { 2896 {
2053 IMG_HANDLE hDevMemHeapExt; 2897 IMG_HANDLE hDevMemHeapExt;
@@ -2063,6 +2907,7 @@ SGXGetInfoForSrvinitBW(IMG_UINT32 ui32BridgeID,
2063 psHeapInfo->hDevMemHeap = hDevMemHeapExt; 2907 psHeapInfo->hDevMemHeap = hDevMemHeapExt;
2064 } 2908 }
2065 } 2909 }
2910#endif
2066 } 2911 }
2067 2912
2068 COMMIT_HANDLE_BATCH_OR_ERROR(psSGXInfoForSrvinitOUT->eError, psPerProc); 2913 COMMIT_HANDLE_BATCH_OR_ERROR(psSGXInfoForSrvinitOUT->eError, psPerProc);
@@ -2072,17 +2917,25 @@ SGXGetInfoForSrvinitBW(IMG_UINT32 ui32BridgeID,
2072 2917
2073#if defined(PDUMP) 2918#if defined(PDUMP)
2074static IMG_VOID 2919static IMG_VOID
2075DumpBufferArray(PVRSRV_PER_PROCESS_DATA *psPerProc, 2920DumpBufferArray(PVRSRV_PER_PROCESS_DATA *psPerProc,
2921#if defined (SUPPORT_SID_INTERFACE)
2922 PSGX_KICKTA_DUMP_BUFFER_KM psBufferArray,
2923#else
2076 PSGX_KICKTA_DUMP_BUFFER psBufferArray, 2924 PSGX_KICKTA_DUMP_BUFFER psBufferArray,
2077 IMG_UINT32 ui32BufferArrayLength, 2925#endif
2078 IMG_BOOL bDumpPolls) 2926 IMG_UINT32 ui32BufferArrayLength,
2927 IMG_BOOL bDumpPolls)
2079{ 2928{
2080 IMG_UINT32 i; 2929 IMG_UINT32 i;
2081 2930
2082 for (i=0; i<ui32BufferArrayLength; i++) 2931 for (i=0; i<ui32BufferArrayLength; i++)
2083 { 2932 {
2933#if defined (SUPPORT_SID_INTERFACE)
2934 PSGX_KICKTA_DUMP_BUFFER_KM psBuffer;
2935#else
2084 PSGX_KICKTA_DUMP_BUFFER psBuffer; 2936 PSGX_KICKTA_DUMP_BUFFER psBuffer;
2085 PVRSRV_KERNEL_MEM_INFO *psCtrlMemInfoKM; 2937#endif
2938 PVRSRV_KERNEL_MEM_INFO *psCtrlMemInfoKM;
2086 IMG_CHAR * pszName; 2939 IMG_CHAR * pszName;
2087 IMG_HANDLE hUniqueTag; 2940 IMG_HANDLE hUniqueTag;
2088 IMG_UINT32 ui32Offset; 2941 IMG_UINT32 ui32Offset;
@@ -2191,7 +3044,12 @@ SGXPDumpBufferArrayBW(IMG_UINT32 ui32BridgeID,
2191 PVRSRV_PER_PROCESS_DATA *psPerProc) 3044 PVRSRV_PER_PROCESS_DATA *psPerProc)
2192{ 3045{
2193 IMG_UINT32 i; 3046 IMG_UINT32 i;
3047#if defined (SUPPORT_SID_INTERFACE)
3048 SGX_KICKTA_DUMP_BUFFER *psUMPtr;
3049 SGX_KICKTA_DUMP_BUFFER_KM *psKickTADumpBufferKM, *psKMPtr;
3050#else
2194 SGX_KICKTA_DUMP_BUFFER *psKickTADumpBuffer; 3051 SGX_KICKTA_DUMP_BUFFER *psKickTADumpBuffer;
3052#endif
2195 IMG_UINT32 ui32BufferArrayLength = 3053 IMG_UINT32 ui32BufferArrayLength =
2196 psPDumpBufferArrayIN->ui32BufferArrayLength; 3054 psPDumpBufferArrayIN->ui32BufferArrayLength;
2197 IMG_UINT32 ui32BufferArraySize = 3055 IMG_UINT32 ui32BufferArraySize =
@@ -2202,14 +3060,22 @@ SGXPDumpBufferArrayBW(IMG_UINT32 ui32BridgeID,
2202 3060
2203 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_PDUMP_BUFFER_ARRAY); 3061 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_PDUMP_BUFFER_ARRAY);
2204 3062
3063#if defined (SUPPORT_SID_INTERFACE)
3064 if(OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
3065 ui32BufferArraySize,
3066 (IMG_PVOID *)&psKickTADumpBufferKM, 0,
3067 "Array of Kick Tile Accelerator Dump Buffer") != PVRSRV_OK)
3068#else
2205 if(OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, 3069 if(OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
2206 ui32BufferArraySize, 3070 ui32BufferArraySize,
2207 (IMG_PVOID *)&psKickTADumpBuffer, 0, 3071 (IMG_PVOID *)&psKickTADumpBuffer, 0,
2208 "Array of Kick Tile Accelerator Dump Buffer") != PVRSRV_OK) 3072 "Array of Kick Tile Accelerator Dump Buffer") != PVRSRV_OK)
3073#endif
2209 { 3074 {
2210 return -ENOMEM; 3075 return -ENOMEM;
2211 } 3076 }
2212 3077
3078#if !defined (SUPPORT_SID_INTERFACE)
2213 if(CopyFromUserWrapper(psPerProc, 3079 if(CopyFromUserWrapper(psPerProc,
2214 ui32BridgeID, 3080 ui32BridgeID,
2215 psKickTADumpBuffer, 3081 psKickTADumpBuffer,
@@ -2220,14 +3086,25 @@ SGXPDumpBufferArrayBW(IMG_UINT32 ui32BridgeID,
2220 3086
2221 return -EFAULT; 3087 return -EFAULT;
2222 } 3088 }
3089#endif
2223 3090
2224 for(i = 0; i < ui32BufferArrayLength; i++) 3091 for(i = 0; i < ui32BufferArrayLength; i++)
2225 { 3092 {
3093#if defined (SUPPORT_SID_INTERFACE)
3094 IMG_VOID *pvMemInfo = IMG_NULL;
3095 psUMPtr = &psPDumpBufferArrayIN->psBufferArray[i];
3096 psKMPtr = &psKickTADumpBufferKM[i];
3097#else
2226 IMG_VOID *pvMemInfo; 3098 IMG_VOID *pvMemInfo;
3099#endif
2227 3100
2228 eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 3101 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
2229 &pvMemInfo, 3102 &pvMemInfo,
3103#if defined (SUPPORT_SID_INTERFACE)
3104 psUMPtr->hKernelMemInfo,
3105#else
2230 psKickTADumpBuffer[i].hKernelMemInfo, 3106 psKickTADumpBuffer[i].hKernelMemInfo,
3107#endif
2231 PVRSRV_HANDLE_TYPE_MEM_INFO); 3108 PVRSRV_HANDLE_TYPE_MEM_INFO);
2232 3109
2233 if(eError != PVRSRV_OK) 3110 if(eError != PVRSRV_OK)
@@ -2236,12 +3113,20 @@ SGXPDumpBufferArrayBW(IMG_UINT32 ui32BridgeID,
2236 "PVRSRVLookupHandle failed (%d)", eError)); 3113 "PVRSRVLookupHandle failed (%d)", eError));
2237 break; 3114 break;
2238 } 3115 }
3116#if defined (SUPPORT_SID_INTERFACE)
3117 psKMPtr->hKernelMemInfo = pvMemInfo;
3118#else
2239 psKickTADumpBuffer[i].hKernelMemInfo = pvMemInfo; 3119 psKickTADumpBuffer[i].hKernelMemInfo = pvMemInfo;
3120#endif
2240 3121
2241#if defined(SUPPORT_SGX_NEW_STATUS_VALS) 3122#if defined(SUPPORT_SGX_NEW_STATUS_VALS)
2242 eError = PVRSRVLookupHandle(psPerProc->psHandleBase, 3123 eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
2243 &pvMemInfo, 3124 &pvMemInfo,
3125#if defined (SUPPORT_SID_INTERFACE)
3126 psUMPtr->hCtrlKernelMemInfo,
3127#else
2244 psKickTADumpBuffer[i].hCtrlKernelMemInfo, 3128 psKickTADumpBuffer[i].hCtrlKernelMemInfo,
3129#endif
2245 PVRSRV_HANDLE_TYPE_MEM_INFO); 3130 PVRSRV_HANDLE_TYPE_MEM_INFO);
2246 3131
2247 if(eError != PVRSRV_OK) 3132 if(eError != PVRSRV_OK)
@@ -2250,19 +3135,43 @@ SGXPDumpBufferArrayBW(IMG_UINT32 ui32BridgeID,
2250 "PVRSRVLookupHandle failed (%d)", eError)); 3135 "PVRSRVLookupHandle failed (%d)", eError));
2251 break; 3136 break;
2252 } 3137 }
3138#if defined (SUPPORT_SID_INTERFACE)
3139 psKMPtr->hCtrlKernelMemInfo = pvMemInfo;
3140 psKMPtr->sCtrlDevVAddr = psUMPtr->sCtrlDevVAddr;
3141#else
2253 psKickTADumpBuffer[i].hCtrlKernelMemInfo = pvMemInfo; 3142 psKickTADumpBuffer[i].hCtrlKernelMemInfo = pvMemInfo;
2254#endif 3143#endif
3144#endif
3145
3146#if defined (SUPPORT_SID_INTERFACE)
3147 psKMPtr->ui32SpaceUsed = psUMPtr->ui32SpaceUsed;
3148 psKMPtr->ui32Start = psUMPtr->ui32Start;
3149 psKMPtr->ui32End = psUMPtr->ui32End;
3150 psKMPtr->ui32BufferSize = psUMPtr->ui32BufferSize;
3151 psKMPtr->ui32BackEndLength = psUMPtr->ui32BackEndLength;
3152 psKMPtr->uiAllocIndex = psUMPtr->uiAllocIndex;
3153 psKMPtr->pvLinAddr = psUMPtr->pvLinAddr;
3154 psKMPtr->pszName = psUMPtr->pszName;
3155#endif
2255 } 3156 }
2256 3157
2257 if(eError == PVRSRV_OK) 3158 if(eError == PVRSRV_OK)
2258 { 3159 {
2259 DumpBufferArray(psPerProc, 3160 DumpBufferArray(psPerProc,
3161#if defined (SUPPORT_SID_INTERFACE)
3162 psKickTADumpBufferKM,
3163#else
2260 psKickTADumpBuffer, 3164 psKickTADumpBuffer,
3165#endif
2261 ui32BufferArrayLength, 3166 ui32BufferArrayLength,
2262 psPDumpBufferArrayIN->bDumpPolls); 3167 psPDumpBufferArrayIN->bDumpPolls);
2263 } 3168 }
2264 3169
3170#if defined (SUPPORT_SID_INTERFACE)
3171 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, ui32BufferArraySize, psKickTADumpBufferKM, 0);
3172#else
2265 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, ui32BufferArraySize, psKickTADumpBuffer, 0); 3173 OSFreeMem(PVRSRV_OS_PAGEABLE_HEAP, ui32BufferArraySize, psKickTADumpBuffer, 0);
3174#endif
2266 3175
2267 3176
2268 return 0; 3177 return 0;
@@ -2276,11 +3185,13 @@ SGXPDump3DSignatureRegistersBW(IMG_UINT32 ui32BridgeID,
2276{ 3185{
2277 IMG_UINT32 ui32RegisterArraySize = psPDump3DSignatureRegistersIN->ui32NumRegisters * sizeof(IMG_UINT32); 3186 IMG_UINT32 ui32RegisterArraySize = psPDump3DSignatureRegistersIN->ui32NumRegisters * sizeof(IMG_UINT32);
2278 IMG_UINT32 *pui32Registers = IMG_NULL; 3187 IMG_UINT32 *pui32Registers = IMG_NULL;
2279 PVRSRV_SGXDEV_INFO *psDevInfo = IMG_NULL; 3188 PVRSRV_SGXDEV_INFO *psDevInfo;
2280#if defined(SGX_FEATURE_MP) && defined(FIX_HW_BRN_27270) 3189#if defined(SGX_FEATURE_MP) && defined(FIX_HW_BRN_27270)
2281 IMG_UINT32 ui32RegVal = 0; 3190 IMG_UINT32 ui32RegVal = 0;
2282#endif 3191#endif
2283 PVRSRV_DEVICE_NODE *psDeviceNode; 3192 PVRSRV_DEVICE_NODE *psDeviceNode;
3193 IMG_HANDLE hDevMemContextInt = 0;
3194 IMG_UINT32 ui32MMUContextID;
2284 IMG_INT ret = -EFAULT; 3195 IMG_INT ret = -EFAULT;
2285 3196
2286 PVR_UNREFERENCED_PARAMETER(psRetOUT); 3197 PVR_UNREFERENCED_PARAMETER(psRetOUT);
@@ -2293,7 +3204,8 @@ SGXPDump3DSignatureRegistersBW(IMG_UINT32 ui32BridgeID,
2293 } 3204 }
2294 3205
2295 psRetOUT->eError = 3206 psRetOUT->eError =
2296 PVRSRVLookupHandle(psPerProc->psHandleBase, (IMG_VOID**)&psDeviceNode, 3207 PVRSRVLookupHandle(psPerProc->psHandleBase,
3208 (IMG_VOID**)&psDeviceNode,
2297 psPDump3DSignatureRegistersIN->hDevCookie, 3209 psPDump3DSignatureRegistersIN->hDevCookie,
2298 PVRSRV_HANDLE_TYPE_DEV_NODE); 3210 PVRSRV_HANDLE_TYPE_DEV_NODE);
2299 if(psRetOUT->eError != PVRSRV_OK) 3211 if(psRetOUT->eError != PVRSRV_OK)
@@ -2339,17 +3251,33 @@ SGXPDump3DSignatureRegistersBW(IMG_UINT32 ui32BridgeID,
2339 pui32Registers, 3251 pui32Registers,
2340 psPDump3DSignatureRegistersIN->ui32NumRegisters); 3252 psPDump3DSignatureRegistersIN->ui32NumRegisters);
2341 3253
3254 psRetOUT->eError =
3255 PVRSRVLookupHandle( psPerProc->psHandleBase,
3256 &hDevMemContextInt,
3257 psPDump3DSignatureRegistersIN->hDevMemContext,
3258 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT);
3259 if(psRetOUT->eError != PVRSRV_OK)
3260 {
3261 return 0;
3262 }
3263
3264
3265 PVR_ASSERT(psDeviceNode->pfnMMUGetContextID != IMG_NULL)
3266 ui32MMUContextID = psDeviceNode->pfnMMUGetContextID(hDevMemContextInt);
3267
2342 PDumpSignatureBuffer(&psDeviceNode->sDevId, 3268 PDumpSignatureBuffer(&psDeviceNode->sDevId,
2343 "out.tasig", "TA", 0, 3269 "out.tasig", "TA", 0,
2344 psDevInfo->psKernelTASigBufferMemInfo->sDevVAddr, 3270 psDevInfo->psKernelTASigBufferMemInfo->sDevVAddr,
2345 psDevInfo->psKernelTASigBufferMemInfo->ui32AllocSize, 3271 (IMG_UINT32)psDevInfo->psKernelTASigBufferMemInfo->uAllocSize,
3272 ui32MMUContextID,
2346 0 ); 3273 0 );
2347 PDumpSignatureBuffer(&psDeviceNode->sDevId, 3274 PDumpSignatureBuffer(&psDeviceNode->sDevId,
2348 "out.3dsig", "3D", 0, 3275 "out.3dsig", "3D", 0,
2349 psDevInfo->psKernel3DSigBufferMemInfo->sDevVAddr, 3276 psDevInfo->psKernel3DSigBufferMemInfo->sDevVAddr,
2350 psDevInfo->psKernel3DSigBufferMemInfo->ui32AllocSize, 3277 (IMG_UINT32)psDevInfo->psKernel3DSigBufferMemInfo->uAllocSize,
3278 ui32MMUContextID,
2351 0 ); 3279 0 );
2352 3280
2353ExitNoError: 3281ExitNoError:
2354 psRetOUT->eError = PVRSRV_OK; 3282 psRetOUT->eError = PVRSRV_OK;
2355 ret = 0; 3283 ret = 0;
@@ -2381,7 +3309,7 @@ SGXPDumpCounterRegistersBW(IMG_UINT32 ui32BridgeID,
2381{ 3309{
2382 IMG_UINT32 ui32RegisterArraySize = psPDumpCounterRegistersIN->ui32NumRegisters * sizeof(IMG_UINT32); 3310 IMG_UINT32 ui32RegisterArraySize = psPDumpCounterRegistersIN->ui32NumRegisters * sizeof(IMG_UINT32);
2383 IMG_UINT32 *pui32Registers = IMG_NULL; 3311 IMG_UINT32 *pui32Registers = IMG_NULL;
2384 PVRSRV_DEVICE_NODE *psDeviceNode; 3312 PVRSRV_DEVICE_NODE *psDeviceNode ;
2385 IMG_INT ret = -EFAULT; 3313 IMG_INT ret = -EFAULT;
2386 3314
2387 PVR_UNREFERENCED_PARAMETER(psBridgeOut); 3315 PVR_UNREFERENCED_PARAMETER(psBridgeOut);
@@ -2393,9 +3321,10 @@ SGXPDumpCounterRegistersBW(IMG_UINT32 ui32BridgeID,
2393 goto ExitNoError; 3321 goto ExitNoError;
2394 } 3322 }
2395 3323
2396 if(PVRSRVLookupHandle(psPerProc->psHandleBase, (IMG_VOID**)&psDeviceNode, 3324 if(PVRSRVLookupHandle(psPerProc->psHandleBase,
2397 psPDumpCounterRegistersIN->hDevCookie, 3325 (IMG_VOID**)&psDeviceNode,
2398 PVRSRV_HANDLE_TYPE_DEV_NODE) != PVRSRV_OK) 3326 psPDumpCounterRegistersIN->hDevCookie,
3327 PVRSRV_HANDLE_TYPE_DEV_NODE) != PVRSRV_OK)
2399 { 3328 {
2400 PVR_DPF((PVR_DBG_ERROR, "SGXPDumpCounterRegistersBW: hDevCookie lookup failed")); 3329 PVR_DPF((PVR_DBG_ERROR, "SGXPDumpCounterRegistersBW: hDevCookie lookup failed"));
2401 ret = -ENOMEM; 3330 ret = -ENOMEM;
@@ -2545,6 +3474,8 @@ SGXPDumpHWPerfCBBW(IMG_UINT32 ui32BridgeID,
2545#if defined(__linux__) 3474#if defined(__linux__)
2546 PVRSRV_SGXDEV_INFO *psDevInfo; 3475 PVRSRV_SGXDEV_INFO *psDevInfo;
2547 PVRSRV_DEVICE_NODE *psDeviceNode; 3476 PVRSRV_DEVICE_NODE *psDeviceNode;
3477 IMG_HANDLE hDevMemContextInt = 0;
3478 IMG_UINT32 ui32MMUContextID = 0;
2548 3479
2549 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_PDUMP_HWPERFCB); 3480 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_PDUMP_HWPERFCB);
2550 3481
@@ -2559,11 +3490,26 @@ SGXPDumpHWPerfCBBW(IMG_UINT32 ui32BridgeID,
2559 3490
2560 psDevInfo = psDeviceNode->pvDevice; 3491 psDevInfo = psDeviceNode->pvDevice;
2561 3492
3493 psRetOUT->eError =
3494 PVRSRVLookupHandle( psPerProc->psHandleBase,
3495 &hDevMemContextInt,
3496 psPDumpHWPerfCBIN->hDevMemContext,
3497 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT);
3498 if(psRetOUT->eError != PVRSRV_OK)
3499 {
3500 return 0;
3501 }
3502
3503
3504 PVR_ASSERT(psDeviceNode->pfnMMUGetContextID != IMG_NULL)
3505 ui32MMUContextID = psDeviceNode->pfnMMUGetContextID(hDevMemContextInt);
3506
2562 PDumpHWPerfCBKM(&psDeviceNode->sDevId, 3507 PDumpHWPerfCBKM(&psDeviceNode->sDevId,
2563 &psPDumpHWPerfCBIN->szFileName[0], 3508 &psPDumpHWPerfCBIN->szFileName[0],
2564 psPDumpHWPerfCBIN->ui32FileOffset, 3509 psPDumpHWPerfCBIN->ui32FileOffset,
2565 psDevInfo->psKernelHWPerfCBMemInfo->sDevVAddr, 3510 psDevInfo->psKernelHWPerfCBMemInfo->sDevVAddr,
2566 psDevInfo->psKernelHWPerfCBMemInfo->ui32AllocSize, 3511 psDevInfo->psKernelHWPerfCBMemInfo->uAllocSize,
3512 ui32MMUContextID,
2567 psPDumpHWPerfCBIN->ui32PDumpFlags); 3513 psPDumpHWPerfCBIN->ui32PDumpFlags);
2568 3514
2569 return 0; 3515 return 0;
@@ -2591,11 +3537,14 @@ SGXPDumpSaveMemBW(IMG_UINT32 ui32BridgeID,
2591 PVRSRV_PER_PROCESS_DATA *psPerProc) 3537 PVRSRV_PER_PROCESS_DATA *psPerProc)
2592{ 3538{
2593 PVRSRV_DEVICE_NODE *psDeviceNode; 3539 PVRSRV_DEVICE_NODE *psDeviceNode;
3540 IMG_HANDLE hDevMemContextInt = 0;
3541 IMG_UINT32 ui32MMUContextID;
2594 3542
2595 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_PDUMP_SAVEMEM); 3543 PVRSRV_BRIDGE_ASSERT_CMD(ui32BridgeID, PVRSRV_BRIDGE_SGX_PDUMP_SAVEMEM);
2596 3544
2597 psRetOUT->eError = 3545 psRetOUT->eError =
2598 PVRSRVLookupHandle(psPerProc->psHandleBase, (IMG_VOID**)&psDeviceNode, 3546 PVRSRVLookupHandle(psPerProc->psHandleBase,
3547 (IMG_VOID**)&psDeviceNode,
2599 psPDumpSaveMem->hDevCookie, 3548 psPDumpSaveMem->hDevCookie,
2600 PVRSRV_HANDLE_TYPE_DEV_NODE); 3549 PVRSRV_HANDLE_TYPE_DEV_NODE);
2601 if(psRetOUT->eError != PVRSRV_OK) 3550 if(psRetOUT->eError != PVRSRV_OK)
@@ -2603,12 +3552,26 @@ SGXPDumpSaveMemBW(IMG_UINT32 ui32BridgeID,
2603 return 0; 3552 return 0;
2604 } 3553 }
2605 3554
3555 psRetOUT->eError =
3556 PVRSRVLookupHandle( psPerProc->psHandleBase,
3557 &hDevMemContextInt,
3558 psPDumpSaveMem->hDevMemContext,
3559 PVRSRV_HANDLE_TYPE_DEV_MEM_CONTEXT);
3560 if(psRetOUT->eError != PVRSRV_OK)
3561 {
3562 return 0;
3563 }
3564
3565
3566 PVR_ASSERT(psDeviceNode->pfnMMUGetContextID != IMG_NULL)
3567 ui32MMUContextID = psDeviceNode->pfnMMUGetContextID(hDevMemContextInt);
3568
2606 PDumpSaveMemKM(&psDeviceNode->sDevId, 3569 PDumpSaveMemKM(&psDeviceNode->sDevId,
2607 &psPDumpSaveMem->szFileName[0], 3570 &psPDumpSaveMem->szFileName[0],
2608 psPDumpSaveMem->ui32FileOffset, 3571 psPDumpSaveMem->ui32FileOffset,
2609 psPDumpSaveMem->sDevVAddr, 3572 psPDumpSaveMem->sDevVAddr,
2610 psPDumpSaveMem->ui32Size, 3573 psPDumpSaveMem->ui32Size,
2611 psPDumpSaveMem->ui32DataMaster, 3574 ui32MMUContextID,
2612 psPDumpSaveMem->ui32PDumpFlags); 3575 psPDumpSaveMem->ui32PDumpFlags);
2613 return 0; 3576 return 0;
2614} 3577}
@@ -2616,7 +3579,7 @@ SGXPDumpSaveMemBW(IMG_UINT32 ui32BridgeID,
2616#endif 3579#endif
2617 3580
2618 3581
2619 3582
2620IMG_VOID SetSGXDispatchTableEntry(IMG_VOID) 3583IMG_VOID SetSGXDispatchTableEntry(IMG_VOID)
2621{ 3584{
2622 3585
diff --git a/drivers/gpu/pvr/sgx/mmu.c b/drivers/gpu/pvr/sgx/mmu.c
index 2685fbf169f..67e86d92025 100644
--- a/drivers/gpu/pvr/sgx/mmu.c
+++ b/drivers/gpu/pvr/sgx/mmu.c
@@ -42,6 +42,38 @@
42 42
43#define SGX_MAX_PD_ENTRIES (1<<(SGX_FEATURE_ADDRESS_SPACE_SIZE - SGX_MMU_PT_SHIFT - SGX_MMU_PAGE_SHIFT)) 43#define SGX_MAX_PD_ENTRIES (1<<(SGX_FEATURE_ADDRESS_SPACE_SIZE - SGX_MMU_PT_SHIFT - SGX_MMU_PAGE_SHIFT))
44 44
45#if defined(FIX_HW_BRN_31620)
46#define SGX_MMU_PDE_DUMMY_PAGE (0)
47#define SGX_MMU_PTE_DUMMY_PAGE (0)
48
49#define BRN31620_PT_ADDRESS_RANGE_SHIFT 22
50#define BRN31620_PT_ADDRESS_RANGE_SIZE (1 << BRN31620_PT_ADDRESS_RANGE_SHIFT)
51
52#define BRN31620_PDE_CACHE_FILL_SHIFT 26
53#define BRN31620_PDE_CACHE_FILL_SIZE (1 << BRN31620_PDE_CACHE_FILL_SHIFT)
54#define BRN31620_PDE_CACHE_FILL_MASK (BRN31620_PDE_CACHE_FILL_SIZE - 1)
55
56#define BRN31620_PDES_PER_CACHE_LINE_SHIFT (BRN31620_PDE_CACHE_FILL_SHIFT - BRN31620_PT_ADDRESS_RANGE_SHIFT)
57#define BRN31620_PDES_PER_CACHE_LINE_SIZE (1 << BRN31620_PDES_PER_CACHE_LINE_SHIFT)
58#define BRN31620_PDES_PER_CACHE_LINE_MASK (BRN31620_PDES_PER_CACHE_LINE_SIZE - 1)
59
60#define BRN31620_DUMMY_PAGE_OFFSET (1 * SGX_MMU_PAGE_SIZE)
61#define BRN31620_DUMMY_PDE_INDEX (BRN31620_DUMMY_PAGE_OFFSET / BRN31620_PT_ADDRESS_RANGE_SIZE)
62#define BRN31620_DUMMY_PTE_INDEX ((BRN31620_DUMMY_PAGE_OFFSET - (BRN31620_DUMMY_PDE_INDEX * BRN31620_PT_ADDRESS_RANGE_SIZE))/SGX_MMU_PAGE_SIZE)
63
64#define BRN31620_CACHE_FLUSH_SHIFT (32 - BRN31620_PDE_CACHE_FILL_SHIFT)
65#define BRN31620_CACHE_FLUSH_SIZE (1 << BRN31620_CACHE_FLUSH_SHIFT)
66
67#define BRN31620_CACHE_FLUSH_BITS_SHIFT 5
68#define BRN31620_CACHE_FLUSH_BITS_SIZE (1 << BRN31620_CACHE_FLUSH_BITS_SHIFT)
69#define BRN31620_CACHE_FLUSH_BITS_MASK (BRN31620_CACHE_FLUSH_BITS_SIZE - 1)
70
71#define BRN31620_CACHE_FLUSH_INDEX_BITS (BRN31620_CACHE_FLUSH_SHIFT - BRN31620_CACHE_FLUSH_BITS_SHIFT)
72#define BRN31620_CACHE_FLUSH_INDEX_SIZE (1 << BRN31620_CACHE_FLUSH_INDEX_BITS)
73
74#define BRN31620_DUMMY_PAGE_SIGNATURE 0xFEEBEE01
75#endif
76
45typedef struct _MMU_PT_INFO_ 77typedef struct _MMU_PT_INFO_
46{ 78{
47 79
@@ -73,6 +105,11 @@ struct _MMU_CONTEXT_
73#endif 105#endif
74#endif 106#endif
75 107
108#if defined (FIX_HW_BRN_31620)
109 IMG_UINT32 ui32PDChangeMask[BRN31620_CACHE_FLUSH_INDEX_SIZE];
110 IMG_UINT32 ui32PDCacheRangeRefCount[BRN31620_CACHE_FLUSH_SIZE];
111 MMU_PT_INFO *apsPTInfoListSave[SGX_MAX_PD_ENTRIES];
112#endif
76 struct _MMU_CONTEXT_ *psNext; 113 struct _MMU_CONTEXT_ *psNext;
77}; 114};
78 115
@@ -88,7 +125,7 @@ struct _MMU_HEAP_
88 125
89 IMG_UINT32 ui32PageTableCount; 126 IMG_UINT32 ui32PageTableCount;
90 127
91 IMG_UINT32 ui32PTETotal; 128 IMG_UINT32 ui32PTETotalUsable;
92 129
93 IMG_UINT32 ui32PDEPageSizeCtrl; 130 IMG_UINT32 ui32PDEPageSizeCtrl;
94 131
@@ -112,7 +149,9 @@ struct _MMU_HEAP_
112 149
113 IMG_UINT32 ui32PTSize; 150 IMG_UINT32 ui32PTSize;
114 151
115 IMG_UINT32 ui32PTECount; 152 IMG_UINT32 ui32PTNumEntriesAllocated;
153
154 IMG_UINT32 ui32PTNumEntriesUsable;
116 155
117 156
118 157
@@ -138,6 +177,9 @@ struct _MMU_HEAP_
138#define DUMMY_DATA_PAGE_SIGNATURE 0xDEADBEEF 177#define DUMMY_DATA_PAGE_SIGNATURE 0xDEADBEEF
139#endif 178#endif
140 179
180static IMG_VOID
181_DeferredFreePageTable (MMU_HEAP *pMMUHeap, IMG_UINT32 ui32PTIndex, IMG_BOOL bOSFreePT);
182
141#if defined(PDUMP) 183#if defined(PDUMP)
142static IMG_VOID 184static IMG_VOID
143MMU_PDumpPageTables (MMU_HEAP *pMMUHeap, 185MMU_PDumpPageTables (MMU_HEAP *pMMUHeap,
@@ -285,6 +327,105 @@ static IMG_VOID MMU_InvalidatePageTableCache(PVRSRV_SGXDEV_INFO *psDevInfo)
285 #endif 327 #endif
286} 328}
287 329
330#if defined(FIX_HW_BRN_31620)
331static IMG_VOID BRN31620InvalidatePageTableEntry(MMU_CONTEXT *psMMUContext, IMG_UINT32 ui32PDIndex, IMG_UINT32 ui32PTIndex, IMG_UINT32 *pui32PTE)
332{
333 PVRSRV_SGXDEV_INFO *psDevInfo = psMMUContext->psDevInfo;
334
335
336 if (((ui32PDIndex % (BRN31620_PDE_CACHE_FILL_SIZE/BRN31620_PT_ADDRESS_RANGE_SIZE)) == BRN31620_DUMMY_PDE_INDEX)
337 && (ui32PTIndex == BRN31620_DUMMY_PTE_INDEX))
338 {
339 *pui32PTE = (psDevInfo->sBRN31620DummyPageDevPAddr.uiAddr>>SGX_MMU_PTE_ADDR_ALIGNSHIFT)
340 | SGX_MMU_PTE_DUMMY_PAGE
341 | SGX_MMU_PTE_READONLY
342 | SGX_MMU_PTE_VALID;
343 }
344 else
345 {
346 *pui32PTE = 0;
347 }
348}
349
350static IMG_BOOL BRN31620FreePageTable(MMU_HEAP *psMMUHeap, IMG_UINT32 ui32PDIndex)
351{
352 MMU_CONTEXT *psMMUContext = psMMUHeap->psMMUContext;
353 PVRSRV_SGXDEV_INFO *psDevInfo = psMMUContext->psDevInfo;
354 IMG_UINT32 ui32PDCacheLine = ui32PDIndex >> BRN31620_PDES_PER_CACHE_LINE_SHIFT;
355 IMG_UINT32 bFreePTs = IMG_FALSE;
356 IMG_UINT32 *pui32Tmp;
357
358 PVR_ASSERT(psMMUHeap != IMG_NULL);
359
360
361 PVR_ASSERT(psMMUContext->apsPTInfoListSave[ui32PDIndex] == IMG_NULL);
362
363 psMMUContext->apsPTInfoListSave[ui32PDIndex] = psMMUContext->apsPTInfoList[ui32PDIndex];
364 psMMUContext->apsPTInfoList[ui32PDIndex] = IMG_NULL;
365
366
367 if (--psMMUContext->ui32PDCacheRangeRefCount[ui32PDCacheLine] == 0)
368 {
369 IMG_UINT32 i;
370 IMG_UINT32 ui32PDIndexStart = ui32PDCacheLine * BRN31620_PDES_PER_CACHE_LINE_SIZE;
371 IMG_UINT32 ui32PDIndexEnd = ui32PDIndexStart + BRN31620_PDES_PER_CACHE_LINE_SIZE;
372 IMG_UINT32 ui32PDBitMaskIndex, ui32PDBitMaskShift;
373
374
375 for (i=ui32PDIndexStart;i<ui32PDIndexEnd;i++)
376 {
377
378 psMMUContext->apsPTInfoList[i] = psMMUContext->apsPTInfoListSave[i];
379 psMMUContext->apsPTInfoListSave[i] = IMG_NULL;
380 _DeferredFreePageTable(psMMUHeap, i - psMMUHeap->ui32PDBaseIndex, IMG_TRUE);
381 }
382
383 ui32PDBitMaskIndex = ui32PDCacheLine >> BRN31620_CACHE_FLUSH_BITS_SHIFT;
384 ui32PDBitMaskShift = ui32PDCacheLine & BRN31620_CACHE_FLUSH_BITS_MASK;
385
386
387 if (MMU_IsHeapShared(psMMUHeap))
388 {
389
390 MMU_CONTEXT *psMMUContextWalker = (MMU_CONTEXT*) psMMUHeap->psMMUContext->psDevInfo->pvMMUContextList;
391
392 while(psMMUContextWalker)
393 {
394 psMMUContextWalker->ui32PDChangeMask[ui32PDBitMaskIndex] |= 1 << ui32PDBitMaskShift;
395
396
397 pui32Tmp = (IMG_UINT32 *) psMMUContextWalker->pvPDCpuVAddr;
398 pui32Tmp[ui32PDIndexStart + BRN31620_DUMMY_PDE_INDEX] = (psDevInfo->sBRN31620DummyPTDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT)
399 | SGX_MMU_PDE_PAGE_SIZE_4K
400 | SGX_MMU_PDE_DUMMY_PAGE
401 | SGX_MMU_PDE_VALID;
402
403 PDUMPCOMMENT("BRN31620 Re-wire dummy PT due to releasing PT allocation block");
404 PDUMPPDENTRIES(&psMMUHeap->sMMUAttrib, psMMUContextWalker->hPDOSMemHandle, (IMG_VOID*)&pui32Tmp[ui32PDIndexStart + BRN31620_DUMMY_PDE_INDEX], sizeof(IMG_UINT32), 0, IMG_FALSE, PDUMP_PT_UNIQUETAG, PDUMP_PT_UNIQUETAG);
405 psMMUContextWalker = psMMUContextWalker->psNext;
406 }
407 }
408 else
409 {
410 psMMUContext->ui32PDChangeMask[ui32PDBitMaskIndex] |= 1 << ui32PDBitMaskShift;
411
412
413 pui32Tmp = (IMG_UINT32 *) psMMUContext->pvPDCpuVAddr;
414 pui32Tmp[ui32PDIndexStart + BRN31620_DUMMY_PDE_INDEX] = (psDevInfo->sBRN31620DummyPTDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT)
415 | SGX_MMU_PDE_PAGE_SIZE_4K
416 | SGX_MMU_PDE_DUMMY_PAGE
417 | SGX_MMU_PDE_VALID;
418
419 PDUMPCOMMENT("BRN31620 Re-wire dummy PT due to releasing PT allocation block");
420 PDUMPPDENTRIES(&psMMUHeap->sMMUAttrib, psMMUContext->hPDOSMemHandle, (IMG_VOID*)&pui32Tmp[ui32PDIndexStart + BRN31620_DUMMY_PDE_INDEX], sizeof(IMG_UINT32), 0, IMG_FALSE, PDUMP_PT_UNIQUETAG, PDUMP_PT_UNIQUETAG);
421 }
422
423 bFreePTs = IMG_TRUE;
424 }
425
426 return bFreePTs;
427}
428#endif
288 429
289static IMG_BOOL 430static IMG_BOOL
290_AllocPageTableMemory (MMU_HEAP *pMMUHeap, 431_AllocPageTableMemory (MMU_HEAP *pMMUHeap,
@@ -373,11 +514,16 @@ _AllocPageTableMemory (MMU_HEAP *pMMUHeap,
373 514
374 pui32Tmp = (IMG_UINT32*)psPTInfoList->PTPageCpuVAddr; 515 pui32Tmp = (IMG_UINT32*)psPTInfoList->PTPageCpuVAddr;
375 516
376 for(i=0; i<pMMUHeap->ui32PTECount; i++) 517 for(i=0; i<pMMUHeap->ui32PTNumEntriesUsable; i++)
377 { 518 {
378 pui32Tmp[i] = (pMMUHeap->psMMUContext->psDevInfo->sDummyDataDevPAddr.uiAddr>>SGX_MMU_PTE_ADDR_ALIGNSHIFT) 519 pui32Tmp[i] = (pMMUHeap->psMMUContext->psDevInfo->sDummyDataDevPAddr.uiAddr>>SGX_MMU_PTE_ADDR_ALIGNSHIFT)
379 | SGX_MMU_PTE_VALID; 520 | SGX_MMU_PTE_VALID;
380 } 521 }
522
523 for(; i<pMMUHeap->ui32PTNumEntriesAllocated; i++)
524 {
525 pui32Tmp[i] = 0;
526 }
381 } 527 }
382#else 528#else
383 529
@@ -388,12 +534,12 @@ _AllocPageTableMemory (MMU_HEAP *pMMUHeap,
388 { 534 {
389 IMG_UINT32 ui32Flags = 0; 535 IMG_UINT32 ui32Flags = 0;
390#if defined(SUPPORT_PDUMP_MULTI_PROCESS) 536#if defined(SUPPORT_PDUMP_MULTI_PROCESS)
391 537
392 ui32Flags |= ( MMU_IsHeapShared(pMMUHeap) ) ? PDUMP_FLAGS_PERSISTENT : 0; 538 ui32Flags |= ( MMU_IsHeapShared(pMMUHeap) ) ? PDUMP_FLAGS_PERSISTENT : 0;
393#endif 539#endif
394 540
395 PDUMPMALLOCPAGETABLE(&pMMUHeap->psMMUContext->psDeviceNode->sDevId, psPTInfoList->hPTPageOSMemHandle, 0, psPTInfoList->PTPageCpuVAddr, pMMUHeap->ui32PTSize, ui32Flags, PDUMP_PT_UNIQUETAG); 541 PDUMPMALLOCPAGETABLE(&pMMUHeap->psMMUContext->psDeviceNode->sDevId, psPTInfoList->hPTPageOSMemHandle, 0, psPTInfoList->PTPageCpuVAddr, pMMUHeap->ui32PTSize, ui32Flags, PDUMP_PT_UNIQUETAG);
396 542
397 PDUMPMEMPTENTRIES(&pMMUHeap->sMMUAttrib, psPTInfoList->hPTPageOSMemHandle, psPTInfoList->PTPageCpuVAddr, pMMUHeap->ui32PTSize, ui32Flags, IMG_TRUE, PDUMP_PT_UNIQUETAG, PDUMP_PT_UNIQUETAG); 543 PDUMPMEMPTENTRIES(&pMMUHeap->sMMUAttrib, psPTInfoList->hPTPageOSMemHandle, psPTInfoList->PTPageCpuVAddr, pMMUHeap->ui32PTSize, ui32Flags, IMG_TRUE, PDUMP_PT_UNIQUETAG, PDUMP_PT_UNIQUETAG);
398 } 544 }
399#endif 545#endif
@@ -482,7 +628,7 @@ _DeferredFreePageTable (MMU_HEAP *pMMUHeap, IMG_UINT32 ui32PTIndex, IMG_BOOL bOS
482#if defined(SUPPORT_PDUMP_MULTI_PROCESS) 628#if defined(SUPPORT_PDUMP_MULTI_PROCESS)
483 ui32Flags |= ( MMU_IsHeapShared(pMMUHeap) ) ? PDUMP_FLAGS_PERSISTENT : 0; 629 ui32Flags |= ( MMU_IsHeapShared(pMMUHeap) ) ? PDUMP_FLAGS_PERSISTENT : 0;
484#endif 630#endif
485 631
486 PDUMPCOMMENT("Free page table (page count == %08X)", pMMUHeap->ui32PageTableCount); 632 PDUMPCOMMENT("Free page table (page count == %08X)", pMMUHeap->ui32PageTableCount);
487 if(ppsPTInfoList[ui32PTIndex] && ppsPTInfoList[ui32PTIndex]->PTPageCpuVAddr) 633 if(ppsPTInfoList[ui32PTIndex] && ppsPTInfoList[ui32PTIndex]->PTPageCpuVAddr)
488 { 634 {
@@ -575,9 +721,10 @@ _DeferredFreePageTable (MMU_HEAP *pMMUHeap, IMG_UINT32 ui32PTIndex, IMG_BOOL bOS
575 721
576 722
577 for(i=0; 723 for(i=0;
578 (i<pMMUHeap->ui32PTETotal) && (i<pMMUHeap->ui32PTECount); 724 (i<pMMUHeap->ui32PTETotalUsable) && (i<pMMUHeap->ui32PTNumEntriesUsable);
579 i++) 725 i++)
580 { 726 {
727
581 pui32Tmp[i] = 0; 728 pui32Tmp[i] = 0;
582 } 729 }
583 730
@@ -591,12 +738,12 @@ _DeferredFreePageTable (MMU_HEAP *pMMUHeap, IMG_UINT32 ui32PTIndex, IMG_BOOL bOS
591 738
592 739
593 740
594 pMMUHeap->ui32PTETotal -= i; 741 pMMUHeap->ui32PTETotalUsable -= i;
595 } 742 }
596 else 743 else
597 { 744 {
598 745
599 pMMUHeap->ui32PTETotal -= pMMUHeap->ui32PTECount; 746 pMMUHeap->ui32PTETotalUsable -= pMMUHeap->ui32PTNumEntriesUsable;
600 } 747 }
601 748
602 if(bOSFreePT) 749 if(bOSFreePT)
@@ -612,7 +759,7 @@ _DeferredFreePageTable (MMU_HEAP *pMMUHeap, IMG_UINT32 ui32PTIndex, IMG_BOOL bOS
612 else 759 else
613 { 760 {
614 761
615 pMMUHeap->ui32PTETotal -= pMMUHeap->ui32PTECount; 762 pMMUHeap->ui32PTETotalUsable -= pMMUHeap->ui32PTNumEntriesUsable;
616 } 763 }
617 764
618 PDUMPCOMMENT("Finished free page table (page count == %08X)", pMMUHeap->ui32PageTableCount); 765 PDUMPCOMMENT("Finished free page table (page count == %08X)", pMMUHeap->ui32PageTableCount);
@@ -622,17 +769,59 @@ static IMG_VOID
622_DeferredFreePageTables (MMU_HEAP *pMMUHeap) 769_DeferredFreePageTables (MMU_HEAP *pMMUHeap)
623{ 770{
624 IMG_UINT32 i; 771 IMG_UINT32 i;
772#if defined(FIX_HW_BRN_31620)
773 MMU_CONTEXT *psMMUContext = pMMUHeap->psMMUContext;
774 IMG_BOOL bInvalidateDirectoryCache = IMG_FALSE;
775 IMG_UINT32 ui32PDIndex;
776 IMG_UINT32 *pui32Tmp;
777 IMG_UINT32 j;
778#endif
625#if defined(PDUMP) 779#if defined(PDUMP)
626 PDUMPCOMMENT("Free PTs (MMU Context ID == %u, PDBaseIndex == %u, PT count == 0x%x)", 780 PDUMPCOMMENT("Free PTs (MMU Context ID == %u, PDBaseIndex == %u, PT count == 0x%x)",
627 pMMUHeap->psMMUContext->ui32PDumpMMUContextID, 781 pMMUHeap->psMMUContext->ui32PDumpMMUContextID,
628 pMMUHeap->ui32PDBaseIndex, 782 pMMUHeap->ui32PDBaseIndex,
629 pMMUHeap->ui32PageTableCount); 783 pMMUHeap->ui32PageTableCount);
630#endif 784#endif
785#if defined(FIX_HW_BRN_31620)
786 for(i=0; i<pMMUHeap->ui32PageTableCount; i++)
787 {
788 ui32PDIndex = (pMMUHeap->ui32PDBaseIndex + i);
789
790 if (psMMUContext->apsPTInfoList[ui32PDIndex])
791 {
792 if (psMMUContext->apsPTInfoList[ui32PDIndex]->PTPageCpuVAddr)
793 {
794
795 for (j=0;j<SGX_MMU_PT_SIZE;j++)
796 {
797 pui32Tmp = (IMG_UINT32 *) psMMUContext->apsPTInfoList[ui32PDIndex]->PTPageCpuVAddr;
798 BRN31620InvalidatePageTableEntry(psMMUContext, ui32PDIndex, j, &pui32Tmp[j]);
799 }
800 }
801
802 if (BRN31620FreePageTable(pMMUHeap, ui32PDIndex) == IMG_TRUE)
803 {
804 bInvalidateDirectoryCache = IMG_TRUE;
805 }
806 }
807 }
808
809
810 if (bInvalidateDirectoryCache)
811 {
812 MMU_InvalidateDirectoryCache(pMMUHeap->psMMUContext->psDevInfo);
813 }
814 else
815 {
816 MMU_InvalidatePageTableCache(pMMUHeap->psMMUContext->psDevInfo);
817 }
818#else
631 for(i=0; i<pMMUHeap->ui32PageTableCount; i++) 819 for(i=0; i<pMMUHeap->ui32PageTableCount; i++)
632 { 820 {
633 _DeferredFreePageTable(pMMUHeap, i, IMG_TRUE); 821 _DeferredFreePageTable(pMMUHeap, i, IMG_TRUE);
634 } 822 }
635 MMU_InvalidateDirectoryCache(pMMUHeap->psMMUContext->psDevInfo); 823 MMU_InvalidateDirectoryCache(pMMUHeap->psMMUContext->psDevInfo);
824#endif
636} 825}
637 826
638 827
@@ -646,6 +835,15 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT
646 MMU_PT_INFO **ppsPTInfoList; 835 MMU_PT_INFO **ppsPTInfoList;
647 SYS_DATA *psSysData; 836 SYS_DATA *psSysData;
648 IMG_DEV_VIRTADDR sHighDevVAddr; 837 IMG_DEV_VIRTADDR sHighDevVAddr;
838#if defined(FIX_HW_BRN_31620)
839 IMG_BOOL bFlushSystemCache = IMG_FALSE;
840 IMG_BOOL bSharedPT = IMG_FALSE;
841 IMG_DEV_VIRTADDR sDevVAddrRequestStart;
842 IMG_DEV_VIRTADDR sDevVAddrRequestEnd;
843 IMG_UINT32 ui32PDRequestStart;
844 IMG_UINT32 ui32PDRequestEnd;
845 IMG_UINT32 ui32ModifiedCachelines[BRN31620_CACHE_FLUSH_INDEX_SIZE];
846#endif
649 847
650 848
651#if SGX_FEATURE_ADDRESS_SPACE_SIZE < 32 849#if SGX_FEATURE_ADDRESS_SPACE_SIZE < 32
@@ -676,6 +874,38 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT
676 874
677 ui32PageTableCount = sHighDevVAddr.uiAddr >> pMMUHeap->ui32PDShift; 875 ui32PageTableCount = sHighDevVAddr.uiAddr >> pMMUHeap->ui32PDShift;
678 876
877
878 if (ui32PageTableCount == 0)
879 ui32PageTableCount = 1024;
880
881#if defined(FIX_HW_BRN_31620)
882 for (i=0;i<BRN31620_CACHE_FLUSH_INDEX_SIZE;i++)
883 {
884 ui32ModifiedCachelines[i] = 0;
885 }
886
887
888
889
890 sDevVAddrRequestStart = DevVAddr;
891 ui32PDRequestStart = ui32PDIndex;
892 sDevVAddrRequestEnd = sHighDevVAddr;
893 ui32PDRequestEnd = ui32PageTableCount - 1;
894
895
896 DevVAddr.uiAddr = DevVAddr.uiAddr & (~BRN31620_PDE_CACHE_FILL_MASK);
897
898
899 sHighDevVAddr.uiAddr = ((sHighDevVAddr.uiAddr + (BRN31620_PDE_CACHE_FILL_SIZE - 1)) & (~BRN31620_PDE_CACHE_FILL_MASK));
900
901 ui32PDIndex = DevVAddr.uiAddr >> pMMUHeap->ui32PDShift;
902 ui32PageTableCount = sHighDevVAddr.uiAddr >> pMMUHeap->ui32PDShift;
903
904
905 if (ui32PageTableCount == 0)
906 ui32PageTableCount = 1024;
907#endif
908
679 ui32PageTableCount -= ui32PDIndex; 909 ui32PageTableCount -= ui32PDIndex;
680 910
681 911
@@ -686,18 +916,45 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT
686 ppsPTInfoList = &pMMUHeap->psMMUContext->apsPTInfoList[ui32PDIndex]; 916 ppsPTInfoList = &pMMUHeap->psMMUContext->apsPTInfoList[ui32PDIndex];
687 917
688#if defined(PDUMP) 918#if defined(PDUMP)
689 PDUMPCOMMENT("Alloc PTs (MMU Context ID == %u, PDBaseIndex == %u, Size == 0x%x)", 919 {
690 pMMUHeap->psMMUContext->ui32PDumpMMUContextID, 920 IMG_UINT32 ui32Flags = 0;
691 pMMUHeap->ui32PDBaseIndex, 921
692 ui32Size); 922
693 PDUMPCOMMENT("Alloc page table (page count == %08X)", ui32PageTableCount); 923 if( MMU_IsHeapShared(pMMUHeap) )
694 PDUMPCOMMENT("Page directory mods (page count == %08X)", ui32PageTableCount); 924 {
925 ui32Flags |= PDUMP_FLAGS_CONTINUOUS;
926 }
927 PDUMPCOMMENTWITHFLAGS(ui32Flags, "Alloc PTs (MMU Context ID == %u, PDBaseIndex == %u, Size == 0x%x)",
928 pMMUHeap->psMMUContext->ui32PDumpMMUContextID,
929 pMMUHeap->ui32PDBaseIndex,
930 ui32Size);
931 PDUMPCOMMENTWITHFLAGS(ui32Flags, "Alloc page table (page count == %08X)", ui32PageTableCount);
932 PDUMPCOMMENTWITHFLAGS(ui32Flags, "Page directory mods (page count == %08X)", ui32PageTableCount);
933 }
695#endif 934#endif
696 935
697 for(i=0; i<ui32PageTableCount; i++) 936 for(i=0; i<ui32PageTableCount; i++)
698 { 937 {
699 if(ppsPTInfoList[i] == IMG_NULL) 938 if(ppsPTInfoList[i] == IMG_NULL)
700 { 939 {
940#if defined(FIX_HW_BRN_31620)
941
942 if (pMMUHeap->psMMUContext->apsPTInfoListSave[ui32PDIndex + i])
943 {
944
945 if (((ui32PDIndex + i) >= ui32PDRequestStart) && ((ui32PDIndex + i) <= ui32PDRequestEnd))
946 {
947 IMG_UINT32 ui32PDCacheLine = (ui32PDIndex + i) >> BRN31620_PDES_PER_CACHE_LINE_SHIFT;
948
949 ppsPTInfoList[i] = pMMUHeap->psMMUContext->apsPTInfoListSave[ui32PDIndex + i];
950 pMMUHeap->psMMUContext->apsPTInfoListSave[ui32PDIndex + i] = IMG_NULL;
951
952 pMMUHeap->psMMUContext->ui32PDCacheRangeRefCount[ui32PDCacheLine]++;
953 }
954 }
955 else
956 {
957#endif
701 OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, 958 OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP,
702 sizeof (MMU_PT_INFO), 959 sizeof (MMU_PT_INFO),
703 (IMG_VOID **)&ppsPTInfoList[i], IMG_NULL, 960 (IMG_VOID **)&ppsPTInfoList[i], IMG_NULL,
@@ -708,8 +965,15 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT
708 return IMG_FALSE; 965 return IMG_FALSE;
709 } 966 }
710 OSMemSet (ppsPTInfoList[i], 0, sizeof(MMU_PT_INFO)); 967 OSMemSet (ppsPTInfoList[i], 0, sizeof(MMU_PT_INFO));
968#if defined(FIX_HW_BRN_31620)
969 }
970#endif
711 } 971 }
712 972#if defined(FIX_HW_BRN_31620)
973
974 if (ppsPTInfoList[i])
975 {
976#endif
713 if(ppsPTInfoList[i]->hPTPageOSMemHandle == IMG_NULL 977 if(ppsPTInfoList[i]->hPTPageOSMemHandle == IMG_NULL
714 && ppsPTInfoList[i]->PTPageCpuVAddr == IMG_NULL) 978 && ppsPTInfoList[i]->PTPageCpuVAddr == IMG_NULL)
715 { 979 {
@@ -718,16 +982,43 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT
718 IMG_UINT32 *pui32Tmp; 982 IMG_UINT32 *pui32Tmp;
719 IMG_UINT32 j; 983 IMG_UINT32 j;
720#else 984#else
985#if !defined(FIX_HW_BRN_31620)
721 986
722 PVR_ASSERT(pui32PDEntry[i] == 0); 987 PVR_ASSERT(pui32PDEntry[i] == 0);
723#endif 988#endif
724 989#endif
725 if(_AllocPageTableMemory (pMMUHeap, ppsPTInfoList[i], &sDevPAddr) != IMG_TRUE) 990 if(_AllocPageTableMemory (pMMUHeap, ppsPTInfoList[i], &sDevPAddr) != IMG_TRUE)
726 { 991 {
727 PVR_DPF((PVR_DBG_ERROR, "_DeferredAllocPagetables: ERROR call to _AllocPageTableMemory failed")); 992 PVR_DPF((PVR_DBG_ERROR, "_DeferredAllocPagetables: ERROR call to _AllocPageTableMemory failed"));
728 return IMG_FALSE; 993 return IMG_FALSE;
729 } 994 }
995#if defined(FIX_HW_BRN_31620)
996 bFlushSystemCache = IMG_TRUE;
997
998 {
999 IMG_UINT32 ui32PD;
1000 IMG_UINT32 ui32PDCacheLine;
1001 IMG_UINT32 ui32PDBitMaskIndex;
1002 IMG_UINT32 ui32PDBitMaskShift;
1003
1004 ui32PD = ui32PDIndex + i;
1005 ui32PDCacheLine = ui32PD >> BRN31620_PDES_PER_CACHE_LINE_SHIFT;
1006 ui32PDBitMaskIndex = ui32PDCacheLine >> BRN31620_CACHE_FLUSH_BITS_SHIFT;
1007 ui32PDBitMaskShift = ui32PDCacheLine & BRN31620_CACHE_FLUSH_BITS_MASK;
1008 ui32ModifiedCachelines[ui32PDBitMaskIndex] |= 1 << ui32PDBitMaskShift;
1009
1010
1011 if ((pMMUHeap->ui32PDBaseIndex + pMMUHeap->ui32PageTableCount) < (ui32PD + 1))
1012 {
1013 pMMUHeap->ui32PageTableCount = (ui32PD + 1) - pMMUHeap->ui32PDBaseIndex;
1014 }
730 1015
1016 if (((ui32PDIndex + i) >= ui32PDRequestStart) && ((ui32PDIndex + i) <= ui32PDRequestEnd))
1017 {
1018 pMMUHeap->psMMUContext->ui32PDCacheRangeRefCount[ui32PDCacheLine]++;
1019 }
1020 }
1021#endif
731 switch(pMMUHeap->psDevArena->DevMemHeapType) 1022 switch(pMMUHeap->psDevArena->DevMemHeapType)
732 { 1023 {
733 case DEVICE_MEMORY_HEAP_SHARED : 1024 case DEVICE_MEMORY_HEAP_SHARED :
@@ -746,21 +1037,22 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT
746 pui32PDEntry[i] = (sDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT) 1037 pui32PDEntry[i] = (sDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT)
747 | pMMUHeap->ui32PDEPageSizeCtrl 1038 | pMMUHeap->ui32PDEPageSizeCtrl
748 | SGX_MMU_PDE_VALID; 1039 | SGX_MMU_PDE_VALID;
749
750 #if defined(PDUMP) 1040 #if defined(PDUMP)
751 1041
752 #if defined(SUPPORT_PDUMP_MULTI_PROCESS) 1042 #if defined(SUPPORT_PDUMP_MULTI_PROCESS)
753 if(psMMUContext->bPDumpActive) 1043 if(psMMUContext->bPDumpActive)
754 #endif 1044 #endif
755 { 1045 {
756 1046
757 PDUMPPDENTRIES(&pMMUHeap->sMMUAttrib, psMMUContext->hPDOSMemHandle, (IMG_VOID*)&pui32PDEntry[i], sizeof(IMG_UINT32), 0, IMG_FALSE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG); 1047 PDUMPPDENTRIES(&pMMUHeap->sMMUAttrib, psMMUContext->hPDOSMemHandle, (IMG_VOID*)&pui32PDEntry[i], sizeof(IMG_UINT32), 0, IMG_FALSE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG);
758 } 1048 }
759 #endif 1049 #endif
760
761 1050
762 psMMUContext = psMMUContext->psNext; 1051 psMMUContext = psMMUContext->psNext;
763 } 1052 }
1053#if defined(FIX_HW_BRN_31620)
1054 bSharedPT = IMG_TRUE;
1055#endif
764 break; 1056 break;
765 } 1057 }
766 case DEVICE_MEMORY_HEAP_PERCONTEXT : 1058 case DEVICE_MEMORY_HEAP_PERCONTEXT :
@@ -772,6 +1064,7 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT
772 | SGX_MMU_PDE_VALID; 1064 | SGX_MMU_PDE_VALID;
773 1065
774 1066
1067
775 PDUMPPDENTRIES(&pMMUHeap->sMMUAttrib, pMMUHeap->psMMUContext->hPDOSMemHandle, (IMG_VOID*)&pui32PDEntry[i], sizeof(IMG_UINT32), 0, IMG_FALSE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG); 1068 PDUMPPDENTRIES(&pMMUHeap->sMMUAttrib, pMMUHeap->psMMUContext->hPDOSMemHandle, (IMG_VOID*)&pui32PDEntry[i], sizeof(IMG_UINT32), 0, IMG_FALSE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG);
776 break; 1069 break;
777 } 1070 }
@@ -789,17 +1082,112 @@ _DeferredAllocPagetables(MMU_HEAP *pMMUHeap, IMG_DEV_VIRTADDR DevVAddr, IMG_UINT
789 1082
790 MMU_InvalidateDirectoryCache(pMMUHeap->psMMUContext->psDevInfo); 1083 MMU_InvalidateDirectoryCache(pMMUHeap->psMMUContext->psDevInfo);
791#endif 1084#endif
1085#if defined(FIX_HW_BRN_31620)
1086
1087 if (((ui32PDIndex + i) < ui32PDRequestStart) || ((ui32PDIndex + i) > ui32PDRequestEnd))
1088 {
1089 pMMUHeap->psMMUContext->apsPTInfoListSave[ui32PDIndex + i] = ppsPTInfoList[i];
1090 ppsPTInfoList[i] = IMG_NULL;
1091 }
1092#endif
792 } 1093 }
793 else 1094 else
794 { 1095 {
1096#if !defined(FIX_HW_BRN_31620)
795 1097
796 PVR_ASSERT(pui32PDEntry[i] != 0); 1098 PVR_ASSERT(pui32PDEntry[i] != 0);
1099#endif
797 } 1100 }
1101#if defined(FIX_HW_BRN_31620)
1102 }
1103#endif
798 } 1104 }
799 1105
800 #if defined(SGX_FEATURE_SYSTEM_CACHE) 1106 #if defined(SGX_FEATURE_SYSTEM_CACHE)
1107 #if defined(FIX_HW_BRN_31620)
1108
1109 if (bFlushSystemCache)
1110 {
1111 #endif
1112
801 MMU_InvalidateSystemLevelCache(pMMUHeap->psMMUContext->psDevInfo); 1113 MMU_InvalidateSystemLevelCache(pMMUHeap->psMMUContext->psDevInfo);
802 #endif 1114 #endif
1115 #if defined(FIX_HW_BRN_31620)
1116 }
1117
1118
1119 sHighDevVAddr.uiAddr = sHighDevVAddr.uiAddr - 1;
1120
1121
1122 if (bFlushSystemCache)
1123 {
1124 MMU_CONTEXT *psMMUContext;
1125
1126 if (bSharedPT)
1127 {
1128 MMU_CONTEXT *psMMUContext = (MMU_CONTEXT*)pMMUHeap->psMMUContext->psDevInfo->pvMMUContextList;
1129
1130 while(psMMUContext)
1131 {
1132 for (i=0;i<BRN31620_CACHE_FLUSH_INDEX_SIZE;i++)
1133 {
1134 psMMUContext->ui32PDChangeMask[i] |= ui32ModifiedCachelines[i];
1135 }
1136
1137
1138 psMMUContext = psMMUContext->psNext;
1139 }
1140 }
1141 else
1142 {
1143 for (i=0;i<BRN31620_CACHE_FLUSH_INDEX_SIZE;i++)
1144 {
1145 pMMUHeap->psMMUContext->ui32PDChangeMask[i] |= ui32ModifiedCachelines[i];
1146 }
1147 }
1148
1149
1150 psMMUContext = pMMUHeap->psMMUContext;
1151 for (i=0;i<BRN31620_CACHE_FLUSH_INDEX_SIZE;i++)
1152 {
1153 IMG_UINT32 j;
1154
1155 for(j=0;j<BRN31620_CACHE_FLUSH_BITS_SIZE;j++)
1156 {
1157 if (ui32ModifiedCachelines[i] & (1 << j))
1158 {
1159 PVRSRV_SGXDEV_INFO *psDevInfo = psMMUContext->psDevInfo;
1160 MMU_PT_INFO *psTempPTInfo = IMG_NULL;
1161 IMG_UINT32 *pui32Tmp;
1162
1163 ui32PDIndex = (((i * BRN31620_CACHE_FLUSH_BITS_SIZE) + j) * BRN31620_PDES_PER_CACHE_LINE_SIZE) + BRN31620_DUMMY_PDE_INDEX;
1164
1165
1166 if (psMMUContext->apsPTInfoList[ui32PDIndex])
1167 {
1168 psTempPTInfo = psMMUContext->apsPTInfoList[ui32PDIndex];
1169 }
1170 else
1171 {
1172 psTempPTInfo = psMMUContext->apsPTInfoListSave[ui32PDIndex];
1173 }
1174
1175 PVR_ASSERT(psTempPTInfo != IMG_NULL);
1176
1177 pui32Tmp = (IMG_UINT32 *) psTempPTInfo->PTPageCpuVAddr;
1178 PVR_ASSERT(pui32Tmp != IMG_NULL);
1179 pui32Tmp[BRN31620_DUMMY_PTE_INDEX] = (psDevInfo->sBRN31620DummyPageDevPAddr.uiAddr>>SGX_MMU_PTE_ADDR_ALIGNSHIFT)
1180 | SGX_MMU_PTE_DUMMY_PAGE
1181 | SGX_MMU_PTE_READONLY
1182 | SGX_MMU_PTE_VALID;
1183
1184 PDUMPCOMMENT("BRN31620 Dump PTE for dummy page after wireing up new PT");
1185 PDUMPMEMPTENTRIES(&pMMUHeap->sMMUAttrib, psTempPTInfo->hPTPageOSMemHandle, (IMG_VOID *) &pui32Tmp[BRN31620_DUMMY_PTE_INDEX], sizeof(IMG_UINT32), 0, IMG_FALSE, PDUMP_PT_UNIQUETAG, PDUMP_PT_UNIQUETAG);
1186 }
1187 }
1188 }
1189 }
1190 #endif
803 1191
804 return IMG_TRUE; 1192 return IMG_TRUE;
805} 1193}
@@ -810,6 +1198,7 @@ IMG_UINT32 MMU_GetPDumpContextID(IMG_HANDLE hDevMemContext)
810{ 1198{
811 BM_CONTEXT *pBMContext = hDevMemContext; 1199 BM_CONTEXT *pBMContext = hDevMemContext;
812 PVR_ASSERT(pBMContext); 1200 PVR_ASSERT(pBMContext);
1201
813 return pBMContext->psMMUContext->ui32PDumpMMUContextID; 1202 return pBMContext->psMMUContext->ui32PDumpMMUContextID;
814} 1203}
815 1204
@@ -956,6 +1345,69 @@ MMU_Initialise (PVRSRV_DEVICE_NODE *psDeviceNode, MMU_CONTEXT **ppsMMUContext, I
956 psDevInfo->sDummyDataDevPAddr = SysCpuPAddrToDevPAddr (PVRSRV_DEVICE_TYPE_SGX, sCpuPAddr); 1345 psDevInfo->sDummyDataDevPAddr = SysCpuPAddrToDevPAddr (PVRSRV_DEVICE_TYPE_SGX, sCpuPAddr);
957 } 1346 }
958#endif 1347#endif
1348#if defined(FIX_HW_BRN_31620)
1349
1350 if(!psDevInfo->pvMMUContextList)
1351 {
1352 IMG_UINT32 j;
1353
1354 if (OSAllocPages(PVRSRV_HAP_WRITECOMBINE | PVRSRV_HAP_KERNEL_ONLY,
1355 SGX_MMU_PAGE_SIZE,
1356 SGX_MMU_PAGE_SIZE,
1357 &psDevInfo->pvBRN31620DummyPageCpuVAddr,
1358 &psDevInfo->hBRN31620DummyPageOSMemHandle) != PVRSRV_OK)
1359 {
1360 PVR_DPF((PVR_DBG_ERROR, "MMU_Initialise: ERROR call to OSAllocPages failed"));
1361 return PVRSRV_ERROR_FAILED_TO_ALLOC_PAGES;
1362 }
1363
1364
1365 if(psDevInfo->pvBRN31620DummyPageCpuVAddr)
1366 {
1367 sCpuPAddr = OSMapLinToCPUPhys(psDevInfo->hBRN31620DummyPageOSMemHandle,
1368 psDevInfo->pvBRN31620DummyPageCpuVAddr);
1369 }
1370 else
1371 {
1372 sCpuPAddr = OSMemHandleToCpuPAddr(psDevInfo->hBRN31620DummyPageOSMemHandle, 0);
1373 }
1374
1375 pui32Tmp = (IMG_UINT32 *)psDevInfo->pvBRN31620DummyPageCpuVAddr;
1376 for(j=0; j<(SGX_MMU_PAGE_SIZE/4); j++)
1377 {
1378 pui32Tmp[j] = BRN31620_DUMMY_PAGE_SIGNATURE;
1379 }
1380
1381 psDevInfo->sBRN31620DummyPageDevPAddr = SysCpuPAddrToDevPAddr(PVRSRV_DEVICE_TYPE_SGX, sCpuPAddr);
1382 PDUMPMALLOCPAGETABLE(&psDeviceNode->sDevId, psDevInfo->hBRN31620DummyPageOSMemHandle, 0, psDevInfo->pvBRN31620DummyPageCpuVAddr, SGX_MMU_PAGE_SIZE, 0, PDUMP_PT_UNIQUETAG);
1383
1384
1385 if (OSAllocPages(PVRSRV_HAP_WRITECOMBINE | PVRSRV_HAP_KERNEL_ONLY,
1386 SGX_MMU_PAGE_SIZE,
1387 SGX_MMU_PAGE_SIZE,
1388 &psDevInfo->pvBRN31620DummyPTCpuVAddr,
1389 &psDevInfo->hBRN31620DummyPTOSMemHandle) != PVRSRV_OK)
1390 {
1391 PVR_DPF((PVR_DBG_ERROR, "MMU_Initialise: ERROR call to OSAllocPages failed"));
1392 return PVRSRV_ERROR_FAILED_TO_ALLOC_PAGES;
1393 }
1394
1395
1396 if(psDevInfo->pvBRN31620DummyPTCpuVAddr)
1397 {
1398 sCpuPAddr = OSMapLinToCPUPhys(psDevInfo->hBRN31620DummyPTOSMemHandle,
1399 psDevInfo->pvBRN31620DummyPTCpuVAddr);
1400 }
1401 else
1402 {
1403 sCpuPAddr = OSMemHandleToCpuPAddr(psDevInfo->hBRN31620DummyPTOSMemHandle, 0);
1404 }
1405
1406 OSMemSet(psDevInfo->pvBRN31620DummyPTCpuVAddr,0,SGX_MMU_PAGE_SIZE);
1407 psDevInfo->sBRN31620DummyPTDevPAddr = SysCpuPAddrToDevPAddr(PVRSRV_DEVICE_TYPE_SGX, sCpuPAddr);
1408 PDUMPMALLOCPAGETABLE(&psDeviceNode->sDevId, psDevInfo->hBRN31620DummyPTOSMemHandle, 0, psDevInfo->pvBRN31620DummyPTCpuVAddr, SGX_MMU_PAGE_SIZE, 0, PDUMP_PT_UNIQUETAG);
1409 }
1410#endif
959 } 1411 }
960 else 1412 else
961 { 1413 {
@@ -1051,16 +1503,96 @@ MMU_Initialise (PVRSRV_DEVICE_NODE *psDeviceNode, MMU_CONTEXT **ppsMMUContext, I
1051 } 1503 }
1052 } 1504 }
1053#endif 1505#endif
1506#if defined(FIX_HW_BRN_31620)
1507
1508 if(!psDevInfo->pvMMUContextList)
1509 {
1510 IMG_UINT32 j;
1511
1512 if(RA_Alloc(psDeviceNode->psLocalDevMemArena,
1513 SGX_MMU_PAGE_SIZE,
1514 IMG_NULL,
1515 IMG_NULL,
1516 0,
1517 SGX_MMU_PAGE_SIZE,
1518 0,
1519 &(sSysPAddr.uiAddr))!= IMG_TRUE)
1520 {
1521 PVR_DPF((PVR_DBG_ERROR, "MMU_Initialise: ERROR call to RA_Alloc failed"));
1522 return PVRSRV_ERROR_FAILED_TO_ALLOC_VIRT_MEMORY;
1523 }
1524
1525
1526 sCpuPAddr = SysSysPAddrToCpuPAddr(sSysPAddr);
1527 psDevInfo->sBRN31620DummyPageDevPAddr = SysSysPAddrToDevPAddr(PVRSRV_DEVICE_TYPE_SGX, sSysPAddr);
1528 psDevInfo->pvBRN31620DummyPageCpuVAddr = OSMapPhysToLin(sCpuPAddr,
1529 SGX_MMU_PAGE_SIZE,
1530 PVRSRV_HAP_WRITECOMBINE|PVRSRV_HAP_KERNEL_ONLY,
1531 &psDevInfo->hBRN31620DummyPageOSMemHandle);
1532 if(!psDevInfo->pvBRN31620DummyPageCpuVAddr)
1533 {
1534 PVR_DPF((PVR_DBG_ERROR, "MMU_Initialise: ERROR failed to map page tables"));
1535 return PVRSRV_ERROR_FAILED_TO_MAP_PAGE_TABLE;
1536 }
1537
1538 pui32Tmp = (IMG_UINT32 *)psDevInfo->pvBRN31620DummyPageCpuVAddr;
1539 for(j=0; j<(SGX_MMU_PAGE_SIZE/4); j++)
1540 {
1541 pui32Tmp[j] = BRN31620_DUMMY_PAGE_SIGNATURE;
1542 }
1543 PDUMPMALLOCPAGETABLE(&psDeviceNode->sDevId, psDevInfo->hBRN31620DummyPageOSMemHandle, 0, psDevInfo->pvBRN31620DummyPageCpuVAddr, SGX_MMU_PAGE_SIZE, 0, PDUMP_PT_UNIQUETAG);
1544
1545
1546 if(RA_Alloc(psDeviceNode->psLocalDevMemArena,
1547 SGX_MMU_PAGE_SIZE,
1548 IMG_NULL,
1549 IMG_NULL,
1550 0,
1551 SGX_MMU_PAGE_SIZE,
1552 0,
1553 &(sSysPAddr.uiAddr))!= IMG_TRUE)
1554 {
1555 PVR_DPF((PVR_DBG_ERROR, "MMU_Initialise: ERROR call to RA_Alloc failed"));
1556 return PVRSRV_ERROR_FAILED_TO_ALLOC_VIRT_MEMORY;
1557 }
1558
1559
1560 sCpuPAddr = SysSysPAddrToCpuPAddr(sSysPAddr);
1561 psDevInfo->sBRN31620DummyPTDevPAddr = SysSysPAddrToDevPAddr(PVRSRV_DEVICE_TYPE_SGX, sSysPAddr);
1562 psDevInfo->pvBRN31620DummyPTCpuVAddr = OSMapPhysToLin(sCpuPAddr,
1563 SGX_MMU_PAGE_SIZE,
1564 PVRSRV_HAP_WRITECOMBINE|PVRSRV_HAP_KERNEL_ONLY,
1565 &psDevInfo->hBRN31620DummyPTOSMemHandle);
1566
1567 if(!psDevInfo->pvBRN31620DummyPTCpuVAddr)
1568 {
1569 PVR_DPF((PVR_DBG_ERROR, "MMU_Initialise: ERROR failed to map page tables"));
1570 return PVRSRV_ERROR_FAILED_TO_MAP_PAGE_TABLE;
1571 }
1572
1573 OSMemSet(psDevInfo->pvBRN31620DummyPTCpuVAddr,0,SGX_MMU_PAGE_SIZE);
1574 PDUMPMALLOCPAGETABLE(&psDeviceNode->sDevId, psDevInfo->hBRN31620DummyPTOSMemHandle, 0, psDevInfo->pvBRN31620DummyPTCpuVAddr, SGX_MMU_PAGE_SIZE, 0, PDUMP_PT_UNIQUETAG);
1575 }
1576#endif
1577 }
1578
1579#if defined(FIX_HW_BRN_31620)
1580 if (!psDevInfo->pvMMUContextList)
1581 {
1582
1583 psDevInfo->hKernelMMUContext = psMMUContext;
1584 PVR_DPF((PVR_DBG_ERROR, "MMU_Initialise: saving kernel mmu context: %p", psMMUContext));
1054 } 1585 }
1586#endif
1055 1587
1056#if defined(PDUMP) 1588#if defined(PDUMP)
1057#if defined(SUPPORT_PDUMP_MULTI_PROCESS) 1589#if defined(SUPPORT_PDUMP_MULTI_PROCESS)
1058 1590
1059 { 1591 {
1060 PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData(); 1592 PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData();
1061 if(psPerProc == IMG_NULL) 1593 if(psPerProc == IMG_NULL)
1062 { 1594 {
1063 1595
1064 psMMUContext->bPDumpActive = IMG_TRUE; 1596 psMMUContext->bPDumpActive = IMG_TRUE;
1065 } 1597 }
1066 else 1598 else
@@ -1068,7 +1600,7 @@ MMU_Initialise (PVRSRV_DEVICE_NODE *psDeviceNode, MMU_CONTEXT **ppsMMUContext, I
1068 psMMUContext->bPDumpActive = psPerProc->bPDumpActive; 1600 psMMUContext->bPDumpActive = psPerProc->bPDumpActive;
1069 } 1601 }
1070 } 1602 }
1071#endif 1603#endif
1072 1604
1073#if IMG_ADDRSPACE_PHYSADDR_BITS == 32 1605#if IMG_ADDRSPACE_PHYSADDR_BITS == 32
1074 PDUMPCOMMENT("Alloc page directory for new MMU context (PDDevPAddr == 0x%08x)", 1606 PDUMPCOMMENT("Alloc page directory for new MMU context (PDDevPAddr == 0x%08x)",
@@ -1079,6 +1611,7 @@ MMU_Initialise (PVRSRV_DEVICE_NODE *psDeviceNode, MMU_CONTEXT **ppsMMUContext, I
1079#endif 1611#endif
1080 PDUMPMALLOCPAGETABLE(&psDeviceNode->sDevId, hPDOSMemHandle, 0, pvPDCpuVAddr, SGX_MMU_PAGE_SIZE, 0, PDUMP_PD_UNIQUETAG); 1612 PDUMPMALLOCPAGETABLE(&psDeviceNode->sDevId, hPDOSMemHandle, 0, pvPDCpuVAddr, SGX_MMU_PAGE_SIZE, 0, PDUMP_PD_UNIQUETAG);
1081#endif 1613#endif
1614
1082#ifdef SUPPORT_SGX_MMU_BYPASS 1615#ifdef SUPPORT_SGX_MMU_BYPASS
1083 EnableHostAccess(psMMUContext); 1616 EnableHostAccess(psMMUContext);
1084#endif 1617#endif
@@ -1093,6 +1626,7 @@ MMU_Initialise (PVRSRV_DEVICE_NODE *psDeviceNode, MMU_CONTEXT **ppsMMUContext, I
1093 return PVRSRV_ERROR_INVALID_CPU_ADDR; 1626 return PVRSRV_ERROR_INVALID_CPU_ADDR;
1094 } 1627 }
1095 1628
1629
1096#if defined(SUPPORT_SGX_MMU_DUMMY_PAGE) 1630#if defined(SUPPORT_SGX_MMU_DUMMY_PAGE)
1097 1631
1098 for(i=0; i<SGX_MMU_PD_SIZE; i++) 1632 for(i=0; i<SGX_MMU_PD_SIZE; i++)
@@ -1140,13 +1674,71 @@ MMU_Initialise (PVRSRV_DEVICE_NODE *psDeviceNode, MMU_CONTEXT **ppsMMUContext, I
1140#if defined(PDUMP) 1674#if defined(PDUMP)
1141#if defined(SUPPORT_PDUMP_MULTI_PROCESS) 1675#if defined(SUPPORT_PDUMP_MULTI_PROCESS)
1142 if(psMMUContext->bPDumpActive) 1676 if(psMMUContext->bPDumpActive)
1143#endif 1677#endif
1144 { 1678 {
1145 1679
1146 PDUMPCOMMENT("Page directory contents"); 1680 PDUMPCOMMENT("Page directory contents");
1147 PDUMPPDENTRIES(&sMMUAttrib, hPDOSMemHandle, pvPDCpuVAddr, SGX_MMU_PAGE_SIZE, 0, IMG_TRUE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG); 1681 PDUMPPDENTRIES(&sMMUAttrib, hPDOSMemHandle, pvPDCpuVAddr, SGX_MMU_PAGE_SIZE, 0, IMG_TRUE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG);
1148 } 1682 }
1149 1683#endif
1684#if defined(FIX_HW_BRN_31620)
1685 {
1686 IMG_UINT32 i;
1687 IMG_UINT32 ui32PDCount = 0;
1688 IMG_UINT32 *pui32PT;
1689 pui32Tmp = (IMG_UINT32 *)pvPDCpuVAddr;
1690
1691 PDUMPCOMMENT("BRN31620 Set up dummy PT");
1692
1693 pui32PT = (IMG_UINT32 *) psDevInfo->pvBRN31620DummyPTCpuVAddr;
1694 pui32PT[BRN31620_DUMMY_PTE_INDEX] = (psDevInfo->sBRN31620DummyPageDevPAddr.uiAddr>>SGX_MMU_PTE_ADDR_ALIGNSHIFT)
1695 | SGX_MMU_PTE_DUMMY_PAGE
1696 | SGX_MMU_PTE_READONLY
1697 | SGX_MMU_PTE_VALID;
1698
1699
1700#if defined(PDUMP)
1701
1702 PDUMPCOMMENT("BRN31620 Dump dummy PT contents");
1703 PDUMPMEMPTENTRIES(&sMMUAttrib, psDevInfo->hBRN31620DummyPTOSMemHandle, psDevInfo->pvBRN31620DummyPTCpuVAddr, SGX_MMU_PAGE_SIZE, 0, IMG_TRUE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG);
1704 PDUMPCOMMENT("BRN31620 Dump dummy page contents");
1705 PDUMPMEMPTENTRIES(&sMMUAttrib, psDevInfo->hBRN31620DummyPageOSMemHandle, psDevInfo->pvBRN31620DummyPageCpuVAddr, SGX_MMU_PAGE_SIZE, 0, IMG_TRUE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG);
1706
1707
1708 for(i=0;i<SGX_MMU_PT_SIZE;i++)
1709 {
1710 PDUMPMEMPTENTRIES(&sMMUAttrib, psDevInfo->hBRN31620DummyPTOSMemHandle, &pui32PT[i], sizeof(IMG_UINT32), 0, IMG_FALSE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG);
1711 }
1712#endif
1713 PDUMPCOMMENT("BRN31620 Dump PDE wire up");
1714
1715 for(i=0;i<SGX_MMU_PD_SIZE;i++)
1716 {
1717 pui32Tmp[i] = 0;
1718
1719 if (ui32PDCount == BRN31620_DUMMY_PDE_INDEX)
1720 {
1721 pui32Tmp[i] = (psDevInfo->sBRN31620DummyPTDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT)
1722 | SGX_MMU_PDE_PAGE_SIZE_4K
1723 | SGX_MMU_PDE_DUMMY_PAGE
1724 | SGX_MMU_PDE_VALID;
1725 }
1726 PDUMPMEMPTENTRIES(&sMMUAttrib, hPDOSMemHandle, (IMG_VOID *) &pui32Tmp[i], sizeof(IMG_UINT32), 0, IMG_FALSE, PDUMP_PT_UNIQUETAG, PDUMP_PT_UNIQUETAG);
1727 ui32PDCount++;
1728 if (ui32PDCount == BRN31620_PDES_PER_CACHE_LINE_SIZE)
1729 {
1730
1731 ui32PDCount = 0;
1732 }
1733 }
1734
1735
1736
1737 PDUMPCOMMENT("BRN31620 dummy Page table contents");
1738 PDUMPMEMPTENTRIES(&sMMUAttrib, psDevInfo->hBRN31620DummyPageOSMemHandle, psDevInfo->pvBRN31620DummyPageCpuVAddr, SGX_MMU_PAGE_SIZE, 0, IMG_TRUE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG);
1739 }
1740#endif
1741#if defined(PDUMP)
1150 1742
1151 { 1743 {
1152 PVRSRV_ERROR eError; 1744 PVRSRV_ERROR eError;
@@ -1179,6 +1771,22 @@ MMU_Initialise (PVRSRV_DEVICE_NODE *psDeviceNode, MMU_CONTEXT **ppsMMUContext, I
1179 PDUMPCOMMENT("Set MMU context complete (MMU Context ID == %u)", psMMUContext->ui32PDumpMMUContextID); 1771 PDUMPCOMMENT("Set MMU context complete (MMU Context ID == %u)", psMMUContext->ui32PDumpMMUContextID);
1180#endif 1772#endif
1181 1773
1774#if defined(FIX_HW_BRN_31620)
1775 for(i=0;i<BRN31620_CACHE_FLUSH_INDEX_SIZE;i++)
1776 {
1777 psMMUContext->ui32PDChangeMask[i] = 0;
1778 }
1779
1780 for(i=0;i<BRN31620_CACHE_FLUSH_SIZE;i++)
1781 {
1782 psMMUContext->ui32PDCacheRangeRefCount[i] = 0;
1783 }
1784
1785 for(i=0;i<SGX_MAX_PD_ENTRIES;i++)
1786 {
1787 psMMUContext->apsPTInfoListSave[i] = IMG_NULL;
1788 }
1789#endif
1182 1790
1183 psMMUContext->pvPDCpuVAddr = pvPDCpuVAddr; 1791 psMMUContext->pvPDCpuVAddr = pvPDCpuVAddr;
1184 psMMUContext->sPDDevPAddr = sPDDevPAddr; 1792 psMMUContext->sPDDevPAddr = sPDDevPAddr;
@@ -1207,7 +1815,7 @@ MMU_Finalise (MMU_CONTEXT *psMMUContext)
1207 IMG_UINT32 *pui32Tmp, i; 1815 IMG_UINT32 *pui32Tmp, i;
1208 SYS_DATA *psSysData; 1816 SYS_DATA *psSysData;
1209 MMU_CONTEXT **ppsMMUContext; 1817 MMU_CONTEXT **ppsMMUContext;
1210#if defined(SUPPORT_SGX_MMU_DUMMY_PAGE) 1818#if defined(SUPPORT_SGX_MMU_DUMMY_PAGE) || defined(FIX_HW_BRN_31620)
1211 PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO*)psMMUContext->psDevInfo; 1819 PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO*)psMMUContext->psDevInfo;
1212 MMU_CONTEXT *psMMUContextList = (MMU_CONTEXT*)psDevInfo->pvMMUContextList; 1820 MMU_CONTEXT *psMMUContextList = (MMU_CONTEXT*)psDevInfo->pvMMUContextList;
1213#endif 1821#endif
@@ -1250,11 +1858,32 @@ MMU_Finalise (MMU_CONTEXT *psMMUContext)
1250 1858
1251 if(psMMUContext->psDeviceNode->psLocalDevMemArena == IMG_NULL) 1859 if(psMMUContext->psDeviceNode->psLocalDevMemArena == IMG_NULL)
1252 { 1860 {
1861#if defined(FIX_HW_BRN_31620)
1862 PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO*)psMMUContext->psDevInfo;
1863#endif
1253 OSFreePages(PVRSRV_HAP_WRITECOMBINE | PVRSRV_HAP_KERNEL_ONLY, 1864 OSFreePages(PVRSRV_HAP_WRITECOMBINE | PVRSRV_HAP_KERNEL_ONLY,
1254 SGX_MMU_PAGE_SIZE, 1865 SGX_MMU_PAGE_SIZE,
1255 psMMUContext->pvPDCpuVAddr, 1866 psMMUContext->pvPDCpuVAddr,
1256 psMMUContext->hPDOSMemHandle); 1867 psMMUContext->hPDOSMemHandle);
1257 1868
1869#if defined(FIX_HW_BRN_31620)
1870
1871 if (!psMMUContextList->psNext)
1872 {
1873 PDUMPFREEPAGETABLE(&psMMUContext->psDeviceNode->sDevId, psDevInfo->hBRN31620DummyPageOSMemHandle, psDevInfo->pvBRN31620DummyPageCpuVAddr, SGX_MMU_PAGE_SIZE, 0, PDUMP_PT_UNIQUETAG);
1874 OSFreePages(PVRSRV_HAP_WRITECOMBINE | PVRSRV_HAP_KERNEL_ONLY,
1875 SGX_MMU_PAGE_SIZE,
1876 psDevInfo->pvBRN31620DummyPageCpuVAddr,
1877 psDevInfo->hBRN31620DummyPageOSMemHandle);
1878
1879 PDUMPFREEPAGETABLE(&psMMUContext->psDeviceNode->sDevId, psDevInfo->hBRN31620DummyPTOSMemHandle, psDevInfo->pvBRN31620DummyPTCpuVAddr, SGX_MMU_PAGE_SIZE, 0, PDUMP_PT_UNIQUETAG);
1880 OSFreePages(PVRSRV_HAP_WRITECOMBINE | PVRSRV_HAP_KERNEL_ONLY,
1881 SGX_MMU_PAGE_SIZE,
1882 psDevInfo->pvBRN31620DummyPTCpuVAddr,
1883 psDevInfo->hBRN31620DummyPTOSMemHandle);
1884
1885 }
1886#endif
1258#if defined(SUPPORT_SGX_MMU_DUMMY_PAGE) 1887#if defined(SUPPORT_SGX_MMU_DUMMY_PAGE)
1259 1888
1260 if(!psMMUContextList->psNext) 1889 if(!psMMUContextList->psNext)
@@ -1319,6 +1948,41 @@ MMU_Finalise (MMU_CONTEXT *psMMUContext)
1319 RA_Free (psMMUContext->psDeviceNode->psLocalDevMemArena, sSysPAddr.uiAddr, IMG_FALSE); 1948 RA_Free (psMMUContext->psDeviceNode->psLocalDevMemArena, sSysPAddr.uiAddr, IMG_FALSE);
1320 } 1949 }
1321#endif 1950#endif
1951#if defined(FIX_HW_BRN_31620)
1952
1953 if(!psMMUContextList->psNext)
1954 {
1955
1956 PDUMPFREEPAGETABLE(&psMMUContext->psDeviceNode->sDevId, psDevInfo->hBRN31620DummyPageOSMemHandle, psDevInfo->pvBRN31620DummyPageCpuVAddr, SGX_MMU_PAGE_SIZE, 0, PDUMP_PT_UNIQUETAG);
1957
1958 sCpuPAddr = OSMapLinToCPUPhys(psDevInfo->hBRN31620DummyPageOSMemHandle,
1959 psDevInfo->pvBRN31620DummyPageCpuVAddr);
1960 sSysPAddr = SysCpuPAddrToSysPAddr(sCpuPAddr);
1961
1962
1963 OSUnMapPhysToLin(psDevInfo->pvBRN31620DummyPageCpuVAddr,
1964 SGX_MMU_PAGE_SIZE,
1965 PVRSRV_HAP_WRITECOMBINE|PVRSRV_HAP_KERNEL_ONLY,
1966 psDevInfo->hBRN31620DummyPageOSMemHandle);
1967
1968 RA_Free (psMMUContext->psDeviceNode->psLocalDevMemArena, sSysPAddr.uiAddr, IMG_FALSE);
1969
1970
1971 PDUMPFREEPAGETABLE(&psMMUContext->psDeviceNode->sDevId, psDevInfo->hBRN31620DummyPTOSMemHandle, psDevInfo->pvBRN31620DummyPTCpuVAddr, SGX_MMU_PAGE_SIZE, 0, PDUMP_PT_UNIQUETAG);
1972
1973 sCpuPAddr = OSMapLinToCPUPhys(psDevInfo->hBRN31620DummyPTOSMemHandle,
1974 psDevInfo->pvBRN31620DummyPTCpuVAddr);
1975 sSysPAddr = SysCpuPAddrToSysPAddr(sCpuPAddr);
1976
1977
1978 OSUnMapPhysToLin(psDevInfo->pvBRN31620DummyPTCpuVAddr,
1979 SGX_MMU_PAGE_SIZE,
1980 PVRSRV_HAP_WRITECOMBINE|PVRSRV_HAP_KERNEL_ONLY,
1981 psDevInfo->hBRN31620DummyPTOSMemHandle);
1982
1983 RA_Free (psMMUContext->psDeviceNode->psLocalDevMemArena, sSysPAddr.uiAddr, IMG_FALSE);
1984 }
1985#endif
1322 } 1986 }
1323 1987
1324 PVR_DPF ((PVR_DBG_MESSAGE, "MMU_Finalise")); 1988 PVR_DPF ((PVR_DBG_MESSAGE, "MMU_Finalise"));
@@ -1374,7 +2038,7 @@ MMU_InsertHeap(MMU_CONTEXT *psMMUContext, MMU_HEAP *psMMUHeap)
1374 2038
1375 for (ui32PDEntry = 0; ui32PDEntry < psMMUHeap->ui32PageTableCount; ui32PDEntry++) 2039 for (ui32PDEntry = 0; ui32PDEntry < psMMUHeap->ui32PageTableCount; ui32PDEntry++)
1376 { 2040 {
1377#if !defined(SUPPORT_SGX_MMU_DUMMY_PAGE) 2041#if (!defined(SUPPORT_SGX_MMU_DUMMY_PAGE)) && (!defined(FIX_HW_BRN_31620))
1378 2042
1379 PVR_ASSERT(pui32PDCpuVAddr[ui32PDEntry] == 0); 2043 PVR_ASSERT(pui32PDCpuVAddr[ui32PDEntry] == 0);
1380#endif 2044#endif
@@ -1383,12 +2047,12 @@ MMU_InsertHeap(MMU_CONTEXT *psMMUContext, MMU_HEAP *psMMUHeap)
1383 pui32PDCpuVAddr[ui32PDEntry] = pui32KernelPDCpuVAddr[ui32PDEntry]; 2047 pui32PDCpuVAddr[ui32PDEntry] = pui32KernelPDCpuVAddr[ui32PDEntry];
1384 if (pui32PDCpuVAddr[ui32PDEntry]) 2048 if (pui32PDCpuVAddr[ui32PDEntry])
1385 { 2049 {
1386 2050
1387 #if defined(PDUMP) 2051 #if defined(PDUMP)
1388 2052
1389 #if defined(SUPPORT_PDUMP_MULTI_PROCESS) 2053 #if defined(SUPPORT_PDUMP_MULTI_PROCESS)
1390 if(psMMUContext->bPDumpActive) 2054 if(psMMUContext->bPDumpActive)
1391 #endif 2055 #endif
1392 { 2056 {
1393 PDUMPPDENTRIES(&psMMUHeap->sMMUAttrib, psMMUContext->hPDOSMemHandle, (IMG_VOID *) &pui32PDCpuVAddr[ui32PDEntry], sizeof(IMG_UINT32), 0, IMG_FALSE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG); 2057 PDUMPPDENTRIES(&psMMUHeap->sMMUAttrib, psMMUContext->hPDOSMemHandle, (IMG_VOID *) &pui32PDCpuVAddr[ui32PDEntry], sizeof(IMG_UINT32), 0, IMG_FALSE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG);
1394 } 2058 }
@@ -1491,8 +2155,12 @@ MMU_UnmapPagesAndFreePTs (MMU_HEAP *psMMUHeap,
1491 | SGX_MMU_PTE_VALID; 2155 | SGX_MMU_PTE_VALID;
1492#else 2156#else
1493 2157
2158#if defined(FIX_HW_BRN_31620)
2159 BRN31620InvalidatePageTableEntry(psMMUHeap->psMMUContext, ui32PDIndex, ui32PTIndex, &pui32Tmp[ui32PTIndex]);
2160#else
1494 pui32Tmp[ui32PTIndex] = 0; 2161 pui32Tmp[ui32PTIndex] = 0;
1495#endif 2162#endif
2163#endif
1496 2164
1497 CheckPT(ppsPTInfoList[0]); 2165 CheckPT(ppsPTInfoList[0]);
1498 } 2166 }
@@ -1501,8 +2169,15 @@ MMU_UnmapPagesAndFreePTs (MMU_HEAP *psMMUHeap,
1501 2169
1502 if (ppsPTInfoList[0] && ppsPTInfoList[0]->ui32ValidPTECount == 0) 2170 if (ppsPTInfoList[0] && ppsPTInfoList[0]->ui32ValidPTECount == 0)
1503 { 2171 {
2172#if defined(FIX_HW_BRN_31620)
2173 if (BRN31620FreePageTable(psMMUHeap, ui32PDIndex) == IMG_TRUE)
2174 {
2175 bInvalidateDirectoryCache = IMG_TRUE;
2176 }
2177#else
1504 _DeferredFreePageTable(psMMUHeap, ui32PDIndex - psMMUHeap->ui32PDBaseIndex, IMG_TRUE); 2178 _DeferredFreePageTable(psMMUHeap, ui32PDIndex - psMMUHeap->ui32PDBaseIndex, IMG_TRUE);
1505 bInvalidateDirectoryCache = IMG_TRUE; 2179 bInvalidateDirectoryCache = IMG_TRUE;
2180#endif
1506 } 2181 }
1507 2182
1508 2183
@@ -1536,9 +2211,9 @@ static IMG_VOID MMU_FreePageTables(IMG_PVOID pvMMUHeap,
1536 MMU_HEAP *pMMUHeap = (MMU_HEAP*)pvMMUHeap; 2211 MMU_HEAP *pMMUHeap = (MMU_HEAP*)pvMMUHeap;
1537 IMG_DEV_VIRTADDR Start; 2212 IMG_DEV_VIRTADDR Start;
1538 2213
1539 Start.uiAddr = ui32Start; 2214 Start.uiAddr = (IMG_UINT32)ui32Start;
1540 2215
1541 MMU_UnmapPagesAndFreePTs(pMMUHeap, Start, (ui32End - ui32Start) >> pMMUHeap->ui32PTShift, hUniqueTag); 2216 MMU_UnmapPagesAndFreePTs(pMMUHeap, Start, (IMG_UINT32)((ui32End - ui32Start) >> pMMUHeap->ui32PTShift), hUniqueTag);
1542} 2217}
1543 2218
1544MMU_HEAP * 2219MMU_HEAP *
@@ -1618,12 +2293,16 @@ MMU_Create (MMU_CONTEXT *psMMUContext,
1618 pMMUHeap->ui32PTBitWidth = SGX_MMU_PT_SHIFT - ui32ScaleSize; 2293 pMMUHeap->ui32PTBitWidth = SGX_MMU_PT_SHIFT - ui32ScaleSize;
1619 pMMUHeap->ui32PTMask = SGX_MMU_PT_MASK & (SGX_MMU_PT_MASK<<ui32ScaleSize); 2294 pMMUHeap->ui32PTMask = SGX_MMU_PT_MASK & (SGX_MMU_PT_MASK<<ui32ScaleSize);
1620 pMMUHeap->ui32PTSize = (IMG_UINT32)(1UL<<pMMUHeap->ui32PTBitWidth) * sizeof(IMG_UINT32); 2295 pMMUHeap->ui32PTSize = (IMG_UINT32)(1UL<<pMMUHeap->ui32PTBitWidth) * sizeof(IMG_UINT32);
2296
1621 2297
1622 if(pMMUHeap->ui32PTSize < 4 * sizeof(IMG_UINT32)) 2298 if(pMMUHeap->ui32PTSize < 4 * sizeof(IMG_UINT32))
1623 { 2299 {
1624 pMMUHeap->ui32PTSize = 4 * sizeof(IMG_UINT32); 2300 pMMUHeap->ui32PTSize = 4 * sizeof(IMG_UINT32);
1625 } 2301 }
1626 pMMUHeap->ui32PTECount = pMMUHeap->ui32PTSize >> 2; 2302 pMMUHeap->ui32PTNumEntriesAllocated = pMMUHeap->ui32PTSize >> 2;
2303
2304
2305 pMMUHeap->ui32PTNumEntriesUsable = (IMG_UINT32)(1UL << pMMUHeap->ui32PTBitWidth);
1627 2306
1628 2307
1629 pMMUHeap->ui32PDShift = pMMUHeap->ui32PTBitWidth + pMMUHeap->ui32PTShift; 2308 pMMUHeap->ui32PDShift = pMMUHeap->ui32PTBitWidth + pMMUHeap->ui32PTShift;
@@ -1645,7 +2324,7 @@ MMU_Create (MMU_CONTEXT *psMMUContext,
1645 } 2324 }
1646 2325
1647 2326
1648 pMMUHeap->ui32PTETotal = pMMUHeap->psDevArena->ui32Size >> pMMUHeap->ui32PTShift; 2327 pMMUHeap->ui32PTETotalUsable = pMMUHeap->psDevArena->ui32Size >> pMMUHeap->ui32PTShift;
1649 2328
1650 2329
1651 pMMUHeap->ui32PDBaseIndex = (pMMUHeap->psDevArena->BaseDevVAddr.uiAddr & pMMUHeap->ui32PDMask) >> pMMUHeap->ui32PDShift; 2330 pMMUHeap->ui32PDBaseIndex = (pMMUHeap->psDevArena->BaseDevVAddr.uiAddr & pMMUHeap->ui32PDMask) >> pMMUHeap->ui32PDShift;
@@ -1653,8 +2332,9 @@ MMU_Create (MMU_CONTEXT *psMMUContext,
1653 2332
1654 2333
1655 2334
1656 pMMUHeap->ui32PageTableCount = (pMMUHeap->ui32PTETotal + pMMUHeap->ui32PTECount - 1) 2335 pMMUHeap->ui32PageTableCount = (pMMUHeap->ui32PTETotalUsable + pMMUHeap->ui32PTNumEntriesUsable - 1)
1657 >> pMMUHeap->ui32PTBitWidth; 2336 >> pMMUHeap->ui32PTBitWidth;
2337 PVR_ASSERT(pMMUHeap->ui32PageTableCount > 0);
1658 2338
1659 2339
1660 pMMUHeap->psVMArena = RA_Create(psDevArena->pszName, 2340 pMMUHeap->psVMArena = RA_Create(psDevArena->pszName,
@@ -1808,7 +2488,7 @@ MMU_Alloc (MMU_HEAP *pMMUHeap,
1808 #endif 2488 #endif
1809 2489
1810 2490
1811 bStatus = _DeferredAllocPagetables(pMMUHeap, *psDevVAddr, uSize); 2491 bStatus = _DeferredAllocPagetables(pMMUHeap, *psDevVAddr, (IMG_UINT32)uSize);
1812 2492
1813 #ifdef SUPPORT_SGX_MMU_BYPASS 2493 #ifdef SUPPORT_SGX_MMU_BYPASS
1814 DisableHostAccess(pMMUHeap->psMMUContext); 2494 DisableHostAccess(pMMUHeap->psMMUContext);
@@ -1874,6 +2554,26 @@ MMU_Disable (MMU_HEAP *pMMUHeap)
1874 2554
1875} 2555}
1876 2556
2557#if defined(FIX_HW_BRN_31620)
2558IMG_VOID MMU_GetCacheFlushRange(MMU_CONTEXT *pMMUContext, IMG_UINT32 *pui32RangeMask)
2559{
2560 IMG_UINT32 i;
2561
2562 for (i=0;i<BRN31620_CACHE_FLUSH_INDEX_SIZE;i++)
2563 {
2564 pui32RangeMask[i] = pMMUContext->ui32PDChangeMask[i];
2565
2566
2567 pMMUContext->ui32PDChangeMask[i] = 0;
2568 }
2569}
2570
2571IMG_VOID MMU_GetPDPhysAddr(MMU_CONTEXT *pMMUContext, IMG_DEV_PHYADDR *psDevPAddr)
2572{
2573 *psDevPAddr = pMMUContext->sPDDevPAddr;
2574}
2575
2576#endif
1877#if defined(PDUMP) 2577#if defined(PDUMP)
1878static IMG_VOID 2578static IMG_VOID
1879MMU_PDumpPageTables (MMU_HEAP *pMMUHeap, 2579MMU_PDumpPageTables (MMU_HEAP *pMMUHeap,
@@ -1891,7 +2591,7 @@ MMU_PDumpPageTables (MMU_HEAP *pMMUHeap,
1891 IMG_UINT32 ui32PTDumpCount; 2591 IMG_UINT32 ui32PTDumpCount;
1892 2592
1893 2593
1894 ui32NumPTEntries = (uSize + pMMUHeap->ui32DataPageMask) >> pMMUHeap->ui32PTShift; 2594 ui32NumPTEntries = (IMG_UINT32)((uSize + pMMUHeap->ui32DataPageMask) >> pMMUHeap->ui32PTShift);
1895 2595
1896 2596
1897 ui32PDIndex = DevVAddr.uiAddr >> pMMUHeap->ui32PDShift; 2597 ui32PDIndex = DevVAddr.uiAddr >> pMMUHeap->ui32PDShift;
@@ -1910,13 +2610,13 @@ MMU_PDumpPageTables (MMU_HEAP *pMMUHeap,
1910 { 2610 {
1911 MMU_PT_INFO* psPTInfo = *ppsPTInfoList++; 2611 MMU_PT_INFO* psPTInfo = *ppsPTInfoList++;
1912 2612
1913 if(ui32NumPTEntries <= pMMUHeap->ui32PTECount - ui32PTIndex) 2613 if(ui32NumPTEntries <= pMMUHeap->ui32PTNumEntriesUsable - ui32PTIndex)
1914 { 2614 {
1915 ui32PTDumpCount = ui32NumPTEntries; 2615 ui32PTDumpCount = ui32NumPTEntries;
1916 } 2616 }
1917 else 2617 else
1918 { 2618 {
1919 ui32PTDumpCount = pMMUHeap->ui32PTECount - ui32PTIndex; 2619 ui32PTDumpCount = pMMUHeap->ui32PTNumEntriesUsable - ui32PTIndex;
1920 } 2620 }
1921 2621
1922 if (psPTInfo) 2622 if (psPTInfo)
@@ -2009,7 +2709,12 @@ MMU_MapPage (MMU_HEAP *pMMUHeap,
2009 IMG_UINT32 uTmp = pui32Tmp[ui32Index]; 2709 IMG_UINT32 uTmp = pui32Tmp[ui32Index];
2010 2710
2011 2711
2012 if (uTmp & SGX_MMU_PTE_VALID) 2712#if defined(FIX_HW_BRN_31620)
2713 if ((uTmp & SGX_MMU_PTE_VALID) && ((DevVAddr.uiAddr & BRN31620_PDE_CACHE_FILL_MASK) != BRN31620_DUMMY_PAGE_OFFSET))
2714#else
2715 if ((uTmp & SGX_MMU_PTE_VALID) != 0)
2716#endif
2717
2013 { 2718 {
2014 PVR_DPF((PVR_DBG_ERROR, "MMU_MapPage: Page is already valid for alloc at VAddr:0x%08X PDIdx:%u PTIdx:%u", 2719 PVR_DPF((PVR_DBG_ERROR, "MMU_MapPage: Page is already valid for alloc at VAddr:0x%08X PDIdx:%u PTIdx:%u",
2015 DevVAddr.uiAddr, 2720 DevVAddr.uiAddr,
@@ -2018,8 +2723,9 @@ MMU_MapPage (MMU_HEAP *pMMUHeap,
2018 PVR_DPF((PVR_DBG_ERROR, "MMU_MapPage: Page table entry value: 0x%08X", uTmp)); 2723 PVR_DPF((PVR_DBG_ERROR, "MMU_MapPage: Page table entry value: 0x%08X", uTmp));
2019 PVR_DPF((PVR_DBG_ERROR, "MMU_MapPage: Physical page to map: 0x%08X", DevPAddr.uiAddr)); 2724 PVR_DPF((PVR_DBG_ERROR, "MMU_MapPage: Physical page to map: 0x%08X", DevPAddr.uiAddr));
2020 } 2725 }
2021 2726#if !defined(FIX_HW_BRN_31620)
2022 PVR_ASSERT((uTmp & SGX_MMU_PTE_VALID) == 0); 2727 PVR_ASSERT((uTmp & SGX_MMU_PTE_VALID) == 0);
2728#endif
2023 } 2729 }
2024#endif 2730#endif
2025 2731
@@ -2322,8 +3028,12 @@ MMU_UnmapPages (MMU_HEAP *psMMUHeap,
2322 | SGX_MMU_PTE_VALID; 3028 | SGX_MMU_PTE_VALID;
2323#else 3029#else
2324 3030
3031#if defined(FIX_HW_BRN_31620)
3032 BRN31620InvalidatePageTableEntry(psMMUHeap->psMMUContext, ui32PDIndex, ui32PTIndex, &pui32Tmp[ui32PTIndex]);
3033#else
2325 pui32Tmp[ui32PTIndex] = 0; 3034 pui32Tmp[ui32PTIndex] = 0;
2326#endif 3035#endif
3036#endif
2327 3037
2328 CheckPT(ppsPTInfoList[0]); 3038 CheckPT(ppsPTInfoList[0]);
2329 3039
@@ -2906,9 +3616,9 @@ PVRSRV_ERROR MMU_MapExtSystemCacheRegs(PVRSRV_DEVICE_NODE *psDeviceNode)
2906 | SGX_MMU_PTE_VALID; 3616 | SGX_MMU_PTE_VALID;
2907 3617
2908 3618
2909 PDUMPMALLOCPAGETABLE(&psDeviceNode->sDevID, hPTPageOSMemHandle, 0, pui32PT, SGX_MMU_PAGE_SIZE, 0, PDUMP_PT_UNIQUETAG); 3619 PDUMPMALLOCPAGETABLE(&psDeviceNode->sDevId, hPTPageOSMemHandle, 0, pui32PT, SGX_MMU_PAGE_SIZE, 0, PDUMP_PT_UNIQUETAG);
2910 PDUMPMEMPTENTRIES(PVRSRV_DEVICE_TYPE_SGX, hPDPageOSMemHandle, pui32PD, SGX_MMU_PAGE_SIZE, 0, IMG_TRUE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG); 3620 PDUMPMEMPTENTRIES(&psDevInfo->sMMUAttrib, psDeviceNode->sDevMemoryInfo.pBMKernelContext->psMMUContext->hPDOSMemHandle, pui32PD, SGX_MMU_PAGE_SIZE, 0, IMG_TRUE, PDUMP_PD_UNIQUETAG, PDUMP_PT_UNIQUETAG);
2911 PDUMPMEMPTENTRIES(PVRSRV_DEVICE_TYPE_SGX, hPTPageOSMemHandle, pui32PT, SGX_MMU_PAGE_SIZE, 0, IMG_TRUE, PDUMP_PT_UNIQUETAG, PDUMP_PD_UNIQUETAG); 3621 PDUMPMEMPTENTRIES(&psDevInfo->sMMUAttrib, hPTPageOSMemHandle, pui32PT, SGX_MMU_PAGE_SIZE, 0, IMG_TRUE, PDUMP_PT_UNIQUETAG, PDUMP_PD_UNIQUETAG);
2912 3622
2913 3623
2914 psDevInfo->pui32ExtSystemCacheRegsPT = pui32PT; 3624 psDevInfo->pui32ExtSystemCacheRegsPT = pui32PT;
diff --git a/drivers/gpu/pvr/sgx/mmu.h b/drivers/gpu/pvr/sgx/mmu.h
index 80e3122a438..3c471a4994f 100644
--- a/drivers/gpu/pvr/sgx/mmu.h
+++ b/drivers/gpu/pvr/sgx/mmu.h
@@ -78,7 +78,7 @@ MMU_MapPages (MMU_HEAP *pMMUHeap,
78IMG_VOID 78IMG_VOID
79MMU_MapShadow (MMU_HEAP * pMMUHeap, 79MMU_MapShadow (MMU_HEAP * pMMUHeap,
80 IMG_DEV_VIRTADDR MapBaseDevVAddr, 80 IMG_DEV_VIRTADDR MapBaseDevVAddr,
81 IMG_SIZE_T uByteSize, 81 IMG_SIZE_T uByteSize,
82 IMG_CPU_VIRTADDR CpuVAddr, 82 IMG_CPU_VIRTADDR CpuVAddr,
83 IMG_HANDLE hOSMemHandle, 83 IMG_HANDLE hOSMemHandle,
84 IMG_DEV_VIRTADDR * pDevVAddr, 84 IMG_DEV_VIRTADDR * pDevVAddr,
@@ -139,6 +139,12 @@ PVRSRV_ERROR MMU_UnmapExtSystemCacheRegs(PVRSRV_DEVICE_NODE *psDeviceNode);
139 139
140IMG_BOOL MMU_IsHeapShared(MMU_HEAP* pMMU_Heap); 140IMG_BOOL MMU_IsHeapShared(MMU_HEAP* pMMU_Heap);
141 141
142#if defined(FIX_HW_BRN_31620)
143IMG_VOID MMU_GetCacheFlushRange(MMU_CONTEXT *pMMUContext, IMG_UINT32 *pui32RangeMask);
144
145IMG_VOID MMU_GetPDPhysAddr(MMU_CONTEXT *pMMUContext, IMG_DEV_PHYADDR *psDevPAddr);
146
147#endif
142#if defined(PDUMP) 148#if defined(PDUMP)
143IMG_UINT32 MMU_GetPDumpContextID(IMG_HANDLE hDevMemContext); 149IMG_UINT32 MMU_GetPDumpContextID(IMG_HANDLE hDevMemContext);
144#endif 150#endif
diff --git a/drivers/gpu/pvr/sgx/pb.c b/drivers/gpu/pvr/sgx/pb.c
index f9e8b19a70a..b2ba005d008 100644
--- a/drivers/gpu/pvr/sgx/pb.c
+++ b/drivers/gpu/pvr/sgx/pb.c
@@ -185,6 +185,7 @@ SGXCleanupSharedPBDescKM(PVRSRV_STUB_PBDESC *psStubPBDescIn)
185 psStubPBDescIn->ui32RefCount--; 185 psStubPBDescIn->ui32RefCount--;
186 if (psStubPBDescIn->ui32RefCount == 0) 186 if (psStubPBDescIn->ui32RefCount == 0)
187 { 187 {
188 IMG_DEV_VIRTADDR sHWPBDescDevVAddr = psStubPBDescIn->sHWPBDescDevVAddr;
188 List_PVRSRV_STUB_PBDESC_Remove(psStubPBDescIn); 189 List_PVRSRV_STUB_PBDESC_Remove(psStubPBDescIn);
189 for(i=0 ; i<psStubPBDescIn->ui32SubKernelMemInfosCount; i++) 190 for(i=0 ; i<psStubPBDescIn->ui32SubKernelMemInfosCount; i++)
190 { 191 {
@@ -215,7 +216,7 @@ SGXCleanupSharedPBDescKM(PVRSRV_STUB_PBDESC *psStubPBDescIn)
215 216
216 217
217 SGXCleanupRequest(psDeviceNode, 218 SGXCleanupRequest(psDeviceNode,
218 IMG_NULL, 219 &sHWPBDescDevVAddr,
219 PVRSRV_CLEANUPCMD_PB); 220 PVRSRV_CLEANUPCMD_PB);
220 } 221 }
221 return PVRSRV_OK; 222 return PVRSRV_OK;
@@ -268,7 +269,8 @@ SGXAddSharedPBDescKM(PVRSRV_PER_PROCESS_DATA *psPerProc,
268 IMG_UINT32 ui32TotalPBSize, 269 IMG_UINT32 ui32TotalPBSize,
269 IMG_HANDLE *phSharedPBDesc, 270 IMG_HANDLE *phSharedPBDesc,
270 PVRSRV_KERNEL_MEM_INFO **ppsSharedPBDescSubKernelMemInfos, 271 PVRSRV_KERNEL_MEM_INFO **ppsSharedPBDescSubKernelMemInfos,
271 IMG_UINT32 ui32SharedPBDescSubKernelMemInfosCount) 272 IMG_UINT32 ui32SharedPBDescSubKernelMemInfosCount,
273 IMG_DEV_VIRTADDR sHWPBDescDevVAddr)
272{ 274{
273 PVRSRV_STUB_PBDESC *psStubPBDesc=IMG_NULL; 275 PVRSRV_STUB_PBDESC *psStubPBDesc=IMG_NULL;
274 PVRSRV_ERROR eRet = PVRSRV_ERROR_INVALID_PERPROC; 276 PVRSRV_ERROR eRet = PVRSRV_ERROR_INVALID_PERPROC;
@@ -402,6 +404,8 @@ SGXAddSharedPBDescKM(PVRSRV_PER_PROCESS_DATA *psPerProc,
402 } 404 }
403 } 405 }
404 406
407 psStubPBDesc->sHWPBDescDevVAddr = sHWPBDescDevVAddr;
408
405 psResItem = ResManRegisterRes(psPerProc->hResManContext, 409 psResItem = ResManRegisterRes(psPerProc->hResManContext,
406 RESMAN_TYPE_SHARED_PB_DESC, 410 RESMAN_TYPE_SHARED_PB_DESC,
407 psStubPBDesc, 411 psStubPBDesc,
diff --git a/drivers/gpu/pvr/sgx/sgx_bridge_km.h b/drivers/gpu/pvr/sgx/sgx_bridge_km.h
index 7738be13f38..7a14024f4ad 100644
--- a/drivers/gpu/pvr/sgx/sgx_bridge_km.h
+++ b/drivers/gpu/pvr/sgx/sgx_bridge_km.h
@@ -39,16 +39,28 @@ extern "C" {
39#endif 39#endif
40 40
41IMG_IMPORT 41IMG_IMPORT
42#if defined (SUPPORT_SID_INTERFACE)
43PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSFER_SGX_KICK_KM *psKick);
44#else
42PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSFER_SGX_KICK *psKick); 45PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSFER_SGX_KICK *psKick);
46#endif
43 47
44#if defined(SGX_FEATURE_2D_HARDWARE) 48#if defined(SGX_FEATURE_2D_HARDWARE)
45IMG_IMPORT 49IMG_IMPORT
50#if defined (SUPPORT_SID_INTERFACE)
51PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK_KM *psKick);
52#else
46PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK *psKick); 53PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK *psKick);
47#endif 54#endif
55#endif
48 56
49IMG_IMPORT 57IMG_IMPORT
50PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, 58PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle,
59#if defined (SUPPORT_SID_INTERFACE)
60 SGX_CCB_KICK_KM *psCCBKick);
61#else
51 SGX_CCB_KICK *psCCBKick); 62 SGX_CCB_KICK *psCCBKick);
63#endif
52 64
53IMG_IMPORT 65IMG_IMPORT
54PVRSRV_ERROR SGXGetPhysPageAddrKM(IMG_HANDLE hDevMemHeap, 66PVRSRV_ERROR SGXGetPhysPageAddrKM(IMG_HANDLE hDevMemHeap,
@@ -86,12 +98,21 @@ PVRSRV_ERROR SGX2DQueryBlitsCompleteKM(PVRSRV_SGXDEV_INFO *psDevInfo,
86 98
87IMG_IMPORT 99IMG_IMPORT
88PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, 100PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle,
101#if defined (SUPPORT_SID_INTERFACE)
102 PVRSRV_HEAP_INFO_KM *pasHeapInfo,
103 IMG_DEV_PHYADDR *psPDDevPAddr);
104#else
89 SGX_BRIDGE_INFO_FOR_SRVINIT *psInitInfo); 105 SGX_BRIDGE_INFO_FOR_SRVINIT *psInitInfo);
106#endif
90 107
91IMG_IMPORT 108IMG_IMPORT
92PVRSRV_ERROR DevInitSGXPart2KM(PVRSRV_PER_PROCESS_DATA *psPerProc, 109PVRSRV_ERROR DevInitSGXPart2KM(PVRSRV_PER_PROCESS_DATA *psPerProc,
93 IMG_HANDLE hDevHandle, 110 IMG_HANDLE hDevHandle,
111#if defined (SUPPORT_SID_INTERFACE)
112 SGX_BRIDGE_INIT_INFO_KM *psInitInfo);
113#else
94 SGX_BRIDGE_INIT_INFO *psInitInfo); 114 SGX_BRIDGE_INIT_INFO *psInitInfo);
115#endif
95 116
96IMG_IMPORT PVRSRV_ERROR 117IMG_IMPORT PVRSRV_ERROR
97SGXFindSharedPBDescKM(PVRSRV_PER_PROCESS_DATA *psPerProc, 118SGXFindSharedPBDescKM(PVRSRV_PER_PROCESS_DATA *psPerProc,
@@ -119,12 +140,17 @@ SGXAddSharedPBDescKM(PVRSRV_PER_PROCESS_DATA *psPerProc,
119 IMG_UINT32 ui32TotalPBSize, 140 IMG_UINT32 ui32TotalPBSize,
120 IMG_HANDLE *phSharedPBDesc, 141 IMG_HANDLE *phSharedPBDesc,
121 PVRSRV_KERNEL_MEM_INFO **psSharedPBDescSubKernelMemInfos, 142 PVRSRV_KERNEL_MEM_INFO **psSharedPBDescSubKernelMemInfos,
122 IMG_UINT32 ui32SharedPBDescSubKernelMemInfosCount); 143 IMG_UINT32 ui32SharedPBDescSubKernelMemInfosCount,
144 IMG_DEV_VIRTADDR sHWPBDescDevVAddr);
123 145
124 146
125IMG_IMPORT PVRSRV_ERROR 147IMG_IMPORT PVRSRV_ERROR
126SGXGetInternalDevInfoKM(IMG_HANDLE hDevCookie, 148SGXGetInternalDevInfoKM(IMG_HANDLE hDevCookie,
149#if defined (SUPPORT_SID_INTERFACE)
150 SGX_INTERNAL_DEVINFO_KM *psSGXInternalDevInfo);
151#else
127 SGX_INTERNAL_DEVINFO *psSGXInternalDevInfo); 152 SGX_INTERNAL_DEVINFO *psSGXInternalDevInfo);
153#endif
128 154
129#if defined (__cplusplus) 155#if defined (__cplusplus)
130} 156}
diff --git a/drivers/gpu/pvr/sgx/sgxconfig.h b/drivers/gpu/pvr/sgx/sgxconfig.h
index 6d9d077bb85..8cbe39bc11f 100644
--- a/drivers/gpu/pvr/sgx/sgxconfig.h
+++ b/drivers/gpu/pvr/sgx/sgxconfig.h
@@ -36,6 +36,70 @@
36#define DEV_MINOR_VERSION 0 36#define DEV_MINOR_VERSION 0
37 37
38#if SGX_FEATURE_ADDRESS_SPACE_SIZE == 32 38#if SGX_FEATURE_ADDRESS_SPACE_SIZE == 32
39#if defined(FIX_HW_BRN_31620)
40 #if defined(SGX_FEATURE_2D_HARDWARE)
41 #define SGX_2D_HEAP_BASE 0x04000000
42 #define SGX_2D_HEAP_SIZE (0x08000000-0x04000000-0x00001000)
43 #endif
44
45 #define SGX_GENERAL_HEAP_BASE 0x08000000
46 #define SGX_GENERAL_HEAP_SIZE (0xB8000000-0x00001000)
47
48
49 #define SGX_3DPARAMETERS_HEAP_SIZE 0x10000000
50
51
52#if !defined(HYBRID_SHARED_PB_SIZE)
53 #define HYBRID_SHARED_PB_SIZE (SGX_3DPARAMETERS_HEAP_SIZE >> 1)
54#endif
55#if defined(SUPPORT_HYBRID_PB)
56 #define SGX_SHARED_3DPARAMETERS_SIZE (HYBRID_SHARED_PB_SIZE)
57 #define SGX_SHARED_3DPARAMETERS_HEAP_SIZE (HYBRID_SHARED_PB_SIZE-0x00001000)
58 #define SGX_PERCONTEXT_3DPARAMETERS_HEAP_SIZE (SGX_3DPARAMETERS_HEAP_SIZE - SGX_SHARED_3DPARAMETERS_SIZE - 0x00001000)
59#else
60#if defined(SUPPORT_PERCONTEXT_PB)
61 #define SGX_SHARED_3DPARAMETERS_SIZE 0
62 #define SGX_SHARED_3DPARAMETERS_HEAP_SIZE 0
63 #define SGX_PERCONTEXT_3DPARAMETERS_HEAP_SIZE (SGX_3DPARAMETERS_HEAP_SIZE - 0x00001000)
64#endif
65#if defined(SUPPORT_SHARED_PB)
66 #define SGX_SHARED_3DPARAMETERS_SIZE SGX_3DPARAMETERS_HEAP_SIZE
67 #define SGX_SHARED_3DPARAMETERS_HEAP_SIZE (SGX_3DPARAMETERS_HEAP_SIZE - 0x00001000)
68 #define SGX_PERCONTEXT_3DPARAMETERS_HEAP_SIZE 0
69#endif
70#endif
71
72 #define SGX_SHARED_3DPARAMETERS_HEAP_BASE 0xC0000000
73
74
75 #define SGX_PERCONTEXT_3DPARAMETERS_HEAP_BASE (SGX_SHARED_3DPARAMETERS_HEAP_BASE + SGX_SHARED_3DPARAMETERS_SIZE)
76
77
78 #define SGX_TADATA_HEAP_BASE 0xD0000000
79 #define SGX_TADATA_HEAP_SIZE (0x0D000000-0x00001000)
80
81 #define SGX_SYNCINFO_HEAP_BASE 0xE0000000
82 #define SGX_SYNCINFO_HEAP_SIZE (0x01000000-0x00001000)
83
84 #define SGX_PDSPIXEL_CODEDATA_HEAP_BASE 0xE4000000
85 #define SGX_PDSPIXEL_CODEDATA_HEAP_SIZE (0x02000000-0x00001000)
86
87 #define SGX_KERNEL_CODE_HEAP_BASE 0xE8000000
88 #define SGX_KERNEL_CODE_HEAP_SIZE (0x00080000-0x00001000)
89
90 #define SGX_PDSVERTEX_CODEDATA_HEAP_BASE 0xEC000000
91 #define SGX_PDSVERTEX_CODEDATA_HEAP_SIZE (0x01C00000-0x00001000)
92
93 #define SGX_KERNEL_DATA_HEAP_BASE 0xF0000000
94 #define SGX_KERNEL_DATA_HEAP_SIZE (0x03000000-0x00001000)
95
96
97 #define SGX_PIXELSHADER_HEAP_BASE 0xF4000000
98 #define SGX_PIXELSHADER_HEAP_SIZE (0x05000000-0x00001000)
99
100 #define SGX_VERTEXSHADER_HEAP_BASE 0xFC000000
101 #define SGX_VERTEXSHADER_HEAP_SIZE (0x02000000-0x00001000)
102#else
39 #if defined(SGX_FEATURE_2D_HARDWARE) 103 #if defined(SGX_FEATURE_2D_HARDWARE)
40 #define SGX_2D_HEAP_BASE 0x00100000 104 #define SGX_2D_HEAP_BASE 0x00100000
41 #define SGX_2D_HEAP_SIZE (0x08000000-0x00100000-0x00001000) 105 #define SGX_2D_HEAP_SIZE (0x08000000-0x00100000-0x00001000)
@@ -54,8 +118,35 @@
54 #define SGX_GENERAL_HEAP_BASE 0x10000000 118 #define SGX_GENERAL_HEAP_BASE 0x10000000
55 #define SGX_GENERAL_HEAP_SIZE (0xC2000000-0x00001000) 119 #define SGX_GENERAL_HEAP_SIZE (0xC2000000-0x00001000)
56 120
57 #define SGX_3DPARAMETERS_HEAP_BASE 0xD2000000 121
58 #define SGX_3DPARAMETERS_HEAP_SIZE (0x10000000-0x00001000) 122 #define SGX_3DPARAMETERS_HEAP_SIZE 0x10000000
123
124
125#if !defined(HYBRID_SHARED_PB_SIZE)
126 #define HYBRID_SHARED_PB_SIZE (SGX_3DPARAMETERS_HEAP_SIZE >> 1)
127#endif
128#if defined(SUPPORT_HYBRID_PB)
129 #define SGX_SHARED_3DPARAMETERS_SIZE (HYBRID_SHARED_PB_SIZE)
130 #define SGX_SHARED_3DPARAMETERS_HEAP_SIZE (HYBRID_SHARED_PB_SIZE-0x00001000)
131 #define SGX_PERCONTEXT_3DPARAMETERS_HEAP_SIZE (SGX_3DPARAMETERS_HEAP_SIZE - SGX_SHARED_3DPARAMETERS_SIZE - 0x00001000)
132#else
133#if defined(SUPPORT_PERCONTEXT_PB)
134 #define SGX_SHARED_3DPARAMETERS_SIZE 0
135 #define SGX_SHARED_3DPARAMETERS_HEAP_SIZE 0
136 #define SGX_PERCONTEXT_3DPARAMETERS_HEAP_SIZE (SGX_3DPARAMETERS_HEAP_SIZE - 0x00001000)
137#endif
138#if defined(SUPPORT_SHARED_PB)
139 #define SGX_SHARED_3DPARAMETERS_SIZE SGX_3DPARAMETERS_HEAP_SIZE
140 #define SGX_SHARED_3DPARAMETERS_HEAP_SIZE (SGX_3DPARAMETERS_HEAP_SIZE - 0x00001000)
141 #define SGX_PERCONTEXT_3DPARAMETERS_HEAP_SIZE 0
142#endif
143#endif
144
145 #define SGX_SHARED_3DPARAMETERS_HEAP_BASE 0xD2000000
146
147
148 #define SGX_PERCONTEXT_3DPARAMETERS_HEAP_BASE (SGX_SHARED_3DPARAMETERS_HEAP_BASE + SGX_SHARED_3DPARAMETERS_SIZE)
149
59 150
60 #define SGX_TADATA_HEAP_BASE 0xE2000000 151 #define SGX_TADATA_HEAP_BASE 0xE2000000
61 #define SGX_TADATA_HEAP_SIZE (0x0D000000-0x00001000) 152 #define SGX_TADATA_HEAP_SIZE (0x0D000000-0x00001000)
@@ -81,10 +172,10 @@
81 172
82 #define SGX_VERTEXSHADER_HEAP_BASE 0xFE000000 173 #define SGX_VERTEXSHADER_HEAP_BASE 0xFE000000
83 #define SGX_VERTEXSHADER_HEAP_SIZE (0x02000000-0x00001000) 174 #define SGX_VERTEXSHADER_HEAP_SIZE (0x02000000-0x00001000)
84 175#endif
85 176
86 #define SGX_CORE_IDENTIFIED 177 #define SGX_CORE_IDENTIFIED
87#endif 178#endif
88 179
89#if SGX_FEATURE_ADDRESS_SPACE_SIZE == 28 180#if SGX_FEATURE_ADDRESS_SPACE_SIZE == 28
90 181
@@ -99,9 +190,35 @@
99 #define SGX_GENERAL_HEAP_BASE 0x00001000 190 #define SGX_GENERAL_HEAP_BASE 0x00001000
100 #define SGX_GENERAL_HEAP_SIZE (0x08800000-0x00001000-0x00001000) 191 #define SGX_GENERAL_HEAP_SIZE (0x08800000-0x00001000-0x00001000)
101#endif 192#endif
193
194 #define SGX_3DPARAMETERS_HEAP_SIZE 0x04000000
195
196
197#if !defined(HYBRID_SHARED_PB_SIZE)
198 #define HYBRID_SHARED_PB_SIZE (SGX_3DPARAMETERS_HEAP_SIZE >> 1)
199#endif
200#if defined(SUPPORT_HYBRID_PB)
201 #define SGX_SHARED_3DPARAMETERS_SIZE (HYBRID_SHARED_PB_SIZE)
202 #define SGX_SHARED_3DPARAMETERS_HEAP_SIZE (HYBRID_SHARED_PB_SIZE-0x00001000)
203 #define SGX_PERCONTEXT_3DPARAMETERS_HEAP_SIZE (SGX_3DPARAMETERS_HEAP_SIZE - SGX_SHARED_3DPARAMETERS_SIZE - 0x00001000)
204#else
205#if defined(SUPPORT_PERCONTEXT_PB)
206 #define SGX_SHARED_3DPARAMETERS_SIZE 0
207 #define SGX_SHARED_3DPARAMETERS_HEAP_SIZE 0
208 #define SGX_PERCONTEXT_3DPARAMETERS_HEAP_SIZE (SGX_3DPARAMETERS_HEAP_SIZE - 0x00001000)
209#endif
210#if defined(SUPPORT_SHARED_PB)
211 #define SGX_SHARED_3DPARAMETERS_SIZE SGX_3DPARAMETERS_HEAP_SIZE
212 #define SGX_SHARED_3DPARAMETERS_HEAP_SIZE (SGX_3DPARAMETERS_HEAP_SIZE - 0x00001000)
213 #define SGX_PERCONTEXT_3DPARAMETERS_HEAP_SIZE 0
214#endif
215#endif
102 216
103 #define SGX_3DPARAMETERS_HEAP_BASE 0x08800000 217 #define SGX_SHARED_3DPARAMETERS_HEAP_BASE 0x08800000
104 #define SGX_3DPARAMETERS_HEAP_SIZE (0x04000000-0x00001000) 218
219
220 #define SGX_PERCONTEXT_3DPARAMETERS_HEAP_BASE (SGX_SHARED_3DPARAMETERS_HEAP_BASE + SGX_SHARED_3DPARAMETERS_SIZE)
221
105 222
106 #define SGX_TADATA_HEAP_BASE 0x0C800000 223 #define SGX_TADATA_HEAP_BASE 0x0C800000
107 #define SGX_TADATA_HEAP_SIZE (0x01000000-0x00001000) 224 #define SGX_TADATA_HEAP_SIZE (0x01000000-0x00001000)
@@ -127,10 +244,10 @@
127 #define SGX_VERTEXSHADER_HEAP_BASE 0x0FC00000 244 #define SGX_VERTEXSHADER_HEAP_BASE 0x0FC00000
128 #define SGX_VERTEXSHADER_HEAP_SIZE (0x00200000-0x00001000) 245 #define SGX_VERTEXSHADER_HEAP_SIZE (0x00200000-0x00001000)
129 246
130 247
131 #define SGX_CORE_IDENTIFIED 248 #define SGX_CORE_IDENTIFIED
132 249
133#endif 250#endif
134 251
135#if !defined(SGX_CORE_IDENTIFIED) 252#if !defined(SGX_CORE_IDENTIFIED)
136 #error "sgxconfig.h: ERROR: unspecified SGX Core version" 253 #error "sgxconfig.h: ERROR: unspecified SGX Core version"
@@ -188,12 +305,18 @@
188 #endif 305 #endif
189#endif 306#endif
190 307
191#if ((SGX_GENERAL_HEAP_BASE + SGX_GENERAL_HEAP_SIZE) >= SGX_3DPARAMETERS_HEAP_BASE) 308#if defined(SUPPORT_HYBRID_PB)
309 #if ((HYBRID_SHARED_PB_SIZE + 0x000001000) > SGX_3DPARAMETERS_HEAP_SIZE)
310 #error "sgxconfig.h: ERROR: HYBRID_SHARED_PB_SIZE too large"
311 #endif
312#endif
313
314#if ((SGX_GENERAL_HEAP_BASE + SGX_GENERAL_HEAP_SIZE) >= SGX_SHARED_3DPARAMETERS_HEAP_BASE)
192 #error "sgxconfig.h: ERROR: SGX_GENERAL_HEAP overlaps SGX_3DPARAMETERS_HEAP" 315 #error "sgxconfig.h: ERROR: SGX_GENERAL_HEAP overlaps SGX_3DPARAMETERS_HEAP"
193#endif 316#endif
194 317
195#if ((SGX_3DPARAMETERS_HEAP_BASE + SGX_3DPARAMETERS_HEAP_SIZE) >= SGX_TADATA_HEAP_BASE) 318#if (((SGX_PERCONTEXT_3DPARAMETERS_HEAP_BASE + SGX_PERCONTEXT_3DPARAMETERS_HEAP_SIZE) >= SGX_TADATA_HEAP_BASE) && (SGX_PERCONTEXT_3DPARAMETERS_HEAP_SIZE > 0))
196 #error "sgxconfig.h: ERROR: SGX_3DPARAMETERS_HEAP overlaps SGX_TADATA_HEAP" 319 #error "sgxconfig.h: ERROR: SGX_PERCONTEXT_3DPARAMETERS_HEAP_BASE overlaps SGX_TADATA_HEAP"
197#endif 320#endif
198 321
199#if ((SGX_TADATA_HEAP_BASE + SGX_TADATA_HEAP_SIZE) >= SGX_SYNCINFO_HEAP_BASE) 322#if ((SGX_TADATA_HEAP_BASE + SGX_TADATA_HEAP_SIZE) >= SGX_SYNCINFO_HEAP_BASE)
diff --git a/drivers/gpu/pvr/sgx/sgxinfokm.h b/drivers/gpu/pvr/sgx/sgxinfokm.h
index 056db35831d..fdb0f671b9d 100644
--- a/drivers/gpu/pvr/sgx/sgxinfokm.h
+++ b/drivers/gpu/pvr/sgx/sgxinfokm.h
@@ -126,6 +126,10 @@ typedef struct _PVRSRV_SGXDEV_INFO_
126#if defined(FIX_HW_BRN_29823) 126#if defined(FIX_HW_BRN_29823)
127 PPVRSRV_KERNEL_MEM_INFO psKernelDummyTermStreamMemInfo; 127 PPVRSRV_KERNEL_MEM_INFO psKernelDummyTermStreamMemInfo;
128#endif 128#endif
129#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && defined(FIX_HW_BRN_31425)
130 PPVRSRV_KERNEL_MEM_INFO psKernelVDMSnapShotBufferMemInfo;
131 PPVRSRV_KERNEL_MEM_INFO psKernelVDMCtrlStreamBufferMemInfo;
132#endif
129#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG) 133#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
130 PPVRSRV_KERNEL_MEM_INFO psKernelEDMStatusBufferMemInfo; 134 PPVRSRV_KERNEL_MEM_INFO psKernelEDMStatusBufferMemInfo;
131#endif 135#endif
@@ -159,6 +163,8 @@ typedef struct _PVRSRV_SGXDEV_INFO_
159 IMG_UINT32 ui32EDMTaskReg0; 163 IMG_UINT32 ui32EDMTaskReg0;
160 IMG_UINT32 ui32EDMTaskReg1; 164 IMG_UINT32 ui32EDMTaskReg1;
161 165
166 IMG_UINT32 ui32ClkGateCtl;
167 IMG_UINT32 ui32ClkGateCtl2;
162 IMG_UINT32 ui32ClkGateStatusReg; 168 IMG_UINT32 ui32ClkGateStatusReg;
163 IMG_UINT32 ui32ClkGateStatusMask; 169 IMG_UINT32 ui32ClkGateStatusMask;
164#if defined(SGX_FEATURE_MP) 170#if defined(SGX_FEATURE_MP)
@@ -228,6 +234,20 @@ typedef struct _PVRSRV_SGXDEV_INFO_
228#endif 234#endif
229 IMG_UINT32 asSGXDevData[SGX_MAX_DEV_DATA]; 235 IMG_UINT32 asSGXDevData[SGX_MAX_DEV_DATA];
230 236
237#if defined(FIX_HW_BRN_31620)
238
239 IMG_VOID *pvBRN31620DummyPageCpuVAddr;
240 IMG_HANDLE hBRN31620DummyPageOSMemHandle;
241 IMG_DEV_PHYADDR sBRN31620DummyPageDevPAddr;
242
243
244 IMG_VOID *pvBRN31620DummyPTCpuVAddr;
245 IMG_HANDLE hBRN31620DummyPTOSMemHandle;
246 IMG_DEV_PHYADDR sBRN31620DummyPTDevPAddr;
247
248 IMG_HANDLE hKernelMMUContext;
249#endif
250
231} PVRSRV_SGXDEV_INFO; 251} PVRSRV_SGXDEV_INFO;
232 252
233 253
@@ -292,6 +312,7 @@ struct _PVRSRV_STUB_PBDESC_
292 IMG_HANDLE hDevCookie; 312 IMG_HANDLE hDevCookie;
293 PVRSRV_KERNEL_MEM_INFO *psBlockKernelMemInfo; 313 PVRSRV_KERNEL_MEM_INFO *psBlockKernelMemInfo;
294 PVRSRV_KERNEL_MEM_INFO *psHWBlockKernelMemInfo; 314 PVRSRV_KERNEL_MEM_INFO *psHWBlockKernelMemInfo;
315 IMG_DEV_VIRTADDR sHWPBDescDevVAddr;
295 PVRSRV_STUB_PBDESC *psNext; 316 PVRSRV_STUB_PBDESC *psNext;
296 PVRSRV_STUB_PBDESC **ppsThis; 317 PVRSRV_STUB_PBDESC **ppsThis;
297}; 318};
@@ -308,6 +329,183 @@ typedef struct _PVRSRV_SGX_CCB_INFO_
308#endif 329#endif
309} PVRSRV_SGX_CCB_INFO; 330} PVRSRV_SGX_CCB_INFO;
310 331
332
333typedef struct _SGX_BRIDGE_INIT_INFO_KM_
334{
335 IMG_HANDLE hKernelCCBMemInfo;
336 IMG_HANDLE hKernelCCBCtlMemInfo;
337 IMG_HANDLE hKernelCCBEventKickerMemInfo;
338 IMG_HANDLE hKernelSGXHostCtlMemInfo;
339 IMG_HANDLE hKernelSGXTA3DCtlMemInfo;
340 IMG_HANDLE hKernelSGXMiscMemInfo;
341
342 IMG_UINT32 aui32HostKickAddr[SGXMKIF_CMD_MAX];
343
344 SGX_INIT_SCRIPTS sScripts;
345
346 IMG_UINT32 ui32ClientBuildOptions;
347 SGX_MISCINFO_STRUCT_SIZES sSGXStructSizes;
348
349#if defined(SGX_SUPPORT_HWPROFILING)
350 IMG_HANDLE hKernelHWProfilingMemInfo;
351#endif
352#if defined(SUPPORT_SGX_HWPERF)
353 IMG_HANDLE hKernelHWPerfCBMemInfo;
354#endif
355 IMG_HANDLE hKernelTASigBufferMemInfo;
356 IMG_HANDLE hKernel3DSigBufferMemInfo;
357
358#if defined(FIX_HW_BRN_29702)
359 IMG_HANDLE hKernelCFIMemInfo;
360#endif
361#if defined(FIX_HW_BRN_29823)
362 IMG_HANDLE hKernelDummyTermStreamMemInfo;
363#endif
364#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
365 IMG_HANDLE hKernelEDMStatusBufferMemInfo;
366#endif
367#if defined(SGX_FEATURE_OVERLAPPED_SPM)
368 IMG_HANDLE hKernelTmpRgnHeaderMemInfo;
369#endif
370#if defined(SGX_FEATURE_SPM_MODE_0)
371 IMG_HANDLE hKernelTmpDPMStateMemInfo;
372#endif
373
374 IMG_UINT32 ui32EDMTaskReg0;
375 IMG_UINT32 ui32EDMTaskReg1;
376
377 IMG_UINT32 ui32ClkGateStatusReg;
378 IMG_UINT32 ui32ClkGateStatusMask;
379#if defined(SGX_FEATURE_MP)
380#endif
381
382 IMG_UINT32 ui32CacheControl;
383
384 IMG_UINT32 asInitDevData[SGX_MAX_DEV_DATA];
385 IMG_HANDLE asInitMemHandles[SGX_MAX_INIT_MEM_HANDLES];
386
387} SGX_BRIDGE_INIT_INFO_KM;
388
389
390typedef struct _SGX_INTERNEL_STATUS_UPDATE_KM_
391{
392 CTL_STATUS sCtlStatus;
393 IMG_HANDLE hKernelMemInfo;
394} SGX_INTERNEL_STATUS_UPDATE_KM;
395
396
397typedef struct _SGX_CCB_KICK_KM_
398{
399 SGXMKIF_COMMAND sCommand;
400 IMG_HANDLE hCCBKernelMemInfo;
401
402 IMG_UINT32 ui32NumDstSyncObjects;
403 IMG_HANDLE hKernelHWSyncListMemInfo;
404
405
406 IMG_HANDLE *pahDstSyncHandles;
407
408 IMG_UINT32 ui32NumTAStatusVals;
409 IMG_UINT32 ui32Num3DStatusVals;
410
411#if defined(SUPPORT_SGX_NEW_STATUS_VALS)
412 SGX_INTERNEL_STATUS_UPDATE_KM asTAStatusUpdate[SGX_MAX_TA_STATUS_VALS];
413 SGX_INTERNEL_STATUS_UPDATE_KM as3DStatusUpdate[SGX_MAX_3D_STATUS_VALS];
414#else
415 IMG_HANDLE ahTAStatusSyncInfo[SGX_MAX_TA_STATUS_VALS];
416 IMG_HANDLE ah3DStatusSyncInfo[SGX_MAX_3D_STATUS_VALS];
417#endif
418
419 IMG_BOOL bFirstKickOrResume;
420#if (defined(NO_HARDWARE) || defined(PDUMP))
421 IMG_BOOL bTerminateOrAbort;
422#endif
423
424
425 IMG_UINT32 ui32CCBOffset;
426
427#if defined(SUPPORT_SGX_GENERALISED_SYNCOBJECTS)
428
429 IMG_UINT32 ui32NumTASrcSyncs;
430 IMG_HANDLE ahTASrcKernelSyncInfo[SGX_MAX_TA_SRC_SYNCS];
431 IMG_UINT32 ui32NumTADstSyncs;
432 IMG_HANDLE ahTADstKernelSyncInfo[SGX_MAX_TA_DST_SYNCS];
433 IMG_UINT32 ui32Num3DSrcSyncs;
434 IMG_HANDLE ah3DSrcKernelSyncInfo[SGX_MAX_3D_SRC_SYNCS];
435#else
436
437 IMG_UINT32 ui32NumSrcSyncs;
438 IMG_HANDLE ahSrcKernelSyncInfo[SGX_MAX_SRC_SYNCS];
439#endif
440
441
442 IMG_BOOL bTADependency;
443 IMG_HANDLE hTA3DSyncInfo;
444
445 IMG_HANDLE hTASyncInfo;
446 IMG_HANDLE h3DSyncInfo;
447#if defined(PDUMP)
448 IMG_UINT32 ui32CCBDumpWOff;
449#endif
450#if defined(NO_HARDWARE)
451 IMG_UINT32 ui32WriteOpsPendingVal;
452#endif
453} SGX_CCB_KICK_KM;
454
455
456#if defined(TRANSFER_QUEUE)
457typedef struct _PVRSRV_TRANSFER_SGX_KICK_KM_
458{
459 IMG_HANDLE hCCBMemInfo;
460 IMG_UINT32 ui32SharedCmdCCBOffset;
461
462 IMG_DEV_VIRTADDR sHWTransferContextDevVAddr;
463
464 IMG_HANDLE hTASyncInfo;
465 IMG_HANDLE h3DSyncInfo;
466
467 IMG_UINT32 ui32NumSrcSync;
468 IMG_HANDLE ahSrcSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS];
469
470 IMG_UINT32 ui32NumDstSync;
471 IMG_HANDLE ahDstSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS];
472
473 IMG_UINT32 ui32Flags;
474
475 IMG_UINT32 ui32PDumpFlags;
476#if defined(PDUMP)
477 IMG_UINT32 ui32CCBDumpWOff;
478#endif
479} PVRSRV_TRANSFER_SGX_KICK_KM, *PPVRSRV_TRANSFER_SGX_KICK_KM;
480
481#if defined(SGX_FEATURE_2D_HARDWARE)
482typedef struct _PVRSRV_2D_SGX_KICK_KM_
483{
484 IMG_HANDLE hCCBMemInfo;
485 IMG_UINT32 ui32SharedCmdCCBOffset;
486
487 IMG_DEV_VIRTADDR sHW2DContextDevVAddr;
488
489 IMG_UINT32 ui32NumSrcSync;
490 IMG_HANDLE ahSrcSyncInfo[SGX_MAX_2D_SRC_SYNC_OPS];
491
492
493 IMG_HANDLE hDstSyncInfo;
494
495
496 IMG_HANDLE hTASyncInfo;
497
498
499 IMG_HANDLE h3DSyncInfo;
500
501 IMG_UINT32 ui32PDumpFlags;
502#if defined(PDUMP)
503 IMG_UINT32 ui32CCBDumpWOff;
504#endif
505} PVRSRV_2D_SGX_KICK_KM, *PPVRSRV_2D_SGX_KICK_KM;
506#endif
507#endif
508
311PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode); 509PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode);
312 510
313IMG_VOID SGXOSTimer(IMG_VOID *pvData); 511IMG_VOID SGXOSTimer(IMG_VOID *pvData);
@@ -316,6 +514,9 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
316 IMG_BOOL bHardwareRecovery, 514 IMG_BOOL bHardwareRecovery,
317 IMG_UINT32 ui32PDUMPFlags); 515 IMG_UINT32 ui32PDUMPFlags);
318 516
517IMG_VOID SGXInitClocks(PVRSRV_SGXDEV_INFO *psDevInfo,
518 IMG_UINT32 ui32PDUMPFlags);
519
319PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo, 520PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
320 IMG_BOOL bHardwareRecovery); 521 IMG_BOOL bHardwareRecovery);
321PVRSRV_ERROR SGXDeinitialise(IMG_HANDLE hDevCookie); 522PVRSRV_ERROR SGXDeinitialise(IMG_HANDLE hDevCookie);
diff --git a/drivers/gpu/pvr/sgx/sgxinit.c b/drivers/gpu/pvr/sgx/sgxinit.c
index 3872102029f..e73c067bd4f 100644
--- a/drivers/gpu/pvr/sgx/sgxinit.c
+++ b/drivers/gpu/pvr/sgx/sgxinit.c
@@ -51,6 +51,7 @@
51 51
52#include "lists.h" 52#include "lists.h"
53#include "srvkm.h" 53#include "srvkm.h"
54#include "ttrace.h"
54 55
55#define VAR(x) #x 56#define VAR(x) #x
56 57
@@ -74,7 +75,8 @@ IMG_BOOL SGX_ISRHandler(IMG_VOID *pvData);
74 75
75static 76static
76PVRSRV_ERROR SGXGetMiscInfoUkernel(PVRSRV_SGXDEV_INFO *psDevInfo, 77PVRSRV_ERROR SGXGetMiscInfoUkernel(PVRSRV_SGXDEV_INFO *psDevInfo,
77 PVRSRV_DEVICE_NODE *psDeviceNode); 78 PVRSRV_DEVICE_NODE *psDeviceNode,
79 IMG_HANDLE hDevMemContext);
78#if defined(PDUMP) 80#if defined(PDUMP)
79static 81static
80PVRSRV_ERROR SGXResetPDump(PVRSRV_DEVICE_NODE *psDeviceNode); 82PVRSRV_ERROR SGXResetPDump(PVRSRV_DEVICE_NODE *psDeviceNode);
@@ -111,7 +113,11 @@ static IMG_UINT32 DeinitDevInfo(PVRSRV_SGXDEV_INFO *psDevInfo)
111 113
112static PVRSRV_ERROR InitDevInfo(PVRSRV_PER_PROCESS_DATA *psPerProc, 114static PVRSRV_ERROR InitDevInfo(PVRSRV_PER_PROCESS_DATA *psPerProc,
113 PVRSRV_DEVICE_NODE *psDeviceNode, 115 PVRSRV_DEVICE_NODE *psDeviceNode,
116#if defined (SUPPORT_SID_INTERFACE)
117 SGX_BRIDGE_INIT_INFO_KM *psInitInfo)
118#else
114 SGX_BRIDGE_INIT_INFO *psInitInfo) 119 SGX_BRIDGE_INIT_INFO *psInitInfo)
120#endif
115{ 121{
116 PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice; 122 PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
117 PVRSRV_ERROR eError; 123 PVRSRV_ERROR eError;
@@ -135,7 +141,7 @@ static PVRSRV_ERROR InitDevInfo(PVRSRV_PER_PROCESS_DATA *psPerProc,
135 141
136 psDevInfo->psKernelSGXTA3DCtlMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelSGXTA3DCtlMemInfo; 142 psDevInfo->psKernelSGXTA3DCtlMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelSGXTA3DCtlMemInfo;
137 143
138 psDevInfo->psKernelSGXMiscMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelSGXMiscMemInfo; 144 psDevInfo->psKernelSGXMiscMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelSGXMiscMemInfo;
139 145
140#if defined(SGX_SUPPORT_HWPROFILING) 146#if defined(SGX_SUPPORT_HWPROFILING)
141 psDevInfo->psKernelHWProfilingMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelHWProfilingMemInfo; 147 psDevInfo->psKernelHWProfilingMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelHWProfilingMemInfo;
@@ -151,6 +157,10 @@ static PVRSRV_ERROR InitDevInfo(PVRSRV_PER_PROCESS_DATA *psPerProc,
151#if defined(FIX_HW_BRN_29823) 157#if defined(FIX_HW_BRN_29823)
152 psDevInfo->psKernelDummyTermStreamMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelDummyTermStreamMemInfo; 158 psDevInfo->psKernelDummyTermStreamMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelDummyTermStreamMemInfo;
153#endif 159#endif
160#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && defined(FIX_HW_BRN_31425)
161 psDevInfo->psKernelVDMSnapShotBufferMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelVDMSnapShotBufferMemInfo;
162 psDevInfo->psKernelVDMCtrlStreamBufferMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelVDMCtrlStreamBufferMemInfo;
163#endif
154#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG) 164#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
155 psDevInfo->psKernelEDMStatusBufferMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelEDMStatusBufferMemInfo; 165 psDevInfo->psKernelEDMStatusBufferMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psInitInfo->hKernelEDMStatusBufferMemInfo;
156#endif 166#endif
@@ -168,7 +178,7 @@ static PVRSRV_ERROR InitDevInfo(PVRSRV_PER_PROCESS_DATA *psPerProc,
168 178
169 179
170 180
171 eError = OSAllocMem(PVRSRV_OS_PAGEABLE_HEAP, 181 eError = OSAllocMem(PVRSRV_OS_NON_PAGEABLE_HEAP,
172 sizeof(PVRSRV_SGX_CCB_INFO), 182 sizeof(PVRSRV_SGX_CCB_INFO),
173 (IMG_VOID **)&psKernelCCBInfo, 0, 183 (IMG_VOID **)&psKernelCCBInfo, 0,
174 "SGX Circular Command Buffer Info"); 184 "SGX Circular Command Buffer Info");
@@ -198,6 +208,8 @@ static PVRSRV_ERROR InitDevInfo(PVRSRV_PER_PROCESS_DATA *psPerProc,
198 208
199 psDevInfo->ui32EDMTaskReg0 = psInitInfo->ui32EDMTaskReg0; 209 psDevInfo->ui32EDMTaskReg0 = psInitInfo->ui32EDMTaskReg0;
200 psDevInfo->ui32EDMTaskReg1 = psInitInfo->ui32EDMTaskReg1; 210 psDevInfo->ui32EDMTaskReg1 = psInitInfo->ui32EDMTaskReg1;
211 psDevInfo->ui32ClkGateCtl = psInitInfo->ui32ClkGateCtl;
212 psDevInfo->ui32ClkGateCtl2 = psInitInfo->ui32ClkGateCtl2;
201 psDevInfo->ui32ClkGateStatusReg = psInitInfo->ui32ClkGateStatusReg; 213 psDevInfo->ui32ClkGateStatusReg = psInitInfo->ui32ClkGateStatusReg;
202 psDevInfo->ui32ClkGateStatusMask = psInitInfo->ui32ClkGateStatusMask; 214 psDevInfo->ui32ClkGateStatusMask = psInitInfo->ui32ClkGateStatusMask;
203#if defined(SGX_FEATURE_MP) 215#if defined(SGX_FEATURE_MP)
@@ -277,6 +289,12 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
277 IMG_BOOL bPDumpIsSuspended = PDumpIsSuspended(); 289 IMG_BOOL bPDumpIsSuspended = PDumpIsSuspended();
278#endif 290#endif
279 291
292#if defined(SGX_FEATURE_MP)
293
294#else
295 SGXInitClocks(psDevInfo, PDUMP_FLAGS_CONTINUOUS);
296#endif
297
280 298
281 299
282 PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, "SGX initialisation script part 1\n"); 300 PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, "SGX initialisation script part 1\n");
@@ -289,6 +307,7 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
289 PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, "End of SGX initialisation script part 1\n"); 307 PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, "End of SGX initialisation script part 1\n");
290 308
291 309
310 psDevInfo->ui32NumResets++;
292 SGXReset(psDevInfo, bFirstTime || bHardwareRecovery, PDUMP_FLAGS_CONTINUOUS); 311 SGXReset(psDevInfo, bFirstTime || bHardwareRecovery, PDUMP_FLAGS_CONTINUOUS);
293 312
294#if defined(EUR_CR_POWER) 313#if defined(EUR_CR_POWER)
@@ -379,12 +398,12 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
379 PDUMP_FLAGS_CONTINUOUS, 398 PDUMP_FLAGS_CONTINUOUS,
380 MAKEUNIQUETAG(psDevInfo->psKernelCCBEventKickerMemInfo)); 399 MAKEUNIQUETAG(psDevInfo->psKernelCCBEventKickerMemInfo));
381 PDUMPREG(SGX_PDUMPREG_NAME, SGX_MP_CORE_SELECT(EUR_CR_EVENT_KICK, 0), EUR_CR_EVENT_KICK_NOW_MASK); 400 PDUMPREG(SGX_PDUMPREG_NAME, SGX_MP_CORE_SELECT(EUR_CR_EVENT_KICK, 0), EUR_CR_EVENT_KICK_NOW_MASK);
382#endif 401#endif
383 } 402 }
384#endif 403#endif
385 404
386#if !defined(NO_HARDWARE) 405#if !defined(NO_HARDWARE)
387 406
388 407
389 if (PollForValueKM(&psSGXHostCtl->ui32InitStatus, 408 if (PollForValueKM(&psSGXHostCtl->ui32InitStatus,
390 PVRSRV_USSE_EDM_INIT_COMPLETE, 409 PVRSRV_USSE_EDM_INIT_COMPLETE,
@@ -396,10 +415,10 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
396 PVR_DPF((PVR_DBG_ERROR, "SGXInitialise: Wait for uKernel initialisation failed")); 415 PVR_DPF((PVR_DBG_ERROR, "SGXInitialise: Wait for uKernel initialisation failed"));
397 #if !defined(FIX_HW_BRN_23281) 416 #if !defined(FIX_HW_BRN_23281)
398 PVR_DBG_BREAK; 417 PVR_DBG_BREAK;
399 #endif 418 #endif
400 return PVRSRV_ERROR_RETRY; 419 return PVRSRV_ERROR_RETRY;
401 } 420 }
402#endif 421#endif
403 422
404#if defined(PDUMP) 423#if defined(PDUMP)
405 PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS, 424 PDUMPCOMMENTWITHFLAGS(PDUMP_FLAGS_CONTINUOUS,
@@ -411,19 +430,19 @@ PVRSRV_ERROR SGXInitialise(PVRSRV_SGXDEV_INFO *psDevInfo,
411 PDUMP_POLL_OPERATOR_EQUAL, 430 PDUMP_POLL_OPERATOR_EQUAL,
412 PDUMP_FLAGS_CONTINUOUS, 431 PDUMP_FLAGS_CONTINUOUS,
413 MAKEUNIQUETAG(psSGXHostCtlMemInfo)); 432 MAKEUNIQUETAG(psSGXHostCtlMemInfo));
414#endif 433#endif
415 434
416#if defined(FIX_HW_BRN_22997) && defined(FIX_HW_BRN_23030) && defined(SGX_FEATURE_HOST_PORT) 435#if defined(FIX_HW_BRN_22997) && defined(FIX_HW_BRN_23030) && defined(SGX_FEATURE_HOST_PORT)
417 436
418 437
419 438
420 WorkaroundBRN22997ReadHostPort(psDevInfo); 439 WorkaroundBRN22997ReadHostPort(psDevInfo);
421#endif 440#endif
422 441
423 PVR_ASSERT(psDevInfo->psKernelCCBCtl->ui32ReadOffset == psDevInfo->psKernelCCBCtl->ui32WriteOffset); 442 PVR_ASSERT(psDevInfo->psKernelCCBCtl->ui32ReadOffset == psDevInfo->psKernelCCBCtl->ui32WriteOffset);
424 443
425 bFirstTime = IMG_FALSE; 444 bFirstTime = IMG_FALSE;
426 445
427 return PVRSRV_OK; 446 return PVRSRV_OK;
428} 447}
429 448
@@ -433,7 +452,7 @@ PVRSRV_ERROR SGXDeinitialise(IMG_HANDLE hDevCookie)
433 PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *) hDevCookie; 452 PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *) hDevCookie;
434 PVRSRV_ERROR eError; 453 PVRSRV_ERROR eError;
435 454
436 455
437 if (psDevInfo->pvRegsBaseKM == IMG_NULL) 456 if (psDevInfo->pvRegsBaseKM == IMG_NULL)
438 { 457 {
439 return PVRSRV_OK; 458 return PVRSRV_OK;
@@ -461,12 +480,16 @@ static PVRSRV_ERROR DevInitSGXPart1 (IMG_VOID *pvDeviceNode)
461 DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap = psDeviceNode->sDevMemoryInfo.psDeviceMemoryHeap; 480 DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap = psDeviceNode->sDevMemoryInfo.psDeviceMemoryHeap;
462 PVRSRV_ERROR eError; 481 PVRSRV_ERROR eError;
463 482
464 483
465 PDUMPCOMMENT("SGX Core Version Information: %s", SGX_CORE_FRIENDLY_NAME); 484 PDUMPCOMMENT("SGX Core Version Information: %s", SGX_CORE_FRIENDLY_NAME);
466 485
467 #if defined(SGX_FEATURE_MP) 486 #if defined(SGX_FEATURE_MP)
487 #if !defined(SGX_FEATURE_MP_PLUS)
468 PDUMPCOMMENT("SGX Multi-processor: %d cores", SGX_FEATURE_MP_CORE_COUNT); 488 PDUMPCOMMENT("SGX Multi-processor: %d cores", SGX_FEATURE_MP_CORE_COUNT);
489 #else
490 PDUMPCOMMENT("SGX Multi-processor: %d TA cores, %d 3D cores", SGX_FEATURE_MP_CORE_COUNT_TA, SGX_FEATURE_MP_CORE_COUNT_3D);
469 #endif 491 #endif
492 #endif
470 493
471#if (SGX_CORE_REV == 0) 494#if (SGX_CORE_REV == 0)
472 PDUMPCOMMENT("SGX Core Revision Information: head RTL"); 495 PDUMPCOMMENT("SGX Core Revision Information: head RTL");
@@ -478,8 +501,8 @@ static PVRSRV_ERROR DevInitSGXPart1 (IMG_VOID *pvDeviceNode)
478 PDUMPCOMMENT("SGX System Level Cache is present\r\n"); 501 PDUMPCOMMENT("SGX System Level Cache is present\r\n");
479 #if defined(SGX_BYPASS_SYSTEM_CACHE) 502 #if defined(SGX_BYPASS_SYSTEM_CACHE)
480 PDUMPCOMMENT("SGX System Level Cache is bypassed\r\n"); 503 PDUMPCOMMENT("SGX System Level Cache is bypassed\r\n");
481 #endif 504 #endif
482 #endif 505 #endif
483 506
484 PDUMPCOMMENT("SGX Initialisation Part 1"); 507 PDUMPCOMMENT("SGX Initialisation Part 1");
485 508
@@ -526,12 +549,16 @@ static PVRSRV_ERROR DevInitSGXPart1 (IMG_VOID *pvDeviceNode)
526 case DEVICE_MEMORY_HEAP_SHARED: 549 case DEVICE_MEMORY_HEAP_SHARED:
527 case DEVICE_MEMORY_HEAP_SHARED_EXPORTED: 550 case DEVICE_MEMORY_HEAP_SHARED_EXPORTED:
528 { 551 {
529 hDevMemHeap = BM_CreateHeap (hKernelDevMemContext,
530 &psDeviceMemoryHeap[i]);
531 552
553 if (psDeviceMemoryHeap[i].ui32HeapSize > 0)
554 {
555 hDevMemHeap = BM_CreateHeap (hKernelDevMemContext,
556 &psDeviceMemoryHeap[i]);
557
532 558
533 559
534 psDeviceMemoryHeap[i].hDevMemHeap = hDevMemHeap; 560 psDeviceMemoryHeap[i].hDevMemHeap = hDevMemHeap;
561 }
535 break; 562 break;
536 } 563 }
537 } 564 }
@@ -554,7 +581,11 @@ static PVRSRV_ERROR DevInitSGXPart1 (IMG_VOID *pvDeviceNode)
554} 581}
555 582
556IMG_EXPORT 583IMG_EXPORT
584#if defined (SUPPORT_SID_INTERFACE)
585PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, PVRSRV_HEAP_INFO_KM *pasHeapInfo, IMG_DEV_PHYADDR *psPDDevPAddr)
586#else
557PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, SGX_BRIDGE_INFO_FOR_SRVINIT *psInitInfo) 587PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, SGX_BRIDGE_INFO_FOR_SRVINIT *psInitInfo)
588#endif
558{ 589{
559 PVRSRV_DEVICE_NODE *psDeviceNode; 590 PVRSRV_DEVICE_NODE *psDeviceNode;
560 PVRSRV_SGXDEV_INFO *psDevInfo; 591 PVRSRV_SGXDEV_INFO *psDevInfo;
@@ -565,9 +596,15 @@ PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, SGX_BRIDGE_INFO_FOR_S
565 psDeviceNode = (PVRSRV_DEVICE_NODE *)hDevHandle; 596 psDeviceNode = (PVRSRV_DEVICE_NODE *)hDevHandle;
566 psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice; 597 psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
567 598
599#if defined (SUPPORT_SID_INTERFACE)
600 *psPDDevPAddr = psDevInfo->sKernelPDDevPAddr;
601
602 eError = PVRSRVGetDeviceMemHeapsKM(hDevHandle, pasHeapInfo);
603#else
568 psInitInfo->sPDDevPAddr = psDevInfo->sKernelPDDevPAddr; 604 psInitInfo->sPDDevPAddr = psDevInfo->sKernelPDDevPAddr;
569 605
570 eError = PVRSRVGetDeviceMemHeapsKM(hDevHandle, &psInitInfo->asHeapInfo[0]); 606 eError = PVRSRVGetDeviceMemHeapsKM(hDevHandle, &psInitInfo->asHeapInfo[0]);
607#endif
571 if (eError != PVRSRV_OK) 608 if (eError != PVRSRV_OK)
572 { 609 {
573 PVR_DPF((PVR_DBG_ERROR,"SGXGetInfoForSrvinit: PVRSRVGetDeviceMemHeapsKM failed (%d)", eError)); 610 PVR_DPF((PVR_DBG_ERROR,"SGXGetInfoForSrvinit: PVRSRVGetDeviceMemHeapsKM failed (%d)", eError));
@@ -580,7 +617,11 @@ PVRSRV_ERROR SGXGetInfoForSrvinitKM(IMG_HANDLE hDevHandle, SGX_BRIDGE_INFO_FOR_S
580IMG_EXPORT 617IMG_EXPORT
581PVRSRV_ERROR DevInitSGXPart2KM (PVRSRV_PER_PROCESS_DATA *psPerProc, 618PVRSRV_ERROR DevInitSGXPart2KM (PVRSRV_PER_PROCESS_DATA *psPerProc,
582 IMG_HANDLE hDevHandle, 619 IMG_HANDLE hDevHandle,
620#if defined (SUPPORT_SID_INTERFACE)
621 SGX_BRIDGE_INIT_INFO_KM *psInitInfo)
622#else
583 SGX_BRIDGE_INIT_INFO *psInitInfo) 623 SGX_BRIDGE_INIT_INFO *psInitInfo)
624#endif
584{ 625{
585 PVRSRV_DEVICE_NODE *psDeviceNode; 626 PVRSRV_DEVICE_NODE *psDeviceNode;
586 PVRSRV_SGXDEV_INFO *psDevInfo; 627 PVRSRV_SGXDEV_INFO *psDevInfo;
@@ -877,9 +918,12 @@ static IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo,
877 PVR_DPF((PVR_DBG_ERROR,"SGX Register Base Address (Linear): 0x%08X", (IMG_UINTPTR_T)psDevInfo->pvRegsBaseKM)); 918 PVR_DPF((PVR_DBG_ERROR,"SGX Register Base Address (Linear): 0x%08X", (IMG_UINTPTR_T)psDevInfo->pvRegsBaseKM));
878 PVR_DPF((PVR_DBG_ERROR,"SGX Register Base Address (Physical): 0x%08X", psDevInfo->sRegsPhysBase.uiAddr)); 919 PVR_DPF((PVR_DBG_ERROR,"SGX Register Base Address (Physical): 0x%08X", psDevInfo->sRegsPhysBase.uiAddr));
879 920
880 for (ui32CoreNum = 0; ui32CoreNum < SGX_FEATURE_MP_CORE_COUNT; ui32CoreNum++) 921 SGXDumpDebugReg(psDevInfo, 0, "EUR_CR_CORE_ID: ", EUR_CR_CORE_ID);
922 SGXDumpDebugReg(psDevInfo, 0, "EUR_CR_CORE_REVISION: ", EUR_CR_CORE_REVISION);
923
924 for (ui32CoreNum = 0; ui32CoreNum < SGX_FEATURE_MP_CORE_COUNT_3D; ui32CoreNum++)
881 { 925 {
882 926
883 SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_EVENT_STATUS: ", EUR_CR_EVENT_STATUS); 927 SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_EVENT_STATUS: ", EUR_CR_EVENT_STATUS);
884 SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_EVENT_STATUS2: ", EUR_CR_EVENT_STATUS2); 928 SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_EVENT_STATUS2: ", EUR_CR_EVENT_STATUS2);
885 SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_BIF_CTRL: ", EUR_CR_BIF_CTRL); 929 SGXDumpDebugReg(psDevInfo, ui32CoreNum, "EUR_CR_BIF_CTRL: ", EUR_CR_BIF_CTRL);
@@ -903,8 +947,15 @@ static IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo,
903 { 947 {
904 948
905 949
906 IMG_UINT32 *pui32HostCtlBuffer = (IMG_UINT32 *)psDevInfo->psSGXHostCtl; 950 SGXMKIF_HOST_CTL *psSGXHostCtl = psDevInfo->psSGXHostCtl;
907 IMG_UINT32 ui32LoopCounter; 951 IMG_UINT32 *pui32HostCtlBuffer = (IMG_UINT32 *)psSGXHostCtl;
952 IMG_UINT32 ui32LoopCounter;
953
954 if (psSGXHostCtl->ui32AssertFail != 0)
955 {
956 PVR_LOG(("SGX Microkernel assert fail: 0x%08X", psSGXHostCtl->ui32AssertFail));
957 psSGXHostCtl->ui32AssertFail = 0;
958 }
908 959
909 PVR_LOG(("SGX Host control:")); 960 PVR_LOG(("SGX Host control:"));
910 961
@@ -927,7 +978,7 @@ static IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo,
927 PVR_LOG(("SGX TA/3D control:")); 978 PVR_LOG(("SGX TA/3D control:"));
928 979
929 for (ui32LoopCounter = 0; 980 for (ui32LoopCounter = 0;
930 ui32LoopCounter < psDevInfo->psKernelSGXTA3DCtlMemInfo->ui32AllocSize / sizeof(*pui32TA3DCtlBuffer); 981 ui32LoopCounter < psDevInfo->psKernelSGXTA3DCtlMemInfo->uAllocSize / sizeof(*pui32TA3DCtlBuffer);
931 ui32LoopCounter += 4) 982 ui32LoopCounter += 4)
932 { 983 {
933 PVR_LOG(("\t(T3C-%X) 0x%08X 0x%08X 0x%08X 0x%08X", ui32LoopCounter * sizeof(*pui32TA3DCtlBuffer), 984 PVR_LOG(("\t(T3C-%X) 0x%08X 0x%08X 0x%08X 0x%08X", ui32LoopCounter * sizeof(*pui32TA3DCtlBuffer),
@@ -995,6 +1046,10 @@ static IMG_VOID SGXDumpDebugInfo (PVRSRV_SGXDEV_INFO *psDevInfo,
995 } 1046 }
996 #endif 1047 #endif
997 } 1048 }
1049 #if defined (TTRACE)
1050 PVRSRVDumpTimeTraceBuffers();
1051 #endif
1052
998} 1053}
999 1054
1000 1055
@@ -1028,36 +1083,35 @@ IMG_VOID HWRecoveryResetSGX (PVRSRV_DEVICE_NODE *psDeviceNode,
1028 1083
1029 SGXDumpDebugInfo(psDeviceNode->pvDevice, IMG_TRUE); 1084 SGXDumpDebugInfo(psDeviceNode->pvDevice, IMG_TRUE);
1030 1085
1031 1086
1032 PDUMPSUSPEND(); 1087 PDUMPSUSPEND();
1033 1088
1034 1089
1035#if defined(FIX_HW_BRN_23281) 1090#if defined(FIX_HW_BRN_23281)
1036 1091
1037 for (eError = PVRSRV_ERROR_RETRY; eError == PVRSRV_ERROR_RETRY;) 1092 for (eError = PVRSRV_ERROR_RETRY; eError == PVRSRV_ERROR_RETRY;)
1038#endif 1093#endif
1039 { 1094 {
1040 eError = SGXInitialise(psDevInfo, IMG_TRUE); 1095 eError = SGXInitialise(psDevInfo, IMG_TRUE);
1041 } 1096 }
1042
1043 if (eError != PVRSRV_OK) 1097 if (eError != PVRSRV_OK)
1044 { 1098 {
1045 PVR_DPF((PVR_DBG_ERROR,"HWRecoveryResetSGX: SGXInitialise failed (%d)", eError)); 1099 PVR_DPF((PVR_DBG_ERROR,"HWRecoveryResetSGX: SGXInitialise failed (%d)", eError));
1046 } 1100 }
1047 1101
1048 1102
1049 PDUMPRESUME(); 1103 PDUMPRESUME();
1050 1104
1051 PVRSRVPowerUnlock(ui32CallerID); 1105 PVRSRVPowerUnlock(ui32CallerID);
1052 1106
1053 1107
1054 SGXScheduleProcessQueuesKM(psDeviceNode); 1108 SGXScheduleProcessQueuesKM(psDeviceNode);
1055 1109
1056 1110
1057 1111
1058 PVRSRVProcessQueues(ui32CallerID, IMG_TRUE); 1112 PVRSRVProcessQueues(IMG_TRUE);
1059} 1113}
1060#endif 1114#endif
1061 1115
1062 1116
1063#if defined(SUPPORT_HW_RECOVERY) 1117#if defined(SUPPORT_HW_RECOVERY)
@@ -1066,7 +1120,7 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
1066 PVRSRV_DEVICE_NODE *psDeviceNode = pvData; 1120 PVRSRV_DEVICE_NODE *psDeviceNode = pvData;
1067 PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; 1121 PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
1068 static IMG_UINT32 ui32EDMTasks = 0; 1122 static IMG_UINT32 ui32EDMTasks = 0;
1069 static IMG_UINT32 ui32LockupCounter = 0; 1123 static IMG_UINT32 ui32LockupCounter = 0;
1070 static IMG_UINT32 ui32NumResets = 0; 1124 static IMG_UINT32 ui32NumResets = 0;
1071#if defined(FIX_HW_BRN_31093) 1125#if defined(FIX_HW_BRN_31093)
1072 static IMG_BOOL bBRN31093Inval = IMG_FALSE; 1126 static IMG_BOOL bBRN31093Inval = IMG_FALSE;
@@ -1075,17 +1129,17 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
1075 IMG_BOOL bLockup = IMG_FALSE; 1129 IMG_BOOL bLockup = IMG_FALSE;
1076 IMG_BOOL bPoweredDown; 1130 IMG_BOOL bPoweredDown;
1077 1131
1078 1132
1079 psDevInfo->ui32TimeStamp++; 1133 psDevInfo->ui32TimeStamp++;
1080 1134
1081#if defined(NO_HARDWARE) 1135#if defined(NO_HARDWARE)
1082 bPoweredDown = IMG_TRUE; 1136 bPoweredDown = IMG_TRUE;
1083#else 1137#else
1084 bPoweredDown = (SGXIsDevicePowered(psDeviceNode)) ? IMG_FALSE : IMG_TRUE; 1138 bPoweredDown = (SGXIsDevicePowered(psDeviceNode)) ? IMG_FALSE : IMG_TRUE;
1085#endif 1139#endif
1086
1087
1088 1140
1141
1142
1089 if (bPoweredDown) 1143 if (bPoweredDown)
1090 { 1144 {
1091 ui32LockupCounter = 0; 1145 ui32LockupCounter = 0;
@@ -1095,7 +1149,7 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
1095 } 1149 }
1096 else 1150 else
1097 { 1151 {
1098 1152
1099 ui32CurrentEDMTasks = OSReadHWReg(psDevInfo->pvRegsBaseKM, psDevInfo->ui32EDMTaskReg0); 1153 ui32CurrentEDMTasks = OSReadHWReg(psDevInfo->pvRegsBaseKM, psDevInfo->ui32EDMTaskReg0);
1100 if (psDevInfo->ui32EDMTaskReg1 != 0) 1154 if (psDevInfo->ui32EDMTaskReg1 != 0)
1101 { 1155 {
@@ -1108,40 +1162,40 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
1108 if (ui32LockupCounter == 3) 1162 if (ui32LockupCounter == 3)
1109 { 1163 {
1110 ui32LockupCounter = 0; 1164 ui32LockupCounter = 0;
1111 1165
1112 #if defined(FIX_HW_BRN_31093) 1166 #if defined(FIX_HW_BRN_31093)
1113 if (bBRN31093Inval == IMG_FALSE) 1167 if (bBRN31093Inval == IMG_FALSE)
1114 { 1168 {
1115 1169
1116 #if defined(FIX_HW_BRN_29997) 1170 #if defined(FIX_HW_BRN_29997)
1117 IMG_UINT32 ui32BIFCtrl; 1171 IMG_UINT32 ui32BIFCtrl;
1118 1172
1119 ui32BIFCtrl = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL); 1173 ui32BIFCtrl = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL);
1120 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32BIFCtrl | EUR_CR_BIF_CTRL_PAUSE_MASK); 1174 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32BIFCtrl | EUR_CR_BIF_CTRL_PAUSE_MASK);
1121 1175
1122 OSWaitus(200 * 1000000 / psDevInfo->ui32CoreClockSpeed); 1176 OSWaitus(200 * 1000000 / psDevInfo->ui32CoreClockSpeed);
1123 #endif 1177 #endif
1124 1178
1125 bBRN31093Inval = IMG_TRUE; 1179 bBRN31093Inval = IMG_TRUE;
1126 1180
1127 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL_INVAL, EUR_CR_BIF_CTRL_INVAL_PTE_MASK); 1181 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL_INVAL, EUR_CR_BIF_CTRL_INVAL_PTE_MASK);
1128 1182
1129 OSWaitus(200 * 1000000 / psDevInfo->ui32CoreClockSpeed); 1183 OSWaitus(200 * 1000000 / psDevInfo->ui32CoreClockSpeed);
1130 1184
1131 #if defined(FIX_HW_BRN_29997) 1185 #if defined(FIX_HW_BRN_29997)
1132 1186
1133 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32BIFCtrl); 1187 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32BIFCtrl);
1134 #endif 1188 #endif
1135 } 1189 }
1136 else 1190 else
1137 #endif 1191 #endif
1138 { 1192 {
1139 PVR_DPF((PVR_DBG_ERROR, "SGXOSTimer() detected SGX lockup (0x%x tasks)", ui32EDMTasks)); 1193 PVR_DPF((PVR_DBG_ERROR, "SGXOSTimer() detected SGX lockup (0x%x tasks)", ui32EDMTasks));
1140 1194
1141 bLockup = IMG_TRUE; 1195 bLockup = IMG_TRUE;
1142 }
1143 } 1196 }
1144 } 1197 }
1198 }
1145 else 1199 else
1146 { 1200 {
1147 #if defined(FIX_HW_BRN_31093) 1201 #if defined(FIX_HW_BRN_31093)
@@ -1157,14 +1211,14 @@ IMG_VOID SGXOSTimer(IMG_VOID *pvData)
1157 { 1211 {
1158 SGXMKIF_HOST_CTL *psSGXHostCtl = (SGXMKIF_HOST_CTL *)psDevInfo->psSGXHostCtl; 1212 SGXMKIF_HOST_CTL *psSGXHostCtl = (SGXMKIF_HOST_CTL *)psDevInfo->psSGXHostCtl;
1159 1213
1160 1214
1161 psSGXHostCtl->ui32HostDetectedLockups ++; 1215 psSGXHostCtl->ui32HostDetectedLockups ++;
1162 1216
1163 1217
1164 HWRecoveryResetSGX(psDeviceNode, 0, KERNEL_ID); 1218 HWRecoveryResetSGX(psDeviceNode, 0, KERNEL_ID);
1165 } 1219 }
1166} 1220}
1167#endif 1221#endif
1168 1222
1169 1223
1170#if defined(SYS_USING_INTERRUPTS) 1224#if defined(SYS_USING_INTERRUPTS)
@@ -1174,18 +1228,18 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData)
1174 IMG_BOOL bInterruptProcessed = IMG_FALSE; 1228 IMG_BOOL bInterruptProcessed = IMG_FALSE;
1175 1229
1176 1230
1177 1231
1178 { 1232 {
1179 IMG_UINT32 ui32EventStatus, ui32EventEnable; 1233 IMG_UINT32 ui32EventStatus, ui32EventEnable;
1180 IMG_UINT32 ui32EventClear = 0; 1234 IMG_UINT32 ui32EventClear = 0;
1181#if defined(SGX_FEATURE_DATA_BREAKPOINTS) 1235#if defined(SGX_FEATURE_DATA_BREAKPOINTS)
1182 IMG_UINT32 ui32EventStatus2, ui32EventEnable2; 1236 IMG_UINT32 ui32EventStatus2, ui32EventEnable2;
1183#endif 1237#endif
1184 IMG_UINT32 ui32EventClear2 = 0; 1238 IMG_UINT32 ui32EventClear2 = 0;
1185 PVRSRV_DEVICE_NODE *psDeviceNode; 1239 PVRSRV_DEVICE_NODE *psDeviceNode;
1186 PVRSRV_SGXDEV_INFO *psDevInfo; 1240 PVRSRV_SGXDEV_INFO *psDevInfo;
1187 1241
1188 1242
1189 if(pvData == IMG_NULL) 1243 if(pvData == IMG_NULL)
1190 { 1244 {
1191 PVR_DPF((PVR_DBG_ERROR, "SGX_ISRHandler: Invalid params\n")); 1245 PVR_DPF((PVR_DBG_ERROR, "SGX_ISRHandler: Invalid params\n"));
@@ -1198,18 +1252,18 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData)
1198 ui32EventStatus = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS); 1252 ui32EventStatus = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS);
1199 ui32EventEnable = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE); 1253 ui32EventEnable = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE);
1200 1254
1201 1255
1202 ui32EventStatus &= ui32EventEnable; 1256 ui32EventStatus &= ui32EventEnable;
1203 1257
1204#if defined(SGX_FEATURE_DATA_BREAKPOINTS) 1258#if defined(SGX_FEATURE_DATA_BREAKPOINTS)
1205 ui32EventStatus2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS2); 1259 ui32EventStatus2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_STATUS2);
1206 ui32EventEnable2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE2); 1260 ui32EventEnable2 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_ENABLE2);
1207 1261
1208 1262
1209 ui32EventStatus2 &= ui32EventEnable2; 1263 ui32EventStatus2 &= ui32EventEnable2;
1210#endif 1264#endif
1211
1212 1265
1266
1213 1267
1214 if (ui32EventStatus & EUR_CR_EVENT_STATUS_SW_EVENT_MASK) 1268 if (ui32EventStatus & EUR_CR_EVENT_STATUS_SW_EVENT_MASK)
1215 { 1269 {
@@ -1226,16 +1280,16 @@ IMG_BOOL SGX_ISRHandler (IMG_VOID *pvData)
1226 { 1280 {
1227 ui32EventClear2 |= EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK; 1281 ui32EventClear2 |= EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK;
1228 } 1282 }
1229#endif 1283#endif
1230 1284
1231 if (ui32EventClear || ui32EventClear2) 1285 if (ui32EventClear || ui32EventClear2)
1232 { 1286 {
1233 bInterruptProcessed = IMG_TRUE; 1287 bInterruptProcessed = IMG_TRUE;
1234 1288
1235 1289
1236 ui32EventClear |= EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK; 1290 ui32EventClear |= EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK;
1237 1291
1238 1292
1239 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR, ui32EventClear); 1293 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR, ui32EventClear);
1240 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2, ui32EventClear2); 1294 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_EVENT_HOST_CLEAR2, ui32EventClear2);
1241 } 1295 }
@@ -1266,7 +1320,7 @@ static IMG_VOID SGX_MISRHandler (IMG_VOID *pvData)
1266 1320
1267 SGXTestActivePowerEvent(psDeviceNode, ISR_ID); 1321 SGXTestActivePowerEvent(psDeviceNode, ISR_ID);
1268} 1322}
1269#endif 1323#endif
1270 1324
1271 1325
1272 1326
@@ -1284,14 +1338,14 @@ PVRSRV_ERROR SGX_AllocMemTilingRange(PVRSRV_DEVICE_NODE *psDeviceNode,
1284 IMG_UINT32 ui32Offset; 1338 IMG_UINT32 ui32Offset;
1285 IMG_UINT32 ui32Val; 1339 IMG_UINT32 ui32Val;
1286 1340
1287 1341
1288 for(i=0; i<10; i++) 1342 for(i=0; i<10; i++)
1289 { 1343 {
1290 if((psDevInfo->ui32MemTilingUsage & (1U << i)) == 0) 1344 if((psDevInfo->ui32MemTilingUsage & (1U << i)) == 0)
1291 { 1345 {
1292 1346
1293 psDevInfo->ui32MemTilingUsage |= 1U << i; 1347 psDevInfo->ui32MemTilingUsage |= 1U << i;
1294 1348
1295 *pui32RangeIndex = i; 1349 *pui32RangeIndex = i;
1296 goto RangeAllocated; 1350 goto RangeAllocated;
1297 } 1351 }
@@ -1304,14 +1358,14 @@ RangeAllocated:
1304 ui32Offset = EUR_CR_BIF_TILE0 + (i<<2); 1358 ui32Offset = EUR_CR_BIF_TILE0 + (i<<2);
1305 1359
1306 ui32Start = psMemInfo->sDevVAddr.uiAddr; 1360 ui32Start = psMemInfo->sDevVAddr.uiAddr;
1307 ui32End = ui32Start + psMemInfo->ui32AllocSize + SGX_MMU_PAGE_SIZE - 1; 1361 ui32End = ui32Start + psMemInfo->uAllocSize + SGX_MMU_PAGE_SIZE - 1;
1308 1362
1309 ui32Val = ((ui32TilingStride << EUR_CR_BIF_TILE0_CFG_SHIFT) & EUR_CR_BIF_TILE0_CFG_MASK) 1363 ui32Val = ((ui32TilingStride << EUR_CR_BIF_TILE0_CFG_SHIFT) & EUR_CR_BIF_TILE0_CFG_MASK)
1310 | (((ui32End>>20) << EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT) & EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK) 1364 | (((ui32End>>20) << EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT) & EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK)
1311 | (((ui32Start>>20) << EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT) & EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK) 1365 | (((ui32Start>>20) << EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT) & EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK)
1312 | (0x8 << EUR_CR_BIF_TILE0_CFG_SHIFT); 1366 | (0x8 << EUR_CR_BIF_TILE0_CFG_SHIFT);
1313 1367
1314 1368
1315 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val); 1369 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val);
1316 PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val); 1370 PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val);
1317 1371
@@ -1320,7 +1374,7 @@ RangeAllocated:
1320 ui32Val = (((ui32End>>12) << EUR_CR_BIF_TILE0_ADDR_EXT_MAX_SHIFT) & EUR_CR_BIF_TILE0_ADDR_EXT_MAX_MASK) 1374 ui32Val = (((ui32End>>12) << EUR_CR_BIF_TILE0_ADDR_EXT_MAX_SHIFT) & EUR_CR_BIF_TILE0_ADDR_EXT_MAX_MASK)
1321 | (((ui32Start>>12) << EUR_CR_BIF_TILE0_ADDR_EXT_MIN_SHIFT) & EUR_CR_BIF_TILE0_ADDR_EXT_MIN_MASK); 1375 | (((ui32Start>>12) << EUR_CR_BIF_TILE0_ADDR_EXT_MIN_SHIFT) & EUR_CR_BIF_TILE0_ADDR_EXT_MIN_MASK);
1322 1376
1323 1377
1324 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val); 1378 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val);
1325 PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val); 1379 PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val);
1326 1380
@@ -1350,14 +1404,14 @@ PVRSRV_ERROR SGX_FreeMemTilingRange(PVRSRV_DEVICE_NODE *psDeviceNode,
1350 return PVRSRV_ERROR_INVALID_PARAMS; 1404 return PVRSRV_ERROR_INVALID_PARAMS;
1351 } 1405 }
1352 1406
1353 1407
1354 psDevInfo->ui32MemTilingUsage &= ~(1<<ui32RangeIndex); 1408 psDevInfo->ui32MemTilingUsage &= ~(1<<ui32RangeIndex);
1355 1409
1356 1410
1357 ui32Offset = EUR_CR_BIF_TILE0 + (ui32RangeIndex<<2); 1411 ui32Offset = EUR_CR_BIF_TILE0 + (ui32RangeIndex<<2);
1358 ui32Val = 0; 1412 ui32Val = 0;
1359 1413
1360 1414
1361 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val); 1415 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32Offset, ui32Val);
1362 PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val); 1416 PDUMPREG(SGX_PDUMPREG_NAME, ui32Offset, ui32Val);
1363 1417
@@ -1378,12 +1432,12 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1378 DEVICE_MEMORY_INFO *psDevMemoryInfo; 1432 DEVICE_MEMORY_INFO *psDevMemoryInfo;
1379 DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap; 1433 DEVICE_MEMORY_HEAP_INFO *psDeviceMemoryHeap;
1380 1434
1381 1435
1382 psDeviceNode->sDevId.eDeviceType = DEV_DEVICE_TYPE; 1436 psDeviceNode->sDevId.eDeviceType = DEV_DEVICE_TYPE;
1383 psDeviceNode->sDevId.eDeviceClass = DEV_DEVICE_CLASS; 1437 psDeviceNode->sDevId.eDeviceClass = DEV_DEVICE_CLASS;
1384#if defined(PDUMP) 1438#if defined(PDUMP)
1385 { 1439 {
1386 1440
1387 SGX_DEVICE_MAP *psSGXDeviceMemMap; 1441 SGX_DEVICE_MAP *psSGXDeviceMemMap;
1388 SysGetDeviceMemoryMap(PVRSRV_DEVICE_TYPE_SGX, 1442 SysGetDeviceMemoryMap(PVRSRV_DEVICE_TYPE_SGX,
1389 (IMG_VOID**)&psSGXDeviceMemMap); 1443 (IMG_VOID**)&psSGXDeviceMemMap);
@@ -1391,9 +1445,9 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1391 psDeviceNode->sDevId.pszPDumpDevName = psSGXDeviceMemMap->pszPDumpDevName; 1445 psDeviceNode->sDevId.pszPDumpDevName = psSGXDeviceMemMap->pszPDumpDevName;
1392 PVR_ASSERT(psDeviceNode->sDevId.pszPDumpDevName != IMG_NULL); 1446 PVR_ASSERT(psDeviceNode->sDevId.pszPDumpDevName != IMG_NULL);
1393 } 1447 }
1394 1448
1395 psDeviceNode->sDevId.pszPDumpRegName = SGX_PDUMPREG_NAME; 1449 psDeviceNode->sDevId.pszPDumpRegName = SGX_PDUMPREG_NAME;
1396#endif 1450#endif
1397 1451
1398 psDeviceNode->pfnInitDevice = &DevInitSGXPart1; 1452 psDeviceNode->pfnInitDevice = &DevInitSGXPart1;
1399 psDeviceNode->pfnDeInitDevice = &DevDeInitSGX; 1453 psDeviceNode->pfnDeInitDevice = &DevDeInitSGX;
@@ -1403,7 +1457,7 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1403 psDeviceNode->pfnPDumpInitDevice = &SGXResetPDump; 1457 psDeviceNode->pfnPDumpInitDevice = &SGXResetPDump;
1404 psDeviceNode->pfnMMUGetContextID = &MMU_GetPDumpContextID; 1458 psDeviceNode->pfnMMUGetContextID = &MMU_GetPDumpContextID;
1405#endif 1459#endif
1406 1460
1407 1461
1408 psDeviceNode->pfnMMUInitialise = &MMU_Initialise; 1462 psDeviceNode->pfnMMUInitialise = &MMU_Initialise;
1409 psDeviceNode->pfnMMUFinalise = &MMU_Finalise; 1463 psDeviceNode->pfnMMUFinalise = &MMU_Finalise;
@@ -1421,9 +1475,15 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1421#if defined(SUPPORT_PDUMP_MULTI_PROCESS) 1475#if defined(SUPPORT_PDUMP_MULTI_PROCESS)
1422 psDeviceNode->pfnMMUIsHeapShared = &MMU_IsHeapShared; 1476 psDeviceNode->pfnMMUIsHeapShared = &MMU_IsHeapShared;
1423#endif 1477#endif
1424 1478#if defined(FIX_HW_BRN_31620)
1479 psDeviceNode->pfnMMUGetCacheFlushRange = &MMU_GetCacheFlushRange;
1480 psDeviceNode->pfnMMUGetPDPhysAddr = &MMU_GetPDPhysAddr;
1481#else
1482 psDeviceNode->pfnMMUGetCacheFlushRange = IMG_NULL;
1483 psDeviceNode->pfnMMUGetPDPhysAddr = IMG_NULL;
1484#endif
1425#if defined (SYS_USING_INTERRUPTS) 1485#if defined (SYS_USING_INTERRUPTS)
1426 1486
1427 1487
1428 psDeviceNode->pfnDeviceISR = SGX_ISRHandler; 1488 psDeviceNode->pfnDeviceISR = SGX_ISRHandler;
1429 psDeviceNode->pfnDeviceMISR = SGX_MISRHandler; 1489 psDeviceNode->pfnDeviceMISR = SGX_MISRHandler;
@@ -1434,20 +1494,20 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1434 psDeviceNode->pfnFreeMemTilingRange = SGX_FreeMemTilingRange; 1494 psDeviceNode->pfnFreeMemTilingRange = SGX_FreeMemTilingRange;
1435#endif 1495#endif
1436 1496
1437 1497
1438 1498
1439 psDeviceNode->pfnDeviceCommandComplete = &SGXCommandComplete; 1499 psDeviceNode->pfnDeviceCommandComplete = &SGXCommandComplete;
1440 1500
1441 1501
1442 1502
1443 psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo; 1503 psDevMemoryInfo = &psDeviceNode->sDevMemoryInfo;
1444 1504
1445 psDevMemoryInfo->ui32AddressSpaceSizeLog2 = SGX_FEATURE_ADDRESS_SPACE_SIZE; 1505 psDevMemoryInfo->ui32AddressSpaceSizeLog2 = SGX_FEATURE_ADDRESS_SPACE_SIZE;
1446 1506
1447 1507
1448 psDevMemoryInfo->ui32Flags = 0; 1508 psDevMemoryInfo->ui32Flags = 0;
1449 1509
1450 1510
1451 if(OSAllocMem( PVRSRV_OS_PAGEABLE_HEAP, 1511 if(OSAllocMem( PVRSRV_OS_PAGEABLE_HEAP,
1452 sizeof(DEVICE_MEMORY_HEAP_INFO) * SGX_MAX_HEAP_ID, 1512 sizeof(DEVICE_MEMORY_HEAP_INFO) * SGX_MAX_HEAP_ID,
1453 (IMG_VOID **)&psDevMemoryInfo->psDeviceMemoryHeap, 0, 1513 (IMG_VOID **)&psDevMemoryInfo->psDeviceMemoryHeap, 0,
@@ -1460,7 +1520,10 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1460 1520
1461 psDeviceMemoryHeap = psDevMemoryInfo->psDeviceMemoryHeap; 1521 psDeviceMemoryHeap = psDevMemoryInfo->psDeviceMemoryHeap;
1462 1522
1523
1524
1463 1525
1526
1464 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_GENERAL_HEAP_ID); 1527 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_GENERAL_HEAP_ID);
1465 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_GENERAL_HEAP_BASE; 1528 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_GENERAL_HEAP_BASE;
1466 psDeviceMemoryHeap->ui32HeapSize = SGX_GENERAL_HEAP_SIZE; 1529 psDeviceMemoryHeap->ui32HeapSize = SGX_GENERAL_HEAP_SIZE;
@@ -1470,16 +1533,16 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1470 psDeviceMemoryHeap->pszName = "General"; 1533 psDeviceMemoryHeap->pszName = "General";
1471 psDeviceMemoryHeap->pszBSName = "General BS"; 1534 psDeviceMemoryHeap->pszBSName = "General BS";
1472 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT; 1535 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT;
1473 1536
1474 psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE; 1537 psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE;
1475#if !defined(SUPPORT_SGX_GENERAL_MAPPING_HEAP) 1538#if !defined(SUPPORT_SGX_GENERAL_MAPPING_HEAP)
1476 1539
1477 psDevMemoryInfo->ui32MappingHeapID = (IMG_UINT32)(psDeviceMemoryHeap - psDevMemoryInfo->psDeviceMemoryHeap); 1540 psDevMemoryInfo->ui32MappingHeapID = (IMG_UINT32)(psDeviceMemoryHeap - psDevMemoryInfo->psDeviceMemoryHeap);
1478#endif 1541#endif
1479 psDeviceMemoryHeap++; 1542 psDeviceMemoryHeap++;
1480 1543
1481 1544
1482 1545
1483 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_TADATA_HEAP_ID); 1546 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_TADATA_HEAP_ID);
1484 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_TADATA_HEAP_BASE; 1547 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_TADATA_HEAP_BASE;
1485 psDeviceMemoryHeap->ui32HeapSize = SGX_TADATA_HEAP_SIZE; 1548 psDeviceMemoryHeap->ui32HeapSize = SGX_TADATA_HEAP_SIZE;
@@ -1489,12 +1552,12 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1489 psDeviceMemoryHeap->pszName = "TA Data"; 1552 psDeviceMemoryHeap->pszName = "TA Data";
1490 psDeviceMemoryHeap->pszBSName = "TA Data BS"; 1553 psDeviceMemoryHeap->pszBSName = "TA Data BS";
1491 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT; 1554 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT;
1492 1555
1493 psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE; 1556 psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE;
1494 psDeviceMemoryHeap++; 1557 psDeviceMemoryHeap++;
1495 1558
1496 1559
1497 1560
1498 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_KERNEL_CODE_HEAP_ID); 1561 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_KERNEL_CODE_HEAP_ID);
1499 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_KERNEL_CODE_HEAP_BASE; 1562 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_KERNEL_CODE_HEAP_BASE;
1500 psDeviceMemoryHeap->ui32HeapSize = SGX_KERNEL_CODE_HEAP_SIZE; 1563 psDeviceMemoryHeap->ui32HeapSize = SGX_KERNEL_CODE_HEAP_SIZE;
@@ -1611,22 +1674,30 @@ PVRSRV_ERROR SGXRegisterDevice (PVRSRV_DEVICE_NODE *psDeviceNode)
1611 1674
1612 1675
1613 1676
1614 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_3DPARAMETERS_HEAP_ID); 1677 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_SHARED_3DPARAMETERS_HEAP_ID);
1615 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_3DPARAMETERS_HEAP_BASE; 1678 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_SHARED_3DPARAMETERS_HEAP_BASE;
1616 psDeviceMemoryHeap->ui32HeapSize = SGX_3DPARAMETERS_HEAP_SIZE; 1679 psDeviceMemoryHeap->ui32HeapSize = SGX_SHARED_3DPARAMETERS_HEAP_SIZE;
1617 psDeviceMemoryHeap->pszName = "3DParameters"; 1680 psDeviceMemoryHeap->pszName = "Shared 3DParameters";
1618 psDeviceMemoryHeap->pszBSName = "3DParameters BS"; 1681 psDeviceMemoryHeap->pszBSName = "Shared 3DParameters BS";
1619#if defined(SUPPORT_PERCONTEXT_PB)
1620 psDeviceMemoryHeap->ui32Attribs = PVRSRV_HAP_WRITECOMBINE
1621 | PVRSRV_MEM_RAM_BACKED_ALLOCATION
1622 | PVRSRV_HAP_SINGLE_PROCESS;
1623 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT;
1624#else
1625 psDeviceMemoryHeap->ui32Attribs = PVRSRV_HAP_WRITECOMBINE 1682 psDeviceMemoryHeap->ui32Attribs = PVRSRV_HAP_WRITECOMBINE
1626 | PVRSRV_MEM_RAM_BACKED_ALLOCATION 1683 | PVRSRV_MEM_RAM_BACKED_ALLOCATION
1627 | PVRSRV_HAP_MULTI_PROCESS; 1684 | PVRSRV_HAP_MULTI_PROCESS;
1628 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_SHARED_EXPORTED; 1685 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_SHARED_EXPORTED;
1629#endif 1686
1687
1688 psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE;
1689 psDeviceMemoryHeap++;
1690
1691
1692 psDeviceMemoryHeap->ui32HeapID = HEAP_ID( PVRSRV_DEVICE_TYPE_SGX, SGX_PERCONTEXT_3DPARAMETERS_HEAP_ID);
1693 psDeviceMemoryHeap->sDevVAddrBase.uiAddr = SGX_PERCONTEXT_3DPARAMETERS_HEAP_BASE;
1694 psDeviceMemoryHeap->ui32HeapSize = SGX_PERCONTEXT_3DPARAMETERS_HEAP_SIZE;
1695 psDeviceMemoryHeap->pszName = "Percontext 3DParameters";
1696 psDeviceMemoryHeap->pszBSName = "Percontext 3DParameters BS";
1697 psDeviceMemoryHeap->ui32Attribs = PVRSRV_HAP_WRITECOMBINE
1698 | PVRSRV_MEM_RAM_BACKED_ALLOCATION
1699 | PVRSRV_HAP_SINGLE_PROCESS;
1700 psDeviceMemoryHeap->DevMemHeapType = DEVICE_MEMORY_HEAP_PERCONTEXT;
1630 1701
1631 psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE; 1702 psDeviceMemoryHeap->ui32DataPageSize = SGX_MMU_PAGE_SIZE;
1632 psDeviceMemoryHeap++; 1703 psDeviceMemoryHeap++;
@@ -1813,7 +1884,7 @@ PVRSRV_ERROR SGXDevInitCompatCheck(PVRSRV_DEVICE_NODE *psDeviceNode)
1813 psSGXMiscInfoInt = psMemInfo->pvLinAddrKM; 1884 psSGXMiscInfoInt = psMemInfo->pvLinAddrKM;
1814 psSGXMiscInfoInt->ui32MiscInfoFlags = 0; 1885 psSGXMiscInfoInt->ui32MiscInfoFlags = 0;
1815 psSGXMiscInfoInt->ui32MiscInfoFlags |= PVRSRV_USSE_MISCINFO_GET_STRUCT_SIZES; 1886 psSGXMiscInfoInt->ui32MiscInfoFlags |= PVRSRV_USSE_MISCINFO_GET_STRUCT_SIZES;
1816 eError = SGXGetMiscInfoUkernel(psDevInfo, psDeviceNode); 1887 eError = SGXGetMiscInfoUkernel(psDevInfo, psDeviceNode, IMG_NULL);
1817 1888
1818 1889
1819 if(eError != PVRSRV_OK) 1890 if(eError != PVRSRV_OK)
@@ -1954,7 +2025,8 @@ chk_exit:
1954 2025
1955static 2026static
1956PVRSRV_ERROR SGXGetMiscInfoUkernel(PVRSRV_SGXDEV_INFO *psDevInfo, 2027PVRSRV_ERROR SGXGetMiscInfoUkernel(PVRSRV_SGXDEV_INFO *psDevInfo,
1957 PVRSRV_DEVICE_NODE *psDeviceNode) 2028 PVRSRV_DEVICE_NODE *psDeviceNode,
2029 IMG_HANDLE hDevMemContext)
1958{ 2030{
1959 PVRSRV_ERROR eError; 2031 PVRSRV_ERROR eError;
1960 SGXMKIF_COMMAND sCommandData; 2032 SGXMKIF_COMMAND sCommandData;
@@ -1988,6 +2060,7 @@ PVRSRV_ERROR SGXGetMiscInfoUkernel(PVRSRV_SGXDEV_INFO *psDevInfo,
1988 &sCommandData, 2060 &sCommandData,
1989 KERNEL_ID, 2061 KERNEL_ID,
1990 0, 2062 0,
2063 hDevMemContext,
1991 IMG_FALSE); 2064 IMG_FALSE);
1992 2065
1993 if (eError != PVRSRV_OK) 2066 if (eError != PVRSRV_OK)
@@ -2099,6 +2172,7 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2099 &sCommandData, 2172 &sCommandData,
2100 KERNEL_ID, 2173 KERNEL_ID,
2101 0, 2174 0,
2175 hDevMemContext,
2102 IMG_FALSE); 2176 IMG_FALSE);
2103 2177
2104 if (eError != PVRSRV_OK) 2178 if (eError != PVRSRV_OK)
@@ -2138,37 +2212,6 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2138 return PVRSRV_OK; 2212 return PVRSRV_OK;
2139 } 2213 }
2140 2214
2141 case SGX_MISC_INFO_REQUEST_WAIT_FOR_BREAKPOINT:
2142 {
2143
2144
2145 PDUMPCOMMENT("Wait for data breakpoint hit");
2146
2147#if defined(NO_HARDWARE) && defined(PDUMP)
2148 {
2149 PDUMPREGPOL(SGX_PDUMPREG_NAME,
2150 EUR_CR_EVENT_STATUS2,
2151 EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_MASK,
2152 EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_MASK);
2153
2154 PDUMPREG(SGX_PDUMPREG_NAME,
2155 EUR_CR_EVENT_HOST_CLEAR2,
2156 EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK);
2157
2158 PDUMPCOMMENT("Breakpoint detected. Wait a bit to show that pipeline stops in simulation");
2159 PDUMPIDL(2000);
2160
2161 PDUMPCOMMENT("Now we can resume");
2162 PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_BREAKPOINT_TRAP, EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_MASK | EUR_CR_BREAKPOINT_TRAP_CONTINUE_MASK);
2163 }
2164#else
2165 {
2166
2167 }
2168#endif
2169 return PVRSRV_OK;
2170 }
2171
2172 case SGX_MISC_INFO_REQUEST_POLL_BREAKPOINT: 2215 case SGX_MISC_INFO_REQUEST_POLL_BREAKPOINT:
2173 { 2216 {
2174 2217
@@ -2179,40 +2222,114 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2179 2222
2180 2223
2181#if !defined(NO_HARDWARE) 2224#if !defined(NO_HARDWARE)
2225#if defined(SGX_FEATURE_MP)
2182 IMG_BOOL bTrappedBPMaster; 2226 IMG_BOOL bTrappedBPMaster;
2183 IMG_BOOL abTrappedBPPerCore[SGX_FEATURE_MP_CORE_COUNT];
2184 IMG_UINT32 ui32CoreNum, ui32TrappedBPCoreNum; 2227 IMG_UINT32 ui32CoreNum, ui32TrappedBPCoreNum;
2228#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2229 IMG_UINT32 ui32PipeNum, ui32TrappedBPPipeNum;
2230#define NUM_PIPES_PLUS_ONE (SGX_FEATURE_PERPIPE_BKPT_REGS_NUMPIPES+1)
2231#endif
2185 IMG_BOOL bTrappedBPAny; 2232 IMG_BOOL bTrappedBPAny;
2233#endif
2234 IMG_BOOL bFoundOne;
2186 2235
2236#if defined(SGX_FEATURE_MP)
2187 ui32TrappedBPCoreNum = 0; 2237 ui32TrappedBPCoreNum = 0;
2188 bTrappedBPMaster = !!(EUR_CR_MASTER_BREAKPOINT_TRAPPED_MASK & OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BREAKPOINT)); 2238 bTrappedBPMaster = !!(EUR_CR_MASTER_BREAKPOINT_TRAPPED_MASK & OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BREAKPOINT));
2189 bTrappedBPAny = bTrappedBPMaster; 2239 bTrappedBPAny = bTrappedBPMaster;
2190 for (ui32CoreNum = 0; ui32CoreNum < SGX_FEATURE_MP_CORE_COUNT; ui32CoreNum++) 2240#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2241 ui32TrappedBPPipeNum = 0;
2242#endif
2243 for (ui32CoreNum = 0; ui32CoreNum < SGX_FEATURE_MP_CORE_COUNT_3D; ui32CoreNum++)
2191 { 2244 {
2192 abTrappedBPPerCore[ui32CoreNum] = !!(EUR_CR_BREAKPOINT_TRAPPED_MASK & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT, ui32CoreNum))); 2245#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2193 if (abTrappedBPPerCore[ui32CoreNum]) 2246
2247
2248
2249#define SGX_MP_CORE_PIPE_SELECT(r,c,p) \
2250 ((SGX_MP_CORE_SELECT(EUR_CR_PARTITION_##r,c) + p*(EUR_CR_PIPE0_##r-EUR_CR_PARTITION_##r)))
2251 for (ui32PipeNum = 0; ui32PipeNum < NUM_PIPES_PLUS_ONE; ui32PipeNum++)
2252 {
2253 bFoundOne =
2254 0 != (EUR_CR_PARTITION_BREAKPOINT_TRAPPED_MASK &
2255 OSReadHWReg(psDevInfo->pvRegsBaseKM,
2256 SGX_MP_CORE_PIPE_SELECT(BREAKPOINT,
2257 ui32CoreNum,
2258 ui32PipeNum)));
2259 if (bFoundOne)
2260 {
2261 bTrappedBPAny = IMG_TRUE;
2262 ui32TrappedBPCoreNum = ui32CoreNum;
2263 ui32TrappedBPPipeNum = ui32PipeNum;
2264 }
2265 }
2266#else
2267 bFoundOne = !!(EUR_CR_BREAKPOINT_TRAPPED_MASK & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT, ui32CoreNum)));
2268 if (bFoundOne)
2194 { 2269 {
2195 bTrappedBPAny = IMG_TRUE; 2270 bTrappedBPAny = IMG_TRUE;
2196 ui32TrappedBPCoreNum = ui32CoreNum; 2271 ui32TrappedBPCoreNum = ui32CoreNum;
2197 } 2272 }
2273#endif
2198 } 2274 }
2199 2275
2200 psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBP = bTrappedBPAny; 2276 psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBP = bTrappedBPAny;
2277#else
2278#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2279 #error Not yet considered the case for per-pipe regs in non-mp case
2280#endif
2281 psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBP = 0 != (EUR_CR_BREAKPOINT_TRAPPED_MASK & OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BREAKPOINT));
2282#endif
2201 2283
2202 if (psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBP) 2284 if (psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBP)
2203 { 2285 {
2204 IMG_UINT32 ui32Info0, ui32Info1; 2286 IMG_UINT32 ui32Info0, ui32Info1;
2205 2287
2288#if defined(SGX_FEATURE_MP)
2289#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2290 ui32Info0 = OSReadHWReg(psDevInfo->pvRegsBaseKM, bTrappedBPMaster?EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0:SGX_MP_CORE_PIPE_SELECT(BREAKPOINT_TRAP_INFO0, ui32TrappedBPCoreNum, ui32TrappedBPPipeNum));
2291 ui32Info1 = OSReadHWReg(psDevInfo->pvRegsBaseKM, bTrappedBPMaster?EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1:SGX_MP_CORE_PIPE_SELECT(BREAKPOINT_TRAP_INFO1, ui32TrappedBPCoreNum, ui32TrappedBPPipeNum));
2292#else
2206 ui32Info0 = OSReadHWReg(psDevInfo->pvRegsBaseKM, bTrappedBPMaster?EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0:SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT_TRAP_INFO0, ui32TrappedBPCoreNum)); 2293 ui32Info0 = OSReadHWReg(psDevInfo->pvRegsBaseKM, bTrappedBPMaster?EUR_CR_MASTER_BREAKPOINT_TRAP_INFO0:SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT_TRAP_INFO0, ui32TrappedBPCoreNum));
2207 ui32Info1 = OSReadHWReg(psDevInfo->pvRegsBaseKM, bTrappedBPMaster?EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1:SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT_TRAP_INFO1, ui32TrappedBPCoreNum)); 2294 ui32Info1 = OSReadHWReg(psDevInfo->pvRegsBaseKM, bTrappedBPMaster?EUR_CR_MASTER_BREAKPOINT_TRAP_INFO1:SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT_TRAP_INFO1, ui32TrappedBPCoreNum));
2295#endif
2296#else
2297 ui32Info0 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BREAKPOINT_TRAP_INFO0);
2298 ui32Info1 = OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BREAKPOINT_TRAP_INFO1);
2299#endif
2208 2300
2301#ifdef SGX_FEATURE_PERPIPE_BKPT_REGS
2302 psMiscInfo->uData.sSGXBreakpointInfo.ui32BPIndex = (ui32Info1 & EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_MASK) >> EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT;
2303 psMiscInfo->uData.sSGXBreakpointInfo.sTrappedBPDevVAddr.uiAddr = ui32Info0 & EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK;
2304 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPBurstLength = (ui32Info1 & EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_MASK) >> EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT;
2305 psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBPRead = !!(ui32Info1 & EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_MASK);
2306 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPDataMaster = (ui32Info1 & EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK) >> EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT;
2307 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPTag = (ui32Info1 & EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_MASK) >> EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_SHIFT;
2308#else
2209 psMiscInfo->uData.sSGXBreakpointInfo.ui32BPIndex = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT; 2309 psMiscInfo->uData.sSGXBreakpointInfo.ui32BPIndex = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT;
2210 psMiscInfo->uData.sSGXBreakpointInfo.sTrappedBPDevVAddr.uiAddr = ui32Info0 & EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK; 2310 psMiscInfo->uData.sSGXBreakpointInfo.sTrappedBPDevVAddr.uiAddr = ui32Info0 & EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK;
2211 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPBurstLength = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT; 2311 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPBurstLength = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT;
2212 psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBPRead = !!(ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_MASK); 2312 psMiscInfo->uData.sSGXBreakpointInfo.bTrappedBPRead = !!(ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_MASK);
2213 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPDataMaster = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT; 2313 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPDataMaster = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT;
2214 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPTag = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_SHIFT; 2314 psMiscInfo->uData.sSGXBreakpointInfo.ui32TrappedBPTag = (ui32Info1 & EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_MASK) >> EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_SHIFT;
2315#endif
2316#if defined(SGX_FEATURE_MP)
2317#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2318
2319 psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum = bTrappedBPMaster?65535:(ui32TrappedBPCoreNum + (ui32TrappedBPPipeNum<<10));
2320#else
2321
2215 psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum = bTrappedBPMaster?65535:ui32TrappedBPCoreNum; 2322 psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum = bTrappedBPMaster?65535:ui32TrappedBPCoreNum;
2323#endif
2324#else
2325#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2326
2327#error non-mp perpipe regs not yet supported
2328#else
2329
2330 psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum = 65534;
2331#endif
2332#endif
2216 } 2333 }
2217#endif 2334#endif
2218 return PVRSRV_OK; 2335 return PVRSRV_OK;
@@ -2224,12 +2341,24 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2224 2341
2225 2342
2226#if !defined(NO_HARDWARE) 2343#if !defined(NO_HARDWARE)
2344#if defined(SGX_FEATURE_MP)
2227 IMG_UINT32 ui32CoreNum; 2345 IMG_UINT32 ui32CoreNum;
2228 IMG_BOOL bMaster; 2346 IMG_BOOL bMaster;
2347#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2348 IMG_UINT32 ui32PipeNum;
2349#endif
2350#endif
2229 IMG_UINT32 ui32OldSeqNum, ui32NewSeqNum; 2351 IMG_UINT32 ui32OldSeqNum, ui32NewSeqNum;
2230 2352
2353#if defined(SGX_FEATURE_MP)
2354#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2355 ui32PipeNum = psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum >> 10;
2356 ui32CoreNum = psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum & 1023;
2357 bMaster = psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum > 32767;
2358#else
2231 ui32CoreNum = psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum; 2359 ui32CoreNum = psMiscInfo->uData.sSGXBreakpointInfo.ui32CoreNum;
2232 bMaster = ui32CoreNum > SGX_FEATURE_MP_CORE_COUNT; 2360 bMaster = ui32CoreNum > SGX_FEATURE_MP_CORE_COUNT_3D;
2361#endif
2233 if (bMaster) 2362 if (bMaster)
2234 { 2363 {
2235 2364
@@ -2243,8 +2372,18 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2243 while (ui32OldSeqNum == ui32NewSeqNum); 2372 while (ui32OldSeqNum == ui32NewSeqNum);
2244 } 2373 }
2245 else 2374 else
2375#endif
2246 { 2376 {
2247 2377
2378#if defined(SGX_FEATURE_PERPIPE_BKPT_REGS)
2379 ui32OldSeqNum = 0x1c & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_PIPE_SELECT(BREAKPOINT, ui32CoreNum, ui32PipeNum));
2380 OSWriteHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_PIPE_SELECT(BREAKPOINT_TRAP, ui32CoreNum, ui32PipeNum), EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_MASK | EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_MASK);
2381 do
2382 {
2383 ui32NewSeqNum = 0x1c & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_PIPE_SELECT(BREAKPOINT, ui32CoreNum, ui32PipeNum));
2384 }
2385 while (ui32OldSeqNum == ui32NewSeqNum);
2386#else
2248 ui32OldSeqNum = 0x1c & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT, ui32CoreNum)); 2387 ui32OldSeqNum = 0x1c & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT, ui32CoreNum));
2249 OSWriteHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT_TRAP, ui32CoreNum), EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_MASK | EUR_CR_BREAKPOINT_TRAP_CONTINUE_MASK); 2388 OSWriteHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT_TRAP, ui32CoreNum), EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_MASK | EUR_CR_BREAKPOINT_TRAP_CONTINUE_MASK);
2250 do 2389 do
@@ -2252,6 +2391,7 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2252 ui32NewSeqNum = 0x1c & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT, ui32CoreNum)); 2391 ui32NewSeqNum = 0x1c & OSReadHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BREAKPOINT, ui32CoreNum));
2253 } 2392 }
2254 while (ui32OldSeqNum == ui32NewSeqNum); 2393 while (ui32OldSeqNum == ui32NewSeqNum);
2394#endif
2255 } 2395 }
2256#endif 2396#endif
2257 return PVRSRV_OK; 2397 return PVRSRV_OK;
@@ -2291,7 +2431,7 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2291 case SGX_MISC_INFO_REQUEST_SGXREV: 2431 case SGX_MISC_INFO_REQUEST_SGXREV:
2292 { 2432 {
2293 PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures; 2433 PVRSRV_SGX_MISCINFO_FEATURES *psSGXFeatures;
2294 eError = SGXGetMiscInfoUkernel(psDevInfo, psDeviceNode); 2434 eError = SGXGetMiscInfoUkernel(psDevInfo, psDeviceNode, hDevMemContext);
2295 if(eError != PVRSRV_OK) 2435 if(eError != PVRSRV_OK)
2296 { 2436 {
2297 PVR_DPF((PVR_DBG_ERROR, "An error occurred in SGXGetMiscInfoUkernel: %d\n", 2437 PVR_DPF((PVR_DBG_ERROR, "An error occurred in SGXGetMiscInfoUkernel: %d\n",
@@ -2481,6 +2621,7 @@ PVRSRV_ERROR SGXGetMiscInfoKM(PVRSRV_SGXDEV_INFO *psDevInfo,
2481 &sCommandData, 2621 &sCommandData,
2482 KERNEL_ID, 2622 KERNEL_ID,
2483 0, 2623 0,
2624 hDevMemContext,
2484 IMG_FALSE); 2625 IMG_FALSE);
2485 return eError; 2626 return eError;
2486 } 2627 }
@@ -2535,6 +2676,8 @@ PVRSRV_ERROR SGXReadHWPerfCBKM(IMG_HANDLE hDevHandle,
2535 SGXMKIF_HWPERF_CB_ENTRY *psMKPerfEntry = &psHWPerfCB->psHWPerfCBData[psHWPerfCB->ui32Roff]; 2676 SGXMKIF_HWPERF_CB_ENTRY *psMKPerfEntry = &psHWPerfCB->psHWPerfCBData[psHWPerfCB->ui32Roff];
2536 2677
2537 psClientHWPerfEntry[i].ui32FrameNo = psMKPerfEntry->ui32FrameNo; 2678 psClientHWPerfEntry[i].ui32FrameNo = psMKPerfEntry->ui32FrameNo;
2679 psClientHWPerfEntry[i].ui32PID = psMKPerfEntry->ui32PID;
2680 psClientHWPerfEntry[i].ui32RTData = psMKPerfEntry->ui32RTData;
2538 psClientHWPerfEntry[i].ui32Type = psMKPerfEntry->ui32Type; 2681 psClientHWPerfEntry[i].ui32Type = psMKPerfEntry->ui32Type;
2539 psClientHWPerfEntry[i].ui32Ordinal = psMKPerfEntry->ui32Ordinal; 2682 psClientHWPerfEntry[i].ui32Ordinal = psMKPerfEntry->ui32Ordinal;
2540 psClientHWPerfEntry[i].ui32Info = psMKPerfEntry->ui32Info; 2683 psClientHWPerfEntry[i].ui32Info = psMKPerfEntry->ui32Info;
@@ -2545,6 +2688,10 @@ PVRSRV_ERROR SGXReadHWPerfCBKM(IMG_HANDLE hDevHandle,
2545 &psMKPerfEntry->ui32Counters[0][0], 2688 &psMKPerfEntry->ui32Counters[0][0],
2546 sizeof(psMKPerfEntry->ui32Counters)); 2689 sizeof(psMKPerfEntry->ui32Counters));
2547 2690
2691 OSMemCopy(&psClientHWPerfEntry[i].ui32MiscCounters[0][0],
2692 &psMKPerfEntry->ui32MiscCounters[0][0],
2693 sizeof(psMKPerfEntry->ui32MiscCounters));
2694
2548 psHWPerfCB->ui32Roff = (psHWPerfCB->ui32Roff + 1) & (SGXMKIF_HWPERF_CB_SIZE - 1); 2695 psHWPerfCB->ui32Roff = (psHWPerfCB->ui32Roff + 1) & (SGXMKIF_HWPERF_CB_SIZE - 1);
2549 } 2696 }
2550 2697
diff --git a/drivers/gpu/pvr/sgx/sgxkick.c b/drivers/gpu/pvr/sgx/sgxkick.c
index 581640b8fd1..115204f67c2 100644
--- a/drivers/gpu/pvr/sgx/sgxkick.c
+++ b/drivers/gpu/pvr/sgx/sgxkick.c
@@ -36,29 +36,48 @@
36#include "osfunc.h" 36#include "osfunc.h"
37#include "pvr_debug.h" 37#include "pvr_debug.h"
38#include "sgxutils.h" 38#include "sgxutils.h"
39#include "ttrace.h"
39 40
40IMG_EXPORT 41IMG_EXPORT
42#if defined (SUPPORT_SID_INTERFACE)
43PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK_KM *psCCBKick)
44#else
41PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick) 45PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
46#endif
42{ 47{
43 PVRSRV_ERROR eError; 48 PVRSRV_ERROR eError;
44 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo; 49 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo;
45 PVRSRV_KERNEL_MEM_INFO *psCCBMemInfo = (PVRSRV_KERNEL_MEM_INFO *) psCCBKick->hCCBKernelMemInfo; 50 PVRSRV_KERNEL_MEM_INFO *psCCBMemInfo = (PVRSRV_KERNEL_MEM_INFO *) psCCBKick->hCCBKernelMemInfo;
46 SGXMKIF_CMDTA_SHARED *psTACmd; 51 SGXMKIF_CMDTA_SHARED *psTACmd;
47 IMG_UINT32 i; 52 IMG_UINT32 i;
53 IMG_HANDLE hDevMemContext = IMG_NULL;
54#if defined(FIX_HW_BRN_31620)
55 hDevMemContext = psCCBKick->hDevMemContext;
56#endif
57 PVR_TTRACE(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_FUNCTION_ENTER, KICK_TOKEN_DOKICK);
48 58
49 if (!CCB_OFFSET_IS_VALID(SGXMKIF_CMDTA_SHARED, psCCBMemInfo, psCCBKick, ui32CCBOffset)) 59 if (!CCB_OFFSET_IS_VALID(SGXMKIF_CMDTA_SHARED, psCCBMemInfo, psCCBKick, ui32CCBOffset))
50 { 60 {
51 PVR_DPF((PVR_DBG_ERROR, "SGXDoKickKM: Invalid CCB offset")); 61 PVR_DPF((PVR_DBG_ERROR, "SGXDoKickKM: Invalid CCB offset"));
62 PVR_TTRACE(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_FUNCTION_EXIT, KICK_TOKEN_DOKICK);
52 return PVRSRV_ERROR_INVALID_PARAMS; 63 return PVRSRV_ERROR_INVALID_PARAMS;
53 } 64 }
54 65
55 66
56 psTACmd = CCB_DATA_FROM_OFFSET(SGXMKIF_CMDTA_SHARED, psCCBMemInfo, psCCBKick, ui32CCBOffset); 67 psTACmd = CCB_DATA_FROM_OFFSET(SGXMKIF_CMDTA_SHARED, psCCBMemInfo, psCCBKick, ui32CCBOffset);
57 68
69 PVR_TTRACE(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_CMD_START, KICK_TOKEN_DOKICK);
70 PVR_TTRACE_UI32(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_CCB,
71 KICK_TOKEN_CCB_OFFSET, psCCBKick->ui32CCBOffset);
72
58 73
59 if (psCCBKick->hTA3DSyncInfo) 74 if (psCCBKick->hTA3DSyncInfo)
60 { 75 {
61 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->hTA3DSyncInfo; 76 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->hTA3DSyncInfo;
77
78 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_KICK, KICK_TOKEN_TA3D_SYNC,
79 psSyncInfo, PVRSRV_SYNCOP_SAMPLE);
80
62 psTACmd->sTA3DDependency.sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; 81 psTACmd->sTA3DDependency.sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr;
63 82
64 psTACmd->sTA3DDependency.ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending; 83 psTACmd->sTA3DDependency.ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending;
@@ -73,6 +92,9 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
73 { 92 {
74 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->hTASyncInfo; 93 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->hTASyncInfo;
75 94
95 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_KICK, KICK_TOKEN_TA_SYNC,
96 psSyncInfo, PVRSRV_SYNCOP_SAMPLE);
97
76 psTACmd->sTATQSyncReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; 98 psTACmd->sTATQSyncReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
77 psTACmd->sTATQSyncWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; 99 psTACmd->sTATQSyncWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr;
78 100
@@ -84,6 +106,9 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
84 { 106 {
85 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->h3DSyncInfo; 107 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psCCBKick->h3DSyncInfo;
86 108
109 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_KICK, KICK_TOKEN_3D_SYNC,
110 psSyncInfo, PVRSRV_SYNCOP_SAMPLE);
111
87 psTACmd->s3DTQSyncReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; 112 psTACmd->s3DTQSyncReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
88 psTACmd->s3DTQSyncWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; 113 psTACmd->s3DTQSyncWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr;
89 114
@@ -174,6 +199,9 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
174 { 199 {
175 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *) psCCBKick->ahSrcKernelSyncInfo[i]; 200 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *) psCCBKick->ahSrcKernelSyncInfo[i];
176 201
202 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_KICK, KICK_TOKEN_SRC_SYNC,
203 psSyncInfo, PVRSRV_SYNCOP_SAMPLE);
204
177 psTACmd->asSrcSyncs[i].sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; 205 psTACmd->asSrcSyncs[i].sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr;
178 psTACmd->asSrcSyncs[i].sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; 206 psTACmd->asSrcSyncs[i].sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
179 207
@@ -191,7 +219,7 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
191 SGXMKIF_HWDEVICE_SYNC_LIST *psHWDeviceSyncList = psHWDstSyncListMemInfo->pvLinAddrKM; 219 SGXMKIF_HWDEVICE_SYNC_LIST *psHWDeviceSyncList = psHWDstSyncListMemInfo->pvLinAddrKM;
192 IMG_UINT32 ui32NumDstSyncs = psCCBKick->ui32NumDstSyncObjects; 220 IMG_UINT32 ui32NumDstSyncs = psCCBKick->ui32NumDstSyncObjects;
193 221
194 PVR_ASSERT(((PVRSRV_KERNEL_MEM_INFO *)psCCBKick->hKernelHWSyncListMemInfo)->ui32AllocSize >= (sizeof(SGXMKIF_HWDEVICE_SYNC_LIST) + 222 PVR_ASSERT(((PVRSRV_KERNEL_MEM_INFO *)psCCBKick->hKernelHWSyncListMemInfo)->uAllocSize >= (sizeof(SGXMKIF_HWDEVICE_SYNC_LIST) +
195 (sizeof(PVRSRV_DEVICE_SYNC_OBJECT) * ui32NumDstSyncs))); 223 (sizeof(PVRSRV_DEVICE_SYNC_OBJECT) * ui32NumDstSyncs)));
196 224
197 psHWDeviceSyncList->ui32NumSyncObjects = ui32NumDstSyncs; 225 psHWDeviceSyncList->ui32NumSyncObjects = ui32NumDstSyncs;
@@ -214,6 +242,10 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
214 242
215 if (psSyncInfo) 243 if (psSyncInfo)
216 { 244 {
245
246 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_KICK, KICK_TOKEN_DST_SYNC,
247 psSyncInfo, PVRSRV_SYNCOP_SAMPLE);
248
217 psHWDeviceSyncList->asSyncData[i].sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; 249 psHWDeviceSyncList->asSyncData[i].sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr;
218 psHWDeviceSyncList->asSyncData[i].sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; 250 psHWDeviceSyncList->asSyncData[i].sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
219 251
@@ -550,7 +582,10 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
550 } 582 }
551#endif 583#endif
552 584
553 eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_TA, &psCCBKick->sCommand, KERNEL_ID, 0, psCCBKick->bLastInScene); 585 PVR_TTRACE(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_CMD_END,
586 KICK_TOKEN_DOKICK);
587
588 eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_TA, &psCCBKick->sCommand, KERNEL_ID, 0, hDevMemContext, psCCBKick->bLastInScene);
554 if (eError == PVRSRV_ERROR_RETRY) 589 if (eError == PVRSRV_ERROR_RETRY)
555 { 590 {
556 if (psCCBKick->bFirstKickOrResume && psCCBKick->ui32NumDstSyncObjects > 0) 591 if (psCCBKick->bFirstKickOrResume && psCCBKick->ui32NumDstSyncObjects > 0)
@@ -597,11 +632,15 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
597 } 632 }
598#endif 633#endif
599 634
635 PVR_TTRACE(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_FUNCTION_EXIT,
636 KICK_TOKEN_DOKICK);
600 return eError; 637 return eError;
601 } 638 }
602 else if (PVRSRV_OK != eError) 639 else if (PVRSRV_OK != eError)
603 { 640 {
604 PVR_DPF((PVR_DBG_ERROR, "SGXDoKickKM: SGXScheduleCCBCommandKM failed.")); 641 PVR_DPF((PVR_DBG_ERROR, "SGXDoKickKM: SGXScheduleCCBCommandKM failed."));
642 PVR_TTRACE(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_FUNCTION_EXIT,
643 KICK_TOKEN_DOKICK);
605 return eError; 644 return eError;
606 } 645 }
607 646
@@ -707,7 +746,8 @@ PVRSRV_ERROR SGXDoKickKM(IMG_HANDLE hDevHandle, SGX_CCB_KICK *psCCBKick)
707 } 746 }
708 } 747 }
709#endif 748#endif
710 749 PVR_TTRACE(PVRSRV_TRACE_GROUP_KICK, PVRSRV_TRACE_CLASS_FUNCTION_EXIT,
750 KICK_TOKEN_DOKICK);
711 return eError; 751 return eError;
712} 752}
713 753
diff --git a/drivers/gpu/pvr/sgx/sgxpower.c b/drivers/gpu/pvr/sgx/sgxpower.c
index 427cb50dd92..bea113ed354 100644
--- a/drivers/gpu/pvr/sgx/sgxpower.c
+++ b/drivers/gpu/pvr/sgx/sgxpower.c
@@ -207,7 +207,7 @@ static IMG_VOID SGXPollForClockGating (PVRSRV_SGXDEV_INFO *psDevInfo,
207 #endif 207 #endif
208 208
209 PDUMPCOMMENT("%s", pszComment); 209 PDUMPCOMMENT("%s", pszComment);
210 PDUMPREGPOL(SGX_PDUMPREG_NAME, ui32Register, 0, ui32RegisterValue); 210 PDUMPREGPOL(SGX_PDUMPREG_NAME, ui32Register, 0, ui32RegisterValue, PDUMP_POLL_OPERATOR_EQUAL);
211} 211}
212 212
213 213
@@ -224,6 +224,7 @@ PVRSRV_ERROR SGXPrePowerState (IMG_HANDLE hDevHandle,
224 IMG_UINT32 ui32PowerCmd, ui32CompleteStatus; 224 IMG_UINT32 ui32PowerCmd, ui32CompleteStatus;
225 SGXMKIF_COMMAND sCommand = {0}; 225 SGXMKIF_COMMAND sCommand = {0};
226 IMG_UINT32 ui32Core; 226 IMG_UINT32 ui32Core;
227 IMG_UINT32 ui32CoresEnabled;
227 228
228 #if defined(SUPPORT_HW_RECOVERY) 229 #if defined(SUPPORT_HW_RECOVERY)
229 230
@@ -252,7 +253,7 @@ PVRSRV_ERROR SGXPrePowerState (IMG_HANDLE hDevHandle,
252 253
253 sCommand.ui32Data[1] = ui32PowerCmd; 254 sCommand.ui32Data[1] = ui32PowerCmd;
254 255
255 eError = SGXScheduleCCBCommand(psDevInfo, SGXMKIF_CMD_POWER, &sCommand, KERNEL_ID, 0, IMG_FALSE); 256 eError = SGXScheduleCCBCommand(psDeviceNode, SGXMKIF_CMD_POWER, &sCommand, KERNEL_ID, 0, IMG_NULL, IMG_FALSE);
256 if (eError != PVRSRV_OK) 257 if (eError != PVRSRV_OK)
257 { 258 {
258 PVR_DPF((PVR_DBG_ERROR,"SGXPrePowerState: Failed to submit power down command")); 259 PVR_DPF((PVR_DBG_ERROR,"SGXPrePowerState: Failed to submit power down command"));
@@ -284,7 +285,13 @@ PVRSRV_ERROR SGXPrePowerState (IMG_HANDLE hDevHandle,
284 MAKEUNIQUETAG(psDevInfo->psKernelSGXHostCtlMemInfo)); 285 MAKEUNIQUETAG(psDevInfo->psKernelSGXHostCtlMemInfo));
285 #endif 286 #endif
286 287
287 for (ui32Core = 0; ui32Core < SGX_FEATURE_MP_CORE_COUNT; ui32Core++) 288#if defined(SGX_FEATURE_MP)
289 ui32CoresEnabled = ((OSReadHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_CORE) & EUR_CR_MASTER_CORE_ENABLE_MASK) >> EUR_CR_MASTER_CORE_ENABLE_SHIFT) + 1;
290#else
291 ui32CoresEnabled = 1;
292#endif
293
294 for (ui32Core = 0; ui32Core < ui32CoresEnabled; ui32Core++)
288 { 295 {
289 296
290 SGXPollForClockGating(psDevInfo, 297 SGXPollForClockGating(psDevInfo,
@@ -373,7 +380,7 @@ PVRSRV_ERROR SGXPostPowerState (IMG_HANDLE hDevHandle,
373 SGXMKIF_COMMAND sCommand = {0}; 380 SGXMKIF_COMMAND sCommand = {0};
374 381
375 sCommand.ui32Data[1] = PVRSRV_POWERCMD_RESUME; 382 sCommand.ui32Data[1] = PVRSRV_POWERCMD_RESUME;
376 eError = SGXScheduleCCBCommand(psDevInfo, SGXMKIF_CMD_POWER, &sCommand, ISR_ID, 0, IMG_FALSE); 383 eError = SGXScheduleCCBCommand(psDeviceNode, SGXMKIF_CMD_POWER, &sCommand, ISR_ID, 0, IMG_NULL, IMG_FALSE);
377 if (eError != PVRSRV_OK) 384 if (eError != PVRSRV_OK)
378 { 385 {
379 PVR_DPF((PVR_DBG_ERROR,"SGXPostPowerState failed to schedule CCB command: %u", eError)); 386 PVR_DPF((PVR_DBG_ERROR,"SGXPostPowerState failed to schedule CCB command: %u", eError));
diff --git a/drivers/gpu/pvr/sgx/sgxreset.c b/drivers/gpu/pvr/sgx/sgxreset.c
index 847ca24a233..d28898b1025 100644
--- a/drivers/gpu/pvr/sgx/sgxreset.c
+++ b/drivers/gpu/pvr/sgx/sgxreset.c
@@ -33,38 +33,162 @@
33#include "pdump_km.h" 33#include "pdump_km.h"
34 34
35 35
36static IMG_VOID SGXResetSoftReset(PVRSRV_SGXDEV_INFO *psDevInfo, 36IMG_VOID SGXInitClocks(PVRSRV_SGXDEV_INFO *psDevInfo,
37 IMG_BOOL bResetBIF, 37 IMG_UINT32 ui32PDUMPFlags)
38 IMG_UINT32 ui32PDUMPFlags,
39 IMG_BOOL bPDump)
40{ 38{
41 IMG_UINT32 ui32SoftResetRegVal; 39 IMG_UINT32 ui32RegVal;
40
41#if !defined(PDUMP)
42 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
43#endif
44
45 ui32RegVal = psDevInfo->ui32ClkGateCtl;
46 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_CLKGATECTL, ui32RegVal);
47 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_CLKGATECTL, ui32RegVal, ui32PDUMPFlags);
48
49#if defined(EUR_CR_CLKGATECTL2)
50 ui32RegVal = psDevInfo->ui32ClkGateCtl2;
51 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_CLKGATECTL2, ui32RegVal);
52 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_CLKGATECTL2, ui32RegVal, ui32PDUMPFlags);
53#endif
54}
42 55
43#if defined(SGX_FEATURE_MP)
44 ui32SoftResetRegVal =
45 EUR_CR_MASTER_SOFT_RESET_IPF_RESET_MASK |
46 EUR_CR_MASTER_SOFT_RESET_DPM_RESET_MASK |
47 EUR_CR_MASTER_SOFT_RESET_VDM_RESET_MASK;
48 56
49#if defined(SGX_FEATURE_PTLA) 57static IMG_VOID SGXResetInitBIFContexts(PVRSRV_SGXDEV_INFO *psDevInfo,
50 ui32SoftResetRegVal |= EUR_CR_MASTER_SOFT_RESET_PTLA_RESET_MASK; 58 IMG_UINT32 ui32PDUMPFlags)
51#endif 59{
52#if defined(SGX_FEATURE_SYSTEM_CACHE) 60 IMG_UINT32 ui32RegVal;
53 ui32SoftResetRegVal |= EUR_CR_MASTER_SOFT_RESET_SLC_RESET_MASK;
54#endif
55 61
56 if (bResetBIF) 62#if !defined(PDUMP)
63 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
64#endif
65
66 ui32RegVal = 0;
67 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
68 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
69
70#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
71 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the BIF bank settings\r\n");
72 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK_SET, ui32RegVal);
73 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK_SET, ui32RegVal, ui32PDUMPFlags);
74 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0, ui32RegVal);
75 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK0, ui32RegVal, ui32PDUMPFlags);
76#endif
77
78 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the BIF directory list\r\n");
79 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
80 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal, ui32PDUMPFlags);
81
82#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
57 { 83 {
58 ui32SoftResetRegVal |= EUR_CR_MASTER_SOFT_RESET_BIF_RESET_MASK; 84 IMG_UINT32 ui32DirList, ui32DirListReg;
85
86 for (ui32DirList = 1;
87 ui32DirList < SGX_FEATURE_BIF_NUM_DIRLISTS;
88 ui32DirList++)
89 {
90 ui32DirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (ui32DirList - 1);
91 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32DirListReg, ui32RegVal);
92 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, ui32DirListReg, ui32RegVal, ui32PDUMPFlags);
93 }
59 } 94 }
95#endif
96}
97
98
99static IMG_VOID SGXResetSetupBIFContexts(PVRSRV_SGXDEV_INFO *psDevInfo,
100 IMG_UINT32 ui32PDUMPFlags)
101{
102 IMG_UINT32 ui32RegVal;
103
104#if !defined(PDUMP)
105 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
106#endif
107
108 #if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
109
110 ui32RegVal = (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT);
111
112 #if defined(SGX_FEATURE_2D_HARDWARE) && !defined(SGX_FEATURE_PTLA)
113
114 ui32RegVal |= (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_2D_SHIFT);
115 #endif
116
117 #if defined(FIX_HW_BRN_23410)
118
119 ui32RegVal |= (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_TA_SHIFT);
120 #endif
121
122 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0, ui32RegVal);
123 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Set up EDM requestor page table in BIF\r\n");
124 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK0, ui32RegVal, ui32PDUMPFlags);
125 #endif
60 126
61 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SOFT_RESET, ui32SoftResetRegVal);
62 if (bPDump)
63 { 127 {
64 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SOFT_RESET, ui32SoftResetRegVal, ui32PDUMPFlags); 128 IMG_UINT32 ui32EDMDirListReg;
129
130
131 #if (SGX_BIF_DIR_LIST_INDEX_EDM == 0)
132 ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE0;
133 #else
134
135 ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (SGX_BIF_DIR_LIST_INDEX_EDM - 1);
136 #endif
137
138 ui32RegVal = psDevInfo->sKernelPDDevPAddr.uiAddr >> SGX_MMU_PDE_ADDR_ALIGNSHIFT;
139
140#if defined(FIX_HW_BRN_28011)
141 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
142 PDUMPPDREGWITHFLAGS(&psDevInfo->sMMUAttrib, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal, ui32PDUMPFlags, PDUMP_PD_UNIQUETAG);
143#endif
144
145 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32EDMDirListReg, ui32RegVal);
146 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the EDM's directory list base\r\n");
147 PDUMPPDREGWITHFLAGS(&psDevInfo->sMMUAttrib, ui32EDMDirListReg, ui32RegVal, ui32PDUMPFlags, PDUMP_PD_UNIQUETAG);
65 } 148 }
149}
150
151
152static IMG_VOID SGXResetSleep(PVRSRV_SGXDEV_INFO *psDevInfo,
153 IMG_UINT32 ui32PDUMPFlags,
154 IMG_BOOL bPDump)
155{
156#if defined(PDUMP)
157 IMG_UINT32 ui32ReadRegister;
158
159 #if defined(SGX_FEATURE_MP)
160 ui32ReadRegister = EUR_CR_MASTER_SOFT_RESET;
161 #else
162 ui32ReadRegister = EUR_CR_SOFT_RESET;
163 #endif
164#endif
165
166#if !defined(PDUMP)
167 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
66#endif 168#endif
67 169
170
171 OSWaitus(100 * 1000000 / psDevInfo->ui32CoreClockSpeed);
172 if (bPDump)
173 {
174 PDUMPIDLWITHFLAGS(30, ui32PDUMPFlags);
175#if defined(PDUMP)
176 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Read back to flush the register writes\r\n");
177 PDumpRegRead(SGX_PDUMPREG_NAME, ui32ReadRegister, ui32PDUMPFlags);
178#endif
179 }
180
181}
182
183
184#if !defined(SGX_FEATURE_MP)
185static IMG_VOID SGXResetSoftReset(PVRSRV_SGXDEV_INFO *psDevInfo,
186 IMG_BOOL bResetBIF,
187 IMG_UINT32 ui32PDUMPFlags,
188 IMG_BOOL bPDump)
189{
190 IMG_UINT32 ui32SoftResetRegVal;
191
68 ui32SoftResetRegVal = 192 ui32SoftResetRegVal =
69 193
70 EUR_CR_SOFT_RESET_DPM_RESET_MASK | 194 EUR_CR_SOFT_RESET_DPM_RESET_MASK |
@@ -139,27 +263,6 @@ static IMG_VOID SGXResetSoftReset(PVRSRV_SGXDEV_INFO *psDevInfo,
139} 263}
140 264
141 265
142static IMG_VOID SGXResetSleep(PVRSRV_SGXDEV_INFO *psDevInfo,
143 IMG_UINT32 ui32PDUMPFlags,
144 IMG_BOOL bPDump)
145{
146#if !defined(PDUMP)
147 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
148#endif
149
150
151 OSWaitus(100 * 1000000 / psDevInfo->ui32CoreClockSpeed);
152 if (bPDump)
153 {
154 PDUMPIDLWITHFLAGS(30, ui32PDUMPFlags);
155#if defined(PDUMP)
156 PDumpRegRead(SGX_PDUMPREG_NAME, EUR_CR_SOFT_RESET, ui32PDUMPFlags);
157#endif
158 }
159
160}
161
162
163static IMG_VOID SGXResetInvalDC(PVRSRV_SGXDEV_INFO *psDevInfo, 266static IMG_VOID SGXResetInvalDC(PVRSRV_SGXDEV_INFO *psDevInfo,
164 IMG_UINT32 ui32PDUMPFlags, 267 IMG_UINT32 ui32PDUMPFlags,
165 IMG_BOOL bPDump) 268 IMG_BOOL bPDump)
@@ -209,16 +312,18 @@ static IMG_VOID SGXResetInvalDC(PVRSRV_SGXDEV_INFO *psDevInfo,
209 312
210 if (bPDump) 313 if (bPDump)
211 { 314 {
212 PDUMPREGPOLWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_MEM_REQ_STAT, 0, EUR_CR_BIF_MEM_REQ_STAT_READS_MASK, ui32PDUMPFlags); 315 PDUMPREGPOLWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_MEM_REQ_STAT, 0, EUR_CR_BIF_MEM_REQ_STAT_READS_MASK, ui32PDUMPFlags, PDUMP_POLL_OPERATOR_EQUAL);
213 } 316 }
214 } 317 }
215#endif 318#endif
216} 319}
320#endif
217 321
218 322
219IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo, 323IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
220 IMG_BOOL bHardwareRecovery, 324 IMG_BOOL bHardwareRecovery,
221 IMG_UINT32 ui32PDUMPFlags) 325 IMG_UINT32 ui32PDUMPFlags)
326#if !defined(SGX_FEATURE_MP)
222{ 327{
223 IMG_UINT32 ui32RegVal; 328 IMG_UINT32 ui32RegVal;
224#if defined(EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK) 329#if defined(EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK)
@@ -227,12 +332,10 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
227 const IMG_UINT32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_MASK; 332 const IMG_UINT32 ui32BifFaultMask = EUR_CR_BIF_INT_STAT_FAULT_MASK;
228#endif 333#endif
229 334
230#ifndef PDUMP 335#if !defined(PDUMP)
231 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags); 336 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
232#endif 337#endif
233 338
234 psDevInfo->ui32NumResets++;
235
236 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Start of SGX reset sequence\r\n"); 339 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Start of SGX reset sequence\r\n");
237 340
238#if defined(FIX_HW_BRN_23944) 341#if defined(FIX_HW_BRN_23944)
@@ -274,37 +377,7 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
274 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK, ui32PDUMPFlags); 377 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_36BIT_ADDRESSING, EUR_CR_BIF_36BIT_ADDRESSING_ENABLE_MASK, ui32PDUMPFlags);
275#endif 378#endif
276 379
277 ui32RegVal = 0; 380 SGXResetInitBIFContexts(psDevInfo, ui32PDUMPFlags);
278 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_CTRL, ui32RegVal);
279 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
280#if defined(SGX_FEATURE_MP)
281 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BIF_CTRL, ui32RegVal);
282 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
283#endif
284#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
285 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK_SET, ui32RegVal);
286 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK_SET, ui32RegVal, ui32PDUMPFlags);
287 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0, ui32RegVal);
288 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK0, ui32RegVal, ui32PDUMPFlags);
289#endif
290
291 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal);
292 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_DIR_LIST_BASE0, ui32RegVal, ui32PDUMPFlags);
293
294#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
295 {
296 IMG_UINT32 ui32DirList, ui32DirListReg;
297
298 for (ui32DirList = 1;
299 ui32DirList < SGX_FEATURE_BIF_NUM_DIRLISTS;
300 ui32DirList++)
301 {
302 ui32DirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (ui32DirList - 1);
303 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32DirListReg, ui32RegVal);
304 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, ui32DirListReg, ui32RegVal, ui32PDUMPFlags);
305 }
306 }
307#endif
308 381
309#if defined(EUR_CR_BIF_MEM_ARB_CONFIG) 382#if defined(EUR_CR_BIF_MEM_ARB_CONFIG)
310 383
@@ -317,30 +390,6 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
317#endif 390#endif
318 391
319#if defined(SGX_FEATURE_SYSTEM_CACHE) 392#if defined(SGX_FEATURE_SYSTEM_CACHE)
320#if defined(SGX_FEATURE_MP)
321 #if defined(SGX_BYPASS_SYSTEM_CACHE)
322 #error SGX_BYPASS_SYSTEM_CACHE not supported
323 #else
324 ui32RegVal = EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ0_MASK |
325 #if defined(FIX_HW_BRN_30954)
326 EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_MASK |
327 #endif
328 (0xC << EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_SHIFT);
329 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
330 PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
331
332 ui32RegVal = EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_MASK;
333 #if defined(FIX_HW_BRN_31195)
334 ui32RegVal |= EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE0_MASK |
335 EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE1_MASK |
336 EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE2_MASK |
337 EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE3_MASK |
338 EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TA_MASK;
339 #endif
340 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
341 PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
342 #endif
343#else
344 #if defined(SGX_BYPASS_SYSTEM_CACHE) 393 #if defined(SGX_BYPASS_SYSTEM_CACHE)
345 394
346 ui32RegVal = MNE_CR_CTRL_BYPASS_ALL_MASK; 395 ui32RegVal = MNE_CR_CTRL_BYPASS_ALL_MASK;
@@ -355,7 +404,6 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
355 OSWriteHWReg(psDevInfo->pvRegsBaseKM, MNE_CR_CTRL, ui32RegVal); 404 OSWriteHWReg(psDevInfo->pvRegsBaseKM, MNE_CR_CTRL, ui32RegVal);
356 PDUMPREG(SGX_PDUMPREG_NAME, MNE_CR_CTRL, ui32RegVal); 405 PDUMPREG(SGX_PDUMPREG_NAME, MNE_CR_CTRL, ui32RegVal);
357#endif 406#endif
358#endif
359 407
360 if (bHardwareRecovery) 408 if (bHardwareRecovery)
361 { 409 {
@@ -439,43 +487,7 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
439 487
440 488
441 489
442 #if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS) 490 SGXResetSetupBIFContexts(psDevInfo, ui32PDUMPFlags);
443
444 ui32RegVal = (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT);
445
446 #if defined(SGX_FEATURE_2D_HARDWARE) && !defined(SGX_FEATURE_PTLA)
447
448 ui32RegVal |= (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_2D_SHIFT);
449 #endif
450
451 #if defined(FIX_HW_BRN_23410)
452
453 ui32RegVal |= (SGX_BIF_DIR_LIST_INDEX_EDM << EUR_CR_BIF_BANK0_INDEX_TA_SHIFT);
454 #endif
455
456 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_BANK0, ui32RegVal);
457 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_BIF_BANK0, ui32RegVal, ui32PDUMPFlags);
458 #endif
459
460 {
461 IMG_UINT32 ui32EDMDirListReg;
462
463
464 #if (SGX_BIF_DIR_LIST_INDEX_EDM == 0)
465 ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE0;
466 #else
467
468 ui32EDMDirListReg = EUR_CR_BIF_DIR_LIST_BASE1 + 4 * (SGX_BIF_DIR_LIST_INDEX_EDM - 1);
469 #endif
470
471#if defined(FIX_HW_BRN_28011)
472 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_BIF_DIR_LIST_BASE0, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT);
473 PDUMPPDREGWITHFLAGS(&psDevInfo->sMMUAttrib, EUR_CR_BIF_DIR_LIST_BASE0, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT, ui32PDUMPFlags, PDUMP_PD_UNIQUETAG);
474#endif
475
476 OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32EDMDirListReg, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT);
477 PDUMPPDREGWITHFLAGS(&psDevInfo->sMMUAttrib, ui32EDMDirListReg, psDevInfo->sKernelPDDevPAddr.uiAddr>>SGX_MMU_PDE_ADDR_ALIGNSHIFT, ui32PDUMPFlags, PDUMP_PD_UNIQUETAG);
478 }
479 491
480#if defined(SGX_FEATURE_2D_HARDWARE) && !defined(SGX_FEATURE_PTLA) 492#if defined(SGX_FEATURE_2D_HARDWARE) && !defined(SGX_FEATURE_PTLA)
481 493
@@ -494,10 +506,6 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
494 506
495 507
496 ui32RegVal = 0; 508 ui32RegVal = 0;
497#if defined(SGX_FEATURE_MP)
498 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SOFT_RESET, ui32RegVal);
499 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
500#endif
501 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_SOFT_RESET, ui32RegVal); 509 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_SOFT_RESET, ui32RegVal);
502 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_SOFT_RESET, ui32RegVal, ui32PDUMPFlags); 510 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
503 511
@@ -507,4 +515,140 @@ IMG_VOID SGXReset(PVRSRV_SGXDEV_INFO *psDevInfo,
507 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "End of SGX reset sequence\r\n"); 515 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "End of SGX reset sequence\r\n");
508} 516}
509 517
518#else
519
520{
521 IMG_UINT32 ui32RegVal;
522
523 PVR_UNREFERENCED_PARAMETER(bHardwareRecovery);
524
525#if !defined(PDUMP)
526 PVR_UNREFERENCED_PARAMETER(ui32PDUMPFlags);
527#endif
528
529 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Start of SGX MP reset sequence\r\n");
530
531
532 ui32RegVal = EUR_CR_MASTER_SOFT_RESET_BIF_RESET_MASK |
533 EUR_CR_MASTER_SOFT_RESET_IPF_RESET_MASK |
534 EUR_CR_MASTER_SOFT_RESET_DPM_RESET_MASK |
535 EUR_CR_MASTER_SOFT_RESET_VDM_RESET_MASK;
536
537#if defined(SGX_FEATURE_PTLA)
538 ui32RegVal |= EUR_CR_MASTER_SOFT_RESET_PTLA_RESET_MASK;
539#endif
540#if defined(SGX_FEATURE_SYSTEM_CACHE)
541 ui32RegVal |= EUR_CR_MASTER_SOFT_RESET_SLC_RESET_MASK;
542#endif
543
544
545 ui32RegVal |= EUR_CR_MASTER_SOFT_RESET_CORE_RESET_MASK(0) |
546 EUR_CR_MASTER_SOFT_RESET_CORE_RESET_MASK(1) |
547 EUR_CR_MASTER_SOFT_RESET_CORE_RESET_MASK(2) |
548 EUR_CR_MASTER_SOFT_RESET_CORE_RESET_MASK(3);
549
550 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SOFT_RESET, ui32RegVal);
551 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Soft reset hydra partition, hard reset the cores\r\n");
552 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
553
554 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
555
556 ui32RegVal = 0;
557 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BIF_CTRL, ui32RegVal);
558 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the hydra BIF control\r\n");
559 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_BIF_CTRL, ui32RegVal, ui32PDUMPFlags);
560
561#if defined(SGX_FEATURE_SYSTEM_CACHE)
562 #if defined(SGX_BYPASS_SYSTEM_CACHE)
563 #error SGX_BYPASS_SYSTEM_CACHE not supported
564 #else
565 ui32RegVal = EUR_CR_MASTER_SLC_CTRL_USSE_INVAL_REQ0_MASK |
566 #if defined(FIX_HW_BRN_30954)
567 EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_MASK |
568 #endif
569 (0xC << EUR_CR_MASTER_SLC_CTRL_ARB_PAGE_SIZE_SHIFT);
570 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
571 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the hydra SLC control\r\n");
572 PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL, ui32RegVal);
573
574 ui32RegVal = EUR_CR_MASTER_SLC_CTRL_BYPASS_BYP_CC_MASK;
575 #if defined(FIX_HW_BRN_31620)
576 ui32RegVal |= EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_MMU_MASK;
577 #endif
578 #if defined(FIX_HW_BRN_31195)
579 ui32RegVal |= EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE0_MASK |
580 EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE1_MASK |
581 EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE2_MASK |
582 EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_USE3_MASK |
583 EUR_CR_MASTER_SLC_CTRL_BYPASS_REQ_TA_MASK;
584 #endif
585 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
586 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the hydra SLC bypass control\r\n");
587 PDUMPREG(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SLC_CTRL_BYPASS, ui32RegVal);
588 #endif
589#endif
590
591 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
592
593
594 ui32RegVal = 0;
595 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_SOFT_RESET, ui32RegVal);
596 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Remove the resets from all of SGX\r\n");
597 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_SOFT_RESET, ui32RegVal, ui32PDUMPFlags);
598
599 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
600
601 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Turn on the slave cores' clock gating\r\n");
602 SGXInitClocks(psDevInfo, ui32PDUMPFlags);
603
604 SGXResetSleep(psDevInfo, ui32PDUMPFlags, IMG_TRUE);
605
606 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "Initialise the slave BIFs\r\n");
607
608#if defined(FIX_HW_BRN_31278) || defined(FIX_HW_BRN_31620) || defined(FIX_HW_BRN_31671)
609 #if defined(FIX_HW_BRN_31278)
610
611 ui32RegVal = (1<<EUR_CR_MASTER_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT);
612 #else
613 ui32RegVal = (1<<EUR_CR_MASTER_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT) | EUR_CR_MASTER_BIF_MMU_CTRL_PREFETCHING_ON_MASK;
614 #endif
615 #if !defined(FIX_HW_BRN_31620) && !defined(FIX_HW_BRN_31671)
616
617 ui32RegVal |= EUR_CR_MASTER_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK;
618 #endif
619
620
621 OSWriteHWReg(psDevInfo->pvRegsBaseKM, EUR_CR_MASTER_BIF_MMU_CTRL, ui32RegVal);
622 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, EUR_CR_MASTER_BIF_MMU_CTRL, ui32RegVal, ui32PDUMPFlags);
623
624 #if defined(FIX_HW_BRN_31278)
625
626 ui32RegVal = (1<<EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT);
627 #else
628 ui32RegVal = (1<<EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT) | EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_MASK;
629 #endif
630 #if !defined(FIX_HW_BRN_31620) && !defined(FIX_HW_BRN_31671)
631
632 ui32RegVal |= EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK;
633 #endif
634
635
636 {
637 IMG_UINT32 ui32Core;
638
639 for (ui32Core=0;ui32Core<SGX_FEATURE_MP_CORE_COUNT;ui32Core++)
640 {
641 OSWriteHWReg(psDevInfo->pvRegsBaseKM, SGX_MP_CORE_SELECT(EUR_CR_BIF_MMU_CTRL, ui32Core), ui32RegVal);
642 PDUMPREGWITHFLAGS(SGX_PDUMPREG_NAME, SGX_MP_CORE_SELECT(EUR_CR_BIF_MMU_CTRL, ui32Core), ui32RegVal, ui32PDUMPFlags);
643 }
644 }
645#endif
646
647 SGXResetInitBIFContexts(psDevInfo, ui32PDUMPFlags);
648 SGXResetSetupBIFContexts(psDevInfo, ui32PDUMPFlags);
649
650 PDUMPCOMMENTWITHFLAGS(ui32PDUMPFlags, "End of SGX MP reset sequence\r\n");
651}
652#endif
653
510 654
diff --git a/drivers/gpu/pvr/sgx/sgxtransfer.c b/drivers/gpu/pvr/sgx/sgxtransfer.c
index ab46ff70b27..ff738453c82 100644
--- a/drivers/gpu/pvr/sgx/sgxtransfer.c
+++ b/drivers/gpu/pvr/sgx/sgxtransfer.c
@@ -42,8 +42,13 @@
42#include "osfunc.h" 42#include "osfunc.h"
43#include "pvr_debug.h" 43#include "pvr_debug.h"
44#include "sgxutils.h" 44#include "sgxutils.h"
45#include "ttrace.h"
45 46
47#if defined (SUPPORT_SID_INTERFACE)
48IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSFER_SGX_KICK_KM *psKick)
49#else
46IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSFER_SGX_KICK *psKick) 50IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSFER_SGX_KICK *psKick)
51#endif
47{ 52{
48 PVRSRV_KERNEL_MEM_INFO *psCCBMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psKick->hCCBMemInfo; 53 PVRSRV_KERNEL_MEM_INFO *psCCBMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psKick->hCCBMemInfo;
49 SGXMKIF_COMMAND sCommand = {0}; 54 SGXMKIF_COMMAND sCommand = {0};
@@ -51,6 +56,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
51 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo; 56 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo;
52 PVRSRV_ERROR eError; 57 PVRSRV_ERROR eError;
53 IMG_UINT32 loop; 58 IMG_UINT32 loop;
59 IMG_HANDLE hDevMemContext = IMG_NULL;
54#if defined(PDUMP) 60#if defined(PDUMP)
55 IMG_BOOL bPersistentProcess = IMG_FALSE; 61 IMG_BOOL bPersistentProcess = IMG_FALSE;
56 62
@@ -62,20 +68,33 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
62 } 68 }
63 } 69 }
64#endif 70#endif
71#if defined(FIX_HW_BRN_31620)
72 hDevMemContext = psKick->hDevMemContext;
73#endif
74 PVR_TTRACE(PVRSRV_TRACE_GROUP_TRANSFER, PVRSRV_TRACE_CLASS_FUNCTION_ENTER, TRANSFER_TOKEN_SUBMIT);
65 75
66 if (!CCB_OFFSET_IS_VALID(SGXMKIF_TRANSFERCMD_SHARED, psCCBMemInfo, psKick, ui32SharedCmdCCBOffset)) 76 if (!CCB_OFFSET_IS_VALID(SGXMKIF_TRANSFERCMD_SHARED, psCCBMemInfo, psKick, ui32SharedCmdCCBOffset))
67 { 77 {
68 PVR_DPF((PVR_DBG_ERROR, "SGXSubmitTransferKM: Invalid CCB offset")); 78 PVR_DPF((PVR_DBG_ERROR, "SGXSubmitTransferKM: Invalid CCB offset"));
79 PVR_TTRACE(PVRSRV_TRACE_GROUP_TRANSFER, PVRSRV_TRACE_CLASS_FUNCTION_EXIT,
80 TRANSFER_TOKEN_SUBMIT);
69 return PVRSRV_ERROR_INVALID_PARAMS; 81 return PVRSRV_ERROR_INVALID_PARAMS;
70 } 82 }
71 83
72 84
73 psSharedTransferCmd = CCB_DATA_FROM_OFFSET(SGXMKIF_TRANSFERCMD_SHARED, psCCBMemInfo, psKick, ui32SharedCmdCCBOffset); 85 psSharedTransferCmd = CCB_DATA_FROM_OFFSET(SGXMKIF_TRANSFERCMD_SHARED, psCCBMemInfo, psKick, ui32SharedCmdCCBOffset);
74 86
87 PVR_TTRACE(PVRSRV_TRACE_GROUP_TRANSFER, PVRSRV_TRACE_CLASS_CMD_START, TRANSFER_TOKEN_SUBMIT);
88 PVR_TTRACE_UI32(PVRSRV_TRACE_GROUP_TRANSFER, PVRSRV_TRACE_CLASS_CCB,
89 TRANSFER_TOKEN_CCB_OFFSET, psKick->ui32SharedCmdCCBOffset);
90
75 if (psKick->hTASyncInfo != IMG_NULL) 91 if (psKick->hTASyncInfo != IMG_NULL)
76 { 92 {
77 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->hTASyncInfo; 93 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->hTASyncInfo;
78 94
95 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_TRANSFER, TRANSFER_TOKEN_TA_SYNC,
96 psSyncInfo, PVRSRV_SYNCOP_SAMPLE);
97
79 psSharedTransferCmd->ui32TASyncWriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending++; 98 psSharedTransferCmd->ui32TASyncWriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending++;
80 psSharedTransferCmd->ui32TASyncReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending; 99 psSharedTransferCmd->ui32TASyncReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending;
81 100
@@ -92,6 +111,9 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
92 { 111 {
93 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->h3DSyncInfo; 112 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->h3DSyncInfo;
94 113
114 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_TRANSFER, TRANSFER_TOKEN_3D_SYNC,
115 psSyncInfo, PVRSRV_SYNCOP_SAMPLE);
116
95 psSharedTransferCmd->ui323DSyncWriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending++; 117 psSharedTransferCmd->ui323DSyncWriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending++;
96 psSharedTransferCmd->ui323DSyncReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending; 118 psSharedTransferCmd->ui323DSyncReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending;
97 119
@@ -112,10 +134,13 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
112 { 134 {
113 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; 135 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop];
114 136
137 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_TRANSFER, TRANSFER_TOKEN_SRC_SYNC,
138 psSyncInfo, PVRSRV_SYNCOP_SAMPLE);
139
115 psSharedTransferCmd->asSrcSyncs[loop].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending; 140 psSharedTransferCmd->asSrcSyncs[loop].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending;
116 psSharedTransferCmd->asSrcSyncs[loop].ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending; 141 psSharedTransferCmd->asSrcSyncs[loop].ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending;
117 142
118 psSharedTransferCmd->asSrcSyncs[loop].sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; 143 psSharedTransferCmd->asSrcSyncs[loop].sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr;
119 psSharedTransferCmd->asSrcSyncs[loop].sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; 144 psSharedTransferCmd->asSrcSyncs[loop].sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
120 145
121 } 146 }
@@ -123,6 +148,9 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
123 { 148 {
124 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop]; 149 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahDstSyncInfo[loop];
125 150
151 PVR_TTRACE_SYNC_OBJECT(PVRSRV_TRACE_GROUP_TRANSFER, TRANSFER_TOKEN_DST_SYNC,
152 psSyncInfo, PVRSRV_SYNCOP_SAMPLE);
153
126 psSharedTransferCmd->asDstSyncs[loop].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending; 154 psSharedTransferCmd->asDstSyncs[loop].ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending;
127 psSharedTransferCmd->asDstSyncs[loop].ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending; 155 psSharedTransferCmd->asDstSyncs[loop].ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending;
128 156
@@ -131,7 +159,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
131 159
132 } 160 }
133 161
134 162
135 for (loop=0; loop<psKick->ui32NumSrcSync; loop++) 163 for (loop=0; loop<psKick->ui32NumSrcSync; loop++)
136 { 164 {
137 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop]; 165 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[loop];
@@ -146,7 +174,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
146 174
147#if defined(PDUMP) 175#if defined(PDUMP)
148 if ((PDumpIsCaptureFrameKM() 176 if ((PDumpIsCaptureFrameKM()
149 || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0)) 177 || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0))
150 && (bPersistentProcess == IMG_FALSE) ) 178 && (bPersistentProcess == IMG_FALSE) )
151 { 179 {
152 PDUMPCOMMENT("Shared part of transfer command\r\n"); 180 PDUMPCOMMENT("Shared part of transfer command\r\n");
@@ -162,19 +190,19 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
162 for (loop=0; loop<psKick->ui32NumSrcSync ; loop++) 190 for (loop=0; loop<psKick->ui32NumSrcSync ; loop++)
163 { 191 {
164 psSyncInfo = psKick->ahSrcSyncInfo[loop]; 192 psSyncInfo = psKick->ahSrcSyncInfo[loop];
165 193
166 PDUMPCOMMENT("Hack src surface write op in transfer cmd\r\n"); 194 PDUMPCOMMENT("Hack src surface write op in transfer cmd\r\n");
167 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, 195 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal,
168 psCCBMemInfo, 196 psCCBMemInfo,
169 psKick->ui32CCBDumpWOff + offsetof(SGXMKIF_TRANSFERCMD_SHARED, asSrcSyncs) + loop * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32WriteOpsPendingVal), 197 psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asSrcSyncs) + loop * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32WriteOpsPendingVal)),
170 sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal), 198 sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal),
171 psKick->ui32PDumpFlags, 199 psKick->ui32PDumpFlags,
172 MAKEUNIQUETAG(psCCBMemInfo)); 200 MAKEUNIQUETAG(psCCBMemInfo));
173 201
174 PDUMPCOMMENT("Hack src surface read op in transfer cmd\r\n"); 202 PDUMPCOMMENT("Hack src surface read op in transfer cmd\r\n");
175 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, 203 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal,
176 psCCBMemInfo, 204 psCCBMemInfo,
177 psKick->ui32CCBDumpWOff + offsetof(SGXMKIF_TRANSFERCMD_SHARED, asSrcSyncs) + loop * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32ReadOpsPendingVal), 205 psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asSrcSyncs) + loop * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32ReadOpsPendingVal)),
178 sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal), 206 sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal),
179 psKick->ui32PDumpFlags, 207 psKick->ui32PDumpFlags,
180 MAKEUNIQUETAG(psCCBMemInfo)); 208 MAKEUNIQUETAG(psCCBMemInfo));
@@ -186,11 +214,11 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
186 for (loop=0; loop< psKick->ui32NumDstSync; loop++) 214 for (loop=0; loop< psKick->ui32NumDstSync; loop++)
187 { 215 {
188 psSyncInfo = psKick->ahDstSyncInfo[loop]; 216 psSyncInfo = psKick->ahDstSyncInfo[loop];
189 217
190 PDUMPCOMMENT("Hack dest surface write op in transfer cmd\r\n"); 218 PDUMPCOMMENT("Hack dest surface write op in transfer cmd\r\n");
191 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, 219 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal,
192 psCCBMemInfo, 220 psCCBMemInfo,
193 psKick->ui32CCBDumpWOff + offsetof(SGXMKIF_TRANSFERCMD_SHARED, asDstSyncs) + loop * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32WriteOpsPendingVal) , 221 psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asDstSyncs) + loop * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32WriteOpsPendingVal)),
194 sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal), 222 sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal),
195 psKick->ui32PDumpFlags, 223 psKick->ui32PDumpFlags,
196 MAKEUNIQUETAG(psCCBMemInfo)); 224 MAKEUNIQUETAG(psCCBMemInfo));
@@ -198,7 +226,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
198 PDUMPCOMMENT("Hack dest surface read op in transfer cmd\r\n"); 226 PDUMPCOMMENT("Hack dest surface read op in transfer cmd\r\n");
199 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, 227 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal,
200 psCCBMemInfo, 228 psCCBMemInfo,
201 psKick->ui32CCBDumpWOff + offsetof(SGXMKIF_TRANSFERCMD_SHARED, asDstSyncs) + loop * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32ReadOpsPendingVal), 229 psKick->ui32CCBDumpWOff + (IMG_UINT32)(offsetof(SGXMKIF_TRANSFERCMD_SHARED, asDstSyncs) + loop * sizeof(PVRSRV_DEVICE_SYNC_OBJECT) + offsetof(PVRSRV_DEVICE_SYNC_OBJECT, ui32ReadOpsPendingVal)),
202 sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal), 230 sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal),
203 psKick->ui32PDumpFlags, 231 psKick->ui32PDumpFlags,
204 MAKEUNIQUETAG(psCCBMemInfo)); 232 MAKEUNIQUETAG(psCCBMemInfo));
@@ -206,7 +234,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
206 } 234 }
207 } 235 }
208 236
209 237
210 if((psKick->ui32Flags & SGXMKIF_TQFLAGS_KEEPPENDING)== 0UL) 238 if((psKick->ui32Flags & SGXMKIF_TQFLAGS_KEEPPENDING)== 0UL)
211 { 239 {
212 for (loop=0; loop<(psKick->ui32NumSrcSync); loop++) 240 for (loop=0; loop<(psKick->ui32NumSrcSync); loop++)
@@ -224,16 +252,19 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
224 psSyncInfo->psSyncData->ui32LastOpDumpVal++; 252 psSyncInfo->psSyncData->ui32LastOpDumpVal++;
225 } 253 }
226 } 254 }
227 } 255 }
228#endif 256#endif
229 257
230 sCommand.ui32Data[1] = psKick->sHWTransferContextDevVAddr.uiAddr; 258 sCommand.ui32Data[1] = psKick->sHWTransferContextDevVAddr.uiAddr;
259
260 PVR_TTRACE(PVRSRV_TRACE_GROUP_TRANSFER, PVRSRV_TRACE_CLASS_CMD_END,
261 TRANSFER_TOKEN_SUBMIT);
231 262
232 eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_TRANSFER, &sCommand, KERNEL_ID, psKick->ui32PDumpFlags, IMG_FALSE); 263 eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_TRANSFER, &sCommand, KERNEL_ID, psKick->ui32PDumpFlags, hDevMemContext, IMG_FALSE);
233 264
234 if (eError == PVRSRV_ERROR_RETRY) 265 if (eError == PVRSRV_ERROR_RETRY)
235 { 266 {
236 267
237 if ((psKick->ui32Flags & SGXMKIF_TQFLAGS_KEEPPENDING) == 0UL) 268 if ((psKick->ui32Flags & SGXMKIF_TQFLAGS_KEEPPENDING) == 0UL)
238 { 269 {
239 if (psKick->ui32NumSrcSync > 0) 270 if (psKick->ui32NumSrcSync > 0)
@@ -264,14 +295,14 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
264#endif 295#endif
265 } 296 }
266 297
267 298
268 if (psKick->hTASyncInfo != IMG_NULL) 299 if (psKick->hTASyncInfo != IMG_NULL)
269 { 300 {
270 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->hTASyncInfo; 301 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->hTASyncInfo;
271 psSyncInfo->psSyncData->ui32WriteOpsPending--; 302 psSyncInfo->psSyncData->ui32WriteOpsPending--;
272 } 303 }
273 304
274 305
275 if (psKick->h3DSyncInfo != IMG_NULL) 306 if (psKick->h3DSyncInfo != IMG_NULL)
276 { 307 {
277 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->h3DSyncInfo; 308 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->h3DSyncInfo;
@@ -282,16 +313,18 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
282 else if (PVRSRV_OK != eError) 313 else if (PVRSRV_OK != eError)
283 { 314 {
284 PVR_DPF((PVR_DBG_ERROR, "SGXSubmitTransferKM: SGXScheduleCCBCommandKM failed.")); 315 PVR_DPF((PVR_DBG_ERROR, "SGXSubmitTransferKM: SGXScheduleCCBCommandKM failed."));
316 PVR_TTRACE(PVRSRV_TRACE_GROUP_TRANSFER, PVRSRV_TRACE_CLASS_FUNCTION_EXIT,
317 TRANSFER_TOKEN_SUBMIT);
285 return eError; 318 return eError;
286 } 319 }
287 320
288 321
289#if defined(NO_HARDWARE) 322#if defined(NO_HARDWARE)
290 if ((psKick->ui32Flags & SGXMKIF_TQFLAGS_NOSYNCUPDATE) == 0) 323 if ((psKick->ui32Flags & SGXMKIF_TQFLAGS_NOSYNCUPDATE) == 0)
291 { 324 {
292 IMG_UINT32 i; 325 IMG_UINT32 i;
293 326
294 327
295 for(i = 0; i < psKick->ui32NumSrcSync; i++) 328 for(i = 0; i < psKick->ui32NumSrcSync; i++)
296 { 329 {
297 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[i]; 330 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->ahSrcSyncInfo[i];
@@ -320,13 +353,18 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmitTransferKM(IMG_HANDLE hDevHandle, PVRSRV_TRANSF
320 } 353 }
321 } 354 }
322#endif 355#endif
323 356 PVR_TTRACE(PVRSRV_TRACE_GROUP_TRANSFER, PVRSRV_TRACE_CLASS_FUNCTION_EXIT,
357 TRANSFER_TOKEN_SUBMIT);
324 return eError; 358 return eError;
325} 359}
326 360
327#if defined(SGX_FEATURE_2D_HARDWARE) 361#if defined(SGX_FEATURE_2D_HARDWARE)
362#if defined (SUPPORT_SID_INTERFACE)
363IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK_KM *psKick)
364#else
328IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK *psKick) 365IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK *psKick)
329 366#endif
367
330{ 368{
331 PVRSRV_KERNEL_MEM_INFO *psCCBMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psKick->hCCBMemInfo; 369 PVRSRV_KERNEL_MEM_INFO *psCCBMemInfo = (PVRSRV_KERNEL_MEM_INFO *)psKick->hCCBMemInfo;
332 SGXMKIF_COMMAND sCommand = {0}; 370 SGXMKIF_COMMAND sCommand = {0};
@@ -334,9 +372,10 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
334 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo; 372 PVRSRV_KERNEL_SYNC_INFO *psSyncInfo;
335 PVRSRV_ERROR eError; 373 PVRSRV_ERROR eError;
336 IMG_UINT32 i; 374 IMG_UINT32 i;
375 IMG_HANDLE hDevMemContext = IMG_NULL;
337#if defined(PDUMP) 376#if defined(PDUMP)
338 IMG_BOOL bPersistentProcess = IMG_FALSE; 377 IMG_BOOL bPersistentProcess = IMG_FALSE;
339 378
340 { 379 {
341 PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData(); 380 PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData();
342 if(psPerProc != IMG_NULL) 381 if(psPerProc != IMG_NULL)
@@ -344,6 +383,9 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
344 bPersistentProcess = psPerProc->bPDumpPersistent; 383 bPersistentProcess = psPerProc->bPDumpPersistent;
345 } 384 }
346 } 385 }
386#endif
387#if defined(FIX_HW_BRN_31620)
388 hDevMemContext = psKick->hDevMemContext;
347#endif 389#endif
348 390
349 if (!CCB_OFFSET_IS_VALID(SGXMKIF_2DCMD_SHARED, psCCBMemInfo, psKick, ui32SharedCmdCCBOffset)) 391 if (!CCB_OFFSET_IS_VALID(SGXMKIF_2DCMD_SHARED, psCCBMemInfo, psKick, ui32SharedCmdCCBOffset))
@@ -351,13 +393,13 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
351 PVR_DPF((PVR_DBG_ERROR, "SGXSubmit2DKM: Invalid CCB offset")); 393 PVR_DPF((PVR_DBG_ERROR, "SGXSubmit2DKM: Invalid CCB offset"));
352 return PVRSRV_ERROR_INVALID_PARAMS; 394 return PVRSRV_ERROR_INVALID_PARAMS;
353 } 395 }
354 396
355 397
356 ps2DCmd = CCB_DATA_FROM_OFFSET(SGXMKIF_2DCMD_SHARED, psCCBMemInfo, psKick, ui32SharedCmdCCBOffset); 398 ps2DCmd = CCB_DATA_FROM_OFFSET(SGXMKIF_2DCMD_SHARED, psCCBMemInfo, psKick, ui32SharedCmdCCBOffset);
357 399
358 OSMemSet(ps2DCmd, 0, sizeof(*ps2DCmd)); 400 OSMemSet(ps2DCmd, 0, sizeof(*ps2DCmd));
359 401
360 402
361 if (psKick->hTASyncInfo != IMG_NULL) 403 if (psKick->hTASyncInfo != IMG_NULL)
362 { 404 {
363 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->hTASyncInfo; 405 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->hTASyncInfo;
@@ -365,11 +407,11 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
365 ps2DCmd->sTASyncData.ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending++; 407 ps2DCmd->sTASyncData.ui32WriteOpsPendingVal = psSyncInfo->psSyncData->ui32WriteOpsPending++;
366 ps2DCmd->sTASyncData.ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending; 408 ps2DCmd->sTASyncData.ui32ReadOpsPendingVal = psSyncInfo->psSyncData->ui32ReadOpsPending;
367 409
368 ps2DCmd->sTASyncData.sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr; 410 ps2DCmd->sTASyncData.sWriteOpsCompleteDevVAddr = psSyncInfo->sWriteOpsCompleteDevVAddr;
369 ps2DCmd->sTASyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; 411 ps2DCmd->sTASyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
370 } 412 }
371 413
372 414
373 if (psKick->h3DSyncInfo != IMG_NULL) 415 if (psKick->h3DSyncInfo != IMG_NULL)
374 { 416 {
375 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->h3DSyncInfo; 417 psSyncInfo = (PVRSRV_KERNEL_SYNC_INFO *)psKick->h3DSyncInfo;
@@ -381,7 +423,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
381 ps2DCmd->s3DSyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; 423 ps2DCmd->s3DSyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
382 } 424 }
383 425
384 426
385 ps2DCmd->ui32NumSrcSync = psKick->ui32NumSrcSync; 427 ps2DCmd->ui32NumSrcSync = psKick->ui32NumSrcSync;
386 for (i = 0; i < psKick->ui32NumSrcSync; i++) 428 for (i = 0; i < psKick->ui32NumSrcSync; i++)
387 { 429 {
@@ -405,7 +447,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
405 ps2DCmd->sDstSyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr; 447 ps2DCmd->sDstSyncData.sReadOpsCompleteDevVAddr = psSyncInfo->sReadOpsCompleteDevVAddr;
406 } 448 }
407 449
408 450
409 for (i = 0; i < psKick->ui32NumSrcSync; i++) 451 for (i = 0; i < psKick->ui32NumSrcSync; i++)
410 { 452 {
411 psSyncInfo = psKick->ahSrcSyncInfo[i]; 453 psSyncInfo = psKick->ahSrcSyncInfo[i];
@@ -423,7 +465,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
423 || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0)) 465 || ((psKick->ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0))
424 && (bPersistentProcess == IMG_FALSE) ) 466 && (bPersistentProcess == IMG_FALSE) )
425 { 467 {
426 468
427 PDUMPCOMMENT("Shared part of 2D command\r\n"); 469 PDUMPCOMMENT("Shared part of 2D command\r\n");
428 PDUMPMEM(ps2DCmd, 470 PDUMPMEM(ps2DCmd,
429 psCCBMemInfo, 471 psCCBMemInfo,
@@ -439,7 +481,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
439 PDUMPCOMMENT("Hack src surface write op in 2D cmd\r\n"); 481 PDUMPCOMMENT("Hack src surface write op in 2D cmd\r\n");
440 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, 482 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal,
441 psCCBMemInfo, 483 psCCBMemInfo,
442 psKick->ui32CCBDumpWOff + offsetof(SGXMKIF_2DCMD_SHARED, sSrcSyncData[i].ui32WriteOpsPendingVal), 484 psKick->ui32CCBDumpWOff + (IMG_UINT32)offsetof(SGXMKIF_2DCMD_SHARED, sSrcSyncData[i].ui32WriteOpsPendingVal),
443 sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal), 485 sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal),
444 psKick->ui32PDumpFlags, 486 psKick->ui32PDumpFlags,
445 MAKEUNIQUETAG(psCCBMemInfo)); 487 MAKEUNIQUETAG(psCCBMemInfo));
@@ -447,7 +489,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
447 PDUMPCOMMENT("Hack src surface read op in 2D cmd\r\n"); 489 PDUMPCOMMENT("Hack src surface read op in 2D cmd\r\n");
448 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, 490 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal,
449 psCCBMemInfo, 491 psCCBMemInfo,
450 psKick->ui32CCBDumpWOff + offsetof(SGXMKIF_2DCMD_SHARED, sSrcSyncData[i].ui32ReadOpsPendingVal), 492 psKick->ui32CCBDumpWOff + (IMG_UINT32)offsetof(SGXMKIF_2DCMD_SHARED, sSrcSyncData[i].ui32ReadOpsPendingVal),
451 sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal), 493 sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal),
452 psKick->ui32PDumpFlags, 494 psKick->ui32PDumpFlags,
453 MAKEUNIQUETAG(psCCBMemInfo)); 495 MAKEUNIQUETAG(psCCBMemInfo));
@@ -460,7 +502,7 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
460 PDUMPCOMMENT("Hack dest surface write op in 2D cmd\r\n"); 502 PDUMPCOMMENT("Hack dest surface write op in 2D cmd\r\n");
461 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal, 503 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastOpDumpVal,
462 psCCBMemInfo, 504 psCCBMemInfo,
463 psKick->ui32CCBDumpWOff + offsetof(SGXMKIF_2DCMD_SHARED, sDstSyncData.ui32WriteOpsPendingVal), 505 psKick->ui32CCBDumpWOff + (IMG_UINT32)offsetof(SGXMKIF_2DCMD_SHARED, sDstSyncData.ui32WriteOpsPendingVal),
464 sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal), 506 sizeof(psSyncInfo->psSyncData->ui32LastOpDumpVal),
465 psKick->ui32PDumpFlags, 507 psKick->ui32PDumpFlags,
466 MAKEUNIQUETAG(psCCBMemInfo)); 508 MAKEUNIQUETAG(psCCBMemInfo));
@@ -468,13 +510,13 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
468 PDUMPCOMMENT("Hack dest surface read op in 2D cmd\r\n"); 510 PDUMPCOMMENT("Hack dest surface read op in 2D cmd\r\n");
469 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal, 511 PDUMPMEM(&psSyncInfo->psSyncData->ui32LastReadOpDumpVal,
470 psCCBMemInfo, 512 psCCBMemInfo,
471 psKick->ui32CCBDumpWOff + offsetof(SGXMKIF_2DCMD_SHARED, sDstSyncData.ui32ReadOpsPendingVal), 513 psKick->ui32CCBDumpWOff + (IMG_UINT32)offsetof(SGXMKIF_2DCMD_SHARED, sDstSyncData.ui32ReadOpsPendingVal),
472 sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal), 514 sizeof(psSyncInfo->psSyncData->ui32LastReadOpDumpVal),
473 psKick->ui32PDumpFlags, 515 psKick->ui32PDumpFlags,
474 MAKEUNIQUETAG(psCCBMemInfo)); 516 MAKEUNIQUETAG(psCCBMemInfo));
475 } 517 }
476 518
477 519
478 for (i = 0; i < psKick->ui32NumSrcSync; i++) 520 for (i = 0; i < psKick->ui32NumSrcSync; i++)
479 { 521 {
480 psSyncInfo = psKick->ahSrcSyncInfo[i]; 522 psSyncInfo = psKick->ahSrcSyncInfo[i];
@@ -486,16 +528,16 @@ IMG_EXPORT PVRSRV_ERROR SGXSubmit2DKM(IMG_HANDLE hDevHandle, PVRSRV_2D_SGX_KICK
486 psSyncInfo = psKick->hDstSyncInfo; 528 psSyncInfo = psKick->hDstSyncInfo;
487 psSyncInfo->psSyncData->ui32LastOpDumpVal++; 529 psSyncInfo->psSyncData->ui32LastOpDumpVal++;
488 } 530 }
489 } 531 }
490#endif 532#endif
491 533
492 sCommand.ui32Data[1] = psKick->sHW2DContextDevVAddr.uiAddr; 534 sCommand.ui32Data[1] = psKick->sHW2DContextDevVAddr.uiAddr;
493 535
494 eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_2D, &sCommand, KERNEL_ID, psKick->ui32PDumpFlags, IMG_FALSE); 536 eError = SGXScheduleCCBCommandKM(hDevHandle, SGXMKIF_CMD_2D, &sCommand, KERNEL_ID, psKick->ui32PDumpFlags, hDevMemContext, IMG_FALSE);
495 537
496 if (eError == PVRSRV_ERROR_RETRY) 538 if (eError == PVRSRV_ERROR_RETRY)
497 { 539 {
498 540
499 541
500#if defined(PDUMP) 542#if defined(PDUMP)
501 if (PDumpIsCaptureFrameKM()) 543 if (PDumpIsCaptureFrameKM())
diff --git a/drivers/gpu/pvr/sgx/sgxutils.c b/drivers/gpu/pvr/sgx/sgxutils.c
index 7f640885b7f..0b205c5029f 100644
--- a/drivers/gpu/pvr/sgx/sgxutils.c
+++ b/drivers/gpu/pvr/sgx/sgxutils.c
@@ -40,6 +40,7 @@
40#include "osfunc.h" 40#include "osfunc.h"
41#include "pvr_debug.h" 41#include "pvr_debug.h"
42#include "sgxutils.h" 42#include "sgxutils.h"
43#include "ttrace.h"
43 44
44#ifdef __linux__ 45#ifdef __linux__
45#include <linux/kernel.h> 46#include <linux/kernel.h>
@@ -149,16 +150,23 @@ static INLINE SGXMKIF_COMMAND * SGXAcquireKernelCCBSlot(PVRSRV_SGX_CCB_INFO *psC
149 return IMG_NULL; 150 return IMG_NULL;
150} 151}
151 152
152PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo, 153PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_DEVICE_NODE *psDeviceNode,
153 SGXMKIF_CMD_TYPE eCmdType, 154 SGXMKIF_CMD_TYPE eCmdType,
154 SGXMKIF_COMMAND *psCommandData, 155 SGXMKIF_COMMAND *psCommandData,
155 IMG_UINT32 ui32CallerID, 156 IMG_UINT32 ui32CallerID,
156 IMG_UINT32 ui32PDumpFlags, 157 IMG_UINT32 ui32PDumpFlags,
157 IMG_BOOL bLastInScene) 158 IMG_HANDLE hDevMemContext,
159 IMG_BOOL bLastInScene)
158{ 160{
159 PVRSRV_SGX_CCB_INFO *psKernelCCB; 161 PVRSRV_SGX_CCB_INFO *psKernelCCB;
160 PVRSRV_ERROR eError = PVRSRV_OK; 162 PVRSRV_ERROR eError = PVRSRV_OK;
161 SGXMKIF_COMMAND *psSGXCommand; 163 SGXMKIF_COMMAND *psSGXCommand;
164 PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
165#if defined(FIX_HW_BRN_31620)
166 IMG_UINT32 ui32CacheMasks[4];
167 IMG_UINT32 i;
168 MMU_CONTEXT *psMMUContext;
169#endif
162#if defined(PDUMP) 170#if defined(PDUMP)
163 IMG_VOID *pvDumpCommand; 171 IMG_VOID *pvDumpCommand;
164 IMG_BOOL bPDumpIsSuspended = PDumpIsSuspended(); 172 IMG_BOOL bPDumpIsSuspended = PDumpIsSuspended();
@@ -168,12 +176,37 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
168 PVR_UNREFERENCED_PARAMETER(ui32PDumpFlags); 176 PVR_UNREFERENCED_PARAMETER(ui32PDumpFlags);
169#endif 177#endif
170 178
171#if defined(FIX_HW_BRN_28889) 179#if defined(FIX_HW_BRN_31620)
180 for(i=0;i<4;i++)
181 {
182 ui32CacheMasks[i] = 0;
183 }
172 184
185 psMMUContext = psDevInfo->hKernelMMUContext;
186 psDeviceNode->pfnMMUGetCacheFlushRange(psMMUContext, &ui32CacheMasks[0]);
173 187
188
189 if (hDevMemContext)
190 {
191 BM_CONTEXT *psBMContext = (BM_CONTEXT *) hDevMemContext;
174 192
193 psMMUContext = psBMContext->psMMUContext;
194 psDeviceNode->pfnMMUGetCacheFlushRange(psMMUContext, &ui32CacheMasks[2]);
195 }
175 196
176 if ( (eCmdType != SGXMKIF_CMD_PROCESS_QUEUES) && 197
198 if (ui32CacheMasks[0] || ui32CacheMasks[1] || ui32CacheMasks[2] || ui32CacheMasks[3])
199 {
200 psDevInfo->ui32CacheControl |= SGXMKIF_CC_INVAL_BIF_PD;
201 }
202#endif
203
204#if defined(FIX_HW_BRN_28889)
205
206
207
208
209 if ( (eCmdType != SGXMKIF_CMD_PROCESS_QUEUES) &&
177 ((psDevInfo->ui32CacheControl & SGXMKIF_CC_INVAL_DATA) != 0) && 210 ((psDevInfo->ui32CacheControl & SGXMKIF_CC_INVAL_DATA) != 0) &&
178 ((psDevInfo->ui32CacheControl & (SGXMKIF_CC_INVAL_BIF_PT | SGXMKIF_CC_INVAL_BIF_PD)) != 0)) 211 ((psDevInfo->ui32CacheControl & (SGXMKIF_CC_INVAL_BIF_PT | SGXMKIF_CC_INVAL_BIF_PD)) != 0))
179 { 212 {
@@ -183,18 +216,19 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
183 SGXMKIF_HOST_CTL *psSGXHostCtl = psDevInfo->psSGXHostCtl; 216 SGXMKIF_HOST_CTL *psSGXHostCtl = psDevInfo->psSGXHostCtl;
184 SGXMKIF_COMMAND sCacheCommand = {0}; 217 SGXMKIF_COMMAND sCacheCommand = {0};
185 218
186 eError = SGXScheduleCCBCommand(psDevInfo, 219 eError = SGXScheduleCCBCommand(psDeviceNode,
187 SGXMKIF_CMD_PROCESS_QUEUES, 220 SGXMKIF_CMD_PROCESS_QUEUES,
188 &sCacheCommand, 221 &sCacheCommand,
189 ui32CallerID, 222 ui32CallerID,
190 ui32PDumpFlags, 223 ui32PDumpFlags,
224 hDevMemContext,
191 bLastInScene); 225 bLastInScene);
192 if (eError != PVRSRV_OK) 226 if (eError != PVRSRV_OK)
193 { 227 {
194 goto Exit; 228 goto Exit;
195 } 229 }
196 230
197 231
198 #if !defined(NO_HARDWARE) 232 #if !defined(NO_HARDWARE)
199 if(PollForValueKM(&psSGXHostCtl->ui32InvalStatus, 233 if(PollForValueKM(&psSGXHostCtl->ui32InvalStatus,
200 PVRSRV_USSE_EDM_BIF_INVAL_COMPLETE, 234 PVRSRV_USSE_EDM_BIF_INVAL_COMPLETE,
@@ -207,9 +241,9 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
207 PVR_DBG_BREAK; 241 PVR_DBG_BREAK;
208 } 242 }
209 #endif 243 #endif
210 244
211 #if defined(PDUMP) 245 #if defined(PDUMP)
212 246
213 PDUMPCOMMENTWITHFLAGS(0, "Host Control - Poll for BIF cache invalidate request to complete"); 247 PDUMPCOMMENTWITHFLAGS(0, "Host Control - Poll for BIF cache invalidate request to complete");
214 PDUMPMEMPOL(psSGXHostCtlMemInfo, 248 PDUMPMEMPOL(psSGXHostCtlMemInfo,
215 offsetof(SGXMKIF_HOST_CTL, ui32InvalStatus), 249 offsetof(SGXMKIF_HOST_CTL, ui32InvalStatus),
@@ -218,15 +252,63 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
218 PDUMP_POLL_OPERATOR_EQUAL, 252 PDUMP_POLL_OPERATOR_EQUAL,
219 0, 253 0,
220 MAKEUNIQUETAG(psSGXHostCtlMemInfo)); 254 MAKEUNIQUETAG(psSGXHostCtlMemInfo));
221 #endif 255 #endif
222 256
223 psSGXHostCtl->ui32InvalStatus &= ~(PVRSRV_USSE_EDM_BIF_INVAL_COMPLETE); 257 psSGXHostCtl->ui32InvalStatus &= ~(PVRSRV_USSE_EDM_BIF_INVAL_COMPLETE);
224 PDUMPMEM(IMG_NULL, psSGXHostCtlMemInfo, offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus), sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psSGXHostCtlMemInfo)); 258 PDUMPMEM(IMG_NULL, psSGXHostCtlMemInfo, offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus), sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psSGXHostCtlMemInfo));
225 } 259 }
260#else
261 PVR_UNREFERENCED_PARAMETER(hDevMemContext);
226#endif 262#endif
263
264#if defined(FIX_HW_BRN_31620)
265 if ((eCmdType != SGXMKIF_CMD_FLUSHPDCACHE) && (psDevInfo->ui32CacheControl & SGXMKIF_CC_INVAL_BIF_PD))
266 {
267 SGXMKIF_COMMAND sPDECacheCommand = {0};
268 IMG_DEV_PHYADDR sDevPAddr;
227 269
228#if defined(PDUMP) 270
271 psMMUContext = psDevInfo->hKernelMMUContext;
272
273 psDeviceNode->pfnMMUGetPDPhysAddr(psMMUContext, &sDevPAddr);
274 sPDECacheCommand.ui32Data[0] = sDevPAddr.uiAddr | 1;
275 sPDECacheCommand.ui32Data[1] = ui32CacheMasks[0];
276 sPDECacheCommand.ui32Data[2] = ui32CacheMasks[1];
277
278
279 if (hDevMemContext)
280 {
281 BM_CONTEXT *psBMContext = (BM_CONTEXT *) hDevMemContext;
229 282
283 psMMUContext = psBMContext->psMMUContext;
284
285 psDeviceNode->pfnMMUGetPDPhysAddr(psMMUContext, &sDevPAddr);
286
287 sPDECacheCommand.ui32Data[3] = sDevPAddr.uiAddr | 1;
288 sPDECacheCommand.ui32Data[4] = ui32CacheMasks[2];
289 sPDECacheCommand.ui32Data[5] = ui32CacheMasks[3];
290 }
291
292
293 if (sPDECacheCommand.ui32Data[1] | sPDECacheCommand.ui32Data[2] | sPDECacheCommand.ui32Data[4] |
294 sPDECacheCommand.ui32Data[5])
295 {
296 eError = SGXScheduleCCBCommand(psDeviceNode,
297 SGXMKIF_CMD_FLUSHPDCACHE,
298 &sPDECacheCommand,
299 ui32CallerID,
300 ui32PDumpFlags,
301 hDevMemContext,
302 bLastInScene);
303 if (eError != PVRSRV_OK)
304 {
305 goto Exit;
306 }
307 }
308 }
309#endif
310#if defined(PDUMP)
311
230 { 312 {
231 PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData(); 313 PVRSRV_PER_PROCESS_DATA* psPerProc = PVRSRVFindPerProcessData();
232 if(psPerProc != IMG_NULL) 314 if(psPerProc != IMG_NULL)
@@ -234,44 +316,45 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
234 bPersistentProcess = psPerProc->bPDumpPersistent; 316 bPersistentProcess = psPerProc->bPDumpPersistent;
235 } 317 }
236 } 318 }
237#endif 319#endif
238 psKernelCCB = psDevInfo->psKernelCCBInfo; 320 psKernelCCB = psDevInfo->psKernelCCBInfo;
239 321
240 psSGXCommand = SGXAcquireKernelCCBSlot(psKernelCCB); 322 psSGXCommand = SGXAcquireKernelCCBSlot(psKernelCCB);
241 323
242 324
243 if(!psSGXCommand) 325 if(!psSGXCommand)
244 { 326 {
327 PVR_DPF((PVR_DBG_ERROR, "SGXScheduleCCBCommand: Wait for CCB space timed out")) ;
245 eError = PVRSRV_ERROR_TIMEOUT; 328 eError = PVRSRV_ERROR_TIMEOUT;
246 goto Exit; 329 goto Exit;
247 } 330 }
248 331
249 332
250 psCommandData->ui32CacheControl = psDevInfo->ui32CacheControl; 333 psCommandData->ui32CacheControl = psDevInfo->ui32CacheControl;
251 334
252#if defined(PDUMP) 335#if defined(PDUMP)
253 336
254 psDevInfo->sPDContext.ui32CacheControl |= psDevInfo->ui32CacheControl; 337 psDevInfo->sPDContext.ui32CacheControl |= psDevInfo->ui32CacheControl;
255#endif 338#endif
256 339
257 340
258 psDevInfo->ui32CacheControl = 0; 341 psDevInfo->ui32CacheControl = 0;
259 342
260 343
261 *psSGXCommand = *psCommandData; 344 *psSGXCommand = *psCommandData;
262 345
263 if (eCmdType >= SGXMKIF_CMD_MAX) 346 if (eCmdType >= SGXMKIF_CMD_MAX)
264 { 347 {
265 PVR_DPF((PVR_DBG_ERROR,"SGXScheduleCCBCommandKM: Unknown command type: %d", eCmdType)) ; 348 PVR_DPF((PVR_DBG_ERROR, "SGXScheduleCCBCommand: Unknown command type: %d", eCmdType)) ;
266 eError = PVRSRV_ERROR_INVALID_CCB_COMMAND; 349 eError = PVRSRV_ERROR_INVALID_CCB_COMMAND;
267 goto Exit; 350 goto Exit;
268 } 351 }
269 352
270 if((eCmdType == SGXMKIF_CMD_TA) && bLastInScene) 353 if ((eCmdType == SGXMKIF_CMD_TA) && bLastInScene)
271 { 354 {
272 SYS_DATA *psSysData; 355 SYS_DATA *psSysData;
273 356
274 357
275 SysAcquireData(&psSysData); 358 SysAcquireData(&psSysData);
276 359
277 if(psSysData->ePendingCacheOpType == PVRSRV_MISC_INFO_CPUCACHEOP_FLUSH) 360 if(psSysData->ePendingCacheOpType == PVRSRV_MISC_INFO_CPUCACHEOP_FLUSH)
@@ -283,18 +366,18 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
283 OSCleanCPUCacheKM(); 366 OSCleanCPUCacheKM();
284 } 367 }
285 368
286 369
287 psSysData->ePendingCacheOpType = PVRSRV_MISC_INFO_CPUCACHEOP_NONE; 370 psSysData->ePendingCacheOpType = PVRSRV_MISC_INFO_CPUCACHEOP_NONE;
288 } 371 }
289 372
290 PVR_ASSERT(eCmdType < SGXMKIF_CMD_MAX); 373 PVR_ASSERT(eCmdType < SGXMKIF_CMD_MAX);
291 psSGXCommand->ui32ServiceAddress = psDevInfo->aui32HostKickAddr[eCmdType]; 374 psSGXCommand->ui32ServiceAddress = psDevInfo->aui32HostKickAddr[eCmdType];
292 375
293#if defined(PDUMP) 376#if defined(PDUMP)
294 if ((ui32CallerID != ISR_ID) && (bPDumpIsSuspended == IMG_FALSE) && 377 if ((ui32CallerID != ISR_ID) && (bPDumpIsSuspended == IMG_FALSE) &&
295 (bPersistentProcess == IMG_FALSE) ) 378 (bPersistentProcess == IMG_FALSE) )
296 { 379 {
297 380
298 PDUMPCOMMENTWITHFLAGS(ui32PDumpFlags, "Poll for space in the Kernel CCB\r\n"); 381 PDUMPCOMMENTWITHFLAGS(ui32PDumpFlags, "Poll for space in the Kernel CCB\r\n");
299 PDUMPMEMPOL(psKernelCCB->psCCBCtlMemInfo, 382 PDUMPMEMPOL(psKernelCCB->psCCBCtlMemInfo,
300 offsetof(PVRSRV_SGX_CCB_CTL, ui32ReadOffset), 383 offsetof(PVRSRV_SGX_CCB_CTL, ui32ReadOffset),
@@ -314,7 +397,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
314 ui32PDumpFlags, 397 ui32PDumpFlags,
315 MAKEUNIQUETAG(psKernelCCB->psCCBMemInfo)); 398 MAKEUNIQUETAG(psKernelCCB->psCCBMemInfo));
316 399
317 400
318 PDUMPMEM(&psDevInfo->sPDContext.ui32CacheControl, 401 PDUMPMEM(&psDevInfo->sPDContext.ui32CacheControl,
319 psKernelCCB->psCCBMemInfo, 402 psKernelCCB->psCCBMemInfo,
320 psKernelCCB->ui32CCBDumpWOff * sizeof(SGXMKIF_COMMAND) + 403 psKernelCCB->ui32CCBDumpWOff * sizeof(SGXMKIF_COMMAND) +
@@ -326,14 +409,14 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
326 if (PDumpIsCaptureFrameKM() 409 if (PDumpIsCaptureFrameKM()
327 || ((ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0)) 410 || ((ui32PDumpFlags & PDUMP_FLAGS_CONTINUOUS) != 0))
328 { 411 {
329 412
330 psDevInfo->sPDContext.ui32CacheControl = 0; 413 psDevInfo->sPDContext.ui32CacheControl = 0;
331 } 414 }
332 } 415 }
333#endif 416#endif
334 417
335#if defined(FIX_HW_BRN_26620) && defined(SGX_FEATURE_SYSTEM_CACHE) && !defined(SGX_BYPASS_SYSTEM_CACHE) 418#if defined(FIX_HW_BRN_26620) && defined(SGX_FEATURE_SYSTEM_CACHE) && !defined(SGX_BYPASS_SYSTEM_CACHE)
336 419
337 eError = PollForValueKM (psKernelCCB->pui32ReadOffset, 420 eError = PollForValueKM (psKernelCCB->pui32ReadOffset,
338 *psKernelCCB->pui32WriteOffset, 421 *psKernelCCB->pui32WriteOffset,
339 0xFF, 422 0xFF,
@@ -342,12 +425,13 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
342 IMG_FALSE); 425 IMG_FALSE);
343 if (eError != PVRSRV_OK) 426 if (eError != PVRSRV_OK)
344 { 427 {
428 PVR_DPF((PVR_DBG_ERROR, "SGXScheduleCCBCommand: Timeout waiting for previous command to be read")) ;
345 eError = PVRSRV_ERROR_TIMEOUT; 429 eError = PVRSRV_ERROR_TIMEOUT;
346 goto Exit; 430 goto Exit;
347 } 431 }
348#endif 432#endif
349 433
350 434
351 435
352 *psKernelCCB->pui32WriteOffset = (*psKernelCCB->pui32WriteOffset + 1) & 255; 436 *psKernelCCB->pui32WriteOffset = (*psKernelCCB->pui32WriteOffset + 1) & 255;
353 437
@@ -400,6 +484,15 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
400 484
401 OSWriteMemoryBarrier(); 485 OSWriteMemoryBarrier();
402 486
487
488 PVR_TTRACE_UI32(PVRSRV_TRACE_GROUP_MKSYNC, PVRSRV_TRACE_CLASS_NONE,
489 MKSYNC_TOKEN_KERNEL_CCB_OFFSET, *psKernelCCB->pui32WriteOffset);
490 PVR_TTRACE_UI32(PVRSRV_TRACE_GROUP_MKSYNC, PVRSRV_TRACE_CLASS_NONE,
491 MKSYNC_TOKEN_CORE_CLK, psDevInfo->ui32CoreClockSpeed);
492 PVR_TTRACE_UI32(PVRSRV_TRACE_GROUP_MKSYNC, PVRSRV_TRACE_CLASS_NONE,
493 MKSYNC_TOKEN_UKERNEL_CLK, psDevInfo->ui32uKernelTimerClock);
494
495
403#if defined(FIX_HW_BRN_26620) && defined(SGX_FEATURE_SYSTEM_CACHE) && !defined(SGX_BYPASS_SYSTEM_CACHE) 496#if defined(FIX_HW_BRN_26620) && defined(SGX_FEATURE_SYSTEM_CACHE) && !defined(SGX_BYPASS_SYSTEM_CACHE)
404 OSWriteHWReg(psDevInfo->pvRegsBaseKM, 497 OSWriteHWReg(psDevInfo->pvRegsBaseKM,
405 SGX_MP_CORE_SELECT(EUR_CR_EVENT_KICK2, 0), 498 SGX_MP_CORE_SELECT(EUR_CR_EVENT_KICK2, 0),
@@ -413,7 +506,7 @@ PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo,
413 OSMemoryBarrier(); 506 OSMemoryBarrier();
414 507
415#if defined(NO_HARDWARE) 508#if defined(NO_HARDWARE)
416 509
417 *psKernelCCB->pui32ReadOffset = (*psKernelCCB->pui32ReadOffset + 1) & 255; 510 *psKernelCCB->pui32ReadOffset = (*psKernelCCB->pui32ReadOffset + 1) & 255;
418#endif 511#endif
419 512
@@ -427,10 +520,10 @@ PVRSRV_ERROR SGXScheduleCCBCommandKM(PVRSRV_DEVICE_NODE *psDeviceNode,
427 SGXMKIF_COMMAND *psCommandData, 520 SGXMKIF_COMMAND *psCommandData,
428 IMG_UINT32 ui32CallerID, 521 IMG_UINT32 ui32CallerID,
429 IMG_UINT32 ui32PDumpFlags, 522 IMG_UINT32 ui32PDumpFlags,
523 IMG_HANDLE hDevMemContext,
430 IMG_BOOL bLastInScene) 524 IMG_BOOL bLastInScene)
431{ 525{
432 PVRSRV_ERROR eError; 526 PVRSRV_ERROR eError;
433 PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
434 527
435 528
436 PDUMPSUSPEND(); 529 PDUMPSUSPEND();
@@ -474,7 +567,7 @@ PVRSRV_ERROR SGXScheduleCCBCommandKM(PVRSRV_DEVICE_NODE *psDeviceNode,
474 return eError; 567 return eError;
475 } 568 }
476 569
477 eError = SGXScheduleCCBCommand(psDevInfo, eCmdType, psCommandData, ui32CallerID, ui32PDumpFlags, bLastInScene); 570 eError = SGXScheduleCCBCommand(psDeviceNode, eCmdType, psCommandData, ui32CallerID, ui32PDumpFlags, hDevMemContext, bLastInScene);
478 571
479 PVRSRVPowerUnlock(ui32CallerID); 572 PVRSRVPowerUnlock(ui32CallerID);
480 573
@@ -496,7 +589,7 @@ PVRSRV_ERROR SGXScheduleProcessQueuesKM(PVRSRV_DEVICE_NODE *psDeviceNode)
496 PVRSRV_ERROR eError; 589 PVRSRV_ERROR eError;
497 PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice; 590 PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
498 SGXMKIF_HOST_CTL *psHostCtl = psDevInfo->psKernelSGXHostCtlMemInfo->pvLinAddrKM; 591 SGXMKIF_HOST_CTL *psHostCtl = psDevInfo->psKernelSGXHostCtlMemInfo->pvLinAddrKM;
499 IMG_UINT32 ui32PowerStatus; 592 IMG_UINT32 ui32PowerStatus;
500 SGXMKIF_COMMAND sCommand = {0}; 593 SGXMKIF_COMMAND sCommand = {0};
501 594
502 ui32PowerStatus = psHostCtl->ui32PowerStatus; 595 ui32PowerStatus = psHostCtl->ui32PowerStatus;
@@ -506,7 +599,7 @@ PVRSRV_ERROR SGXScheduleProcessQueuesKM(PVRSRV_DEVICE_NODE *psDeviceNode)
506 return PVRSRV_OK; 599 return PVRSRV_OK;
507 } 600 }
508 601
509 eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_PROCESS_QUEUES, &sCommand, ISR_ID, 0, IMG_FALSE); 602 eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_PROCESS_QUEUES, &sCommand, ISR_ID, 0, IMG_NULL, IMG_FALSE);
510 if (eError != PVRSRV_OK) 603 if (eError != PVRSRV_OK)
511 { 604 {
512 PVR_DPF((PVR_DBG_ERROR,"SGXScheduleProcessQueuesKM failed to schedule CCB command: %u", eError)); 605 PVR_DPF((PVR_DBG_ERROR,"SGXScheduleProcessQueuesKM failed to schedule CCB command: %u", eError));
@@ -524,7 +617,11 @@ IMG_BOOL SGXIsDevicePowered(PVRSRV_DEVICE_NODE *psDeviceNode)
524 617
525IMG_EXPORT 618IMG_EXPORT
526PVRSRV_ERROR SGXGetInternalDevInfoKM(IMG_HANDLE hDevCookie, 619PVRSRV_ERROR SGXGetInternalDevInfoKM(IMG_HANDLE hDevCookie,
620#if defined (SUPPORT_SID_INTERFACE)
621 SGX_INTERNAL_DEVINFO_KM *psSGXInternalDevInfo)
622#else
527 SGX_INTERNAL_DEVINFO *psSGXInternalDevInfo) 623 SGX_INTERNAL_DEVINFO *psSGXInternalDevInfo)
624#endif
528{ 625{
529 PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *)((PVRSRV_DEVICE_NODE *)hDevCookie)->pvDevice; 626 PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *)((PVRSRV_DEVICE_NODE *)hDevCookie)->pvDevice;
530 627
@@ -544,65 +641,58 @@ IMG_VOID SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode,
544 IMG_UINT32 ui32CleanupType) 641 IMG_UINT32 ui32CleanupType)
545{ 642{
546 PVRSRV_ERROR eError; 643 PVRSRV_ERROR eError;
547 PVRSRV_SGXDEV_INFO *psSGXDevInfo = psDeviceNode->pvDevice; 644 PVRSRV_SGXDEV_INFO *psDevInfo = psDeviceNode->pvDevice;
548 PVRSRV_KERNEL_MEM_INFO *psSGXHostCtlMemInfo = psSGXDevInfo->psKernelSGXHostCtlMemInfo; 645 PVRSRV_KERNEL_MEM_INFO *psHostCtlMemInfo = psDevInfo->psKernelSGXHostCtlMemInfo;
549 SGXMKIF_HOST_CTL *psSGXHostCtl = psSGXHostCtlMemInfo->pvLinAddrKM; 646 SGXMKIF_HOST_CTL *psHostCtl = psHostCtlMemInfo->pvLinAddrKM;
550 647
551 if ((psSGXHostCtl->ui32PowerStatus & PVRSRV_USSE_EDM_POWMAN_NO_WORK) != 0) 648 SGXMKIF_COMMAND sCommand = {0};
552 {
553
554 }
555 else
556 {
557 SGXMKIF_COMMAND sCommand = {0};
558
559 PDUMPCOMMENTWITHFLAGS(0, "Request ukernel resouce clean-up");
560 sCommand.ui32Data[0] = ui32CleanupType;
561 sCommand.ui32Data[1] = (psHWDataDevVAddr == IMG_NULL) ? 0 : psHWDataDevVAddr->uiAddr;
562
563 eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_CLEANUP, &sCommand, KERNEL_ID, 0, IMG_FALSE);
564 if (eError != PVRSRV_OK)
565 {
566 PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Failed to submit clean-up command"));
567 PVR_DBG_BREAK;
568 }
569 649
570 650 sCommand.ui32Data[0] = ui32CleanupType;
571 #if !defined(NO_HARDWARE) 651 sCommand.ui32Data[1] = (psHWDataDevVAddr == IMG_NULL) ? 0 : psHWDataDevVAddr->uiAddr;
572 if(PollForValueKM(&psSGXHostCtl->ui32CleanupStatus, 652 PDUMPCOMMENTWITHFLAGS(0, "Request ukernel resource clean-up, Type %u, Data 0x%X", sCommand.ui32Data[0], sCommand.ui32Data[1]);
573 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
574 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
575 10 * MAX_HW_TIME_US,
576 1000,
577 IMG_TRUE) != PVRSRV_OK)
578 {
579 PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Wait for uKernel to clean up (%u) failed", ui32CleanupType));
580 PVR_DBG_BREAK;
581 }
582 #endif
583 653
584 #if defined(PDUMP) 654 eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_CLEANUP, &sCommand, KERNEL_ID, 0, IMG_NULL, IMG_FALSE);
585 655 if (eError != PVRSRV_OK)
586 PDUMPCOMMENTWITHFLAGS(0, "Host Control - Poll for clean-up request to complete"); 656 {
587 PDUMPMEMPOL(psSGXHostCtlMemInfo, 657 PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Failed to submit clean-up command"));
588 offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus), 658 PVR_DBG_BREAK;
589 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE, 659 }
590 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
591 PDUMP_POLL_OPERATOR_EQUAL,
592 0,
593 MAKEUNIQUETAG(psSGXHostCtlMemInfo));
594 #endif
595 660
596 psSGXHostCtl->ui32CleanupStatus &= ~(PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE); 661
597 PDUMPMEM(IMG_NULL, psSGXHostCtlMemInfo, offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus), sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psSGXHostCtlMemInfo)); 662 #if !defined(NO_HARDWARE)
598 663 if(PollForValueKM(&psHostCtl->ui32CleanupStatus,
599 664 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
600 #if defined(SGX_FEATURE_SYSTEM_CACHE) 665 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
601 psSGXDevInfo->ui32CacheControl |= (SGXMKIF_CC_INVAL_BIF_SL | SGXMKIF_CC_INVAL_DATA); 666 10 * MAX_HW_TIME_US,
602 #else 667 1000,
603 psSGXDevInfo->ui32CacheControl |= SGXMKIF_CC_INVAL_DATA; 668 IMG_TRUE) != PVRSRV_OK)
604 #endif 669 {
670 PVR_DPF((PVR_DBG_ERROR,"SGXCleanupRequest: Wait for uKernel to clean up (%u) failed", ui32CleanupType));
671 PVR_DBG_BREAK;
605 } 672 }
673 #endif
674
675 #if defined(PDUMP)
676
677 PDUMPCOMMENTWITHFLAGS(0, "Host Control - Poll for clean-up request to complete");
678 PDUMPMEMPOL(psHostCtlMemInfo,
679 offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus),
680 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
681 PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE,
682 PDUMP_POLL_OPERATOR_EQUAL,
683 0,
684 MAKEUNIQUETAG(psHostCtlMemInfo));
685 #endif
686
687 psHostCtl->ui32CleanupStatus &= ~(PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE);
688 PDUMPMEM(IMG_NULL, psHostCtlMemInfo, offsetof(SGXMKIF_HOST_CTL, ui32CleanupStatus), sizeof(IMG_UINT32), 0, MAKEUNIQUETAG(psHostCtlMemInfo));
689
690
691#if defined(SGX_FEATURE_SYSTEM_CACHE)
692 psDevInfo->ui32CacheControl |= (SGXMKIF_CC_INVAL_BIF_SL | SGXMKIF_CC_INVAL_DATA);
693#else
694 psDevInfo->ui32CacheControl |= SGXMKIF_CC_INVAL_DATA;
695#endif
606} 696}
607 697
608 698
@@ -1018,3 +1108,40 @@ IMG_UINT32 SGXConvertTimeStamp(PVRSRV_SGXDEV_INFO *psDevInfo,
1018 1108
1019 1109
1020 1110
1111IMG_EXPORT
1112PVRSRV_ERROR PVRSRVGetSGXRevDataKM(PVRSRV_DEVICE_NODE* psDeviceNode, IMG_UINT32 *pui32SGXCoreRev,
1113 IMG_UINT32 *pui32SGXCoreID)
1114{
1115 PVRSRV_SGXDEV_INFO *psDevInfo = (PVRSRV_SGXDEV_INFO *)psDeviceNode->pvDevice;
1116 SGX_MISC_INFO sMiscInfo;
1117 PVRSRV_ERROR eError;
1118
1119 sMiscInfo.eRequest = SGX_MISC_INFO_REQUEST_SGXREV;
1120 eError = SGXGetMiscInfoKM(psDevInfo, &sMiscInfo, psDeviceNode, NULL);
1121
1122 *pui32SGXCoreRev = sMiscInfo.uData.sSGXFeatures.ui32CoreRev;
1123 *pui32SGXCoreID = sMiscInfo.uData.sSGXFeatures.ui32CoreID;
1124 return eError;
1125}
1126
1127
1128PVRSRV_ERROR SGXContextSuspend(PVRSRV_DEVICE_NODE *psDeviceNode,
1129 IMG_DEV_VIRTADDR *psHWContextDevVAddr,
1130 IMG_BOOL bResume)
1131{
1132 PVRSRV_ERROR eError;
1133 SGXMKIF_COMMAND sCommand = {0};
1134
1135 sCommand.ui32Data[0] = psHWContextDevVAddr->uiAddr;
1136 sCommand.ui32Data[1] = bResume ? PVRSRV_CTXSUSPCMD_RESUME : PVRSRV_CTXSUSPCMD_SUSPEND;
1137
1138 eError = SGXScheduleCCBCommandKM(psDeviceNode, SGXMKIF_CMD_CONTEXTSUSPEND, &sCommand, KERNEL_ID, 0, IMG_NULL, IMG_FALSE);
1139 if (eError != PVRSRV_OK)
1140 {
1141 PVR_DPF((PVR_DBG_ERROR,"SGXContextSuspend: Failed to submit context suspend command"));
1142 return eError;
1143 }
1144
1145 return eError;
1146}
1147
diff --git a/drivers/gpu/pvr/sgx/sgxutils.h b/drivers/gpu/pvr/sgx/sgxutils.h
index ef03e4f3454..51e8696547f 100644
--- a/drivers/gpu/pvr/sgx/sgxutils.h
+++ b/drivers/gpu/pvr/sgx/sgxutils.h
@@ -27,10 +27,10 @@
27#include "perproc.h" 27#include "perproc.h"
28#include "sgxinfokm.h" 28#include "sgxinfokm.h"
29 29
30 30
31#define CCB_OFFSET_IS_VALID(type, psCCBMemInfo, psCCBKick, offset) \ 31#define CCB_OFFSET_IS_VALID(type, psCCBMemInfo, psCCBKick, offset) \
32 ((sizeof(type) <= (psCCBMemInfo)->ui32AllocSize) && \ 32 ((sizeof(type) <= (psCCBMemInfo)->uAllocSize) && \
33 ((psCCBKick)->offset <= (psCCBMemInfo)->ui32AllocSize - sizeof(type))) 33 ((psCCBKick)->offset <= (psCCBMemInfo)->uAllocSize - sizeof(type)))
34 34
35#define CCB_DATA_FROM_OFFSET(type, psCCBMemInfo, psCCBKick, offset) \ 35#define CCB_DATA_FROM_OFFSET(type, psCCBMemInfo, psCCBKick, offset) \
36 ((type *)(((IMG_CHAR *)(psCCBMemInfo)->pvLinAddrKM) + \ 36 ((type *)(((IMG_CHAR *)(psCCBMemInfo)->pvLinAddrKM) + \
@@ -42,18 +42,20 @@ IMG_VOID SGXTestActivePowerEvent(PVRSRV_DEVICE_NODE *psDeviceNode,
42 IMG_UINT32 ui32CallerID); 42 IMG_UINT32 ui32CallerID);
43 43
44IMG_IMPORT 44IMG_IMPORT
45PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_SGXDEV_INFO *psDevInfo, 45PVRSRV_ERROR SGXScheduleCCBCommand(PVRSRV_DEVICE_NODE *psDeviceNode,
46 SGXMKIF_CMD_TYPE eCommandType, 46 SGXMKIF_CMD_TYPE eCommandType,
47 SGXMKIF_COMMAND *psCommandData, 47 SGXMKIF_COMMAND *psCommandData,
48 IMG_UINT32 ui32CallerID, 48 IMG_UINT32 ui32CallerID,
49 IMG_UINT32 ui32PDumpFlags, 49 IMG_UINT32 ui32PDumpFlags,
50 IMG_BOOL bLastInScene); 50 IMG_HANDLE hDevMemContext,
51 IMG_BOOL bLastInScene);
51IMG_IMPORT 52IMG_IMPORT
52PVRSRV_ERROR SGXScheduleCCBCommandKM(PVRSRV_DEVICE_NODE *psDeviceNode, 53PVRSRV_ERROR SGXScheduleCCBCommandKM(PVRSRV_DEVICE_NODE *psDeviceNode,
53 SGXMKIF_CMD_TYPE eCommandType, 54 SGXMKIF_CMD_TYPE eCommandType,
54 SGXMKIF_COMMAND *psCommandData, 55 SGXMKIF_COMMAND *psCommandData,
55 IMG_UINT32 ui32CallerID, 56 IMG_UINT32 ui32CallerID,
56 IMG_UINT32 ui32PDumpFlags, 57 IMG_UINT32 ui32PDumpFlags,
58 IMG_HANDLE hDevMemContext,
57 IMG_BOOL bLastInScene); 59 IMG_BOOL bLastInScene);
58 60
59IMG_IMPORT 61IMG_IMPORT
@@ -99,4 +101,11 @@ IMG_VOID SGXCleanupRequest(PVRSRV_DEVICE_NODE *psDeviceNode,
99 IMG_DEV_VIRTADDR *psHWDataDevVAddr, 101 IMG_DEV_VIRTADDR *psHWDataDevVAddr,
100 IMG_UINT32 ui32CleanupType); 102 IMG_UINT32 ui32CleanupType);
101 103
104IMG_IMPORT
105PVRSRV_ERROR PVRSRVGetSGXRevDataKM(PVRSRV_DEVICE_NODE* psDeviceNode, IMG_UINT32 *pui32SGXCoreRev,
106 IMG_UINT32 *pui32SGXCoreID);
107
108PVRSRV_ERROR SGXContextSuspend(PVRSRV_DEVICE_NODE *psDeviceNode,
109 IMG_DEV_VIRTADDR *psHWContextDevVAddr,
110 IMG_BOOL bResume);
102 111
diff --git a/drivers/gpu/pvr/sgx531defs.h b/drivers/gpu/pvr/sgx531defs.h
new file mode 100644
index 00000000000..b0c663c2be7
--- /dev/null
+++ b/drivers/gpu/pvr/sgx531defs.h
@@ -0,0 +1,544 @@
1/**********************************************************************
2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 *
25 ******************************************************************************/
26
27#ifndef _SGX531DEFS_KM_H_
28#define _SGX531DEFS_KM_H_
29
30#define EUR_CR_CLKGATECTL 0x0000
31#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U
32#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0
33#define EUR_CR_CLKGATECTL_ISP2_CLKG_MASK 0x0000000CU
34#define EUR_CR_CLKGATECTL_ISP2_CLKG_SHIFT 2
35#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000030U
36#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 4
37#define EUR_CR_CLKGATECTL_TE_CLKG_MASK 0x000000C0U
38#define EUR_CR_CLKGATECTL_TE_CLKG_SHIFT 6
39#define EUR_CR_CLKGATECTL_MTE_CLKG_MASK 0x00000300U
40#define EUR_CR_CLKGATECTL_MTE_CLKG_SHIFT 8
41#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00000C00U
42#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 10
43#define EUR_CR_CLKGATECTL_VDM_CLKG_MASK 0x00003000U
44#define EUR_CR_CLKGATECTL_VDM_CLKG_SHIFT 12
45#define EUR_CR_CLKGATECTL_PDS_CLKG_MASK 0x0000C000U
46#define EUR_CR_CLKGATECTL_PDS_CLKG_SHIFT 14
47#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_MASK 0x00030000U
48#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SHIFT 16
49#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x000C0000U
50#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 18
51#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U
52#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24
53#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_MASK 0x10000000U
54#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SHIFT 28
55#define EUR_CR_CLKGATECTL2 0x0004
56#define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U
57#define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0
58#define EUR_CR_CLKGATECTL2_CACHEL2_CLKG_MASK 0x0000000CU
59#define EUR_CR_CLKGATECTL2_CACHEL2_CLKG_SHIFT 2
60#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_MASK 0x00000030U
61#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SHIFT 4
62#define EUR_CR_CLKGATECTL2_USE0_CLKG_MASK 0x000000C0U
63#define EUR_CR_CLKGATECTL2_USE0_CLKG_SHIFT 6
64#define EUR_CR_CLKGATECTL2_ITR0_CLKG_MASK 0x00000300U
65#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SHIFT 8
66#define EUR_CR_CLKGATECTL2_TEX0_CLKG_MASK 0x00000C00U
67#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SHIFT 10
68#define EUR_CR_CLKGATECTL2_MADD0_CLKG_MASK 0x00003000U
69#define EUR_CR_CLKGATECTL2_MADD0_CLKG_SHIFT 12
70#define EUR_CR_CLKGATECTL2_USE1_CLKG_MASK 0x0000C000U
71#define EUR_CR_CLKGATECTL2_USE1_CLKG_SHIFT 14
72#define EUR_CR_CLKGATECTL2_ITR1_CLKG_MASK 0x00030000U
73#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SHIFT 16
74#define EUR_CR_CLKGATECTL2_TEX1_CLKG_MASK 0x000C0000U
75#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SHIFT 18
76#define EUR_CR_CLKGATECTL2_MADD1_CLKG_MASK 0x00300000U
77#define EUR_CR_CLKGATECTL2_MADD1_CLKG_SHIFT 20
78#define EUR_CR_CLKGATESTATUS 0x0008
79#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U
80#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0
81#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_MASK 0x00000002U
82#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SHIFT 1
83#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000004U
84#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 2
85#define EUR_CR_CLKGATESTATUS_TE_CLKS_MASK 0x00000008U
86#define EUR_CR_CLKGATESTATUS_TE_CLKS_SHIFT 3
87#define EUR_CR_CLKGATESTATUS_MTE_CLKS_MASK 0x00000010U
88#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SHIFT 4
89#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00000020U
90#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 5
91#define EUR_CR_CLKGATESTATUS_VDM_CLKS_MASK 0x00000040U
92#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SHIFT 6
93#define EUR_CR_CLKGATESTATUS_PDS_CLKS_MASK 0x00000080U
94#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SHIFT 7
95#define EUR_CR_CLKGATESTATUS_PBE_CLKS_MASK 0x00000100U
96#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SHIFT 8
97#define EUR_CR_CLKGATESTATUS_CACHEL2_CLKS_MASK 0x00000200U
98#define EUR_CR_CLKGATESTATUS_CACHEL2_CLKS_SHIFT 9
99#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_MASK 0x00000400U
100#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SHIFT 10
101#define EUR_CR_CLKGATESTATUS_USE0_CLKS_MASK 0x00000800U
102#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SHIFT 11
103#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_MASK 0x00001000U
104#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SHIFT 12
105#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_MASK 0x00002000U
106#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SHIFT 13
107#define EUR_CR_CLKGATESTATUS_MADD0_CLKS_MASK 0x00004000U
108#define EUR_CR_CLKGATESTATUS_MADD0_CLKS_SHIFT 14
109#define EUR_CR_CLKGATESTATUS_USE1_CLKS_MASK 0x00008000U
110#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SHIFT 15
111#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_MASK 0x00010000U
112#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SHIFT 16
113#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_MASK 0x00020000U
114#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SHIFT 17
115#define EUR_CR_CLKGATESTATUS_MADD1_CLKS_MASK 0x00040000U
116#define EUR_CR_CLKGATESTATUS_MADD1_CLKS_SHIFT 18
117#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_MASK 0x00080000U
118#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SHIFT 19
119#define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00100000U
120#define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 20
121#define EUR_CR_CLKGATECTLOVR 0x000C
122#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U
123#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0
124#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_MASK 0x0000000CU
125#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SHIFT 2
126#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000030U
127#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 4
128#define EUR_CR_CLKGATECTLOVR_TE_CLKO_MASK 0x000000C0U
129#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SHIFT 6
130#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_MASK 0x00000300U
131#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SHIFT 8
132#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00000C00U
133#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 10
134#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_MASK 0x00003000U
135#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SHIFT 12
136#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_MASK 0x0000C000U
137#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SHIFT 14
138#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_MASK 0x00030000U
139#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SHIFT 16
140#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x000C0000U
141#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 18
142#define EUR_CR_CORE_ID 0x0020
143#define EUR_CR_CORE_ID_CONFIG_MASK 0x0000FFFFU
144#define EUR_CR_CORE_ID_CONFIG_SHIFT 0
145#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U
146#define EUR_CR_CORE_ID_ID_SHIFT 16
147#define EUR_CR_CORE_REVISION 0x0024
148#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU
149#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0
150#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U
151#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8
152#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U
153#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16
154#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U
155#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24
156#define EUR_CR_DESIGNER_REV_FIELD1 0x0028
157#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU
158#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0
159#define EUR_CR_DESIGNER_REV_FIELD2 0x002C
160#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU
161#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0
162#define EUR_CR_SOFT_RESET 0x0080
163#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U
164#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0
165#define EUR_CR_SOFT_RESET_VDM_RESET_MASK 0x00000002U
166#define EUR_CR_SOFT_RESET_VDM_RESET_SHIFT 1
167#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U
168#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2
169#define EUR_CR_SOFT_RESET_TE_RESET_MASK 0x00000008U
170#define EUR_CR_SOFT_RESET_TE_RESET_SHIFT 3
171#define EUR_CR_SOFT_RESET_MTE_RESET_MASK 0x00000010U
172#define EUR_CR_SOFT_RESET_MTE_RESET_SHIFT 4
173#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U
174#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5
175#define EUR_CR_SOFT_RESET_ISP2_RESET_MASK 0x00000040U
176#define EUR_CR_SOFT_RESET_ISP2_RESET_SHIFT 6
177#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000080U
178#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 7
179#define EUR_CR_SOFT_RESET_PDS_RESET_MASK 0x00000100U
180#define EUR_CR_SOFT_RESET_PDS_RESET_SHIFT 8
181#define EUR_CR_SOFT_RESET_PBE_RESET_MASK 0x00000200U
182#define EUR_CR_SOFT_RESET_PBE_RESET_SHIFT 9
183#define EUR_CR_SOFT_RESET_CACHEL2_RESET_MASK 0x00000400U
184#define EUR_CR_SOFT_RESET_CACHEL2_RESET_SHIFT 10
185#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK 0x00000800U
186#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SHIFT 11
187#define EUR_CR_SOFT_RESET_MADD_RESET_MASK 0x00001000U
188#define EUR_CR_SOFT_RESET_MADD_RESET_SHIFT 12
189#define EUR_CR_SOFT_RESET_ITR_RESET_MASK 0x00002000U
190#define EUR_CR_SOFT_RESET_ITR_RESET_SHIFT 13
191#define EUR_CR_SOFT_RESET_TEX_RESET_MASK 0x00004000U
192#define EUR_CR_SOFT_RESET_TEX_RESET_SHIFT 14
193#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00008000U
194#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 15
195#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK 0x00010000U
196#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SHIFT 16
197#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00020000U
198#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 17
199#define EUR_CR_EVENT_HOST_ENABLE2 0x0110
200#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U
201#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4
202#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U
203#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3
204#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U
205#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2
206#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U
207#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1
208#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U
209#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0
210#define EUR_CR_EVENT_HOST_CLEAR2 0x0114
211#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U
212#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4
213#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U
214#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3
215#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U
216#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2
217#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U
218#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1
219#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U
220#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0
221#define EUR_CR_EVENT_STATUS2 0x0118
222#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U
223#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4
224#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U
225#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3
226#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U
227#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2
228#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U
229#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1
230#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U
231#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0
232#define EUR_CR_EVENT_STATUS 0x012CU
233#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U
234#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31
235#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U
236#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29
237#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U
238#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28
239#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_MASK 0x08000000U
240#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_SHIFT 27
241#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U
242#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_SHIFT 26
243#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
244#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
245#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U
246#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24
247#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U
248#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23
249#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U
250#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22
251#define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U
252#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21
253#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U
254#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20
255#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U
256#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19
257#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U
258#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18
259#define EUR_CR_EVENT_STATUS_ISP_HALT_MASK 0x00020000U
260#define EUR_CR_EVENT_STATUS_ISP_HALT_SHIFT 17
261#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_MASK 0x00010000U
262#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_SHIFT 16
263#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U
264#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15
265#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U
266#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14
267#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U
268#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13
269#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U
270#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12
271#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U
272#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11
273#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U
274#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10
275#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U
276#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9
277#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U
278#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8
279#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U
280#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7
281#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U
282#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6
283#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U
284#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5
285#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U
286#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4
287#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
288#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3
289#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
290#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
291#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
292#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1
293#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U
294#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0
295#define EUR_CR_EVENT_HOST_ENABLE 0x0130
296#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U
297#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31
298#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U
299#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29
300#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U
301#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28
302#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_MASK 0x08000000U
303#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_SHIFT 27
304#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U
305#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_SHIFT 26
306#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
307#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
308#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U
309#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24
310#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U
311#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23
312#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U
313#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22
314#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U
315#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21
316#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U
317#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20
318#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U
319#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19
320#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U
321#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18
322#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_MASK 0x00020000U
323#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_SHIFT 17
324#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_MASK 0x00010000U
325#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_SHIFT 16
326#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U
327#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15
328#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U
329#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14
330#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U
331#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13
332#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U
333#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12
334#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U
335#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11
336#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U
337#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10
338#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U
339#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9
340#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U
341#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8
342#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U
343#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7
344#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U
345#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6
346#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U
347#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5
348#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U
349#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4
350#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
351#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3
352#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
353#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
354#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
355#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1
356#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U
357#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0
358#define EUR_CR_EVENT_HOST_CLEAR 0x0134
359#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U
360#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31
361#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U
362#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29
363#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U
364#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28
365#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_MASK 0x08000000U
366#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_SHIFT 27
367#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U
368#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_SHIFT 26
369#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
370#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
371#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U
372#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24
373#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U
374#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23
375#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U
376#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22
377#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U
378#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21
379#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U
380#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20
381#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U
382#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19
383#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U
384#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18
385#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_MASK 0x00020000U
386#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_SHIFT 17
387#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_MASK 0x00010000U
388#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_SHIFT 16
389#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U
390#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15
391#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U
392#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14
393#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U
394#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13
395#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U
396#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12
397#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U
398#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11
399#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U
400#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10
401#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U
402#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9
403#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U
404#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8
405#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U
406#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7
407#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U
408#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6
409#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U
410#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5
411#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U
412#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4
413#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
414#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3
415#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
416#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
417#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
418#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1
419#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U
420#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0
421#define EUR_CR_TIMER 0x0144
422#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU
423#define EUR_CR_TIMER_VALUE_SHIFT 0
424#define EUR_CR_EVENT_KICK1 0x0AB0
425#define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU
426#define EUR_CR_EVENT_KICK1_NOW_SHIFT 0
427#define EUR_CR_PDS_EXEC_BASE 0x0AB8
428#define EUR_CR_PDS_EXEC_BASE_ADDR_MASK 0x0FF00000U
429#define EUR_CR_PDS_EXEC_BASE_ADDR_SHIFT 20
430#define EUR_CR_EVENT_KICK2 0x0AC0
431#define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U
432#define EUR_CR_EVENT_KICK2_NOW_SHIFT 0
433#define EUR_CR_EVENT_KICKER 0x0AC4
434#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0x0FFFFFF0U
435#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4
436#define EUR_CR_EVENT_KICK 0x0AC8
437#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U
438#define EUR_CR_EVENT_KICK_NOW_SHIFT 0
439#define EUR_CR_EVENT_TIMER 0x0ACC
440#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U
441#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24
442#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU
443#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0
444#define EUR_CR_PDS_INV0 0x0AD0
445#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U
446#define EUR_CR_PDS_INV0_DSC_SHIFT 0
447#define EUR_CR_PDS_INV1 0x0AD4
448#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U
449#define EUR_CR_PDS_INV1_DSC_SHIFT 0
450#define EUR_CR_EVENT_KICK3 0x0AD8
451#define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U
452#define EUR_CR_EVENT_KICK3_NOW_SHIFT 0
453#define EUR_CR_PDS_INV3 0x0ADC
454#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U
455#define EUR_CR_PDS_INV3_DSC_SHIFT 0
456#define EUR_CR_PDS_INV_CSC 0x0AE0
457#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U
458#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0
459#define EUR_CR_PDS_PC_BASE 0x0B2C
460#define EUR_CR_PDS_PC_BASE_ADDRESS_MASK 0x00FFFFFFU
461#define EUR_CR_PDS_PC_BASE_ADDRESS_SHIFT 0
462#define EUR_CR_BIF_CTRL 0x0C00
463#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U
464#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0
465#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U
466#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1
467#define EUR_CR_BIF_CTRL_FLUSH_MASK 0x00000004U
468#define EUR_CR_BIF_CTRL_FLUSH_SHIFT 2
469#define EUR_CR_BIF_CTRL_INVALDC_MASK 0x00000008U
470#define EUR_CR_BIF_CTRL_INVALDC_SHIFT 3
471#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U
472#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4
473#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_MASK 0x00000100U
474#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_SHIFT 8
475#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U
476#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9
477#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_MASK 0x00000400U
478#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_SHIFT 10
479#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U
480#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12
481#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U
482#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13
483#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U
484#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14
485#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U
486#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15
487#define EUR_CR_BIF_INT_STAT 0x0C04
488#define EUR_CR_BIF_INT_STAT_FAULT_MASK 0x00003FFFU
489#define EUR_CR_BIF_INT_STAT_FAULT_SHIFT 0
490#define EUR_CR_BIF_INT_STAT_PF_N_RW_MASK 0x00004000U
491#define EUR_CR_BIF_INT_STAT_PF_N_RW_SHIFT 14
492#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00008000U
493#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 15
494#define EUR_CR_BIF_FAULT 0x0C08
495#define EUR_CR_BIF_FAULT_SB_MASK 0x000001F0U
496#define EUR_CR_BIF_FAULT_SB_SHIFT 4
497#define EUR_CR_BIF_FAULT_ADDR_MASK 0x0FFFF000U
498#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12
499#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84
500#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U
501#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12
502#define EUR_CR_BIF_TA_REQ_BASE 0x0C90
503#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0x0FF00000U
504#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20
505#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8
506#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU
507#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0
508#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC
509#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0x0FF00000U
510#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20
511#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0
512#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0x0FF00000U
513#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20
514#define EUR_CR_2D_BLIT_STATUS 0x0E04
515#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU
516#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0
517#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U
518#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24
519#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10
520#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U
521#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0
522#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU
523#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1
524#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U
525#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4
526#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U
527#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12
528#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14
529#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU
530#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0
531#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U
532#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12
533#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U
534#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24
535#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X)))
536#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x00FFFFFFU
537#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0
538#define EUR_CR_USE_CODE_BASE_DM_MASK 0x03000000U
539#define EUR_CR_USE_CODE_BASE_DM_SHIFT 24
540#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16
541#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16
542
543#endif
544
diff --git a/drivers/gpu/pvr/sgx535defs.h b/drivers/gpu/pvr/sgx535defs.h
new file mode 100644
index 00000000000..04f43be12b1
--- /dev/null
+++ b/drivers/gpu/pvr/sgx535defs.h
@@ -0,0 +1,650 @@
1/**********************************************************************
2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 *
25 ******************************************************************************/
26
27#ifndef _SGX535DEFS_KM_H_
28#define _SGX535DEFS_KM_H_
29
30#define EUR_CR_CLKGATECTL 0x0000
31#define EUR_CR_CLKGATECTL_2D_CLKG_MASK 0x00000003U
32#define EUR_CR_CLKGATECTL_2D_CLKG_SHIFT 0
33#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000030U
34#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 4
35#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000300U
36#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 8
37#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x00003000U
38#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 12
39#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00030000U
40#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 16
41#define EUR_CR_CLKGATECTL_USE_CLKG_MASK 0x00300000U
42#define EUR_CR_CLKGATECTL_USE_CLKG_SHIFT 20
43#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U
44#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24
45#define EUR_CR_CLKGATESTATUS 0x0004
46#define EUR_CR_CLKGATESTATUS_2D_CLKS_MASK 0x00000001
47#define EUR_CR_CLKGATESTATUS_2D_CLKS_SHIFT 0
48#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000010U
49#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 4
50#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000100U
51#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 8
52#define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00001000U
53#define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 12
54#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00010000U
55#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 16
56#define EUR_CR_CLKGATESTATUS_USE_CLKS_MASK 0x00100000U
57#define EUR_CR_CLKGATESTATUS_USE_CLKS_SHIFT 20
58#define EUR_CR_CLKGATECTLOVR 0x0008
59#define EUR_CR_CLKGATECTLOVR_2D_CLKO_MASK 0x00000003U
60#define EUR_CR_CLKGATECTLOVR_2D_CLKO_SHIFT 0
61#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000030U
62#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 4
63#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000300U
64#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 8
65#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x00003000U
66#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 12
67#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00030000U
68#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 16
69#define EUR_CR_CLKGATECTLOVR_USE_CLKO_MASK 0x00300000U
70#define EUR_CR_CLKGATECTLOVR_USE_CLKO_SHIFT 20
71#define EUR_CR_CORE_ID 0x0010
72#define EUR_CR_CORE_ID_CONFIG_MASK 0x0000FFFFU
73#define EUR_CR_CORE_ID_CONFIG_SHIFT 0
74#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U
75#define EUR_CR_CORE_ID_ID_SHIFT 16
76#define EUR_CR_CORE_REVISION 0x0014
77#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU
78#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0
79#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U
80#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8
81#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U
82#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16
83#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U
84#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24
85#define EUR_CR_DESIGNER_REV_FIELD1 0x0018
86#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU
87#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0
88#define EUR_CR_DESIGNER_REV_FIELD2 0x001C
89#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU
90#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0
91#define EUR_CR_SOFT_RESET 0x0080
92#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U
93#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0
94#define EUR_CR_SOFT_RESET_TWOD_RESET_MASK 0x00000002U
95#define EUR_CR_SOFT_RESET_TWOD_RESET_SHIFT 1
96#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U
97#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2
98#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00000008U
99#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 3
100#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00000010U
101#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 4
102#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U
103#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5
104#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000040U
105#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 6
106#define EUR_CR_EVENT_HOST_ENABLE2 0x0110
107#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000080U
108#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 7
109#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000040U
110#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 6
111#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000020U
112#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 5
113#define EUR_CR_EVENT_HOST_ENABLE2_BIF_REQUESTER_FAULT_MASK 0x00000010U
114#define EUR_CR_EVENT_HOST_ENABLE2_BIF_REQUESTER_FAULT_SHIFT 4
115#define EUR_CR_EVENT_HOST_ENABLE2_DPM_DHOST_FREE_LOAD_MASK 0x00000008U
116#define EUR_CR_EVENT_HOST_ENABLE2_DPM_DHOST_FREE_LOAD_SHIFT 3
117#define EUR_CR_EVENT_HOST_ENABLE2_DPM_HOST_FREE_LOAD_MASK 0x00000004U
118#define EUR_CR_EVENT_HOST_ENABLE2_DPM_HOST_FREE_LOAD_SHIFT 2
119#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U
120#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1
121#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U
122#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0
123#define EUR_CR_EVENT_HOST_CLEAR2 0x0114
124#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000080U
125#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 7
126#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000040U
127#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 6
128#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000020U
129#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 5
130#define EUR_CR_EVENT_HOST_CLEAR2_BIF_REQUESTER_FAULT_MASK 0x00000010U
131#define EUR_CR_EVENT_HOST_CLEAR2_BIF_REQUESTER_FAULT_SHIFT 4
132#define EUR_CR_EVENT_HOST_CLEAR2_DPM_DHOST_FREE_LOAD_MASK 0x00000008U
133#define EUR_CR_EVENT_HOST_CLEAR2_DPM_DHOST_FREE_LOAD_SHIFT 3
134#define EUR_CR_EVENT_HOST_CLEAR2_DPM_HOST_FREE_LOAD_MASK 0x00000004U
135#define EUR_CR_EVENT_HOST_CLEAR2_DPM_HOST_FREE_LOAD_SHIFT 2
136#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U
137#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1
138#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U
139#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0
140#define EUR_CR_EVENT_STATUS2 0x0118U
141#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000080U
142#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 7
143#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000040U
144#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 6
145#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000020U
146#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 5
147#define EUR_CR_EVENT_STATUS2_BIF_REQUESTER_FAULT_MASK 0x00000010U
148#define EUR_CR_EVENT_STATUS2_BIF_REQUESTER_FAULT_SHIFT 4
149#define EUR_CR_EVENT_STATUS2_DPM_DHOST_FREE_LOAD_MASK 0x00000008U
150#define EUR_CR_EVENT_STATUS2_DPM_DHOST_FREE_LOAD_SHIFT 3
151#define EUR_CR_EVENT_STATUS2_DPM_HOST_FREE_LOAD_MASK 0x00000004U
152#define EUR_CR_EVENT_STATUS2_DPM_HOST_FREE_LOAD_SHIFT 2
153#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U
154#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1
155#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U
156#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0
157#define EUR_CR_EVENT_STATUS 0x012CU
158#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U
159#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31
160#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U
161#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29
162#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U
163#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28
164#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_MASK 0x08000000U
165#define EUR_CR_EVENT_STATUS_TWOD_COMPLETE_SHIFT 27
166#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U
167#define EUR_CR_EVENT_STATUS_MADD_CACHE_INVALCOMPLETE_SHIFT 26
168#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
169#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
170#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U
171#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24
172#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U
173#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23
174#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U
175#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22
176#define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U
177#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21
178#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U
179#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20
180#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U
181#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19
182#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U
183#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18
184#define EUR_CR_EVENT_STATUS_ISP_HALT_MASK 0x00020000U
185#define EUR_CR_EVENT_STATUS_ISP_HALT_SHIFT 17
186#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_MASK 0x00010000U
187#define EUR_CR_EVENT_STATUS_ISP_VISIBILITY_FAIL_SHIFT 16
188#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U
189#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15
190#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U
191#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14
192#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U
193#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13
194#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U
195#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12
196#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U
197#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11
198#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U
199#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10
200#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U
201#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9
202#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U
203#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8
204#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U
205#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7
206#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U
207#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6
208#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U
209#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5
210#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U
211#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4
212#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
213#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3
214#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
215#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
216#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
217#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1
218#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U
219#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0
220#define EUR_CR_EVENT_HOST_ENABLE 0x0130
221#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U
222#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31
223#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U
224#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29
225#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U
226#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28
227#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_MASK 0x08000000U
228#define EUR_CR_EVENT_HOST_ENABLE_TWOD_COMPLETE_SHIFT 27
229#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U
230#define EUR_CR_EVENT_HOST_ENABLE_MADD_CACHE_INVALCOMPLETE_SHIFT 26
231#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
232#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
233#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U
234#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24
235#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U
236#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23
237#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U
238#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22
239#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U
240#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21
241#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U
242#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20
243#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U
244#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19
245#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U
246#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18
247#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_MASK 0x00020000U
248#define EUR_CR_EVENT_HOST_ENABLE_ISP_HALT_SHIFT 17
249#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_MASK 0x00010000U
250#define EUR_CR_EVENT_HOST_ENABLE_ISP_VISIBILITY_FAIL_SHIFT 16
251#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U
252#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15
253#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U
254#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14
255#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U
256#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13
257#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U
258#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12
259#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U
260#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11
261#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U
262#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10
263#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U
264#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9
265#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U
266#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8
267#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U
268#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7
269#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U
270#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6
271#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U
272#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5
273#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U
274#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4
275#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
276#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3
277#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
278#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
279#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
280#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1
281#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U
282#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0
283#define EUR_CR_EVENT_HOST_CLEAR 0x0134
284#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U
285#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31
286#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U
287#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29
288#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U
289#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28
290#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_MASK 0x08000000U
291#define EUR_CR_EVENT_HOST_CLEAR_TWOD_COMPLETE_SHIFT 27
292#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_MASK 0x04000000U
293#define EUR_CR_EVENT_HOST_CLEAR_MADD_CACHE_INVALCOMPLETE_SHIFT 26
294#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
295#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
296#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U
297#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24
298#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U
299#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23
300#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U
301#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22
302#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U
303#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21
304#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U
305#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20
306#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U
307#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19
308#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U
309#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18
310#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_MASK 0x00020000U
311#define EUR_CR_EVENT_HOST_CLEAR_ISP_HALT_SHIFT 17
312#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_MASK 0x00010000U
313#define EUR_CR_EVENT_HOST_CLEAR_ISP_VISIBILITY_FAIL_SHIFT 16
314#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U
315#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15
316#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U
317#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14
318#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U
319#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13
320#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U
321#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12
322#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U
323#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11
324#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U
325#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10
326#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U
327#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9
328#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U
329#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8
330#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U
331#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7
332#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U
333#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6
334#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U
335#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5
336#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U
337#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4
338#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
339#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3
340#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
341#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
342#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
343#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1
344#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U
345#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0
346#define EUR_CR_PDS_EXEC_BASE 0x0AB8
347#define EUR_CR_PDS_EXEC_BASE_ADDR_MASK 0xFFF00000U
348#define EUR_CR_PDS_EXEC_BASE_ADDR_SHIFT 20
349#define EUR_CR_EVENT_KICKER 0x0AC4
350#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0xFFFFFFF0U
351#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4
352#define EUR_CR_EVENT_KICK 0x0AC8
353#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U
354#define EUR_CR_EVENT_KICK_NOW_SHIFT 0
355#define EUR_CR_EVENT_TIMER 0x0ACC
356#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U
357#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24
358#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU
359#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0
360#define EUR_CR_PDS_INV0 0x0AD0
361#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U
362#define EUR_CR_PDS_INV0_DSC_SHIFT 0
363#define EUR_CR_PDS_INV1 0x0AD4
364#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U
365#define EUR_CR_PDS_INV1_DSC_SHIFT 0
366#define EUR_CR_PDS_INV2 0x0AD8
367#define EUR_CR_PDS_INV2_DSC_MASK 0x00000001U
368#define EUR_CR_PDS_INV2_DSC_SHIFT 0
369#define EUR_CR_PDS_INV3 0x0ADC
370#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U
371#define EUR_CR_PDS_INV3_DSC_SHIFT 0
372#define EUR_CR_PDS_INV_CSC 0x0AE0
373#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U
374#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0
375#define EUR_CR_PDS_PC_BASE 0x0B2C
376#define EUR_CR_PDS_PC_BASE_ADDRESS_MASK 0x3FFFFFFFU
377#define EUR_CR_PDS_PC_BASE_ADDRESS_SHIFT 0
378#define EUR_CR_BIF_CTRL 0x0C00
379#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U
380#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0
381#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U
382#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1
383#define EUR_CR_BIF_CTRL_FLUSH_MASK 0x00000004U
384#define EUR_CR_BIF_CTRL_FLUSH_SHIFT 2
385#define EUR_CR_BIF_CTRL_INVALDC_MASK 0x00000008U
386#define EUR_CR_BIF_CTRL_INVALDC_SHIFT 3
387#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U
388#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4
389#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_MASK 0x00000100U
390#define EUR_CR_BIF_CTRL_MMU_BYPASS_CACHE_SHIFT 8
391#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U
392#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9
393#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_MASK 0x00000400U
394#define EUR_CR_BIF_CTRL_MMU_BYPASS_TE_SHIFT 10
395#define EUR_CR_BIF_CTRL_MMU_BYPASS_TWOD_MASK 0x00000800U
396#define EUR_CR_BIF_CTRL_MMU_BYPASS_TWOD_SHIFT 11
397#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U
398#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12
399#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U
400#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13
401#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U
402#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14
403#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U
404#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15
405#define EUR_CR_BIF_CTRL_MMU_BYPASS_HOST_MASK 0x00010000U
406#define EUR_CR_BIF_CTRL_MMU_BYPASS_HOST_SHIFT 16
407#define EUR_CR_BIF_INT_STAT 0x0C04
408#define EUR_CR_BIF_INT_STAT_FAULT_MASK 0x00003FFFU
409#define EUR_CR_BIF_INT_STAT_FAULT_SHIFT 0
410#define EUR_CR_BIF_INT_STAT_PF_N_RW_MASK 0x00004000U
411#define EUR_CR_BIF_INT_STAT_PF_N_RW_SHIFT 14
412#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00008000U
413#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 15
414#define EUR_CR_BIF_FAULT 0x0C08
415#define EUR_CR_BIF_FAULT_ADDR_MASK 0xFFFFF000U
416#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12
417#define EUR_CR_BIF_TILE0 0x0C0C
418#define EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK 0x00000FFFU
419#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT 0
420#define EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK 0x00FFF000U
421#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT 12
422#define EUR_CR_BIF_TILE0_CFG_MASK 0x0F000000U
423#define EUR_CR_BIF_TILE0_CFG_SHIFT 24
424#define EUR_CR_BIF_TILE1 0x0C10
425#define EUR_CR_BIF_TILE1_MIN_ADDRESS_MASK 0x00000FFFU
426#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SHIFT 0
427#define EUR_CR_BIF_TILE1_MAX_ADDRESS_MASK 0x00FFF000U
428#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SHIFT 12
429#define EUR_CR_BIF_TILE1_CFG_MASK 0x0F000000U
430#define EUR_CR_BIF_TILE1_CFG_SHIFT 24
431#define EUR_CR_BIF_TILE2 0x0C14
432#define EUR_CR_BIF_TILE2_MIN_ADDRESS_MASK 0x00000FFFU
433#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SHIFT 0
434#define EUR_CR_BIF_TILE2_MAX_ADDRESS_MASK 0x00FFF000U
435#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SHIFT 12
436#define EUR_CR_BIF_TILE2_CFG_MASK 0x0F000000U
437#define EUR_CR_BIF_TILE2_CFG_SHIFT 24
438#define EUR_CR_BIF_TILE3 0x0C18
439#define EUR_CR_BIF_TILE3_MIN_ADDRESS_MASK 0x00000FFFU
440#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SHIFT 0
441#define EUR_CR_BIF_TILE3_MAX_ADDRESS_MASK 0x00FFF000U
442#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SHIFT 12
443#define EUR_CR_BIF_TILE3_CFG_MASK 0x0F000000U
444#define EUR_CR_BIF_TILE3_CFG_SHIFT 24
445#define EUR_CR_BIF_TILE4 0x0C1C
446#define EUR_CR_BIF_TILE4_MIN_ADDRESS_MASK 0x00000FFFU
447#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SHIFT 0
448#define EUR_CR_BIF_TILE4_MAX_ADDRESS_MASK 0x00FFF000U
449#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SHIFT 12
450#define EUR_CR_BIF_TILE4_CFG_MASK 0x0F000000U
451#define EUR_CR_BIF_TILE4_CFG_SHIFT 24
452#define EUR_CR_BIF_TILE5 0x0C20
453#define EUR_CR_BIF_TILE5_MIN_ADDRESS_MASK 0x00000FFFU
454#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SHIFT 0
455#define EUR_CR_BIF_TILE5_MAX_ADDRESS_MASK 0x00FFF000U
456#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SHIFT 12
457#define EUR_CR_BIF_TILE5_CFG_MASK 0x0F000000U
458#define EUR_CR_BIF_TILE5_CFG_SHIFT 24
459#define EUR_CR_BIF_TILE6 0x0C24
460#define EUR_CR_BIF_TILE6_MIN_ADDRESS_MASK 0x00000FFFU
461#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SHIFT 0
462#define EUR_CR_BIF_TILE6_MAX_ADDRESS_MASK 0x00FFF000U
463#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SHIFT 12
464#define EUR_CR_BIF_TILE6_CFG_MASK 0x0F000000U
465#define EUR_CR_BIF_TILE6_CFG_SHIFT 24
466#define EUR_CR_BIF_TILE7 0x0C28
467#define EUR_CR_BIF_TILE7_MIN_ADDRESS_MASK 0x00000FFFU
468#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SHIFT 0
469#define EUR_CR_BIF_TILE7_MAX_ADDRESS_MASK 0x00FFF000U
470#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SHIFT 12
471#define EUR_CR_BIF_TILE7_CFG_MASK 0x0F000000U
472#define EUR_CR_BIF_TILE7_CFG_SHIFT 24
473#define EUR_CR_BIF_TILE8 0x0C2C
474#define EUR_CR_BIF_TILE8_MIN_ADDRESS_MASK 0x00000FFFU
475#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SHIFT 0
476#define EUR_CR_BIF_TILE8_MAX_ADDRESS_MASK 0x00FFF000U
477#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SHIFT 12
478#define EUR_CR_BIF_TILE8_CFG_MASK 0x0F000000U
479#define EUR_CR_BIF_TILE8_CFG_SHIFT 24
480#define EUR_CR_BIF_TILE9 0x0C30
481#define EUR_CR_BIF_TILE9_MIN_ADDRESS_MASK 0x00000FFFU
482#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SHIFT 0
483#define EUR_CR_BIF_TILE9_MAX_ADDRESS_MASK 0x00FFF000U
484#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SHIFT 12
485#define EUR_CR_BIF_TILE9_CFG_MASK 0x0F000000U
486#define EUR_CR_BIF_TILE9_CFG_SHIFT 24
487#define EUR_CR_BIF_DIR_LIST_BASE1 0x0C38
488#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_MASK 0xFFFFF000U
489#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SHIFT 12
490#define EUR_CR_BIF_DIR_LIST_BASE2 0x0C3C
491#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_MASK 0xFFFFF000U
492#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SHIFT 12
493#define EUR_CR_BIF_DIR_LIST_BASE3 0x0C40
494#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_MASK 0xFFFFF000U
495#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SHIFT 12
496#define EUR_CR_BIF_DIR_LIST_BASE4 0x0C44
497#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_MASK 0xFFFFF000U
498#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SHIFT 12
499#define EUR_CR_BIF_DIR_LIST_BASE5 0x0C48
500#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_MASK 0xFFFFF000U
501#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SHIFT 12
502#define EUR_CR_BIF_DIR_LIST_BASE6 0x0C4C
503#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_MASK 0xFFFFF000U
504#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SHIFT 12
505#define EUR_CR_BIF_DIR_LIST_BASE7 0x0C50
506#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_MASK 0xFFFFF000U
507#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SHIFT 12
508#define EUR_CR_BIF_DIR_LIST_BASE8 0x0C54
509#define EUR_CR_BIF_DIR_LIST_BASE8_ADDR_MASK 0xFFFFF000U
510#define EUR_CR_BIF_DIR_LIST_BASE8_ADDR_SHIFT 12
511#define EUR_CR_BIF_DIR_LIST_BASE9 0x0C58
512#define EUR_CR_BIF_DIR_LIST_BASE9_ADDR_MASK 0xFFFFF000U
513#define EUR_CR_BIF_DIR_LIST_BASE9_ADDR_SHIFT 12
514#define EUR_CR_BIF_DIR_LIST_BASE10 0x0C5C
515#define EUR_CR_BIF_DIR_LIST_BASE10_ADDR_MASK 0xFFFFF000U
516#define EUR_CR_BIF_DIR_LIST_BASE10_ADDR_SHIFT 12
517#define EUR_CR_BIF_DIR_LIST_BASE11 0x0C60
518#define EUR_CR_BIF_DIR_LIST_BASE11_ADDR_MASK 0xFFFFF000U
519#define EUR_CR_BIF_DIR_LIST_BASE11_ADDR_SHIFT 12
520#define EUR_CR_BIF_DIR_LIST_BASE12 0x0C64
521#define EUR_CR_BIF_DIR_LIST_BASE12_ADDR_MASK 0xFFFFF000U
522#define EUR_CR_BIF_DIR_LIST_BASE12_ADDR_SHIFT 12
523#define EUR_CR_BIF_DIR_LIST_BASE13 0x0C68
524#define EUR_CR_BIF_DIR_LIST_BASE13_ADDR_MASK 0xFFFFF000U
525#define EUR_CR_BIF_DIR_LIST_BASE13_ADDR_SHIFT 12
526#define EUR_CR_BIF_DIR_LIST_BASE14 0x0C6C
527#define EUR_CR_BIF_DIR_LIST_BASE14_ADDR_MASK 0xFFFFF000U
528#define EUR_CR_BIF_DIR_LIST_BASE14_ADDR_SHIFT 12
529#define EUR_CR_BIF_DIR_LIST_BASE15 0x0C70
530#define EUR_CR_BIF_DIR_LIST_BASE15_ADDR_MASK 0xFFFFF000U
531#define EUR_CR_BIF_DIR_LIST_BASE15_ADDR_SHIFT 12
532#define EUR_CR_BIF_BANK_SET 0x0C74
533#define EUR_CR_BIF_BANK_SET_SELECT_MASK 0x000003FFU
534#define EUR_CR_BIF_BANK_SET_SELECT_SHIFT 0
535#define EUR_CR_BIF_BANK0 0x0C78
536#define EUR_CR_BIF_BANK0_INDEX_EDM_MASK 0x0000000FU
537#define EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT 0
538#define EUR_CR_BIF_BANK0_INDEX_TA_MASK 0x000000F0U
539#define EUR_CR_BIF_BANK0_INDEX_TA_SHIFT 4
540#define EUR_CR_BIF_BANK0_INDEX_HOST_MASK 0x00000F00U
541#define EUR_CR_BIF_BANK0_INDEX_HOST_SHIFT 8
542#define EUR_CR_BIF_BANK0_INDEX_3D_MASK 0x0000F000U
543#define EUR_CR_BIF_BANK0_INDEX_3D_SHIFT 12
544#define EUR_CR_BIF_BANK0_INDEX_2D_MASK 0x000F0000U
545#define EUR_CR_BIF_BANK0_INDEX_2D_SHIFT 16
546#define EUR_CR_BIF_BANK1 0x0C7C
547#define EUR_CR_BIF_BANK1_INDEX_EDM_MASK 0x0000000FU
548#define EUR_CR_BIF_BANK1_INDEX_EDM_SHIFT 0
549#define EUR_CR_BIF_BANK1_INDEX_TA_MASK 0x000000F0U
550#define EUR_CR_BIF_BANK1_INDEX_TA_SHIFT 4
551#define EUR_CR_BIF_BANK1_INDEX_HOST_MASK 0x00000F00U
552#define EUR_CR_BIF_BANK1_INDEX_HOST_SHIFT 8
553#define EUR_CR_BIF_BANK1_INDEX_3D_MASK 0x0000F000U
554#define EUR_CR_BIF_BANK1_INDEX_3D_SHIFT 12
555#define EUR_CR_BIF_BANK1_INDEX_2D_MASK 0x000F0000U
556#define EUR_CR_BIF_BANK1_INDEX_2D_SHIFT 16
557#define EUR_CR_BIF_ADT_TTE 0x0C80
558#define EUR_CR_BIF_ADT_TTE_VALUE_MASK 0x000000FFU
559#define EUR_CR_BIF_ADT_TTE_VALUE_SHIFT 0
560#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84
561#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U
562#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12
563#define EUR_CR_BIF_TWOD_REQ_BASE 0x0C88
564#define EUR_CR_BIF_TWOD_REQ_BASE_ADDR_MASK 0xFFF00000U
565#define EUR_CR_BIF_TWOD_REQ_BASE_ADDR_SHIFT 20
566#define EUR_CR_BIF_TA_REQ_BASE 0x0C90
567#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0xFFF00000U
568#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20
569#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1 0x0C94
570#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_MMU_MASK 0x00000007U
571#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_MMU_SHIFT 0
572#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_CACHE_MASK 0x00000038U
573#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_CACHE_SHIFT 3
574#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_VDM_MASK 0x000001C0U
575#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_VDM_SHIFT 6
576#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TE_MASK 0x00000E00U
577#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TE_SHIFT 9
578#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TWOD_MASK 0x00007000U
579#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_TWOD_SHIFT 12
580#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_PBE_MASK 0x00038000U
581#define EUR_CR_BIF_MEM_ARB_FLOWRATES_1_PBE_SHIFT 15
582#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2 0x0C98
583#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_HOST_MASK 0x00000007U
584#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_HOST_SHIFT 0
585#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_USE_MASK 0x00000038U
586#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_USE_SHIFT 3
587#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_ISP_MASK 0x000001C0U
588#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_ISP_SHIFT 6
589#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_TSPP_MASK 0x00000E00U
590#define EUR_CR_BIF_MEM_ARB_FLOWRATES_2_TSPP_SHIFT 9
591#define EUR_CR_BIF_MEM_ARB_CONFIG 0x0CA0
592#define EUR_CR_BIF_MEM_ARB_CONFIG_PAGE_SIZE_MASK 0x0000000FU
593#define EUR_CR_BIF_MEM_ARB_CONFIG_PAGE_SIZE_SHIFT 0
594#define EUR_CR_BIF_MEM_ARB_CONFIG_BEST_CNT_MASK 0x00000FF0U
595#define EUR_CR_BIF_MEM_ARB_CONFIG_BEST_CNT_SHIFT 4
596#define EUR_CR_BIF_MEM_ARB_CONFIG_TTE_THRESH_MASK 0x00FFF000U
597#define EUR_CR_BIF_MEM_ARB_CONFIG_TTE_THRESH_SHIFT 12
598#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8
599#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU
600#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0
601#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC
602#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0xFFF00000U
603#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20
604#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0
605#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0xFFF00000U
606#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20
607#define EUR_CR_BIF_BANK_STATUS 0x0CB4
608#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_MASK 0x00000001U
609#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SHIFT 0
610#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U
611#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1
612#define EUR_CR_2D_BLIT_STATUS 0x0E04
613#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU
614#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0
615#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U
616#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24
617#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10
618#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U
619#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0
620#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU
621#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1
622#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U
623#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4
624#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U
625#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12
626#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14
627#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU
628#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0
629#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U
630#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12
631#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U
632#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24
633#define EUR_CR_2D_SOCIF 0x0E18
634#define EUR_CR_2D_SOCIF_FREESPACE_MASK 0x000000FFU
635#define EUR_CR_2D_SOCIF_FREESPACE_SHIFT 0
636#define EUR_CR_2D_ALPHA 0x0E1C
637#define EUR_CR_2D_ALPHA_COMPONENT_ONE_MASK 0x0000FF00U
638#define EUR_CR_2D_ALPHA_COMPONENT_ONE_SHIFT 8
639#define EUR_CR_2D_ALPHA_COMPONENT_ZERO_MASK 0x000000FFU
640#define EUR_CR_2D_ALPHA_COMPONENT_ZERO_SHIFT 0
641#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X)))
642#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x01FFFFFFU
643#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0
644#define EUR_CR_USE_CODE_BASE_DM_MASK 0x06000000U
645#define EUR_CR_USE_CODE_BASE_DM_SHIFT 25
646#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16
647#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16
648
649#endif
650
diff --git a/drivers/gpu/pvr/sgx543_v1.164defs.h b/drivers/gpu/pvr/sgx543_v1.164defs.h
new file mode 100644
index 00000000000..e25cc5cc42c
--- /dev/null
+++ b/drivers/gpu/pvr/sgx543_v1.164defs.h
@@ -0,0 +1,1284 @@
1/**********************************************************************
2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 *
25 ******************************************************************************/
26
27#ifndef _SGX543DEFS_KM_H_
28#define _SGX543DEFS_KM_H_
29
30#define EUR_CR_CLKGATECTL 0x0000
31#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U
32#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0
33#define EUR_CR_CLKGATECTL_ISP_CLKG_SIGNED 0
34#define EUR_CR_CLKGATECTL_ISP2_CLKG_MASK 0x0000000CU
35#define EUR_CR_CLKGATECTL_ISP2_CLKG_SHIFT 2
36#define EUR_CR_CLKGATECTL_ISP2_CLKG_SIGNED 0
37#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000030U
38#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 4
39#define EUR_CR_CLKGATECTL_TSP_CLKG_SIGNED 0
40#define EUR_CR_CLKGATECTL_TE_CLKG_MASK 0x000000C0U
41#define EUR_CR_CLKGATECTL_TE_CLKG_SHIFT 6
42#define EUR_CR_CLKGATECTL_TE_CLKG_SIGNED 0
43#define EUR_CR_CLKGATECTL_MTE_CLKG_MASK 0x00000300U
44#define EUR_CR_CLKGATECTL_MTE_CLKG_SHIFT 8
45#define EUR_CR_CLKGATECTL_MTE_CLKG_SIGNED 0
46#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00000C00U
47#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 10
48#define EUR_CR_CLKGATECTL_DPM_CLKG_SIGNED 0
49#define EUR_CR_CLKGATECTL_VDM_CLKG_MASK 0x00003000U
50#define EUR_CR_CLKGATECTL_VDM_CLKG_SHIFT 12
51#define EUR_CR_CLKGATECTL_VDM_CLKG_SIGNED 0
52#define EUR_CR_CLKGATECTL_PDS_CLKG_MASK 0x0000C000U
53#define EUR_CR_CLKGATECTL_PDS_CLKG_SHIFT 14
54#define EUR_CR_CLKGATECTL_PDS_CLKG_SIGNED 0
55#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_MASK 0x00030000U
56#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SHIFT 16
57#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SIGNED 0
58#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x000C0000U
59#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 18
60#define EUR_CR_CLKGATECTL_TA_CLKG_SIGNED 0
61#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_MASK 0x00300000U
62#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SHIFT 20
63#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SIGNED 0
64#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U
65#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24
66#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SIGNED 0
67#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_MASK 0x10000000U
68#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SHIFT 28
69#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SIGNED 0
70#define EUR_CR_CLKGATECTL2 0x0004
71#define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U
72#define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0
73#define EUR_CR_CLKGATECTL2_PBE_CLKG_SIGNED 0
74#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_MASK 0x0000000CU
75#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SHIFT 2
76#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SIGNED 0
77#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_MASK 0x00000030U
78#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SHIFT 4
79#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SIGNED 0
80#define EUR_CR_CLKGATECTL2_USE0_CLKG_MASK 0x000000C0U
81#define EUR_CR_CLKGATECTL2_USE0_CLKG_SHIFT 6
82#define EUR_CR_CLKGATECTL2_USE0_CLKG_SIGNED 0
83#define EUR_CR_CLKGATECTL2_ITR0_CLKG_MASK 0x00000300U
84#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SHIFT 8
85#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SIGNED 0
86#define EUR_CR_CLKGATECTL2_TEX0_CLKG_MASK 0x00000C00U
87#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SHIFT 10
88#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SIGNED 0
89#define EUR_CR_CLKGATECTL2_USE1_CLKG_MASK 0x0000C000U
90#define EUR_CR_CLKGATECTL2_USE1_CLKG_SHIFT 14
91#define EUR_CR_CLKGATECTL2_USE1_CLKG_SIGNED 0
92#define EUR_CR_CLKGATECTL2_ITR1_CLKG_MASK 0x00030000U
93#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SHIFT 16
94#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SIGNED 0
95#define EUR_CR_CLKGATECTL2_TEX1_CLKG_MASK 0x000C0000U
96#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SHIFT 18
97#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SIGNED 0
98#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_MASK 0x00C00000U
99#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SHIFT 22
100#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SIGNED 0
101#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_MASK 0x03000000U
102#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SHIFT 24
103#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SIGNED 0
104#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_MASK 0x0C000000U
105#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SHIFT 26
106#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SIGNED 0
107#define EUR_CR_CLKGATESTATUS 0x0008
108#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U
109#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0
110#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SIGNED 0
111#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_MASK 0x00000002U
112#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SHIFT 1
113#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SIGNED 0
114#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000004U
115#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 2
116#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SIGNED 0
117#define EUR_CR_CLKGATESTATUS_TE_CLKS_MASK 0x00000008U
118#define EUR_CR_CLKGATESTATUS_TE_CLKS_SHIFT 3
119#define EUR_CR_CLKGATESTATUS_TE_CLKS_SIGNED 0
120#define EUR_CR_CLKGATESTATUS_MTE_CLKS_MASK 0x00000010U
121#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SHIFT 4
122#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SIGNED 0
123#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00000020U
124#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 5
125#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SIGNED 0
126#define EUR_CR_CLKGATESTATUS_VDM_CLKS_MASK 0x00000040U
127#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SHIFT 6
128#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SIGNED 0
129#define EUR_CR_CLKGATESTATUS_PDS_CLKS_MASK 0x00000080U
130#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SHIFT 7
131#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SIGNED 0
132#define EUR_CR_CLKGATESTATUS_PBE_CLKS_MASK 0x00000100U
133#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SHIFT 8
134#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SIGNED 0
135#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_MASK 0x00000200U
136#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SHIFT 9
137#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SIGNED 0
138#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_MASK 0x00000400U
139#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SHIFT 10
140#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SIGNED 0
141#define EUR_CR_CLKGATESTATUS_USE0_CLKS_MASK 0x00000800U
142#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SHIFT 11
143#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SIGNED 0
144#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_MASK 0x00001000U
145#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SHIFT 12
146#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SIGNED 0
147#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_MASK 0x00002000U
148#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SHIFT 13
149#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SIGNED 0
150#define EUR_CR_CLKGATESTATUS_USE1_CLKS_MASK 0x00008000U
151#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SHIFT 15
152#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SIGNED 0
153#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_MASK 0x00010000U
154#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SHIFT 16
155#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SIGNED 0
156#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_MASK 0x00020000U
157#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SHIFT 17
158#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SIGNED 0
159#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_MASK 0x00080000U
160#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SHIFT 19
161#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SIGNED 0
162#define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00100000U
163#define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 20
164#define EUR_CR_CLKGATESTATUS_TA_CLKS_SIGNED 0
165#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_MASK 0x00200000U
166#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SHIFT 21
167#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SIGNED 0
168#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_MASK 0x00400000U
169#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SHIFT 22
170#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SIGNED 0
171#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_MASK 0x00800000U
172#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SHIFT 23
173#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SIGNED 0
174#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_MASK 0x01000000U
175#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SHIFT 24
176#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SIGNED 0
177#define EUR_CR_CLKGATECTLOVR 0x000C
178#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U
179#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0
180#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SIGNED 0
181#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_MASK 0x0000000CU
182#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SHIFT 2
183#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SIGNED 0
184#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000030U
185#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 4
186#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SIGNED 0
187#define EUR_CR_CLKGATECTLOVR_TE_CLKO_MASK 0x000000C0U
188#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SHIFT 6
189#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SIGNED 0
190#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_MASK 0x00000300U
191#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SHIFT 8
192#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SIGNED 0
193#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00000C00U
194#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 10
195#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SIGNED 0
196#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_MASK 0x00003000U
197#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SHIFT 12
198#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SIGNED 0
199#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_MASK 0x0000C000U
200#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SHIFT 14
201#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SIGNED 0
202#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_MASK 0x00030000U
203#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SHIFT 16
204#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SIGNED 0
205#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x000C0000U
206#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 18
207#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SIGNED 0
208#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_MASK 0x00300000U
209#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SHIFT 20
210#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SIGNED 0
211#define EUR_CR_POWER 0x001C
212#define EUR_CR_POWER_PIPE_DISABLE_MASK 0x00000001U
213#define EUR_CR_POWER_PIPE_DISABLE_SHIFT 0
214#define EUR_CR_POWER_PIPE_DISABLE_SIGNED 0
215#define EUR_CR_CORE_ID 0x0020
216#define EUR_CR_CORE_ID_CONFIG_MULTI_MASK 0x00000001U
217#define EUR_CR_CORE_ID_CONFIG_MULTI_SHIFT 0
218#define EUR_CR_CORE_ID_CONFIG_MULTI_SIGNED 0
219#define EUR_CR_CORE_ID_CONFIG_BASE_MASK 0x00000002U
220#define EUR_CR_CORE_ID_CONFIG_BASE_SHIFT 1
221#define EUR_CR_CORE_ID_CONFIG_BASE_SIGNED 0
222#define EUR_CR_CORE_ID_CONFIG_MASK 0x000000FCU
223#define EUR_CR_CORE_ID_CONFIG_SHIFT 2
224#define EUR_CR_CORE_ID_CONFIG_SIGNED 0
225#define EUR_CR_CORE_ID_CONFIG_CORES_MASK 0x00000F00U
226#define EUR_CR_CORE_ID_CONFIG_CORES_SHIFT 8
227#define EUR_CR_CORE_ID_CONFIG_CORES_SIGNED 0
228#define EUR_CR_CORE_ID_CONFIG_SLC_MASK 0x0000F000U
229#define EUR_CR_CORE_ID_CONFIG_SLC_SHIFT 12
230#define EUR_CR_CORE_ID_CONFIG_SLC_SIGNED 0
231#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U
232#define EUR_CR_CORE_ID_ID_SHIFT 16
233#define EUR_CR_CORE_ID_ID_SIGNED 0
234#define EUR_CR_CORE_REVISION 0x0024
235#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU
236#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0
237#define EUR_CR_CORE_REVISION_MAINTENANCE_SIGNED 0
238#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U
239#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8
240#define EUR_CR_CORE_REVISION_MINOR_SIGNED 0
241#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U
242#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16
243#define EUR_CR_CORE_REVISION_MAJOR_SIGNED 0
244#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U
245#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24
246#define EUR_CR_CORE_REVISION_DESIGNER_SIGNED 0
247#define EUR_CR_DESIGNER_REV_FIELD1 0x0028
248#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU
249#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0
250#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SIGNED 0
251#define EUR_CR_DESIGNER_REV_FIELD2 0x002C
252#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU
253#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0
254#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SIGNED 0
255#define EUR_CR_SOFT_RESET 0x0080
256#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U
257#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0
258#define EUR_CR_SOFT_RESET_BIF_RESET_SIGNED 0
259#define EUR_CR_SOFT_RESET_VDM_RESET_MASK 0x00000002U
260#define EUR_CR_SOFT_RESET_VDM_RESET_SHIFT 1
261#define EUR_CR_SOFT_RESET_VDM_RESET_SIGNED 0
262#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U
263#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2
264#define EUR_CR_SOFT_RESET_DPM_RESET_SIGNED 0
265#define EUR_CR_SOFT_RESET_TE_RESET_MASK 0x00000008U
266#define EUR_CR_SOFT_RESET_TE_RESET_SHIFT 3
267#define EUR_CR_SOFT_RESET_TE_RESET_SIGNED 0
268#define EUR_CR_SOFT_RESET_MTE_RESET_MASK 0x00000010U
269#define EUR_CR_SOFT_RESET_MTE_RESET_SHIFT 4
270#define EUR_CR_SOFT_RESET_MTE_RESET_SIGNED 0
271#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U
272#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5
273#define EUR_CR_SOFT_RESET_ISP_RESET_SIGNED 0
274#define EUR_CR_SOFT_RESET_ISP2_RESET_MASK 0x00000040U
275#define EUR_CR_SOFT_RESET_ISP2_RESET_SHIFT 6
276#define EUR_CR_SOFT_RESET_ISP2_RESET_SIGNED 0
277#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000080U
278#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 7
279#define EUR_CR_SOFT_RESET_TSP_RESET_SIGNED 0
280#define EUR_CR_SOFT_RESET_PDS_RESET_MASK 0x00000100U
281#define EUR_CR_SOFT_RESET_PDS_RESET_SHIFT 8
282#define EUR_CR_SOFT_RESET_PDS_RESET_SIGNED 0
283#define EUR_CR_SOFT_RESET_PBE_RESET_MASK 0x00000200U
284#define EUR_CR_SOFT_RESET_PBE_RESET_SHIFT 9
285#define EUR_CR_SOFT_RESET_PBE_RESET_SIGNED 0
286#define EUR_CR_SOFT_RESET_TCU_L2_RESET_MASK 0x00000400U
287#define EUR_CR_SOFT_RESET_TCU_L2_RESET_SHIFT 10
288#define EUR_CR_SOFT_RESET_TCU_L2_RESET_SIGNED 0
289#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK 0x00000800U
290#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SHIFT 11
291#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SIGNED 0
292#define EUR_CR_SOFT_RESET_ITR_RESET_MASK 0x00002000U
293#define EUR_CR_SOFT_RESET_ITR_RESET_SHIFT 13
294#define EUR_CR_SOFT_RESET_ITR_RESET_SIGNED 0
295#define EUR_CR_SOFT_RESET_TEX_RESET_MASK 0x00004000U
296#define EUR_CR_SOFT_RESET_TEX_RESET_SHIFT 14
297#define EUR_CR_SOFT_RESET_TEX_RESET_SIGNED 0
298#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00008000U
299#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 15
300#define EUR_CR_SOFT_RESET_USE_RESET_SIGNED 0
301#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK 0x00010000U
302#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SHIFT 16
303#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SIGNED 0
304#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00020000U
305#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 17
306#define EUR_CR_SOFT_RESET_TA_RESET_SIGNED 0
307#define EUR_CR_SOFT_RESET_DCU_L2_RESET_MASK 0x00040000U
308#define EUR_CR_SOFT_RESET_DCU_L2_RESET_SHIFT 18
309#define EUR_CR_SOFT_RESET_DCU_L2_RESET_SIGNED 0
310#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_MASK 0x00080000U
311#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SHIFT 19
312#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SIGNED 0
313#define EUR_CR_EVENT_HOST_ENABLE2 0x0110
314#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U
315#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11
316#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0
317#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U
318#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SHIFT 10
319#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SIGNED 0
320#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_MASK 0x00000200U
321#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SHIFT 9
322#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SIGNED 0
323#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U
324#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SHIFT 8
325#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SIGNED 0
326#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_MASK 0x00000080U
327#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SHIFT 7
328#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SIGNED 0
329#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_MASK 0x00000040U
330#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SHIFT 6
331#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SIGNED 0
332#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U
333#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5
334#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0
335#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U
336#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4
337#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SIGNED 0
338#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U
339#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3
340#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SIGNED 0
341#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U
342#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2
343#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SIGNED 0
344#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U
345#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1
346#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SIGNED 0
347#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U
348#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0
349#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SIGNED 0
350#define EUR_CR_EVENT_HOST_CLEAR2 0x0114
351#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U
352#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11
353#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0
354#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U
355#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SHIFT 10
356#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SIGNED 0
357#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_MASK 0x00000200U
358#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SHIFT 9
359#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SIGNED 0
360#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U
361#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SHIFT 8
362#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SIGNED 0
363#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_MASK 0x00000080U
364#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SHIFT 7
365#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SIGNED 0
366#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_MASK 0x00000040U
367#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SHIFT 6
368#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SIGNED 0
369#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U
370#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5
371#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0
372#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U
373#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4
374#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SIGNED 0
375#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U
376#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3
377#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SIGNED 0
378#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U
379#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2
380#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SIGNED 0
381#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U
382#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1
383#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SIGNED 0
384#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U
385#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0
386#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SIGNED 0
387#define EUR_CR_EVENT_STATUS2 0x0118
388#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U
389#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11
390#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0
391#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U
392#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SHIFT 10
393#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SIGNED 0
394#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_MASK 0x00000200U
395#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SHIFT 9
396#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SIGNED 0
397#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U
398#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SHIFT 8
399#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SIGNED 0
400#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_MASK 0x00000080U
401#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SHIFT 7
402#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SIGNED 0
403#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_MASK 0x00000040U
404#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SHIFT 6
405#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SIGNED 0
406#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U
407#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5
408#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0
409#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U
410#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4
411#define EUR_CR_EVENT_STATUS2_TRIG_TA_SIGNED 0
412#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U
413#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3
414#define EUR_CR_EVENT_STATUS2_TRIG_3D_SIGNED 0
415#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U
416#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2
417#define EUR_CR_EVENT_STATUS2_TRIG_DL_SIGNED 0
418#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U
419#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1
420#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SIGNED 0
421#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U
422#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0
423#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SIGNED 0
424#define EUR_CR_EVENT_STATUS 0x012C
425#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U
426#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31
427#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SIGNED 0
428#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U
429#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29
430#define EUR_CR_EVENT_STATUS_TIMER_SIGNED 0
431#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U
432#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28
433#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SIGNED 0
434#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_MASK 0x04000000U
435#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SHIFT 26
436#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SIGNED 0
437#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
438#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
439#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0
440#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U
441#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24
442#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SIGNED 0
443#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U
444#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23
445#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SIGNED 0
446#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U
447#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22
448#define EUR_CR_EVENT_STATUS_DPM_INITEND_SIGNED 0
449#define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U
450#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21
451#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SIGNED 0
452#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U
453#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20
454#define EUR_CR_EVENT_STATUS_OTPM_INV_SIGNED 0
455#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U
456#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19
457#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SIGNED 0
458#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U
459#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18
460#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SIGNED 0
461#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U
462#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15
463#define EUR_CR_EVENT_STATUS_BREAKPOINT_SIGNED 0
464#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U
465#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14
466#define EUR_CR_EVENT_STATUS_SW_EVENT_SIGNED 0
467#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U
468#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13
469#define EUR_CR_EVENT_STATUS_TA_FINISHED_SIGNED 0
470#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U
471#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12
472#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SIGNED 0
473#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U
474#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11
475#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SIGNED 0
476#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U
477#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10
478#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SIGNED 0
479#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U
480#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9
481#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SIGNED 0
482#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U
483#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8
484#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SIGNED 0
485#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U
486#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7
487#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SIGNED 0
488#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U
489#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6
490#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SIGNED 0
491#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U
492#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5
493#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SIGNED 0
494#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U
495#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4
496#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SIGNED 0
497#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
498#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3
499#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SIGNED 0
500#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
501#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
502#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SIGNED 0
503#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
504#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1
505#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SIGNED 0
506#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U
507#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0
508#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SIGNED 0
509#define EUR_CR_EVENT_HOST_ENABLE 0x0130
510#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U
511#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31
512#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SIGNED 0
513#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U
514#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29
515#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SIGNED 0
516#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U
517#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28
518#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SIGNED 0
519#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_MASK 0x04000000U
520#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SHIFT 26
521#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SIGNED 0
522#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
523#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
524#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0
525#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U
526#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24
527#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SIGNED 0
528#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U
529#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23
530#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SIGNED 0
531#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U
532#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22
533#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SIGNED 0
534#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U
535#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21
536#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SIGNED 0
537#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U
538#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20
539#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SIGNED 0
540#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U
541#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19
542#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SIGNED 0
543#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U
544#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18
545#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SIGNED 0
546#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U
547#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15
548#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SIGNED 0
549#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U
550#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14
551#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SIGNED 0
552#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U
553#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13
554#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SIGNED 0
555#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U
556#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12
557#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SIGNED 0
558#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U
559#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11
560#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SIGNED 0
561#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U
562#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10
563#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SIGNED 0
564#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U
565#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9
566#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SIGNED 0
567#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U
568#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8
569#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SIGNED 0
570#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U
571#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7
572#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SIGNED 0
573#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U
574#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6
575#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SIGNED 0
576#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U
577#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5
578#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SIGNED 0
579#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U
580#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4
581#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SIGNED 0
582#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
583#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3
584#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SIGNED 0
585#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
586#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
587#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SIGNED 0
588#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
589#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1
590#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SIGNED 0
591#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U
592#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0
593#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SIGNED 0
594#define EUR_CR_EVENT_HOST_CLEAR 0x0134
595#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U
596#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31
597#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SIGNED 0
598#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U
599#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29
600#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SIGNED 0
601#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U
602#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28
603#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SIGNED 0
604#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_MASK 0x04000000U
605#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SHIFT 26
606#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SIGNED 0
607#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
608#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
609#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0
610#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U
611#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24
612#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SIGNED 0
613#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U
614#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23
615#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SIGNED 0
616#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U
617#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22
618#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SIGNED 0
619#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U
620#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21
621#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SIGNED 0
622#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U
623#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20
624#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SIGNED 0
625#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U
626#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19
627#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SIGNED 0
628#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U
629#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18
630#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SIGNED 0
631#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U
632#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15
633#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SIGNED 0
634#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U
635#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14
636#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SIGNED 0
637#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U
638#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13
639#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SIGNED 0
640#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U
641#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12
642#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SIGNED 0
643#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U
644#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11
645#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SIGNED 0
646#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U
647#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10
648#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SIGNED 0
649#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U
650#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9
651#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SIGNED 0
652#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U
653#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8
654#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SIGNED 0
655#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U
656#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7
657#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SIGNED 0
658#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U
659#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6
660#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SIGNED 0
661#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U
662#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5
663#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SIGNED 0
664#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U
665#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4
666#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SIGNED 0
667#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
668#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3
669#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SIGNED 0
670#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
671#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
672#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SIGNED 0
673#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
674#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1
675#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SIGNED 0
676#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U
677#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0
678#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SIGNED 0
679#define EUR_CR_TIMER 0x0144
680#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU
681#define EUR_CR_TIMER_VALUE_SHIFT 0
682#define EUR_CR_TIMER_VALUE_SIGNED 0
683#define EUR_CR_EVENT_KICK1 0x0AB0
684#define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU
685#define EUR_CR_EVENT_KICK1_NOW_SHIFT 0
686#define EUR_CR_EVENT_KICK1_NOW_SIGNED 0
687#define EUR_CR_EVENT_KICK2 0x0AC0
688#define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U
689#define EUR_CR_EVENT_KICK2_NOW_SHIFT 0
690#define EUR_CR_EVENT_KICK2_NOW_SIGNED 0
691#define EUR_CR_EVENT_KICKER 0x0AC4
692#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0xFFFFFFF0U
693#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4
694#define EUR_CR_EVENT_KICKER_ADDRESS_SIGNED 0
695#define EUR_CR_EVENT_KICK 0x0AC8
696#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U
697#define EUR_CR_EVENT_KICK_NOW_SHIFT 0
698#define EUR_CR_EVENT_KICK_NOW_SIGNED 0
699#define EUR_CR_EVENT_TIMER 0x0ACC
700#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U
701#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24
702#define EUR_CR_EVENT_TIMER_ENABLE_SIGNED 0
703#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU
704#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0
705#define EUR_CR_EVENT_TIMER_VALUE_SIGNED 0
706#define EUR_CR_PDS_INV0 0x0AD0
707#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U
708#define EUR_CR_PDS_INV0_DSC_SHIFT 0
709#define EUR_CR_PDS_INV0_DSC_SIGNED 0
710#define EUR_CR_PDS_INV1 0x0AD4
711#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U
712#define EUR_CR_PDS_INV1_DSC_SHIFT 0
713#define EUR_CR_PDS_INV1_DSC_SIGNED 0
714#define EUR_CR_EVENT_KICK3 0x0AD8
715#define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U
716#define EUR_CR_EVENT_KICK3_NOW_SHIFT 0
717#define EUR_CR_EVENT_KICK3_NOW_SIGNED 0
718#define EUR_CR_PDS_INV3 0x0ADC
719#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U
720#define EUR_CR_PDS_INV3_DSC_SHIFT 0
721#define EUR_CR_PDS_INV3_DSC_SIGNED 0
722#define EUR_CR_PDS_INV_CSC 0x0AE0
723#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U
724#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0
725#define EUR_CR_PDS_INV_CSC_KICK_SIGNED 0
726#define EUR_CR_BIF_CTRL 0x0C00
727#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U
728#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0
729#define EUR_CR_BIF_CTRL_NOREORDER_SIGNED 0
730#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U
731#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1
732#define EUR_CR_BIF_CTRL_PAUSE_SIGNED 0
733#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U
734#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4
735#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SIGNED 0
736#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U
737#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9
738#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SIGNED 0
739#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_MASK 0x00000400U
740#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SHIFT 10
741#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SIGNED 0
742#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U
743#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12
744#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SIGNED 0
745#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U
746#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13
747#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SIGNED 0
748#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U
749#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14
750#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SIGNED 0
751#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U
752#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15
753#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SIGNED 0
754#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_MASK 0x00010000U
755#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SHIFT 16
756#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SIGNED 0
757#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_MASK 0x00020000U
758#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SHIFT 17
759#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SIGNED 0
760#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_MASK 0x00040000U
761#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SHIFT 18
762#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SIGNED 0
763#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_MASK 0x00080000U
764#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SHIFT 19
765#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SIGNED 0
766#define EUR_CR_BIF_INT_STAT 0x0C04
767#define EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK 0x00003FFFU
768#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SHIFT 0
769#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SIGNED 0
770#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_MASK 0x00070000U
771#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SHIFT 16
772#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SIGNED 0
773#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00080000U
774#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 19
775#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SIGNED 0
776#define EUR_CR_BIF_FAULT 0x0C08
777#define EUR_CR_BIF_FAULT_CID_MASK 0x0000000FU
778#define EUR_CR_BIF_FAULT_CID_SHIFT 0
779#define EUR_CR_BIF_FAULT_CID_SIGNED 0
780#define EUR_CR_BIF_FAULT_SB_MASK 0x000001F0U
781#define EUR_CR_BIF_FAULT_SB_SHIFT 4
782#define EUR_CR_BIF_FAULT_SB_SIGNED 0
783#define EUR_CR_BIF_FAULT_ADDR_MASK 0xFFFFF000U
784#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12
785#define EUR_CR_BIF_FAULT_ADDR_SIGNED 0
786#define EUR_CR_BIF_TILE0 0x0C0C
787#define EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK 0x00000FFFU
788#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT 0
789#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SIGNED 0
790#define EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK 0x00FFF000U
791#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT 12
792#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SIGNED 0
793#define EUR_CR_BIF_TILE0_CFG_MASK 0x0F000000U
794#define EUR_CR_BIF_TILE0_CFG_SHIFT 24
795#define EUR_CR_BIF_TILE0_CFG_SIGNED 0
796#define EUR_CR_BIF_TILE1 0x0C10
797#define EUR_CR_BIF_TILE1_MIN_ADDRESS_MASK 0x00000FFFU
798#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SHIFT 0
799#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SIGNED 0
800#define EUR_CR_BIF_TILE1_MAX_ADDRESS_MASK 0x00FFF000U
801#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SHIFT 12
802#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SIGNED 0
803#define EUR_CR_BIF_TILE1_CFG_MASK 0x0F000000U
804#define EUR_CR_BIF_TILE1_CFG_SHIFT 24
805#define EUR_CR_BIF_TILE1_CFG_SIGNED 0
806#define EUR_CR_BIF_TILE2 0x0C14
807#define EUR_CR_BIF_TILE2_MIN_ADDRESS_MASK 0x00000FFFU
808#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SHIFT 0
809#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SIGNED 0
810#define EUR_CR_BIF_TILE2_MAX_ADDRESS_MASK 0x00FFF000U
811#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SHIFT 12
812#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SIGNED 0
813#define EUR_CR_BIF_TILE2_CFG_MASK 0x0F000000U
814#define EUR_CR_BIF_TILE2_CFG_SHIFT 24
815#define EUR_CR_BIF_TILE2_CFG_SIGNED 0
816#define EUR_CR_BIF_TILE3 0x0C18
817#define EUR_CR_BIF_TILE3_MIN_ADDRESS_MASK 0x00000FFFU
818#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SHIFT 0
819#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SIGNED 0
820#define EUR_CR_BIF_TILE3_MAX_ADDRESS_MASK 0x00FFF000U
821#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SHIFT 12
822#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SIGNED 0
823#define EUR_CR_BIF_TILE3_CFG_MASK 0x0F000000U
824#define EUR_CR_BIF_TILE3_CFG_SHIFT 24
825#define EUR_CR_BIF_TILE3_CFG_SIGNED 0
826#define EUR_CR_BIF_TILE4 0x0C1C
827#define EUR_CR_BIF_TILE4_MIN_ADDRESS_MASK 0x00000FFFU
828#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SHIFT 0
829#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SIGNED 0
830#define EUR_CR_BIF_TILE4_MAX_ADDRESS_MASK 0x00FFF000U
831#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SHIFT 12
832#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SIGNED 0
833#define EUR_CR_BIF_TILE4_CFG_MASK 0x0F000000U
834#define EUR_CR_BIF_TILE4_CFG_SHIFT 24
835#define EUR_CR_BIF_TILE4_CFG_SIGNED 0
836#define EUR_CR_BIF_TILE5 0x0C20
837#define EUR_CR_BIF_TILE5_MIN_ADDRESS_MASK 0x00000FFFU
838#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SHIFT 0
839#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SIGNED 0
840#define EUR_CR_BIF_TILE5_MAX_ADDRESS_MASK 0x00FFF000U
841#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SHIFT 12
842#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SIGNED 0
843#define EUR_CR_BIF_TILE5_CFG_MASK 0x0F000000U
844#define EUR_CR_BIF_TILE5_CFG_SHIFT 24
845#define EUR_CR_BIF_TILE5_CFG_SIGNED 0
846#define EUR_CR_BIF_TILE6 0x0C24
847#define EUR_CR_BIF_TILE6_MIN_ADDRESS_MASK 0x00000FFFU
848#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SHIFT 0
849#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SIGNED 0
850#define EUR_CR_BIF_TILE6_MAX_ADDRESS_MASK 0x00FFF000U
851#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SHIFT 12
852#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SIGNED 0
853#define EUR_CR_BIF_TILE6_CFG_MASK 0x0F000000U
854#define EUR_CR_BIF_TILE6_CFG_SHIFT 24
855#define EUR_CR_BIF_TILE6_CFG_SIGNED 0
856#define EUR_CR_BIF_TILE7 0x0C28
857#define EUR_CR_BIF_TILE7_MIN_ADDRESS_MASK 0x00000FFFU
858#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SHIFT 0
859#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SIGNED 0
860#define EUR_CR_BIF_TILE7_MAX_ADDRESS_MASK 0x00FFF000U
861#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SHIFT 12
862#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SIGNED 0
863#define EUR_CR_BIF_TILE7_CFG_MASK 0x0F000000U
864#define EUR_CR_BIF_TILE7_CFG_SHIFT 24
865#define EUR_CR_BIF_TILE7_CFG_SIGNED 0
866#define EUR_CR_BIF_TILE8 0x0C2C
867#define EUR_CR_BIF_TILE8_MIN_ADDRESS_MASK 0x00000FFFU
868#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SHIFT 0
869#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SIGNED 0
870#define EUR_CR_BIF_TILE8_MAX_ADDRESS_MASK 0x00FFF000U
871#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SHIFT 12
872#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SIGNED 0
873#define EUR_CR_BIF_TILE8_CFG_MASK 0x0F000000U
874#define EUR_CR_BIF_TILE8_CFG_SHIFT 24
875#define EUR_CR_BIF_TILE8_CFG_SIGNED 0
876#define EUR_CR_BIF_TILE9 0x0C30
877#define EUR_CR_BIF_TILE9_MIN_ADDRESS_MASK 0x00000FFFU
878#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SHIFT 0
879#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SIGNED 0
880#define EUR_CR_BIF_TILE9_MAX_ADDRESS_MASK 0x00FFF000U
881#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SHIFT 12
882#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SIGNED 0
883#define EUR_CR_BIF_TILE9_CFG_MASK 0x0F000000U
884#define EUR_CR_BIF_TILE9_CFG_SHIFT 24
885#define EUR_CR_BIF_TILE9_CFG_SIGNED 0
886#define EUR_CR_BIF_CTRL_INVAL 0x0C34
887#define EUR_CR_BIF_CTRL_INVAL_PTE_MASK 0x00000004U
888#define EUR_CR_BIF_CTRL_INVAL_PTE_SHIFT 2
889#define EUR_CR_BIF_CTRL_INVAL_PTE_SIGNED 0
890#define EUR_CR_BIF_CTRL_INVAL_ALL_MASK 0x00000008U
891#define EUR_CR_BIF_CTRL_INVAL_ALL_SHIFT 3
892#define EUR_CR_BIF_CTRL_INVAL_ALL_SIGNED 0
893#define EUR_CR_BIF_DIR_LIST_BASE1 0x0C38
894#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_MASK 0xFFFFF000U
895#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SHIFT 12
896#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SIGNED 0
897#define EUR_CR_BIF_DIR_LIST_BASE2 0x0C3C
898#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_MASK 0xFFFFF000U
899#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SHIFT 12
900#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SIGNED 0
901#define EUR_CR_BIF_DIR_LIST_BASE3 0x0C40
902#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_MASK 0xFFFFF000U
903#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SHIFT 12
904#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SIGNED 0
905#define EUR_CR_BIF_DIR_LIST_BASE4 0x0C44
906#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_MASK 0xFFFFF000U
907#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SHIFT 12
908#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SIGNED 0
909#define EUR_CR_BIF_DIR_LIST_BASE5 0x0C48
910#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_MASK 0xFFFFF000U
911#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SHIFT 12
912#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SIGNED 0
913#define EUR_CR_BIF_DIR_LIST_BASE6 0x0C4C
914#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_MASK 0xFFFFF000U
915#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SHIFT 12
916#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SIGNED 0
917#define EUR_CR_BIF_DIR_LIST_BASE7 0x0C50
918#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_MASK 0xFFFFF000U
919#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SHIFT 12
920#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SIGNED 0
921#define EUR_CR_BIF_BANK_SET 0x0C74
922#define EUR_CR_BIF_BANK_SET_SELECT_2D_MASK 0x00000001U
923#define EUR_CR_BIF_BANK_SET_SELECT_2D_SHIFT 0
924#define EUR_CR_BIF_BANK_SET_SELECT_2D_SIGNED 0
925#define EUR_CR_BIF_BANK_SET_SELECT_3D_MASK 0x0000000CU
926#define EUR_CR_BIF_BANK_SET_SELECT_3D_SHIFT 2
927#define EUR_CR_BIF_BANK_SET_SELECT_3D_SIGNED 0
928#define EUR_CR_BIF_BANK_SET_SELECT_HOST_MASK 0x00000010U
929#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SHIFT 4
930#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SIGNED 0
931#define EUR_CR_BIF_BANK_SET_SELECT_TA_MASK 0x000000C0U
932#define EUR_CR_BIF_BANK_SET_SELECT_TA_SHIFT 6
933#define EUR_CR_BIF_BANK_SET_SELECT_TA_SIGNED 0
934#define EUR_CR_BIF_BANK_SET_SELECT_EDM_MASK 0x00000100U
935#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SHIFT 8
936#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SIGNED 0
937#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_MASK 0x00000200U
938#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SHIFT 9
939#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SIGNED 0
940#define EUR_CR_BIF_BANK0 0x0C78
941#define EUR_CR_BIF_BANK0_INDEX_EDM_MASK 0x0000000FU
942#define EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT 0
943#define EUR_CR_BIF_BANK0_INDEX_EDM_SIGNED 0
944#define EUR_CR_BIF_BANK0_INDEX_TA_MASK 0x000000F0U
945#define EUR_CR_BIF_BANK0_INDEX_TA_SHIFT 4
946#define EUR_CR_BIF_BANK0_INDEX_TA_SIGNED 0
947#define EUR_CR_BIF_BANK0_INDEX_3D_MASK 0x0000F000U
948#define EUR_CR_BIF_BANK0_INDEX_3D_SHIFT 12
949#define EUR_CR_BIF_BANK0_INDEX_3D_SIGNED 0
950#define EUR_CR_BIF_BANK0_INDEX_PTLA_MASK 0x000F0000U
951#define EUR_CR_BIF_BANK0_INDEX_PTLA_SHIFT 16
952#define EUR_CR_BIF_BANK0_INDEX_PTLA_SIGNED 0
953#define EUR_CR_BIF_BANK1 0x0C7C
954#define EUR_CR_BIF_BANK1_INDEX_EDM_MASK 0x0000000FU
955#define EUR_CR_BIF_BANK1_INDEX_EDM_SHIFT 0
956#define EUR_CR_BIF_BANK1_INDEX_EDM_SIGNED 0
957#define EUR_CR_BIF_BANK1_INDEX_TA_MASK 0x000000F0U
958#define EUR_CR_BIF_BANK1_INDEX_TA_SHIFT 4
959#define EUR_CR_BIF_BANK1_INDEX_TA_SIGNED 0
960#define EUR_CR_BIF_BANK1_INDEX_3D_MASK 0x0000F000U
961#define EUR_CR_BIF_BANK1_INDEX_3D_SHIFT 12
962#define EUR_CR_BIF_BANK1_INDEX_3D_SIGNED 0
963#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84
964#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U
965#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12
966#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SIGNED 0
967#define EUR_CR_BIF_TA_REQ_BASE 0x0C90
968#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0xFFF00000U
969#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20
970#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SIGNED 0
971#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8
972#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU
973#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0
974#define EUR_CR_BIF_MEM_REQ_STAT_READS_SIGNED 0
975#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC
976#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0xFFF00000U
977#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20
978#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SIGNED 0
979#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0
980#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0xFFF00000U
981#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20
982#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SIGNED 0
983#define EUR_CR_BIF_BANK_STATUS 0x0CB4
984#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_MASK 0x00000001U
985#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SHIFT 0
986#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SIGNED 0
987#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U
988#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1
989#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0
990#define EUR_CR_BIF_MMU_CTRL 0x0CD0
991#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_MASK 0x00000001U
992#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SHIFT 0
993#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SIGNED 0
994#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_MASK 0x00000006U
995#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT 1
996#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SIGNED 0
997#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_MASK 0x00000008U
998#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SHIFT 3
999#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SIGNED 0
1000#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK 0x00000010U
1001#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SHIFT 4
1002#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SIGNED 0
1003#define EUR_CR_2D_BLIT_STATUS 0x0E04
1004#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU
1005#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0
1006#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SIGNED 0
1007#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U
1008#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24
1009#define EUR_CR_2D_BLIT_STATUS_BUSY_SIGNED 0
1010#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10
1011#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U
1012#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0
1013#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SIGNED 0
1014#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU
1015#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1
1016#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SIGNED 0
1017#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U
1018#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4
1019#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SIGNED 0
1020#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U
1021#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12
1022#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SIGNED 0
1023#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14
1024#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU
1025#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0
1026#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SIGNED 0
1027#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U
1028#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12
1029#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SIGNED 0
1030#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U
1031#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24
1032#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SIGNED 0
1033#define EUR_CR_BREAKPOINT0_START 0x0F44
1034#define EUR_CR_BREAKPOINT0_START_ADDRESS_MASK 0xFFFFFFF0U
1035#define EUR_CR_BREAKPOINT0_START_ADDRESS_SHIFT 4
1036#define EUR_CR_BREAKPOINT0_START_ADDRESS_SIGNED 0
1037#define EUR_CR_BREAKPOINT0_END 0x0F48
1038#define EUR_CR_BREAKPOINT0_END_ADDRESS_MASK 0xFFFFFFF0U
1039#define EUR_CR_BREAKPOINT0_END_ADDRESS_SHIFT 4
1040#define EUR_CR_BREAKPOINT0_END_ADDRESS_SIGNED 0
1041#define EUR_CR_BREAKPOINT0 0x0F4C
1042#define EUR_CR_BREAKPOINT0_MASK_DM_MASK 0x00000038U
1043#define EUR_CR_BREAKPOINT0_MASK_DM_SHIFT 3
1044#define EUR_CR_BREAKPOINT0_MASK_DM_SIGNED 0
1045#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_MASK 0x00000004U
1046#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SHIFT 2
1047#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SIGNED 0
1048#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_MASK 0x00000002U
1049#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SHIFT 1
1050#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SIGNED 0
1051#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_MASK 0x00000001U
1052#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SHIFT 0
1053#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SIGNED 0
1054#define EUR_CR_BREAKPOINT1_START 0x0F50
1055#define EUR_CR_BREAKPOINT1_START_ADDRESS_MASK 0xFFFFFFF0U
1056#define EUR_CR_BREAKPOINT1_START_ADDRESS_SHIFT 4
1057#define EUR_CR_BREAKPOINT1_START_ADDRESS_SIGNED 0
1058#define EUR_CR_BREAKPOINT1_END 0x0F54
1059#define EUR_CR_BREAKPOINT1_END_ADDRESS_MASK 0xFFFFFFF0U
1060#define EUR_CR_BREAKPOINT1_END_ADDRESS_SHIFT 4
1061#define EUR_CR_BREAKPOINT1_END_ADDRESS_SIGNED 0
1062#define EUR_CR_BREAKPOINT1 0x0F58
1063#define EUR_CR_BREAKPOINT1_MASK_DM_MASK 0x00000038U
1064#define EUR_CR_BREAKPOINT1_MASK_DM_SHIFT 3
1065#define EUR_CR_BREAKPOINT1_MASK_DM_SIGNED 0
1066#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_MASK 0x00000004U
1067#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SHIFT 2
1068#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SIGNED 0
1069#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_MASK 0x00000002U
1070#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SHIFT 1
1071#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SIGNED 0
1072#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_MASK 0x00000001U
1073#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SHIFT 0
1074#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SIGNED 0
1075#define EUR_CR_BREAKPOINT2_START 0x0F5C
1076#define EUR_CR_BREAKPOINT2_START_ADDRESS_MASK 0xFFFFFFF0U
1077#define EUR_CR_BREAKPOINT2_START_ADDRESS_SHIFT 4
1078#define EUR_CR_BREAKPOINT2_START_ADDRESS_SIGNED 0
1079#define EUR_CR_BREAKPOINT2_END 0x0F60
1080#define EUR_CR_BREAKPOINT2_END_ADDRESS_MASK 0xFFFFFFF0U
1081#define EUR_CR_BREAKPOINT2_END_ADDRESS_SHIFT 4
1082#define EUR_CR_BREAKPOINT2_END_ADDRESS_SIGNED 0
1083#define EUR_CR_BREAKPOINT2 0x0F64
1084#define EUR_CR_BREAKPOINT2_MASK_DM_MASK 0x00000038U
1085#define EUR_CR_BREAKPOINT2_MASK_DM_SHIFT 3
1086#define EUR_CR_BREAKPOINT2_MASK_DM_SIGNED 0
1087#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_MASK 0x00000004U
1088#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SHIFT 2
1089#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SIGNED 0
1090#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_MASK 0x00000002U
1091#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SHIFT 1
1092#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SIGNED 0
1093#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_MASK 0x00000001U
1094#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SHIFT 0
1095#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SIGNED 0
1096#define EUR_CR_BREAKPOINT3_START 0x0F68
1097#define EUR_CR_BREAKPOINT3_START_ADDRESS_MASK 0xFFFFFFF0U
1098#define EUR_CR_BREAKPOINT3_START_ADDRESS_SHIFT 4
1099#define EUR_CR_BREAKPOINT3_START_ADDRESS_SIGNED 0
1100#define EUR_CR_BREAKPOINT3_END 0x0F6C
1101#define EUR_CR_BREAKPOINT3_END_ADDRESS_MASK 0xFFFFFFF0U
1102#define EUR_CR_BREAKPOINT3_END_ADDRESS_SHIFT 4
1103#define EUR_CR_BREAKPOINT3_END_ADDRESS_SIGNED 0
1104#define EUR_CR_BREAKPOINT3 0x0F70
1105#define EUR_CR_BREAKPOINT3_MASK_DM_MASK 0x00000038U
1106#define EUR_CR_BREAKPOINT3_MASK_DM_SHIFT 3
1107#define EUR_CR_BREAKPOINT3_MASK_DM_SIGNED 0
1108#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_MASK 0x00000004U
1109#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SHIFT 2
1110#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SIGNED 0
1111#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_MASK 0x00000002U
1112#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SHIFT 1
1113#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SIGNED 0
1114#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_MASK 0x00000001U
1115#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SHIFT 0
1116#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SIGNED 0
1117#define EUR_CR_BREAKPOINT_READ 0x0F74
1118#define EUR_CR_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U
1119#define EUR_CR_BREAKPOINT_READ_ADDRESS_SHIFT 4
1120#define EUR_CR_BREAKPOINT_READ_ADDRESS_SIGNED 0
1121#define EUR_CR_BREAKPOINT_TRAP 0x0F78
1122#define EUR_CR_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U
1123#define EUR_CR_BREAKPOINT_TRAP_CONTINUE_SHIFT 1
1124#define EUR_CR_BREAKPOINT_TRAP_CONTINUE_SIGNED 0
1125#define EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U
1126#define EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0
1127#define EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0
1128#define EUR_CR_BREAKPOINT 0x0F7C
1129#define EUR_CR_BREAKPOINT_MODULE_ID_MASK 0x000003C0U
1130#define EUR_CR_BREAKPOINT_MODULE_ID_SHIFT 6
1131#define EUR_CR_BREAKPOINT_MODULE_ID_SIGNED 0
1132#define EUR_CR_BREAKPOINT_ID_MASK 0x00000030U
1133#define EUR_CR_BREAKPOINT_ID_SHIFT 4
1134#define EUR_CR_BREAKPOINT_ID_SIGNED 0
1135#define EUR_CR_BREAKPOINT_UNTRAPPED_MASK 0x00000008U
1136#define EUR_CR_BREAKPOINT_UNTRAPPED_SHIFT 3
1137#define EUR_CR_BREAKPOINT_UNTRAPPED_SIGNED 0
1138#define EUR_CR_BREAKPOINT_TRAPPED_MASK 0x00000004U
1139#define EUR_CR_BREAKPOINT_TRAPPED_SHIFT 2
1140#define EUR_CR_BREAKPOINT_TRAPPED_SIGNED 0
1141#define EUR_CR_BREAKPOINT_TRAP_INFO0 0x0F80
1142#define EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U
1143#define EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4
1144#define EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0
1145#define EUR_CR_BREAKPOINT_TRAP_INFO1 0x0F84
1146#define EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U
1147#define EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10
1148#define EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0
1149#define EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U
1150#define EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8
1151#define EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0
1152#define EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U
1153#define EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3
1154#define EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0
1155#define EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U
1156#define EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1
1157#define EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0
1158#define EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U
1159#define EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0
1160#define EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0
1161#define EUR_CR_USE_CODE_BASE_0 0x0A0C
1162#define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x03FFFFFFU
1163#define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0
1164#define EUR_CR_USE_CODE_BASE_ADDR_00_SIGNED 0
1165#define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x0C000000U
1166#define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 26
1167#define EUR_CR_USE_CODE_BASE_DM_00_SIGNED 0
1168#define EUR_CR_USE_CODE_BASE_1 0x0A10
1169#define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x03FFFFFFU
1170#define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0
1171#define EUR_CR_USE_CODE_BASE_ADDR_01_SIGNED 0
1172#define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x0C000000U
1173#define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 26
1174#define EUR_CR_USE_CODE_BASE_DM_01_SIGNED 0
1175#define EUR_CR_USE_CODE_BASE_2 0x0A14
1176#define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x03FFFFFFU
1177#define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0
1178#define EUR_CR_USE_CODE_BASE_ADDR_02_SIGNED 0
1179#define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x0C000000U
1180#define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 26
1181#define EUR_CR_USE_CODE_BASE_DM_02_SIGNED 0
1182#define EUR_CR_USE_CODE_BASE_3 0x0A18
1183#define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x03FFFFFFU
1184#define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0
1185#define EUR_CR_USE_CODE_BASE_ADDR_03_SIGNED 0
1186#define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x0C000000U
1187#define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 26
1188#define EUR_CR_USE_CODE_BASE_DM_03_SIGNED 0
1189#define EUR_CR_USE_CODE_BASE_4 0x0A1C
1190#define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x03FFFFFFU
1191#define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0
1192#define EUR_CR_USE_CODE_BASE_ADDR_04_SIGNED 0
1193#define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x0C000000U
1194#define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 26
1195#define EUR_CR_USE_CODE_BASE_DM_04_SIGNED 0
1196#define EUR_CR_USE_CODE_BASE_5 0x0A20
1197#define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x03FFFFFFU
1198#define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0
1199#define EUR_CR_USE_CODE_BASE_ADDR_05_SIGNED 0
1200#define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x0C000000U
1201#define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 26
1202#define EUR_CR_USE_CODE_BASE_DM_05_SIGNED 0
1203#define EUR_CR_USE_CODE_BASE_6 0x0A24
1204#define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x03FFFFFFU
1205#define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0
1206#define EUR_CR_USE_CODE_BASE_ADDR_06_SIGNED 0
1207#define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x0C000000U
1208#define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 26
1209#define EUR_CR_USE_CODE_BASE_DM_06_SIGNED 0
1210#define EUR_CR_USE_CODE_BASE_7 0x0A28
1211#define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x03FFFFFFU
1212#define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0
1213#define EUR_CR_USE_CODE_BASE_ADDR_07_SIGNED 0
1214#define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x0C000000U
1215#define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 26
1216#define EUR_CR_USE_CODE_BASE_DM_07_SIGNED 0
1217#define EUR_CR_USE_CODE_BASE_8 0x0A2C
1218#define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x03FFFFFFU
1219#define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0
1220#define EUR_CR_USE_CODE_BASE_ADDR_08_SIGNED 0
1221#define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x0C000000U
1222#define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 26
1223#define EUR_CR_USE_CODE_BASE_DM_08_SIGNED 0
1224#define EUR_CR_USE_CODE_BASE_9 0x0A30
1225#define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x03FFFFFFU
1226#define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0
1227#define EUR_CR_USE_CODE_BASE_ADDR_09_SIGNED 0
1228#define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x0C000000U
1229#define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 26
1230#define EUR_CR_USE_CODE_BASE_DM_09_SIGNED 0
1231#define EUR_CR_USE_CODE_BASE_10 0x0A34
1232#define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x03FFFFFFU
1233#define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0
1234#define EUR_CR_USE_CODE_BASE_ADDR_10_SIGNED 0
1235#define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x0C000000U
1236#define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 26
1237#define EUR_CR_USE_CODE_BASE_DM_10_SIGNED 0
1238#define EUR_CR_USE_CODE_BASE_11 0x0A38
1239#define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x03FFFFFFU
1240#define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0
1241#define EUR_CR_USE_CODE_BASE_ADDR_11_SIGNED 0
1242#define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x0C000000U
1243#define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 26
1244#define EUR_CR_USE_CODE_BASE_DM_11_SIGNED 0
1245#define EUR_CR_USE_CODE_BASE_12 0x0A3C
1246#define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x03FFFFFFU
1247#define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0
1248#define EUR_CR_USE_CODE_BASE_ADDR_12_SIGNED 0
1249#define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x0C000000U
1250#define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 26
1251#define EUR_CR_USE_CODE_BASE_DM_12_SIGNED 0
1252#define EUR_CR_USE_CODE_BASE_13 0x0A40
1253#define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x03FFFFFFU
1254#define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0
1255#define EUR_CR_USE_CODE_BASE_ADDR_13_SIGNED 0
1256#define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x0C000000U
1257#define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 26
1258#define EUR_CR_USE_CODE_BASE_DM_13_SIGNED 0
1259#define EUR_CR_USE_CODE_BASE_14 0x0A44
1260#define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x03FFFFFFU
1261#define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0
1262#define EUR_CR_USE_CODE_BASE_ADDR_14_SIGNED 0
1263#define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x0C000000U
1264#define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 26
1265#define EUR_CR_USE_CODE_BASE_DM_14_SIGNED 0
1266#define EUR_CR_USE_CODE_BASE_15 0x0A48
1267#define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x03FFFFFFU
1268#define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0
1269#define EUR_CR_USE_CODE_BASE_ADDR_15_SIGNED 0
1270#define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x0C000000U
1271#define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 26
1272#define EUR_CR_USE_CODE_BASE_DM_15_SIGNED 0
1273#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X)))
1274#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x03FFFFFFU
1275#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0
1276#define EUR_CR_USE_CODE_BASE_ADDR_SIGNED 0
1277#define EUR_CR_USE_CODE_BASE_DM_MASK 0x0C000000U
1278#define EUR_CR_USE_CODE_BASE_DM_SHIFT 26
1279#define EUR_CR_USE_CODE_BASE_DM_SIGNED 0
1280#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16
1281#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16
1282
1283#endif
1284
diff --git a/drivers/gpu/pvr/sgx543defs.h b/drivers/gpu/pvr/sgx543defs.h
index ef8a06e5c2b..939a70ce8ba 100644
--- a/drivers/gpu/pvr/sgx543defs.h
+++ b/drivers/gpu/pvr/sgx543defs.h
@@ -58,6 +58,9 @@
58#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x000C0000U 58#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x000C0000U
59#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 18 59#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 18
60#define EUR_CR_CLKGATECTL_TA_CLKG_SIGNED 0 60#define EUR_CR_CLKGATECTL_TA_CLKG_SIGNED 0
61#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_MASK 0x00300000U
62#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SHIFT 20
63#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SIGNED 0
61#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U 64#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U
62#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24 65#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24
63#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SIGNED 0 66#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SIGNED 0
@@ -168,6 +171,9 @@
168#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_MASK 0x00800000U 171#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_MASK 0x00800000U
169#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SHIFT 23 172#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SHIFT 23
170#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SIGNED 0 173#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SIGNED 0
174#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_MASK 0x01000000U
175#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SHIFT 24
176#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SIGNED 0
171#define EUR_CR_CLKGATECTLOVR 0x000C 177#define EUR_CR_CLKGATECTLOVR 0x000C
172#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U 178#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U
173#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0 179#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0
@@ -199,6 +205,9 @@
199#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x000C0000U 205#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x000C0000U
200#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 18 206#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 18
201#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SIGNED 0 207#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SIGNED 0
208#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_MASK 0x00300000U
209#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SHIFT 20
210#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SIGNED 0
202#define EUR_CR_POWER 0x001C 211#define EUR_CR_POWER 0x001C
203#define EUR_CR_POWER_PIPE_DISABLE_MASK 0x00000001U 212#define EUR_CR_POWER_PIPE_DISABLE_MASK 0x00000001U
204#define EUR_CR_POWER_PIPE_DISABLE_SHIFT 0 213#define EUR_CR_POWER_PIPE_DISABLE_SHIFT 0
@@ -671,118 +680,6 @@
671#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU 680#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU
672#define EUR_CR_TIMER_VALUE_SHIFT 0 681#define EUR_CR_TIMER_VALUE_SHIFT 0
673#define EUR_CR_TIMER_VALUE_SIGNED 0 682#define EUR_CR_TIMER_VALUE_SIGNED 0
674#define EUR_CR_USE_CODE_BASE_0 0x0A0C
675#define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x03FFFFFFU
676#define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0
677#define EUR_CR_USE_CODE_BASE_ADDR_00_SIGNED 0
678#define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x0C000000U
679#define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 26
680#define EUR_CR_USE_CODE_BASE_DM_00_SIGNED 0
681#define EUR_CR_USE_CODE_BASE_1 0x0A10
682#define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x03FFFFFFU
683#define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0
684#define EUR_CR_USE_CODE_BASE_ADDR_01_SIGNED 0
685#define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x0C000000U
686#define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 26
687#define EUR_CR_USE_CODE_BASE_DM_01_SIGNED 0
688#define EUR_CR_USE_CODE_BASE_2 0x0A14
689#define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x03FFFFFFU
690#define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0
691#define EUR_CR_USE_CODE_BASE_ADDR_02_SIGNED 0
692#define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x0C000000U
693#define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 26
694#define EUR_CR_USE_CODE_BASE_DM_02_SIGNED 0
695#define EUR_CR_USE_CODE_BASE_3 0x0A18
696#define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x03FFFFFFU
697#define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0
698#define EUR_CR_USE_CODE_BASE_ADDR_03_SIGNED 0
699#define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x0C000000U
700#define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 26
701#define EUR_CR_USE_CODE_BASE_DM_03_SIGNED 0
702#define EUR_CR_USE_CODE_BASE_4 0x0A1C
703#define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x03FFFFFFU
704#define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0
705#define EUR_CR_USE_CODE_BASE_ADDR_04_SIGNED 0
706#define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x0C000000U
707#define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 26
708#define EUR_CR_USE_CODE_BASE_DM_04_SIGNED 0
709#define EUR_CR_USE_CODE_BASE_5 0x0A20
710#define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x03FFFFFFU
711#define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0
712#define EUR_CR_USE_CODE_BASE_ADDR_05_SIGNED 0
713#define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x0C000000U
714#define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 26
715#define EUR_CR_USE_CODE_BASE_DM_05_SIGNED 0
716#define EUR_CR_USE_CODE_BASE_6 0x0A24
717#define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x03FFFFFFU
718#define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0
719#define EUR_CR_USE_CODE_BASE_ADDR_06_SIGNED 0
720#define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x0C000000U
721#define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 26
722#define EUR_CR_USE_CODE_BASE_DM_06_SIGNED 0
723#define EUR_CR_USE_CODE_BASE_7 0x0A28
724#define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x03FFFFFFU
725#define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0
726#define EUR_CR_USE_CODE_BASE_ADDR_07_SIGNED 0
727#define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x0C000000U
728#define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 26
729#define EUR_CR_USE_CODE_BASE_DM_07_SIGNED 0
730#define EUR_CR_USE_CODE_BASE_8 0x0A2C
731#define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x03FFFFFFU
732#define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0
733#define EUR_CR_USE_CODE_BASE_ADDR_08_SIGNED 0
734#define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x0C000000U
735#define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 26
736#define EUR_CR_USE_CODE_BASE_DM_08_SIGNED 0
737#define EUR_CR_USE_CODE_BASE_9 0x0A30
738#define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x03FFFFFFU
739#define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0
740#define EUR_CR_USE_CODE_BASE_ADDR_09_SIGNED 0
741#define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x0C000000U
742#define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 26
743#define EUR_CR_USE_CODE_BASE_DM_09_SIGNED 0
744#define EUR_CR_USE_CODE_BASE_10 0x0A34
745#define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x03FFFFFFU
746#define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0
747#define EUR_CR_USE_CODE_BASE_ADDR_10_SIGNED 0
748#define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x0C000000U
749#define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 26
750#define EUR_CR_USE_CODE_BASE_DM_10_SIGNED 0
751#define EUR_CR_USE_CODE_BASE_11 0x0A38
752#define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x03FFFFFFU
753#define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0
754#define EUR_CR_USE_CODE_BASE_ADDR_11_SIGNED 0
755#define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x0C000000U
756#define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 26
757#define EUR_CR_USE_CODE_BASE_DM_11_SIGNED 0
758#define EUR_CR_USE_CODE_BASE_12 0x0A3C
759#define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x03FFFFFFU
760#define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0
761#define EUR_CR_USE_CODE_BASE_ADDR_12_SIGNED 0
762#define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x0C000000U
763#define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 26
764#define EUR_CR_USE_CODE_BASE_DM_12_SIGNED 0
765#define EUR_CR_USE_CODE_BASE_13 0x0A40
766#define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x03FFFFFFU
767#define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0
768#define EUR_CR_USE_CODE_BASE_ADDR_13_SIGNED 0
769#define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x0C000000U
770#define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 26
771#define EUR_CR_USE_CODE_BASE_DM_13_SIGNED 0
772#define EUR_CR_USE_CODE_BASE_14 0x0A44
773#define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x03FFFFFFU
774#define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0
775#define EUR_CR_USE_CODE_BASE_ADDR_14_SIGNED 0
776#define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x0C000000U
777#define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 26
778#define EUR_CR_USE_CODE_BASE_DM_14_SIGNED 0
779#define EUR_CR_USE_CODE_BASE_15 0x0A48
780#define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x03FFFFFFU
781#define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0
782#define EUR_CR_USE_CODE_BASE_ADDR_15_SIGNED 0
783#define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x0C000000U
784#define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 26
785#define EUR_CR_USE_CODE_BASE_DM_15_SIGNED 0
786#define EUR_CR_EVENT_KICK1 0x0AB0 683#define EUR_CR_EVENT_KICK1 0x0AB0
787#define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU 684#define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU
788#define EUR_CR_EVENT_KICK1_NOW_SHIFT 0 685#define EUR_CR_EVENT_KICK1_NOW_SHIFT 0
@@ -1090,6 +987,19 @@
1090#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U 987#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U
1091#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1 988#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1
1092#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0 989#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0
990#define EUR_CR_BIF_MMU_CTRL 0x0CD0
991#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_MASK 0x00000001U
992#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SHIFT 0
993#define EUR_CR_BIF_MMU_CTRL_PREFETCHING_ON_SIGNED 0
994#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_MASK 0x00000006U
995#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT 1
996#define EUR_CR_BIF_MMU_CTRL_ADDR_HASH_MODE_SIGNED 0
997#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_MASK 0x00000008U
998#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SHIFT 3
999#define EUR_CR_BIF_MMU_CTRL_ENABLE_WRITE_BURST_COLLATE_SIGNED 0
1000#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK 0x00000010U
1001#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SHIFT 4
1002#define EUR_CR_BIF_MMU_CTRL_ENABLE_DC_TLB_SIGNED 0
1093#define EUR_CR_2D_BLIT_STATUS 0x0E04 1003#define EUR_CR_2D_BLIT_STATUS 0x0E04
1094#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU 1004#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU
1095#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0 1005#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0
@@ -1208,40 +1118,238 @@
1208#define EUR_CR_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U 1118#define EUR_CR_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U
1209#define EUR_CR_BREAKPOINT_READ_ADDRESS_SHIFT 4 1119#define EUR_CR_BREAKPOINT_READ_ADDRESS_SHIFT 4
1210#define EUR_CR_BREAKPOINT_READ_ADDRESS_SIGNED 0 1120#define EUR_CR_BREAKPOINT_READ_ADDRESS_SIGNED 0
1211#define EUR_CR_BREAKPOINT_TRAP 0x0F78 1121#define EUR_CR_PARTITION_BREAKPOINT_TRAP 0x0F78
1212#define EUR_CR_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U 1122#define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U
1213#define EUR_CR_BREAKPOINT_TRAP_CONTINUE_SHIFT 1 1123#define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_SHIFT 1
1214#define EUR_CR_BREAKPOINT_TRAP_CONTINUE_SIGNED 0 1124#define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_SIGNED 0
1215#define EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U 1125#define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U
1216#define EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 1126#define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0
1217#define EUR_CR_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 1127#define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0
1218#define EUR_CR_BREAKPOINT 0x0F7C 1128#define EUR_CR_PARTITION_BREAKPOINT 0x0F7C
1219#define EUR_CR_BREAKPOINT_UNTRAPPED_MASK 0x00000008U 1129#define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_MASK 0x000003C0U
1220#define EUR_CR_BREAKPOINT_UNTRAPPED_SHIFT 3 1130#define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_SHIFT 6
1221#define EUR_CR_BREAKPOINT_UNTRAPPED_SIGNED 0 1131#define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_SIGNED 0
1222#define EUR_CR_BREAKPOINT_TRAPPED_MASK 0x00000004U 1132#define EUR_CR_PARTITION_BREAKPOINT_ID_MASK 0x00000030U
1223#define EUR_CR_BREAKPOINT_TRAPPED_SHIFT 2 1133#define EUR_CR_PARTITION_BREAKPOINT_ID_SHIFT 4
1224#define EUR_CR_BREAKPOINT_TRAPPED_SIGNED 0 1134#define EUR_CR_PARTITION_BREAKPOINT_ID_SIGNED 0
1225#define EUR_CR_BREAKPOINT_TRAP_INFO0 0x0F80 1135#define EUR_CR_PARTITION_BREAKPOINT_UNTRAPPED_MASK 0x00000008U
1226#define EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U 1136#define EUR_CR_PARTITION_BREAKPOINT_UNTRAPPED_SHIFT 3
1227#define EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4 1137#define EUR_CR_PARTITION_BREAKPOINT_UNTRAPPED_SIGNED 0
1228#define EUR_CR_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0 1138#define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_MASK 0x00000004U
1229#define EUR_CR_BREAKPOINT_TRAP_INFO1 0x0F84 1139#define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_SHIFT 2
1230#define EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U 1140#define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_SIGNED 0
1231#define EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10 1141#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0 0x0F80
1232#define EUR_CR_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0 1142#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U
1233#define EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U 1143#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4
1234#define EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8 1144#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0
1235#define EUR_CR_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0 1145#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1 0x0F84
1236#define EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U 1146#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U
1237#define EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3 1147#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10
1238#define EUR_CR_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0 1148#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0
1239#define EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U 1149#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U
1240#define EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1 1150#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8
1241#define EUR_CR_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0 1151#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0
1242#define EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U 1152#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U
1243#define EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0 1153#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3
1244#define EUR_CR_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0 1154#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0
1155#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U
1156#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1
1157#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0
1158#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U
1159#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0
1160#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0
1161#define EUR_CR_USE_CODE_BASE_0 0x0A0C
1162#define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x03FFFFFFU
1163#define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0
1164#define EUR_CR_USE_CODE_BASE_ADDR_00_SIGNED 0
1165#define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x0C000000U
1166#define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 26
1167#define EUR_CR_USE_CODE_BASE_DM_00_SIGNED 0
1168#define EUR_CR_USE_CODE_BASE_1 0x0A10
1169#define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x03FFFFFFU
1170#define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0
1171#define EUR_CR_USE_CODE_BASE_ADDR_01_SIGNED 0
1172#define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x0C000000U
1173#define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 26
1174#define EUR_CR_USE_CODE_BASE_DM_01_SIGNED 0
1175#define EUR_CR_USE_CODE_BASE_2 0x0A14
1176#define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x03FFFFFFU
1177#define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0
1178#define EUR_CR_USE_CODE_BASE_ADDR_02_SIGNED 0
1179#define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x0C000000U
1180#define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 26
1181#define EUR_CR_USE_CODE_BASE_DM_02_SIGNED 0
1182#define EUR_CR_USE_CODE_BASE_3 0x0A18
1183#define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x03FFFFFFU
1184#define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0
1185#define EUR_CR_USE_CODE_BASE_ADDR_03_SIGNED 0
1186#define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x0C000000U
1187#define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 26
1188#define EUR_CR_USE_CODE_BASE_DM_03_SIGNED 0
1189#define EUR_CR_USE_CODE_BASE_4 0x0A1C
1190#define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x03FFFFFFU
1191#define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0
1192#define EUR_CR_USE_CODE_BASE_ADDR_04_SIGNED 0
1193#define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x0C000000U
1194#define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 26
1195#define EUR_CR_USE_CODE_BASE_DM_04_SIGNED 0
1196#define EUR_CR_USE_CODE_BASE_5 0x0A20
1197#define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x03FFFFFFU
1198#define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0
1199#define EUR_CR_USE_CODE_BASE_ADDR_05_SIGNED 0
1200#define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x0C000000U
1201#define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 26
1202#define EUR_CR_USE_CODE_BASE_DM_05_SIGNED 0
1203#define EUR_CR_USE_CODE_BASE_6 0x0A24
1204#define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x03FFFFFFU
1205#define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0
1206#define EUR_CR_USE_CODE_BASE_ADDR_06_SIGNED 0
1207#define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x0C000000U
1208#define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 26
1209#define EUR_CR_USE_CODE_BASE_DM_06_SIGNED 0
1210#define EUR_CR_USE_CODE_BASE_7 0x0A28
1211#define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x03FFFFFFU
1212#define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0
1213#define EUR_CR_USE_CODE_BASE_ADDR_07_SIGNED 0
1214#define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x0C000000U
1215#define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 26
1216#define EUR_CR_USE_CODE_BASE_DM_07_SIGNED 0
1217#define EUR_CR_USE_CODE_BASE_8 0x0A2C
1218#define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x03FFFFFFU
1219#define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0
1220#define EUR_CR_USE_CODE_BASE_ADDR_08_SIGNED 0
1221#define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x0C000000U
1222#define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 26
1223#define EUR_CR_USE_CODE_BASE_DM_08_SIGNED 0
1224#define EUR_CR_USE_CODE_BASE_9 0x0A30
1225#define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x03FFFFFFU
1226#define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0
1227#define EUR_CR_USE_CODE_BASE_ADDR_09_SIGNED 0
1228#define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x0C000000U
1229#define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 26
1230#define EUR_CR_USE_CODE_BASE_DM_09_SIGNED 0
1231#define EUR_CR_USE_CODE_BASE_10 0x0A34
1232#define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x03FFFFFFU
1233#define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0
1234#define EUR_CR_USE_CODE_BASE_ADDR_10_SIGNED 0
1235#define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x0C000000U
1236#define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 26
1237#define EUR_CR_USE_CODE_BASE_DM_10_SIGNED 0
1238#define EUR_CR_USE_CODE_BASE_11 0x0A38
1239#define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x03FFFFFFU
1240#define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0
1241#define EUR_CR_USE_CODE_BASE_ADDR_11_SIGNED 0
1242#define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x0C000000U
1243#define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 26
1244#define EUR_CR_USE_CODE_BASE_DM_11_SIGNED 0
1245#define EUR_CR_USE_CODE_BASE_12 0x0A3C
1246#define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x03FFFFFFU
1247#define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0
1248#define EUR_CR_USE_CODE_BASE_ADDR_12_SIGNED 0
1249#define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x0C000000U
1250#define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 26
1251#define EUR_CR_USE_CODE_BASE_DM_12_SIGNED 0
1252#define EUR_CR_USE_CODE_BASE_13 0x0A40
1253#define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x03FFFFFFU
1254#define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0
1255#define EUR_CR_USE_CODE_BASE_ADDR_13_SIGNED 0
1256#define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x0C000000U
1257#define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 26
1258#define EUR_CR_USE_CODE_BASE_DM_13_SIGNED 0
1259#define EUR_CR_USE_CODE_BASE_14 0x0A44
1260#define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x03FFFFFFU
1261#define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0
1262#define EUR_CR_USE_CODE_BASE_ADDR_14_SIGNED 0
1263#define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x0C000000U
1264#define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 26
1265#define EUR_CR_USE_CODE_BASE_DM_14_SIGNED 0
1266#define EUR_CR_USE_CODE_BASE_15 0x0A48
1267#define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x03FFFFFFU
1268#define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0
1269#define EUR_CR_USE_CODE_BASE_ADDR_15_SIGNED 0
1270#define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x0C000000U
1271#define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 26
1272#define EUR_CR_USE_CODE_BASE_DM_15_SIGNED 0
1273#define EUR_CR_PIPE0_BREAKPOINT_TRAP 0x0F88
1274#define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U
1275#define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_SHIFT 1
1276#define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_SIGNED 0
1277#define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U
1278#define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0
1279#define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0
1280#define EUR_CR_PIPE0_BREAKPOINT 0x0F8C
1281#define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_MASK 0x000003C0U
1282#define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_SHIFT 6
1283#define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_SIGNED 0
1284#define EUR_CR_PIPE0_BREAKPOINT_ID_MASK 0x00000030U
1285#define EUR_CR_PIPE0_BREAKPOINT_ID_SHIFT 4
1286#define EUR_CR_PIPE0_BREAKPOINT_ID_SIGNED 0
1287#define EUR_CR_PIPE0_BREAKPOINT_UNTRAPPED_MASK 0x00000008U
1288#define EUR_CR_PIPE0_BREAKPOINT_UNTRAPPED_SHIFT 3
1289#define EUR_CR_PIPE0_BREAKPOINT_UNTRAPPED_SIGNED 0
1290#define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_MASK 0x00000004U
1291#define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_SHIFT 2
1292#define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_SIGNED 0
1293#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0 0x0F90
1294#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U
1295#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4
1296#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0
1297#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1 0x0F94
1298#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U
1299#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10
1300#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0
1301#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U
1302#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8
1303#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0
1304#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U
1305#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3
1306#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0
1307#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U
1308#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1
1309#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0
1310#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U
1311#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0
1312#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0
1313#define EUR_CR_PIPE1_BREAKPOINT_TRAP 0x0F98
1314#define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U
1315#define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_SHIFT 1
1316#define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_SIGNED 0
1317#define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U
1318#define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0
1319#define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0
1320#define EUR_CR_PIPE1_BREAKPOINT 0x0F9C
1321#define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_MASK 0x000003C0U
1322#define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_SHIFT 6
1323#define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_SIGNED 0
1324#define EUR_CR_PIPE1_BREAKPOINT_ID_MASK 0x00000030U
1325#define EUR_CR_PIPE1_BREAKPOINT_ID_SHIFT 4
1326#define EUR_CR_PIPE1_BREAKPOINT_ID_SIGNED 0
1327#define EUR_CR_PIPE1_BREAKPOINT_UNTRAPPED_MASK 0x00000008U
1328#define EUR_CR_PIPE1_BREAKPOINT_UNTRAPPED_SHIFT 3
1329#define EUR_CR_PIPE1_BREAKPOINT_UNTRAPPED_SIGNED 0
1330#define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_MASK 0x00000004U
1331#define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_SHIFT 2
1332#define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_SIGNED 0
1333#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0 0x0FA0
1334#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U
1335#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4
1336#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0
1337#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1 0x0FA4
1338#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U
1339#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10
1340#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0
1341#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U
1342#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8
1343#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0
1344#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U
1345#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3
1346#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0
1347#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U
1348#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1
1349#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0
1350#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U
1351#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0
1352#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0
1245#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X))) 1353#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X)))
1246#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x03FFFFFFU 1354#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x03FFFFFFU
1247#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0 1355#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0
diff --git a/drivers/gpu/pvr/sgx544defs.h b/drivers/gpu/pvr/sgx544defs.h
new file mode 100644
index 00000000000..eb9268d4ecc
--- /dev/null
+++ b/drivers/gpu/pvr/sgx544defs.h
@@ -0,0 +1,1351 @@
1/**********************************************************************
2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 *
25 ******************************************************************************/
26
27#ifndef _SGX544DEFS_KM_H_
28#define _SGX544DEFS_KM_H_
29
30#define EUR_CR_CLKGATECTL 0x0000
31#define EUR_CR_CLKGATECTL_ISP_CLKG_MASK 0x00000003U
32#define EUR_CR_CLKGATECTL_ISP_CLKG_SHIFT 0
33#define EUR_CR_CLKGATECTL_ISP_CLKG_SIGNED 0
34#define EUR_CR_CLKGATECTL_ISP2_CLKG_MASK 0x0000000CU
35#define EUR_CR_CLKGATECTL_ISP2_CLKG_SHIFT 2
36#define EUR_CR_CLKGATECTL_ISP2_CLKG_SIGNED 0
37#define EUR_CR_CLKGATECTL_TSP_CLKG_MASK 0x00000030U
38#define EUR_CR_CLKGATECTL_TSP_CLKG_SHIFT 4
39#define EUR_CR_CLKGATECTL_TSP_CLKG_SIGNED 0
40#define EUR_CR_CLKGATECTL_TE_CLKG_MASK 0x000000C0U
41#define EUR_CR_CLKGATECTL_TE_CLKG_SHIFT 6
42#define EUR_CR_CLKGATECTL_TE_CLKG_SIGNED 0
43#define EUR_CR_CLKGATECTL_MTE_CLKG_MASK 0x00000300U
44#define EUR_CR_CLKGATECTL_MTE_CLKG_SHIFT 8
45#define EUR_CR_CLKGATECTL_MTE_CLKG_SIGNED 0
46#define EUR_CR_CLKGATECTL_DPM_CLKG_MASK 0x00000C00U
47#define EUR_CR_CLKGATECTL_DPM_CLKG_SHIFT 10
48#define EUR_CR_CLKGATECTL_DPM_CLKG_SIGNED 0
49#define EUR_CR_CLKGATECTL_VDM_CLKG_MASK 0x00003000U
50#define EUR_CR_CLKGATECTL_VDM_CLKG_SHIFT 12
51#define EUR_CR_CLKGATECTL_VDM_CLKG_SIGNED 0
52#define EUR_CR_CLKGATECTL_PDS_CLKG_MASK 0x0000C000U
53#define EUR_CR_CLKGATECTL_PDS_CLKG_SHIFT 14
54#define EUR_CR_CLKGATECTL_PDS_CLKG_SIGNED 0
55#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_MASK 0x00030000U
56#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SHIFT 16
57#define EUR_CR_CLKGATECTL_IDXFIFO_CLKG_SIGNED 0
58#define EUR_CR_CLKGATECTL_TA_CLKG_MASK 0x000C0000U
59#define EUR_CR_CLKGATECTL_TA_CLKG_SHIFT 18
60#define EUR_CR_CLKGATECTL_TA_CLKG_SIGNED 0
61#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_MASK 0x00300000U
62#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SHIFT 20
63#define EUR_CR_CLKGATECTL_BIF_CORE_CLKG_SIGNED 0
64#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_MASK 0x01000000U
65#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SHIFT 24
66#define EUR_CR_CLKGATECTL_AUTO_MAN_REG_SIGNED 0
67#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_MASK 0x10000000U
68#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SHIFT 28
69#define EUR_CR_CLKGATECTL_SYSTEM_CLKG_SIGNED 0
70#define EUR_CR_CLKGATECTL2 0x0004
71#define EUR_CR_CLKGATECTL2_PBE_CLKG_MASK 0x00000003U
72#define EUR_CR_CLKGATECTL2_PBE_CLKG_SHIFT 0
73#define EUR_CR_CLKGATECTL2_PBE_CLKG_SIGNED 0
74#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_MASK 0x0000000CU
75#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SHIFT 2
76#define EUR_CR_CLKGATECTL2_TCU_L2_CLKG_SIGNED 0
77#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_MASK 0x00000030U
78#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SHIFT 4
79#define EUR_CR_CLKGATECTL2_UCACHEL2_CLKG_SIGNED 0
80#define EUR_CR_CLKGATECTL2_USE0_CLKG_MASK 0x000000C0U
81#define EUR_CR_CLKGATECTL2_USE0_CLKG_SHIFT 6
82#define EUR_CR_CLKGATECTL2_USE0_CLKG_SIGNED 0
83#define EUR_CR_CLKGATECTL2_ITR0_CLKG_MASK 0x00000300U
84#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SHIFT 8
85#define EUR_CR_CLKGATECTL2_ITR0_CLKG_SIGNED 0
86#define EUR_CR_CLKGATECTL2_TEX0_CLKG_MASK 0x00000C00U
87#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SHIFT 10
88#define EUR_CR_CLKGATECTL2_TEX0_CLKG_SIGNED 0
89#define EUR_CR_CLKGATECTL2_USE1_CLKG_MASK 0x0000C000U
90#define EUR_CR_CLKGATECTL2_USE1_CLKG_SHIFT 14
91#define EUR_CR_CLKGATECTL2_USE1_CLKG_SIGNED 0
92#define EUR_CR_CLKGATECTL2_ITR1_CLKG_MASK 0x00030000U
93#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SHIFT 16
94#define EUR_CR_CLKGATECTL2_ITR1_CLKG_SIGNED 0
95#define EUR_CR_CLKGATECTL2_TEX1_CLKG_MASK 0x000C0000U
96#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SHIFT 18
97#define EUR_CR_CLKGATECTL2_TEX1_CLKG_SIGNED 0
98#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_MASK 0x00C00000U
99#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SHIFT 22
100#define EUR_CR_CLKGATECTL2_DCU_L2_CLKG_SIGNED 0
101#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_MASK 0x03000000U
102#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SHIFT 24
103#define EUR_CR_CLKGATECTL2_DCU1_L0L1_CLKG_SIGNED 0
104#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_MASK 0x0C000000U
105#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SHIFT 26
106#define EUR_CR_CLKGATECTL2_DCU0_L0L1_CLKG_SIGNED 0
107#define EUR_CR_CLKGATESTATUS 0x0008
108#define EUR_CR_CLKGATESTATUS_ISP_CLKS_MASK 0x00000001U
109#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SHIFT 0
110#define EUR_CR_CLKGATESTATUS_ISP_CLKS_SIGNED 0
111#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_MASK 0x00000002U
112#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SHIFT 1
113#define EUR_CR_CLKGATESTATUS_ISP2_CLKS_SIGNED 0
114#define EUR_CR_CLKGATESTATUS_TSP_CLKS_MASK 0x00000004U
115#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SHIFT 2
116#define EUR_CR_CLKGATESTATUS_TSP_CLKS_SIGNED 0
117#define EUR_CR_CLKGATESTATUS_TE_CLKS_MASK 0x00000008U
118#define EUR_CR_CLKGATESTATUS_TE_CLKS_SHIFT 3
119#define EUR_CR_CLKGATESTATUS_TE_CLKS_SIGNED 0
120#define EUR_CR_CLKGATESTATUS_MTE_CLKS_MASK 0x00000010U
121#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SHIFT 4
122#define EUR_CR_CLKGATESTATUS_MTE_CLKS_SIGNED 0
123#define EUR_CR_CLKGATESTATUS_DPM_CLKS_MASK 0x00000020U
124#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SHIFT 5
125#define EUR_CR_CLKGATESTATUS_DPM_CLKS_SIGNED 0
126#define EUR_CR_CLKGATESTATUS_VDM_CLKS_MASK 0x00000040U
127#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SHIFT 6
128#define EUR_CR_CLKGATESTATUS_VDM_CLKS_SIGNED 0
129#define EUR_CR_CLKGATESTATUS_PDS_CLKS_MASK 0x00000080U
130#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SHIFT 7
131#define EUR_CR_CLKGATESTATUS_PDS_CLKS_SIGNED 0
132#define EUR_CR_CLKGATESTATUS_PBE_CLKS_MASK 0x00000100U
133#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SHIFT 8
134#define EUR_CR_CLKGATESTATUS_PBE_CLKS_SIGNED 0
135#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_MASK 0x00000200U
136#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SHIFT 9
137#define EUR_CR_CLKGATESTATUS_TCU_L2_CLKS_SIGNED 0
138#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_MASK 0x00000400U
139#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SHIFT 10
140#define EUR_CR_CLKGATESTATUS_UCACHEL2_CLKS_SIGNED 0
141#define EUR_CR_CLKGATESTATUS_USE0_CLKS_MASK 0x00000800U
142#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SHIFT 11
143#define EUR_CR_CLKGATESTATUS_USE0_CLKS_SIGNED 0
144#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_MASK 0x00001000U
145#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SHIFT 12
146#define EUR_CR_CLKGATESTATUS_ITR0_CLKS_SIGNED 0
147#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_MASK 0x00002000U
148#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SHIFT 13
149#define EUR_CR_CLKGATESTATUS_TEX0_CLKS_SIGNED 0
150#define EUR_CR_CLKGATESTATUS_USE1_CLKS_MASK 0x00008000U
151#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SHIFT 15
152#define EUR_CR_CLKGATESTATUS_USE1_CLKS_SIGNED 0
153#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_MASK 0x00010000U
154#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SHIFT 16
155#define EUR_CR_CLKGATESTATUS_ITR1_CLKS_SIGNED 0
156#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_MASK 0x00020000U
157#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SHIFT 17
158#define EUR_CR_CLKGATESTATUS_TEX1_CLKS_SIGNED 0
159#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_MASK 0x00080000U
160#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SHIFT 19
161#define EUR_CR_CLKGATESTATUS_IDXFIFO_CLKS_SIGNED 0
162#define EUR_CR_CLKGATESTATUS_TA_CLKS_MASK 0x00100000U
163#define EUR_CR_CLKGATESTATUS_TA_CLKS_SHIFT 20
164#define EUR_CR_CLKGATESTATUS_TA_CLKS_SIGNED 0
165#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_MASK 0x00200000U
166#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SHIFT 21
167#define EUR_CR_CLKGATESTATUS_DCU_L2_CLKS_SIGNED 0
168#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_MASK 0x00400000U
169#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SHIFT 22
170#define EUR_CR_CLKGATESTATUS_DCU0_L0L1_CLKS_SIGNED 0
171#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_MASK 0x00800000U
172#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SHIFT 23
173#define EUR_CR_CLKGATESTATUS_DCU1_L0L1_CLKS_SIGNED 0
174#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_MASK 0x01000000U
175#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SHIFT 24
176#define EUR_CR_CLKGATESTATUS_BIF_CORE_CLKS_SIGNED 0
177#define EUR_CR_CLKGATECTLOVR 0x000C
178#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_MASK 0x00000003U
179#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SHIFT 0
180#define EUR_CR_CLKGATECTLOVR_ISP_CLKO_SIGNED 0
181#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_MASK 0x0000000CU
182#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SHIFT 2
183#define EUR_CR_CLKGATECTLOVR_ISP2_CLKO_SIGNED 0
184#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_MASK 0x00000030U
185#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SHIFT 4
186#define EUR_CR_CLKGATECTLOVR_TSP_CLKO_SIGNED 0
187#define EUR_CR_CLKGATECTLOVR_TE_CLKO_MASK 0x000000C0U
188#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SHIFT 6
189#define EUR_CR_CLKGATECTLOVR_TE_CLKO_SIGNED 0
190#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_MASK 0x00000300U
191#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SHIFT 8
192#define EUR_CR_CLKGATECTLOVR_MTE_CLKO_SIGNED 0
193#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_MASK 0x00000C00U
194#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SHIFT 10
195#define EUR_CR_CLKGATECTLOVR_DPM_CLKO_SIGNED 0
196#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_MASK 0x00003000U
197#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SHIFT 12
198#define EUR_CR_CLKGATECTLOVR_VDM_CLKO_SIGNED 0
199#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_MASK 0x0000C000U
200#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SHIFT 14
201#define EUR_CR_CLKGATECTLOVR_PDS_CLKO_SIGNED 0
202#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_MASK 0x00030000U
203#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SHIFT 16
204#define EUR_CR_CLKGATECTLOVR_IDXFIFO_CLKO_SIGNED 0
205#define EUR_CR_CLKGATECTLOVR_TA_CLKO_MASK 0x000C0000U
206#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SHIFT 18
207#define EUR_CR_CLKGATECTLOVR_TA_CLKO_SIGNED 0
208#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_MASK 0x00300000U
209#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SHIFT 20
210#define EUR_CR_CLKGATECTLOVR_BIF_CORE_CLKO_SIGNED 0
211#define EUR_CR_POWER 0x001C
212#define EUR_CR_POWER_PIPE_DISABLE_MASK 0x00000001U
213#define EUR_CR_POWER_PIPE_DISABLE_SHIFT 0
214#define EUR_CR_POWER_PIPE_DISABLE_SIGNED 0
215#define EUR_CR_CORE_ID 0x0020
216#define EUR_CR_CORE_ID_CONFIG_MULTI_MASK 0x00000001U
217#define EUR_CR_CORE_ID_CONFIG_MULTI_SHIFT 0
218#define EUR_CR_CORE_ID_CONFIG_MULTI_SIGNED 0
219#define EUR_CR_CORE_ID_CONFIG_BASE_MASK 0x00000002U
220#define EUR_CR_CORE_ID_CONFIG_BASE_SHIFT 1
221#define EUR_CR_CORE_ID_CONFIG_BASE_SIGNED 0
222#define EUR_CR_CORE_ID_CONFIG_MASK 0x000000FCU
223#define EUR_CR_CORE_ID_CONFIG_SHIFT 2
224#define EUR_CR_CORE_ID_CONFIG_SIGNED 0
225#define EUR_CR_CORE_ID_CONFIG_CORES_MASK 0x00000F00U
226#define EUR_CR_CORE_ID_CONFIG_CORES_SHIFT 8
227#define EUR_CR_CORE_ID_CONFIG_CORES_SIGNED 0
228#define EUR_CR_CORE_ID_CONFIG_SLC_MASK 0x0000F000U
229#define EUR_CR_CORE_ID_CONFIG_SLC_SHIFT 12
230#define EUR_CR_CORE_ID_CONFIG_SLC_SIGNED 0
231#define EUR_CR_CORE_ID_ID_MASK 0xFFFF0000U
232#define EUR_CR_CORE_ID_ID_SHIFT 16
233#define EUR_CR_CORE_ID_ID_SIGNED 0
234#define EUR_CR_CORE_REVISION 0x0024
235#define EUR_CR_CORE_REVISION_MAINTENANCE_MASK 0x000000FFU
236#define EUR_CR_CORE_REVISION_MAINTENANCE_SHIFT 0
237#define EUR_CR_CORE_REVISION_MAINTENANCE_SIGNED 0
238#define EUR_CR_CORE_REVISION_MINOR_MASK 0x0000FF00U
239#define EUR_CR_CORE_REVISION_MINOR_SHIFT 8
240#define EUR_CR_CORE_REVISION_MINOR_SIGNED 0
241#define EUR_CR_CORE_REVISION_MAJOR_MASK 0x00FF0000U
242#define EUR_CR_CORE_REVISION_MAJOR_SHIFT 16
243#define EUR_CR_CORE_REVISION_MAJOR_SIGNED 0
244#define EUR_CR_CORE_REVISION_DESIGNER_MASK 0xFF000000U
245#define EUR_CR_CORE_REVISION_DESIGNER_SHIFT 24
246#define EUR_CR_CORE_REVISION_DESIGNER_SIGNED 0
247#define EUR_CR_DESIGNER_REV_FIELD1 0x0028
248#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_MASK 0xFFFFFFFFU
249#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SHIFT 0
250#define EUR_CR_DESIGNER_REV_FIELD1_DESIGNER_REV_FIELD1_SIGNED 0
251#define EUR_CR_DESIGNER_REV_FIELD2 0x002C
252#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_MASK 0xFFFFFFFFU
253#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SHIFT 0
254#define EUR_CR_DESIGNER_REV_FIELD2_DESIGNER_REV_FIELD2_SIGNED 0
255#define EUR_CR_SOFT_RESET 0x0080
256#define EUR_CR_SOFT_RESET_BIF_RESET_MASK 0x00000001U
257#define EUR_CR_SOFT_RESET_BIF_RESET_SHIFT 0
258#define EUR_CR_SOFT_RESET_BIF_RESET_SIGNED 0
259#define EUR_CR_SOFT_RESET_VDM_RESET_MASK 0x00000002U
260#define EUR_CR_SOFT_RESET_VDM_RESET_SHIFT 1
261#define EUR_CR_SOFT_RESET_VDM_RESET_SIGNED 0
262#define EUR_CR_SOFT_RESET_DPM_RESET_MASK 0x00000004U
263#define EUR_CR_SOFT_RESET_DPM_RESET_SHIFT 2
264#define EUR_CR_SOFT_RESET_DPM_RESET_SIGNED 0
265#define EUR_CR_SOFT_RESET_TE_RESET_MASK 0x00000008U
266#define EUR_CR_SOFT_RESET_TE_RESET_SHIFT 3
267#define EUR_CR_SOFT_RESET_TE_RESET_SIGNED 0
268#define EUR_CR_SOFT_RESET_MTE_RESET_MASK 0x00000010U
269#define EUR_CR_SOFT_RESET_MTE_RESET_SHIFT 4
270#define EUR_CR_SOFT_RESET_MTE_RESET_SIGNED 0
271#define EUR_CR_SOFT_RESET_ISP_RESET_MASK 0x00000020U
272#define EUR_CR_SOFT_RESET_ISP_RESET_SHIFT 5
273#define EUR_CR_SOFT_RESET_ISP_RESET_SIGNED 0
274#define EUR_CR_SOFT_RESET_ISP2_RESET_MASK 0x00000040U
275#define EUR_CR_SOFT_RESET_ISP2_RESET_SHIFT 6
276#define EUR_CR_SOFT_RESET_ISP2_RESET_SIGNED 0
277#define EUR_CR_SOFT_RESET_TSP_RESET_MASK 0x00000080U
278#define EUR_CR_SOFT_RESET_TSP_RESET_SHIFT 7
279#define EUR_CR_SOFT_RESET_TSP_RESET_SIGNED 0
280#define EUR_CR_SOFT_RESET_PDS_RESET_MASK 0x00000100U
281#define EUR_CR_SOFT_RESET_PDS_RESET_SHIFT 8
282#define EUR_CR_SOFT_RESET_PDS_RESET_SIGNED 0
283#define EUR_CR_SOFT_RESET_PBE_RESET_MASK 0x00000200U
284#define EUR_CR_SOFT_RESET_PBE_RESET_SHIFT 9
285#define EUR_CR_SOFT_RESET_PBE_RESET_SIGNED 0
286#define EUR_CR_SOFT_RESET_TCU_L2_RESET_MASK 0x00000400U
287#define EUR_CR_SOFT_RESET_TCU_L2_RESET_SHIFT 10
288#define EUR_CR_SOFT_RESET_TCU_L2_RESET_SIGNED 0
289#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_MASK 0x00000800U
290#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SHIFT 11
291#define EUR_CR_SOFT_RESET_UCACHEL2_RESET_SIGNED 0
292#define EUR_CR_SOFT_RESET_ITR_RESET_MASK 0x00002000U
293#define EUR_CR_SOFT_RESET_ITR_RESET_SHIFT 13
294#define EUR_CR_SOFT_RESET_ITR_RESET_SIGNED 0
295#define EUR_CR_SOFT_RESET_TEX_RESET_MASK 0x00004000U
296#define EUR_CR_SOFT_RESET_TEX_RESET_SHIFT 14
297#define EUR_CR_SOFT_RESET_TEX_RESET_SIGNED 0
298#define EUR_CR_SOFT_RESET_USE_RESET_MASK 0x00008000U
299#define EUR_CR_SOFT_RESET_USE_RESET_SHIFT 15
300#define EUR_CR_SOFT_RESET_USE_RESET_SIGNED 0
301#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_MASK 0x00010000U
302#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SHIFT 16
303#define EUR_CR_SOFT_RESET_IDXFIFO_RESET_SIGNED 0
304#define EUR_CR_SOFT_RESET_TA_RESET_MASK 0x00020000U
305#define EUR_CR_SOFT_RESET_TA_RESET_SHIFT 17
306#define EUR_CR_SOFT_RESET_TA_RESET_SIGNED 0
307#define EUR_CR_SOFT_RESET_DCU_L2_RESET_MASK 0x00040000U
308#define EUR_CR_SOFT_RESET_DCU_L2_RESET_SHIFT 18
309#define EUR_CR_SOFT_RESET_DCU_L2_RESET_SIGNED 0
310#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_MASK 0x00080000U
311#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SHIFT 19
312#define EUR_CR_SOFT_RESET_DCU_L0L1_RESET_SIGNED 0
313#define EUR_CR_EVENT_HOST_ENABLE2 0x0110
314#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U
315#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11
316#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0
317#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U
318#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SHIFT 10
319#define EUR_CR_EVENT_HOST_ENABLE2_DATA_BREAKPOINT_TRAPPED_SIGNED 0
320#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_MASK 0x00000200U
321#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SHIFT 9
322#define EUR_CR_EVENT_HOST_ENABLE2_MTE_CONTEXT_DRAINED_SIGNED 0
323#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U
324#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SHIFT 8
325#define EUR_CR_EVENT_HOST_ENABLE2_ISP2_ZLS_CSW_FINISHED_SIGNED 0
326#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_MASK 0x00000080U
327#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SHIFT 7
328#define EUR_CR_EVENT_HOST_ENABLE2_DCU_INVALCOMPLETE_SIGNED 0
329#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_MASK 0x00000040U
330#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SHIFT 6
331#define EUR_CR_EVENT_HOST_ENABLE2_MTE_STATE_FLUSHED_SIGNED 0
332#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U
333#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5
334#define EUR_CR_EVENT_HOST_ENABLE2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0
335#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_MASK 0x00000010U
336#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SHIFT 4
337#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_TA_SIGNED 0
338#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_MASK 0x00000008U
339#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SHIFT 3
340#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_3D_SIGNED 0
341#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_MASK 0x00000004U
342#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SHIFT 2
343#define EUR_CR_EVENT_HOST_ENABLE2_TRIG_DL_SIGNED 0
344#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_MASK 0x00000002U
345#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SHIFT 1
346#define EUR_CR_EVENT_HOST_ENABLE2_DPM_3D_FREE_LOAD_SIGNED 0
347#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_MASK 0x00000001U
348#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SHIFT 0
349#define EUR_CR_EVENT_HOST_ENABLE2_DPM_TA_FREE_LOAD_SIGNED 0
350#define EUR_CR_EVENT_HOST_CLEAR2 0x0114
351#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U
352#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11
353#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0
354#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U
355#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SHIFT 10
356#define EUR_CR_EVENT_HOST_CLEAR2_DATA_BREAKPOINT_TRAPPED_SIGNED 0
357#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_MASK 0x00000200U
358#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SHIFT 9
359#define EUR_CR_EVENT_HOST_CLEAR2_MTE_CONTEXT_DRAINED_SIGNED 0
360#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U
361#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SHIFT 8
362#define EUR_CR_EVENT_HOST_CLEAR2_ISP2_ZLS_CSW_FINISHED_SIGNED 0
363#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_MASK 0x00000080U
364#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SHIFT 7
365#define EUR_CR_EVENT_HOST_CLEAR2_DCU_INVALCOMPLETE_SIGNED 0
366#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_MASK 0x00000040U
367#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SHIFT 6
368#define EUR_CR_EVENT_HOST_CLEAR2_MTE_STATE_FLUSHED_SIGNED 0
369#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U
370#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5
371#define EUR_CR_EVENT_HOST_CLEAR2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0
372#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_MASK 0x00000010U
373#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SHIFT 4
374#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_TA_SIGNED 0
375#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_MASK 0x00000008U
376#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SHIFT 3
377#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_3D_SIGNED 0
378#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_MASK 0x00000004U
379#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SHIFT 2
380#define EUR_CR_EVENT_HOST_CLEAR2_TRIG_DL_SIGNED 0
381#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_MASK 0x00000002U
382#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SHIFT 1
383#define EUR_CR_EVENT_HOST_CLEAR2_DPM_3D_FREE_LOAD_SIGNED 0
384#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_MASK 0x00000001U
385#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SHIFT 0
386#define EUR_CR_EVENT_HOST_CLEAR2_DPM_TA_FREE_LOAD_SIGNED 0
387#define EUR_CR_EVENT_STATUS2 0x0118
388#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_MASK 0x00000800U
389#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SHIFT 11
390#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_UNTRAPPED_SIGNED 0
391#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_MASK 0x00000400U
392#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SHIFT 10
393#define EUR_CR_EVENT_STATUS2_DATA_BREAKPOINT_TRAPPED_SIGNED 0
394#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_MASK 0x00000200U
395#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SHIFT 9
396#define EUR_CR_EVENT_STATUS2_MTE_CONTEXT_DRAINED_SIGNED 0
397#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_MASK 0x00000100U
398#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SHIFT 8
399#define EUR_CR_EVENT_STATUS2_ISP2_ZLS_CSW_FINISHED_SIGNED 0
400#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_MASK 0x00000080U
401#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SHIFT 7
402#define EUR_CR_EVENT_STATUS2_DCU_INVALCOMPLETE_SIGNED 0
403#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_MASK 0x00000040U
404#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SHIFT 6
405#define EUR_CR_EVENT_STATUS2_MTE_STATE_FLUSHED_SIGNED 0
406#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_MASK 0x00000020U
407#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SHIFT 5
408#define EUR_CR_EVENT_STATUS2_TE_RGNHDR_INIT_COMPLETE_SIGNED 0
409#define EUR_CR_EVENT_STATUS2_TRIG_TA_MASK 0x00000010U
410#define EUR_CR_EVENT_STATUS2_TRIG_TA_SHIFT 4
411#define EUR_CR_EVENT_STATUS2_TRIG_TA_SIGNED 0
412#define EUR_CR_EVENT_STATUS2_TRIG_3D_MASK 0x00000008U
413#define EUR_CR_EVENT_STATUS2_TRIG_3D_SHIFT 3
414#define EUR_CR_EVENT_STATUS2_TRIG_3D_SIGNED 0
415#define EUR_CR_EVENT_STATUS2_TRIG_DL_MASK 0x00000004U
416#define EUR_CR_EVENT_STATUS2_TRIG_DL_SHIFT 2
417#define EUR_CR_EVENT_STATUS2_TRIG_DL_SIGNED 0
418#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_MASK 0x00000002U
419#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SHIFT 1
420#define EUR_CR_EVENT_STATUS2_DPM_3D_FREE_LOAD_SIGNED 0
421#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_MASK 0x00000001U
422#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SHIFT 0
423#define EUR_CR_EVENT_STATUS2_DPM_TA_FREE_LOAD_SIGNED 0
424#define EUR_CR_EVENT_STATUS 0x012C
425#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_MASK 0x80000000U
426#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SHIFT 31
427#define EUR_CR_EVENT_STATUS_MASTER_INTERRUPT_SIGNED 0
428#define EUR_CR_EVENT_STATUS_TIMER_MASK 0x20000000U
429#define EUR_CR_EVENT_STATUS_TIMER_SHIFT 29
430#define EUR_CR_EVENT_STATUS_TIMER_SIGNED 0
431#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_MASK 0x10000000U
432#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SHIFT 28
433#define EUR_CR_EVENT_STATUS_TA_DPM_FAULT_SIGNED 0
434#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_MASK 0x04000000U
435#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SHIFT 26
436#define EUR_CR_EVENT_STATUS_TCU_INVALCOMPLETE_SIGNED 0
437#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
438#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
439#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0
440#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_MASK 0x01000000U
441#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SHIFT 24
442#define EUR_CR_EVENT_STATUS_DPM_TA_MEM_FREE_SIGNED 0
443#define EUR_CR_EVENT_STATUS_ISP_END_TILE_MASK 0x00800000U
444#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SHIFT 23
445#define EUR_CR_EVENT_STATUS_ISP_END_TILE_SIGNED 0
446#define EUR_CR_EVENT_STATUS_DPM_INITEND_MASK 0x00400000U
447#define EUR_CR_EVENT_STATUS_DPM_INITEND_SHIFT 22
448#define EUR_CR_EVENT_STATUS_DPM_INITEND_SIGNED 0
449#define EUR_CR_EVENT_STATUS_OTPM_LOADED_MASK 0x00200000U
450#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SHIFT 21
451#define EUR_CR_EVENT_STATUS_OTPM_LOADED_SIGNED 0
452#define EUR_CR_EVENT_STATUS_OTPM_INV_MASK 0x00100000U
453#define EUR_CR_EVENT_STATUS_OTPM_INV_SHIFT 20
454#define EUR_CR_EVENT_STATUS_OTPM_INV_SIGNED 0
455#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_MASK 0x00080000U
456#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SHIFT 19
457#define EUR_CR_EVENT_STATUS_OTPM_FLUSHED_SIGNED 0
458#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_MASK 0x00040000U
459#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SHIFT 18
460#define EUR_CR_EVENT_STATUS_PIXELBE_END_RENDER_SIGNED 0
461#define EUR_CR_EVENT_STATUS_BREAKPOINT_MASK 0x00008000U
462#define EUR_CR_EVENT_STATUS_BREAKPOINT_SHIFT 15
463#define EUR_CR_EVENT_STATUS_BREAKPOINT_SIGNED 0
464#define EUR_CR_EVENT_STATUS_SW_EVENT_MASK 0x00004000U
465#define EUR_CR_EVENT_STATUS_SW_EVENT_SHIFT 14
466#define EUR_CR_EVENT_STATUS_SW_EVENT_SIGNED 0
467#define EUR_CR_EVENT_STATUS_TA_FINISHED_MASK 0x00002000U
468#define EUR_CR_EVENT_STATUS_TA_FINISHED_SHIFT 13
469#define EUR_CR_EVENT_STATUS_TA_FINISHED_SIGNED 0
470#define EUR_CR_EVENT_STATUS_TA_TERMINATE_MASK 0x00001000U
471#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SHIFT 12
472#define EUR_CR_EVENT_STATUS_TA_TERMINATE_SIGNED 0
473#define EUR_CR_EVENT_STATUS_TPC_CLEAR_MASK 0x00000800U
474#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SHIFT 11
475#define EUR_CR_EVENT_STATUS_TPC_CLEAR_SIGNED 0
476#define EUR_CR_EVENT_STATUS_TPC_FLUSH_MASK 0x00000400U
477#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SHIFT 10
478#define EUR_CR_EVENT_STATUS_TPC_FLUSH_SIGNED 0
479#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_MASK 0x00000200U
480#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SHIFT 9
481#define EUR_CR_EVENT_STATUS_DPM_CONTROL_CLEAR_SIGNED 0
482#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_MASK 0x00000100U
483#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SHIFT 8
484#define EUR_CR_EVENT_STATUS_DPM_CONTROL_LOAD_SIGNED 0
485#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_MASK 0x00000080U
486#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SHIFT 7
487#define EUR_CR_EVENT_STATUS_DPM_CONTROL_STORE_SIGNED 0
488#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_MASK 0x00000040U
489#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SHIFT 6
490#define EUR_CR_EVENT_STATUS_DPM_STATE_CLEAR_SIGNED 0
491#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_MASK 0x00000020U
492#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SHIFT 5
493#define EUR_CR_EVENT_STATUS_DPM_STATE_LOAD_SIGNED 0
494#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_MASK 0x00000010U
495#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SHIFT 4
496#define EUR_CR_EVENT_STATUS_DPM_STATE_STORE_SIGNED 0
497#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
498#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SHIFT 3
499#define EUR_CR_EVENT_STATUS_DPM_REACHED_MEM_THRESH_SIGNED 0
500#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
501#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
502#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_GBL_SIGNED 0
503#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
504#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SHIFT 1
505#define EUR_CR_EVENT_STATUS_DPM_OUT_OF_MEMORY_MT_SIGNED 0
506#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_MASK 0x00000001U
507#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SHIFT 0
508#define EUR_CR_EVENT_STATUS_DPM_3D_MEM_FREE_SIGNED 0
509#define EUR_CR_EVENT_HOST_ENABLE 0x0130
510#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_MASK 0x80000000U
511#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SHIFT 31
512#define EUR_CR_EVENT_HOST_ENABLE_MASTER_INTERRUPT_SIGNED 0
513#define EUR_CR_EVENT_HOST_ENABLE_TIMER_MASK 0x20000000U
514#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SHIFT 29
515#define EUR_CR_EVENT_HOST_ENABLE_TIMER_SIGNED 0
516#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_MASK 0x10000000U
517#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SHIFT 28
518#define EUR_CR_EVENT_HOST_ENABLE_TA_DPM_FAULT_SIGNED 0
519#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_MASK 0x04000000U
520#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SHIFT 26
521#define EUR_CR_EVENT_HOST_ENABLE_TCU_INVALCOMPLETE_SIGNED 0
522#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
523#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
524#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0
525#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_MASK 0x01000000U
526#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SHIFT 24
527#define EUR_CR_EVENT_HOST_ENABLE_DPM_TA_MEM_FREE_SIGNED 0
528#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_MASK 0x00800000U
529#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SHIFT 23
530#define EUR_CR_EVENT_HOST_ENABLE_ISP_END_TILE_SIGNED 0
531#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_MASK 0x00400000U
532#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SHIFT 22
533#define EUR_CR_EVENT_HOST_ENABLE_DPM_INITEND_SIGNED 0
534#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_MASK 0x00200000U
535#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SHIFT 21
536#define EUR_CR_EVENT_HOST_ENABLE_OTPM_LOADED_SIGNED 0
537#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_MASK 0x00100000U
538#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SHIFT 20
539#define EUR_CR_EVENT_HOST_ENABLE_OTPM_INV_SIGNED 0
540#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_MASK 0x00080000U
541#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SHIFT 19
542#define EUR_CR_EVENT_HOST_ENABLE_OTPM_FLUSHED_SIGNED 0
543#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_MASK 0x00040000U
544#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SHIFT 18
545#define EUR_CR_EVENT_HOST_ENABLE_PIXELBE_END_RENDER_SIGNED 0
546#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_MASK 0x00008000U
547#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SHIFT 15
548#define EUR_CR_EVENT_HOST_ENABLE_BREAKPOINT_SIGNED 0
549#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_MASK 0x00004000U
550#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SHIFT 14
551#define EUR_CR_EVENT_HOST_ENABLE_SW_EVENT_SIGNED 0
552#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_MASK 0x00002000U
553#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SHIFT 13
554#define EUR_CR_EVENT_HOST_ENABLE_TA_FINISHED_SIGNED 0
555#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_MASK 0x00001000U
556#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SHIFT 12
557#define EUR_CR_EVENT_HOST_ENABLE_TA_TERMINATE_SIGNED 0
558#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_MASK 0x00000800U
559#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SHIFT 11
560#define EUR_CR_EVENT_HOST_ENABLE_TPC_CLEAR_SIGNED 0
561#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_MASK 0x00000400U
562#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SHIFT 10
563#define EUR_CR_EVENT_HOST_ENABLE_TPC_FLUSH_SIGNED 0
564#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_MASK 0x00000200U
565#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SHIFT 9
566#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_CLEAR_SIGNED 0
567#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_MASK 0x00000100U
568#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SHIFT 8
569#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_LOAD_SIGNED 0
570#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_MASK 0x00000080U
571#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SHIFT 7
572#define EUR_CR_EVENT_HOST_ENABLE_DPM_CONTROL_STORE_SIGNED 0
573#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_MASK 0x00000040U
574#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SHIFT 6
575#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_CLEAR_SIGNED 0
576#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_MASK 0x00000020U
577#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SHIFT 5
578#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_LOAD_SIGNED 0
579#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_MASK 0x00000010U
580#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SHIFT 4
581#define EUR_CR_EVENT_HOST_ENABLE_DPM_STATE_STORE_SIGNED 0
582#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
583#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SHIFT 3
584#define EUR_CR_EVENT_HOST_ENABLE_DPM_REACHED_MEM_THRESH_SIGNED 0
585#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
586#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
587#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_GBL_SIGNED 0
588#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
589#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SHIFT 1
590#define EUR_CR_EVENT_HOST_ENABLE_DPM_OUT_OF_MEMORY_MT_SIGNED 0
591#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_MASK 0x00000001U
592#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SHIFT 0
593#define EUR_CR_EVENT_HOST_ENABLE_DPM_3D_MEM_FREE_SIGNED 0
594#define EUR_CR_EVENT_HOST_CLEAR 0x0134
595#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_MASK 0x80000000U
596#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SHIFT 31
597#define EUR_CR_EVENT_HOST_CLEAR_MASTER_INTERRUPT_SIGNED 0
598#define EUR_CR_EVENT_HOST_CLEAR_TIMER_MASK 0x20000000U
599#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SHIFT 29
600#define EUR_CR_EVENT_HOST_CLEAR_TIMER_SIGNED 0
601#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_MASK 0x10000000U
602#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SHIFT 28
603#define EUR_CR_EVENT_HOST_CLEAR_TA_DPM_FAULT_SIGNED 0
604#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_MASK 0x04000000U
605#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SHIFT 26
606#define EUR_CR_EVENT_HOST_CLEAR_TCU_INVALCOMPLETE_SIGNED 0
607#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_MASK 0x02000000U
608#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SHIFT 25
609#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_ZLS_SIGNED 0
610#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_MASK 0x01000000U
611#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SHIFT 24
612#define EUR_CR_EVENT_HOST_CLEAR_DPM_TA_MEM_FREE_SIGNED 0
613#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_MASK 0x00800000U
614#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SHIFT 23
615#define EUR_CR_EVENT_HOST_CLEAR_ISP_END_TILE_SIGNED 0
616#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_MASK 0x00400000U
617#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SHIFT 22
618#define EUR_CR_EVENT_HOST_CLEAR_DPM_INITEND_SIGNED 0
619#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_MASK 0x00200000U
620#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SHIFT 21
621#define EUR_CR_EVENT_HOST_CLEAR_OTPM_LOADED_SIGNED 0
622#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_MASK 0x00100000U
623#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SHIFT 20
624#define EUR_CR_EVENT_HOST_CLEAR_OTPM_INV_SIGNED 0
625#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_MASK 0x00080000U
626#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SHIFT 19
627#define EUR_CR_EVENT_HOST_CLEAR_OTPM_FLUSHED_SIGNED 0
628#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_MASK 0x00040000U
629#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SHIFT 18
630#define EUR_CR_EVENT_HOST_CLEAR_PIXELBE_END_RENDER_SIGNED 0
631#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_MASK 0x00008000U
632#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SHIFT 15
633#define EUR_CR_EVENT_HOST_CLEAR_BREAKPOINT_SIGNED 0
634#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_MASK 0x00004000U
635#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SHIFT 14
636#define EUR_CR_EVENT_HOST_CLEAR_SW_EVENT_SIGNED 0
637#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_MASK 0x00002000U
638#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SHIFT 13
639#define EUR_CR_EVENT_HOST_CLEAR_TA_FINISHED_SIGNED 0
640#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_MASK 0x00001000U
641#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SHIFT 12
642#define EUR_CR_EVENT_HOST_CLEAR_TA_TERMINATE_SIGNED 0
643#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_MASK 0x00000800U
644#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SHIFT 11
645#define EUR_CR_EVENT_HOST_CLEAR_TPC_CLEAR_SIGNED 0
646#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_MASK 0x00000400U
647#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SHIFT 10
648#define EUR_CR_EVENT_HOST_CLEAR_TPC_FLUSH_SIGNED 0
649#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_MASK 0x00000200U
650#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SHIFT 9
651#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_CLEAR_SIGNED 0
652#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_MASK 0x00000100U
653#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SHIFT 8
654#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_LOAD_SIGNED 0
655#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_MASK 0x00000080U
656#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SHIFT 7
657#define EUR_CR_EVENT_HOST_CLEAR_DPM_CONTROL_STORE_SIGNED 0
658#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_MASK 0x00000040U
659#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SHIFT 6
660#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_CLEAR_SIGNED 0
661#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_MASK 0x00000020U
662#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SHIFT 5
663#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_LOAD_SIGNED 0
664#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_MASK 0x00000010U
665#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SHIFT 4
666#define EUR_CR_EVENT_HOST_CLEAR_DPM_STATE_STORE_SIGNED 0
667#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_MASK 0x00000008U
668#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SHIFT 3
669#define EUR_CR_EVENT_HOST_CLEAR_DPM_REACHED_MEM_THRESH_SIGNED 0
670#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_MASK 0x00000004U
671#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SHIFT 2
672#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_GBL_SIGNED 0
673#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_MASK 0x00000002U
674#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SHIFT 1
675#define EUR_CR_EVENT_HOST_CLEAR_DPM_OUT_OF_MEMORY_MT_SIGNED 0
676#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_MASK 0x00000001U
677#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SHIFT 0
678#define EUR_CR_EVENT_HOST_CLEAR_DPM_3D_MEM_FREE_SIGNED 0
679#define EUR_CR_TIMER 0x0144
680#define EUR_CR_TIMER_VALUE_MASK 0xFFFFFFFFU
681#define EUR_CR_TIMER_VALUE_SHIFT 0
682#define EUR_CR_TIMER_VALUE_SIGNED 0
683#define EUR_CR_EVENT_KICK1 0x0AB0
684#define EUR_CR_EVENT_KICK1_NOW_MASK 0x000000FFU
685#define EUR_CR_EVENT_KICK1_NOW_SHIFT 0
686#define EUR_CR_EVENT_KICK1_NOW_SIGNED 0
687#define EUR_CR_EVENT_KICK2 0x0AC0
688#define EUR_CR_EVENT_KICK2_NOW_MASK 0x00000001U
689#define EUR_CR_EVENT_KICK2_NOW_SHIFT 0
690#define EUR_CR_EVENT_KICK2_NOW_SIGNED 0
691#define EUR_CR_EVENT_KICKER 0x0AC4
692#define EUR_CR_EVENT_KICKER_ADDRESS_MASK 0xFFFFFFF0U
693#define EUR_CR_EVENT_KICKER_ADDRESS_SHIFT 4
694#define EUR_CR_EVENT_KICKER_ADDRESS_SIGNED 0
695#define EUR_CR_EVENT_KICK 0x0AC8
696#define EUR_CR_EVENT_KICK_NOW_MASK 0x00000001U
697#define EUR_CR_EVENT_KICK_NOW_SHIFT 0
698#define EUR_CR_EVENT_KICK_NOW_SIGNED 0
699#define EUR_CR_EVENT_TIMER 0x0ACC
700#define EUR_CR_EVENT_TIMER_ENABLE_MASK 0x01000000U
701#define EUR_CR_EVENT_TIMER_ENABLE_SHIFT 24
702#define EUR_CR_EVENT_TIMER_ENABLE_SIGNED 0
703#define EUR_CR_EVENT_TIMER_VALUE_MASK 0x00FFFFFFU
704#define EUR_CR_EVENT_TIMER_VALUE_SHIFT 0
705#define EUR_CR_EVENT_TIMER_VALUE_SIGNED 0
706#define EUR_CR_PDS_INV0 0x0AD0
707#define EUR_CR_PDS_INV0_DSC_MASK 0x00000001U
708#define EUR_CR_PDS_INV0_DSC_SHIFT 0
709#define EUR_CR_PDS_INV0_DSC_SIGNED 0
710#define EUR_CR_PDS_INV1 0x0AD4
711#define EUR_CR_PDS_INV1_DSC_MASK 0x00000001U
712#define EUR_CR_PDS_INV1_DSC_SHIFT 0
713#define EUR_CR_PDS_INV1_DSC_SIGNED 0
714#define EUR_CR_EVENT_KICK3 0x0AD8
715#define EUR_CR_EVENT_KICK3_NOW_MASK 0x00000001U
716#define EUR_CR_EVENT_KICK3_NOW_SHIFT 0
717#define EUR_CR_EVENT_KICK3_NOW_SIGNED 0
718#define EUR_CR_PDS_INV3 0x0ADC
719#define EUR_CR_PDS_INV3_DSC_MASK 0x00000001U
720#define EUR_CR_PDS_INV3_DSC_SHIFT 0
721#define EUR_CR_PDS_INV3_DSC_SIGNED 0
722#define EUR_CR_PDS_INV_CSC 0x0AE0
723#define EUR_CR_PDS_INV_CSC_KICK_MASK 0x00000001U
724#define EUR_CR_PDS_INV_CSC_KICK_SHIFT 0
725#define EUR_CR_PDS_INV_CSC_KICK_SIGNED 0
726#define EUR_CR_BIF_CTRL 0x0C00
727#define EUR_CR_BIF_CTRL_NOREORDER_MASK 0x00000001U
728#define EUR_CR_BIF_CTRL_NOREORDER_SHIFT 0
729#define EUR_CR_BIF_CTRL_NOREORDER_SIGNED 0
730#define EUR_CR_BIF_CTRL_PAUSE_MASK 0x00000002U
731#define EUR_CR_BIF_CTRL_PAUSE_SHIFT 1
732#define EUR_CR_BIF_CTRL_PAUSE_SIGNED 0
733#define EUR_CR_BIF_CTRL_CLEAR_FAULT_MASK 0x00000010U
734#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SHIFT 4
735#define EUR_CR_BIF_CTRL_CLEAR_FAULT_SIGNED 0
736#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_MASK 0x00000200U
737#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SHIFT 9
738#define EUR_CR_BIF_CTRL_MMU_BYPASS_VDM_SIGNED 0
739#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_MASK 0x00000400U
740#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SHIFT 10
741#define EUR_CR_BIF_CTRL_MMU_BYPASS_TA_SIGNED 0
742#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_MASK 0x00001000U
743#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SHIFT 12
744#define EUR_CR_BIF_CTRL_MMU_BYPASS_PBE_SIGNED 0
745#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_MASK 0x00002000U
746#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SHIFT 13
747#define EUR_CR_BIF_CTRL_MMU_BYPASS_TSPP_SIGNED 0
748#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_MASK 0x00004000U
749#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SHIFT 14
750#define EUR_CR_BIF_CTRL_MMU_BYPASS_ISP_SIGNED 0
751#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_MASK 0x00008000U
752#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SHIFT 15
753#define EUR_CR_BIF_CTRL_MMU_BYPASS_USE_SIGNED 0
754#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_MASK 0x00010000U
755#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SHIFT 16
756#define EUR_CR_BIF_CTRL_MMU_BYPASS_PTLA_SIGNED 0
757#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_MASK 0x00020000U
758#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SHIFT 17
759#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_VDM_SIGNED 0
760#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_MASK 0x00040000U
761#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SHIFT 18
762#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_IPF_SIGNED 0
763#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_MASK 0x00080000U
764#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SHIFT 19
765#define EUR_CR_BIF_CTRL_MMU_BYPASS_MASTER_DPM_SIGNED 0
766#define EUR_CR_BIF_INT_STAT 0x0C04
767#define EUR_CR_BIF_INT_STAT_FAULT_REQ_MASK 0x00003FFFU
768#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SHIFT 0
769#define EUR_CR_BIF_INT_STAT_FAULT_REQ_SIGNED 0
770#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_MASK 0x00070000U
771#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SHIFT 16
772#define EUR_CR_BIF_INT_STAT_FAULT_TYPE_SIGNED 0
773#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_MASK 0x00080000U
774#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SHIFT 19
775#define EUR_CR_BIF_INT_STAT_FLUSH_COMPLETE_SIGNED 0
776#define EUR_CR_BIF_FAULT 0x0C08
777#define EUR_CR_BIF_FAULT_CID_MASK 0x0000000FU
778#define EUR_CR_BIF_FAULT_CID_SHIFT 0
779#define EUR_CR_BIF_FAULT_CID_SIGNED 0
780#define EUR_CR_BIF_FAULT_SB_MASK 0x000001F0U
781#define EUR_CR_BIF_FAULT_SB_SHIFT 4
782#define EUR_CR_BIF_FAULT_SB_SIGNED 0
783#define EUR_CR_BIF_FAULT_ADDR_MASK 0xFFFFF000U
784#define EUR_CR_BIF_FAULT_ADDR_SHIFT 12
785#define EUR_CR_BIF_FAULT_ADDR_SIGNED 0
786#define EUR_CR_BIF_TILE0 0x0C0C
787#define EUR_CR_BIF_TILE0_MIN_ADDRESS_MASK 0x00000FFFU
788#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SHIFT 0
789#define EUR_CR_BIF_TILE0_MIN_ADDRESS_SIGNED 0
790#define EUR_CR_BIF_TILE0_MAX_ADDRESS_MASK 0x00FFF000U
791#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SHIFT 12
792#define EUR_CR_BIF_TILE0_MAX_ADDRESS_SIGNED 0
793#define EUR_CR_BIF_TILE0_CFG_MASK 0x0F000000U
794#define EUR_CR_BIF_TILE0_CFG_SHIFT 24
795#define EUR_CR_BIF_TILE0_CFG_SIGNED 0
796#define EUR_CR_BIF_TILE1 0x0C10
797#define EUR_CR_BIF_TILE1_MIN_ADDRESS_MASK 0x00000FFFU
798#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SHIFT 0
799#define EUR_CR_BIF_TILE1_MIN_ADDRESS_SIGNED 0
800#define EUR_CR_BIF_TILE1_MAX_ADDRESS_MASK 0x00FFF000U
801#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SHIFT 12
802#define EUR_CR_BIF_TILE1_MAX_ADDRESS_SIGNED 0
803#define EUR_CR_BIF_TILE1_CFG_MASK 0x0F000000U
804#define EUR_CR_BIF_TILE1_CFG_SHIFT 24
805#define EUR_CR_BIF_TILE1_CFG_SIGNED 0
806#define EUR_CR_BIF_TILE2 0x0C14
807#define EUR_CR_BIF_TILE2_MIN_ADDRESS_MASK 0x00000FFFU
808#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SHIFT 0
809#define EUR_CR_BIF_TILE2_MIN_ADDRESS_SIGNED 0
810#define EUR_CR_BIF_TILE2_MAX_ADDRESS_MASK 0x00FFF000U
811#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SHIFT 12
812#define EUR_CR_BIF_TILE2_MAX_ADDRESS_SIGNED 0
813#define EUR_CR_BIF_TILE2_CFG_MASK 0x0F000000U
814#define EUR_CR_BIF_TILE2_CFG_SHIFT 24
815#define EUR_CR_BIF_TILE2_CFG_SIGNED 0
816#define EUR_CR_BIF_TILE3 0x0C18
817#define EUR_CR_BIF_TILE3_MIN_ADDRESS_MASK 0x00000FFFU
818#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SHIFT 0
819#define EUR_CR_BIF_TILE3_MIN_ADDRESS_SIGNED 0
820#define EUR_CR_BIF_TILE3_MAX_ADDRESS_MASK 0x00FFF000U
821#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SHIFT 12
822#define EUR_CR_BIF_TILE3_MAX_ADDRESS_SIGNED 0
823#define EUR_CR_BIF_TILE3_CFG_MASK 0x0F000000U
824#define EUR_CR_BIF_TILE3_CFG_SHIFT 24
825#define EUR_CR_BIF_TILE3_CFG_SIGNED 0
826#define EUR_CR_BIF_TILE4 0x0C1C
827#define EUR_CR_BIF_TILE4_MIN_ADDRESS_MASK 0x00000FFFU
828#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SHIFT 0
829#define EUR_CR_BIF_TILE4_MIN_ADDRESS_SIGNED 0
830#define EUR_CR_BIF_TILE4_MAX_ADDRESS_MASK 0x00FFF000U
831#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SHIFT 12
832#define EUR_CR_BIF_TILE4_MAX_ADDRESS_SIGNED 0
833#define EUR_CR_BIF_TILE4_CFG_MASK 0x0F000000U
834#define EUR_CR_BIF_TILE4_CFG_SHIFT 24
835#define EUR_CR_BIF_TILE4_CFG_SIGNED 0
836#define EUR_CR_BIF_TILE5 0x0C20
837#define EUR_CR_BIF_TILE5_MIN_ADDRESS_MASK 0x00000FFFU
838#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SHIFT 0
839#define EUR_CR_BIF_TILE5_MIN_ADDRESS_SIGNED 0
840#define EUR_CR_BIF_TILE5_MAX_ADDRESS_MASK 0x00FFF000U
841#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SHIFT 12
842#define EUR_CR_BIF_TILE5_MAX_ADDRESS_SIGNED 0
843#define EUR_CR_BIF_TILE5_CFG_MASK 0x0F000000U
844#define EUR_CR_BIF_TILE5_CFG_SHIFT 24
845#define EUR_CR_BIF_TILE5_CFG_SIGNED 0
846#define EUR_CR_BIF_TILE6 0x0C24
847#define EUR_CR_BIF_TILE6_MIN_ADDRESS_MASK 0x00000FFFU
848#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SHIFT 0
849#define EUR_CR_BIF_TILE6_MIN_ADDRESS_SIGNED 0
850#define EUR_CR_BIF_TILE6_MAX_ADDRESS_MASK 0x00FFF000U
851#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SHIFT 12
852#define EUR_CR_BIF_TILE6_MAX_ADDRESS_SIGNED 0
853#define EUR_CR_BIF_TILE6_CFG_MASK 0x0F000000U
854#define EUR_CR_BIF_TILE6_CFG_SHIFT 24
855#define EUR_CR_BIF_TILE6_CFG_SIGNED 0
856#define EUR_CR_BIF_TILE7 0x0C28
857#define EUR_CR_BIF_TILE7_MIN_ADDRESS_MASK 0x00000FFFU
858#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SHIFT 0
859#define EUR_CR_BIF_TILE7_MIN_ADDRESS_SIGNED 0
860#define EUR_CR_BIF_TILE7_MAX_ADDRESS_MASK 0x00FFF000U
861#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SHIFT 12
862#define EUR_CR_BIF_TILE7_MAX_ADDRESS_SIGNED 0
863#define EUR_CR_BIF_TILE7_CFG_MASK 0x0F000000U
864#define EUR_CR_BIF_TILE7_CFG_SHIFT 24
865#define EUR_CR_BIF_TILE7_CFG_SIGNED 0
866#define EUR_CR_BIF_TILE8 0x0C2C
867#define EUR_CR_BIF_TILE8_MIN_ADDRESS_MASK 0x00000FFFU
868#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SHIFT 0
869#define EUR_CR_BIF_TILE8_MIN_ADDRESS_SIGNED 0
870#define EUR_CR_BIF_TILE8_MAX_ADDRESS_MASK 0x00FFF000U
871#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SHIFT 12
872#define EUR_CR_BIF_TILE8_MAX_ADDRESS_SIGNED 0
873#define EUR_CR_BIF_TILE8_CFG_MASK 0x0F000000U
874#define EUR_CR_BIF_TILE8_CFG_SHIFT 24
875#define EUR_CR_BIF_TILE8_CFG_SIGNED 0
876#define EUR_CR_BIF_TILE9 0x0C30
877#define EUR_CR_BIF_TILE9_MIN_ADDRESS_MASK 0x00000FFFU
878#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SHIFT 0
879#define EUR_CR_BIF_TILE9_MIN_ADDRESS_SIGNED 0
880#define EUR_CR_BIF_TILE9_MAX_ADDRESS_MASK 0x00FFF000U
881#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SHIFT 12
882#define EUR_CR_BIF_TILE9_MAX_ADDRESS_SIGNED 0
883#define EUR_CR_BIF_TILE9_CFG_MASK 0x0F000000U
884#define EUR_CR_BIF_TILE9_CFG_SHIFT 24
885#define EUR_CR_BIF_TILE9_CFG_SIGNED 0
886#define EUR_CR_BIF_CTRL_INVAL 0x0C34
887#define EUR_CR_BIF_CTRL_INVAL_PTE_MASK 0x00000004U
888#define EUR_CR_BIF_CTRL_INVAL_PTE_SHIFT 2
889#define EUR_CR_BIF_CTRL_INVAL_PTE_SIGNED 0
890#define EUR_CR_BIF_CTRL_INVAL_ALL_MASK 0x00000008U
891#define EUR_CR_BIF_CTRL_INVAL_ALL_SHIFT 3
892#define EUR_CR_BIF_CTRL_INVAL_ALL_SIGNED 0
893#define EUR_CR_BIF_DIR_LIST_BASE1 0x0C38
894#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_MASK 0xFFFFF000U
895#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SHIFT 12
896#define EUR_CR_BIF_DIR_LIST_BASE1_ADDR_SIGNED 0
897#define EUR_CR_BIF_DIR_LIST_BASE2 0x0C3C
898#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_MASK 0xFFFFF000U
899#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SHIFT 12
900#define EUR_CR_BIF_DIR_LIST_BASE2_ADDR_SIGNED 0
901#define EUR_CR_BIF_DIR_LIST_BASE3 0x0C40
902#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_MASK 0xFFFFF000U
903#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SHIFT 12
904#define EUR_CR_BIF_DIR_LIST_BASE3_ADDR_SIGNED 0
905#define EUR_CR_BIF_DIR_LIST_BASE4 0x0C44
906#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_MASK 0xFFFFF000U
907#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SHIFT 12
908#define EUR_CR_BIF_DIR_LIST_BASE4_ADDR_SIGNED 0
909#define EUR_CR_BIF_DIR_LIST_BASE5 0x0C48
910#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_MASK 0xFFFFF000U
911#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SHIFT 12
912#define EUR_CR_BIF_DIR_LIST_BASE5_ADDR_SIGNED 0
913#define EUR_CR_BIF_DIR_LIST_BASE6 0x0C4C
914#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_MASK 0xFFFFF000U
915#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SHIFT 12
916#define EUR_CR_BIF_DIR_LIST_BASE6_ADDR_SIGNED 0
917#define EUR_CR_BIF_DIR_LIST_BASE7 0x0C50
918#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_MASK 0xFFFFF000U
919#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SHIFT 12
920#define EUR_CR_BIF_DIR_LIST_BASE7_ADDR_SIGNED 0
921#define EUR_CR_BIF_BANK_SET 0x0C74
922#define EUR_CR_BIF_BANK_SET_SELECT_2D_MASK 0x00000001U
923#define EUR_CR_BIF_BANK_SET_SELECT_2D_SHIFT 0
924#define EUR_CR_BIF_BANK_SET_SELECT_2D_SIGNED 0
925#define EUR_CR_BIF_BANK_SET_SELECT_3D_MASK 0x0000000CU
926#define EUR_CR_BIF_BANK_SET_SELECT_3D_SHIFT 2
927#define EUR_CR_BIF_BANK_SET_SELECT_3D_SIGNED 0
928#define EUR_CR_BIF_BANK_SET_SELECT_HOST_MASK 0x00000010U
929#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SHIFT 4
930#define EUR_CR_BIF_BANK_SET_SELECT_HOST_SIGNED 0
931#define EUR_CR_BIF_BANK_SET_SELECT_TA_MASK 0x000000C0U
932#define EUR_CR_BIF_BANK_SET_SELECT_TA_SHIFT 6
933#define EUR_CR_BIF_BANK_SET_SELECT_TA_SIGNED 0
934#define EUR_CR_BIF_BANK_SET_SELECT_EDM_MASK 0x00000100U
935#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SHIFT 8
936#define EUR_CR_BIF_BANK_SET_SELECT_EDM_SIGNED 0
937#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_MASK 0x00000200U
938#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SHIFT 9
939#define EUR_CR_BIF_BANK_SET_SELECT_DPM_LSS_SIGNED 0
940#define EUR_CR_BIF_BANK0 0x0C78
941#define EUR_CR_BIF_BANK0_INDEX_EDM_MASK 0x0000000FU
942#define EUR_CR_BIF_BANK0_INDEX_EDM_SHIFT 0
943#define EUR_CR_BIF_BANK0_INDEX_EDM_SIGNED 0
944#define EUR_CR_BIF_BANK0_INDEX_TA_MASK 0x000000F0U
945#define EUR_CR_BIF_BANK0_INDEX_TA_SHIFT 4
946#define EUR_CR_BIF_BANK0_INDEX_TA_SIGNED 0
947#define EUR_CR_BIF_BANK0_INDEX_3D_MASK 0x0000F000U
948#define EUR_CR_BIF_BANK0_INDEX_3D_SHIFT 12
949#define EUR_CR_BIF_BANK0_INDEX_3D_SIGNED 0
950#define EUR_CR_BIF_BANK0_INDEX_PTLA_MASK 0x000F0000U
951#define EUR_CR_BIF_BANK0_INDEX_PTLA_SHIFT 16
952#define EUR_CR_BIF_BANK0_INDEX_PTLA_SIGNED 0
953#define EUR_CR_BIF_BANK1 0x0C7C
954#define EUR_CR_BIF_BANK1_INDEX_EDM_MASK 0x0000000FU
955#define EUR_CR_BIF_BANK1_INDEX_EDM_SHIFT 0
956#define EUR_CR_BIF_BANK1_INDEX_EDM_SIGNED 0
957#define EUR_CR_BIF_BANK1_INDEX_TA_MASK 0x000000F0U
958#define EUR_CR_BIF_BANK1_INDEX_TA_SHIFT 4
959#define EUR_CR_BIF_BANK1_INDEX_TA_SIGNED 0
960#define EUR_CR_BIF_BANK1_INDEX_3D_MASK 0x0000F000U
961#define EUR_CR_BIF_BANK1_INDEX_3D_SHIFT 12
962#define EUR_CR_BIF_BANK1_INDEX_3D_SIGNED 0
963#define EUR_CR_BIF_DIR_LIST_BASE0 0x0C84
964#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_MASK 0xFFFFF000U
965#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SHIFT 12
966#define EUR_CR_BIF_DIR_LIST_BASE0_ADDR_SIGNED 0
967#define EUR_CR_BIF_TA_REQ_BASE 0x0C90
968#define EUR_CR_BIF_TA_REQ_BASE_ADDR_MASK 0xFFF00000U
969#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SHIFT 20
970#define EUR_CR_BIF_TA_REQ_BASE_ADDR_SIGNED 0
971#define EUR_CR_BIF_MEM_REQ_STAT 0x0CA8
972#define EUR_CR_BIF_MEM_REQ_STAT_READS_MASK 0x000000FFU
973#define EUR_CR_BIF_MEM_REQ_STAT_READS_SHIFT 0
974#define EUR_CR_BIF_MEM_REQ_STAT_READS_SIGNED 0
975#define EUR_CR_BIF_3D_REQ_BASE 0x0CAC
976#define EUR_CR_BIF_3D_REQ_BASE_ADDR_MASK 0xFFF00000U
977#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SHIFT 20
978#define EUR_CR_BIF_3D_REQ_BASE_ADDR_SIGNED 0
979#define EUR_CR_BIF_ZLS_REQ_BASE 0x0CB0
980#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_MASK 0xFFF00000U
981#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SHIFT 20
982#define EUR_CR_BIF_ZLS_REQ_BASE_ADDR_SIGNED 0
983#define EUR_CR_BIF_BANK_STATUS 0x0CB4
984#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_MASK 0x00000001U
985#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SHIFT 0
986#define EUR_CR_BIF_BANK_STATUS_3D_CURRENT_BANK_SIGNED 0
987#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_MASK 0x00000002U
988#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SHIFT 1
989#define EUR_CR_BIF_BANK_STATUS_TA_CURRENT_BANK_SIGNED 0
990#define EUR_CR_2D_BLIT_STATUS 0x0E04
991#define EUR_CR_2D_BLIT_STATUS_COMPLETE_MASK 0x00FFFFFFU
992#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SHIFT 0
993#define EUR_CR_2D_BLIT_STATUS_COMPLETE_SIGNED 0
994#define EUR_CR_2D_BLIT_STATUS_BUSY_MASK 0x01000000U
995#define EUR_CR_2D_BLIT_STATUS_BUSY_SHIFT 24
996#define EUR_CR_2D_BLIT_STATUS_BUSY_SIGNED 0
997#define EUR_CR_2D_VIRTUAL_FIFO_0 0x0E10
998#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_MASK 0x00000001U
999#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SHIFT 0
1000#define EUR_CR_2D_VIRTUAL_FIFO_0_ENABLE_SIGNED 0
1001#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MASK 0x0000000EU
1002#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SHIFT 1
1003#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_SIGNED 0
1004#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_MASK 0x00000FF0U
1005#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SHIFT 4
1006#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_DIV_SIGNED 0
1007#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_MASK 0x0000F000U
1008#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SHIFT 12
1009#define EUR_CR_2D_VIRTUAL_FIFO_0_FLOWRATE_MUL_SIGNED 0
1010#define EUR_CR_2D_VIRTUAL_FIFO_1 0x0E14
1011#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_MASK 0x00000FFFU
1012#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SHIFT 0
1013#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_ACC_SIGNED 0
1014#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_MASK 0x00FFF000U
1015#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SHIFT 12
1016#define EUR_CR_2D_VIRTUAL_FIFO_1_MAX_ACC_SIGNED 0
1017#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_MASK 0xFF000000U
1018#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SHIFT 24
1019#define EUR_CR_2D_VIRTUAL_FIFO_1_MIN_METRIC_SIGNED 0
1020#define EUR_CR_BREAKPOINT0_START 0x0F44
1021#define EUR_CR_BREAKPOINT0_START_ADDRESS_MASK 0xFFFFFFF0U
1022#define EUR_CR_BREAKPOINT0_START_ADDRESS_SHIFT 4
1023#define EUR_CR_BREAKPOINT0_START_ADDRESS_SIGNED 0
1024#define EUR_CR_BREAKPOINT0_END 0x0F48
1025#define EUR_CR_BREAKPOINT0_END_ADDRESS_MASK 0xFFFFFFF0U
1026#define EUR_CR_BREAKPOINT0_END_ADDRESS_SHIFT 4
1027#define EUR_CR_BREAKPOINT0_END_ADDRESS_SIGNED 0
1028#define EUR_CR_BREAKPOINT0 0x0F4C
1029#define EUR_CR_BREAKPOINT0_MASK_DM_MASK 0x00000038U
1030#define EUR_CR_BREAKPOINT0_MASK_DM_SHIFT 3
1031#define EUR_CR_BREAKPOINT0_MASK_DM_SIGNED 0
1032#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_MASK 0x00000004U
1033#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SHIFT 2
1034#define EUR_CR_BREAKPOINT0_CTRL_TRAPENABLE_SIGNED 0
1035#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_MASK 0x00000002U
1036#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SHIFT 1
1037#define EUR_CR_BREAKPOINT0_CTRL_WENABLE_SIGNED 0
1038#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_MASK 0x00000001U
1039#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SHIFT 0
1040#define EUR_CR_BREAKPOINT0_CTRL_RENABLE_SIGNED 0
1041#define EUR_CR_BREAKPOINT1_START 0x0F50
1042#define EUR_CR_BREAKPOINT1_START_ADDRESS_MASK 0xFFFFFFF0U
1043#define EUR_CR_BREAKPOINT1_START_ADDRESS_SHIFT 4
1044#define EUR_CR_BREAKPOINT1_START_ADDRESS_SIGNED 0
1045#define EUR_CR_BREAKPOINT1_END 0x0F54
1046#define EUR_CR_BREAKPOINT1_END_ADDRESS_MASK 0xFFFFFFF0U
1047#define EUR_CR_BREAKPOINT1_END_ADDRESS_SHIFT 4
1048#define EUR_CR_BREAKPOINT1_END_ADDRESS_SIGNED 0
1049#define EUR_CR_BREAKPOINT1 0x0F58
1050#define EUR_CR_BREAKPOINT1_MASK_DM_MASK 0x00000038U
1051#define EUR_CR_BREAKPOINT1_MASK_DM_SHIFT 3
1052#define EUR_CR_BREAKPOINT1_MASK_DM_SIGNED 0
1053#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_MASK 0x00000004U
1054#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SHIFT 2
1055#define EUR_CR_BREAKPOINT1_CTRL_TRAPENABLE_SIGNED 0
1056#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_MASK 0x00000002U
1057#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SHIFT 1
1058#define EUR_CR_BREAKPOINT1_CTRL_WENABLE_SIGNED 0
1059#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_MASK 0x00000001U
1060#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SHIFT 0
1061#define EUR_CR_BREAKPOINT1_CTRL_RENABLE_SIGNED 0
1062#define EUR_CR_BREAKPOINT2_START 0x0F5C
1063#define EUR_CR_BREAKPOINT2_START_ADDRESS_MASK 0xFFFFFFF0U
1064#define EUR_CR_BREAKPOINT2_START_ADDRESS_SHIFT 4
1065#define EUR_CR_BREAKPOINT2_START_ADDRESS_SIGNED 0
1066#define EUR_CR_BREAKPOINT2_END 0x0F60
1067#define EUR_CR_BREAKPOINT2_END_ADDRESS_MASK 0xFFFFFFF0U
1068#define EUR_CR_BREAKPOINT2_END_ADDRESS_SHIFT 4
1069#define EUR_CR_BREAKPOINT2_END_ADDRESS_SIGNED 0
1070#define EUR_CR_BREAKPOINT2 0x0F64
1071#define EUR_CR_BREAKPOINT2_MASK_DM_MASK 0x00000038U
1072#define EUR_CR_BREAKPOINT2_MASK_DM_SHIFT 3
1073#define EUR_CR_BREAKPOINT2_MASK_DM_SIGNED 0
1074#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_MASK 0x00000004U
1075#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SHIFT 2
1076#define EUR_CR_BREAKPOINT2_CTRL_TRAPENABLE_SIGNED 0
1077#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_MASK 0x00000002U
1078#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SHIFT 1
1079#define EUR_CR_BREAKPOINT2_CTRL_WENABLE_SIGNED 0
1080#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_MASK 0x00000001U
1081#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SHIFT 0
1082#define EUR_CR_BREAKPOINT2_CTRL_RENABLE_SIGNED 0
1083#define EUR_CR_BREAKPOINT3_START 0x0F68
1084#define EUR_CR_BREAKPOINT3_START_ADDRESS_MASK 0xFFFFFFF0U
1085#define EUR_CR_BREAKPOINT3_START_ADDRESS_SHIFT 4
1086#define EUR_CR_BREAKPOINT3_START_ADDRESS_SIGNED 0
1087#define EUR_CR_BREAKPOINT3_END 0x0F6C
1088#define EUR_CR_BREAKPOINT3_END_ADDRESS_MASK 0xFFFFFFF0U
1089#define EUR_CR_BREAKPOINT3_END_ADDRESS_SHIFT 4
1090#define EUR_CR_BREAKPOINT3_END_ADDRESS_SIGNED 0
1091#define EUR_CR_BREAKPOINT3 0x0F70
1092#define EUR_CR_BREAKPOINT3_MASK_DM_MASK 0x00000038U
1093#define EUR_CR_BREAKPOINT3_MASK_DM_SHIFT 3
1094#define EUR_CR_BREAKPOINT3_MASK_DM_SIGNED 0
1095#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_MASK 0x00000004U
1096#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SHIFT 2
1097#define EUR_CR_BREAKPOINT3_CTRL_TRAPENABLE_SIGNED 0
1098#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_MASK 0x00000002U
1099#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SHIFT 1
1100#define EUR_CR_BREAKPOINT3_CTRL_WENABLE_SIGNED 0
1101#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_MASK 0x00000001U
1102#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SHIFT 0
1103#define EUR_CR_BREAKPOINT3_CTRL_RENABLE_SIGNED 0
1104#define EUR_CR_BREAKPOINT_READ 0x0F74
1105#define EUR_CR_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U
1106#define EUR_CR_BREAKPOINT_READ_ADDRESS_SHIFT 4
1107#define EUR_CR_BREAKPOINT_READ_ADDRESS_SIGNED 0
1108#define EUR_CR_PARTITION_BREAKPOINT_TRAP 0x0F78
1109#define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U
1110#define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_SHIFT 1
1111#define EUR_CR_PARTITION_BREAKPOINT_TRAP_CONTINUE_SIGNED 0
1112#define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U
1113#define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0
1114#define EUR_CR_PARTITION_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0
1115#define EUR_CR_PARTITION_BREAKPOINT 0x0F7C
1116#define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_MASK 0x000003C0U
1117#define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_SHIFT 6
1118#define EUR_CR_PARTITION_BREAKPOINT_MODULE_ID_SIGNED 0
1119#define EUR_CR_PARTITION_BREAKPOINT_ID_MASK 0x00000030U
1120#define EUR_CR_PARTITION_BREAKPOINT_ID_SHIFT 4
1121#define EUR_CR_PARTITION_BREAKPOINT_ID_SIGNED 0
1122#define EUR_CR_PARTITION_BREAKPOINT_UNTRAPPED_MASK 0x00000008U
1123#define EUR_CR_PARTITION_BREAKPOINT_UNTRAPPED_SHIFT 3
1124#define EUR_CR_PARTITION_BREAKPOINT_UNTRAPPED_SIGNED 0
1125#define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_MASK 0x00000004U
1126#define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_SHIFT 2
1127#define EUR_CR_PARTITION_BREAKPOINT_TRAPPED_SIGNED 0
1128#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0 0x0F80
1129#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U
1130#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4
1131#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0
1132#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1 0x0F84
1133#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U
1134#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10
1135#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0
1136#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U
1137#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8
1138#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0
1139#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U
1140#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3
1141#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0
1142#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U
1143#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1
1144#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0
1145#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U
1146#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0
1147#define EUR_CR_PARTITION_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0
1148#define EUR_CR_USE_CODE_BASE_0 0x0A0C
1149#define EUR_CR_USE_CODE_BASE_ADDR_00_MASK 0x03FFFFFFU
1150#define EUR_CR_USE_CODE_BASE_ADDR_00_SHIFT 0
1151#define EUR_CR_USE_CODE_BASE_ADDR_00_SIGNED 0
1152#define EUR_CR_USE_CODE_BASE_DM_00_MASK 0x0C000000U
1153#define EUR_CR_USE_CODE_BASE_DM_00_SHIFT 26
1154#define EUR_CR_USE_CODE_BASE_DM_00_SIGNED 0
1155#define EUR_CR_USE_CODE_BASE_1 0x0A10
1156#define EUR_CR_USE_CODE_BASE_ADDR_01_MASK 0x03FFFFFFU
1157#define EUR_CR_USE_CODE_BASE_ADDR_01_SHIFT 0
1158#define EUR_CR_USE_CODE_BASE_ADDR_01_SIGNED 0
1159#define EUR_CR_USE_CODE_BASE_DM_01_MASK 0x0C000000U
1160#define EUR_CR_USE_CODE_BASE_DM_01_SHIFT 26
1161#define EUR_CR_USE_CODE_BASE_DM_01_SIGNED 0
1162#define EUR_CR_USE_CODE_BASE_2 0x0A14
1163#define EUR_CR_USE_CODE_BASE_ADDR_02_MASK 0x03FFFFFFU
1164#define EUR_CR_USE_CODE_BASE_ADDR_02_SHIFT 0
1165#define EUR_CR_USE_CODE_BASE_ADDR_02_SIGNED 0
1166#define EUR_CR_USE_CODE_BASE_DM_02_MASK 0x0C000000U
1167#define EUR_CR_USE_CODE_BASE_DM_02_SHIFT 26
1168#define EUR_CR_USE_CODE_BASE_DM_02_SIGNED 0
1169#define EUR_CR_USE_CODE_BASE_3 0x0A18
1170#define EUR_CR_USE_CODE_BASE_ADDR_03_MASK 0x03FFFFFFU
1171#define EUR_CR_USE_CODE_BASE_ADDR_03_SHIFT 0
1172#define EUR_CR_USE_CODE_BASE_ADDR_03_SIGNED 0
1173#define EUR_CR_USE_CODE_BASE_DM_03_MASK 0x0C000000U
1174#define EUR_CR_USE_CODE_BASE_DM_03_SHIFT 26
1175#define EUR_CR_USE_CODE_BASE_DM_03_SIGNED 0
1176#define EUR_CR_USE_CODE_BASE_4 0x0A1C
1177#define EUR_CR_USE_CODE_BASE_ADDR_04_MASK 0x03FFFFFFU
1178#define EUR_CR_USE_CODE_BASE_ADDR_04_SHIFT 0
1179#define EUR_CR_USE_CODE_BASE_ADDR_04_SIGNED 0
1180#define EUR_CR_USE_CODE_BASE_DM_04_MASK 0x0C000000U
1181#define EUR_CR_USE_CODE_BASE_DM_04_SHIFT 26
1182#define EUR_CR_USE_CODE_BASE_DM_04_SIGNED 0
1183#define EUR_CR_USE_CODE_BASE_5 0x0A20
1184#define EUR_CR_USE_CODE_BASE_ADDR_05_MASK 0x03FFFFFFU
1185#define EUR_CR_USE_CODE_BASE_ADDR_05_SHIFT 0
1186#define EUR_CR_USE_CODE_BASE_ADDR_05_SIGNED 0
1187#define EUR_CR_USE_CODE_BASE_DM_05_MASK 0x0C000000U
1188#define EUR_CR_USE_CODE_BASE_DM_05_SHIFT 26
1189#define EUR_CR_USE_CODE_BASE_DM_05_SIGNED 0
1190#define EUR_CR_USE_CODE_BASE_6 0x0A24
1191#define EUR_CR_USE_CODE_BASE_ADDR_06_MASK 0x03FFFFFFU
1192#define EUR_CR_USE_CODE_BASE_ADDR_06_SHIFT 0
1193#define EUR_CR_USE_CODE_BASE_ADDR_06_SIGNED 0
1194#define EUR_CR_USE_CODE_BASE_DM_06_MASK 0x0C000000U
1195#define EUR_CR_USE_CODE_BASE_DM_06_SHIFT 26
1196#define EUR_CR_USE_CODE_BASE_DM_06_SIGNED 0
1197#define EUR_CR_USE_CODE_BASE_7 0x0A28
1198#define EUR_CR_USE_CODE_BASE_ADDR_07_MASK 0x03FFFFFFU
1199#define EUR_CR_USE_CODE_BASE_ADDR_07_SHIFT 0
1200#define EUR_CR_USE_CODE_BASE_ADDR_07_SIGNED 0
1201#define EUR_CR_USE_CODE_BASE_DM_07_MASK 0x0C000000U
1202#define EUR_CR_USE_CODE_BASE_DM_07_SHIFT 26
1203#define EUR_CR_USE_CODE_BASE_DM_07_SIGNED 0
1204#define EUR_CR_USE_CODE_BASE_8 0x0A2C
1205#define EUR_CR_USE_CODE_BASE_ADDR_08_MASK 0x03FFFFFFU
1206#define EUR_CR_USE_CODE_BASE_ADDR_08_SHIFT 0
1207#define EUR_CR_USE_CODE_BASE_ADDR_08_SIGNED 0
1208#define EUR_CR_USE_CODE_BASE_DM_08_MASK 0x0C000000U
1209#define EUR_CR_USE_CODE_BASE_DM_08_SHIFT 26
1210#define EUR_CR_USE_CODE_BASE_DM_08_SIGNED 0
1211#define EUR_CR_USE_CODE_BASE_9 0x0A30
1212#define EUR_CR_USE_CODE_BASE_ADDR_09_MASK 0x03FFFFFFU
1213#define EUR_CR_USE_CODE_BASE_ADDR_09_SHIFT 0
1214#define EUR_CR_USE_CODE_BASE_ADDR_09_SIGNED 0
1215#define EUR_CR_USE_CODE_BASE_DM_09_MASK 0x0C000000U
1216#define EUR_CR_USE_CODE_BASE_DM_09_SHIFT 26
1217#define EUR_CR_USE_CODE_BASE_DM_09_SIGNED 0
1218#define EUR_CR_USE_CODE_BASE_10 0x0A34
1219#define EUR_CR_USE_CODE_BASE_ADDR_10_MASK 0x03FFFFFFU
1220#define EUR_CR_USE_CODE_BASE_ADDR_10_SHIFT 0
1221#define EUR_CR_USE_CODE_BASE_ADDR_10_SIGNED 0
1222#define EUR_CR_USE_CODE_BASE_DM_10_MASK 0x0C000000U
1223#define EUR_CR_USE_CODE_BASE_DM_10_SHIFT 26
1224#define EUR_CR_USE_CODE_BASE_DM_10_SIGNED 0
1225#define EUR_CR_USE_CODE_BASE_11 0x0A38
1226#define EUR_CR_USE_CODE_BASE_ADDR_11_MASK 0x03FFFFFFU
1227#define EUR_CR_USE_CODE_BASE_ADDR_11_SHIFT 0
1228#define EUR_CR_USE_CODE_BASE_ADDR_11_SIGNED 0
1229#define EUR_CR_USE_CODE_BASE_DM_11_MASK 0x0C000000U
1230#define EUR_CR_USE_CODE_BASE_DM_11_SHIFT 26
1231#define EUR_CR_USE_CODE_BASE_DM_11_SIGNED 0
1232#define EUR_CR_USE_CODE_BASE_12 0x0A3C
1233#define EUR_CR_USE_CODE_BASE_ADDR_12_MASK 0x03FFFFFFU
1234#define EUR_CR_USE_CODE_BASE_ADDR_12_SHIFT 0
1235#define EUR_CR_USE_CODE_BASE_ADDR_12_SIGNED 0
1236#define EUR_CR_USE_CODE_BASE_DM_12_MASK 0x0C000000U
1237#define EUR_CR_USE_CODE_BASE_DM_12_SHIFT 26
1238#define EUR_CR_USE_CODE_BASE_DM_12_SIGNED 0
1239#define EUR_CR_USE_CODE_BASE_13 0x0A40
1240#define EUR_CR_USE_CODE_BASE_ADDR_13_MASK 0x03FFFFFFU
1241#define EUR_CR_USE_CODE_BASE_ADDR_13_SHIFT 0
1242#define EUR_CR_USE_CODE_BASE_ADDR_13_SIGNED 0
1243#define EUR_CR_USE_CODE_BASE_DM_13_MASK 0x0C000000U
1244#define EUR_CR_USE_CODE_BASE_DM_13_SHIFT 26
1245#define EUR_CR_USE_CODE_BASE_DM_13_SIGNED 0
1246#define EUR_CR_USE_CODE_BASE_14 0x0A44
1247#define EUR_CR_USE_CODE_BASE_ADDR_14_MASK 0x03FFFFFFU
1248#define EUR_CR_USE_CODE_BASE_ADDR_14_SHIFT 0
1249#define EUR_CR_USE_CODE_BASE_ADDR_14_SIGNED 0
1250#define EUR_CR_USE_CODE_BASE_DM_14_MASK 0x0C000000U
1251#define EUR_CR_USE_CODE_BASE_DM_14_SHIFT 26
1252#define EUR_CR_USE_CODE_BASE_DM_14_SIGNED 0
1253#define EUR_CR_USE_CODE_BASE_15 0x0A48
1254#define EUR_CR_USE_CODE_BASE_ADDR_15_MASK 0x03FFFFFFU
1255#define EUR_CR_USE_CODE_BASE_ADDR_15_SHIFT 0
1256#define EUR_CR_USE_CODE_BASE_ADDR_15_SIGNED 0
1257#define EUR_CR_USE_CODE_BASE_DM_15_MASK 0x0C000000U
1258#define EUR_CR_USE_CODE_BASE_DM_15_SHIFT 26
1259#define EUR_CR_USE_CODE_BASE_DM_15_SIGNED 0
1260#define EUR_CR_PIPE0_BREAKPOINT_TRAP 0x0F88
1261#define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U
1262#define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_SHIFT 1
1263#define EUR_CR_PIPE0_BREAKPOINT_TRAP_CONTINUE_SIGNED 0
1264#define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U
1265#define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0
1266#define EUR_CR_PIPE0_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0
1267#define EUR_CR_PIPE0_BREAKPOINT 0x0F8C
1268#define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_MASK 0x000003C0U
1269#define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_SHIFT 6
1270#define EUR_CR_PIPE0_BREAKPOINT_MODULE_ID_SIGNED 0
1271#define EUR_CR_PIPE0_BREAKPOINT_ID_MASK 0x00000030U
1272#define EUR_CR_PIPE0_BREAKPOINT_ID_SHIFT 4
1273#define EUR_CR_PIPE0_BREAKPOINT_ID_SIGNED 0
1274#define EUR_CR_PIPE0_BREAKPOINT_UNTRAPPED_MASK 0x00000008U
1275#define EUR_CR_PIPE0_BREAKPOINT_UNTRAPPED_SHIFT 3
1276#define EUR_CR_PIPE0_BREAKPOINT_UNTRAPPED_SIGNED 0
1277#define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_MASK 0x00000004U
1278#define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_SHIFT 2
1279#define EUR_CR_PIPE0_BREAKPOINT_TRAPPED_SIGNED 0
1280#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0 0x0F90
1281#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U
1282#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4
1283#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0
1284#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1 0x0F94
1285#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U
1286#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10
1287#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0
1288#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U
1289#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8
1290#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0
1291#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U
1292#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3
1293#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0
1294#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U
1295#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1
1296#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0
1297#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U
1298#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0
1299#define EUR_CR_PIPE0_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0
1300#define EUR_CR_PIPE1_BREAKPOINT_TRAP 0x0F98
1301#define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_MASK 0x00000002U
1302#define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_SHIFT 1
1303#define EUR_CR_PIPE1_BREAKPOINT_TRAP_CONTINUE_SIGNED 0
1304#define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_MASK 0x00000001U
1305#define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0
1306#define EUR_CR_PIPE1_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0
1307#define EUR_CR_PIPE1_BREAKPOINT 0x0F9C
1308#define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_MASK 0x000003C0U
1309#define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_SHIFT 6
1310#define EUR_CR_PIPE1_BREAKPOINT_MODULE_ID_SIGNED 0
1311#define EUR_CR_PIPE1_BREAKPOINT_ID_MASK 0x00000030U
1312#define EUR_CR_PIPE1_BREAKPOINT_ID_SHIFT 4
1313#define EUR_CR_PIPE1_BREAKPOINT_ID_SIGNED 0
1314#define EUR_CR_PIPE1_BREAKPOINT_UNTRAPPED_MASK 0x00000008U
1315#define EUR_CR_PIPE1_BREAKPOINT_UNTRAPPED_SHIFT 3
1316#define EUR_CR_PIPE1_BREAKPOINT_UNTRAPPED_SIGNED 0
1317#define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_MASK 0x00000004U
1318#define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_SHIFT 2
1319#define EUR_CR_PIPE1_BREAKPOINT_TRAPPED_SIGNED 0
1320#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0 0x0FA0
1321#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_MASK 0xFFFFFFF0U
1322#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_SHIFT 4
1323#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO0_ADDRESS_SIGNED 0
1324#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1 0x0FA4
1325#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_MASK 0x00007C00U
1326#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_SHIFT 10
1327#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_SIZE_SIGNED 0
1328#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_NUMBER_MASK 0x00000300U
1329#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_NUMBER_SHIFT 8
1330#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_NUMBER_SIGNED 0
1331#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_TAG_MASK 0x000000F8U
1332#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_TAG_SHIFT 3
1333#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_TAG_SIGNED 0
1334#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_DATA_MASTER_MASK 0x00000006U
1335#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SHIFT 1
1336#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_DATA_MASTER_SIGNED 0
1337#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_MASK 0x00000001U
1338#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_SHIFT 0
1339#define EUR_CR_PIPE1_BREAKPOINT_TRAP_INFO1_RNW_SIGNED 0
1340#define EUR_CR_USE_CODE_BASE(X) (0x0A0C + (4 * (X)))
1341#define EUR_CR_USE_CODE_BASE_ADDR_MASK 0x03FFFFFFU
1342#define EUR_CR_USE_CODE_BASE_ADDR_SHIFT 0
1343#define EUR_CR_USE_CODE_BASE_ADDR_SIGNED 0
1344#define EUR_CR_USE_CODE_BASE_DM_MASK 0x0C000000U
1345#define EUR_CR_USE_CODE_BASE_DM_SHIFT 26
1346#define EUR_CR_USE_CODE_BASE_DM_SIGNED 0
1347#define EUR_CR_USE_CODE_BASE_SIZE_UINT32 16
1348#define EUR_CR_USE_CODE_BASE_NUM_ENTRIES 16
1349
1350#endif
1351
diff --git a/drivers/gpu/pvr/sgx_bridge.h b/drivers/gpu/pvr/sgx_bridge.h
index 10e59196ef9..3f43f76971e 100644
--- a/drivers/gpu/pvr/sgx_bridge.h
+++ b/drivers/gpu/pvr/sgx_bridge.h
@@ -27,7 +27,11 @@
27#if !defined(__SGX_BRIDGE_H__) 27#if !defined(__SGX_BRIDGE_H__)
28#define __SGX_BRIDGE_H__ 28#define __SGX_BRIDGE_H__
29 29
30#if defined (SUPPORT_SID_INTERFACE)
31#include "sgxapi.h"
32#else
30#include "sgxapi_km.h" 33#include "sgxapi_km.h"
34#endif
31#include "sgxinfo.h" 35#include "sgxinfo.h"
32#include "pvr_bridge.h" 36#include "pvr_bridge.h"
33 37
@@ -106,8 +110,13 @@ typedef struct PVRSRV_BRIDGE_OUT_GETPHYSPAGEADDR
106typedef struct PVRSRV_BRIDGE_IN_SGX_GETMMU_PDADDR_TAG 110typedef struct PVRSRV_BRIDGE_IN_SGX_GETMMU_PDADDR_TAG
107{ 111{
108 IMG_UINT32 ui32BridgeFlags; 112 IMG_UINT32 ui32BridgeFlags;
113#if defined (SUPPORT_SID_INTERFACE)
114 IMG_SID hDevCookie;
115 IMG_SID hDevMemContext;
116#else
109 IMG_HANDLE hDevCookie; 117 IMG_HANDLE hDevCookie;
110 IMG_HANDLE hDevMemContext; 118 IMG_HANDLE hDevMemContext;
119#endif
111}PVRSRV_BRIDGE_IN_SGX_GETMMU_PDADDR; 120}PVRSRV_BRIDGE_IN_SGX_GETMMU_PDADDR;
112 121
113 122
@@ -121,7 +130,11 @@ typedef struct PVRSRV_BRIDGE_OUT_SGX_GETMMU_PDADDR_TAG
121typedef struct PVRSRV_BRIDGE_IN_GETCLIENTINFO_TAG 130typedef struct PVRSRV_BRIDGE_IN_GETCLIENTINFO_TAG
122{ 131{
123 IMG_UINT32 ui32BridgeFlags; 132 IMG_UINT32 ui32BridgeFlags;
133#if defined (SUPPORT_SID_INTERFACE)
134 IMG_SID hDevCookie;
135#else
124 IMG_HANDLE hDevCookie; 136 IMG_HANDLE hDevCookie;
137#endif
125}PVRSRV_BRIDGE_IN_GETCLIENTINFO; 138}PVRSRV_BRIDGE_IN_GETCLIENTINFO;
126 139
127 140
@@ -135,7 +148,11 @@ typedef struct PVRSRV_BRIDGE_OUT_GETINTERNALDEVINFO_TAG
135typedef struct PVRSRV_BRIDGE_IN_GETINTERNALDEVINFO_TAG 148typedef struct PVRSRV_BRIDGE_IN_GETINTERNALDEVINFO_TAG
136{ 149{
137 IMG_UINT32 ui32BridgeFlags; 150 IMG_UINT32 ui32BridgeFlags;
151#if defined (SUPPORT_SID_INTERFACE)
152 IMG_SID hDevCookie;
153#else
138 IMG_HANDLE hDevCookie; 154 IMG_HANDLE hDevCookie;
155#endif
139}PVRSRV_BRIDGE_IN_GETINTERNALDEVINFO; 156}PVRSRV_BRIDGE_IN_GETINTERNALDEVINFO;
140 157
141 158
@@ -148,8 +165,12 @@ typedef struct PVRSRV_BRIDGE_OUT_GETCLIENTINFO_TAG
148 165
149typedef struct PVRSRV_BRIDGE_IN_RELEASECLIENTINFO_TAG 166typedef struct PVRSRV_BRIDGE_IN_RELEASECLIENTINFO_TAG
150{ 167{
151 IMG_UINT32 ui32BridgeFlags; 168 IMG_UINT32 ui32BridgeFlags;
152 IMG_HANDLE hDevCookie; 169#if defined (SUPPORT_SID_INTERFACE)
170 IMG_SID hDevCookie;
171#else
172 IMG_HANDLE hDevCookie;
173#endif
153 SGX_CLIENT_INFO sClientInfo; 174 SGX_CLIENT_INFO sClientInfo;
154}PVRSRV_BRIDGE_IN_RELEASECLIENTINFO; 175}PVRSRV_BRIDGE_IN_RELEASECLIENTINFO;
155 176
@@ -157,14 +178,22 @@ typedef struct PVRSRV_BRIDGE_IN_RELEASECLIENTINFO_TAG
157typedef struct PVRSRV_BRIDGE_IN_ISPBREAKPOLL_TAG 178typedef struct PVRSRV_BRIDGE_IN_ISPBREAKPOLL_TAG
158{ 179{
159 IMG_UINT32 ui32BridgeFlags; 180 IMG_UINT32 ui32BridgeFlags;
181#if defined (SUPPORT_SID_INTERFACE)
182 IMG_SID hDevCookie;
183#else
160 IMG_HANDLE hDevCookie; 184 IMG_HANDLE hDevCookie;
185#endif
161}PVRSRV_BRIDGE_IN_ISPBREAKPOLL; 186}PVRSRV_BRIDGE_IN_ISPBREAKPOLL;
162 187
163 188
164typedef struct PVRSRV_BRIDGE_IN_DOKICK_TAG 189typedef struct PVRSRV_BRIDGE_IN_DOKICK_TAG
165{ 190{
166 IMG_UINT32 ui32BridgeFlags; 191 IMG_UINT32 ui32BridgeFlags;
192#if defined (SUPPORT_SID_INTERFACE)
193 IMG_SID hDevCookie;
194#else
167 IMG_HANDLE hDevCookie; 195 IMG_HANDLE hDevCookie;
196#endif
168 SGX_CCB_KICK sCCBKick; 197 SGX_CCB_KICK sCCBKick;
169}PVRSRV_BRIDGE_IN_DOKICK; 198}PVRSRV_BRIDGE_IN_DOKICK;
170 199
@@ -172,7 +201,11 @@ typedef struct PVRSRV_BRIDGE_IN_DOKICK_TAG
172typedef struct PVRSRV_BRIDGE_IN_SGX_SCHEDULE_PROCESS_QUEUES_TAG 201typedef struct PVRSRV_BRIDGE_IN_SGX_SCHEDULE_PROCESS_QUEUES_TAG
173{ 202{
174 IMG_UINT32 ui32BridgeFlags; 203 IMG_UINT32 ui32BridgeFlags;
204#if defined (SUPPORT_SID_INTERFACE)
205 IMG_SID hDevCookie;
206#else
175 IMG_HANDLE hDevCookie; 207 IMG_HANDLE hDevCookie;
208#endif
176}PVRSRV_BRIDGE_IN_SGX_SCHEDULE_PROCESS_QUEUES; 209}PVRSRV_BRIDGE_IN_SGX_SCHEDULE_PROCESS_QUEUES;
177 210
178 211
@@ -181,7 +214,11 @@ typedef struct PVRSRV_BRIDGE_IN_SGX_SCHEDULE_PROCESS_QUEUES_TAG
181typedef struct PVRSRV_BRIDGE_IN_SUBMITTRANSFER_TAG 214typedef struct PVRSRV_BRIDGE_IN_SUBMITTRANSFER_TAG
182{ 215{
183 IMG_UINT32 ui32BridgeFlags; 216 IMG_UINT32 ui32BridgeFlags;
217#if defined (SUPPORT_SID_INTERFACE)
218 IMG_SID hDevCookie;
219#else
184 IMG_HANDLE hDevCookie; 220 IMG_HANDLE hDevCookie;
221#endif
185 PVRSRV_TRANSFER_SGX_KICK sKick; 222 PVRSRV_TRANSFER_SGX_KICK sKick;
186}PVRSRV_BRIDGE_IN_SUBMITTRANSFER; 223}PVRSRV_BRIDGE_IN_SUBMITTRANSFER;
187 224
@@ -190,8 +227,12 @@ typedef struct PVRSRV_BRIDGE_IN_SUBMITTRANSFER_TAG
190typedef struct PVRSRV_BRIDGE_IN_SUBMIT2D_TAG 227typedef struct PVRSRV_BRIDGE_IN_SUBMIT2D_TAG
191{ 228{
192 IMG_UINT32 ui32BridgeFlags; 229 IMG_UINT32 ui32BridgeFlags;
230#if defined (SUPPORT_SID_INTERFACE)
231 IMG_SID hDevCookie;
232#else
193 IMG_HANDLE hDevCookie; 233 IMG_HANDLE hDevCookie;
194 PVRSRV_2D_SGX_KICK sKick; 234#endif
235 PVRSRV_2D_SGX_KICK sKick;
195} PVRSRV_BRIDGE_IN_SUBMIT2D; 236} PVRSRV_BRIDGE_IN_SUBMIT2D;
196#endif 237#endif
197#endif 238#endif
@@ -200,7 +241,11 @@ typedef struct PVRSRV_BRIDGE_IN_SUBMIT2D_TAG
200typedef struct PVRSRV_BRIDGE_IN_READREGDWORD_TAG 241typedef struct PVRSRV_BRIDGE_IN_READREGDWORD_TAG
201{ 242{
202 IMG_UINT32 ui32BridgeFlags; 243 IMG_UINT32 ui32BridgeFlags;
244#if defined (SUPPORT_SID_INTERFACE)
245 IMG_SID hDevCookie;
246#else
203 IMG_HANDLE hDevCookie; 247 IMG_HANDLE hDevCookie;
248#endif
204 IMG_PCHAR pszKey; 249 IMG_PCHAR pszKey;
205 IMG_PCHAR pszValue; 250 IMG_PCHAR pszValue;
206}PVRSRV_BRIDGE_IN_READREGDWORD; 251}PVRSRV_BRIDGE_IN_READREGDWORD;
@@ -216,14 +261,22 @@ typedef struct PVRSRV_BRIDGE_OUT_READREGDWORD_TAG
216typedef struct PVRSRV_BRIDGE_IN_SGXGETMISCINFO_TAG 261typedef struct PVRSRV_BRIDGE_IN_SGXGETMISCINFO_TAG
217{ 262{
218 IMG_UINT32 ui32BridgeFlags; 263 IMG_UINT32 ui32BridgeFlags;
264#if defined (SUPPORT_SID_INTERFACE)
265 IMG_SID hDevCookie;
266#else
219 IMG_HANDLE hDevCookie; 267 IMG_HANDLE hDevCookie;
268#endif
220 SGX_MISC_INFO *psMiscInfo; 269 SGX_MISC_INFO *psMiscInfo;
221}PVRSRV_BRIDGE_IN_SGXGETMISCINFO; 270}PVRSRV_BRIDGE_IN_SGXGETMISCINFO;
222 271
223typedef struct PVRSRV_BRIDGE_IN_SGXINFO_FOR_SRVINIT_TAG 272typedef struct PVRSRV_BRIDGE_IN_SGXINFO_FOR_SRVINIT_TAG
224{ 273{
225 IMG_UINT32 ui32BridgeFlags; 274 IMG_UINT32 ui32BridgeFlags;
275#if defined (SUPPORT_SID_INTERFACE)
276 IMG_SID hDevCookie;
277#else
226 IMG_HANDLE hDevCookie; 278 IMG_HANDLE hDevCookie;
279#endif
227}PVRSRV_BRIDGE_IN_SGXINFO_FOR_SRVINIT; 280}PVRSRV_BRIDGE_IN_SGXINFO_FOR_SRVINIT;
228 281
229typedef struct PVRSRV_BRIDGE_OUT_SGXINFO_FOR_SRVINIT_TAG 282typedef struct PVRSRV_BRIDGE_OUT_SGXINFO_FOR_SRVINIT_TAG
@@ -235,16 +288,32 @@ typedef struct PVRSRV_BRIDGE_OUT_SGXINFO_FOR_SRVINIT_TAG
235typedef struct PVRSRV_BRIDGE_IN_SGXDEVINITPART2_TAG 288typedef struct PVRSRV_BRIDGE_IN_SGXDEVINITPART2_TAG
236{ 289{
237 IMG_UINT32 ui32BridgeFlags; 290 IMG_UINT32 ui32BridgeFlags;
291#if defined (SUPPORT_SID_INTERFACE)
292 IMG_SID hDevCookie;
293#else
238 IMG_HANDLE hDevCookie; 294 IMG_HANDLE hDevCookie;
295#endif
239 SGX_BRIDGE_INIT_INFO sInitInfo; 296 SGX_BRIDGE_INIT_INFO sInitInfo;
240}PVRSRV_BRIDGE_IN_SGXDEVINITPART2; 297}PVRSRV_BRIDGE_IN_SGXDEVINITPART2;
241 298
299typedef struct PVRSRV_BRIDGE_OUT_SGXDEVINITPART2_TAG
300{
301 PVRSRV_ERROR eError;
302 IMG_UINT32 ui32KMBuildOptions;
303
304}PVRSRV_BRIDGE_OUT_SGXDEVINITPART2;
305
242 306
243typedef struct PVRSRV_BRIDGE_IN_2DQUERYBLTSCOMPLETE_TAG 307typedef struct PVRSRV_BRIDGE_IN_2DQUERYBLTSCOMPLETE_TAG
244{ 308{
245 IMG_UINT32 ui32BridgeFlags; 309 IMG_UINT32 ui32BridgeFlags;
310#if defined (SUPPORT_SID_INTERFACE)
311 IMG_SID hDevCookie;
312 IMG_SID hKernSyncInfo;
313#else
246 IMG_HANDLE hDevCookie; 314 IMG_HANDLE hDevCookie;
247 IMG_HANDLE hKernSyncInfo; 315 IMG_HANDLE hKernSyncInfo;
316#endif
248 IMG_BOOL bWaitForComplete; 317 IMG_BOOL bWaitForComplete;
249}PVRSRV_BRIDGE_IN_2DQUERYBLTSCOMPLETE; 318}PVRSRV_BRIDGE_IN_2DQUERYBLTSCOMPLETE;
250 319
@@ -254,13 +323,26 @@ typedef struct PVRSRV_BRIDGE_IN_2DQUERYBLTSCOMPLETE_TAG
254typedef struct PVRSRV_BRIDGE_IN_SGXFINDSHAREDPBDESC_TAG 323typedef struct PVRSRV_BRIDGE_IN_SGXFINDSHAREDPBDESC_TAG
255{ 324{
256 IMG_UINT32 ui32BridgeFlags; 325 IMG_UINT32 ui32BridgeFlags;
326#if defined (SUPPORT_SID_INTERFACE)
327 IMG_SID hDevCookie;
328#else
257 IMG_HANDLE hDevCookie; 329 IMG_HANDLE hDevCookie;
258 IMG_BOOL bLockOnFailure; 330#endif
331 IMG_BOOL bLockOnFailure;
259 IMG_UINT32 ui32TotalPBSize; 332 IMG_UINT32 ui32TotalPBSize;
260}PVRSRV_BRIDGE_IN_SGXFINDSHAREDPBDESC; 333}PVRSRV_BRIDGE_IN_SGXFINDSHAREDPBDESC;
261 334
262typedef struct PVRSRV_BRIDGE_OUT_SGXFINDSHAREDPBDESC_TAG 335typedef struct PVRSRV_BRIDGE_OUT_SGXFINDSHAREDPBDESC_TAG
263{ 336{
337#if defined (SUPPORT_SID_INTERFACE)
338 IMG_SID hKernelMemInfo;
339 IMG_SID hSharedPBDesc;
340 IMG_SID hSharedPBDescKernelMemInfoHandle;
341 IMG_SID hHWPBDescKernelMemInfoHandle;
342 IMG_SID hBlockKernelMemInfoHandle;
343 IMG_SID hHWBlockKernelMemInfoHandle;
344 IMG_SID ahSharedPBDescSubKernelMemInfoHandles[PVRSRV_BRIDGE_SGX_SHAREDPBDESC_MAX_SUBMEMINFOS];
345#else
264 IMG_HANDLE hKernelMemInfo; 346 IMG_HANDLE hKernelMemInfo;
265 IMG_HANDLE hSharedPBDesc; 347 IMG_HANDLE hSharedPBDesc;
266 IMG_HANDLE hSharedPBDescKernelMemInfoHandle; 348 IMG_HANDLE hSharedPBDescKernelMemInfoHandle;
@@ -268,6 +350,7 @@ typedef struct PVRSRV_BRIDGE_OUT_SGXFINDSHAREDPBDESC_TAG
268 IMG_HANDLE hBlockKernelMemInfoHandle; 350 IMG_HANDLE hBlockKernelMemInfoHandle;
269 IMG_HANDLE hHWBlockKernelMemInfoHandle; 351 IMG_HANDLE hHWBlockKernelMemInfoHandle;
270 IMG_HANDLE ahSharedPBDescSubKernelMemInfoHandles[PVRSRV_BRIDGE_SGX_SHAREDPBDESC_MAX_SUBMEMINFOS]; 352 IMG_HANDLE ahSharedPBDescSubKernelMemInfoHandles[PVRSRV_BRIDGE_SGX_SHAREDPBDESC_MAX_SUBMEMINFOS];
353#endif
271 IMG_UINT32 ui32SharedPBDescSubKernelMemInfoHandlesCount; 354 IMG_UINT32 ui32SharedPBDescSubKernelMemInfoHandlesCount;
272 PVRSRV_ERROR eError; 355 PVRSRV_ERROR eError;
273}PVRSRV_BRIDGE_OUT_SGXFINDSHAREDPBDESC; 356}PVRSRV_BRIDGE_OUT_SGXFINDSHAREDPBDESC;
@@ -275,7 +358,11 @@ typedef struct PVRSRV_BRIDGE_OUT_SGXFINDSHAREDPBDESC_TAG
275typedef struct PVRSRV_BRIDGE_IN_SGXUNREFSHAREDPBDESC_TAG 358typedef struct PVRSRV_BRIDGE_IN_SGXUNREFSHAREDPBDESC_TAG
276{ 359{
277 IMG_UINT32 ui32BridgeFlags; 360 IMG_UINT32 ui32BridgeFlags;
361#if defined (SUPPORT_SID_INTERFACE)
362 IMG_SID hSharedPBDesc;
363#else
278 IMG_HANDLE hSharedPBDesc; 364 IMG_HANDLE hSharedPBDesc;
365#endif
279}PVRSRV_BRIDGE_IN_SGXUNREFSHAREDPBDESC; 366}PVRSRV_BRIDGE_IN_SGXUNREFSHAREDPBDESC;
280 367
281typedef struct PVRSRV_BRIDGE_OUT_SGXUNREFSHAREDPBDESC_TAG 368typedef struct PVRSRV_BRIDGE_OUT_SGXUNREFSHAREDPBDESC_TAG
@@ -287,20 +374,34 @@ typedef struct PVRSRV_BRIDGE_OUT_SGXUNREFSHAREDPBDESC_TAG
287typedef struct PVRSRV_BRIDGE_IN_SGXADDSHAREDPBDESC_TAG 374typedef struct PVRSRV_BRIDGE_IN_SGXADDSHAREDPBDESC_TAG
288{ 375{
289 IMG_UINT32 ui32BridgeFlags; 376 IMG_UINT32 ui32BridgeFlags;
377 IMG_UINT32 ui32TotalPBSize;
378#if defined (SUPPORT_SID_INTERFACE)
379 IMG_SID hDevCookie;
380 IMG_SID hSharedPBDescKernelMemInfo;
381 IMG_SID hHWPBDescKernelMemInfo;
382 IMG_SID hBlockKernelMemInfo;
383 IMG_SID hHWBlockKernelMemInfo;
384 IMG_SID *phKernelMemInfoHandles;
385#else
290 IMG_HANDLE hDevCookie; 386 IMG_HANDLE hDevCookie;
291 IMG_HANDLE hSharedPBDescKernelMemInfo; 387 IMG_HANDLE hSharedPBDescKernelMemInfo;
292 IMG_HANDLE hHWPBDescKernelMemInfo; 388 IMG_HANDLE hHWPBDescKernelMemInfo;
293 IMG_HANDLE hBlockKernelMemInfo; 389 IMG_HANDLE hBlockKernelMemInfo;
294 IMG_HANDLE hHWBlockKernelMemInfo; 390 IMG_HANDLE hHWBlockKernelMemInfo;
295 IMG_UINT32 ui32TotalPBSize;
296 IMG_HANDLE *phKernelMemInfoHandles; 391 IMG_HANDLE *phKernelMemInfoHandles;
392#endif
297 IMG_UINT32 ui32KernelMemInfoHandlesCount; 393 IMG_UINT32 ui32KernelMemInfoHandlesCount;
394 IMG_DEV_VIRTADDR sHWPBDescDevVAddr;
298}PVRSRV_BRIDGE_IN_SGXADDSHAREDPBDESC; 395}PVRSRV_BRIDGE_IN_SGXADDSHAREDPBDESC;
299 396
300typedef struct PVRSRV_BRIDGE_OUT_SGXADDSHAREDPBDESC_TAG 397typedef struct PVRSRV_BRIDGE_OUT_SGXADDSHAREDPBDESC_TAG
301{ 398{
302 PVRSRV_ERROR eError; 399 PVRSRV_ERROR eError;
400#if defined (SUPPORT_SID_INTERFACE)
401 IMG_SID hSharedPBDesc;
402#else
303 IMG_HANDLE hSharedPBDesc; 403 IMG_HANDLE hSharedPBDesc;
404#endif
304}PVRSRV_BRIDGE_OUT_SGXADDSHAREDPBDESC; 405}PVRSRV_BRIDGE_OUT_SGXADDSHAREDPBDESC;
305 406
306 407
@@ -316,9 +417,15 @@ typedef struct PVRSRV_BRIDGE_IN_PDUMP_BUFFER_ARRAY_TAG
316typedef struct PVRSRV_BRIDGE_IN_PDUMP_3D_SIGNATURE_REGISTERS_TAG 417typedef struct PVRSRV_BRIDGE_IN_PDUMP_3D_SIGNATURE_REGISTERS_TAG
317{ 418{
318 IMG_UINT32 ui32BridgeFlags; 419 IMG_UINT32 ui32BridgeFlags;
420#if defined (SUPPORT_SID_INTERFACE)
421 IMG_SID hDevCookie;
422 IMG_SID hDevMemContext;
423#else
319 IMG_HANDLE hDevCookie; 424 IMG_HANDLE hDevCookie;
425 IMG_HANDLE hDevMemContext;
426#endif
320 IMG_UINT32 ui32DumpFrameNum; 427 IMG_UINT32 ui32DumpFrameNum;
321 IMG_BOOL bLastFrame; 428 IMG_BOOL bLastFrame;
322 IMG_UINT32 *pui32Registers; 429 IMG_UINT32 *pui32Registers;
323 IMG_UINT32 ui32NumRegisters; 430 IMG_UINT32 ui32NumRegisters;
324}PVRSRV_BRIDGE_IN_PDUMP_3D_SIGNATURE_REGISTERS; 431}PVRSRV_BRIDGE_IN_PDUMP_3D_SIGNATURE_REGISTERS;
@@ -326,7 +433,11 @@ typedef struct PVRSRV_BRIDGE_IN_PDUMP_3D_SIGNATURE_REGISTERS_TAG
326typedef struct PVRSRV_BRIDGE_IN_PDUMPCOUNTER_REGISTERS_TAG 433typedef struct PVRSRV_BRIDGE_IN_PDUMPCOUNTER_REGISTERS_TAG
327{ 434{
328 IMG_UINT32 ui32BridgeFlags; 435 IMG_UINT32 ui32BridgeFlags;
436#if defined (SUPPORT_SID_INTERFACE)
437 IMG_SID hDevCookie;
438#else
329 IMG_HANDLE hDevCookie; 439 IMG_HANDLE hDevCookie;
440#endif
330 IMG_UINT32 ui32DumpFrameNum; 441 IMG_UINT32 ui32DumpFrameNum;
331 IMG_BOOL bLastFrame; 442 IMG_BOOL bLastFrame;
332 IMG_UINT32 *pui32Registers; 443 IMG_UINT32 *pui32Registers;
@@ -336,7 +447,11 @@ typedef struct PVRSRV_BRIDGE_IN_PDUMPCOUNTER_REGISTERS_TAG
336typedef struct PVRSRV_BRIDGE_IN_PDUMP_TA_SIGNATURE_REGISTERS_TAG 447typedef struct PVRSRV_BRIDGE_IN_PDUMP_TA_SIGNATURE_REGISTERS_TAG
337{ 448{
338 IMG_UINT32 ui32BridgeFlags; 449 IMG_UINT32 ui32BridgeFlags;
450#if defined (SUPPORT_SID_INTERFACE)
451 IMG_SID hDevCookie;
452#else
339 IMG_HANDLE hDevCookie; 453 IMG_HANDLE hDevCookie;
454#endif
340 IMG_UINT32 ui32DumpFrameNum; 455 IMG_UINT32 ui32DumpFrameNum;
341 IMG_UINT32 ui32TAKickCount; 456 IMG_UINT32 ui32TAKickCount;
342 IMG_BOOL bLastFrame; 457 IMG_BOOL bLastFrame;
@@ -347,7 +462,13 @@ typedef struct PVRSRV_BRIDGE_IN_PDUMP_TA_SIGNATURE_REGISTERS_TAG
347typedef struct PVRSRV_BRIDGE_IN_PDUMP_HWPERFCB_TAG 462typedef struct PVRSRV_BRIDGE_IN_PDUMP_HWPERFCB_TAG
348{ 463{
349 IMG_UINT32 ui32BridgeFlags; 464 IMG_UINT32 ui32BridgeFlags;
465#if defined (SUPPORT_SID_INTERFACE)
466 IMG_SID hDevCookie;
467 IMG_SID hDevMemContext;
468#else
350 IMG_HANDLE hDevCookie; 469 IMG_HANDLE hDevCookie;
470 IMG_HANDLE hDevMemContext;
471#endif
351 IMG_CHAR szFileName[PVRSRV_PDUMP_MAX_FILENAME_SIZE]; 472 IMG_CHAR szFileName[PVRSRV_PDUMP_MAX_FILENAME_SIZE];
352 IMG_UINT32 ui32FileOffset; 473 IMG_UINT32 ui32FileOffset;
353 IMG_UINT32 ui32PDumpFlags; 474 IMG_UINT32 ui32PDumpFlags;
@@ -357,12 +478,19 @@ typedef struct PVRSRV_BRIDGE_IN_PDUMP_HWPERFCB_TAG
357typedef struct PVRSRV_BRIDGE_IN_PDUMP_SAVEMEM 478typedef struct PVRSRV_BRIDGE_IN_PDUMP_SAVEMEM
358{ 479{
359 IMG_UINT32 ui32BridgeFlags; 480 IMG_UINT32 ui32BridgeFlags;
481#if defined (SUPPORT_SID_INTERFACE)
482 IMG_SID hDevCookie;
483 IMG_SID hDevMemContext;
484#else
360 IMG_HANDLE hDevCookie; 485 IMG_HANDLE hDevCookie;
486#endif
361 IMG_CHAR szFileName[PVRSRV_PDUMP_MAX_FILENAME_SIZE]; 487 IMG_CHAR szFileName[PVRSRV_PDUMP_MAX_FILENAME_SIZE];
362 IMG_UINT32 ui32FileOffset; 488 IMG_UINT32 ui32FileOffset;
363 IMG_DEV_VIRTADDR sDevVAddr; 489 IMG_DEV_VIRTADDR sDevVAddr;
364 IMG_UINT32 ui32Size; 490 IMG_UINT32 ui32Size;
365 IMG_UINT32 ui32DataMaster; 491#if !defined (SUPPORT_SID_INTERFACE)
492 IMG_HANDLE hDevMemContext;
493#endif
366 IMG_UINT32 ui32PDumpFlags; 494 IMG_UINT32 ui32PDumpFlags;
367 495
368}PVRSRV_BRIDGE_IN_PDUMP_SAVEMEM; 496}PVRSRV_BRIDGE_IN_PDUMP_SAVEMEM;
@@ -372,47 +500,77 @@ typedef struct PVRSRV_BRIDGE_IN_PDUMP_SAVEMEM
372typedef struct PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_RENDER_CONTEXT_TAG 500typedef struct PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_RENDER_CONTEXT_TAG
373{ 501{
374 IMG_UINT32 ui32BridgeFlags; 502 IMG_UINT32 ui32BridgeFlags;
503#if defined (SUPPORT_SID_INTERFACE)
504 IMG_SID hDevCookie;
505#else
375 IMG_HANDLE hDevCookie; 506 IMG_HANDLE hDevCookie;
507#endif
376 IMG_DEV_VIRTADDR sHWRenderContextDevVAddr; 508 IMG_DEV_VIRTADDR sHWRenderContextDevVAddr;
377}PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_RENDER_CONTEXT; 509}PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_RENDER_CONTEXT;
378 510
379typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_RENDER_CONTEXT_TAG 511typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_RENDER_CONTEXT_TAG
380{ 512{
381 PVRSRV_ERROR eError; 513 PVRSRV_ERROR eError;
514#if defined (SUPPORT_SID_INTERFACE)
515 IMG_SID hHWRenderContext;
516#else
382 IMG_HANDLE hHWRenderContext; 517 IMG_HANDLE hHWRenderContext;
518#endif
383}PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_RENDER_CONTEXT; 519}PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_RENDER_CONTEXT;
384 520
385typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_RENDER_CONTEXT_TAG 521typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_RENDER_CONTEXT_TAG
386{ 522{
387 IMG_UINT32 ui32BridgeFlags; 523 IMG_UINT32 ui32BridgeFlags;
524#if defined (SUPPORT_SID_INTERFACE)
525 IMG_SID hDevCookie;
526 IMG_SID hHWRenderContext;
527#else
388 IMG_HANDLE hDevCookie; 528 IMG_HANDLE hDevCookie;
389 IMG_HANDLE hHWRenderContext; 529 IMG_HANDLE hHWRenderContext;
530#endif
390}PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_RENDER_CONTEXT; 531}PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_RENDER_CONTEXT;
391 532
392typedef struct PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_TRANSFER_CONTEXT_TAG 533typedef struct PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_TRANSFER_CONTEXT_TAG
393{ 534{
394 IMG_UINT32 ui32BridgeFlags; 535 IMG_UINT32 ui32BridgeFlags;
536#if defined (SUPPORT_SID_INTERFACE)
537 IMG_SID hDevCookie;
538#else
395 IMG_HANDLE hDevCookie; 539 IMG_HANDLE hDevCookie;
540#endif
396 IMG_DEV_VIRTADDR sHWTransferContextDevVAddr; 541 IMG_DEV_VIRTADDR sHWTransferContextDevVAddr;
397}PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_TRANSFER_CONTEXT; 542}PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_TRANSFER_CONTEXT;
398 543
399typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_TRANSFER_CONTEXT_TAG 544typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_TRANSFER_CONTEXT_TAG
400{ 545{
401 PVRSRV_ERROR eError; 546 PVRSRV_ERROR eError;
547#if defined (SUPPORT_SID_INTERFACE)
548 IMG_SID hHWTransferContext;
549#else
402 IMG_HANDLE hHWTransferContext; 550 IMG_HANDLE hHWTransferContext;
551#endif
403}PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_TRANSFER_CONTEXT; 552}PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_TRANSFER_CONTEXT;
404 553
405typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_TRANSFER_CONTEXT_TAG 554typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_TRANSFER_CONTEXT_TAG
406{ 555{
407 IMG_UINT32 ui32BridgeFlags; 556 IMG_UINT32 ui32BridgeFlags;
557#if defined (SUPPORT_SID_INTERFACE)
558 IMG_SID hDevCookie;
559 IMG_SID hHWTransferContext;
560#else
408 IMG_HANDLE hDevCookie; 561 IMG_HANDLE hDevCookie;
409 IMG_HANDLE hHWTransferContext; 562 IMG_HANDLE hHWTransferContext;
563#endif
410}PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_TRANSFER_CONTEXT; 564}PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_TRANSFER_CONTEXT;
411 565
412typedef struct PVRSRV_BRIDGE_IN_SGX_FLUSH_HW_RENDER_TARGET_TAG 566typedef struct PVRSRV_BRIDGE_IN_SGX_FLUSH_HW_RENDER_TARGET_TAG
413{ 567{
414 IMG_UINT32 ui32BridgeFlags; 568 IMG_UINT32 ui32BridgeFlags;
569#if defined (SUPPORT_SID_INTERFACE)
570 IMG_SID hDevCookie;
571#else
415 IMG_HANDLE hDevCookie; 572 IMG_HANDLE hDevCookie;
573#endif
416 IMG_DEV_VIRTADDR sHWRTDataSetDevVAddr; 574 IMG_DEV_VIRTADDR sHWRTDataSetDevVAddr;
417}PVRSRV_BRIDGE_IN_SGX_FLUSH_HW_RENDER_TARGET; 575}PVRSRV_BRIDGE_IN_SGX_FLUSH_HW_RENDER_TARGET;
418 576
@@ -421,21 +579,34 @@ typedef struct PVRSRV_BRIDGE_IN_SGX_FLUSH_HW_RENDER_TARGET_TAG
421typedef struct PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_2D_CONTEXT_TAG 579typedef struct PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_2D_CONTEXT_TAG
422{ 580{
423 IMG_UINT32 ui32BridgeFlags; 581 IMG_UINT32 ui32BridgeFlags;
582#if defined (SUPPORT_SID_INTERFACE)
583 IMG_SID hDevCookie;
584#else
424 IMG_HANDLE hDevCookie; 585 IMG_HANDLE hDevCookie;
586#endif
425 IMG_DEV_VIRTADDR sHW2DContextDevVAddr; 587 IMG_DEV_VIRTADDR sHW2DContextDevVAddr;
426}PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_2D_CONTEXT; 588}PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_2D_CONTEXT;
427 589
428typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_2D_CONTEXT_TAG 590typedef struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_2D_CONTEXT_TAG
429{ 591{
430 PVRSRV_ERROR eError; 592 PVRSRV_ERROR eError;
593#if defined (SUPPORT_SID_INTERFACE)
594 IMG_SID hHW2DContext;
595#else
431 IMG_HANDLE hHW2DContext; 596 IMG_HANDLE hHW2DContext;
597#endif
432}PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_2D_CONTEXT; 598}PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_2D_CONTEXT;
433 599
434typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_2D_CONTEXT_TAG 600typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_2D_CONTEXT_TAG
435{ 601{
436 IMG_UINT32 ui32BridgeFlags; 602 IMG_UINT32 ui32BridgeFlags;
603#if defined (SUPPORT_SID_INTERFACE)
604 IMG_SID hDevCookie;
605 IMG_SID hHW2DContext;
606#else
437 IMG_HANDLE hDevCookie; 607 IMG_HANDLE hDevCookie;
438 IMG_HANDLE hHW2DContext; 608 IMG_HANDLE hHW2DContext;
609#endif
439}PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_2D_CONTEXT; 610}PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_2D_CONTEXT;
440 611
441#define SGX2D_MAX_BLT_CMD_SIZ 256 612#define SGX2D_MAX_BLT_CMD_SIZ 256
@@ -445,7 +616,11 @@ typedef struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_2D_CONTEXT_TAG
445typedef struct PVRSRV_BRIDGE_IN_SGX_READ_HWPERF_CB_TAG 616typedef struct PVRSRV_BRIDGE_IN_SGX_READ_HWPERF_CB_TAG
446{ 617{
447 IMG_UINT32 ui32BridgeFlags; 618 IMG_UINT32 ui32BridgeFlags;
619#if defined (SUPPORT_SID_INTERFACE)
620 IMG_SID hDevCookie;
621#else
448 IMG_HANDLE hDevCookie; 622 IMG_HANDLE hDevCookie;
623#endif
449 IMG_UINT32 ui32ArraySize; 624 IMG_UINT32 ui32ArraySize;
450 PVRSRV_SGX_HWPERF_CB_ENTRY *psHWPerfCBData; 625 PVRSRV_SGX_HWPERF_CB_ENTRY *psHWPerfCBData;
451} PVRSRV_BRIDGE_IN_SGX_READ_HWPERF_CB; 626} PVRSRV_BRIDGE_IN_SGX_READ_HWPERF_CB;
diff --git a/drivers/gpu/pvr/sgx_mkif_km.h b/drivers/gpu/pvr/sgx_mkif_km.h
index bd8f58b02a2..839cb87bd66 100644
--- a/drivers/gpu/pvr/sgx_mkif_km.h
+++ b/drivers/gpu/pvr/sgx_mkif_km.h
@@ -32,29 +32,25 @@
32#include "sgxapi_km.h" 32#include "sgxapi_km.h"
33 33
34 34
35#if !defined (SGX_MP_CORE_SELECT)
35#if defined(SGX_FEATURE_MP) 36#if defined(SGX_FEATURE_MP)
36 #define SGX_REG_BANK_SHIFT (12) 37 #define SGX_REG_BANK_SHIFT (14)
37 #define SGX_REG_BANK_SIZE (0x4000) 38 #define SGX_REG_BANK_SIZE (1 << SGX_REG_BANK_SHIFT)
38 #if defined(SGX541) 39 #define SGX_REG_BANK_BASE_INDEX (2)
39 #define SGX_REG_BANK_BASE_INDEX (1) 40 #define SGX_REG_BANK_MASTER_INDEX (1)
40 #define SGX_REG_BANK_MASTER_INDEX (SGX_REG_BANK_BASE_INDEX + SGX_FEATURE_MP_CORE_COUNT)
41 #else
42 #define SGX_REG_BANK_BASE_INDEX (2)
43 #define SGX_REG_BANK_MASTER_INDEX (1)
44 #endif
45 #define SGX_MP_CORE_SELECT(x,i) (x + ((i + SGX_REG_BANK_BASE_INDEX) * SGX_REG_BANK_SIZE)) 41 #define SGX_MP_CORE_SELECT(x,i) (x + ((i + SGX_REG_BANK_BASE_INDEX) * SGX_REG_BANK_SIZE))
46 #define SGX_MP_MASTER_SELECT(x) (x + (SGX_REG_BANK_MASTER_INDEX * SGX_REG_BANK_SIZE)) 42 #define SGX_MP_MASTER_SELECT(x) (x + (SGX_REG_BANK_MASTER_INDEX * SGX_REG_BANK_SIZE))
47#else 43#else
48 #define SGX_MP_CORE_SELECT(x,i) (x) 44 #define SGX_MP_CORE_SELECT(x,i) (x)
49#endif 45#endif
46#endif
50 47
51 48
52typedef struct _SGXMKIF_COMMAND_ 49typedef struct _SGXMKIF_COMMAND_
53{ 50{
54 IMG_UINT32 ui32ServiceAddress; 51 IMG_UINT32 ui32ServiceAddress;
55 IMG_UINT32 ui32CacheControl; 52 IMG_UINT32 ui32CacheControl;
56 IMG_UINT32 ui32Data[4]; 53 IMG_UINT32 ui32Data[6];
57 IMG_UINT32 ui32Padding[2];
58} SGXMKIF_COMMAND; 54} SGXMKIF_COMMAND;
59 55
60 56
@@ -82,7 +78,7 @@ typedef struct _SGXMKIF_HOST_CTL_
82 volatile IMG_UINT32 ui32PowerStatus; 78 volatile IMG_UINT32 ui32PowerStatus;
83 volatile IMG_UINT32 ui32CleanupStatus; 79 volatile IMG_UINT32 ui32CleanupStatus;
84#if defined(FIX_HW_BRN_28889) 80#if defined(FIX_HW_BRN_28889)
85 volatile IMG_UINT32 ui32InvalStatus; 81 volatile IMG_UINT32 ui32InvalStatus;
86#endif 82#endif
87#if defined(SUPPORT_HW_RECOVERY) 83#if defined(SUPPORT_HW_RECOVERY)
88 IMG_UINT32 ui32uKernelDetectedLockups; 84 IMG_UINT32 ui32uKernelDetectedLockups;
@@ -99,6 +95,7 @@ typedef struct _SGXMKIF_HOST_CTL_
99 95
100 IMG_UINT32 ui32TimeWraps; 96 IMG_UINT32 ui32TimeWraps;
101 IMG_UINT32 ui32HostClock; 97 IMG_UINT32 ui32HostClock;
98 IMG_UINT32 ui32AssertFail;
102 99
103#if defined(SGX_FEATURE_EXTENDED_PERF_COUNTERS) 100#if defined(SGX_FEATURE_EXTENDED_PERF_COUNTERS)
104 IMG_UINT32 aui32PerfGroup[PVRSRV_SGX_HWPERF_NUM_COUNTERS]; 101 IMG_UINT32 aui32PerfGroup[PVRSRV_SGX_HWPERF_NUM_COUNTERS];
@@ -106,6 +103,10 @@ typedef struct _SGXMKIF_HOST_CTL_
106#else 103#else
107 IMG_UINT32 ui32PerfGroup; 104 IMG_UINT32 ui32PerfGroup;
108#endif 105#endif
106
107#if defined(FIX_HW_BRN_31939)
108 IMG_UINT32 ui32BRN31939Mem;
109#endif
109} SGXMKIF_HOST_CTL; 110} SGXMKIF_HOST_CTL;
110 111
111#define SGXMKIF_CMDTA_CTRLFLAGS_READY 0x00000001 112#define SGXMKIF_CMDTA_CTRLFLAGS_READY 0x00000001
@@ -171,14 +172,7 @@ typedef struct _SGXMKIF_TRANSFERCMD_SHARED_
171 172
172 173
173 IMG_UINT32 ui32NumDstSyncs; 174 IMG_UINT32 ui32NumDstSyncs;
174 PVRSRV_DEVICE_SYNC_OBJECT asDstSyncs[SGX_MAX_DST_SYNCS]; 175 PVRSRV_DEVICE_SYNC_OBJECT asDstSyncs[SGX_MAX_DST_SYNCS];
175
176 IMG_UINT32 ui32DstReadOpPendingVal;
177 IMG_DEV_VIRTADDR sDstReadOpsCompleteDevAddr;
178
179 IMG_UINT32 ui32DstWriteOpPendingVal;
180 IMG_DEV_VIRTADDR sDstWriteOpsCompleteDevAddr;
181
182 176
183 IMG_UINT32 ui32TASyncWriteOpsPendingVal; 177 IMG_UINT32 ui32TASyncWriteOpsPendingVal;
184 IMG_DEV_VIRTADDR sTASyncWriteOpsCompleteDevVAddr; 178 IMG_DEV_VIRTADDR sTASyncWriteOpsCompleteDevVAddr;
@@ -236,7 +230,7 @@ typedef struct _SGXMKIF_HWDEVICE_SYNC_LIST_
236#define PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE (1UL << 0) 230#define PVRSRV_USSE_EDM_CLEANUPCMD_COMPLETE (1UL << 0)
237 231
238#if defined(FIX_HW_BRN_28889) 232#if defined(FIX_HW_BRN_28889)
239#define PVRSRV_USSE_EDM_BIF_INVAL_COMPLETE (1UL << 0) 233#define PVRSRV_USSE_EDM_BIF_INVAL_COMPLETE (1UL << 0)
240#endif 234#endif
241 235
242#define PVRSRV_USSE_MISCINFO_READY 0x1UL 236#define PVRSRV_USSE_MISCINFO_READY 0x1UL
@@ -250,18 +244,21 @@ typedef struct _SGXMKIF_HWDEVICE_SYNC_LIST_
250#endif 244#endif
251 245
252 246
253#define PVRSRV_CLEANUPCMD_RT 0x1 247#define PVRSRV_CLEANUPCMD_RT 0x1U
254#define PVRSRV_CLEANUPCMD_RC 0x2 248#define PVRSRV_CLEANUPCMD_RC 0x2U
255#define PVRSRV_CLEANUPCMD_TC 0x3 249#define PVRSRV_CLEANUPCMD_TC 0x3U
256#define PVRSRV_CLEANUPCMD_2DC 0x4 250#define PVRSRV_CLEANUPCMD_2DC 0x4U
257#define PVRSRV_CLEANUPCMD_PB 0x5 251#define PVRSRV_CLEANUPCMD_PB 0x5U
258 252
259#define PVRSRV_POWERCMD_POWEROFF 0x1 253#define PVRSRV_POWERCMD_POWEROFF 0x1U
260#define PVRSRV_POWERCMD_IDLE 0x2 254#define PVRSRV_POWERCMD_IDLE 0x2U
261#define PVRSRV_POWERCMD_RESUME 0x3 255#define PVRSRV_POWERCMD_RESUME 0x3U
262 256
257#define PVRSRV_CTXSUSPCMD_SUSPEND 0x1U
258#define PVRSRV_CTXSUSPCMD_RESUME 0x2U
263 259
264#if defined(SGX_FEATURE_BIF_NUM_DIRLISTS) 260
261#if defined(SGX_FEATURE_MULTIPLE_MEM_CONTEXTS)
265#define SGX_BIF_DIR_LIST_INDEX_EDM (SGX_FEATURE_BIF_NUM_DIRLISTS - 1) 262#define SGX_BIF_DIR_LIST_INDEX_EDM (SGX_FEATURE_BIF_NUM_DIRLISTS - 1)
266#else 263#else
267#define SGX_BIF_DIR_LIST_INDEX_EDM (0) 264#define SGX_BIF_DIR_LIST_INDEX_EDM (0)
@@ -323,12 +320,16 @@ typedef struct _PVRSRV_SGX_MISCINFO_INFO
323typedef struct _SGXMKIF_HWPERF_CB_ENTRY_ 320typedef struct _SGXMKIF_HWPERF_CB_ENTRY_
324{ 321{
325 IMG_UINT32 ui32FrameNo; 322 IMG_UINT32 ui32FrameNo;
323 IMG_UINT32 ui32PID;
324 IMG_UINT32 ui32RTData;
326 IMG_UINT32 ui32Type; 325 IMG_UINT32 ui32Type;
327 IMG_UINT32 ui32Ordinal; 326 IMG_UINT32 ui32Ordinal;
328 IMG_UINT32 ui32Info; 327 IMG_UINT32 ui32Info;
329 IMG_UINT32 ui32TimeWraps; 328 IMG_UINT32 ui32TimeWraps;
330 IMG_UINT32 ui32Time; 329 IMG_UINT32 ui32Time;
331 IMG_UINT32 ui32Counters[SGX_FEATURE_MP_CORE_COUNT][PVRSRV_SGX_HWPERF_NUM_COUNTERS]; 330
331 IMG_UINT32 ui32Counters[SGX_FEATURE_MP_CORE_COUNT_3D][PVRSRV_SGX_HWPERF_NUM_COUNTERS];
332 IMG_UINT32 ui32MiscCounters[SGX_FEATURE_MP_CORE_COUNT_3D][PVRSRV_SGX_HWPERF_NUM_MISC_COUNTERS];
332} SGXMKIF_HWPERF_CB_ENTRY; 333} SGXMKIF_HWPERF_CB_ENTRY;
333 334
334typedef struct _SGXMKIF_HWPERF_CB_ 335typedef struct _SGXMKIF_HWPERF_CB_
diff --git a/drivers/gpu/pvr/sgx_options.h b/drivers/gpu/pvr/sgx_options.h
index 6f918947d8d..e81f3bf1d25 100644
--- a/drivers/gpu/pvr/sgx_options.h
+++ b/drivers/gpu/pvr/sgx_options.h
@@ -26,79 +26,84 @@
26 26
27#if defined(DEBUG) || defined (INTERNAL_TEST) 27#if defined(DEBUG) || defined (INTERNAL_TEST)
28#define DEBUG_SET_OFFSET OPTIONS_BIT0 28#define DEBUG_SET_OFFSET OPTIONS_BIT0
29#define OPTIONS_BIT0 0x1 29#define OPTIONS_BIT0 0x1U
30#else 30#else
31#define OPTIONS_BIT0 0x0 31#define OPTIONS_BIT0 0x0
32#endif 32#endif
33 33
34#if defined(PDUMP) || defined (INTERNAL_TEST) 34#if defined(PDUMP) || defined (INTERNAL_TEST)
35#define PDUMP_SET_OFFSET OPTIONS_BIT1 35#define PDUMP_SET_OFFSET OPTIONS_BIT1
36#define OPTIONS_BIT1 (0x1 << 1) 36#define OPTIONS_BIT1 (0x1U << 1)
37#else 37#else
38#define OPTIONS_BIT1 0x0 38#define OPTIONS_BIT1 0x0
39#endif 39#endif
40 40
41#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG) || defined (INTERNAL_TEST) 41#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG) || defined (INTERNAL_TEST)
42#define PVRSRV_USSE_EDM_STATUS_DEBUG_SET_OFFSET OPTIONS_BIT2 42#define PVRSRV_USSE_EDM_STATUS_DEBUG_SET_OFFSET OPTIONS_BIT2
43#define OPTIONS_BIT2 (0x1 << 2) 43#define OPTIONS_BIT2 (0x1U << 2)
44#else 44#else
45#define OPTIONS_BIT2 0x0 45#define OPTIONS_BIT2 0x0
46#endif 46#endif
47 47
48#if defined(SUPPORT_HW_RECOVERY) || defined (INTERNAL_TEST) 48#if defined(SUPPORT_HW_RECOVERY) || defined (INTERNAL_TEST)
49#define SUPPORT_HW_RECOVERY_SET_OFFSET OPTIONS_BIT3 49#define SUPPORT_HW_RECOVERY_SET_OFFSET OPTIONS_BIT3
50#define OPTIONS_BIT3 (0x1 << 3) 50#define OPTIONS_BIT3 (0x1U << 3)
51#else 51#else
52#define OPTIONS_BIT3 0x0 52#define OPTIONS_BIT3 0x0
53#endif 53#endif
54 54
55 55
56 56
57#if defined (SUPPORT_SID_INTERFACE)
58#define PVR_SECURE_HANDLES_SET_OFFSET OPTIONS_BIT4
59#define OPTIONS_BIT4 (0x1U << 4)
60#else
57#if defined(PVR_SECURE_HANDLES) || defined (INTERNAL_TEST) 61#if defined(PVR_SECURE_HANDLES) || defined (INTERNAL_TEST)
58#define PVR_SECURE_HANDLES_SET_OFFSET OPTIONS_BIT4 62#define PVR_SECURE_HANDLES_SET_OFFSET OPTIONS_BIT4
59#define OPTIONS_BIT4 (0x1 << 4) 63#define OPTIONS_BIT4 (0x1U << 4)
60#else 64#else
61#define OPTIONS_BIT4 0x0 65#define OPTIONS_BIT4 0x0
62#endif 66#endif
67#endif
63 68
64#if defined(SGX_BYPASS_SYSTEM_CACHE) || defined (INTERNAL_TEST) 69#if defined(SGX_BYPASS_SYSTEM_CACHE) || defined (INTERNAL_TEST)
65#define SGX_BYPASS_SYSTEM_CACHE_SET_OFFSET OPTIONS_BIT5 70#define SGX_BYPASS_SYSTEM_CACHE_SET_OFFSET OPTIONS_BIT5
66#define OPTIONS_BIT5 (0x1 << 5) 71#define OPTIONS_BIT5 (0x1U << 5)
67#else 72#else
68#define OPTIONS_BIT5 0x0 73#define OPTIONS_BIT5 0x0
69#endif 74#endif
70 75
71#if defined(SGX_DMS_AGE_ENABLE) || defined (INTERNAL_TEST) 76#if defined(SGX_DMS_AGE_ENABLE) || defined (INTERNAL_TEST)
72#define SGX_DMS_AGE_ENABLE_SET_OFFSET OPTIONS_BIT6 77#define SGX_DMS_AGE_ENABLE_SET_OFFSET OPTIONS_BIT6
73#define OPTIONS_BIT6 (0x1 << 6) 78#define OPTIONS_BIT6 (0x1U << 6)
74#else 79#else
75#define OPTIONS_BIT6 0x0 80#define OPTIONS_BIT6 0x0
76#endif 81#endif
77 82
78#if defined(SGX_FAST_DPM_INIT) || defined (INTERNAL_TEST) 83#if defined(SGX_FAST_DPM_INIT) || defined (INTERNAL_TEST)
79#define SGX_FAST_DPM_INIT_SET_OFFSET OPTIONS_BIT8 84#define SGX_FAST_DPM_INIT_SET_OFFSET OPTIONS_BIT8
80#define OPTIONS_BIT8 (0x1 << 8) 85#define OPTIONS_BIT8 (0x1U << 8)
81#else 86#else
82#define OPTIONS_BIT8 0x0 87#define OPTIONS_BIT8 0x0
83#endif 88#endif
84 89
85#if defined(SGX_FEATURE_WRITEBACK_DCU) || defined (INTERNAL_TEST) 90#if defined(SGX_FEATURE_WRITEBACK_DCU) || defined (INTERNAL_TEST)
86#define SGX_FEATURE_DCU_SET_OFFSET OPTIONS_BIT9 91#define SGX_FEATURE_DCU_SET_OFFSET OPTIONS_BIT9
87#define OPTIONS_BIT9 (0x1 << 9) 92#define OPTIONS_BIT9 (0x1U << 9)
88#else 93#else
89#define OPTIONS_BIT9 0x0 94#define OPTIONS_BIT9 0x0
90#endif 95#endif
91 96
92#if defined(SGX_FEATURE_MP) || defined (INTERNAL_TEST) 97#if defined(SGX_FEATURE_MP) || defined (INTERNAL_TEST)
93#define SGX_FEATURE_MP_SET_OFFSET OPTIONS_BIT10 98#define SGX_FEATURE_MP_SET_OFFSET OPTIONS_BIT10
94#define OPTIONS_BIT10 (0x1 << 10) 99#define OPTIONS_BIT10 (0x1U << 10)
95#else 100#else
96#define OPTIONS_BIT10 0x0 101#define OPTIONS_BIT10 0x0
97#endif 102#endif
98 103
99#if defined(SGX_FEATURE_MULTITHREADED_UKERNEL) || defined (INTERNAL_TEST) 104#if defined(SGX_FEATURE_MULTITHREADED_UKERNEL) || defined (INTERNAL_TEST)
100#define SGX_FEATURE_MULTITHREADED_UKERNEL_SET_OFFSET OPTIONS_BIT11 105#define SGX_FEATURE_MULTITHREADED_UKERNEL_SET_OFFSET OPTIONS_BIT11
101#define OPTIONS_BIT11 (0x1 << 11) 106#define OPTIONS_BIT11 (0x1U << 11)
102#else 107#else
103#define OPTIONS_BIT11 0x0 108#define OPTIONS_BIT11 0x0
104#endif 109#endif
@@ -107,7 +112,7 @@
107 112
108#if defined(SGX_FEATURE_OVERLAPPED_SPM) || defined (INTERNAL_TEST) 113#if defined(SGX_FEATURE_OVERLAPPED_SPM) || defined (INTERNAL_TEST)
109#define SGX_FEATURE_OVERLAPPED_SPM_SET_OFFSET OPTIONS_BIT12 114#define SGX_FEATURE_OVERLAPPED_SPM_SET_OFFSET OPTIONS_BIT12
110#define OPTIONS_BIT12 (0x1 << 12) 115#define OPTIONS_BIT12 (0x1U << 12)
111#else 116#else
112#define OPTIONS_BIT12 0x0 117#define OPTIONS_BIT12 0x0
113#endif 118#endif
@@ -115,14 +120,14 @@
115 120
116#if defined(SGX_FEATURE_SYSTEM_CACHE) || defined (INTERNAL_TEST) 121#if defined(SGX_FEATURE_SYSTEM_CACHE) || defined (INTERNAL_TEST)
117#define SGX_FEATURE_SYSTEM_CACHE_SET_OFFSET OPTIONS_BIT13 122#define SGX_FEATURE_SYSTEM_CACHE_SET_OFFSET OPTIONS_BIT13
118#define OPTIONS_BIT13 (0x1 << 13) 123#define OPTIONS_BIT13 (0x1U << 13)
119#else 124#else
120#define OPTIONS_BIT13 0x0 125#define OPTIONS_BIT13 0x0
121#endif 126#endif
122 127
123#if defined(SGX_SUPPORT_HWPROFILING) || defined (INTERNAL_TEST) 128#if defined(SGX_SUPPORT_HWPROFILING) || defined (INTERNAL_TEST)
124#define SGX_SUPPORT_HWPROFILING_SET_OFFSET OPTIONS_BIT14 129#define SGX_SUPPORT_HWPROFILING_SET_OFFSET OPTIONS_BIT14
125#define OPTIONS_BIT14 (0x1 << 14) 130#define OPTIONS_BIT14 (0x1U << 14)
126#else 131#else
127#define OPTIONS_BIT14 0x0 132#define OPTIONS_BIT14 0x0
128#endif 133#endif
@@ -131,28 +136,28 @@
131 136
132#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT) || defined (INTERNAL_TEST) 137#if defined(SUPPORT_ACTIVE_POWER_MANAGEMENT) || defined (INTERNAL_TEST)
133#define SUPPORT_ACTIVE_POWER_MANAGEMENT_SET_OFFSET OPTIONS_BIT15 138#define SUPPORT_ACTIVE_POWER_MANAGEMENT_SET_OFFSET OPTIONS_BIT15
134#define OPTIONS_BIT15 (0x1 << 15) 139#define OPTIONS_BIT15 (0x1U << 15)
135#else 140#else
136#define OPTIONS_BIT15 0x0 141#define OPTIONS_BIT15 0x0
137#endif 142#endif
138 143
139#if defined(SUPPORT_DISPLAYCONTROLLER_TILING) || defined (INTERNAL_TEST) 144#if defined(SUPPORT_DISPLAYCONTROLLER_TILING) || defined (INTERNAL_TEST)
140#define SUPPORT_DISPLAYCONTROLLER_TILING_SET_OFFSET OPTIONS_BIT16 145#define SUPPORT_DISPLAYCONTROLLER_TILING_SET_OFFSET OPTIONS_BIT16
141#define OPTIONS_BIT16 (0x1 << 16) 146#define OPTIONS_BIT16 (0x1U << 16)
142#else 147#else
143#define OPTIONS_BIT16 0x0 148#define OPTIONS_BIT16 0x0
144#endif 149#endif
145 150
146#if defined(SUPPORT_PERCONTEXT_PB) || defined (INTERNAL_TEST) 151#if defined(SUPPORT_PERCONTEXT_PB) || defined (INTERNAL_TEST)
147#define SUPPORT_PERCONTEXT_PB_SET_OFFSET OPTIONS_BIT17 152#define SUPPORT_PERCONTEXT_PB_SET_OFFSET OPTIONS_BIT17
148#define OPTIONS_BIT17 (0x1 << 17) 153#define OPTIONS_BIT17 (0x1U << 17)
149#else 154#else
150#define OPTIONS_BIT17 0x0 155#define OPTIONS_BIT17 0x0
151#endif 156#endif
152 157
153#if defined(SUPPORT_SGX_HWPERF) || defined (INTERNAL_TEST) 158#if defined(SUPPORT_SGX_HWPERF) || defined (INTERNAL_TEST)
154#define SUPPORT_SGX_HWPERF_SET_OFFSET OPTIONS_BIT18 159#define SUPPORT_SGX_HWPERF_SET_OFFSET OPTIONS_BIT18
155#define OPTIONS_BIT18 (0x1 << 18) 160#define OPTIONS_BIT18 (0x1U << 18)
156#else 161#else
157#define OPTIONS_BIT18 0x0 162#define OPTIONS_BIT18 0x0
158#endif 163#endif
@@ -161,38 +166,45 @@
161 166
162#if defined(SUPPORT_SGX_MMU_DUMMY_PAGE) || defined (INTERNAL_TEST) 167#if defined(SUPPORT_SGX_MMU_DUMMY_PAGE) || defined (INTERNAL_TEST)
163#define SUPPORT_SGX_MMU_DUMMY_PAGE_SET_OFFSET OPTIONS_BIT19 168#define SUPPORT_SGX_MMU_DUMMY_PAGE_SET_OFFSET OPTIONS_BIT19
164#define OPTIONS_BIT19 (0x1 << 19) 169#define OPTIONS_BIT19 (0x1U << 19)
165#else 170#else
166#define OPTIONS_BIT19 0x0 171#define OPTIONS_BIT19 0x0
167#endif 172#endif
168 173
169#if defined(SUPPORT_SGX_PRIORITY_SCHEDULING) || defined (INTERNAL_TEST) 174#if defined(SUPPORT_SGX_PRIORITY_SCHEDULING) || defined (INTERNAL_TEST)
170#define SUPPORT_SGX_PRIORITY_SCHEDULING_SET_OFFSET OPTIONS_BIT20 175#define SUPPORT_SGX_PRIORITY_SCHEDULING_SET_OFFSET OPTIONS_BIT20
171#define OPTIONS_BIT20 (0x1 << 20) 176#define OPTIONS_BIT20 (0x1U << 20)
172#else 177#else
173#define OPTIONS_BIT20 0x0 178#define OPTIONS_BIT20 0x0
174#endif 179#endif
175 180
176#if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) || defined (INTERNAL_TEST) 181#if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) || defined (INTERNAL_TEST)
177#define SUPPORT_SGX_LOW_LATENCY_SCHEDULING_SET_OFFSET OPTIONS_BIT21 182#define SUPPORT_SGX_LOW_LATENCY_SCHEDULING_SET_OFFSET OPTIONS_BIT21
178#define OPTIONS_BIT21 (0x1 << 21) 183#define OPTIONS_BIT21 (0x1U << 21)
179#else 184#else
180#define OPTIONS_BIT21 0x0 185#define OPTIONS_BIT21 0x0
181#endif 186#endif
182 187
183#if defined(USE_SUPPORT_NO_TA3D_OVERLAP) || defined (INTERNAL_TEST) 188#if defined(USE_SUPPORT_NO_TA3D_OVERLAP) || defined (INTERNAL_TEST)
184#define USE_SUPPORT_NO_TA3D_OVERLAP_SET_OFFSET OPTIONS_BIT22 189#define USE_SUPPORT_NO_TA3D_OVERLAP_SET_OFFSET OPTIONS_BIT22
185#define OPTIONS_BIT22 (0x1 << 22) 190#define OPTIONS_BIT22 (0x1U << 22)
186#else 191#else
187#define OPTIONS_BIT22 0x0 192#define OPTIONS_BIT22 0x0
188#endif 193#endif
189 194
190
191#if defined(SGX_FEATURE_MP) || defined (INTERNAL_TEST) 195#if defined(SGX_FEATURE_MP) || defined (INTERNAL_TEST)
196#if defined(SGX_FEATURE_MP_CORE_COUNT)
192#define OPTIONS_HIGHBYTE ((SGX_FEATURE_MP_CORE_COUNT-1) << SGX_FEATURE_MP_CORE_COUNT_SET_OFFSET) 197#define OPTIONS_HIGHBYTE ((SGX_FEATURE_MP_CORE_COUNT-1) << SGX_FEATURE_MP_CORE_COUNT_SET_OFFSET)
193#define SGX_FEATURE_MP_CORE_COUNT_SET_OFFSET 28UL 198#define SGX_FEATURE_MP_CORE_COUNT_SET_OFFSET 28UL
194#define SGX_FEATURE_MP_CORE_COUNT_SET_MASK 0xFF 199#define SGX_FEATURE_MP_CORE_COUNT_SET_MASK 0xFF
195#else 200#else
201#define OPTIONS_HIGHBYTE (((SGX_FEATURE_MP_CORE_COUNT_TA-1) << SGX_FEATURE_MP_CORE_COUNT_SET_OFFSET) |\
202 ((SGX_FEATURE_MP_CORE_COUNT_3D-1) << SGX_FEATURE_MP_CORE_COUNT_SET_OFFSET_3D))
203#define SGX_FEATURE_MP_CORE_COUNT_SET_OFFSET 24UL
204#define SGX_FEATURE_MP_CORE_COUNT_SET_OFFSET_3D 28UL
205#define SGX_FEATURE_MP_CORE_COUNT_SET_MASK 0xFF
206#endif
207#else
196#define OPTIONS_HIGHBYTE 0x0 208#define OPTIONS_HIGHBYTE 0x0
197#endif 209#endif
198 210
diff --git a/drivers/gpu/pvr/sgxapi_km.h b/drivers/gpu/pvr/sgxapi_km.h
index f38a85c0dcd..3e4b281b3f9 100644
--- a/drivers/gpu/pvr/sgxapi_km.h
+++ b/drivers/gpu/pvr/sgxapi_km.h
@@ -51,19 +51,25 @@ extern "C" {
51#define SGX_PDSPIXEL_CODEDATA_HEAP_ID 6 51#define SGX_PDSPIXEL_CODEDATA_HEAP_ID 6
52#define SGX_PDSVERTEX_CODEDATA_HEAP_ID 7 52#define SGX_PDSVERTEX_CODEDATA_HEAP_ID 7
53#define SGX_SYNCINFO_HEAP_ID 8 53#define SGX_SYNCINFO_HEAP_ID 8
54#define SGX_3DPARAMETERS_HEAP_ID 9 54#define SGX_SHARED_3DPARAMETERS_HEAP_ID 9
55#define SGX_PERCONTEXT_3DPARAMETERS_HEAP_ID 10
55#if defined(SUPPORT_SGX_GENERAL_MAPPING_HEAP) 56#if defined(SUPPORT_SGX_GENERAL_MAPPING_HEAP)
56#define SGX_GENERAL_MAPPING_HEAP_ID 10 57#define SGX_GENERAL_MAPPING_HEAP_ID 11
57#endif 58#endif
58#if defined(SGX_FEATURE_2D_HARDWARE) 59#if defined(SGX_FEATURE_2D_HARDWARE)
59#define SGX_2D_HEAP_ID 11 60#define SGX_2D_HEAP_ID 12
60#else 61#else
61#if defined(FIX_HW_BRN_26915) 62#if defined(FIX_HW_BRN_26915)
62#define SGX_CGBUFFER_HEAP_ID 12 63#define SGX_CGBUFFER_HEAP_ID 13
63#endif 64#endif
64#endif 65#endif
65#define SGX_MAX_HEAP_ID 13 66#define SGX_MAX_HEAP_ID 14
66 67
68#if (defined(SUPPORT_PERCONTEXT_PB) || defined(SUPPORT_HYBRID_PB))
69#define SGX_3DPARAMETERS_HEAP_ID SGX_PERCONTEXT_3DPARAMETERS_HEAP_ID
70#else
71#define SGX_3DPARAMETERS_HEAP_ID SGX_SHARED_3DPARAMETERS_HEAP_ID
72#endif
67#if defined(SGX543) || defined(SGX544) || defined(SGX554) 73#if defined(SGX543) || defined(SGX544) || defined(SGX554)
68#define SGX_USE_CODE_SEGMENT_RANGE_BITS 23 74#define SGX_USE_CODE_SEGMENT_RANGE_BITS 23
69#else 75#else
@@ -78,20 +84,17 @@ extern "C" {
78#define SGX_MAX_TA_SRC_SYNCS 1 84#define SGX_MAX_TA_SRC_SYNCS 1
79#define SGX_MAX_3D_SRC_SYNCS 4 85#define SGX_MAX_3D_SRC_SYNCS 4
80#else 86#else
81#if defined(ANDROID)
82#define SGX_MAX_SRC_SYNCS 8 87#define SGX_MAX_SRC_SYNCS 8
83#define SGX_MAX_DST_SYNCS 1 88#define SGX_MAX_DST_SYNCS 1
84#else
85#define SGX_MAX_SRC_SYNCS 4
86#define SGX_MAX_DST_SYNCS 1
87#endif
88#endif 89#endif
89 90
90 91
91#if defined(SGX_FEATURE_EXTENDED_PERF_COUNTERS) 92#if defined(SGX_FEATURE_EXTENDED_PERF_COUNTERS)
92#define PVRSRV_SGX_HWPERF_NUM_COUNTERS 8 93#define PVRSRV_SGX_HWPERF_NUM_COUNTERS 8
94#define PVRSRV_SGX_HWPERF_NUM_MISC_COUNTERS 11
93#else 95#else
94#define PVRSRV_SGX_HWPERF_NUM_COUNTERS 9 96#define PVRSRV_SGX_HWPERF_NUM_COUNTERS 9
97#define PVRSRV_SGX_HWPERF_NUM_MISC_COUNTERS 8
95#endif 98#endif
96 99
97#define PVRSRV_SGX_HWPERF_INVALID 0x1 100#define PVRSRV_SGX_HWPERF_INVALID 0x1
@@ -102,11 +105,19 @@ extern "C" {
102#define PVRSRV_SGX_HWPERF_2D 0x5 105#define PVRSRV_SGX_HWPERF_2D 0x5
103#define PVRSRV_SGX_HWPERF_POWER 0x6 106#define PVRSRV_SGX_HWPERF_POWER 0x6
104#define PVRSRV_SGX_HWPERF_PERIODIC 0x7 107#define PVRSRV_SGX_HWPERF_PERIODIC 0x7
108#define PVRSRV_SGX_HWPERF_3DSPM 0x8
105 109
106#define PVRSRV_SGX_HWPERF_MK_EVENT 0x101 110#define PVRSRV_SGX_HWPERF_MK_EVENT 0x101
107#define PVRSRV_SGX_HWPERF_MK_TA 0x102 111#define PVRSRV_SGX_HWPERF_MK_TA 0x102
108#define PVRSRV_SGX_HWPERF_MK_3D 0x103 112#define PVRSRV_SGX_HWPERF_MK_3D 0x103
109#define PVRSRV_SGX_HWPERF_MK_2D 0x104 113#define PVRSRV_SGX_HWPERF_MK_2D 0x104
114#define PVRSRV_SGX_HWPERF_MK_TRANSFER_DUMMY 0x105
115#define PVRSRV_SGX_HWPERF_MK_TA_DUMMY 0x106
116#define PVRSRV_SGX_HWPERF_MK_3D_DUMMY 0x107
117#define PVRSRV_SGX_HWPERF_MK_2D_DUMMY 0x108
118#define PVRSRV_SGX_HWPERF_MK_TA_LOCKUP 0x109
119#define PVRSRV_SGX_HWPERF_MK_3D_LOCKUP 0x10A
120#define PVRSRV_SGX_HWPERF_MK_2D_LOCKUP 0x10B
110 121
111#define PVRSRV_SGX_HWPERF_TYPE_STARTEND_BIT 28 122#define PVRSRV_SGX_HWPERF_TYPE_STARTEND_BIT 28
112#define PVRSRV_SGX_HWPERF_TYPE_OP_MASK ((1UL << PVRSRV_SGX_HWPERF_TYPE_STARTEND_BIT) - 1) 123#define PVRSRV_SGX_HWPERF_TYPE_OP_MASK ((1UL << PVRSRV_SGX_HWPERF_TYPE_STARTEND_BIT) - 1)
@@ -124,6 +135,19 @@ extern "C" {
124#define PVRSRV_SGX_HWPERF_TYPE_POWER_START (PVRSRV_SGX_HWPERF_POWER | PVRSRV_SGX_HWPERF_TYPE_OP_START) 135#define PVRSRV_SGX_HWPERF_TYPE_POWER_START (PVRSRV_SGX_HWPERF_POWER | PVRSRV_SGX_HWPERF_TYPE_OP_START)
125#define PVRSRV_SGX_HWPERF_TYPE_POWER_END (PVRSRV_SGX_HWPERF_POWER | PVRSRV_SGX_HWPERF_TYPE_OP_END) 136#define PVRSRV_SGX_HWPERF_TYPE_POWER_END (PVRSRV_SGX_HWPERF_POWER | PVRSRV_SGX_HWPERF_TYPE_OP_END)
126#define PVRSRV_SGX_HWPERF_TYPE_PERIODIC (PVRSRV_SGX_HWPERF_PERIODIC) 137#define PVRSRV_SGX_HWPERF_TYPE_PERIODIC (PVRSRV_SGX_HWPERF_PERIODIC)
138#define PVRSRV_SGX_HWPERF_TYPE_3DSPM_START (PVRSRV_SGX_HWPERF_3DSPM | PVRSRV_SGX_HWPERF_TYPE_OP_START)
139#define PVRSRV_SGX_HWPERF_TYPE_3DSPM_END (PVRSRV_SGX_HWPERF_3DSPM | PVRSRV_SGX_HWPERF_TYPE_OP_END)
140#define PVRSRV_SGX_HWPERF_TYPE_MK_TRANSFER_DUMMY_START (PVRSRV_SGX_HWPERF_MK_TRANSFER_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_START)
141#define PVRSRV_SGX_HWPERF_TYPE_MK_TRANSFER_DUMMY_END (PVRSRV_SGX_HWPERF_MK_TRANSFER_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_END)
142#define PVRSRV_SGX_HWPERF_TYPE_MK_TA_DUMMY_START (PVRSRV_SGX_HWPERF_MK_TA_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_START)
143#define PVRSRV_SGX_HWPERF_TYPE_MK_TA_DUMMY_END (PVRSRV_SGX_HWPERF_MK_TA_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_END)
144#define PVRSRV_SGX_HWPERF_TYPE_MK_3D_DUMMY_START (PVRSRV_SGX_HWPERF_MK_3D_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_START)
145#define PVRSRV_SGX_HWPERF_TYPE_MK_3D_DUMMY_END (PVRSRV_SGX_HWPERF_MK_3D_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_END)
146#define PVRSRV_SGX_HWPERF_TYPE_MK_2D_DUMMY_START (PVRSRV_SGX_HWPERF_MK_2D_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_START)
147#define PVRSRV_SGX_HWPERF_TYPE_MK_2D_DUMMY_END (PVRSRV_SGX_HWPERF_MK_2D_DUMMY | PVRSRV_SGX_HWPERF_TYPE_OP_END)
148#define PVRSRV_SGX_HWPERF_TYPE_MK_TA_LOCKUP (PVRSRV_SGX_HWPERF_MK_TA_LOCKUP)
149#define PVRSRV_SGX_HWPERF_TYPE_MK_3D_LOCKUP (PVRSRV_SGX_HWPERF_MK_3D_LOCKUP)
150#define PVRSRV_SGX_HWPERF_TYPE_MK_2D_LOCKUP (PVRSRV_SGX_HWPERF_MK_2D_LOCKUP)
127 151
128#define PVRSRV_SGX_HWPERF_TYPE_MK_EVENT_START (PVRSRV_SGX_HWPERF_MK_EVENT | PVRSRV_SGX_HWPERF_TYPE_OP_START) 152#define PVRSRV_SGX_HWPERF_TYPE_MK_EVENT_START (PVRSRV_SGX_HWPERF_MK_EVENT | PVRSRV_SGX_HWPERF_TYPE_OP_START)
129#define PVRSRV_SGX_HWPERF_TYPE_MK_EVENT_END (PVRSRV_SGX_HWPERF_MK_EVENT | PVRSRV_SGX_HWPERF_TYPE_OP_END) 153#define PVRSRV_SGX_HWPERF_TYPE_MK_EVENT_END (PVRSRV_SGX_HWPERF_MK_EVENT | PVRSRV_SGX_HWPERF_TYPE_OP_END)
@@ -144,11 +168,15 @@ extern "C" {
144typedef struct _PVRSRV_SGX_HWPERF_CB_ENTRY_ 168typedef struct _PVRSRV_SGX_HWPERF_CB_ENTRY_
145{ 169{
146 IMG_UINT32 ui32FrameNo; 170 IMG_UINT32 ui32FrameNo;
171 IMG_UINT32 ui32PID;
172 IMG_UINT32 ui32RTData;
147 IMG_UINT32 ui32Type; 173 IMG_UINT32 ui32Type;
148 IMG_UINT32 ui32Ordinal; 174 IMG_UINT32 ui32Ordinal;
149 IMG_UINT32 ui32Info; 175 IMG_UINT32 ui32Info;
150 IMG_UINT32 ui32Clocksx16; 176 IMG_UINT32 ui32Clocksx16;
151 IMG_UINT32 ui32Counters[SGX_FEATURE_MP_CORE_COUNT][PVRSRV_SGX_HWPERF_NUM_COUNTERS]; 177
178 IMG_UINT32 ui32Counters[SGX_FEATURE_MP_CORE_COUNT_3D][PVRSRV_SGX_HWPERF_NUM_COUNTERS];
179 IMG_UINT32 ui32MiscCounters[SGX_FEATURE_MP_CORE_COUNT_3D][PVRSRV_SGX_HWPERF_NUM_MISC_COUNTERS];
152} PVRSRV_SGX_HWPERF_CB_ENTRY; 180} PVRSRV_SGX_HWPERF_CB_ENTRY;
153 181
154 182
@@ -171,7 +199,6 @@ typedef enum _SGX_MISC_INFO_REQUEST_
171 SGX_MISC_INFO_REQUEST_SET_HWPERF_STATUS, 199 SGX_MISC_INFO_REQUEST_SET_HWPERF_STATUS,
172#if defined(SGX_FEATURE_DATA_BREAKPOINTS) 200#if defined(SGX_FEATURE_DATA_BREAKPOINTS)
173 SGX_MISC_INFO_REQUEST_SET_BREAKPOINT, 201 SGX_MISC_INFO_REQUEST_SET_BREAKPOINT,
174 SGX_MISC_INFO_REQUEST_WAIT_FOR_BREAKPOINT,
175 SGX_MISC_INFO_REQUEST_POLL_BREAKPOINT, 202 SGX_MISC_INFO_REQUEST_POLL_BREAKPOINT,
176 SGX_MISC_INFO_REQUEST_RESUME_BREAKPOINT, 203 SGX_MISC_INFO_REQUEST_RESUME_BREAKPOINT,
177#endif 204#endif
@@ -274,6 +301,7 @@ typedef struct _PVRSRV_SGX_MISCINFO_SET_HWPERF_STATUS
274typedef struct _SGX_MISC_INFO_ 301typedef struct _SGX_MISC_INFO_
275{ 302{
276 SGX_MISC_INFO_REQUEST eRequest; 303 SGX_MISC_INFO_REQUEST eRequest;
304 IMG_UINT32 ui32Padding;
277#if defined(SUPPORT_SGX_EDM_MEMORY_DEBUG) 305#if defined(SUPPORT_SGX_EDM_MEMORY_DEBUG)
278 IMG_DEV_VIRTADDR sDevVAddrSrc; 306 IMG_DEV_VIRTADDR sDevVAddrSrc;
279 IMG_DEV_VIRTADDR sDevVAddrDest; 307 IMG_DEV_VIRTADDR sDevVAddrDest;
@@ -323,6 +351,7 @@ typedef struct _PVRSRV_SGX_PDUMP_CONTEXT_
323} PVRSRV_SGX_PDUMP_CONTEXT; 351} PVRSRV_SGX_PDUMP_CONTEXT;
324 352
325 353
354#if !defined (SUPPORT_SID_INTERFACE)
326typedef struct _SGX_KICKTA_DUMP_ROFF_ 355typedef struct _SGX_KICKTA_DUMP_ROFF_
327{ 356{
328 IMG_HANDLE hKernelMemInfo; 357 IMG_HANDLE hKernelMemInfo;
@@ -331,8 +360,13 @@ typedef struct _SGX_KICKTA_DUMP_ROFF_
331 IMG_UINT32 ui32Value; 360 IMG_UINT32 ui32Value;
332 IMG_PCHAR pszName; 361 IMG_PCHAR pszName;
333} SGX_KICKTA_DUMP_ROFF, *PSGX_KICKTA_DUMP_ROFF; 362} SGX_KICKTA_DUMP_ROFF, *PSGX_KICKTA_DUMP_ROFF;
363#endif
334 364
365#if defined (SUPPORT_SID_INTERFACE)
366typedef struct _SGX_KICKTA_DUMP_BUFFER_KM_
367#else
335typedef struct _SGX_KICKTA_DUMP_BUFFER_ 368typedef struct _SGX_KICKTA_DUMP_BUFFER_
369#endif
336{ 370{
337 IMG_UINT32 ui32SpaceUsed; 371 IMG_UINT32 ui32SpaceUsed;
338 IMG_UINT32 ui32Start; 372 IMG_UINT32 ui32Start;
@@ -347,8 +381,13 @@ typedef struct _SGX_KICKTA_DUMP_BUFFER_
347 IMG_DEV_VIRTADDR sCtrlDevVAddr; 381 IMG_DEV_VIRTADDR sCtrlDevVAddr;
348#endif 382#endif
349 IMG_PCHAR pszName; 383 IMG_PCHAR pszName;
384#if defined (SUPPORT_SID_INTERFACE)
385} SGX_KICKTA_DUMP_BUFFER_KM, *PSGX_KICKTA_DUMP_BUFFER_KM;
386#else
350} SGX_KICKTA_DUMP_BUFFER, *PSGX_KICKTA_DUMP_BUFFER; 387} SGX_KICKTA_DUMP_BUFFER, *PSGX_KICKTA_DUMP_BUFFER;
388#endif
351 389
390#if !defined (SUPPORT_SID_INTERFACE)
352#ifdef PDUMP 391#ifdef PDUMP
353typedef struct _SGX_KICKTA_PDUMP_ 392typedef struct _SGX_KICKTA_PDUMP_
354{ 393{
@@ -365,6 +404,7 @@ typedef struct _SGX_KICKTA_PDUMP_
365 IMG_UINT32 ui32ROffArraySize; 404 IMG_UINT32 ui32ROffArraySize;
366} SGX_KICKTA_PDUMP, *PSGX_KICKTA_PDUMP; 405} SGX_KICKTA_PDUMP, *PSGX_KICKTA_PDUMP;
367#endif 406#endif
407#endif
368 408
369#if defined(TRANSFER_QUEUE) 409#if defined(TRANSFER_QUEUE)
370#if defined(SGX_FEATURE_2D_HARDWARE) 410#if defined(SGX_FEATURE_2D_HARDWARE)
diff --git a/drivers/gpu/pvr/sgxdefs.h b/drivers/gpu/pvr/sgxdefs.h
index 9e5effbc853..3b870596fb5 100644
--- a/drivers/gpu/pvr/sgxdefs.h
+++ b/drivers/gpu/pvr/sgxdefs.h
@@ -45,11 +45,12 @@
45#if defined(SGX540) 45#if defined(SGX540)
46#include "sgx540defs.h" 46#include "sgx540defs.h"
47#else 47#else
48#if defined(SGX541)
49#include "sgx541defs.h"
50#else
51#if defined(SGX543) 48#if defined(SGX543)
49#if SGX_CORE_REV == 113 || SGX_CORE_REV == 122 || SGX_CORE_REV == 1221 || SGX_CORE_REV == 140
50#include "sgx543_v1.164defs.h"
51#else
52#include "sgx543defs.h" 52#include "sgx543defs.h"
53#endif
53#else 54#else
54#if defined(SGX544) 55#if defined(SGX544)
55#include "sgx544defs.h" 56#include "sgx544defs.h"
@@ -72,15 +73,10 @@
72#endif 73#endif
73#endif 74#endif
74#endif 75#endif
75#endif
76 76
77#if defined(SGX_FEATURE_MP) 77#if defined(SGX_FEATURE_MP)
78#if defined(SGX541) 78#if defined(SGX554)
79#if SGX_CORE_REV == 100 79#include "sgxmpplusdefs.h"
80#include "sgx541_100mpdefs.h"
81#else
82#include "sgx541mpdefs.h"
83#endif
84#else 80#else
85#include "sgxmpdefs.h" 81#include "sgxmpdefs.h"
86#endif 82#endif
diff --git a/drivers/gpu/pvr/sgxerrata.h b/drivers/gpu/pvr/sgxerrata.h
index ded7a524283..8d76618accb 100644
--- a/drivers/gpu/pvr/sgxerrata.h
+++ b/drivers/gpu/pvr/sgxerrata.h
@@ -68,6 +68,10 @@
68 #define FIX_HW_BRN_22934 68 #define FIX_HW_BRN_22934
69 #define FIX_HW_BRN_28889 69 #define FIX_HW_BRN_28889
70 #else 70 #else
71 #if SGX_CORE_REV == 1111
72 #define FIX_HW_BRN_22934
73 #define FIX_HW_BRN_28889
74 #else
71 #if SGX_CORE_REV == 120 75 #if SGX_CORE_REV == 120
72 #define FIX_HW_BRN_22934 76 #define FIX_HW_BRN_22934
73 #define FIX_HW_BRN_28889 77 #define FIX_HW_BRN_28889
@@ -88,6 +92,7 @@
88 #endif 92 #endif
89 #endif 93 #endif
90 #endif 94 #endif
95 #endif
91#endif 96#endif
92 #endif 97 #endif
93 98
@@ -240,15 +245,113 @@
240 #endif 245 #endif
241 246
242 #if SGX_CORE_REV == 113 247 #if SGX_CORE_REV == 113
248 #define FIX_HW_BRN_29954
249 #define FIX_HW_BRN_29997
243 #define FIX_HW_BRN_30954 250 #define FIX_HW_BRN_30954
251 #define FIX_HW_BRN_31093
252 #define FIX_HW_BRN_31195
253 #define FIX_HW_BRN_31278
254 #if defined(SGX_FEATURE_MP)
255 #define FIX_HW_BRN_31425
256 #endif
257 #define FIX_HW_BRN_31620
258 #define FIX_HW_BRN_31542
259 #define FIX_HW_BRN_32044
244 260
245 #else 261 #else
246 #if SGX_CORE_REV == 122 262 #if SGX_CORE_REV == 122
247 #define FIX_HW_BRN_30954 263 #define FIX_HW_BRN_29954
248 264 #define FIX_HW_BRN_29997
265 #define FIX_HW_BRN_30954
266 #define FIX_HW_BRN_31093
267 #define FIX_HW_BRN_31195
268 #define FIX_HW_BRN_31278
269 #if defined(SGX_FEATURE_MP)
270 #define FIX_HW_BRN_31425
271 #endif
272 #define FIX_HW_BRN_31620
273 #define FIX_HW_BRN_31542
274 #define FIX_HW_BRN_32044
275
276 #else
277 #if SGX_CORE_REV == 1221
278 #define FIX_HW_BRN_29954
279 #define FIX_HW_BRN_31195
280 #define FIX_HW_BRN_31278
281 #if defined(SGX_FEATURE_MP)
282 #define FIX_HW_BRN_31425
283 #endif
284 #define FIX_HW_BRN_31620
285 #define FIX_HW_BRN_31542
286 #define FIX_HW_BRN_32044
287
249 #else 288 #else
250 #if SGX_CORE_REV == 140 289 #if SGX_CORE_REV == 140
251 #define FIX_HW_BRN_30954 290 #define FIX_HW_BRN_29954
291 #define FIX_HW_BRN_30954
292 #define FIX_HW_BRN_31093
293 #define FIX_HW_BRN_31195
294 #define FIX_HW_BRN_31278
295 #if defined(SGX_FEATURE_MP)
296 #define FIX_HW_BRN_31425
297 #endif
298 #define FIX_HW_BRN_31620
299 #define FIX_HW_BRN_31542
300 #define FIX_HW_BRN_32044
301
302 #else
303 #if SGX_CORE_REV == 1401
304 #define FIX_HW_BRN_29954
305 #define FIX_HW_BRN_30954
306 #define FIX_HW_BRN_31195
307 #define FIX_HW_BRN_31278
308 #if defined(SGX_FEATURE_MP)
309 #define FIX_HW_BRN_31425
310 #endif
311 #define FIX_HW_BRN_31620
312 #define FIX_HW_BRN_31542
313 #define FIX_HW_BRN_32044
314
315 #else
316 #if SGX_CORE_REV == 141
317 #if defined(SGX_FEATURE_MP)
318 #define FIX_HW_BRN_31425
319 #endif
320 #define FIX_HW_BRN_32044
321
322 #else
323 #if SGX_CORE_REV == 211
324 #define FIX_HW_BRN_31093
325 #define FIX_HW_BRN_31195
326 #define FIX_HW_BRN_31278
327 #if defined(SGX_FEATURE_MP)
328 #define FIX_HW_BRN_31425
329 #endif
330 #define FIX_HW_BRN_31620
331 #define FIX_HW_BRN_31542
332 #define FIX_HW_BRN_32044
333
334 #else
335 #if SGX_CORE_REV == 2111
336 #define FIX_HW_BRN_31093
337 #define FIX_HW_BRN_31195
338 #define FIX_HW_BRN_31278
339 #if defined(SGX_FEATURE_MP)
340 #define FIX_HW_BRN_31425
341 #endif
342 #define FIX_HW_BRN_31620
343 #define FIX_HW_BRN_31542
344 #define FIX_HW_BRN_30970
345 #define FIX_HW_BRN_32044
346 #define FIX_HW_BRN_30982
347
348 #else
349 #if SGX_CORE_REV == 213
350 #if defined(SGX_FEATURE_MP)
351 #define FIX_HW_BRN_31425
352 #endif
353 #define FIX_HW_BRN_31542
354 #define FIX_HW_BRN_32044
252 355
253 #else 356 #else
254 #if SGX_CORE_REV == SGX_CORE_REV_HEAD 357 #if SGX_CORE_REV == SGX_CORE_REV_HEAD
@@ -259,6 +362,12 @@
259 #endif 362 #endif
260 #endif 363 #endif
261 #endif 364 #endif
365 #endif
366 #endif
367 #endif
368 #endif
369 #endif
370 #endif
262 371
263 #define SGX_CORE_DEFINED 372 #define SGX_CORE_DEFINED
264#endif 373#endif
@@ -272,7 +381,24 @@
272 #endif 381 #endif
273 382
274 #if SGX_CORE_REV == 100 383 #if SGX_CORE_REV == 100
275 384 #if defined(SGX_FEATURE_MP)
385 #define FIX_HW_BRN_31425
386 #endif
387 #else
388 #if SGX_CORE_REV == 102
389 #if defined(SGX_FEATURE_MP)
390 #define FIX_HW_BRN_31425
391 #endif
392 #else
393 #if SGX_CORE_REV == 103
394 #if defined(SGX_FEATURE_MP)
395 #define FIX_HW_BRN_31425
396 #endif
397 #else
398 #if SGX_CORE_REV == 105
399 #if defined(SGX_FEATURE_MP)
400 #define FIX_HW_BRN_31425
401 #endif
276 #else 402 #else
277 #if SGX_CORE_REV == SGX_CORE_REV_HEAD 403 #if SGX_CORE_REV == SGX_CORE_REV_HEAD
278 404
@@ -280,6 +406,9 @@
280 #error "sgxerrata.h: SGX544 Core Revision unspecified" 406 #error "sgxerrata.h: SGX544 Core Revision unspecified"
281 #endif 407 #endif
282 #endif 408 #endif
409 #endif
410 #endif
411 #endif
283 412
284 #define SGX_CORE_DEFINED 413 #define SGX_CORE_DEFINED
285#endif 414#endif
@@ -302,12 +431,13 @@
302 #if SGX_CORE_REV == 109 431 #if SGX_CORE_REV == 109
303 #define FIX_HW_BRN_29702 432 #define FIX_HW_BRN_29702
304 #define FIX_HW_BRN_29823 433 #define FIX_HW_BRN_29823
434 #define FIX_HW_BRN_31939
305 #else 435 #else
306 #if SGX_CORE_REV == 1012 436 #if SGX_CORE_REV == 1012
307 #define FIX_HW_BRN_29823 437 #define FIX_HW_BRN_31939
308 #else 438 #else
309 #if SGX_CORE_REV == 1013 439 #if SGX_CORE_REV == 1013
310 #define FIX_HW_BRN_29823 440 #define FIX_HW_BRN_31939
311 #else 441 #else
312 #if SGX_CORE_REV == SGX_CORE_REV_HEAD 442 #if SGX_CORE_REV == SGX_CORE_REV_HEAD
313 443
@@ -331,6 +461,16 @@
331 #endif 461 #endif
332 462
333 #if SGX_CORE_REV == 100 463 #if SGX_CORE_REV == 100
464 #if defined(SGX_FEATURE_MP)
465 #define FIX_HW_BRN_31425
466 #endif
467 #else
468 #if SGX_CORE_REV == 101
469 #if defined(SGX_FEATURE_MP)
470 #define FIX_HW_BRN_31425
471 #endif
472 #else
473 #if SGX_CORE_REV == 123
334 474
335 #else 475 #else
336 #if SGX_CORE_REV == SGX_CORE_REV_HEAD 476 #if SGX_CORE_REV == SGX_CORE_REV_HEAD
@@ -339,6 +479,8 @@
339 #error "sgxerrata.h: SGX554 Core Revision unspecified" 479 #error "sgxerrata.h: SGX554 Core Revision unspecified"
340 #endif 480 #endif
341 #endif 481 #endif
482 #endif
483 #endif
342 484
343 #define SGX_CORE_DEFINED 485 #define SGX_CORE_DEFINED
344#endif 486#endif
diff --git a/drivers/gpu/pvr/sgxfeaturedefs.h b/drivers/gpu/pvr/sgxfeaturedefs.h
index 714bea3027a..97da0078e3b 100644
--- a/drivers/gpu/pvr/sgxfeaturedefs.h
+++ b/drivers/gpu/pvr/sgxfeaturedefs.h
@@ -52,6 +52,7 @@
52 #define SGX_FEATURE_2D_HARDWARE 52 #define SGX_FEATURE_2D_HARDWARE
53 #define SGX_FEATURE_AUTOCLOCKGATING 53 #define SGX_FEATURE_AUTOCLOCKGATING
54 #define SUPPORT_SGX_GENERAL_MAPPING_HEAP 54 #define SUPPORT_SGX_GENERAL_MAPPING_HEAP
55 #define SGX_FEATURE_EDM_VERTEX_PDSADDR_FULL_RANGE
55#else 56#else
56#if defined(SGX540) 57#if defined(SGX540)
57 #define SGX_CORE_FRIENDLY_NAME "SGX540" 58 #define SGX_CORE_FRIENDLY_NAME "SGX540"
@@ -60,16 +61,6 @@
60 #define SGX_FEATURE_AUTOCLOCKGATING 61 #define SGX_FEATURE_AUTOCLOCKGATING
61 #define SGX_FEATURE_MULTI_EVENT_KICK 62 #define SGX_FEATURE_MULTI_EVENT_KICK
62#else 63#else
63#if defined(SGX541)
64 #define SGX_CORE_FRIENDLY_NAME "SGX541"
65 #define SGX_CORE_ID SGX_CORE_ID_541
66 #define SGX_FEATURE_ADDRESS_SPACE_SIZE (32)
67 #define SGX_FEATURE_MULTIPLE_MEM_CONTEXTS
68 #define SGX_FEATURE_BIF_NUM_DIRLISTS (8)
69 #define SGX_FEATURE_AUTOCLOCKGATING
70 #define SGX_FEATURE_SPM_MODE_0
71 #define SGX_FEATURE_MULTI_EVENT_KICK
72#else
73#if defined(SGX543) 64#if defined(SGX543)
74 #define SGX_CORE_FRIENDLY_NAME "SGX543" 65 #define SGX_CORE_FRIENDLY_NAME "SGX543"
75 #define SGX_CORE_ID SGX_CORE_ID_543 66 #define SGX_CORE_ID SGX_CORE_ID_543
@@ -83,9 +74,19 @@
83 #define SGX_FEATURE_SPM_MODE_0 74 #define SGX_FEATURE_SPM_MODE_0
84 #define SGX_FEATURE_MULTI_EVENT_KICK 75 #define SGX_FEATURE_MULTI_EVENT_KICK
85 #define SGX_FEATURE_DATA_BREAKPOINTS 76 #define SGX_FEATURE_DATA_BREAKPOINTS
77 #define SGX_FEATURE_PERPIPE_BKPT_REGS
78 #define SGX_FEATURE_PERPIPE_BKPT_REGS_NUMPIPES (2)
86 #define SGX_FEATURE_2D_HARDWARE 79 #define SGX_FEATURE_2D_HARDWARE
87 #define SGX_FEATURE_PTLA 80 #define SGX_FEATURE_PTLA
88 #define SGX_FEATURE_EXTENDED_PERF_COUNTERS 81 #define SGX_FEATURE_EXTENDED_PERF_COUNTERS
82 #define SGX_FEATURE_EDM_VERTEX_PDSADDR_FULL_RANGE
83 #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING)
84 #if defined(SGX_FEATURE_MP)
85 #define SGX_FEATURE_MASTER_VDM_CONTEXT_SWITCH
86 #endif
87 #define SGX_FEATURE_SLAVE_VDM_CONTEXT_SWITCH
88 #define SGX_FEATURE_ISP_CONTEXT_SWITCH_REV_3
89 #endif
89#else 90#else
90#if defined(SGX544) 91#if defined(SGX544)
91 #define SGX_CORE_FRIENDLY_NAME "SGX544" 92 #define SGX_CORE_FRIENDLY_NAME "SGX544"
@@ -99,8 +100,15 @@
99 #define SGX_FEATURE_MONOLITHIC_UKERNEL 100 #define SGX_FEATURE_MONOLITHIC_UKERNEL
100 #define SGX_FEATURE_SPM_MODE_0 101 #define SGX_FEATURE_SPM_MODE_0
101 #define SGX_FEATURE_MULTI_EVENT_KICK 102 #define SGX_FEATURE_MULTI_EVENT_KICK
102 #define SGX_FEATURE_DATA_BREAKPOINTS
103 #define SGX_FEATURE_EXTENDED_PERF_COUNTERS 103 #define SGX_FEATURE_EXTENDED_PERF_COUNTERS
104 #define SGX_FEATURE_EDM_VERTEX_PDSADDR_FULL_RANGE
105 #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING)
106 #if defined(SGX_FEATURE_MP)
107 #define SGX_FEATURE_MASTER_VDM_CONTEXT_SWITCH
108 #endif
109 #define SGX_FEATURE_SLAVE_VDM_CONTEXT_SWITCH
110 #define SGX_FEATURE_ISP_CONTEXT_SWITCH_REV_3
111 #endif
104#else 112#else
105#if defined(SGX545) 113#if defined(SGX545)
106 #define SGX_CORE_FRIENDLY_NAME "SGX545" 114 #define SGX_CORE_FRIENDLY_NAME "SGX545"
@@ -130,6 +138,14 @@
130 138
131 #define SGX_FEATURE_BIF_WIDE_TILING_AND_4K_ADDRESS 139 #define SGX_FEATURE_BIF_WIDE_TILING_AND_4K_ADDRESS
132 #define SGX_FEATURE_MULTI_EVENT_KICK 140 #define SGX_FEATURE_MULTI_EVENT_KICK
141 #define SGX_FEATURE_EDM_VERTEX_PDSADDR_FULL_RANGE
142 #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING)
143 #if defined(USE_SGX_CORE_REV_HEAD)
144 #define SGX_FEATURE_FAST_RENDER_CONTEXT_SWITCH
145 #endif
146 #define SGX_FEATURE_SLAVE_VDM_CONTEXT_SWITCH
147 #define SGX_FEATURE_ISP_CONTEXT_SWITCH_REV_2
148 #endif
133#else 149#else
134#if defined(SGX554) 150#if defined(SGX554)
135 #define SGX_CORE_FRIENDLY_NAME "SGX554" 151 #define SGX_CORE_FRIENDLY_NAME "SGX554"
@@ -143,8 +159,17 @@
143 #define SGX_FEATURE_MONOLITHIC_UKERNEL 159 #define SGX_FEATURE_MONOLITHIC_UKERNEL
144 #define SGX_FEATURE_SPM_MODE_0 160 #define SGX_FEATURE_SPM_MODE_0
145 #define SGX_FEATURE_MULTI_EVENT_KICK 161 #define SGX_FEATURE_MULTI_EVENT_KICK
146 #define SGX_FEATURE_DATA_BREAKPOINTS 162 #define SGX_FEATURE_2D_HARDWARE
163 #define SGX_FEATURE_PTLA
147 #define SGX_FEATURE_EXTENDED_PERF_COUNTERS 164 #define SGX_FEATURE_EXTENDED_PERF_COUNTERS
165 #define SGX_FEATURE_EDM_VERTEX_PDSADDR_FULL_RANGE
166 #if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING)
167 #if defined(SGX_FEATURE_MP)
168 #define SGX_FEATURE_MASTER_VDM_CONTEXT_SWITCH
169 #endif
170 #define SGX_FEATURE_SLAVE_VDM_CONTEXT_SWITCH
171 #define SGX_FEATURE_ISP_CONTEXT_SWITCH_REV_3
172 #endif
148#endif 173#endif
149#endif 174#endif
150#endif 175#endif
@@ -154,6 +179,15 @@
154#endif 179#endif
155#endif 180#endif
156#endif 181#endif
182
183#if defined(SGX_FEATURE_SLAVE_VDM_CONTEXT_SWITCH) \
184 || defined(SGX_FEATURE_MASTER_VDM_CONTEXT_SWITCH)
185#define SGX_FEATURE_VDM_CONTEXT_SWITCH
186#endif
187
188#if defined(SGX_FEATURE_ISP_CONTEXT_SWITCH_REV_2) \
189 || defined(SGX_FEATURE_ISP_CONTEXT_SWITCH_REV_3)
190#define SGX_FEATURE_ISP_CONTEXT_SWITCH
157#endif 191#endif
158 192
159#if defined(FIX_HW_BRN_22693) 193#if defined(FIX_HW_BRN_22693)
@@ -182,14 +216,36 @@
182 #endif 216 #endif
183#endif 217#endif
184 218
185#if defined(SGX_FEATURE_MP) 219#if defined(FIX_HW_BRN_29954)
186#if !defined(SGX_FEATURE_MP_CORE_COUNT) 220#undef SGX_FEATURE_PERPIPE_BKPT_REGS
187#error SGX_FEATURE_MP_CORE_COUNT must be defined when SGX_FEATURE_MP is defined
188#endif 221#endif
189#else 222
190#define SGX_FEATURE_MP_CORE_COUNT (1) 223#if defined(FIX_HW_BRN_31620)
224#undef SGX_FEATURE_MULTIPLE_MEM_CONTEXTS
225#undef SGX_FEATURE_BIF_NUM_DIRLISTS
191#endif 226#endif
192 227
228#if defined(SGX_FEATURE_MP)
229#if defined(SGX_FEATURE_MP_CORE_COUNT_TA) && defined(SGX_FEATURE_MP_CORE_COUNT_3D)
230#if (SGX_FEATURE_MP_CORE_COUNT_TA > SGX_FEATURE_MP_CORE_COUNT_3D)
231#error Number of TA cores larger than number of 3D cores not supported in current driver
232#endif
233#else
234#if defined(SGX_FEATURE_MP_CORE_COUNT)
235#define SGX_FEATURE_MP_CORE_COUNT_TA (SGX_FEATURE_MP_CORE_COUNT)
236#define SGX_FEATURE_MP_CORE_COUNT_3D (SGX_FEATURE_MP_CORE_COUNT)
237#else
238#error Either SGX_FEATURE_MP_CORE_COUNT or \
239both SGX_FEATURE_MP_CORE_COUNT_TA and SGX_FEATURE_MP_CORE_COUNT_3D \
240must be defined when SGX_FEATURE_MP is defined
241#endif
242#endif
243#else
244#define SGX_FEATURE_MP_CORE_COUNT (1)
245#define SGX_FEATURE_MP_CORE_COUNT_TA (1)
246#define SGX_FEATURE_MP_CORE_COUNT_3D (1)
247#endif
248
193#if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && !defined(SUPPORT_SGX_PRIORITY_SCHEDULING) 249#if defined(SUPPORT_SGX_LOW_LATENCY_SCHEDULING) && !defined(SUPPORT_SGX_PRIORITY_SCHEDULING)
194#define SUPPORT_SGX_PRIORITY_SCHEDULING 250#define SUPPORT_SGX_PRIORITY_SCHEDULING
195#endif 251#endif
diff --git a/drivers/gpu/pvr/sgxinfo.h b/drivers/gpu/pvr/sgxinfo.h
index 50f11134b43..51870873eec 100644
--- a/drivers/gpu/pvr/sgxinfo.h
+++ b/drivers/gpu/pvr/sgxinfo.h
@@ -30,12 +30,14 @@
30#include "sgxscript.h" 30#include "sgxscript.h"
31#include "servicesint.h" 31#include "servicesint.h"
32#include "services.h" 32#include "services.h"
33#if !defined (SUPPORT_SID_INTERFACE)
33#include "sgxapi_km.h" 34#include "sgxapi_km.h"
35#endif
34#include "sgx_mkif_km.h" 36#include "sgx_mkif_km.h"
35 37
36 38
37#define SGX_MAX_DEV_DATA 24 39#define SGX_MAX_DEV_DATA 24
38#define SGX_MAX_INIT_MEM_HANDLES 16 40#define SGX_MAX_INIT_MEM_HANDLES 18
39 41
40 42
41typedef struct _SGX_BRIDGE_INFO_FOR_SRVINIT 43typedef struct _SGX_BRIDGE_INFO_FOR_SRVINIT
@@ -51,12 +53,14 @@ typedef enum _SGXMKIF_CMD_TYPE_
51 SGXMKIF_CMD_TRANSFER = 1, 53 SGXMKIF_CMD_TRANSFER = 1,
52 SGXMKIF_CMD_2D = 2, 54 SGXMKIF_CMD_2D = 2,
53 SGXMKIF_CMD_POWER = 3, 55 SGXMKIF_CMD_POWER = 3,
54 SGXMKIF_CMD_CLEANUP = 4, 56 SGXMKIF_CMD_CONTEXTSUSPEND = 4,
55 SGXMKIF_CMD_GETMISCINFO = 5, 57 SGXMKIF_CMD_CLEANUP = 5,
56 SGXMKIF_CMD_PROCESS_QUEUES = 6, 58 SGXMKIF_CMD_GETMISCINFO = 6,
57 SGXMKIF_CMD_DATABREAKPOINT = 7, 59 SGXMKIF_CMD_PROCESS_QUEUES = 7,
58 SGXMKIF_CMD_SETHWPERFSTATUS = 8, 60 SGXMKIF_CMD_DATABREAKPOINT = 8,
59 SGXMKIF_CMD_MAX = 9, 61 SGXMKIF_CMD_SETHWPERFSTATUS = 9,
62 SGXMKIF_CMD_FLUSHPDCACHE = 10,
63 SGXMKIF_CMD_MAX = 11,
60 64
61 SGXMKIF_CMD_FORCE_I32 = -1, 65 SGXMKIF_CMD_FORCE_I32 = -1,
62 66
@@ -65,12 +69,21 @@ typedef enum _SGXMKIF_CMD_TYPE_
65 69
66typedef struct _SGX_BRIDGE_INIT_INFO_ 70typedef struct _SGX_BRIDGE_INIT_INFO_
67{ 71{
72#if defined (SUPPORT_SID_INTERFACE)
73 IMG_SID hKernelCCBMemInfo;
74 IMG_SID hKernelCCBCtlMemInfo;
75 IMG_SID hKernelCCBEventKickerMemInfo;
76 IMG_SID hKernelSGXHostCtlMemInfo;
77 IMG_SID hKernelSGXTA3DCtlMemInfo;
78 IMG_SID hKernelSGXMiscMemInfo;
79#else
68 IMG_HANDLE hKernelCCBMemInfo; 80 IMG_HANDLE hKernelCCBMemInfo;
69 IMG_HANDLE hKernelCCBCtlMemInfo; 81 IMG_HANDLE hKernelCCBCtlMemInfo;
70 IMG_HANDLE hKernelCCBEventKickerMemInfo; 82 IMG_HANDLE hKernelCCBEventKickerMemInfo;
71 IMG_HANDLE hKernelSGXHostCtlMemInfo; 83 IMG_HANDLE hKernelSGXHostCtlMemInfo;
72 IMG_HANDLE hKernelSGXTA3DCtlMemInfo; 84 IMG_HANDLE hKernelSGXTA3DCtlMemInfo;
73 IMG_HANDLE hKernelSGXMiscMemInfo; 85 IMG_HANDLE hKernelSGXMiscMemInfo;
86#endif
74 87
75 IMG_UINT32 aui32HostKickAddr[SGXMKIF_CMD_MAX]; 88 IMG_UINT32 aui32HostKickAddr[SGXMKIF_CMD_MAX];
76 89
@@ -80,33 +93,95 @@ typedef struct _SGX_BRIDGE_INIT_INFO_
80 SGX_MISCINFO_STRUCT_SIZES sSGXStructSizes; 93 SGX_MISCINFO_STRUCT_SIZES sSGXStructSizes;
81 94
82#if defined(SGX_SUPPORT_HWPROFILING) 95#if defined(SGX_SUPPORT_HWPROFILING)
96#if defined (SUPPORT_SID_INTERFACE)
97 IMG_SID hKernelHWProfilingMemInfo;
98#else
83 IMG_HANDLE hKernelHWProfilingMemInfo; 99 IMG_HANDLE hKernelHWProfilingMemInfo;
84#endif 100#endif
101#endif
85#if defined(SUPPORT_SGX_HWPERF) 102#if defined(SUPPORT_SGX_HWPERF)
103#if defined (SUPPORT_SID_INTERFACE)
104 IMG_SID hKernelHWPerfCBMemInfo;
105#else
86 IMG_HANDLE hKernelHWPerfCBMemInfo; 106 IMG_HANDLE hKernelHWPerfCBMemInfo;
87#endif 107#endif
108#endif
109#if defined (SUPPORT_SID_INTERFACE)
110 IMG_SID hKernelTASigBufferMemInfo;
111 IMG_SID hKernel3DSigBufferMemInfo;
112#else
88 IMG_HANDLE hKernelTASigBufferMemInfo; 113 IMG_HANDLE hKernelTASigBufferMemInfo;
89 IMG_HANDLE hKernel3DSigBufferMemInfo; 114 IMG_HANDLE hKernel3DSigBufferMemInfo;
115#endif
90 116
91#if defined(FIX_HW_BRN_29702) 117#if defined(FIX_HW_BRN_29702)
118#if defined (SUPPORT_SID_INTERFACE)
119 IMG_SID hKernelCFIMemInfo;
120#else
92 IMG_HANDLE hKernelCFIMemInfo; 121 IMG_HANDLE hKernelCFIMemInfo;
93#endif 122#endif
123#endif
94#if defined(FIX_HW_BRN_29823) 124#if defined(FIX_HW_BRN_29823)
125#if defined (SUPPORT_SID_INTERFACE)
126 IMG_SID hKernelDummyTermStreamMemInfo;
127#else
95 IMG_HANDLE hKernelDummyTermStreamMemInfo; 128 IMG_HANDLE hKernelDummyTermStreamMemInfo;
96#endif 129#endif
130#endif
131
132#if defined(FIX_HW_BRN_31542)
133#if defined (SUPPORT_SID_INTERFACE)
134 IMG_SID hKernelClearClipWAVDMStreamMemInfo;
135 IMG_SID hKernelClearClipWAIndexStreamMemInfo;
136 IMG_SID hKernelClearClipWAPDSMemInfo;
137 IMG_SID hKernelClearClipWAUSEMemInfo;
138 IMG_SID hKernelClearClipWAParamMemInfo;
139 IMG_SID hKernelClearClipWAPMPTMemInfo;
140 IMG_SID hKernelClearClipWATPCMemInfo;
141 IMG_SID hKernelClearClipWAPSGRgnHdrMemInfo;
142#else
143 IMG_HANDLE hKernelClearClipWAVDMStreamMemInfo;
144 IMG_HANDLE hKernelClearClipWAIndexStreamMemInfo;
145 IMG_HANDLE hKernelClearClipWAPDSMemInfo;
146 IMG_HANDLE hKernelClearClipWAUSEMemInfo;
147 IMG_HANDLE hKernelClearClipWAParamMemInfo;
148 IMG_HANDLE hKernelClearClipWAPMPTMemInfo;
149 IMG_HANDLE hKernelClearClipWATPCMemInfo;
150 IMG_HANDLE hKernelClearClipWAPSGRgnHdrMemInfo;
151#endif
152#endif
153
154#if defined(SGX_FEATURE_VDM_CONTEXT_SWITCH) && defined(FIX_HW_BRN_31425)
155 IMG_HANDLE hKernelVDMSnapShotBufferMemInfo;
156 IMG_HANDLE hKernelVDMCtrlStreamBufferMemInfo;
157#endif
97#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG) 158#if defined(PVRSRV_USSE_EDM_STATUS_DEBUG)
159#if defined (SUPPORT_SID_INTERFACE)
160 IMG_SID hKernelEDMStatusBufferMemInfo;
161#else
98 IMG_HANDLE hKernelEDMStatusBufferMemInfo; 162 IMG_HANDLE hKernelEDMStatusBufferMemInfo;
99#endif 163#endif
164#endif
100#if defined(SGX_FEATURE_OVERLAPPED_SPM) 165#if defined(SGX_FEATURE_OVERLAPPED_SPM)
166#if defined (SUPPORT_SID_INTERFACE)
167 IMG_SID hKernelTmpRgnHeaderMemInfo;
168#else
101 IMG_HANDLE hKernelTmpRgnHeaderMemInfo; 169 IMG_HANDLE hKernelTmpRgnHeaderMemInfo;
102#endif 170#endif
171#endif
103#if defined(SGX_FEATURE_SPM_MODE_0) 172#if defined(SGX_FEATURE_SPM_MODE_0)
173#if defined (SUPPORT_SID_INTERFACE)
174 IMG_SID hKernelTmpDPMStateMemInfo;
175#else
104 IMG_HANDLE hKernelTmpDPMStateMemInfo; 176 IMG_HANDLE hKernelTmpDPMStateMemInfo;
105#endif 177#endif
178#endif
106 179
107 IMG_UINT32 ui32EDMTaskReg0; 180 IMG_UINT32 ui32EDMTaskReg0;
108 IMG_UINT32 ui32EDMTaskReg1; 181 IMG_UINT32 ui32EDMTaskReg1;
109 182
183 IMG_UINT32 ui32ClkGateCtl;
184 IMG_UINT32 ui32ClkGateCtl2;
110 IMG_UINT32 ui32ClkGateStatusReg; 185 IMG_UINT32 ui32ClkGateStatusReg;
111 IMG_UINT32 ui32ClkGateStatusMask; 186 IMG_UINT32 ui32ClkGateStatusMask;
112#if defined(SGX_FEATURE_MP) 187#if defined(SGX_FEATURE_MP)
@@ -119,7 +194,11 @@ typedef struct _SGX_BRIDGE_INIT_INFO_
119 IMG_UINT32 ui32CacheControl; 194 IMG_UINT32 ui32CacheControl;
120 195
121 IMG_UINT32 asInitDevData[SGX_MAX_DEV_DATA]; 196 IMG_UINT32 asInitDevData[SGX_MAX_DEV_DATA];
197#if defined (SUPPORT_SID_INTERFACE)
198 IMG_SID asInitMemHandles[SGX_MAX_INIT_MEM_HANDLES];
199#else
122 IMG_HANDLE asInitMemHandles[SGX_MAX_INIT_MEM_HANDLES]; 200 IMG_HANDLE asInitMemHandles[SGX_MAX_INIT_MEM_HANDLES];
201#endif
123 202
124} SGX_BRIDGE_INIT_INFO; 203} SGX_BRIDGE_INIT_INFO;
125 204
@@ -128,7 +207,11 @@ typedef struct _SGX_DEVICE_SYNC_LIST_
128{ 207{
129 PSGXMKIF_HWDEVICE_SYNC_LIST psHWDeviceSyncList; 208 PSGXMKIF_HWDEVICE_SYNC_LIST psHWDeviceSyncList;
130 209
210#if defined (SUPPORT_SID_INTERFACE)
211 IMG_SID hKernelHWSyncListMemInfo;
212#else
131 IMG_HANDLE hKernelHWSyncListMemInfo; 213 IMG_HANDLE hKernelHWSyncListMemInfo;
214#endif
132 PVRSRV_CLIENT_MEM_INFO *psHWDeviceSyncListClientMemInfo; 215 PVRSRV_CLIENT_MEM_INFO *psHWDeviceSyncListClientMemInfo;
133 PVRSRV_CLIENT_MEM_INFO *psAccessResourceClientMemInfo; 216 PVRSRV_CLIENT_MEM_INFO *psAccessResourceClientMemInfo;
134 217
@@ -138,27 +221,47 @@ typedef struct _SGX_DEVICE_SYNC_LIST_
138 221
139 222
140 IMG_UINT32 ui32NumSyncObjects; 223 IMG_UINT32 ui32NumSyncObjects;
224#if defined (SUPPORT_SID_INTERFACE)
225 IMG_SID ahSyncHandles[1];
226#else
141 IMG_HANDLE ahSyncHandles[1]; 227 IMG_HANDLE ahSyncHandles[1];
228#endif
142} SGX_DEVICE_SYNC_LIST, *PSGX_DEVICE_SYNC_LIST; 229} SGX_DEVICE_SYNC_LIST, *PSGX_DEVICE_SYNC_LIST;
143 230
144 231
145typedef struct _SGX_INTERNEL_STATUS_UPDATE_ 232typedef struct _SGX_INTERNEL_STATUS_UPDATE_
146{ 233{
147 CTL_STATUS sCtlStatus; 234 CTL_STATUS sCtlStatus;
235#if defined (SUPPORT_SID_INTERFACE)
236 IMG_SID hKernelMemInfo;
237#else
148 IMG_HANDLE hKernelMemInfo; 238 IMG_HANDLE hKernelMemInfo;
239#endif
149} SGX_INTERNEL_STATUS_UPDATE; 240} SGX_INTERNEL_STATUS_UPDATE;
150 241
151 242
152typedef struct _SGX_CCB_KICK_ 243typedef struct _SGX_CCB_KICK_
153{ 244{
154 SGXMKIF_COMMAND sCommand; 245 SGXMKIF_COMMAND sCommand;
155 IMG_HANDLE hCCBKernelMemInfo; 246#if defined (SUPPORT_SID_INTERFACE)
247 IMG_SID hCCBKernelMemInfo;
248#else
249 IMG_HANDLE hCCBKernelMemInfo;
250#endif
156 251
157 IMG_UINT32 ui32NumDstSyncObjects; 252 IMG_UINT32 ui32NumDstSyncObjects;
253#if defined (SUPPORT_SID_INTERFACE)
254 IMG_SID hKernelHWSyncListMemInfo;
255#else
158 IMG_HANDLE hKernelHWSyncListMemInfo; 256 IMG_HANDLE hKernelHWSyncListMemInfo;
257#endif
159 258
160 259
260#if defined (SUPPORT_SID_INTERFACE)
261 IMG_SID *pahDstSyncHandles;
262#else
161 IMG_HANDLE *pahDstSyncHandles; 263 IMG_HANDLE *pahDstSyncHandles;
264#endif
162 265
163 IMG_UINT32 ui32NumTAStatusVals; 266 IMG_UINT32 ui32NumTAStatusVals;
164 IMG_UINT32 ui32Num3DStatusVals; 267 IMG_UINT32 ui32Num3DStatusVals;
@@ -167,9 +270,14 @@ typedef struct _SGX_CCB_KICK_
167 SGX_INTERNEL_STATUS_UPDATE asTAStatusUpdate[SGX_MAX_TA_STATUS_VALS]; 270 SGX_INTERNEL_STATUS_UPDATE asTAStatusUpdate[SGX_MAX_TA_STATUS_VALS];
168 SGX_INTERNEL_STATUS_UPDATE as3DStatusUpdate[SGX_MAX_3D_STATUS_VALS]; 271 SGX_INTERNEL_STATUS_UPDATE as3DStatusUpdate[SGX_MAX_3D_STATUS_VALS];
169#else 272#else
273#if defined (SUPPORT_SID_INTERFACE)
274 IMG_SID ahTAStatusSyncInfo[SGX_MAX_TA_STATUS_VALS];
275 IMG_SID ah3DStatusSyncInfo[SGX_MAX_3D_STATUS_VALS];
276#else
170 IMG_HANDLE ahTAStatusSyncInfo[SGX_MAX_TA_STATUS_VALS]; 277 IMG_HANDLE ahTAStatusSyncInfo[SGX_MAX_TA_STATUS_VALS];
171 IMG_HANDLE ah3DStatusSyncInfo[SGX_MAX_3D_STATUS_VALS]; 278 IMG_HANDLE ah3DStatusSyncInfo[SGX_MAX_3D_STATUS_VALS];
172#endif 279#endif
280#endif
173 281
174 IMG_BOOL bFirstKickOrResume; 282 IMG_BOOL bFirstKickOrResume;
175#if (defined(NO_HARDWARE) || defined(PDUMP)) 283#if (defined(NO_HARDWARE) || defined(PDUMP))
@@ -183,29 +291,53 @@ typedef struct _SGX_CCB_KICK_
183#if defined(SUPPORT_SGX_GENERALISED_SYNCOBJECTS) 291#if defined(SUPPORT_SGX_GENERALISED_SYNCOBJECTS)
184 292
185 IMG_UINT32 ui32NumTASrcSyncs; 293 IMG_UINT32 ui32NumTASrcSyncs;
294#if defined (SUPPORT_SID_INTERFACE)
295 IMG_SID ahTASrcKernelSyncInfo[SGX_MAX_TA_SRC_SYNCS];
296#else
186 IMG_HANDLE ahTASrcKernelSyncInfo[SGX_MAX_TA_SRC_SYNCS]; 297 IMG_HANDLE ahTASrcKernelSyncInfo[SGX_MAX_TA_SRC_SYNCS];
298#endif
187 IMG_UINT32 ui32NumTADstSyncs; 299 IMG_UINT32 ui32NumTADstSyncs;
300#if defined (SUPPORT_SID_INTERFACE)
301 IMG_SID ahTADstKernelSyncInfo[SGX_MAX_TA_DST_SYNCS];
302#else
188 IMG_HANDLE ahTADstKernelSyncInfo[SGX_MAX_TA_DST_SYNCS]; 303 IMG_HANDLE ahTADstKernelSyncInfo[SGX_MAX_TA_DST_SYNCS];
304#endif
189 IMG_UINT32 ui32Num3DSrcSyncs; 305 IMG_UINT32 ui32Num3DSrcSyncs;
306#if defined (SUPPORT_SID_INTERFACE)
307 IMG_SID ah3DSrcKernelSyncInfo[SGX_MAX_3D_SRC_SYNCS];
308#else
190 IMG_HANDLE ah3DSrcKernelSyncInfo[SGX_MAX_3D_SRC_SYNCS]; 309 IMG_HANDLE ah3DSrcKernelSyncInfo[SGX_MAX_3D_SRC_SYNCS];
310#endif
191#else 311#else
192 312
193 IMG_UINT32 ui32NumSrcSyncs; 313 IMG_UINT32 ui32NumSrcSyncs;
314#if defined (SUPPORT_SID_INTERFACE)
315 IMG_SID ahSrcKernelSyncInfo[SGX_MAX_SRC_SYNCS];
316#else
194 IMG_HANDLE ahSrcKernelSyncInfo[SGX_MAX_SRC_SYNCS]; 317 IMG_HANDLE ahSrcKernelSyncInfo[SGX_MAX_SRC_SYNCS];
195#endif 318#endif
319#endif
196 320
197 321
198 IMG_BOOL bTADependency; 322 IMG_BOOL bTADependency;
323#if defined (SUPPORT_SID_INTERFACE)
324 IMG_SID hTA3DSyncInfo;
325
326 IMG_SID hTASyncInfo;
327 IMG_SID h3DSyncInfo;
328#else
199 IMG_HANDLE hTA3DSyncInfo; 329 IMG_HANDLE hTA3DSyncInfo;
200 330
201 IMG_HANDLE hTASyncInfo; 331 IMG_HANDLE hTASyncInfo;
202 IMG_HANDLE h3DSyncInfo; 332 IMG_HANDLE h3DSyncInfo;
333#endif
203#if defined(PDUMP) 334#if defined(PDUMP)
204 IMG_UINT32 ui32CCBDumpWOff; 335 IMG_UINT32 ui32CCBDumpWOff;
205#endif 336#endif
206#if defined(NO_HARDWARE) 337#if defined(NO_HARDWARE)
207 IMG_UINT32 ui32WriteOpsPendingVal; 338 IMG_UINT32 ui32WriteOpsPendingVal;
208#endif 339#endif
340 IMG_HANDLE hDevMemContext;
209} SGX_CCB_KICK; 341} SGX_CCB_KICK;
210 342
211 343
@@ -225,27 +357,56 @@ typedef struct _SGX_CLIENT_INFO_
225typedef struct _SGX_INTERNAL_DEVINFO_ 357typedef struct _SGX_INTERNAL_DEVINFO_
226{ 358{
227 IMG_UINT32 ui32Flags; 359 IMG_UINT32 ui32Flags;
360#if defined (SUPPORT_SID_INTERFACE)
361 IMG_SID hHostCtlKernelMemInfoHandle;
362#else
228 IMG_HANDLE hHostCtlKernelMemInfoHandle; 363 IMG_HANDLE hHostCtlKernelMemInfoHandle;
364#endif
229 IMG_BOOL bForcePTOff; 365 IMG_BOOL bForcePTOff;
230} SGX_INTERNAL_DEVINFO; 366} SGX_INTERNAL_DEVINFO;
231 367
232 368
369typedef struct _SGX_INTERNAL_DEVINFO_KM_
370{
371 IMG_UINT32 ui32Flags;
372 IMG_HANDLE hHostCtlKernelMemInfoHandle;
373 IMG_BOOL bForcePTOff;
374} SGX_INTERNAL_DEVINFO_KM;
375
376
233#if defined(TRANSFER_QUEUE) 377#if defined(TRANSFER_QUEUE)
234typedef struct _PVRSRV_TRANSFER_SGX_KICK_ 378typedef struct _PVRSRV_TRANSFER_SGX_KICK_
235{ 379{
380#if defined (SUPPORT_SID_INTERFACE)
381 IMG_SID hCCBMemInfo;
382#else
236 IMG_HANDLE hCCBMemInfo; 383 IMG_HANDLE hCCBMemInfo;
384#endif
237 IMG_UINT32 ui32SharedCmdCCBOffset; 385 IMG_UINT32 ui32SharedCmdCCBOffset;
238 386
239 IMG_DEV_VIRTADDR sHWTransferContextDevVAddr; 387 IMG_DEV_VIRTADDR sHWTransferContextDevVAddr;
240 388
389#if defined (SUPPORT_SID_INTERFACE)
390 IMG_SID hTASyncInfo;
391 IMG_SID h3DSyncInfo;
392#else
241 IMG_HANDLE hTASyncInfo; 393 IMG_HANDLE hTASyncInfo;
242 IMG_HANDLE h3DSyncInfo; 394 IMG_HANDLE h3DSyncInfo;
395#endif
243 396
244 IMG_UINT32 ui32NumSrcSync; 397 IMG_UINT32 ui32NumSrcSync;
398#if defined (SUPPORT_SID_INTERFACE)
399 IMG_SID ahSrcSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS];
400#else
245 IMG_HANDLE ahSrcSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS]; 401 IMG_HANDLE ahSrcSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS];
402#endif
246 403
247 IMG_UINT32 ui32NumDstSync; 404 IMG_UINT32 ui32NumDstSync;
405#if defined (SUPPORT_SID_INTERFACE)
406 IMG_SID ahDstSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS];
407#else
248 IMG_HANDLE ahDstSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS]; 408 IMG_HANDLE ahDstSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS];
409#endif
249 410
250 IMG_UINT32 ui32Flags; 411 IMG_UINT32 ui32Flags;
251 412
@@ -253,17 +414,34 @@ typedef struct _PVRSRV_TRANSFER_SGX_KICK_
253#if defined(PDUMP) 414#if defined(PDUMP)
254 IMG_UINT32 ui32CCBDumpWOff; 415 IMG_UINT32 ui32CCBDumpWOff;
255#endif 416#endif
417 IMG_HANDLE hDevMemContext;
256} PVRSRV_TRANSFER_SGX_KICK, *PPVRSRV_TRANSFER_SGX_KICK; 418} PVRSRV_TRANSFER_SGX_KICK, *PPVRSRV_TRANSFER_SGX_KICK;
257 419
258#if defined(SGX_FEATURE_2D_HARDWARE) 420#if defined(SGX_FEATURE_2D_HARDWARE)
259typedef struct _PVRSRV_2D_SGX_KICK_ 421typedef struct _PVRSRV_2D_SGX_KICK_
260{ 422{
423#if defined (SUPPORT_SID_INTERFACE)
424 IMG_SID hCCBMemInfo;
425#else
261 IMG_HANDLE hCCBMemInfo; 426 IMG_HANDLE hCCBMemInfo;
427#endif
262 IMG_UINT32 ui32SharedCmdCCBOffset; 428 IMG_UINT32 ui32SharedCmdCCBOffset;
263 429
264 IMG_DEV_VIRTADDR sHW2DContextDevVAddr; 430 IMG_DEV_VIRTADDR sHW2DContextDevVAddr;
265 431
266 IMG_UINT32 ui32NumSrcSync; 432 IMG_UINT32 ui32NumSrcSync;
433#if defined (SUPPORT_SID_INTERFACE)
434 IMG_SID ahSrcSyncInfo[SGX_MAX_2D_SRC_SYNC_OPS];
435
436
437 IMG_SID hDstSyncInfo;
438
439
440 IMG_SID hTASyncInfo;
441
442
443 IMG_SID h3DSyncInfo;
444#else
267 IMG_HANDLE ahSrcSyncInfo[SGX_MAX_2D_SRC_SYNC_OPS]; 445 IMG_HANDLE ahSrcSyncInfo[SGX_MAX_2D_SRC_SYNC_OPS];
268 446
269 447
@@ -274,11 +452,13 @@ typedef struct _PVRSRV_2D_SGX_KICK_
274 452
275 453
276 IMG_HANDLE h3DSyncInfo; 454 IMG_HANDLE h3DSyncInfo;
455#endif
277 456
278 IMG_UINT32 ui32PDumpFlags; 457 IMG_UINT32 ui32PDumpFlags;
279#if defined(PDUMP) 458#if defined(PDUMP)
280 IMG_UINT32 ui32CCBDumpWOff; 459 IMG_UINT32 ui32CCBDumpWOff;
281#endif 460#endif
461 IMG_HANDLE hDevMemContext;
282} PVRSRV_2D_SGX_KICK, *PPVRSRV_2D_SGX_KICK; 462} PVRSRV_2D_SGX_KICK, *PPVRSRV_2D_SGX_KICK;
283#endif 463#endif
284#endif 464#endif
diff --git a/drivers/gpu/pvr/sgxmmu.h b/drivers/gpu/pvr/sgxmmu.h
index 4df8003361c..ed74f532c62 100644
--- a/drivers/gpu/pvr/sgxmmu.h
+++ b/drivers/gpu/pvr/sgxmmu.h
@@ -44,19 +44,12 @@
44#endif 44#endif
45#define SGX_MMU_PDE_VALID (0x00000001U) 45#define SGX_MMU_PDE_VALID (0x00000001U)
46#define SGX_MMU_PDE_PAGE_SIZE_4K (0x00000000U) 46#define SGX_MMU_PDE_PAGE_SIZE_4K (0x00000000U)
47#if defined(SGX_FEATURE_VARIABLE_MMU_PAGE_SIZE) 47#define SGX_MMU_PDE_PAGE_SIZE_16K (0x00000002U)
48 #define SGX_MMU_PDE_PAGE_SIZE_16K (0x00000002U) 48#define SGX_MMU_PDE_PAGE_SIZE_64K (0x00000004U)
49 #define SGX_MMU_PDE_PAGE_SIZE_64K (0x00000004U) 49#define SGX_MMU_PDE_PAGE_SIZE_256K (0x00000006U)
50 #define SGX_MMU_PDE_PAGE_SIZE_256K (0x00000006U) 50#define SGX_MMU_PDE_PAGE_SIZE_1M (0x00000008U)
51 #define SGX_MMU_PDE_PAGE_SIZE_1M (0x00000008U) 51#define SGX_MMU_PDE_PAGE_SIZE_4M (0x0000000AU)
52 #define SGX_MMU_PDE_PAGE_SIZE_4M (0x0000000AU) 52#define SGX_MMU_PDE_PAGE_SIZE_MASK (0x0000000EU)
53 #define SGX_MMU_PDE_PAGE_SIZE_MASK (0x0000000EU)
54#else
55 #define SGX_MMU_PDE_WRITEONLY (0x00000002U)
56 #define SGX_MMU_PDE_READONLY (0x00000004U)
57 #define SGX_MMU_PDE_CACHECONSISTENT (0x00000008U)
58 #define SGX_MMU_PDE_EDMPROTECT (0x00000010U)
59#endif
60 53
61#define SGX_MMU_PT_SHIFT (10) 54#define SGX_MMU_PT_SHIFT (10)
62#define SGX_MMU_PT_SIZE (1U<<SGX_MMU_PT_SHIFT) 55#define SGX_MMU_PT_SIZE (1U<<SGX_MMU_PT_SHIFT)
diff --git a/drivers/gpu/pvr/sgxmpdefs.h b/drivers/gpu/pvr/sgxmpdefs.h
index b1b67bf784b..ace1d43ceb2 100644
--- a/drivers/gpu/pvr/sgxmpdefs.h
+++ b/drivers/gpu/pvr/sgxmpdefs.h
@@ -24,8 +24,8 @@
24 * 24 *
25 ******************************************************************************/ 25 ******************************************************************************/
26 26
27#ifndef _SGXMPDEFS_KM_H_ 27#ifndef _SGXMPDEFS_H_
28#define _SGXMPDEFS_KM_H_ 28#define _SGXMPDEFS_H_
29 29
30#define EUR_CR_MASTER_BIF_CTRL 0x4C00 30#define EUR_CR_MASTER_BIF_CTRL 0x4C00
31#define EUR_CR_MASTER_BIF_CTRL_NOREORDER_MASK 0x00000001U 31#define EUR_CR_MASTER_BIF_CTRL_NOREORDER_MASK 0x00000001U
@@ -56,6 +56,16 @@
56#define EUR_CR_MASTER_BIF_CTRL_INVAL_ALL_MASK 0x00000008U 56#define EUR_CR_MASTER_BIF_CTRL_INVAL_ALL_MASK 0x00000008U
57#define EUR_CR_MASTER_BIF_CTRL_INVAL_ALL_SHIFT 3 57#define EUR_CR_MASTER_BIF_CTRL_INVAL_ALL_SHIFT 3
58#define EUR_CR_MASTER_BIF_CTRL_INVAL_ALL_SIGNED 0 58#define EUR_CR_MASTER_BIF_CTRL_INVAL_ALL_SIGNED 0
59#define EUR_CR_MASTER_BIF_MMU_CTRL 0x4CD0
60#define EUR_CR_MASTER_BIF_MMU_CTRL_PREFETCHING_ON_MASK 0x00000001U
61#define EUR_CR_MASTER_BIF_MMU_CTRL_PREFETCHING_ON_SHIFT 0
62#define EUR_CR_MASTER_BIF_MMU_CTRL_PREFETCHING_ON_SIGNED 0
63#define EUR_CR_MASTER_BIF_MMU_CTRL_ADDR_HASH_MODE_MASK 0x00000006U
64#define EUR_CR_MASTER_BIF_MMU_CTRL_ADDR_HASH_MODE_SHIFT 1
65#define EUR_CR_MASTER_BIF_MMU_CTRL_ADDR_HASH_MODE_SIGNED 0
66#define EUR_CR_MASTER_BIF_MMU_CTRL_ENABLE_DC_TLB_MASK 0x00000010U
67#define EUR_CR_MASTER_BIF_MMU_CTRL_ENABLE_DC_TLB_SHIFT 4
68#define EUR_CR_MASTER_BIF_MMU_CTRL_ENABLE_DC_TLB_SIGNED 0
59#define EUR_CR_MASTER_SLC_CTRL 0x4D00 69#define EUR_CR_MASTER_SLC_CTRL 0x4D00
60#define EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_MASK 0x00800000U 70#define EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_MASK 0x00800000U
61#define EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_SHIFT 23 71#define EUR_CR_MASTER_SLC_CTRL_DISABLE_REORDERING_SHIFT 23
@@ -202,6 +212,19 @@
202#define EUR_CR_MASTER_SLC_CTRL_FLUSH_ALL_MASK 0x00000010U 212#define EUR_CR_MASTER_SLC_CTRL_FLUSH_ALL_MASK 0x00000010U
203#define EUR_CR_MASTER_SLC_CTRL_FLUSH_ALL_SHIFT 4 213#define EUR_CR_MASTER_SLC_CTRL_FLUSH_ALL_SHIFT 4
204#define EUR_CR_MASTER_SLC_CTRL_FLUSH_ALL_SIGNED 0 214#define EUR_CR_MASTER_SLC_CTRL_FLUSH_ALL_SIGNED 0
215#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV 0x4D34
216#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_EVENT_MASK 0x00000080U
217#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_EVENT_SHIFT 7
218#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_EVENT_SIGNED 0
219#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_PIXEL_MASK 0x00000040U
220#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_PIXEL_SHIFT 6
221#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_PIXEL_SIGNED 0
222#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_VERTEX_MASK 0x00000020U
223#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_VERTEX_SHIFT 5
224#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_DM_VERTEX_SIGNED 0
225#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_ALL_MASK 0x00000010U
226#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_ALL_SHIFT 4
227#define EUR_CR_MASTER_SLC_CTRL_FLUSH_INV_ALL_SIGNED 0
205#define EUR_CR_MASTER_BREAKPOINT_READ 0x4F18 228#define EUR_CR_MASTER_BREAKPOINT_READ 0x4F18
206#define EUR_CR_MASTER_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U 229#define EUR_CR_MASTER_BREAKPOINT_READ_ADDRESS_MASK 0xFFFFFFF0U
207#define EUR_CR_MASTER_BREAKPOINT_READ_ADDRESS_SHIFT 4 230#define EUR_CR_MASTER_BREAKPOINT_READ_ADDRESS_SHIFT 4
@@ -214,6 +237,9 @@
214#define EUR_CR_MASTER_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0 237#define EUR_CR_MASTER_BREAKPOINT_TRAP_WRNOTIFY_SHIFT 0
215#define EUR_CR_MASTER_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0 238#define EUR_CR_MASTER_BREAKPOINT_TRAP_WRNOTIFY_SIGNED 0
216#define EUR_CR_MASTER_BREAKPOINT 0x4F20 239#define EUR_CR_MASTER_BREAKPOINT 0x4F20
240#define EUR_CR_MASTER_BREAKPOINT_ID_MASK 0x00000030U
241#define EUR_CR_MASTER_BREAKPOINT_ID_SHIFT 4
242#define EUR_CR_MASTER_BREAKPOINT_ID_SIGNED 0
217#define EUR_CR_MASTER_BREAKPOINT_UNTRAPPED_MASK 0x00000008U 243#define EUR_CR_MASTER_BREAKPOINT_UNTRAPPED_MASK 0x00000008U
218#define EUR_CR_MASTER_BREAKPOINT_UNTRAPPED_SHIFT 3 244#define EUR_CR_MASTER_BREAKPOINT_UNTRAPPED_SHIFT 3
219#define EUR_CR_MASTER_BREAKPOINT_UNTRAPPED_SIGNED 0 245#define EUR_CR_MASTER_BREAKPOINT_UNTRAPPED_SIGNED 0
diff --git a/drivers/gpu/pvr/syscommon.h b/drivers/gpu/pvr/syscommon.h
index 38b610738dd..46ac17375d1 100644
--- a/drivers/gpu/pvr/syscommon.h
+++ b/drivers/gpu/pvr/syscommon.h
@@ -57,6 +57,9 @@ typedef struct _SYS_DEVICE_ID_TAG
57 57
58#define SYS_MAX_LOCAL_DEVMEM_ARENAS 4 58#define SYS_MAX_LOCAL_DEVMEM_ARENAS 4
59 59
60typedef IMG_HANDLE (*PFN_HTIMER_CREATE) (IMG_VOID);
61typedef IMG_UINT32 (*PFN_HTIMER_GETUS) (IMG_HANDLE);
62typedef IMG_VOID (*PFN_HTIMER_DESTROY) (IMG_HANDLE);
60typedef struct _SYS_DATA_TAG_ 63typedef struct _SYS_DATA_TAG_
61{ 64{
62 IMG_UINT32 ui32NumDevices; 65 IMG_UINT32 ui32NumDevices;
@@ -81,14 +84,20 @@ typedef struct _SYS_DATA_TAG_
81 struct _DEVICE_COMMAND_DATA_ *apsDeviceCommandData[SYS_DEVICE_COUNT]; 84 struct _DEVICE_COMMAND_DATA_ *apsDeviceCommandData[SYS_DEVICE_COUNT];
82 85
83 86
84 IMG_BOOL bReProcessQueues;
85
86 RA_ARENA *apsLocalDevMemArena[SYS_MAX_LOCAL_DEVMEM_ARENAS]; 87 RA_ARENA *apsLocalDevMemArena[SYS_MAX_LOCAL_DEVMEM_ARENAS];
87 88
88 IMG_CHAR *pszVersionString; 89 IMG_CHAR *pszVersionString;
89 PVRSRV_EVENTOBJECT *psGlobalEventObject; 90#if defined (SUPPORT_SID_INTERFACE)
91 PVRSRV_EVENTOBJECT_KM *psGlobalEventObject;
92#else
93 PVRSRV_EVENTOBJECT *psGlobalEventObject;
94#endif
90 95
91 PVRSRV_MISC_INFO_CPUCACHEOP_TYPE ePendingCacheOpType; 96 PVRSRV_MISC_INFO_CPUCACHEOP_TYPE ePendingCacheOpType;
97
98 PFN_HTIMER_CREATE pfnHighResTimerCreate;
99 PFN_HTIMER_GETUS pfnHighResTimerGetus;
100 PFN_HTIMER_DESTROY pfnHighResTimerDestroy;
92} SYS_DATA; 101} SYS_DATA;
93 102
94 103
@@ -120,8 +129,8 @@ PVRSRV_ERROR SysDevicePostPowerState(IMG_UINT32 ui32DeviceIndex,
120 PVRSRV_DEV_POWER_STATE eCurrentPowerState); 129 PVRSRV_DEV_POWER_STATE eCurrentPowerState);
121 130
122#if defined(SYS_CUSTOM_POWERLOCK_WRAP) 131#if defined(SYS_CUSTOM_POWERLOCK_WRAP)
123PVRSRV_ERROR SysPowerLockWrap(SYS_DATA *psSysData); 132PVRSRV_ERROR SysPowerLockWrap(IMG_VOID);
124IMG_VOID SysPowerLockUnwrap(SYS_DATA *psSysData); 133IMG_VOID SysPowerLockUnwrap(IMG_VOID);
125#endif 134#endif
126 135
127PVRSRV_ERROR SysOEMFunction ( IMG_UINT32 ui32ID, 136PVRSRV_ERROR SysOEMFunction ( IMG_UINT32 ui32ID,
@@ -143,6 +152,7 @@ IMG_BOOL SysVerifySysPAddrToDevPAddr (PVRSRV_DEVICE_TYPE eDeviceType, IMG_SYS_PH
143 152
144extern SYS_DATA* gpsSysData; 153extern SYS_DATA* gpsSysData;
145 154
155
146#if !defined(USE_CODE) 156#if !defined(USE_CODE)
147 157
148#ifdef INLINE_IS_PRAGMA 158#ifdef INLINE_IS_PRAGMA
@@ -216,5 +226,37 @@ static inline IMG_VOID SysWriteHWReg(IMG_PVOID pvLinRegBaseAddr, IMG_UINT32 ui32
216} 226}
217#endif 227#endif
218 228
229#ifdef INLINE_IS_PRAGMA
230#pragma inline(SysHighResTimerCreate)
231#endif
232static INLINE IMG_HANDLE SysHighResTimerCreate(IMG_VOID)
233{
234 SYS_DATA *psSysData;
235
236 SysAcquireData(&psSysData);
237 return psSysData->pfnHighResTimerCreate();
238}
239
240#ifdef INLINE_IS_PRAGMA
241#pragma inline(SysHighResTimerGetus)
242#endif
243static INLINE IMG_UINT32 SysHighResTimerGetus(IMG_HANDLE hTimer)
244{
245 SYS_DATA *psSysData;
246
247 SysAcquireData(&psSysData);
248 return psSysData->pfnHighResTimerGetus(hTimer);
249}
250
251#ifdef INLINE_IS_PRAGMA
252#pragma inline(SysHighResTimerDestroy)
253#endif
254static INLINE IMG_VOID SysHighResTimerDestroy(IMG_HANDLE hTimer)
255{
256 SYS_DATA *psSysData;
257
258 SysAcquireData(&psSysData);
259 psSysData->pfnHighResTimerDestroy(hTimer);
260}
219#endif 261#endif
220 262
diff --git a/drivers/gpu/pvr/ttrace.h b/drivers/gpu/pvr/ttrace.h
new file mode 100644
index 00000000000..159cbcaeb52
--- /dev/null
+++ b/drivers/gpu/pvr/ttrace.h
@@ -0,0 +1,184 @@
1/**********************************************************************
2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 *
25 ******************************************************************************/
26
27#include "services_headers.h"
28#include "ttrace_common.h"
29#include "ttrace_tokens.h"
30
31#ifndef __TTRACE_H__
32#define __TTRACE_H__
33
34#if defined(TTRACE)
35
36 #define PVR_TTRACE(group, class, token) \
37 PVRSRVTimeTrace(group, class, token)
38 #define PVR_TTRACE_UI8(group, class, token, val) \
39 PVRSRVTimeTraceUI8(group, class, token, val)
40 #define PVR_TTRACE_UI16(group, class, token, val) \
41 PVRSRVTimeTraceUI16(group, class, token, val)
42 #define PVR_TTRACE_UI32(group, class, token, val) \
43 PVRSRVTimeTraceUI32(group, class, token, val)
44 #define PVR_TTRACE_UI64(group, class, token, val) \
45 PVRSRVTimeTraceUI64(group, class, token, val)
46 #define PVR_TTRACE_DEV_VIRTADDR(group, class, token, val) \
47 PVRSRVTimeTraceDevVirtAddr(group, class, token, val)
48 #define PVR_TTRACE_CPU_PHYADDR(group, class, token, val) \
49 PVRSRVTimeTraceCpuPhyAddr(group, class, token, val)
50 #define PVR_TTRACE_DEV_PHYADDR(group, class, token, val) \
51 PVRSRVTimeTraceDevPhysAddr(group, class, token, val)
52 #define PVR_TTRACE_SYS_PHYADDR(group, class, token, val) \
53 PVRSRVTimeTraceSysPhysAddr(group, class, token, val)
54 #define PVR_TTRACE_SYNC_OBJECT(group, token, syncobj, op) \
55 PVRSRVTimeTraceSyncObject(group, token, syncobj, op)
56
57IMG_IMPORT IMG_VOID IMG_CALLCONV PVRSRVTimeTraceArray(IMG_UINT32 ui32Group, IMG_UINT32 ui32Class,
58 IMG_UINT32 ui32Token, IMG_UINT32 ui32TypeSize,
59 IMG_UINT32 ui32Count, IMG_UINT8 *ui8Data);
60
61#ifdef INLINE_IS_PRAGMA
62#pragma inline(PVRSRVTimeTrace)
63#endif
64static INLINE IMG_VOID PVRSRVTimeTrace(IMG_UINT32 ui32Group, IMG_UINT32 ui32Class,
65 IMG_UINT32 ui32Token)
66{
67 PVRSRVTimeTraceArray(ui32Group, ui32Class, ui32Token, 0, 0, NULL);
68}
69
70#ifdef INLINE_IS_PRAGMA
71#pragma inline(PVRSRVTimeTraceUI8)
72#endif
73static INLINE IMG_VOID PVRSRVTimeTraceUI8(IMG_UINT32 ui32Group, IMG_UINT32 ui32Class,
74 IMG_UINT32 ui32Token, IMG_UINT8 ui8Value)
75{
76 PVRSRVTimeTraceArray(ui32Group, ui32Class, ui32Token, PVRSRV_TRACE_TYPE_UI8,
77 1, &ui8Value);
78}
79
80#ifdef INLINE_IS_PRAGMA
81#pragma inline(PVRSRVTimeTraceUI16)
82#endif
83static INLINE IMG_VOID PVRSRVTimeTraceUI16(IMG_UINT32 ui32Group, IMG_UINT32 ui32Class,
84 IMG_UINT32 ui32Token, IMG_UINT16 ui16Value)
85{
86 PVRSRVTimeTraceArray(ui32Group, ui32Class, ui32Token, PVRSRV_TRACE_TYPE_UI16,
87 1, (IMG_UINT8 *) &ui16Value);
88}
89
90#ifdef INLINE_IS_PRAGMA
91#pragma inline(PVRSRVTimeTraceUI32)
92#endif
93static INLINE IMG_VOID PVRSRVTimeTraceUI32(IMG_UINT32 ui32Group, IMG_UINT32 ui32Class,
94 IMG_UINT32 ui32Token, IMG_UINT32 ui32Value)
95{
96 PVRSRVTimeTraceArray(ui32Group, ui32Class, ui32Token, PVRSRV_TRACE_TYPE_UI32,
97 1, (IMG_UINT8 *) &ui32Value);
98}
99
100#ifdef INLINE_IS_PRAGMA
101#pragma inline(PVRSRVTimeTraceUI64)
102#endif
103static INLINE IMG_VOID PVRSRVTimeTraceUI64(IMG_UINT32 ui32Group, IMG_UINT32 ui32Class,
104 IMG_UINT32 ui32Token, IMG_UINT64 ui64Value)
105{
106 PVRSRVTimeTraceArray(ui32Group, ui32Class, ui32Token, PVRSRV_TRACE_TYPE_UI64,
107 1, (IMG_UINT8 *) &ui64Value);
108}
109
110#ifdef INLINE_IS_PRAGMA
111#pragma inline(PVRSRVTimeTraceDevVirtAddr)
112#endif
113static INLINE IMG_VOID PVRSRVTimeTraceDevVirtAddr(IMG_UINT32 ui32Group, IMG_UINT32 ui32Class,
114 IMG_UINT32 ui32Token, IMG_DEV_VIRTADDR psVAddr)
115{
116 PVRSRVTimeTraceArray(ui32Group, ui32Class, ui32Token, PVRSRV_TRACE_TYPE_UI32,
117 1, (IMG_UINT8 *) &psVAddr.uiAddr);
118}
119
120#ifdef INLINE_IS_PRAGMA
121#pragma inline(PVRSRVTimeTraceCpuPhyAddr)
122#endif
123static INLINE IMG_VOID PVRSRVTimeTraceCpuPhyAddr(IMG_UINT32 ui32Group, IMG_UINT32 ui32Class,
124 IMG_UINT32 ui32Token, IMG_CPU_PHYADDR psPAddr)
125{
126 PVRSRVTimeTraceArray(ui32Group, ui32Class, ui32Token, PVRSRV_TRACE_TYPE_UI32,
127 1, (IMG_UINT8 *) &psPAddr.uiAddr);
128}
129
130#ifdef INLINE_IS_PRAGMA
131#pragma inline(PVRSRVTimeTraceDevPhysAddr)
132#endif
133static INLINE IMG_VOID PVRSRVTimeTraceDevPhysAddr(IMG_UINT32 ui32Group, IMG_UINT32 ui32Class,
134 IMG_UINT32 ui32Token, IMG_DEV_PHYADDR psPAddr)
135{
136 PVRSRVTimeTraceArray(ui32Group, ui32Class, ui32Token, PVRSRV_TRACE_TYPE_UI32,
137 1, (IMG_UINT8 *) &psPAddr.uiAddr);
138}
139
140#ifdef INLINE_IS_PRAGMA
141#pragma inline(PVRSRVTimeTraceSysPhysAddr)
142#endif
143static INLINE IMG_VOID PVRSRVTimeTraceSysPhysAddr(IMG_UINT32 ui32Group, IMG_UINT32 ui32Class,
144 IMG_UINT32 ui32Token, IMG_SYS_PHYADDR psPAddr)
145{
146 PVRSRVTimeTraceArray(ui32Group, ui32Class, ui32Token, sizeof(psPAddr.uiAddr),
147 1, (IMG_UINT8 *) &psPAddr.uiAddr);
148}
149
150#else
151
152 #define PVR_TTRACE(group, class, token) \
153 ((void) 0)
154 #define PVR_TTRACE_UI8(group, class, token, val) \
155 ((void) 0)
156 #define PVR_TTRACE_UI16(group, class, token, val) \
157 ((void) 0)
158 #define PVR_TTRACE_UI32(group, class, token, val) \
159 ((void) 0)
160 #define PVR_TTRACE_UI64(group, class, token, val) \
161 ((void) 0)
162 #define PVR_TTRACE_DEV_VIRTADDR(group, class, token, val) \
163 ((void) 0)
164 #define PVR_TTRACE_CPU_PHYADDR(group, class, token, val) \
165 ((void) 0)
166 #define PVR_TTRACE_DEV_PHYADDR(group, class, token, val) \
167 ((void) 0)
168 #define PVR_TTRACE_SYS_PHYADDR(group, class, token, val) \
169 ((void) 0)
170 #define PVR_TTRACE_SYNC_OBJECT(group, token, syncobj, op) \
171 ((void) 0)
172
173#endif
174
175IMG_IMPORT PVRSRV_ERROR PVRSRVTimeTraceInit(IMG_VOID);
176IMG_IMPORT IMG_VOID PVRSRVTimeTraceDeinit(IMG_VOID);
177
178IMG_IMPORT IMG_VOID PVRSRVTimeTraceSyncObject(IMG_UINT32 ui32Group, IMG_UINT32 ui32Token,
179 PVRSRV_KERNEL_SYNC_INFO *psSync, IMG_UINT8 ui8SyncOp);
180IMG_IMPORT PVRSRV_ERROR PVRSRVTimeTraceBufferCreate(IMG_UINT32 ui32PID);
181IMG_IMPORT PVRSRV_ERROR PVRSRVTimeTraceBufferDestroy(IMG_UINT32 ui32PID);
182
183IMG_IMPORT IMG_VOID PVRSRVDumpTimeTraceBuffers(IMG_VOID);
184#endif
diff --git a/drivers/gpu/pvr/ttrace_common.h b/drivers/gpu/pvr/ttrace_common.h
new file mode 100644
index 00000000000..b7f884e0992
--- /dev/null
+++ b/drivers/gpu/pvr/ttrace_common.h
@@ -0,0 +1,81 @@
1/**********************************************************************
2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 *
25 ******************************************************************************/
26
27#include "img_types.h"
28
29#ifndef __TTRACE_COMMON_H__
30#define __TTRACE_COMMON_H__
31
32#define PVRSRV_TRACE_HEADER 0
33#define PVRSRV_TRACE_TIMESTAMP 1
34#define PVRSRV_TRACE_HOSTUID 2
35#define PVRSRV_TRACE_DATA_HEADER 3
36#define PVRSRV_TRACE_DATA_PAYLOAD 4
37
38#define PVRSRV_TRACE_ITEM_SIZE 16
39
40#define PVRSRV_TRACE_GROUP_MASK 0xff
41#define PVRSRV_TRACE_CLASS_MASK 0xff
42#define PVRSRV_TRACE_TOKEN_MASK 0xffff
43
44#define PVRSRV_TRACE_GROUP_SHIFT 24
45#define PVRSRV_TRACE_CLASS_SHIFT 16
46#define PVRSRV_TRACE_TOKEN_SHIFT 0
47
48#define PVRSRV_TRACE_SIZE_MASK 0xffff
49#define PVRSRV_TRACE_TYPE_MASK 0xf
50#define PVRSRV_TRACE_COUNT_MASK 0xfff
51
52#define PVRSRV_TRACE_SIZE_SHIFT 16
53#define PVRSRV_TRACE_TYPE_SHIFT 12
54#define PVRSRV_TRACE_COUNT_SHIFT 0
55
56
57#define WRITE_HEADER(n,m) \
58 ((m & PVRSRV_TRACE_##n##_MASK) << PVRSRV_TRACE_##n##_SHIFT)
59
60#define READ_HEADER(n,m) \
61 ((m & (PVRSRV_TRACE_##n##_MASK << PVRSRV_TRACE_##n##_SHIFT)) >> PVRSRV_TRACE_##n##_SHIFT)
62
63#define TIME_TRACE_BUFFER_SIZE 4096
64
65#define PVRSRV_TRACE_TYPE_UI8 0
66#define PVRSRV_TRACE_TYPE_UI16 1
67#define PVRSRV_TRACE_TYPE_UI32 2
68#define PVRSRV_TRACE_TYPE_UI64 3
69
70#define PVRSRV_TRACE_TYPE_SYNC 15
71 #define PVRSRV_TRACE_SYNC_UID 0
72 #define PVRSRV_TRACE_SYNC_WOP 1
73 #define PVRSRV_TRACE_SYNC_WOC 2
74 #define PVRSRV_TRACE_SYNC_ROP 3
75 #define PVRSRV_TRACE_SYNC_ROC 4
76 #define PVRSRV_TRACE_SYNC_WO_DEV_VADDR 5
77 #define PVRSRV_TRACE_SYNC_RO_DEV_VADDR 6
78 #define PVRSRV_TRACE_SYNC_OP 7
79#define PVRSRV_TRACE_TYPE_SYNC_SIZE ((PVRSRV_TRACE_SYNC_OP + 1) * sizeof(IMG_UINT32))
80
81#endif
diff --git a/drivers/gpu/pvr/ttrace_tokens.h b/drivers/gpu/pvr/ttrace_tokens.h
new file mode 100644
index 00000000000..530ce3e380e
--- /dev/null
+++ b/drivers/gpu/pvr/ttrace_tokens.h
@@ -0,0 +1,84 @@
1/**********************************************************************
2 *
3 * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful but, except
10 * as otherwise stated in writing, without any warranty; without even the
11 * implied warranty of merchantability or fitness for a particular purpose.
12 * See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23 * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24 *
25 ******************************************************************************/
26
27#ifndef __TTRACE_TOKENS_H__
28#define __TTRACE_TOKENS_H__
29
30#define PVRSRV_TRACE_GROUP_KICK 0
31#define PVRSRV_TRACE_GROUP_TRANSFER 1
32#define PVRSRV_TRACE_GROUP_QUEUE 2
33#define PVRSRV_TRACE_GROUP_POWER 3
34#define PVRSRV_TRACE_GROUP_MKSYNC 4
35
36#define PVRSRV_TRACE_GROUP_PADDING 255
37
38#define PVRSRV_TRACE_CLASS_FUNCTION_ENTER 0
39#define PVRSRV_TRACE_CLASS_FUNCTION_EXIT 1
40#define PVRSRV_TRACE_CLASS_SYNC 2
41#define PVRSRV_TRACE_CLASS_CCB 3
42#define PVRSRV_TRACE_CLASS_CMD_START 4
43#define PVRSRV_TRACE_CLASS_CMD_END 5
44#define PVRSRV_TRACE_CLASS_CMD_COMP_START 6
45#define PVRSRV_TRACE_CLASS_CMD_COMP_END 7
46
47#define PVRSRV_TRACE_CLASS_NONE 255
48
49#define PVRSRV_SYNCOP_SAMPLE 0
50#define PVRSRV_SYNCOP_COMPLETE 1
51#define PVRSRV_SYNCOP_DUMP 2
52
53#define KICK_TOKEN_DOKICK 0
54#define KICK_TOKEN_CCB_OFFSET 1
55#define KICK_TOKEN_TA3D_SYNC 2
56#define KICK_TOKEN_TA_SYNC 3
57#define KICK_TOKEN_3D_SYNC 4
58#define KICK_TOKEN_SRC_SYNC 5
59#define KICK_TOKEN_DST_SYNC 6
60
61#define TRANSFER_TOKEN_SUBMIT 0
62#define TRANSFER_TOKEN_TA_SYNC 1
63#define TRANSFER_TOKEN_3D_SYNC 2
64#define TRANSFER_TOKEN_SRC_SYNC 3
65#define TRANSFER_TOKEN_DST_SYNC 4
66#define TRANSFER_TOKEN_CCB_OFFSET 5
67
68#define QUEUE_TOKEN_GET_SPACE 0
69#define QUEUE_TOKEN_INSERTKM 1
70#define QUEUE_TOKEN_SUBMITKM 2
71#define QUEUE_TOKEN_PROCESS_COMMAND 3
72#define QUEUE_TOKEN_PROCESS_QUEUES 4
73#define QUEUE_TOKEN_COMMAND_COMPLETE 5
74#define QUEUE_TOKEN_UPDATE_DST 6
75#define QUEUE_TOKEN_UPDATE_SRC 7
76#define QUEUE_TOKEN_SRC_SYNC 8
77#define QUEUE_TOKEN_DST_SYNC 9
78#define QUEUE_TOKEN_COMMAND_TYPE 10
79
80#define MKSYNC_TOKEN_KERNEL_CCB_OFFSET 0
81#define MKSYNC_TOKEN_CORE_CLK 1
82#define MKSYNC_TOKEN_UKERNEL_CLK 2
83
84#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 01:14:40 -0400