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authorChristopher Kenna <cjk@cs.unc.edu>2012-09-28 13:46:28 -0400
committerChristopher Kenna <cjk@cs.unc.edu>2012-09-28 14:50:15 -0400
commitdaa22703f14c007e93b464c45fa60019a36f546d (patch)
treea1a130b6e128dc9d57c35c026977e1b4953105e1 /arch/arm/plat-samsung/include
parent5aa287dcf1b5879aa0150b0511833c52885f5b4c (diff)
Apply k4412 kernel from HardKernel for ODROID-X.
Diffstat (limited to 'arch/arm/plat-samsung/include')
-rw-r--r--arch/arm/plat-samsung/include/plat/audio.h6
-rw-r--r--arch/arm/plat-samsung/include/plat/backlight.h26
-rw-r--r--arch/arm/plat-samsung/include/plat/clock.h12
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h130
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h94
-rw-r--r--arch/arm/plat-samsung/include/plat/dma.h18
-rw-r--r--arch/arm/plat-samsung/include/plat/fb-core.h21
-rw-r--r--arch/arm/plat-samsung/include/plat/fb.h60
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg.h61
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-core.h3
-rw-r--r--arch/arm/plat-samsung/include/plat/iic.h3
-rw-r--r--arch/arm/plat-samsung/include/plat/map-base.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/mshci.h163
-rw-r--r--arch/arm/plat-samsung/include/plat/pd.h20
-rw-r--r--arch/arm/plat-samsung/include/plat/pm.h5
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-adc.h6
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-fb-v4.h11
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-fb.h82
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-otg.h259
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd-phy.h75
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h22
-rw-r--r--arch/arm/plat-samsung/include/plat/s3c64xx-spi.h1
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h71
-rw-r--r--arch/arm/plat-samsung/include/plat/ts.h6
-rw-r--r--arch/arm/plat-samsung/include/plat/tv-core.h37
-rw-r--r--arch/arm/plat-samsung/include/plat/watchdog-reset.h12
26 files changed, 1157 insertions, 49 deletions
diff --git a/arch/arm/plat-samsung/include/plat/audio.h b/arch/arm/plat-samsung/include/plat/audio.h
index a0826ed2f9f..bfee6448fcc 100644
--- a/arch/arm/plat-samsung/include/plat/audio.h
+++ b/arch/arm/plat-samsung/include/plat/audio.h
@@ -36,6 +36,10 @@ struct samsung_i2s {
36 */ 36 */
37#define QUIRK_NO_MUXPSR (1 << 2) 37#define QUIRK_NO_MUXPSR (1 << 2)
38#define QUIRK_NEED_RSTCLR (1 << 3) 38#define QUIRK_NEED_RSTCLR (1 << 3)
39/* If the idma will be enabled */
40#define QUIRK_ENABLED_IDMA (1 << 4)
41/* If the srp will be enabled */
42#define QUIRK_ENABLED_SRP (1 << 5)
39 /* Quirks of the I2S controller */ 43 /* Quirks of the I2S controller */
40 u32 quirks; 44 u32 quirks;
41 45
@@ -56,3 +60,5 @@ struct s3c_audio_pdata {
56 struct samsung_i2s i2s; 60 struct samsung_i2s i2s;
57 } type; 61 } type;
58}; 62};
63
64extern void __init exynos4_i2sv3_setup_resource(void);
diff --git a/arch/arm/plat-samsung/include/plat/backlight.h b/arch/arm/plat-samsung/include/plat/backlight.h
new file mode 100644
index 00000000000..ad530c78fe8
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/backlight.h
@@ -0,0 +1,26 @@
1/* linux/arch/arm/plat-samsung/include/plat/backlight.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_PLAT_BACKLIGHT_H
12#define __ASM_PLAT_BACKLIGHT_H __FILE__
13
14/* samsung_bl_gpio_info - GPIO info for PWM Backlight control
15 * @no: GPIO number for PWM timer out
16 * @func: Special function of GPIO line for PWM timer
17 */
18struct samsung_bl_gpio_info {
19 int no;
20 int func;
21};
22
23extern void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
24 struct platform_pwm_backlight_data *bl_data);
25
26#endif /* __ASM_PLAT_BACKLIGHT_H */
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 983c578b827..76198a77098 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -9,7 +9,11 @@
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10*/ 10*/
11 11
12#ifndef __ASM_PLAT_CLOCK_H
13#define __ASM_PLAT_CLOCK_H __FILE__
14
12#include <linux/spinlock.h> 15#include <linux/spinlock.h>
16#include <linux/clkdev.h>
13 17
14struct clk; 18struct clk;
15 19
@@ -40,6 +44,7 @@ struct clk {
40 struct module *owner; 44 struct module *owner;
41 struct clk *parent; 45 struct clk *parent;
42 const char *name; 46 const char *name;
47 const char *devname;
43 int id; 48 int id;
44 int usage; 49 int usage;
45 unsigned long rate; 50 unsigned long rate;
@@ -47,6 +52,7 @@ struct clk {
47 52
48 struct clk_ops *ops; 53 struct clk_ops *ops;
49 int (*enable)(struct clk *, int enable); 54 int (*enable)(struct clk *, int enable);
55 struct clk_lookup lookup;
50#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) 56#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
51 struct dentry *dent; /* For visible tree hierarchy */ 57 struct dentry *dent; /* For visible tree hierarchy */
52#endif 58#endif
@@ -78,6 +84,7 @@ extern struct clk clk_h2;
78extern struct clk clk_27m; 84extern struct clk clk_27m;
79extern struct clk clk_48m; 85extern struct clk clk_48m;
80extern struct clk clk_xusbxti; 86extern struct clk clk_xusbxti;
87extern struct clk clk_xxti;
81 88
82extern int clk_default_setrate(struct clk *clk, unsigned long rate); 89extern int clk_default_setrate(struct clk *clk, unsigned long rate);
83extern struct clk_ops clk_ops_def_setrate; 90extern struct clk_ops clk_ops_def_setrate;
@@ -118,3 +125,8 @@ extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
118 125
119extern void s3c_pwmclk_init(void); 126extern void s3c_pwmclk_init(void);
120 127
128/* Global watchdog clock used by arch_wtd_reset() callback */
129
130extern struct clk *s3c2410_wdtclk;
131
132#endif /* __ASM_PLAT_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index c0a5741b23e..b8c6f4ffbde 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -1,9 +1,12 @@
1/* linux/arch/arm/plat-samsung/include/plat/cpu.h 1/* linux/arch/arm/plat-samsung/include/plat/cpu.h
2 * 2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
3 * Copyright (c) 2004-2005 Simtec Electronics 6 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 7 * Ben Dooks <ben@simtec.co.uk>
5 * 8 *
6 * Header file for S3C24XX CPU support 9 * Header file for Samsung CPU support
7 * 10 *
8 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 12 * it under the terms of the GNU General Public License version 2 as
@@ -15,6 +18,124 @@
15#ifndef __SAMSUNG_PLAT_CPU_H 18#ifndef __SAMSUNG_PLAT_CPU_H
16#define __SAMSUNG_PLAT_CPU_H 19#define __SAMSUNG_PLAT_CPU_H
17 20
21extern unsigned long samsung_cpu_id;
22
23#define S3C24XX_CPU_ID 0x32400000
24#define S3C24XX_CPU_MASK 0xFFF00000
25
26#define S3C6400_CPU_ID 0x36400000
27#define S3C6410_CPU_ID 0x36410000
28#define S3C64XX_CPU_ID (S3C6400_CPU_ID & S3C6410_CPU_ID)
29#define S3C64XX_CPU_MASK 0x1FF40000
30
31#define S5P6440_CPU_ID 0x56440000
32#define S5P6450_CPU_ID 0x36450000
33#define S5P64XX_CPU_MASK 0x1FF40000
34
35#define S5PC100_CPU_ID 0x43100000
36#define S5PC100_CPU_MASK 0xFFFFF000
37
38#define S5PV210_CPU_ID 0x43110000
39#define S5PV210_CPU_MASK 0xFFFFF000
40
41#define EXYNOS4210_CPU_ID 0x43210000
42#define EXYNOS4212_CPU_ID 0x43220000
43#define EXYNOS4412_CPU_ID 0xE4412200
44#define EXYNOS5250_CPU_ID 0x43520000
45#define EXYNOS_CPU_MASK 0xFFFE0000
46
47#define IS_SAMSUNG_CPU(name, id, mask) \
48static inline int is_samsung_##name(void) \
49{ \
50 return ((samsung_cpu_id & mask) == (id & mask)); \
51}
52
53IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
54IS_SAMSUNG_CPU(s3c64xx, S3C64XX_CPU_ID, S3C64XX_CPU_MASK)
55IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
56IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
57IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
58IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
59IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS_CPU_MASK)
60IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS_CPU_MASK)
61IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS_CPU_MASK)
62IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_CPU_ID, EXYNOS_CPU_MASK)
63
64#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
65 defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
66 defined(CONFIG_CPU_S3C2442) || defined(CONFIG_CPU_S3C244X) || \
67 defined(CONFIG_CPU_S3C2443)
68# define soc_is_s3c24xx() is_samsung_s3c24xx()
69#else
70# define soc_is_s3c24xx() 0
71#endif
72
73#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
74# define soc_is_s3c64xx() is_samsung_s3c64xx()
75#else
76# define soc_is_s3c64xx() 0
77#endif
78
79#if defined(CONFIG_CPU_S5P6440)
80# define soc_is_s5p6440() is_samsung_s5p6440()
81#else
82# define soc_is_s5p6440() 0
83#endif
84
85#if defined(CONFIG_CPU_S5P6450)
86# define soc_is_s5p6450() is_samsung_s5p6450()
87#else
88# define soc_is_s5p6450() 0
89#endif
90
91#if defined(CONFIG_CPU_S5PC100)
92# define soc_is_s5pc100() is_samsung_s5pc100()
93#else
94# define soc_is_s5pc100() 0
95#endif
96
97#if defined(CONFIG_CPU_S5PV210)
98# define soc_is_s5pv210() is_samsung_s5pv210()
99#else
100# define soc_is_s5pv210() 0
101#endif
102
103#if defined(CONFIG_CPU_EXYNOS4210)
104# define soc_is_exynos4210() is_samsung_exynos4210()
105#else
106# define soc_is_exynos4210() 0
107#endif
108
109#define EXYNOS4210_REV_0 (0x0)
110#define EXYNOS4210_REV_1_0 (0x10)
111#define EXYNOS4210_REV_1_1 (0x11)
112
113#if defined(CONFIG_CPU_EXYNOS4212)
114# define soc_is_exynos4212() is_samsung_exynos4212()
115#else
116# define soc_is_exynos4212() 0
117#endif
118
119#define EXYNOS4212_REV_0 (0x0)
120#define EXYNOS4212_REV_1_0 (0x10)
121
122#if defined(CONFIG_CPU_EXYNOS4412)
123# define soc_is_exynos4412() is_samsung_exynos4412()
124#else
125# define soc_is_exynos4412() 0
126#endif
127
128#define EXYNOS4412_REV_0 (0x0)
129#define EXYNOS4412_REV_0_1 (0x01)
130#define EXYNOS4412_REV_1_0 (0x10)
131#define EXYNOS4412_REV_1_1 (0x11)
132
133#if defined(CONFIG_CPU_EXYNOS5250)
134# define soc_is_exynos5250() is_samsung_exynos5250()
135#else
136# define soc_is_exynos5250() 0
137#endif
138
18#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE } 139#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
19 140
20#ifndef MHZ 141#ifndef MHZ
@@ -55,6 +176,12 @@ extern void s3c64xx_init_io(struct map_desc *mach_desc, int size);
55extern void s5p_init_io(struct map_desc *mach_desc, 176extern void s5p_init_io(struct map_desc *mach_desc,
56 int size, void __iomem *cpuid_addr); 177 int size, void __iomem *cpuid_addr);
57 178
179extern void s3c24xx_init_cpu(void);
180extern void s3c64xx_init_cpu(void);
181extern void s5p_init_cpu(void __iomem *cpuid_addr);
182
183extern unsigned int samsung_rev(void);
184
58extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no); 185extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
59 186
60extern void s3c24xx_init_clocks(int xtal); 187extern void s3c24xx_init_clocks(int xtal);
@@ -88,6 +215,7 @@ extern struct sysdev_class s3c64xx_sysclass;
88extern struct sysdev_class s5p64x0_sysclass; 215extern struct sysdev_class s5p64x0_sysclass;
89extern struct sysdev_class s5pv210_sysclass; 216extern struct sysdev_class s5pv210_sysclass;
90extern struct sysdev_class exynos4_sysclass; 217extern struct sysdev_class exynos4_sysclass;
218extern struct sysdev_class exynos5_sysclass;
91 219
92extern void (*s5pc1xx_idle)(void); 220extern void (*s5pc1xx_idle)(void);
93 221
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index e3b31c26ac3..bba92774b93 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -17,6 +17,7 @@
17#define __PLAT_DEVS_H __FILE__ 17#define __PLAT_DEVS_H __FILE__
18 18
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/platform_data/exynos_usb3_drd.h>
20 21
21struct s3c24xx_uart_resources { 22struct s3c24xx_uart_resources {
22 struct resource *resources; 23 struct resource *resources;
@@ -40,6 +41,7 @@ extern struct platform_device s3c64xx_device_spi0;
40extern struct platform_device s3c64xx_device_spi1; 41extern struct platform_device s3c64xx_device_spi1;
41 42
42extern struct platform_device samsung_asoc_dma; 43extern struct platform_device samsung_asoc_dma;
44extern struct platform_device samsung_asoc_idma;
43 45
44extern struct platform_device s3c64xx_device_pcm0; 46extern struct platform_device s3c64xx_device_pcm0;
45extern struct platform_device s3c64xx_device_pcm1; 47extern struct platform_device s3c64xx_device_pcm1;
@@ -47,8 +49,11 @@ extern struct platform_device s3c64xx_device_pcm1;
47extern struct platform_device s3c64xx_device_ac97; 49extern struct platform_device s3c64xx_device_ac97;
48 50
49extern struct platform_device s3c_device_ts; 51extern struct platform_device s3c_device_ts;
52extern struct platform_device s3c_device_ts1;
50 53
51extern struct platform_device s3c_device_fb; 54extern struct platform_device s3c_device_fb;
55extern struct platform_device s5p_device_fimd0;
56extern struct platform_device s5p_device_fimd1;
52extern struct platform_device s3c_device_ohci; 57extern struct platform_device s3c_device_ohci;
53extern struct platform_device s3c_device_lcd; 58extern struct platform_device s3c_device_lcd;
54extern struct platform_device s3c_device_wdt; 59extern struct platform_device s3c_device_wdt;
@@ -60,6 +65,7 @@ extern struct platform_device s3c_device_i2c4;
60extern struct platform_device s3c_device_i2c5; 65extern struct platform_device s3c_device_i2c5;
61extern struct platform_device s3c_device_i2c6; 66extern struct platform_device s3c_device_i2c6;
62extern struct platform_device s3c_device_i2c7; 67extern struct platform_device s3c_device_i2c7;
68extern struct platform_device s5p_device_i2c_hdmiphy;
63extern struct platform_device s3c_device_rtc; 69extern struct platform_device s3c_device_rtc;
64extern struct platform_device s3c_device_adc; 70extern struct platform_device s3c_device_adc;
65extern struct platform_device s3c_device_sdi; 71extern struct platform_device s3c_device_sdi;
@@ -69,6 +75,7 @@ extern struct platform_device s3c_device_hsmmc0;
69extern struct platform_device s3c_device_hsmmc1; 75extern struct platform_device s3c_device_hsmmc1;
70extern struct platform_device s3c_device_hsmmc2; 76extern struct platform_device s3c_device_hsmmc2;
71extern struct platform_device s3c_device_hsmmc3; 77extern struct platform_device s3c_device_hsmmc3;
78extern struct platform_device s3c_device_mshci;
72extern struct platform_device s3c_device_cfcon; 79extern struct platform_device s3c_device_cfcon;
73 80
74extern struct platform_device s3c_device_spi0; 81extern struct platform_device s3c_device_spi0;
@@ -81,6 +88,9 @@ extern struct platform_device s5pv210_device_spi0;
81extern struct platform_device s5pv210_device_spi1; 88extern struct platform_device s5pv210_device_spi1;
82extern struct platform_device s5p64x0_device_spi0; 89extern struct platform_device s5p64x0_device_spi0;
83extern struct platform_device s5p64x0_device_spi1; 90extern struct platform_device s5p64x0_device_spi1;
91extern struct platform_device exynos_device_spi0;
92extern struct platform_device exynos_device_spi1;
93extern struct platform_device exynos_device_spi2;
84 94
85extern struct platform_device s3c_device_hwmon; 95extern struct platform_device s3c_device_hwmon;
86 96
@@ -92,6 +102,13 @@ extern struct platform_device s5p_device_onenand;
92extern struct platform_device s3c_device_usbgadget; 102extern struct platform_device s3c_device_usbgadget;
93extern struct platform_device s3c_device_usb_hsudc; 103extern struct platform_device s3c_device_usb_hsudc;
94extern struct platform_device s3c_device_usb_hsotg; 104extern struct platform_device s3c_device_usb_hsotg;
105extern struct platform_device s3c_device_usb_hsudc;
106extern struct platform_device s3c_device_android_usb;
107extern struct platform_device s3c_device_usb_mass_storage;
108#ifdef CONFIG_USB_ANDROID_RNDIS
109extern struct platform_device s3c_device_rndis;
110#endif
111extern struct platform_device s5p_device_usbswitch;
95 112
96extern struct platform_device s5pv210_device_ac97; 113extern struct platform_device s5pv210_device_ac97;
97extern struct platform_device s5pv210_device_pcm0; 114extern struct platform_device s5pv210_device_pcm0;
@@ -101,17 +118,39 @@ extern struct platform_device s5pv210_device_iis0;
101extern struct platform_device s5pv210_device_iis1; 118extern struct platform_device s5pv210_device_iis1;
102extern struct platform_device s5pv210_device_iis2; 119extern struct platform_device s5pv210_device_iis2;
103extern struct platform_device s5pv210_device_spdif; 120extern struct platform_device s5pv210_device_spdif;
104 121extern struct platform_device s5pv210_device_cpufreq;
105extern struct platform_device exynos4_device_ac97; 122extern struct platform_device s5pv210_device_pdma0;
106extern struct platform_device exynos4_device_pcm0; 123extern struct platform_device s5pv210_device_pdma1;
107extern struct platform_device exynos4_device_pcm1; 124extern struct platform_device s5pv210_device_mdma;
108extern struct platform_device exynos4_device_pcm2; 125
109extern struct platform_device exynos4_device_i2s0; 126extern struct platform_device exynos_device_ac97;
110extern struct platform_device exynos4_device_i2s1; 127extern struct platform_device exynos_device_pcm0;
111extern struct platform_device exynos4_device_i2s2; 128extern struct platform_device exynos_device_pcm1;
112extern struct platform_device exynos4_device_spdif; 129extern struct platform_device exynos_device_pcm2;
130extern struct platform_device exynos_device_i2s0;
131extern struct platform_device exynos_device_i2s1;
132extern struct platform_device exynos_device_i2s2;
133extern struct platform_device exynos_device_spdif;
134extern struct platform_device exynos_device_srp;
113extern struct platform_device exynos4_device_pd[]; 135extern struct platform_device exynos4_device_pd[];
114extern struct platform_device exynos4_device_ahci; 136extern struct platform_device exynos4_device_ahci;
137extern struct platform_device exynos4_device_pdma0;
138extern struct platform_device exynos4_device_pdma1;
139extern struct platform_device exynos4_device_mdma;
140extern struct platform_device exynos_device_dwmci;
141extern struct platform_device exynos_device_flite0;
142extern struct platform_device exynos_device_flite1;
143extern struct platform_device exynos4_device_fimc_is;
144extern struct platform_device exynos5_device_fimc_is;
145extern struct platform_device exynos5_device_pd[];
146extern struct platform_device exynos5_device_gsc0;
147extern struct platform_device exynos5_device_gsc1;
148extern struct platform_device exynos5_device_gsc2;
149extern struct platform_device exynos5_device_gsc3;
150extern struct platform_device exynos5_device_ahci;
151extern struct platform_device exynos_device_c2c;
152extern struct platform_device exynos_device_ss_udc;
153extern struct platform_device exynos_device_xhci;
115 154
116extern struct platform_device s5p6440_device_pcm; 155extern struct platform_device s5p6440_device_pcm;
117extern struct platform_device s5p6440_device_iis; 156extern struct platform_device s5p6440_device_iis;
@@ -130,18 +169,46 @@ extern struct platform_device s5pc100_device_iis2;
130extern struct platform_device s5pc100_device_spdif; 169extern struct platform_device s5pc100_device_spdif;
131 170
132extern struct platform_device samsung_device_keypad; 171extern struct platform_device samsung_device_keypad;
133 172#ifndef CONFIG_VIDEO_FIMC
134extern struct platform_device s5p_device_fimc0; 173extern struct platform_device s5p_device_fimc0;
135extern struct platform_device s5p_device_fimc1; 174extern struct platform_device s5p_device_fimc1;
136extern struct platform_device s5p_device_fimc2; 175extern struct platform_device s5p_device_fimc2;
137extern struct platform_device s5p_device_fimc3; 176extern struct platform_device s5p_device_fimc3;
138 177#else
178extern struct platform_device s3c_device_fimc0;
179extern struct platform_device s3c_device_fimc1;
180extern struct platform_device s3c_device_fimc2;
181extern struct platform_device s3c_device_fimc3;
182#endif
183#ifndef CONFIG_VIDEO_FIMC_MIPI
139extern struct platform_device s5p_device_mipi_csis0; 184extern struct platform_device s5p_device_mipi_csis0;
140extern struct platform_device s5p_device_mipi_csis1; 185extern struct platform_device s5p_device_mipi_csis1;
186#else
187extern struct platform_device s3c_device_csis0;
188extern struct platform_device s3c_device_csis1;
189#endif
190extern struct platform_device s5p_device_dp;
191
192extern struct platform_device s5p_device_jpeg;
193extern struct platform_device s5p_device_tvout;
194extern struct platform_device s5p_device_cec;
195extern struct platform_device s5p_device_hpd;
196extern struct platform_device s5p_device_ace;
197extern struct platform_device s5p_device_fimg2d;
198extern struct platform_device exynos_device_rotator;
141 199
142extern struct platform_device s5p_device_ehci; 200extern struct platform_device s5p_device_ehci;
201extern struct platform_device s5p_device_ohci;
202
203extern struct platform_device exynos_device_sysmmu[];
143 204
144extern struct platform_device exynos4_device_sysmmu; 205extern struct platform_device s5p_device_mfc;
206extern struct platform_device s5p_device_mipi_dsim;
207extern struct platform_device s5p_device_dsim;
208
209extern struct platform_device s5p_device_hdmi;
210extern struct platform_device s5p_device_mixer;
211extern struct platform_device s5p_device_sdo;
145 212
146/* s3c2440 specific devices */ 213/* s3c2440 specific devices */
147 214
@@ -152,6 +219,9 @@ extern struct platform_device s3c_device_ac97;
152 219
153#endif 220#endif
154 221
222extern void exynos_ss_udc_set_platdata(struct exynos_usb3_drd_pdata *pd);
223extern void exynos_xhci_set_platdata(struct exynos_usb3_drd_pdata *pd);
224
155/** 225/**
156 * s3c_set_platdata() - helper for setting platform data 226 * s3c_set_platdata() - helper for setting platform data
157 * @pd: The default platform data for this device. 227 * @pd: The default platform data for this device.
diff --git a/arch/arm/plat-samsung/include/plat/dma.h b/arch/arm/plat-samsung/include/plat/dma.h
index 8c273b7a6f5..816d50581b7 100644
--- a/arch/arm/plat-samsung/include/plat/dma.h
+++ b/arch/arm/plat-samsung/include/plat/dma.h
@@ -18,7 +18,9 @@ enum s3c2410_dma_buffresult {
18 18
19enum s3c2410_dmasrc { 19enum s3c2410_dmasrc {
20 S3C2410_DMASRC_HW, /* source is memory */ 20 S3C2410_DMASRC_HW, /* source is memory */
21 S3C2410_DMASRC_MEM /* source is hardware */ 21 S3C2410_DMASRC_MEM, /* source is hardware */
22 S3C_DMA_MEM2MEM,
23 S3C_DMA_MEM2MEM_SET,
22}; 24};
23 25
24/* enum s3c2410_chan_op 26/* enum s3c2410_chan_op
@@ -96,8 +98,18 @@ extern int s3c2410_dma_free(enum dma_ch channel, struct s3c2410_dma_client *);
96 * drained before the buffer is given to the DMA system. 98 * drained before the buffer is given to the DMA system.
97*/ 99*/
98 100
99extern int s3c2410_dma_enqueue(enum dma_ch channel, void *id, 101#define s3c2410_dma_enqueue(id, token, addr, size) \
100 dma_addr_t data, int size); 102 s3c2410_dma_enqueue_ring(id, token, addr, size, 0)
103
104/* s3c2410_dma_enqueue_ring
105 *
106 * place the given buffer onto the queue of operations for the channel.
107 * The buffer must be allocated from dma coherent memory, or the Dcache/WB
108 * drained before the buffer is given to the DMA system.
109*/
110
111extern int s3c2410_dma_enqueue_ring(enum dma_ch channel, void *id,
112 dma_addr_t data, int size, int numofblock);
101 113
102/* s3c2410_dma_config 114/* s3c2410_dma_config
103 * 115 *
diff --git a/arch/arm/plat-samsung/include/plat/fb-core.h b/arch/arm/plat-samsung/include/plat/fb-core.h
index bca383efcf6..43358405d58 100644
--- a/arch/arm/plat-samsung/include/plat/fb-core.h
+++ b/arch/arm/plat-samsung/include/plat/fb-core.h
@@ -26,4 +26,25 @@ static inline void s3c_fb_setname(char *name)
26#endif 26#endif
27} 27}
28 28
29/* Re-define device name depending on support. */
30static inline void s5p_fb_setname(int id, char *name)
31{
32 switch (id) {
33#ifdef CONFIG_S5P_DEV_FIMD0
34 case 0:
35 s5p_device_fimd0.name = name;
36 break;
37#endif
38
39#ifdef CONFIG_S5P_DEV_FIMD1
40 case 1:
41 s5p_device_fimd1.name = name;
42 break;
43#endif
44 default:
45 printk(KERN_ERR "%s: invalid device id(%d)\n", __func__, id);
46 break;
47 }
48}
49
29#endif /* __ASM_PLAT_FB_CORE_H */ 50#endif /* __ASM_PLAT_FB_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index cb3ca3adc68..c58a03f35cd 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -15,6 +15,8 @@
15#ifndef __PLAT_S3C_FB_H 15#ifndef __PLAT_S3C_FB_H
16#define __PLAT_S3C_FB_H __FILE__ 16#define __PLAT_S3C_FB_H __FILE__
17 17
18#include <plat/gpio-cfg.h>
19
18/* S3C_FB_MAX_WIN 20/* S3C_FB_MAX_WIN
19 * Set to the maximum number of windows that any of the supported hardware 21 * Set to the maximum number of windows that any of the supported hardware
20 * can use. Since the platform data uses this for an array size, having it 22 * can use. Since the platform data uses this for an array size, having it
@@ -22,11 +24,25 @@
22 */ 24 */
23#define S3C_FB_MAX_WIN (5) 25#define S3C_FB_MAX_WIN (5)
24 26
27/* IOCTL commands */
28#define S3CFB_WIN_POSITION _IOW('F', 203, \
29 struct s3c_fb_user_window)
30#define S3CFB_WIN_SET_PLANE_ALPHA _IOW('F', 204, \
31 struct s3c_fb_user_plane_alpha)
32#define S3CFB_WIN_SET_CHROMA _IOW('F', 205, \
33 struct s3c_fb_user_chroma)
34#define S3CFB_SET_VSYNC_INT _IOW('F', 206, u32)
35
36#define S3CFB_GET_ION_USER_HANDLE _IOWR('F', 208, \
37 struct s3c_fb_user_ion_client)
38
25/** 39/**
26 * struct s3c_fb_pd_win - per window setup data 40 * struct s3c_fb_pd_win - per window setup data
27 * @win_mode: The display parameters to initialise (not for window 0) 41 * @win_mode: The display parameters to initialise (not for window 0)
28 * @virtual_x: The virtual X size. 42 * @virtual_x: The virtual X size.
29 * @virtual_y: The virtual Y size. 43 * @virtual_y: The virtual Y size.
44 * @width: The width of display in mm
45 * @height: The height of display in mm
30 */ 46 */
31struct s3c_fb_pd_win { 47struct s3c_fb_pd_win {
32 struct fb_videomode win_mode; 48 struct fb_videomode win_mode;
@@ -35,6 +51,8 @@ struct s3c_fb_pd_win {
35 unsigned short max_bpp; 51 unsigned short max_bpp;
36 unsigned short virtual_x; 52 unsigned short virtual_x;
37 unsigned short virtual_y; 53 unsigned short virtual_y;
54 unsigned short width;
55 unsigned short height;
38}; 56};
39 57
40/** 58/**
@@ -74,6 +92,22 @@ struct s3c_fb_platdata {
74extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd); 92extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
75 93
76/** 94/**
95 * s5p_fimd0_set_platdata() - Setup the FB device with platform data.
96 * @pd: The platform data to set. The data is copied from the passed structure
97 * so the machine data can mark the data __initdata so that any unused
98 * machines will end up dumping their data at runtime.
99 */
100extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd);
101
102/**
103 * s5p_fimd1_set_platdata() - Setup the FB device with platform data.
104 * @pd: The platform data to set. The data is copied from the passed structure
105 * so the machine data can mark the data __initdata so that any unused
106 * machines will end up dumping their data at runtime.
107 */
108extern void s5p_fimd1_set_platdata(struct s3c_fb_platdata *pd);
109
110/**
77 * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD 111 * s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
78 * 112 *
79 * Initialise the GPIO for an 24bpp LCD display on the RGB interface. 113 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
@@ -94,4 +128,30 @@ extern void s5pc100_fb_gpio_setup_24bpp(void);
94 */ 128 */
95extern void s5pv210_fb_gpio_setup_24bpp(void); 129extern void s5pv210_fb_gpio_setup_24bpp(void);
96 130
131/**
132 * exynos4_fimd0_gpio_setup_24bpp() - Exynos4 setup function for 24bpp LCD0
133 *
134 * Initialise the GPIO for an 24bpp LCD display on the RGB interface 0.
135 */
136extern void exynos4_fimd0_gpio_setup_24bpp(void);
137
138/**
139 * exynos4_fimd_cfg_gpios() - Exynos4 setup function for 24bpp LCD
140 *
141 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
142 */
143extern void exynos4_fimd_cfg_gpios(unsigned int base, unsigned int nr,
144 unsigned int cfg, s5p_gpio_drvstr_t drvstr);
145
146/**
147 * exynos4_fimd0_setup_clock() = Exynos4 setup function for parent clock.
148 * @dev: device pointer
149 * @parent: parent clock used for LCD pixel clock
150 * @clk_rate: clock rate for parent clock
151 */
152int __init exynos4_fimd0_setup_clock(struct device *dev, const char *parent,
153 unsigned long clk_rate);
154
155int __init exynos4_fimd_setup_clock(struct device *dev, const char *bus_clk,
156 const char *parent, unsigned long clk_rate);
97#endif /* __PLAT_S3C_FB_H */ 157#endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index 1762dcb4cb9..e750ec6fef2 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -26,6 +26,8 @@
26 26
27typedef unsigned int __bitwise__ s3c_gpio_pull_t; 27typedef unsigned int __bitwise__ s3c_gpio_pull_t;
28typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; 28typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
29typedef unsigned int __bitwise__ s5p_gpio_pd_cfg_t;
30typedef unsigned int __bitwise__ s5p_gpio_pd_pull_t;
29 31
30/* forward declaration if gpio-core.h hasn't been included */ 32/* forward declaration if gpio-core.h hasn't been included */
31struct s3c_gpio_chip; 33struct s3c_gpio_chip;
@@ -207,6 +209,65 @@ extern s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin);
207*/ 209*/
208extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr); 210extern int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr);
209 211
212/* Define values for the power down configuration available for each gpio pin.
213 *
214 * These values control the state of the power down configuration resistors
215 * available on most pins on the S5P series.
216 */
217#define S5P_GPIO_PD_OUTPUT0 ((__force s5p_gpio_pd_cfg_t)0x00)
218#define S5P_GPIO_PD_OUTPUT1 ((__force s5p_gpio_pd_cfg_t)0x01)
219#define S5P_GPIO_PD_INPUT ((__force s5p_gpio_pd_cfg_t)0x02)
220#define S5P_GPIO_PD_PREV_STATE ((__force s5p_gpio_pd_cfg_t)0x03)
221
222/**
223 * s5p_gpio_set_pd_cfg() - set the configuration of a gpio power down mode
224 * @pin: The pin number to configure the pull resistor.
225 * @pd_cfg: The configuration for the pwer down mode configuration register.
226 *
227 * This function sets the configuration of the power down mode resistor for the
228 * specified pin. It will return 0 if successful, or a negative error
229 * code if the pin cannot support the requested power down mode.
230 *
231*/
232extern int s5p_gpio_set_pd_cfg(unsigned int pin, s5p_gpio_pd_cfg_t pd_cfg);
233
234/**
235 * s5p_gpio_get_pd_cfg() - get the power down mode configuration of a gpio pin
236 * @pin: The pin number to get the settings for
237 *
238 * Read the power down mode resistor value for the specified pin.
239*/
240extern s5p_gpio_pd_cfg_t s5p_gpio_get_pd_cfg(unsigned int pin);
241
242/* Define values for the power down pull-{up,down} available for each gpio pin.
243 *
244 * These values control the state of the power down mode pull-{up,down}
245 * resistors available on most pins on the S5P series.
246 */
247#define S5P_GPIO_PD_UPDOWN_DISABLE ((__force s5p_gpio_pd_pull_t)0x00)
248#define S5P_GPIO_PD_DOWN_ENABLE ((__force s5p_gpio_pd_pull_t)0x01)
249#define S5P_GPIO_PD_UP_ENABLE ((__force s5p_gpio_pd_pull_t)0x03)
250
251/**
252 * s5p_gpio_set_pd_pull() - set the pull-{up,down} of a gpio pin power down mode
253 * @pin: The pin number to configure the pull resistor.
254 * @pd_pull: The configuration for the power down mode pull resistor.
255 *
256 * This function sets the configuration of the pull-{up,down} resistor for the
257 * specified pin. It will return 0 if successful, or a negative error
258 * code if the pin cannot support the requested pull setting.
259 *
260*/
261extern int s5p_gpio_set_pd_pull(unsigned int pin, s5p_gpio_pd_pull_t pd_pull);
262
263/**
264 * s5p_gpio_get_pd_pull() - get the power down pull resistor config of gpio pin
265 * @pin: The pin number to get the settings for
266 *
267 * Read the power mode pull resistor value for the specified pin.
268*/
269extern s5p_gpio_pd_pull_t s5p_gpio_get_pd_pull(unsigned int pin);
270
210/** 271/**
211 * s5p_register_gpio_interrupt() - register interrupt support for a gpio group 272 * s5p_register_gpio_interrupt() - register interrupt support for a gpio group
212 * @pin: The pin number from the group to be registered 273 * @pin: The pin number from the group to be registered
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index 8cad4cf19c3..35a508ccdf8 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -67,7 +67,8 @@ struct s3c_gpio_chip {
67 void __iomem *base; 67 void __iomem *base;
68 int irq_base; 68 int irq_base;
69 int group; 69 int group;
70 spinlock_t lock; 70 unsigned int eint_offset;
71 spinlock_t lock;
71#ifdef CONFIG_PM 72#ifdef CONFIG_PM
72 u32 pm_save[4]; 73 u32 pm_save[4];
73#endif 74#endif
diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h
index 1543da8f85c..51d52e767a1 100644
--- a/arch/arm/plat-samsung/include/plat/iic.h
+++ b/arch/arm/plat-samsung/include/plat/iic.h
@@ -60,6 +60,7 @@ extern void s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *i2c);
60extern void s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *i2c); 60extern void s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *i2c);
61extern void s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *i2c); 61extern void s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *i2c);
62extern void s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *i2c); 62extern void s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *i2c);
63extern void s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *i2c);
63 64
64/* defined by architecture to configure gpio */ 65/* defined by architecture to configure gpio */
65extern void s3c_i2c0_cfg_gpio(struct platform_device *dev); 66extern void s3c_i2c0_cfg_gpio(struct platform_device *dev);
@@ -71,4 +72,6 @@ extern void s3c_i2c5_cfg_gpio(struct platform_device *dev);
71extern void s3c_i2c6_cfg_gpio(struct platform_device *dev); 72extern void s3c_i2c6_cfg_gpio(struct platform_device *dev);
72extern void s3c_i2c7_cfg_gpio(struct platform_device *dev); 73extern void s3c_i2c7_cfg_gpio(struct platform_device *dev);
73 74
75extern struct s3c2410_platform_i2c default_i2c_data;
76
74#endif /* __ASM_ARCH_IIC_H */ 77#endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/map-base.h b/arch/arm/plat-samsung/include/plat/map-base.h
index 3ffac4d2e4f..ac5fc7b2c91 100644
--- a/arch/arm/plat-samsung/include/plat/map-base.h
+++ b/arch/arm/plat-samsung/include/plat/map-base.h
@@ -35,6 +35,8 @@
35#define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */ 35#define S3C_VA_MEM S3C_ADDR(0x00200000) /* memory control */
36#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */ 36#define S3C_VA_TIMER S3C_ADDR(0x00300000) /* timer block */
37#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */ 37#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000) /* watchdog */
38#define S3C_VA_HSOTG S3C_ADDR(0x00E00000) /* OTG */
39#define S3C_VA_HSPHY S3C_ADDR(0x00F00000) /* OTG PHY */
38#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */ 40#define S3C_VA_UART S3C_ADDR(0x01000000) /* UART */
39 41
40/* This is used for the CPU specific mappings that may be needed, so that 42/* This is used for the CPU specific mappings that may be needed, so that
diff --git a/arch/arm/plat-samsung/include/plat/mshci.h b/arch/arm/plat-samsung/include/plat/mshci.h
new file mode 100644
index 00000000000..a9e84f99492
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/mshci.h
@@ -0,0 +1,163 @@
1/* linux/arch/arm/plat-samsung/include/plat/mshci.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * EXYNOS4 - MSHCI (HSMMC) platform data definitions
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __PLAT_S3C_MSHCI_H
16#define __PLAT_S3C_MSHCI_H __FILE__
17
18struct platform_device;
19struct mmc_host;
20struct mmc_card;
21struct mmc_ios;
22
23enum ms_cd_types {
24 S3C_MSHCI_CD_INTERNAL, /* use mmc internal CD line */
25 S3C_MSHCI_CD_EXTERNAL, /* use external callback */
26 S3C_MSHCI_CD_GPIO, /* use external gpio pin for CD line */
27 S3C_MSHCI_CD_NONE, /* no CD line, use polling to detect card */
28 S3C_MSHCI_CD_PERMANENT, /* no CD line, card permanently wired to host */
29};
30
31/**
32 * struct s3c_mshci_platdata() - Platform device data for Samsung MSHCI
33 * @max_width: The maximum number of data bits supported.
34 * @host_caps: Standard MMC host capabilities bit field.
35 * @cd_type: Type of Card Detection method (see cd_types enum above)
36 * @wp_gpio: The gpio number using for WP.
37 * @has_wp_gpio: Check using wp_gpio or not.
38 * @ext_cd_init: Initialize external card detect subsystem. Called on
39 * mshci-s3c driver probe when cd_type == S3C_MSHCI_CD_EXTERNAL.
40 * notify_func argument is a callback to the mshci-s3c driver
41 * that triggers the card detection event. Callback arguments:
42 * dev is pointer to platform device of the host controller,
43 * state is new state of the card (0 - removed, 1 - inserted).
44 * @ext_cd_cleanup: Cleanup external card detect subsystem. Called on
45 * mshci-s3c driver remove when cd_type == S3C_MSHCI_CD_EXTERNAL.
46 * notify_func argument is the same callback as for ext_cd_init.
47 * @ext_cd_gpio: gpio pin used for external CD line, valid only if
48 * cd_type == S3C_MSHCI_CD_GPIO
49 * @ext_cd_gpio_invert: invert values for external CD gpio line
50 * @cfg_gpio: Configure the GPIO for a specific card bit-width
51 * @cfg_card: Configure the interface for a specific card and speed. This
52 * is necessary the controllers and/or GPIO blocks require the
53 * changing of driver-strength and other controls dependant on
54 * the card and speed of operation.
55 *
56 * Initialisation data specific to either the machine or the platform
57 * for the device driver to use or call-back when configuring gpio or
58 * card speed information.
59*/
60struct s3c_mshci_platdata {
61 unsigned int max_width;
62 unsigned int host_caps;
63 enum ms_cd_types cd_type;
64
65 char **clocks; /* set of clock sources */
66
67 int wp_gpio;
68 int ext_cd_gpio;
69 bool ext_cd_gpio_invert;
70 bool has_wp_gpio;
71 int (*ext_cd_init)(void (*notify_func)(struct platform_device *,
72 int state));
73 int (*ext_cd_cleanup)(void (*notify_func)(struct platform_device *,
74 int state));
75
76 void (*cfg_gpio)(struct platform_device *dev, int width);
77#if defined(CONFIG_EXYNOS4_MSHC_VPLL_46MHZ) || \
78 defined(CONFIG_EXYNOS4_MSHC_EPLL_45MHZ)
79 void (*cfg_ddr)(struct platform_device *dev, int ddr);
80#endif
81 void (*init_card)(struct platform_device *dev);
82
83 void (*cfg_card)(struct platform_device *dev,
84 void __iomem *regbase,
85 struct mmc_ios *ios,
86 struct mmc_card *card);
87};
88
89/**
90 * s3c_mshci_set_platdata - Set platform data for S3C MSHCI device.
91 * @pd: Platform data to register to device.
92 *
93 * Register the given platform data for use withe S3C MSHCI device.
94 * The call will copy the platform data, so the board definitions can
95 * make the structure itself __initdata.
96 */
97extern void s3c_mshci_set_platdata(struct s3c_mshci_platdata *pd);
98
99/* Default platform data, exported so that per-cpu initialisation can
100 * set the correct one when there are more than one cpu type selected.
101*/
102
103extern struct s3c_mshci_platdata s3c_mshci_def_platdata;
104
105/* Helper function availablity */
106
107extern void s5p6450_setup_mshci_cfg_gpio(struct platform_device *, int w);
108
109/* S5P6450 MSHCI setup */
110extern char *s5p6450_mshc_clksrcs[1];
111
112extern void s5p6450_setup_mshci_cfg_card(struct platform_device *dev,
113 void __iomem *r,
114 struct mmc_ios *ios,
115 struct mmc_card *card);
116
117static inline void s5p6450_default_mshci(void)
118{
119#ifdef CONFIG_S5P_DEV_MSHC
120 s3c_mshci_def_platdata.clocks = s5p6450_mshc_clksrcs;
121 s3c_mshci_def_platdata.cfg_gpio = s5p6450_setup_mshci_cfg_gpio;
122 s3c_mshci_def_platdata.cfg_card = s5p6450_setup_mshci_cfg_card;
123#endif /* CONFIG_S3C_DEV_MSHC */
124}
125
126extern void exynos4_setup_mshci_cfg_gpio(struct platform_device *, int w);
127
128/* EXYNOS4 MSHCI setup */
129#ifdef CONFIG_EXYNOS4_SETUP_MSHCI
130extern char *exynos4_mshci_clksrcs[1];
131#endif
132
133extern void exynos4_setup_mshci_cfg_card(struct platform_device *dev,
134 void __iomem *r,
135 struct mmc_ios *ios,
136 struct mmc_card *card);
137
138#if defined(CONFIG_EXYNOS4_MSHC_VPLL_46MHZ) || \
139 defined(CONFIG_EXYNOS4_MSHC_EPLL_45MHZ)
140extern void exynos4_setup_mshci_cfg_ddr(struct platform_device *dev,
141 int ddr);
142#endif
143
144extern void exynos4_setup_mshci_init_card(struct platform_device *dev);
145
146#ifdef CONFIG_S5P_DEV_MSHC
147static inline void exynos4_default_mshci(void)
148{
149 s3c_mshci_def_platdata.clocks = exynos4_mshci_clksrcs;
150 s3c_mshci_def_platdata.cfg_gpio = exynos4_setup_mshci_cfg_gpio;
151 s3c_mshci_def_platdata.cfg_card = exynos4_setup_mshci_cfg_card;
152#if defined(CONFIG_EXYNOS4_MSHC_VPLL_46MHZ) || \
153 defined(CONFIG_EXYNOS4_MSHC_EPLL_45MHZ)
154 s3c_mshci_def_platdata.cfg_ddr = exynos4_setup_mshci_cfg_ddr;
155#endif
156
157 s3c_mshci_def_platdata.init_card = exynos4_setup_mshci_init_card;
158}
159#else
160static inline void exynos4_default_mshci(void) { }
161#endif /* CONFIG_S5P_DEV_MSHC */
162
163#endif /* __PLAT_S3C_MSHCI_H */
diff --git a/arch/arm/plat-samsung/include/plat/pd.h b/arch/arm/plat-samsung/include/plat/pd.h
index abb4bc32716..ccbbc910b05 100644
--- a/arch/arm/plat-samsung/include/plat/pd.h
+++ b/arch/arm/plat-samsung/include/plat/pd.h
@@ -12,19 +12,35 @@
12#define __ASM_PLAT_SAMSUNG_PD_H __FILE__ 12#define __ASM_PLAT_SAMSUNG_PD_H __FILE__
13 13
14struct samsung_pd_info { 14struct samsung_pd_info {
15 int (*init)(struct device *dev);
15 int (*enable)(struct device *dev); 16 int (*enable)(struct device *dev);
16 int (*disable)(struct device *dev); 17 int (*disable)(struct device *dev);
17 void __iomem *base; 18 void __iomem *base;
19 void *data;
18}; 20};
19 21
20enum exynos4_pd_block { 22enum exynos_pd_block {
21 PD_MFC, 23 PD_MFC,
22 PD_G3D, 24 PD_G3D,
23 PD_LCD0, 25 PD_LCD0,
24 PD_LCD1, 26 PD_LCD1,
25 PD_TV, 27 PD_TV,
26 PD_CAM, 28 PD_CAM,
27 PD_GPS 29 PD_GPS,
30 PD_GPS_ALIVE,
31 PD_ISP,
32 PD_GSCL,
33 PD_DISP1,
28}; 34};
29 35
36struct exynos_pd_data {
37 void __iomem *clk_base;
38 void __iomem *clksrc_base;
39 void __iomem *read_base;
40 unsigned long read_phy_addr;
41};
42
43int exynos_pd_init(struct device *dev);
44int exynos_pd_enable(struct device *dev);
45int exynos_pd_disable(struct device *dev);
30#endif /* __ASM_PLAT_SAMSUNG_PD_H */ 46#endif /* __ASM_PLAT_SAMSUNG_PD_H */
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index 7fb6f6be8c8..ee289223919 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -43,6 +43,7 @@ extern unsigned long s3c_irqwake_eintallow;
43 43
44extern void (*pm_cpu_prep)(void); 44extern void (*pm_cpu_prep)(void);
45extern void (*pm_cpu_sleep)(void); 45extern void (*pm_cpu_sleep)(void);
46extern void (*pm_cpu_restore)(void);
46 47
47/* Flags for PM Control */ 48/* Flags for PM Control */
48 49
@@ -102,10 +103,12 @@ extern void s3c_pm_do_restore(struct sleep_save *ptr, int count);
102extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count); 103extern void s3c_pm_do_restore_core(struct sleep_save *ptr, int count);
103 104
104#ifdef CONFIG_PM 105#ifdef CONFIG_PM
106extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
105extern int s3c_irqext_wake(struct irq_data *data, unsigned int state); 107extern int s3c_irqext_wake(struct irq_data *data, unsigned int state);
106extern int s3c24xx_irq_suspend(void); 108extern int s3c24xx_irq_suspend(void);
107extern void s3c24xx_irq_resume(void); 109extern void s3c24xx_irq_resume(void);
108#else 110#else
111#define s3c_irq_wake NULL
109#define s3c_irqext_wake NULL 112#define s3c_irqext_wake NULL
110#define s3c24xx_irq_suspend NULL 113#define s3c24xx_irq_suspend NULL
111#define s3c24xx_irq_resume NULL 114#define s3c24xx_irq_resume NULL
@@ -128,7 +131,7 @@ extern void s3c_pm_dbg(const char *msg, ...);
128 131
129#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt) 132#define S3C_PMDBG(fmt...) s3c_pm_dbg(fmt)
130#else 133#else
131#define S3C_PMDBG(fmt...) printk(KERN_DEBUG fmt) 134#define S3C_PMDBG(fmt...) pr_debug(fmt)
132#endif 135#endif
133 136
134#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK 137#ifdef CONFIG_S3C_PM_DEBUG_LED_SMDK
diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h
index 7554c4fcddb..18a95105b88 100644
--- a/arch/arm/plat-samsung/include/plat/regs-adc.h
+++ b/arch/arm/plat-samsung/include/plat/regs-adc.h
@@ -21,16 +21,19 @@
21#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10) 21#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
22#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14) 22#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14)
23#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18) 23#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18)
24#define S5PV210_ADCMUX S3C2410_ADCREG(0x1C)
24#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20) 25#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)
25 26
26 27
27/* ADCCON Register Bits */ 28/* ADCCON Register Bits */
29#define S3C64XX_ADCCON_TSSEL (1<<17)
28#define S3C64XX_ADCCON_RESSEL (1<<16) 30#define S3C64XX_ADCCON_RESSEL (1<<16)
29#define S3C2410_ADCCON_ECFLG (1<<15) 31#define S3C2410_ADCCON_ECFLG (1<<15)
30#define S3C2410_ADCCON_PRSCEN (1<<14) 32#define S3C2410_ADCCON_PRSCEN (1<<14)
31#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6) 33#define S3C2410_ADCCON_PRSCVL(x) (((x)&0xFF)<<6)
32#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6) 34#define S3C2410_ADCCON_PRSCVLMASK (0xFF<<6)
33#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3) 35#define S3C2410_ADCCON_SELMUX(x) (((x)&0x7)<<3)
36#define S5PV210_ADCCON_SELMUX(x) (((x)&0xF)<<0)
34#define S3C2410_ADCCON_MUXMASK (0x7<<3) 37#define S3C2410_ADCCON_MUXMASK (0x7<<3)
35#define S3C2410_ADCCON_STDBM (1<<2) 38#define S3C2410_ADCCON_STDBM (1<<2)
36#define S3C2410_ADCCON_READ_START (1<<1) 39#define S3C2410_ADCCON_READ_START (1<<1)
@@ -59,6 +62,9 @@
59#define S3C2410_ADCDAT1_XY_PST (0x3<<12) 62#define S3C2410_ADCDAT1_XY_PST (0x3<<12)
60#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF) 63#define S3C2410_ADCDAT1_YPDATA_MASK (0x03FF)
61 64
65/* ADCDLY Register Bits */
66#define S3C2410_ADCDLY_DELAY(x) (((x)&0xFFFF)<<0)
67
62#endif /* __ASM_ARCH_REGS_ADC_H */ 68#endif /* __ASM_ARCH_REGS_ADC_H */
63 69
64 70
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
index 4c3647f8005..9c5534ef2a2 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
@@ -30,9 +30,17 @@
30#define VIDCON1_FSTATUS_EVEN (1 << 15) 30#define VIDCON1_FSTATUS_EVEN (1 << 15)
31 31
32/* Video timing controls */ 32/* Video timing controls */
33#ifdef CONFIG_FB_EXYNOS_FIMD_V8
34#define VIDTCON0 (0x20010)
35#define VIDTCON1 (0x20014)
36#define VIDTCON2 (0x20018)
37#define VIDTCON3 (0x2001C)
38#else
33#define VIDTCON0 (0x10) 39#define VIDTCON0 (0x10)
34#define VIDTCON1 (0x14) 40#define VIDTCON1 (0x14)
35#define VIDTCON2 (0x18) 41#define VIDTCON2 (0x18)
42#define VIDTCON3 (0x1C)
43#endif
36 44
37/* Window position controls */ 45/* Window position controls */
38 46
@@ -43,9 +51,12 @@
43#define VIDOSD_BASE (0x40) 51#define VIDOSD_BASE (0x40)
44 52
45#define VIDINTCON0 (0x130) 53#define VIDINTCON0 (0x130)
54#define VIDINTCON1 (0x134)
46 55
47/* WINCONx */ 56/* WINCONx */
48 57
58#define WINCONx_CSC_CON_EQ709 (1 << 28)
59#define WINCONx_CSC_CON_EQ601 (0 << 28)
49#define WINCONx_CSCWIDTH_MASK (0x3 << 26) 60#define WINCONx_CSCWIDTH_MASK (0x3 << 26)
50#define WINCONx_CSCWIDTH_SHIFT (26) 61#define WINCONx_CSCWIDTH_SHIFT (26)
51#define WINCONx_CSCWIDTH_WIDE (0x0 << 26) 62#define WINCONx_CSCWIDTH_WIDE (0x0 << 26)
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
index 8f39aa5b26e..98d9e16b9e0 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -38,6 +38,7 @@
38#define VIDCON0_VIDOUT_TV (0x1 << 26) 38#define VIDCON0_VIDOUT_TV (0x1 << 26)
39#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) 39#define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26)
40#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26) 40#define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26)
41#define VIDCON0_VIDOUT_WB (0x4 << 26)
41 42
42#define VIDCON0_L1_DATA_MASK (0x7 << 23) 43#define VIDCON0_L1_DATA_MASK (0x7 << 23)
43#define VIDCON0_L1_DATA_SHIFT (23) 44#define VIDCON0_L1_DATA_SHIFT (23)
@@ -81,7 +82,12 @@
81#define VIDCON0_ENVID (1 << 1) 82#define VIDCON0_ENVID (1 << 1)
82#define VIDCON0_ENVID_F (1 << 0) 83#define VIDCON0_ENVID_F (1 << 0)
83 84
85#ifdef CONFIG_FB_EXYNOS_FIMD_V8
86#define VIDCON1 (0x20004)
87#else
84#define VIDCON1 (0x04) 88#define VIDCON1 (0x04)
89#endif
90
85#define VIDCON1_LINECNT_MASK (0x7ff << 16) 91#define VIDCON1_LINECNT_MASK (0x7ff << 16)
86#define VIDCON1_LINECNT_SHIFT (16) 92#define VIDCON1_LINECNT_SHIFT (16)
87#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) 93#define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff)
@@ -91,6 +97,9 @@
91#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13) 97#define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13)
92#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13) 98#define VIDCON1_VSTATUS_ACTIVE (0x2 << 13)
93#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13) 99#define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13)
100#define VIDCON1_VCLK_MASK (0x3 << 9)
101#define VIDCON1_VCLK_HOLD (0x0 << 9)
102#define VIDCON1_VCLK_RUN (0x1 << 9)
94 103
95#define VIDCON1_INV_VCLK (1 << 7) 104#define VIDCON1_INV_VCLK (1 << 7)
96#define VIDCON1_INV_HSYNC (1 << 6) 105#define VIDCON1_INV_HSYNC (1 << 6)
@@ -99,18 +108,22 @@
99 108
100/* VIDCON2 */ 109/* VIDCON2 */
101 110
102#define VIDCON2 (0x08) 111#define VIDCON2 (0x08)
103#define VIDCON2_EN601 (1 << 23) 112#define VIDCON2_EN601 (1 << 23)
104#define VIDCON2_TVFMTSEL_SW (1 << 14) 113#define VIDCON2_WB_DISABLE (0 << 15)
105 114#define VIDCON2_WB_ENABLE (1 << 15)
106#define VIDCON2_TVFMTSEL1_MASK (0x3 << 12) 115#define VIDCON2_WB_MASK (1 << 15)
107#define VIDCON2_TVFMTSEL1_SHIFT (12) 116#define VIDCON2_TVFORMATSEL_HW (0 << 14)
108#define VIDCON2_TVFMTSEL1_RGB (0x0 << 12) 117#define VIDCON2_TVFORMATSEL_SW (1 << 14)
109#define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12) 118#define VIDCON2_TVFORMATSEL_HW_SW_MASK (1 << 14)
110#define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12) 119#define VIDCON2_TVFORMATSEL_MASK (0x3 << 12)
111 120#define VIDCON2_TVFORMATSEL_SHIFT (12)
112#define VIDCON2_ORGYCbCr (1 << 8) 121#define VIDCON2_TVFORMATSEL_RGB (0x0 << 12)
113#define VIDCON2_YUVORDCrCb (1 << 7) 122#define VIDCON2_TVFORMATSEL_YUV422 (0x1 << 12)
123#define VIDCON2_TVFORMATSEL_YUV444 (0x2 << 12)
124
125#define VIDCON2_ORGYCbCr (1 << 8)
126#define VIDCON2_YUVORDCrCb (1 << 7)
114 127
115/* PRTCON (S3C6410, S5PC100) 128/* PRTCON (S3C6410, S5PC100)
116 * Might not be present in the S3C6410 documentation, 129 * Might not be present in the S3C6410 documentation,
@@ -163,24 +176,29 @@
163#define VIDTCON1_HSPW_LIMIT (0xff) 176#define VIDTCON1_HSPW_LIMIT (0xff)
164#define VIDTCON1_HSPW(_x) ((_x) << 0) 177#define VIDTCON1_HSPW(_x) ((_x) << 0)
165 178
166#define VIDTCON2 (0x18) 179/* VIDTCON2 */
180
181#define VIDTCON2_LINEVAL_E(_x) ((((_x) & 0x800) >> 11) << 23)
167#define VIDTCON2_LINEVAL_MASK (0x7ff << 11) 182#define VIDTCON2_LINEVAL_MASK (0x7ff << 11)
168#define VIDTCON2_LINEVAL_SHIFT (11) 183#define VIDTCON2_LINEVAL_SHIFT (11)
169#define VIDTCON2_LINEVAL_LIMIT (0x7ff) 184#define VIDTCON2_LINEVAL_LIMIT (0x7ff)
170#define VIDTCON2_LINEVAL(_x) ((_x) << 11) 185#define VIDTCON2_LINEVAL(_x) (((_x) & 0x7ff) << 11)
171 186
187#define VIDTCON2_HOZVAL_E(_x) ((((_x) & 0x800) >> 11) << 22)
172#define VIDTCON2_HOZVAL_MASK (0x7ff << 0) 188#define VIDTCON2_HOZVAL_MASK (0x7ff << 0)
173#define VIDTCON2_HOZVAL_SHIFT (0) 189#define VIDTCON2_HOZVAL_SHIFT (0)
174#define VIDTCON2_HOZVAL_LIMIT (0x7ff) 190#define VIDTCON2_HOZVAL_LIMIT (0x7ff)
175#define VIDTCON2_HOZVAL(_x) ((_x) << 0) 191#define VIDTCON2_HOZVAL(_x) (((_x) & 0x7ff) << 0)
176 192
177/* WINCONx */ 193/* WINCONx */
178 194
179
180#define WINCONx_BITSWP (1 << 18) 195#define WINCONx_BITSWP (1 << 18)
181#define WINCONx_BYTSWP (1 << 17) 196#define WINCONx_BYTSWP (1 << 17)
182#define WINCONx_HAWSWP (1 << 16) 197#define WINCONx_HAWSWP (1 << 16)
183#define WINCONx_WSWP (1 << 15) 198#define WINCONx_WSWP (1 << 15)
199#define WINCONx_ENLOCAL_MASK (0xf << 15)
200#define WINCONx_INRGB_RGB (0 << 13)
201#define WINCONx_INRGB_YCBCR (1 << 13)
184#define WINCONx_BURSTLEN_MASK (0x3 << 9) 202#define WINCONx_BURSTLEN_MASK (0x3 << 9)
185#define WINCONx_BURSTLEN_SHIFT (9) 203#define WINCONx_BURSTLEN_SHIFT (9)
186#define WINCONx_BURSTLEN_16WORD (0x0 << 9) 204#define WINCONx_BURSTLEN_16WORD (0x0 << 9)
@@ -200,6 +218,7 @@
200#define WINCON0_BPPMODE_24BPP_888 (0xb << 2) 218#define WINCON0_BPPMODE_24BPP_888 (0xb << 2)
201 219
202#define WINCON1_BLD_PIX (1 << 6) 220#define WINCON1_BLD_PIX (1 << 6)
221#define WINCON1_BLD_PLANE (0 << 6)
203 222
204#define WINCON1_ALPHA_SEL (1 << 1) 223#define WINCON1_ALPHA_SEL (1 << 1)
205#define WINCON1_BPPMODE_MASK (0xf << 2) 224#define WINCON1_BPPMODE_MASK (0xf << 2)
@@ -228,25 +247,29 @@
228/* Local input channels (windows 0-2) */ 247/* Local input channels (windows 0-2) */
229#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win))) 248#define SHADOWCON_CHx_LOCAL_ENABLE(_win) (1 << (5 + (_win)))
230 249
250#define VIDOSDxA_TOPLEFT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
231#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) 251#define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11)
232#define VIDOSDxA_TOPLEFT_X_SHIFT (11) 252#define VIDOSDxA_TOPLEFT_X_SHIFT (11)
233#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff) 253#define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff)
234#define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11) 254#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x7ff) << 11)
235 255
256#define VIDOSDxA_TOPLEFT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
236#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0) 257#define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0)
237#define VIDOSDxA_TOPLEFT_Y_SHIFT (0) 258#define VIDOSDxA_TOPLEFT_Y_SHIFT (0)
238#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff) 259#define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff)
239#define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0) 260#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x7ff) << 0)
240 261
262#define VIDOSDxB_BOTRIGHT_X_E(_x) ((((_x) & 0x800) >> 11) << 23)
241#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11) 263#define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11)
242#define VIDOSDxB_BOTRIGHT_X_SHIFT (11) 264#define VIDOSDxB_BOTRIGHT_X_SHIFT (11)
243#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff) 265#define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff)
244#define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11) 266#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x7ff) << 11)
245 267
268#define VIDOSDxB_BOTRIGHT_Y_E(_x) ((((_x) & 0x800) >> 11) << 22)
246#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0) 269#define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0)
247#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0) 270#define VIDOSDxB_BOTRIGHT_Y_SHIFT (0)
248#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff) 271#define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff)
249#define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0) 272#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x7ff) << 0)
250 273
251/* For VIDOSD[1..4]C */ 274/* For VIDOSD[1..4]C */
252#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20) 275#define VIDISD14C_ALPHA0_R(_x) ((_x) << 20)
@@ -278,15 +301,17 @@
278#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8)) 301#define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8))
279#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4)) 302#define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4))
280 303
304#define VIDW_BUF_SIZE_OFFSET_E(_x) ((((_x) & 0x2000) >> 13) << 27)
281#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13) 305#define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13)
282#define VIDW_BUF_SIZE_OFFSET_SHIFT (13) 306#define VIDW_BUF_SIZE_OFFSET_SHIFT (13)
283#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff) 307#define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff)
284#define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13) 308#define VIDW_BUF_SIZE_OFFSET(_x) (((_x) & 0x1fff) << 13)
285 309
310#define VIDW_BUF_SIZE_PAGEWIDTH_E(_x) ((((_x) & 0x2000) >> 13) << 26)
286#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0) 311#define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0)
287#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0) 312#define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0)
288#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff) 313#define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff)
289#define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0) 314#define VIDW_BUF_SIZE_PAGEWIDTH(_x) (((_x) & 0x1fff) << 0)
290 315
291/* Interrupt controls and status */ 316/* Interrupt controls and status */
292 317
@@ -384,3 +409,16 @@
384#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0) 409#define WPALCON_W0PAL_16BPP_A555 (0x5 << 0)
385#define WPALCON_W0PAL_16BPP_565 (0x6 << 0) 410#define WPALCON_W0PAL_16BPP_565 (0x6 << 0)
386 411
412/* Blending equation control */
413#define BLENDCON (0x260)
414#define BLENDCON_NEW_MASK (1 << 0)
415#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
416#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
417
418/* DP clock control */
419#define DPCLKCON (0x27c)
420#define DPCLKCON_ENABLE (1 << 1)
421
422/* Window alpha control */
423#define VIDW0ALPHA0 (0x200)
424#define VIDW0ALPHA1 (0x204)
diff --git a/arch/arm/plat-samsung/include/plat/regs-otg.h b/arch/arm/plat-samsung/include/plat/regs-otg.h
new file mode 100644
index 00000000000..cf01506301c
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-otg.h
@@ -0,0 +1,259 @@
1/* linux/arch/arm/plat-samsung/include/plat/regs-otg.h
2 *
3 * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
4 *
5 * This include file is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9*/
10
11#ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
12#define __ASM_ARCH_REGS_USB_OTG_HS_H
13
14/* USB2.0 OTG Controller register */
15#define S3C_USBOTG_PHYREG(x) ((x) + S3C_VA_HSPHY)
16#define S3C_USBOTG_PHYPWR S3C_USBOTG_PHYREG(0x0)
17#define S3C_USBOTG_PHYCLK S3C_USBOTG_PHYREG(0x4)
18#define S3C_USBOTG_RSTCON S3C_USBOTG_PHYREG(0x8)
19#define S3C_USBOTG_PHY1CON S3C_USBOTG_PHYREG(0x34)
20
21/* USB2.0 OTG Controller register */
22#define S3C_USBOTGREG(x) (x)
23/*============================================================================================== */
24 /* Core Global Registers */
25#define S3C_UDC_OTG_GOTGCTL S3C_USBOTGREG(0x000) /* OTG Control & Status */
26#define S3C_UDC_OTG_GOTGINT S3C_USBOTGREG(0x004) /* OTG Interrupt */
27#define S3C_UDC_OTG_GAHBCFG S3C_USBOTGREG(0x008) /* Core AHB Configuration */
28#define S3C_UDC_OTG_GUSBCFG S3C_USBOTGREG(0x00C) /* Core USB Configuration */
29#define S3C_UDC_OTG_GRSTCTL S3C_USBOTGREG(0x010) /* Core Reset */
30#define S3C_UDC_OTG_GINTSTS S3C_USBOTGREG(0x014) /* Core Interrupt */
31#define S3C_UDC_OTG_GINTMSK S3C_USBOTGREG(0x018) /* Core Interrupt Mask */
32#define S3C_UDC_OTG_GRXSTSR S3C_USBOTGREG(0x01C) /* Receive Status Debug Read/Status Read */
33#define S3C_UDC_OTG_GRXSTSP S3C_USBOTGREG(0x020) /* Receive Status Debug Pop/Status Pop */
34#define S3C_UDC_OTG_GRXFSIZ S3C_USBOTGREG(0x024) /* Receive FIFO Size */
35#define S3C_UDC_OTG_GNPTXFSIZ S3C_USBOTGREG(0x028) /* Non-Periodic Transmit FIFO Size */
36#define S3C_UDC_OTG_GNPTXSTS S3C_USBOTGREG(0x02C) /* Non-Periodic Transmit FIFO/Queue Status */
37
38#define S3C_UDC_OTG_HPTXFSIZ S3C_USBOTGREG(0x100) /* Host Periodic Transmit FIFO Size */
39#define S3C_UDC_OTG_DIEPTXF(n) S3C_USBOTGREG(0x104 + (n-1)*0x4)/* Device IN EP Transmit FIFO Size Register */
40
41/*============================================================================================== */
42/* Host Mode Registers */
43/*------------------------------------------------ */
44/* Host Global Registers */
45#define S3C_UDC_OTG_HCFG S3C_USBOTGREG(0x400) /* Host Configuration */
46#define S3C_UDC_OTG_HFIR S3C_USBOTGREG(0x404) /* Host Frame Interval */
47#define S3C_UDC_OTG_HFNUM S3C_USBOTGREG(0x408) /* Host Frame Number/Frame Time Remaining */
48#define S3C_UDC_OTG_HPTXSTS S3C_USBOTGREG(0x410) /* Host Periodic Transmit FIFO/Queue Status */
49#define S3C_UDC_OTG_HAINT S3C_USBOTGREG(0x414) /* Host All Channels Interrupt */
50#define S3C_UDC_OTG_HAINTMSK S3C_USBOTGREG(0x418) /* Host All Channels Interrupt Mask */
51
52/*------------------------------------------------ */
53/* Host Port Control & Status Registers */
54#define S3C_UDC_OTG_HPRT S3C_USBOTGREG(0x440) /* Host Port Control & Status */
55
56/*------------------------------------------------ */
57/* Host Channel-Specific Registers */
58#define S3C_UDC_OTG_HCCHAR0 S3C_USBOTGREG(0x500) /* Host Channel-0 Characteristics */
59#define S3C_UDC_OTG_HCSPLT0 S3C_USBOTGREG(0x504) /* Host Channel-0 Split Control */
60#define S3C_UDC_OTG_HCINT0 S3C_USBOTGREG(0x508) /* Host Channel-0 Interrupt */
61#define S3C_UDC_OTG_HCINTMSK0 S3C_USBOTGREG(0x50C) /* Host Channel-0 Interrupt Mask */
62#define S3C_UDC_OTG_HCTSIZ0 S3C_USBOTGREG(0x510) /* Host Channel-0 Transfer Size */
63#define S3C_UDC_OTG_HCDMA0 S3C_USBOTGREG(0x514) /* Host Channel-0 DMA Address */
64
65/*============================================================================================== */
66/* Device Mode Registers */
67/*------------------------------------------------ */
68/* Device Global Registers */
69#define S3C_UDC_OTG_DCFG S3C_USBOTGREG(0x800) /* Device Configuration */
70#define S3C_UDC_OTG_DCTL S3C_USBOTGREG(0x804) /* Device Control */
71#define S3C_UDC_OTG_DSTS S3C_USBOTGREG(0x808) /* Device Status */
72#define S3C_UDC_OTG_DIEPMSK S3C_USBOTGREG(0x810) /* Device IN Endpoint Common Interrupt Mask */
73#define S3C_UDC_OTG_DOEPMSK S3C_USBOTGREG(0x814) /* Device OUT Endpoint Common Interrupt Mask */
74#define S3C_UDC_OTG_DAINT S3C_USBOTGREG(0x818) /* Device All Endpoints Interrupt */
75#define S3C_UDC_OTG_DAINTMSK S3C_USBOTGREG(0x81C) /* Device All Endpoints Interrupt Mask */
76#define S3C_UDC_OTG_DTKNQR1 S3C_USBOTGREG(0x820) /* Device IN Token Sequence Learning Queue Read 1 */
77#define S3C_UDC_OTG_DTKNQR2 S3C_USBOTGREG(0x824) /* Device IN Token Sequence Learning Queue Read 2 */
78#define S3C_UDC_OTG_DVBUSDIS S3C_USBOTGREG(0x828) /* Device VBUS Discharge Time */
79#define S3C_UDC_OTG_DVBUSPULSE S3C_USBOTGREG(0x82C) /* Device VBUS Pulsing Time */
80#define S3C_UDC_OTG_DTKNQR3 S3C_USBOTGREG(0x830) /* Device IN Token Sequence Learning Queue Read 3 */
81#define S3C_UDC_OTG_DTKNQR4 S3C_USBOTGREG(0x834) /* Device IN Token Sequence Learning Queue Read 4 */
82
83/*------------------------------------------------ */
84/* Device Logical IN Endpoint-Specific Registers */
85#define S3C_UDC_OTG_DIEPCTL(n) S3C_USBOTGREG(0x900 + n*0x20) /* Device IN Endpoint n Control */
86#define S3C_UDC_OTG_DIEPINT(n) S3C_USBOTGREG(0x908 + n*0x20) /* Device IN Endpoint n Interrupt */
87#define S3C_UDC_OTG_DIEPTSIZ(n) S3C_USBOTGREG(0x910 + n*0x20) /* Device IN Endpoint n Transfer Size */
88#define S3C_UDC_OTG_DIEPDMA(n) S3C_USBOTGREG(0x914 + n*0x20) /* Device IN Endpoint n DMA Address */
89
90/*------------------------------------------------ */
91/* Device Logical OUT Endpoint-Specific Registers */
92#define S3C_UDC_OTG_DOEPCTL(n) S3C_USBOTGREG(0xB00 + n*0x20) /* Device OUT Endpoint n Control */
93#define S3C_UDC_OTG_DOEPINT(n) S3C_USBOTGREG(0xB08 + n*0x20) /* Device OUT Endpoint n Interrupt */
94#define S3C_UDC_OTG_DOEPTSIZ(n) S3C_USBOTGREG(0xB10 + n*0x20) /* Device OUT Endpoint n Transfer Size */
95#define S3C_UDC_OTG_DOEPDMA(n) S3C_USBOTGREG(0xB14 + n*0x20) /* Device OUT Endpoint n DMA Address */
96
97/*------------------------------------------------ */
98/* Endpoint FIFO address */
99#define S3C_UDC_OTG_EP0_FIFO S3C_USBOTGREG(0x1000)
100#define S3C_UDC_OTG_EP1_FIFO S3C_USBOTGREG(0x2000)
101#define S3C_UDC_OTG_EP2_FIFO S3C_USBOTGREG(0x3000)
102#define S3C_UDC_OTG_EP3_FIFO S3C_USBOTGREG(0x4000)
103#define S3C_UDC_OTG_EP4_FIFO S3C_USBOTGREG(0x5000)
104#define S3C_UDC_OTG_EP5_FIFO S3C_USBOTGREG(0x6000)
105#define S3C_UDC_OTG_EP6_FIFO S3C_USBOTGREG(0x7000)
106#define S3C_UDC_OTG_EP7_FIFO S3C_USBOTGREG(0x8000)
107#define S3C_UDC_OTG_EP8_FIFO S3C_USBOTGREG(0x9000)
108#define S3C_UDC_OTG_EP9_FIFO S3C_USBOTGREG(0xA000)
109#define S3C_UDC_OTG_EP10_FIFO S3C_USBOTGREG(0xB000)
110#define S3C_UDC_OTG_EP11_FIFO S3C_USBOTGREG(0xC000)
111#define S3C_UDC_OTG_EP12_FIFO S3C_USBOTGREG(0xD000)
112#define S3C_UDC_OTG_EP13_FIFO S3C_USBOTGREG(0xE000)
113#define S3C_UDC_OTG_EP14_FIFO S3C_USBOTGREG(0xF000)
114#define S3C_UDC_OTG_EP15_FIFO S3C_USBOTGREG(0x10000)
115
116/*===================================================================== */
117/*definitions related to CSR setting */
118
119/* S3C_UDC_OTG_GOTGCTL */
120#define B_SESSION_VALID (0x1<<19)
121#define A_SESSION_VALID (0x1<<18)
122
123/* S3C_UDC_OTG_GAHBCFG */
124#define PTXFE_HALF (0<<8)
125#define PTXFE_ZERO (1<<8)
126#define NPTXFE_HALF (0<<7)
127#define NPTXFE_ZERO (1<<7)
128#define MODE_SLAVE (0<<5)
129#define MODE_DMA (1<<5)
130#define BURST_SINGLE (0<<1)
131#define BURST_INCR (1<<1)
132#define BURST_INCR4 (3<<1)
133#define BURST_INCR8 (5<<1)
134#define BURST_INCR16 (7<<1)
135#define GBL_INT_UNMASK (1<<0)
136#define GBL_INT_MASK (0<<0)
137
138/* S3C_UDC_OTG_GRSTCTL */
139#define AHB_MASTER_IDLE (1u<<31)
140#define CORE_SOFT_RESET (0x1<<0)
141
142/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */
143#define INT_RESUME (1u<<31)
144#define INT_DISCONN (0x1<<29)
145#define INT_CONN_ID_STS_CNG (0x1<<28)
146#define INT_OUT_EP (0x1<<19)
147#define INT_IN_EP (0x1<<18)
148#define INT_ENUMDONE (0x1<<13)
149#define INT_RESET (0x1<<12)
150#define INT_SUSPEND (0x1<<11)
151#define INT_EARLY_SUSPEND (0x1<<10)
152#define INT_NP_TX_FIFO_EMPTY (0x1<<5)
153#define INT_RX_FIFO_NOT_EMPTY (0x1<<4)
154#define INT_SOF (0x1<<3)
155#define INT_DEV_MODE (0x0<<0)
156#define INT_HOST_MODE (0x1<<1)
157#define INT_GOUTNakEff (0x01<<7)
158#define INT_GINNakEff (0x01<<6)
159
160#define FULL_SPEED_CONTROL_PKT_SIZE 8
161#define FULL_SPEED_BULK_PKT_SIZE 64
162
163#define HIGH_SPEED_CONTROL_PKT_SIZE 64
164#define HIGH_SPEED_BULK_PKT_SIZE 512
165
166#ifdef CONFIG_CPU_S5P6450
167#define RX_FIFO_SIZE (4096>>2)
168#define NPTX_FIFO_START_ADDR RX_FIFO_SIZE
169#define NPTX_FIFO_SIZE (4096>>2)
170#define PTX_FIFO_SIZE (1520>>2)
171#else
172#define RX_FIFO_SIZE (4096>>2)
173#define NPTX_FIFO_START_ADDR RX_FIFO_SIZE
174#define NPTX_FIFO_SIZE (4096>>2)
175#define PTX_FIFO_SIZE (1024>>2)
176#endif
177
178/* Enumeration speed */
179#define USB_HIGH_30_60MHZ (0x0<<1)
180#define USB_FULL_30_60MHZ (0x1<<1)
181#define USB_LOW_6MHZ (0x2<<1)
182#define USB_FULL_48MHZ (0x3<<1)
183
184/* S3C_UDC_OTG_GRXSTSP STATUS */
185#define OUT_PKT_RECEIVED (0x2<<17)
186#define OUT_TRANSFER_COMPLELTED (0x3<<17)
187#define SETUP_TRANSACTION_COMPLETED (0x4<<17)
188#define SETUP_PKT_RECEIVED (0x6<<17)
189#define GLOBAL_OUT_NAK (0x1<<17)
190
191/* S3C_UDC_OTG_DCTL device control register */
192#define NORMAL_OPERATION (0x1<<0)
193#define SOFT_DISCONNECT (0x1<<1)
194#define TEST_CONTROL_MASK (0x7<<4)
195#define TEST_J_MODE (0x1<<4)
196#define TEST_K_MODE (0x2<<4)
197#define TEST_SE0_NAK_MODE (0x3<<4)
198#define TEST_PACKET_MODE (0x4<<4)
199#define TEST_FORCE_ENABLE_MODE (0x5<<4)
200
201/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */
202#define DAINT_OUT_BIT (16)
203#define DAINT_MASK (0xFFFF)
204
205/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device control IN/OUT endpoint 0 control register */
206#define DEPCTL_EPENA (0x1<<31)
207#define DEPCTL_EPDIS (0x1<<30)
208#define DEPCTL_SETD1PID (0x1<<29)
209#define DEPCTL_SETD0PID (0x1<<28)
210#define DEPCTL_SNAK (0x1<<27)
211#define DEPCTL_CNAK (0x1<<26)
212#define DEPCTL_STALL (0x1<<21)
213#define DEPCTL_TYPE_BIT (18)
214#define DEPCTL_TXFNUM_BIT (22)
215#define DEPCTL_TXFNUM_MASK (0xF<<22)
216#define DEPCTL_TYPE_MASK (0x3<<18)
217#define DEPCTL_CTRL_TYPE (0x0<<18)
218#define DEPCTL_ISO_TYPE (0x1<<18)
219#define DEPCTL_BULK_TYPE (0x2<<18)
220#define DEPCTL_INTR_TYPE (0x3<<18)
221#define DEPCTL_NAKSTS (0x1<<17)
222#define DEPCTL_USBACTEP (0x1<<15)
223#define DEPCTL_NEXT_EP_BIT (11)
224#define DEPCTL_MPS_BIT (0)
225#define DEPCTL_MPS_MASK (0x7FF)
226
227#define DEPCTL0_MPS_64 (0x0<<0)
228#define DEPCTL0_MPS_32 (0x1<<0)
229#define DEPCTL0_MPS_16 (0x2<<0)
230#define DEPCTL0_MPS_8 (0x3<<0)
231#define DEPCTL_MPS_BULK_512 (512<<0)
232#define DEPCTL_MPS_INT_MPS_16 (16<<0)
233
234#define DIEPCTL0_NEXT_EP_BIT (11)
235
236/* S3C_UDC_OTG_DIEPCTLn/DOEPCTLn device control IN/OUT endpoint n control register */
237
238/* S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint common interrupt mask register */
239/* S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
240#define BACK2BACK_SETUP_RECEIVED (0x1<<6)
241#define INTKNEPMIS (0x1<<5)
242#define INTKN_TXFEMP (0x1<<4)
243#define NON_ISO_IN_EP_TIMEOUT (0x1<<3)
244#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3)
245#define AHB_ERROR (0x1<<2)
246#define EPDISBLD (0x1<<1)
247#define TRANSFER_DONE (0x1<<0)
248
249/*DIEPTSIZ0 / DOEPTSIZ0 */
250
251/* DEPTSIZ common bit */
252#define DEPTSIZ_PKT_CNT_BIT (19)
253#define DEPTSIZ_XFER_SIZE_BIT (0)
254
255#define DEPTSIZ_SETUP_PKCNT_1 (1<<29)
256#define DEPTSIZ_SETUP_PKCNT_2 (2<<29)
257#define DEPTSIZ_SETUP_PKCNT_3 (3<<29)
258
259#endif
diff --git a/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd-phy.h b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd-phy.h
new file mode 100644
index 00000000000..50d29544bcb
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-usb3-exynos-drd-phy.h
@@ -0,0 +1,75 @@
1/* arch/arm/plat-samsung/include/plat/regs-usb3-exynos-udc-drd.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co. Ltd
4 * Author: Anton Tikhomirov <av.tikhomirov@samsung.com>
5 *
6 * Exynos SuperSpeed USB 3.0 DRD Controller PHY registers
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __PLAT_SAMSUNG_REGS_USB3_EXYNOS_DRD_PHY_H
14#define __PLAT_SAMSUNG_REGS_USB3_EXYNOS_DRD_PHY_H __FILE__
15
16#define EXYNOS_USB3_PHYREG(x) ((x) + S5P_VA_SS_PHY)
17
18
19#define EXYNOS_USB3_LINKSYSTEM EXYNOS_USB3_PHYREG(0x04)
20#define EXYNOS_USB3_PHYUTMI EXYNOS_USB3_PHYREG(0x08)
21
22#define EXYNOS_USB3_PHYUTMI_OTGDISABLE (1 << 6)
23#define EXYNOS_USB3_PHYUTMI_FORCESUSPEND (1 << 1)
24#define EXYNOS_USB3_PHYUTMI_FORCESLEEP (1 << 0)
25
26#define EXYNOS_USB3_PHYPIPE EXYNOS_USB3_PHYREG(0x0C)
27
28
29#define EXYNOS_USB3_PHYCLKRST EXYNOS_USB3_PHYREG(0x10)
30
31#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL_MASK (0xff << 23)
32#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL_SHIFT (23)
33#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL_LIMIT (0xff)
34#define EXYNOS_USB3_PHYCLKRST_SSC_REF_CLK_SEL(_x) ((_x) << 23)
35
36#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
37#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE_SHIFT (21)
38#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE_LIMIT (0x03)
39#define EXYNOS_USB3_PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
40
41#define EXYNOS_USB3_PHYCLKRST_SSC_EN (1 << 20)
42#define EXYNOS_USB3_PHYCLKRST_REF_SSP_EN (1 << 19)
43#define EXYNOS_USB3_PHYCLKRST_REF_CLKDIV2 (1 << 18)
44
45#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
46#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER_SHIFT (11)
47#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER_LIMIT (0x7f)
48#define EXYNOS_USB3_PHYCLKRST_MPLL_MULTIPLIER(_x) ((_x) << 11)
49
50#define EXYNOS_USB3_PHYCLKRST_FSEL_MASK (0x3f << 5)
51#define EXYNOS_USB3_PHYCLKRST_FSEL_SHIFT (5)
52#define EXYNOS_USB3_PHYCLKRST_FSEL_LIMIT (0x3f)
53#define EXYNOS_USB3_PHYCLKRST_FSEL(_x) ((_x) << 5)
54
55#define EXYNOS_USB3_PHYCLKRST_RETENABLEN (1 << 4)
56
57#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
58#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL_SHIFT (2)
59#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL_LIMIT (0x03)
60#define EXYNOS_USB3_PHYCLKRST_REFCLKSEL(_x) ((_x) << 2)
61
62#define EXYNOS_USB3_PHYCLKRST_PORTRESET (1 << 1)
63#define EXYNOS_USB3_PHYCLKRST_COMMONONN (1 << 0)
64
65#define EXYNOS_USB3_PHYREG0 EXYNOS_USB3_PHYREG(0x14)
66#define EXYNOS_USB3_PHYREG1 EXYNOS_USB3_PHYREG(0x18)
67#define EXYNOS_USB3_PHYPARAM0 EXYNOS_USB3_PHYREG(0x1C)
68#define EXYNOS_USB3_PHYPARAM1 EXYNOS_USB3_PHYREG(0x20)
69#define EXYNOS_USB3_PHYTERM EXYNOS_USB3_PHYREG(0x24)
70#define EXYNOS_USB3_PHYTEST EXYNOS_USB3_PHYREG(0x28)
71#define EXYNOS_USB3_PHYADP EXYNOS_USB3_PHYREG(0x2C)
72#define EXYNOS_USB3_PHYBATCHG EXYNOS_USB3_PHYREG(0x30)
73#define EXYNOS_USB3_PHYRESUME EXYNOS_USB3_PHYREG(0x34)
74#define EXYNOS_USB3_LINKPORT EXYNOS_USB3_PHYREG(0x44)
75#endif /* __PLAT_SAMSUNG_REGS_USB3_EXYNOS_DRD_PHY_H */
diff --git a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
index 81074421312..ee155ad45ca 100644
--- a/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/s3c-dma-pl330.h
@@ -84,6 +84,23 @@ enum dma_ch {
84 DMACH_SLIMBUS4_TX, 84 DMACH_SLIMBUS4_TX,
85 DMACH_SLIMBUS5_RX, 85 DMACH_SLIMBUS5_RX,
86 DMACH_SLIMBUS5_TX, 86 DMACH_SLIMBUS5_TX,
87 DMACH_MIPI_HSI0,
88 DMACH_MIPI_HSI1,
89 DMACH_MIPI_HSI2,
90 DMACH_MIPI_HSI3,
91 DMACH_MIPI_HSI4,
92 DMACH_MIPI_HSI5,
93 DMACH_MIPI_HSI6,
94 DMACH_MIPI_HSI7,
95 DMACH_DISP1,
96 DMACH_MTOM_0,
97 DMACH_MTOM_1,
98 DMACH_MTOM_2,
99 DMACH_MTOM_3,
100 DMACH_MTOM_4,
101 DMACH_MTOM_5,
102 DMACH_MTOM_6,
103 DMACH_MTOM_7,
87 /* END Marker, also used to denote a reserved channel */ 104 /* END Marker, also used to denote a reserved channel */
88 DMACH_MAX, 105 DMACH_MAX,
89}; 106};
@@ -93,6 +110,11 @@ static inline bool s3c_dma_has_circular(void)
93 return true; 110 return true;
94} 111}
95 112
113static inline bool s3c_dma_has_infiniteloop(void)
114{
115 return true;
116}
117
96#include <plat/dma.h> 118#include <plat/dma.h>
97 119
98#endif /* __S3C_DMA_PL330_H_ */ 120#endif /* __S3C_DMA_PL330_H_ */
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index 4c16fa3621b..353ceb6c86c 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -71,5 +71,6 @@ extern void s3c64xx_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
71extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 71extern void s5pc100_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
72extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 72extern void s5pv210_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
73extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs); 73extern void s5p64x0_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
74extern void exynos_spi_set_info(int cntrlr, int src_clk_nr, int num_cs);
74 75
75#endif /* __S3C64XX_PLAT_SPI_H */ 76#endif /* __S3C64XX_PLAT_SPI_H */
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 058e09654fe..448abea9b95 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -18,6 +18,8 @@
18#ifndef __PLAT_S3C_SDHCI_H 18#ifndef __PLAT_S3C_SDHCI_H
19#define __PLAT_S3C_SDHCI_H __FILE__ 19#define __PLAT_S3C_SDHCI_H __FILE__
20 20
21/* ignore mmc suspend/resume for BCM WIFI */
22#define S3C_SDHCI_PM_IGNORE_SUSPEND_RESUME (1 << 30)
21struct platform_device; 23struct platform_device;
22struct mmc_host; 24struct mmc_host;
23struct mmc_card; 25struct mmc_card;
@@ -72,8 +74,11 @@ struct s3c_sdhci_platdata {
72 74
73 char **clocks; /* set of clock sources */ 75 char **clocks; /* set of clock sources */
74 76
77 char *vmmc_name; /* name for regulator */
75 int ext_cd_gpio; 78 int ext_cd_gpio;
76 bool ext_cd_gpio_invert; 79 bool ext_cd_gpio_invert;
80 unsigned int pm_flags;
81
77 int (*ext_cd_init)(void (*notify_func)(struct platform_device *, 82 int (*ext_cd_init)(void (*notify_func)(struct platform_device *,
78 int state)); 83 int state));
79 int (*ext_cd_cleanup)(void (*notify_func)(struct platform_device *, 84 int (*ext_cd_cleanup)(void (*notify_func)(struct platform_device *,
@@ -84,6 +89,10 @@ struct s3c_sdhci_platdata {
84 void __iomem *regbase, 89 void __iomem *regbase,
85 struct mmc_ios *ios, 90 struct mmc_ios *ios,
86 struct mmc_card *card); 91 struct mmc_card *card);
92#ifdef CONFIG_MACH_PX
93 int (*ext_pdev)(struct platform_device *dev_id);
94#endif
95
87}; 96};
88 97
89/** 98/**
@@ -126,6 +135,10 @@ extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
126extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 135extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
127extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w); 136extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
128extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w); 137extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
138extern void exynos5_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
139extern void exynos5_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
140extern void exynos5_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
141extern void exynos5_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
129 142
130/* S3C2416 SDHCI setup */ 143/* S3C2416 SDHCI setup */
131 144
@@ -390,4 +403,62 @@ static inline void exynos4_default_sdhci3(void) { }
390 403
391#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */ 404#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
392 405
406extern void mmc_force_presence_change(struct platform_device *pdev);
407
408/* EXYNOS5 SDHCI setup */
409#ifdef CONFIG_EXYNOS4_SETUP_SDHCI
410extern char *exynos4_hsmmc_clksrcs[4];
411
412extern void exynos4_setup_sdhci_cfg_card(struct platform_device *dev,
413 void __iomem *r,
414 struct mmc_ios *ios,
415 struct mmc_card *card);
416
417static inline void exynos5_default_sdhci0(void)
418{
419#ifdef CONFIG_S3C_DEV_HSMMC
420 s3c_hsmmc0_def_platdata.clocks = exynos4_hsmmc_clksrcs;
421 s3c_hsmmc0_def_platdata.cfg_gpio = exynos5_setup_sdhci0_cfg_gpio;
422 s3c_hsmmc0_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
423#endif
424}
425
426static inline void exynos5_default_sdhci1(void)
427{
428#ifdef CONFIG_S3C_DEV_HSMMC1
429 s3c_hsmmc1_def_platdata.clocks = exynos4_hsmmc_clksrcs;
430 s3c_hsmmc1_def_platdata.cfg_gpio = exynos5_setup_sdhci1_cfg_gpio;
431 s3c_hsmmc1_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
432#endif
433}
434
435static inline void exynos5_default_sdhci2(void)
436{
437#ifdef CONFIG_S3C_DEV_HSMMC2
438 s3c_hsmmc2_def_platdata.clocks = exynos4_hsmmc_clksrcs;
439 s3c_hsmmc2_def_platdata.cfg_gpio = exynos5_setup_sdhci2_cfg_gpio;
440 s3c_hsmmc2_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
441#endif
442}
443
444static inline void exynos5_default_sdhci3(void)
445{
446#ifdef CONFIG_S3C_DEV_HSMMC3
447 s3c_hsmmc3_def_platdata.clocks = exynos4_hsmmc_clksrcs;
448 s3c_hsmmc3_def_platdata.cfg_gpio = exynos5_setup_sdhci3_cfg_gpio;
449 s3c_hsmmc3_def_platdata.cfg_card = exynos4_setup_sdhci_cfg_card;
450#endif
451}
452
453#else
454static inline void exynos5_default_sdhci0(void) { }
455static inline void exynos5_default_sdhci1(void) { }
456static inline void exynos5_default_sdhci2(void) { }
457static inline void exynos5_default_sdhci3(void) { }
458
459#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
460
461// Hardkernel / ODROID
462extern void sdhci_s3c_force_presence_change(struct platform_device *pdev, int);
463
393#endif /* __PLAT_S3C_SDHCI_H */ 464#endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/plat-samsung/include/plat/ts.h b/arch/arm/plat-samsung/include/plat/ts.h
index 26fdb22e0fc..3fb52b99f28 100644
--- a/arch/arm/plat-samsung/include/plat/ts.h
+++ b/arch/arm/plat-samsung/include/plat/ts.h
@@ -14,10 +14,16 @@ struct s3c2410_ts_mach_info {
14 int delay; 14 int delay;
15 int presc; 15 int presc;
16 int oversampling_shift; 16 int oversampling_shift;
17
18 int cal_x_max;
19 int cal_y_max;
20 int cal_param[7];
21
17 void (*cfg_gpio)(struct platform_device *dev); 22 void (*cfg_gpio)(struct platform_device *dev);
18}; 23};
19 24
20extern void s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *); 25extern void s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *);
26extern void s3c24xx_ts1_set_platdata(struct s3c2410_ts_mach_info *);
21 27
22/* defined by architecture to configure gpio */ 28/* defined by architecture to configure gpio */
23extern void s3c24xx_ts_cfg_gpio(struct platform_device *dev); 29extern void s3c24xx_ts_cfg_gpio(struct platform_device *dev);
diff --git a/arch/arm/plat-samsung/include/plat/tv-core.h b/arch/arm/plat-samsung/include/plat/tv-core.h
new file mode 100644
index 00000000000..d647eeceb60
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/tv-core.h
@@ -0,0 +1,37 @@
1/*
2 * arch/arm/plat-samsung/include/plat/tv.h
3 *
4 * Copyright 2011 Samsung Electronics Co., Ltd.
5 * Tomasz Stanislawski <t.stanislaws@samsung.com>
6 *
7 * Samsung TV driver core functions
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __SAMSUNG_PLAT_TV_H
15#define __SAMSUNG_PLAT_TV_H __FILE__
16
17/*
18 * These functions are only for use with the core support code, such as
19 * the CPU-specific initialization code.
20 */
21
22/* Re-define device name to differentiate the subsystem in various SoCs. */
23static inline void s5p_hdmi_setname(char *name)
24{
25#ifdef CONFIG_S5P_DEV_TV
26 s5p_device_hdmi.name = name;
27#endif
28}
29
30static inline void s5p_mixer_setname(char *name)
31{
32#ifdef CONFIG_S5P_DEV_TV
33 s5p_device_mixer.name = name;
34#endif
35}
36
37#endif /* __SAMSUNG_PLAT_TV_H */
diff --git a/arch/arm/plat-samsung/include/plat/watchdog-reset.h b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
index 54b762acb5a..4dc5adf0a23 100644
--- a/arch/arm/plat-samsung/include/plat/watchdog-reset.h
+++ b/arch/arm/plat-samsung/include/plat/watchdog-reset.h
@@ -10,26 +10,24 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13#include <plat/clock.h>
13#include <plat/regs-watchdog.h> 14#include <plat/regs-watchdog.h>
14#include <mach/map.h> 15#include <mach/map.h>
15 16
17#include <linux/kernel.h>
16#include <linux/clk.h> 18#include <linux/clk.h>
19#include <linux/delay.h>
17#include <linux/err.h> 20#include <linux/err.h>
18#include <linux/io.h> 21#include <linux/io.h>
19 22
20static inline void arch_wdt_reset(void) 23static inline void arch_wdt_reset(void)
21{ 24{
22 struct clk *wdtclk;
23
24 printk("arch_reset: attempting watchdog reset\n"); 25 printk("arch_reset: attempting watchdog reset\n");
25 26
26 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */ 27 __raw_writel(0, S3C2410_WTCON); /* disable watchdog, to be safe */
27 28
28 wdtclk = clk_get(NULL, "watchdog"); 29 if (s3c2410_wdtclk)
29 if (!IS_ERR(wdtclk)) { 30 clk_enable(s3c2410_wdtclk);
30 clk_enable(wdtclk);
31 } else
32 printk(KERN_WARNING "%s: warning: cannot get watchdog clock\n", __func__);
33 31
34 /* put initial values into count and data */ 32 /* put initial values into count and data */
35 __raw_writel(0x80, S3C2410_WTCNT); 33 __raw_writel(0x80, S3C2410_WTCNT);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-15 21:51:32 -0400