1 files changed, 259 insertions, 0 deletions
diff --git a/arch/arm/plat-samsung/include/plat/regs-otg.h b/arch/arm/plat-samsung/include/plat/regs-otg.h
new file mode 100644
index 00000000000..cf01506301c
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-otg.h
@@ -0,0 +1,259 @@
+/* linux/arch/arm/plat-samsung/include/plat/regs-otg.h
+ *
+ * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
+ *
+ * This include file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+*/
+#ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
+#define __ASM_ARCH_REGS_USB_OTG_HS_H
+/* USB2.0 OTG Controller register */
+#define S3C_USBOTG_PHYREG(x)            ((x) + S3C_VA_HSPHY)
+#define S3C_USBOTG_PHYPWR               S3C_USBOTG_PHYREG(0x0)
+#define S3C_USBOTG_PHYCLK               S3C_USBOTG_PHYREG(0x4)
+#define S3C_USBOTG_RSTCON               S3C_USBOTG_PHYREG(0x8)
+#define S3C_USBOTG_PHY1CON              S3C_USBOTG_PHYREG(0x34)
+/* USB2.0 OTG Controller register */
+#define S3C_USBOTGREG(x) (x)
+/*============================================================================================== */
+        /* Core Global Registers */
+#define S3C_UDC_OTG_GOTGCTL             S3C_USBOTGREG(0x000)            /* OTG Control & Status */
+#define S3C_UDC_OTG_GOTGINT             S3C_USBOTGREG(0x004)            /* OTG Interrupt */
+#define S3C_UDC_OTG_GAHBCFG             S3C_USBOTGREG(0x008)            /* Core AHB Configuration */
+#define S3C_UDC_OTG_GUSBCFG             S3C_USBOTGREG(0x00C)            /* Core USB Configuration */
+#define S3C_UDC_OTG_GRSTCTL             S3C_USBOTGREG(0x010)            /* Core Reset */
+#define S3C_UDC_OTG_GINTSTS             S3C_USBOTGREG(0x014)            /* Core Interrupt */
+#define S3C_UDC_OTG_GINTMSK             S3C_USBOTGREG(0x018)            /* Core Interrupt Mask */
+#define S3C_UDC_OTG_GRXSTSR             S3C_USBOTGREG(0x01C)            /* Receive Status Debug Read/Status Read */
+#define S3C_UDC_OTG_GRXSTSP             S3C_USBOTGREG(0x020)            /* Receive Status Debug Pop/Status Pop */
+#define S3C_UDC_OTG_GRXFSIZ             S3C_USBOTGREG(0x024)            /* Receive FIFO Size */
+#define S3C_UDC_OTG_GNPTXFSIZ           S3C_USBOTGREG(0x028)            /* Non-Periodic Transmit FIFO Size */
+#define S3C_UDC_OTG_GNPTXSTS            S3C_USBOTGREG(0x02C)            /* Non-Periodic Transmit FIFO/Queue Status */
+#define S3C_UDC_OTG_HPTXFSIZ            S3C_USBOTGREG(0x100)            /* Host Periodic Transmit FIFO Size */
+#define S3C_UDC_OTG_DIEPTXF(n)          S3C_USBOTGREG(0x104 + (n-1)*0x4)/* Device IN EP Transmit FIFO Size Register */
+/*============================================================================================== */
+/* Host Mode Registers */
+/*------------------------------------------------ */
+/* Host Global Registers */
+#define S3C_UDC_OTG_HCFG                S3C_USBOTGREG(0x400)            /* Host Configuration */
+#define S3C_UDC_OTG_HFIR                S3C_USBOTGREG(0x404)            /* Host Frame Interval */
+#define S3C_UDC_OTG_HFNUM               S3C_USBOTGREG(0x408)            /* Host Frame Number/Frame Time Remaining */
+#define S3C_UDC_OTG_HPTXSTS             S3C_USBOTGREG(0x410)            /* Host Periodic Transmit FIFO/Queue Status */
+#define S3C_UDC_OTG_HAINT               S3C_USBOTGREG(0x414)            /* Host All Channels Interrupt */
+#define S3C_UDC_OTG_HAINTMSK            S3C_USBOTGREG(0x418)            /* Host All Channels Interrupt Mask */
+/*------------------------------------------------ */
+/* Host Port Control & Status Registers */
+#define S3C_UDC_OTG_HPRT                S3C_USBOTGREG(0x440)            /* Host Port Control & Status */
+/*------------------------------------------------ */
+/* Host Channel-Specific Registers */
+#define S3C_UDC_OTG_HCCHAR0             S3C_USBOTGREG(0x500)            /* Host Channel-0 Characteristics */
+#define S3C_UDC_OTG_HCSPLT0             S3C_USBOTGREG(0x504)            /* Host Channel-0 Split Control */
+#define S3C_UDC_OTG_HCINT0              S3C_USBOTGREG(0x508)            /* Host Channel-0 Interrupt */
+#define S3C_UDC_OTG_HCINTMSK0           S3C_USBOTGREG(0x50C)            /* Host Channel-0 Interrupt Mask */
+#define S3C_UDC_OTG_HCTSIZ0             S3C_USBOTGREG(0x510)            /* Host Channel-0 Transfer Size */
+#define S3C_UDC_OTG_HCDMA0              S3C_USBOTGREG(0x514)            /* Host Channel-0 DMA Address */
+/*============================================================================================== */
+/* Device Mode Registers */
+/*------------------------------------------------ */
+/* Device Global Registers */
+#define S3C_UDC_OTG_DCFG                S3C_USBOTGREG(0x800)            /* Device Configuration */
+#define S3C_UDC_OTG_DCTL                S3C_USBOTGREG(0x804)            /* Device Control */
+#define S3C_UDC_OTG_DSTS                S3C_USBOTGREG(0x808)            /* Device Status */
+#define S3C_UDC_OTG_DIEPMSK             S3C_USBOTGREG(0x810)            /* Device IN Endpoint Common Interrupt Mask */
+#define S3C_UDC_OTG_DOEPMSK             S3C_USBOTGREG(0x814)            /* Device OUT Endpoint Common Interrupt Mask */
+#define S3C_UDC_OTG_DAINT               S3C_USBOTGREG(0x818)            /* Device All Endpoints Interrupt */
+#define S3C_UDC_OTG_DAINTMSK            S3C_USBOTGREG(0x81C)            /* Device All Endpoints Interrupt Mask */
+#define S3C_UDC_OTG_DTKNQR1             S3C_USBOTGREG(0x820)            /* Device IN Token Sequence Learning Queue Read 1 */
+#define S3C_UDC_OTG_DTKNQR2             S3C_USBOTGREG(0x824)            /* Device IN Token Sequence Learning Queue Read 2 */
+#define S3C_UDC_OTG_DVBUSDIS            S3C_USBOTGREG(0x828)            /* Device VBUS Discharge Time */
+#define S3C_UDC_OTG_DVBUSPULSE          S3C_USBOTGREG(0x82C)            /* Device VBUS Pulsing Time */
+#define S3C_UDC_OTG_DTKNQR3             S3C_USBOTGREG(0x830)            /* Device IN Token Sequence Learning Queue Read 3 */
+#define S3C_UDC_OTG_DTKNQR4             S3C_USBOTGREG(0x834)            /* Device IN Token Sequence Learning Queue Read 4 */
+/*------------------------------------------------ */
+/* Device Logical IN Endpoint-Specific Registers */
+#define S3C_UDC_OTG_DIEPCTL(n)          S3C_USBOTGREG(0x900 + n*0x20)   /* Device IN Endpoint n Control */
+#define S3C_UDC_OTG_DIEPINT(n)          S3C_USBOTGREG(0x908 + n*0x20)   /* Device IN Endpoint n Interrupt */
+#define S3C_UDC_OTG_DIEPTSIZ(n)         S3C_USBOTGREG(0x910 + n*0x20)   /* Device IN Endpoint n Transfer Size */
+#define S3C_UDC_OTG_DIEPDMA(n)          S3C_USBOTGREG(0x914 + n*0x20)   /* Device IN Endpoint n DMA Address */
+/*------------------------------------------------ */
+/* Device Logical OUT Endpoint-Specific Registers */
+#define S3C_UDC_OTG_DOEPCTL(n)          S3C_USBOTGREG(0xB00 + n*0x20)   /* Device OUT Endpoint n Control */
+#define S3C_UDC_OTG_DOEPINT(n)          S3C_USBOTGREG(0xB08 + n*0x20)   /* Device OUT Endpoint n Interrupt */
+#define S3C_UDC_OTG_DOEPTSIZ(n)         S3C_USBOTGREG(0xB10 + n*0x20)   /* Device OUT Endpoint n Transfer Size */
+#define S3C_UDC_OTG_DOEPDMA(n)          S3C_USBOTGREG(0xB14 + n*0x20)   /* Device OUT Endpoint n DMA Address */
+/*------------------------------------------------ */
+/* Endpoint FIFO address */
+#define S3C_UDC_OTG_EP0_FIFO            S3C_USBOTGREG(0x1000)
+#define S3C_UDC_OTG_EP1_FIFO            S3C_USBOTGREG(0x2000)
+#define S3C_UDC_OTG_EP2_FIFO            S3C_USBOTGREG(0x3000)
+#define S3C_UDC_OTG_EP3_FIFO            S3C_USBOTGREG(0x4000)
+#define S3C_UDC_OTG_EP4_FIFO            S3C_USBOTGREG(0x5000)
+#define S3C_UDC_OTG_EP5_FIFO            S3C_USBOTGREG(0x6000)
+#define S3C_UDC_OTG_EP6_FIFO            S3C_USBOTGREG(0x7000)
+#define S3C_UDC_OTG_EP7_FIFO            S3C_USBOTGREG(0x8000)
+#define S3C_UDC_OTG_EP8_FIFO            S3C_USBOTGREG(0x9000)
+#define S3C_UDC_OTG_EP9_FIFO            S3C_USBOTGREG(0xA000)
+#define S3C_UDC_OTG_EP10_FIFO           S3C_USBOTGREG(0xB000)
+#define S3C_UDC_OTG_EP11_FIFO           S3C_USBOTGREG(0xC000)
+#define S3C_UDC_OTG_EP12_FIFO           S3C_USBOTGREG(0xD000)
+#define S3C_UDC_OTG_EP13_FIFO           S3C_USBOTGREG(0xE000)
+#define S3C_UDC_OTG_EP14_FIFO           S3C_USBOTGREG(0xF000)
+#define S3C_UDC_OTG_EP15_FIFO           S3C_USBOTGREG(0x10000)
+/*===================================================================== */
+/*definitions related to CSR setting */
+/* S3C_UDC_OTG_GOTGCTL */
+#define B_SESSION_VALID                 (0x1<<19)
+#define A_SESSION_VALID                 (0x1<<18)
+/* S3C_UDC_OTG_GAHBCFG */
+#define PTXFE_HALF                      (0<<8)
+#define PTXFE_ZERO                      (1<<8)
+#define NPTXFE_HALF                     (0<<7)
+#define NPTXFE_ZERO                     (1<<7)
+#define MODE_SLAVE                      (0<<5)
+#define MODE_DMA                        (1<<5)
+#define BURST_SINGLE                    (0<<1)
+#define BURST_INCR                      (1<<1)
+#define BURST_INCR4                     (3<<1)
+#define BURST_INCR8                     (5<<1)
+#define BURST_INCR16                    (7<<1)
+#define GBL_INT_UNMASK                  (1<<0)
+#define GBL_INT_MASK                    (0<<0)
+/* S3C_UDC_OTG_GRSTCTL */
+#define AHB_MASTER_IDLE                 (1u<<31)
+#define CORE_SOFT_RESET                 (0x1<<0)
+/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */
+#define INT_RESUME                      (1u<<31)
+#define INT_DISCONN                     (0x1<<29)
+#define INT_CONN_ID_STS_CNG             (0x1<<28)
+#define INT_OUT_EP                      (0x1<<19)
+#define INT_IN_EP                       (0x1<<18)
+#define INT_ENUMDONE                    (0x1<<13)
+#define INT_RESET                       (0x1<<12)
+#define INT_SUSPEND                     (0x1<<11)
+#define INT_EARLY_SUSPEND               (0x1<<10)
+#define INT_NP_TX_FIFO_EMPTY            (0x1<<5)
+#define INT_RX_FIFO_NOT_EMPTY           (0x1<<4)
+#define INT_SOF                         (0x1<<3)
+#define INT_DEV_MODE                    (0x0<<0)
+#define INT_HOST_MODE                   (0x1<<1)
+#define INT_GOUTNakEff                  (0x01<<7)
+#define INT_GINNakEff                   (0x01<<6)
+#define FULL_SPEED_CONTROL_PKT_SIZE     8
+#define FULL_SPEED_BULK_PKT_SIZE        64
+#define HIGH_SPEED_CONTROL_PKT_SIZE     64
+#define HIGH_SPEED_BULK_PKT_SIZE        512
+#ifdef CONFIG_CPU_S5P6450
+#define RX_FIFO_SIZE                    (4096>>2)
+#define NPTX_FIFO_START_ADDR            RX_FIFO_SIZE
+#define NPTX_FIFO_SIZE                  (4096>>2)
+#define PTX_FIFO_SIZE                   (1520>>2)
+#else
+#define RX_FIFO_SIZE                    (4096>>2)
+#define NPTX_FIFO_START_ADDR            RX_FIFO_SIZE
+#define NPTX_FIFO_SIZE                  (4096>>2)
+#define PTX_FIFO_SIZE                   (1024>>2)
+#endif
+/* Enumeration speed */
+#define USB_HIGH_30_60MHZ               (0x0<<1)
+#define USB_FULL_30_60MHZ               (0x1<<1)
+#define USB_LOW_6MHZ                    (0x2<<1)
+#define USB_FULL_48MHZ                  (0x3<<1)
+/* S3C_UDC_OTG_GRXSTSP STATUS */
+#define OUT_PKT_RECEIVED                (0x2<<17)
+#define OUT_TRANSFER_COMPLELTED         (0x3<<17)
+#define SETUP_TRANSACTION_COMPLETED     (0x4<<17)
+#define SETUP_PKT_RECEIVED              (0x6<<17)
+#define GLOBAL_OUT_NAK                  (0x1<<17)
+/* S3C_UDC_OTG_DCTL device control register */
+#define NORMAL_OPERATION                (0x1<<0)
+#define SOFT_DISCONNECT                 (0x1<<1)
+#define TEST_CONTROL_MASK               (0x7<<4)
+#define TEST_J_MODE                     (0x1<<4)
+#define TEST_K_MODE                     (0x2<<4)
+#define TEST_SE0_NAK_MODE               (0x3<<4)
+#define TEST_PACKET_MODE                (0x4<<4)
+#define TEST_FORCE_ENABLE_MODE          (0x5<<4)
+/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */
+#define DAINT_OUT_BIT                   (16)
+#define DAINT_MASK                      (0xFFFF)
+/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device control IN/OUT endpoint 0 control register */
+#define DEPCTL_EPENA                    (0x1<<31)
+#define DEPCTL_EPDIS                    (0x1<<30)
+#define DEPCTL_SETD1PID                 (0x1<<29)
+#define DEPCTL_SETD0PID                 (0x1<<28)
+#define DEPCTL_SNAK                     (0x1<<27)
+#define DEPCTL_CNAK                     (0x1<<26)
+#define DEPCTL_STALL                    (0x1<<21)
+#define DEPCTL_TYPE_BIT                 (18)
+#define DEPCTL_TXFNUM_BIT               (22)
+#define DEPCTL_TXFNUM_MASK              (0xF<<22)
+#define DEPCTL_TYPE_MASK                (0x3<<18)
+#define DEPCTL_CTRL_TYPE                (0x0<<18)
+#define DEPCTL_ISO_TYPE                 (0x1<<18)
+#define DEPCTL_BULK_TYPE                (0x2<<18)
+#define DEPCTL_INTR_TYPE                (0x3<<18)
+#define DEPCTL_NAKSTS                   (0x1<<17)
+#define DEPCTL_USBACTEP                 (0x1<<15)
+#define DEPCTL_NEXT_EP_BIT              (11)
+#define DEPCTL_MPS_BIT                  (0)
+#define DEPCTL_MPS_MASK                 (0x7FF)
+#define DEPCTL0_MPS_64                  (0x0<<0)
+#define DEPCTL0_MPS_32                  (0x1<<0)
+#define DEPCTL0_MPS_16                  (0x2<<0)
+#define DEPCTL0_MPS_8                   (0x3<<0)
+#define DEPCTL_MPS_BULK_512             (512<<0)
+#define DEPCTL_MPS_INT_MPS_16           (16<<0)
+#define DIEPCTL0_NEXT_EP_BIT            (11)
+/* S3C_UDC_OTG_DIEPCTLn/DOEPCTLn device control IN/OUT endpoint n control register */
+/* S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint common interrupt mask register */
+/* S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
+#define BACK2BACK_SETUP_RECEIVED        (0x1<<6)
+#define INTKNEPMIS                      (0x1<<5)
+#define INTKN_TXFEMP                    (0x1<<4)
+#define NON_ISO_IN_EP_TIMEOUT           (0x1<<3)
+#define CTRL_OUT_EP_SETUP_PHASE_DONE    (0x1<<3)
+#define AHB_ERROR                       (0x1<<2)
+#define EPDISBLD                        (0x1<<1)
+#define TRANSFER_DONE                   (0x1<<0)
+/*DIEPTSIZ0 / DOEPTSIZ0 */
+/* DEPTSIZ common bit */
+#define DEPTSIZ_PKT_CNT_BIT             (19)
+#define DEPTSIZ_XFER_SIZE_BIT           (0)
+#define DEPTSIZ_SETUP_PKCNT_1           (1<<29)
+#define DEPTSIZ_SETUP_PKCNT_2           (2<<29)
+#define DEPTSIZ_SETUP_PKCNT_3           (3<<29)
+#endif

diff --git a/arch/arm/plat-samsung/include/plat/regs-otg.h b/arch/arm/plat-samsung/include/plat/regs-otg.h new file mode 100644 index 00000000000..cf01506301c --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/regs-otg.h
@@ -0,0 +1,259 @@
	1	/* linux/arch/arm/plat-samsung/include/plat/regs-otg.h
	2	*
	3	* Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
	4	*
	5	* This include file is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License as
	7	* published by the Free Software Foundation; either version 2 of
	8	* the License, or (at your option) any later version.
	9	*/
	10
	11	#ifndef __ASM_ARCH_REGS_USB_OTG_HS_H
	12	#define __ASM_ARCH_REGS_USB_OTG_HS_H
	13
	14	/* USB2.0 OTG Controller register */
	15	#define S3C_USBOTG_PHYREG(x) ((x) + S3C_VA_HSPHY)
	16	#define S3C_USBOTG_PHYPWR S3C_USBOTG_PHYREG(0x0)
	17	#define S3C_USBOTG_PHYCLK S3C_USBOTG_PHYREG(0x4)
	18	#define S3C_USBOTG_RSTCON S3C_USBOTG_PHYREG(0x8)
	19	#define S3C_USBOTG_PHY1CON S3C_USBOTG_PHYREG(0x34)
	20
	21	/* USB2.0 OTG Controller register */
	22	#define S3C_USBOTGREG(x) (x)
	23	/============================================================================================== /
	24	/* Core Global Registers */
	25	#define S3C_UDC_OTG_GOTGCTL S3C_USBOTGREG(0x000) /* OTG Control & Status */
	26	#define S3C_UDC_OTG_GOTGINT S3C_USBOTGREG(0x004) /* OTG Interrupt */
	27	#define S3C_UDC_OTG_GAHBCFG S3C_USBOTGREG(0x008) /* Core AHB Configuration */
	28	#define S3C_UDC_OTG_GUSBCFG S3C_USBOTGREG(0x00C) /* Core USB Configuration */
	29	#define S3C_UDC_OTG_GRSTCTL S3C_USBOTGREG(0x010) /* Core Reset */
	30	#define S3C_UDC_OTG_GINTSTS S3C_USBOTGREG(0x014) /* Core Interrupt */
	31	#define S3C_UDC_OTG_GINTMSK S3C_USBOTGREG(0x018) /* Core Interrupt Mask */
	32	#define S3C_UDC_OTG_GRXSTSR S3C_USBOTGREG(0x01C) /* Receive Status Debug Read/Status Read */
	33	#define S3C_UDC_OTG_GRXSTSP S3C_USBOTGREG(0x020) /* Receive Status Debug Pop/Status Pop */
	34	#define S3C_UDC_OTG_GRXFSIZ S3C_USBOTGREG(0x024) /* Receive FIFO Size */
	35	#define S3C_UDC_OTG_GNPTXFSIZ S3C_USBOTGREG(0x028) /* Non-Periodic Transmit FIFO Size */
	36	#define S3C_UDC_OTG_GNPTXSTS S3C_USBOTGREG(0x02C) /* Non-Periodic Transmit FIFO/Queue Status */
	37
	38	#define S3C_UDC_OTG_HPTXFSIZ S3C_USBOTGREG(0x100) /* Host Periodic Transmit FIFO Size */
	39	#define S3C_UDC_OTG_DIEPTXF(n) S3C_USBOTGREG(0x104 + (n-1)0x4)/ Device IN EP Transmit FIFO Size Register */
	40
	41	/============================================================================================== /
	42	/* Host Mode Registers */
	43	/------------------------------------------------ /
	44	/* Host Global Registers */
	45	#define S3C_UDC_OTG_HCFG S3C_USBOTGREG(0x400) /* Host Configuration */
	46	#define S3C_UDC_OTG_HFIR S3C_USBOTGREG(0x404) /* Host Frame Interval */
	47	#define S3C_UDC_OTG_HFNUM S3C_USBOTGREG(0x408) /* Host Frame Number/Frame Time Remaining */
	48	#define S3C_UDC_OTG_HPTXSTS S3C_USBOTGREG(0x410) /* Host Periodic Transmit FIFO/Queue Status */
	49	#define S3C_UDC_OTG_HAINT S3C_USBOTGREG(0x414) /* Host All Channels Interrupt */
	50	#define S3C_UDC_OTG_HAINTMSK S3C_USBOTGREG(0x418) /* Host All Channels Interrupt Mask */
	51
	52	/------------------------------------------------ /
	53	/* Host Port Control & Status Registers */
	54	#define S3C_UDC_OTG_HPRT S3C_USBOTGREG(0x440) /* Host Port Control & Status */
	55
	56	/------------------------------------------------ /
	57	/* Host Channel-Specific Registers */
	58	#define S3C_UDC_OTG_HCCHAR0 S3C_USBOTGREG(0x500) /* Host Channel-0 Characteristics */
	59	#define S3C_UDC_OTG_HCSPLT0 S3C_USBOTGREG(0x504) /* Host Channel-0 Split Control */
	60	#define S3C_UDC_OTG_HCINT0 S3C_USBOTGREG(0x508) /* Host Channel-0 Interrupt */
	61	#define S3C_UDC_OTG_HCINTMSK0 S3C_USBOTGREG(0x50C) /* Host Channel-0 Interrupt Mask */
	62	#define S3C_UDC_OTG_HCTSIZ0 S3C_USBOTGREG(0x510) /* Host Channel-0 Transfer Size */
	63	#define S3C_UDC_OTG_HCDMA0 S3C_USBOTGREG(0x514) /* Host Channel-0 DMA Address */
	64
	65	/============================================================================================== /
	66	/* Device Mode Registers */
	67	/------------------------------------------------ /
	68	/* Device Global Registers */
	69	#define S3C_UDC_OTG_DCFG S3C_USBOTGREG(0x800) /* Device Configuration */
	70	#define S3C_UDC_OTG_DCTL S3C_USBOTGREG(0x804) /* Device Control */
	71	#define S3C_UDC_OTG_DSTS S3C_USBOTGREG(0x808) /* Device Status */
	72	#define S3C_UDC_OTG_DIEPMSK S3C_USBOTGREG(0x810) /* Device IN Endpoint Common Interrupt Mask */
	73	#define S3C_UDC_OTG_DOEPMSK S3C_USBOTGREG(0x814) /* Device OUT Endpoint Common Interrupt Mask */
	74	#define S3C_UDC_OTG_DAINT S3C_USBOTGREG(0x818) /* Device All Endpoints Interrupt */
	75	#define S3C_UDC_OTG_DAINTMSK S3C_USBOTGREG(0x81C) /* Device All Endpoints Interrupt Mask */
	76	#define S3C_UDC_OTG_DTKNQR1 S3C_USBOTGREG(0x820) /* Device IN Token Sequence Learning Queue Read 1 */
	77	#define S3C_UDC_OTG_DTKNQR2 S3C_USBOTGREG(0x824) /* Device IN Token Sequence Learning Queue Read 2 */
	78	#define S3C_UDC_OTG_DVBUSDIS S3C_USBOTGREG(0x828) /* Device VBUS Discharge Time */
	79	#define S3C_UDC_OTG_DVBUSPULSE S3C_USBOTGREG(0x82C) /* Device VBUS Pulsing Time */
	80	#define S3C_UDC_OTG_DTKNQR3 S3C_USBOTGREG(0x830) /* Device IN Token Sequence Learning Queue Read 3 */
	81	#define S3C_UDC_OTG_DTKNQR4 S3C_USBOTGREG(0x834) /* Device IN Token Sequence Learning Queue Read 4 */
	82
	83	/------------------------------------------------ /
	84	/* Device Logical IN Endpoint-Specific Registers */
	85	#define S3C_UDC_OTG_DIEPCTL(n) S3C_USBOTGREG(0x900 + n0x20) / Device IN Endpoint n Control */
	86	#define S3C_UDC_OTG_DIEPINT(n) S3C_USBOTGREG(0x908 + n0x20) / Device IN Endpoint n Interrupt */
	87	#define S3C_UDC_OTG_DIEPTSIZ(n) S3C_USBOTGREG(0x910 + n0x20) / Device IN Endpoint n Transfer Size */
	88	#define S3C_UDC_OTG_DIEPDMA(n) S3C_USBOTGREG(0x914 + n0x20) / Device IN Endpoint n DMA Address */
	89
	90	/------------------------------------------------ /
	91	/* Device Logical OUT Endpoint-Specific Registers */
	92	#define S3C_UDC_OTG_DOEPCTL(n) S3C_USBOTGREG(0xB00 + n0x20) / Device OUT Endpoint n Control */
	93	#define S3C_UDC_OTG_DOEPINT(n) S3C_USBOTGREG(0xB08 + n0x20) / Device OUT Endpoint n Interrupt */
	94	#define S3C_UDC_OTG_DOEPTSIZ(n) S3C_USBOTGREG(0xB10 + n0x20) / Device OUT Endpoint n Transfer Size */
	95	#define S3C_UDC_OTG_DOEPDMA(n) S3C_USBOTGREG(0xB14 + n0x20) / Device OUT Endpoint n DMA Address */
	96
	97	/------------------------------------------------ /
	98	/* Endpoint FIFO address */
	99	#define S3C_UDC_OTG_EP0_FIFO S3C_USBOTGREG(0x1000)
	100	#define S3C_UDC_OTG_EP1_FIFO S3C_USBOTGREG(0x2000)
	101	#define S3C_UDC_OTG_EP2_FIFO S3C_USBOTGREG(0x3000)
	102	#define S3C_UDC_OTG_EP3_FIFO S3C_USBOTGREG(0x4000)
	103	#define S3C_UDC_OTG_EP4_FIFO S3C_USBOTGREG(0x5000)
	104	#define S3C_UDC_OTG_EP5_FIFO S3C_USBOTGREG(0x6000)
	105	#define S3C_UDC_OTG_EP6_FIFO S3C_USBOTGREG(0x7000)
	106	#define S3C_UDC_OTG_EP7_FIFO S3C_USBOTGREG(0x8000)
	107	#define S3C_UDC_OTG_EP8_FIFO S3C_USBOTGREG(0x9000)
	108	#define S3C_UDC_OTG_EP9_FIFO S3C_USBOTGREG(0xA000)
	109	#define S3C_UDC_OTG_EP10_FIFO S3C_USBOTGREG(0xB000)
	110	#define S3C_UDC_OTG_EP11_FIFO S3C_USBOTGREG(0xC000)
	111	#define S3C_UDC_OTG_EP12_FIFO S3C_USBOTGREG(0xD000)
	112	#define S3C_UDC_OTG_EP13_FIFO S3C_USBOTGREG(0xE000)
	113	#define S3C_UDC_OTG_EP14_FIFO S3C_USBOTGREG(0xF000)
	114	#define S3C_UDC_OTG_EP15_FIFO S3C_USBOTGREG(0x10000)
	115
	116	/===================================================================== /
	117	/definitions related to CSR setting /
	118
	119	/* S3C_UDC_OTG_GOTGCTL */
	120	#define B_SESSION_VALID (0x1<<19)
	121	#define A_SESSION_VALID (0x1<<18)
	122
	123	/* S3C_UDC_OTG_GAHBCFG */
	124	#define PTXFE_HALF (0<<8)
	125	#define PTXFE_ZERO (1<<8)
	126	#define NPTXFE_HALF (0<<7)
	127	#define NPTXFE_ZERO (1<<7)
	128	#define MODE_SLAVE (0<<5)
	129	#define MODE_DMA (1<<5)
	130	#define BURST_SINGLE (0<<1)
	131	#define BURST_INCR (1<<1)
	132	#define BURST_INCR4 (3<<1)
	133	#define BURST_INCR8 (5<<1)
	134	#define BURST_INCR16 (7<<1)
	135	#define GBL_INT_UNMASK (1<<0)
	136	#define GBL_INT_MASK (0<<0)
	137
	138	/* S3C_UDC_OTG_GRSTCTL */
	139	#define AHB_MASTER_IDLE (1u<<31)
	140	#define CORE_SOFT_RESET (0x1<<0)
	141
	142	/* S3C_UDC_OTG_GINTSTS/S3C_UDC_OTG_GINTMSK core interrupt register */
	143	#define INT_RESUME (1u<<31)
	144	#define INT_DISCONN (0x1<<29)
	145	#define INT_CONN_ID_STS_CNG (0x1<<28)
	146	#define INT_OUT_EP (0x1<<19)
	147	#define INT_IN_EP (0x1<<18)
	148	#define INT_ENUMDONE (0x1<<13)
	149	#define INT_RESET (0x1<<12)
	150	#define INT_SUSPEND (0x1<<11)
	151	#define INT_EARLY_SUSPEND (0x1<<10)
	152	#define INT_NP_TX_FIFO_EMPTY (0x1<<5)
	153	#define INT_RX_FIFO_NOT_EMPTY (0x1<<4)
	154	#define INT_SOF (0x1<<3)
	155	#define INT_DEV_MODE (0x0<<0)
	156	#define INT_HOST_MODE (0x1<<1)
	157	#define INT_GOUTNakEff (0x01<<7)
	158	#define INT_GINNakEff (0x01<<6)
	159
	160	#define FULL_SPEED_CONTROL_PKT_SIZE 8
	161	#define FULL_SPEED_BULK_PKT_SIZE 64
	162
	163	#define HIGH_SPEED_CONTROL_PKT_SIZE 64
	164	#define HIGH_SPEED_BULK_PKT_SIZE 512
	165
	166	#ifdef CONFIG_CPU_S5P6450
	167	#define RX_FIFO_SIZE (4096>>2)
	168	#define NPTX_FIFO_START_ADDR RX_FIFO_SIZE
	169	#define NPTX_FIFO_SIZE (4096>>2)
	170	#define PTX_FIFO_SIZE (1520>>2)
	171	#else
	172	#define RX_FIFO_SIZE (4096>>2)
	173	#define NPTX_FIFO_START_ADDR RX_FIFO_SIZE
	174	#define NPTX_FIFO_SIZE (4096>>2)
	175	#define PTX_FIFO_SIZE (1024>>2)
	176	#endif
	177
	178	/* Enumeration speed */
	179	#define USB_HIGH_30_60MHZ (0x0<<1)
	180	#define USB_FULL_30_60MHZ (0x1<<1)
	181	#define USB_LOW_6MHZ (0x2<<1)
	182	#define USB_FULL_48MHZ (0x3<<1)
	183
	184	/* S3C_UDC_OTG_GRXSTSP STATUS */
	185	#define OUT_PKT_RECEIVED (0x2<<17)
	186	#define OUT_TRANSFER_COMPLELTED (0x3<<17)
	187	#define SETUP_TRANSACTION_COMPLETED (0x4<<17)
	188	#define SETUP_PKT_RECEIVED (0x6<<17)
	189	#define GLOBAL_OUT_NAK (0x1<<17)
	190
	191	/* S3C_UDC_OTG_DCTL device control register */
	192	#define NORMAL_OPERATION (0x1<<0)
	193	#define SOFT_DISCONNECT (0x1<<1)
	194	#define TEST_CONTROL_MASK (0x7<<4)
	195	#define TEST_J_MODE (0x1<<4)
	196	#define TEST_K_MODE (0x2<<4)
	197	#define TEST_SE0_NAK_MODE (0x3<<4)
	198	#define TEST_PACKET_MODE (0x4<<4)
	199	#define TEST_FORCE_ENABLE_MODE (0x5<<4)
	200
	201	/* S3C_UDC_OTG_DAINT device all endpoint interrupt register */
	202	#define DAINT_OUT_BIT (16)
	203	#define DAINT_MASK (0xFFFF)
	204
	205	/* S3C_UDC_OTG_DIEPCTL0/DOEPCTL0 device control IN/OUT endpoint 0 control register */
	206	#define DEPCTL_EPENA (0x1<<31)
	207	#define DEPCTL_EPDIS (0x1<<30)
	208	#define DEPCTL_SETD1PID (0x1<<29)
	209	#define DEPCTL_SETD0PID (0x1<<28)
	210	#define DEPCTL_SNAK (0x1<<27)
	211	#define DEPCTL_CNAK (0x1<<26)
	212	#define DEPCTL_STALL (0x1<<21)
	213	#define DEPCTL_TYPE_BIT (18)
	214	#define DEPCTL_TXFNUM_BIT (22)
	215	#define DEPCTL_TXFNUM_MASK (0xF<<22)
	216	#define DEPCTL_TYPE_MASK (0x3<<18)
	217	#define DEPCTL_CTRL_TYPE (0x0<<18)
	218	#define DEPCTL_ISO_TYPE (0x1<<18)
	219	#define DEPCTL_BULK_TYPE (0x2<<18)
	220	#define DEPCTL_INTR_TYPE (0x3<<18)
	221	#define DEPCTL_NAKSTS (0x1<<17)
	222	#define DEPCTL_USBACTEP (0x1<<15)
	223	#define DEPCTL_NEXT_EP_BIT (11)
	224	#define DEPCTL_MPS_BIT (0)
	225	#define DEPCTL_MPS_MASK (0x7FF)
	226
	227	#define DEPCTL0_MPS_64 (0x0<<0)
	228	#define DEPCTL0_MPS_32 (0x1<<0)
	229	#define DEPCTL0_MPS_16 (0x2<<0)
	230	#define DEPCTL0_MPS_8 (0x3<<0)
	231	#define DEPCTL_MPS_BULK_512 (512<<0)
	232	#define DEPCTL_MPS_INT_MPS_16 (16<<0)
	233
	234	#define DIEPCTL0_NEXT_EP_BIT (11)
	235
	236	/* S3C_UDC_OTG_DIEPCTLn/DOEPCTLn device control IN/OUT endpoint n control register */
	237
	238	/* S3C_UDC_OTG_DIEPMSK/DOEPMSK device IN/OUT endpoint common interrupt mask register */
	239	/* S3C_UDC_OTG_DIEPINTn/DOEPINTn device IN/OUT endpoint interrupt register */
	240	#define BACK2BACK_SETUP_RECEIVED (0x1<<6)
	241	#define INTKNEPMIS (0x1<<5)
	242	#define INTKN_TXFEMP (0x1<<4)
	243	#define NON_ISO_IN_EP_TIMEOUT (0x1<<3)
	244	#define CTRL_OUT_EP_SETUP_PHASE_DONE (0x1<<3)
	245	#define AHB_ERROR (0x1<<2)
	246	#define EPDISBLD (0x1<<1)
	247	#define TRANSFER_DONE (0x1<<0)
	248
	249	/DIEPTSIZ0 / DOEPTSIZ0 /
	250
	251	/* DEPTSIZ common bit */
	252	#define DEPTSIZ_PKT_CNT_BIT (19)
	253	#define DEPTSIZ_XFER_SIZE_BIT (0)
	254
	255	#define DEPTSIZ_SETUP_PKCNT_1 (1<<29)
	256	#define DEPTSIZ_SETUP_PKCNT_2 (2<<29)
	257	#define DEPTSIZ_SETUP_PKCNT_3 (3<<29)
	258
	259	#endif