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* ENGR00322581-05 tty: serial: imx: Revert "tty: serial: imx: set uart to cpu ↵Fugang Duan2014-07-14
| | | | | | | | | | | | mode by default" Since uart SDMA can work for Atheros BT module in android environment, the previous patch (commit f337845718) disable SDMA mode in default, now revert the patch to avoid the big change in dts for all platforms. By default, we enable SDMA mode for uart. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00322379 tty: serial: imx: set uart to cpu mode by defaultFugang Duan2014-07-11
| | | | | | | | | | Now uart cannot work well with CSR/Atheros BT module with SDMA mode. Set it to cpu mode before SDMA mode work. To enable dma mode, just add "fsl,dma-mode" in the device tree for the node. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00317086-1 clk: Add dcic clock define for imx6qSandor Yu2014-07-03
| | | | | | | Add dcic1 and dcic define in imx6q clock tree. Signed-off-by: Sandor Yu <R01008@freescale.com> (cherry picked from commit 93ae4ba005f1931ed3cd4e0ac0e8948e3752ad68)
* ENGR00319720-9 Documentation: usb: chipidea: Update test procedure for HNP ↵Li Jun2014-06-26
| | | | | | | | polling support Update HNP test procedure as HNP polling is supported. Signed-off-by: Li Jun <b47624@freescale.com>
* Doc: usb: chipidea: need to build both kernel Image and modulesPeter Chen2014-06-26
| | | | | | | | | | When tried to enable OTG FSM, we need to rebuild both kernel Image and modules, since there are some codes at gadget modules which are controlled by related configurations. Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> (cherry picked from commit d5b9d41f94a17af4c39b519703451c07a6a5ea9b)
* ENGR00318063-8: ARM: imx6q: hide buggy ldb_di_sel from clk APIShawn Guo2014-06-25
| | | | | | | | | | | | | | | | | | | | | | | | The clk_set_parent() on the buggy mux ldb_di0_sel and ldb_di1_sel can possibly lock up the downstream divider and result in no clock output. Let's hard-code the parent to be pll2_pfd0_352m at boot time, and hide these two buggy muxes from clk API. Then no clk_set_parent() can be called on these muxes to switch parent clock at run-time. Kernel parameter 'ldb_di_clk_sel' is created to select parent of ldb_di_clk among the following clocks at boot time. 'pll5_video_div' 'pll2_pfd0_352m' 'pll2_pfd2_396m' 'mmdc_ch1_axi' 'pll3_usb_otg' Example format: ldb_di_clk_sel=pll5_video_div If the kernel parameter is absent or invalid, pll2_pfd0_352m will be selected by default. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-2: ARM: imx6q: fix axi_sels mux settingShawn Guo2014-06-25
| | | | | | | | | | | | | | | | | | The current imx6q clock driver combines two mux clocks axi_alt_sel and axi_sel into one, while axi_alt_sel is a glitchy mux and axi_sel is a glitchless one. Fix it to match the clock tree in Reference Manual, and update busfreq driver regarding parent switching on that. Note, the parent checking before calling clk_set_parent() in busfreq driver isn't really necessary, because clk API will make the check and do nothing if the new parent is the same one as the old. One thing clk API clients need to take care is that clk_set_parent() can be called on glitchy axi_alt_sel only when axi_sel selects the other path, i.e. periph. Otherwise, a glitch could be generated on axi_alt_sel and get propagated into the divider axi_podf. In that case, axi_podf gets locked up and axi clock has no output. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00319455-1 can: m_can: add Bosch M_CAN controller supportDong Aisheng2014-06-20
| | | | | | | | | | | | | | | | | | | | The patch adds the basic CAN TX/RX function support for Bosch M_CAN controller. For TX, only one dedicated tx buffer is used for sending data. For RX, RXFIFO 0 is used for receiving data to avoid overflow. Rx FIFO 1 and Rx Buffers are not used currently, as well as Tx Event FIFO. Due to the message ram can be shared by multi m_can instances and the fifo element is configurable which is SoC dependant, the design is to parse the message ram related configuration data from device tree rather than hardcode define it in driver which can make the message ram using fully transparently to M_CAN controller driver, then we can gain better driver maintainability and future features upgrade. M_CAN also supports CANFD protocol features like data payload up to 64 bytes and bitrate switch at runtime, however, this patch still does not add the support for these features. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* ENGR00318259-2 ARM: imx: support mega fast domain power off in DSMAnson Huang2014-06-17
| | | | | | | | | | Add mega fast domain power off feature in DSM, it can save about 0.72mW power; If there is any module in Mega/Fast domain enabled as wakeup source, then Mega/Fast domain's power will be kept on in DSM. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00313685-9 of/irq: create interrupts-extended propertyGrant Likely2014-05-16
| | | | | | | | | | | | | | | | | | | | | | | commit 79d9701559a9f3e9b2021fbd292f5e70ad75f686 upstream. The standard interrupts property in device tree can only handle interrupts coming from a single interrupt parent. If a device is wired to multiple interrupt controllers, then it needs to be attached to a node with an interrupt-map property to demux the interrupt specifiers which is confusing. It would be a lot easier if there was a form of the interrupts property that allows for a separate interrupt phandle for each interrupt specifier. This patch does exactly that by creating a new interrupts-extended property which reuses the phandle+arguments pattern used by GPIOs and other core bindings. Signed-off-by: Grant Likely <grant.likely@linaro.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Kumar Gala <galak@codeaurora.org> [grant.likely: removed versatile platform hunks into separate patch] Cc: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00313280-2 ASoC: fsl: Merge upsteamed cs42xx8 driver.Shengjiu Wang2014-05-13
| | | | | | | | | | | | | | | | | | The upsteamed commit is 0c516b4ff85c0be4cee5b30ae59c9565c7f91a00 ASoC: cs42xx8: Add codec driver support for CS42448/CS42888 This patch adds support for the Cirrus Logic CS42448/CS42888 Audio CODEC that has six/four 24-bit AD and eight 24-bit DA converters. [ CS42448/CS42888 supports both I2C and SPI control ports. As initial patch, this patch only adds the support for I2C. ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Acked-by: Brian Austin <brian.austin@cirrus.com> Acked-by: Paul Handrigan <Paul.Handrigan@cirrus.com> Signed-off-by: Mark Brown <broonie@linaro.org> Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* ENGR00310878-2 ASoC: fsl_esai: cherry-pick from upstream and merge to mainlineShengjiu Wang2014-04-29
| | | | | | | | | | | | | | | cherry-picked commit is 43d24e76b69826ce32292f47060ad78cdd0197fa Header of this commit is "ASoC: fsl_esai: Add ESAI CPU DAI driver", use upstream driver to replace current one. Merged feature is: 1. Move setting of PRRC and PCRC to the end of hw_params, and disable it in shutdown function. 2. Merged the xrun handler with this commit. 3. Use dma init with NO_RESIDUE|NO_DT|COMPAT. 4. Add spba clock for ESAI Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* ENGR00310878-1 Asoc: fsl: refine clock tree for ESAIShengjiu Wang2014-04-29
| | | | | | | There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Make the clock for ESAI more clear. Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* ENGR00309073-1 ASoC: fsl: Naming of p2p item is not properShengjiu Wang2014-04-17
| | | | | | Change the output-rate, output-width to p2p-rate, p2p-width. Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* ENGR00307558-11 Documentation: usb: add chipidea.txt for how to demo usb OTG ↵Li Jun2014-04-16
| | | | | | | | | | HNP and SRP This patch adds a file chipidea.txt for how to demo chipidea usb OTG HNP and SRP functions via sysfs input files, any other possible information should be documented for chipidea usb driver in future can be added into this file. Signed-off-by: Li Jun <b47624@freescale.com>
* ENGR00307558-10 Documentation: ABI: usb: sysfs Description for chipidea USB ↵Li Jun2014-04-16
| | | | | | | | OTG HNP and SRP This patch adds sysfs interface description for chipidea USB OTG HNP and SRP. Signed-off-by: Li Jun <b47624@freescale.com>
* ENGR00307635-5 ASoC: imx-wm8962: Add non-SSI cpu dai supportNicolin Chen2014-04-16
| | | | | | | | | | | | The current imx-wm8962 machine driver is designed for SSI as CPU DAI only while as its name we should make the driver more generic to any other CPU DAI on i.MX serires -- ESAI, SAI for example. So this patch makes the driver more general so as to support those non-SSI cases. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00307635-2 dmaengine: imx-sdma: Add imx6sx platform supportNicolin Chen2014-04-16
| | | | | | | | | | | | | | The new Solo X has more requirements for SDMA events. So it creates a event mux to remap most of event numbers in GPR (General Purpose Register). If we want to use SDMA support for those module who do not get the even number as default, we need to configure GPR first. Thus this patch adds this support of GPR event remapping configuration to the SDMA driver. Acked-by: Robin Gong <b38343@freescale.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ASoC: fsl_sai: Add clock controls for SAINicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | The SAI mainly has the following clocks: bus clock control and configure registers and to generate synchronous interrupts and DMA requests. mclk1, mclk2, mclk3 to generate the bit clock when the receiver or transmitter is configured for an internally generated bit clock. So this patch adds these clocks and their clock controls to the driver. [ To concern the old DTB cases, I've added a bit of extra code to make the driver compatible with them. And by marking clock NULL if failed to get, the clk_prepare() or clk_get_rate() would easily return 0 so no further path should be broken. -- by Nicolin ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Acked-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 17d1eb6628e70488c44c46003dcfe583696bb7b7)
* pwm-backlight: Use new enable_gpio fieldThierry Reding2014-04-16
| | | | | | | | | | Make use of the new enable_gpio field and allow it to be set from DT as well. Now that all legacy users of platform data have been converted to initialize this field to an invalid value, it is safe to use the field from the driver. Signed-off-by: Thierry Reding <treding@nvidia.com> (cherry picked from commit 8265b2e4e62632b01f998095d1bbda4d281629fe)
* ENGR00306653-2 input: keyboad: snvs_pwrkey: add snvs power key driverRobin Gong2014-04-16
| | | | | | add snvs power key driver since ic team has fix some issues of SNVS on i.mx6sx Signed-off-by: Robin Gong <b38343@freescale.com>
* Input: tsc2007 - add device tree support.Denis Carikli2014-04-16
| | | | | Signed-off-by: Denis Carikli <denis@eukrea.com> Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
* ASoC: fsl_sai: Add imx6sx platform supportNicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | The next coming i.MX6 Solo X SoC also contains SAI module while we use imp_pcm_init() for i.MX platform. So this patch adds one compatible route for imx6sx and updates the DT doc accordingly. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit 30c35252aadb460e009ca8a3fdc8891903bdfc66) [ Added essential parameters to imx_pcm_init() calling due to build error, resulted from the define change of the function on the upstream. ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ASoC: fsl-sai: Add device tree bindings for Freescale SAI.Xiubo Li2014-04-16
| | | | | | | | | This adds the Document for Freescale SAI driver under Documentation/devicetree/bindings/sound/. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit b6344859b911990152e5ee411e62b82eb968004f)
* ENGR00305648-8 dma: imx-sdma: Add SAI script supportNicolin Chen2014-04-16
| | | | | | | This patch adds SAI script support to imx-sdma. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00305648-1 ASoC: imx-sgtl5000: Support non-ssi cpu-daiNicolin Chen2014-04-16
| | | | | | | | | | The current imx-sgtl5000 driver always attaches the cpu-dai to ssi while in fact it could be attached to other cpu-dais like SAI. Thus this patch use a general code to support another cpu-dai. And meanwhile update the devicetree for i.MX6 Series. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00304563-1 net: fec: add fixed phy address supportFugang Duan2014-04-16
| | | | | | | | | | | | Add fixed phy address support. i.MX6sx has two MACs, and MAC1 mdio bus connects to two phys which means MAC2 share MDIO bus with MAC1. So for any one of the two MACn, which can scan two phy address. For current implementment, it selects the little address for the default address and binding with the phy. For the situation, user can add the fixed phy address to DTS. Signed-off-by: Fugang Duan <B38611@freescale.com>
* usb: doc: rename ci13xxx-imx.txt to ci-hdrc-imx.txtPeter Chen2014-04-16
| | | | | | | | | | We have already renamed the file name, change doc name at this patch. Cc: devicetree@vger.kernel.org Cc: linux-doc@vger.kernel.org Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* usb: chipidea: udc: add maximum-speed = full-speed optionMichael Grzeschik2014-04-16
| | | | | | | | | | This patch makes it possible to set the chipidea udc into full-speed only mode. It is set by the oftree property "maximum-speed = full-speed". Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* usb: common: introduce of_usb_get_maximum_speed()Felipe Balbi2014-04-16
| | | | | | | | | | | | this helper will be used for controllers which want to work at a lower speed even though they support higher USB transfer rates. One such case is Texas Instruments' AM437x SoC where it uses a USB3 controller without a USB3 PHY, rendering the controller USB2-only. Signed-off-by: Felipe Balbi <balbi@ti.com>
* ENGR00302869-1 ARM: dts: imx6qdl: add cfg_clk for MIPI CSI2Robby Cai2014-04-16
| | | | | | | MIPI CSI2 depends on this clock to work. This patch also updates the binding document. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00302472-10 video: mxsfb: Add mxc disp driver supportLiu Ying2014-04-16
| | | | | | | This patch adds mxc display driver support for the mxsfb driver so that it may interactive with encoder drivers. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-6 video: mxc: LDB driver refactorLiu Ying2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | This patch almost reworks the LDB driver to make the implementation simpler and clearer. The new version should support all the LDB modules embedded in imx53, imx6qdl and imx6sx. The lvds-channel subsidiary DT node is introduced to represent each LVDS channel. People may specify a channel's CRTC, working mode(dual mode or split mode), data width, data mapping, display timing and if it is a primary channel in the node. Change logs: * Use CTRC concept so that the driver may support both IPU and LCDIF as the display engines. * Add mxc dispdrv enable() callback. * Cache LDB ctrl register value at probe()/setup()/ enable() stages and finally write to the register at enable() stage. * Simplify logics for setting ctrl/bus muxing/clocks. * Use regmap to write crtl and bus muxing registers. * Remove LDB description in DT binding doc fsl_ipuv3_fb.txt. Instead, add a new one in fsl,ldb.txt. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* regulator: pfuze100: add pfuze200 supportRobin Gong2014-04-16
| | | | | | | | | | | | support pfuze200 chip which remove SW1C and SW4 based on pfuze100. Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org> (cherry picked from commit f2518480c7b744296a5587990a54e3a284d932b8) Conflicts: drivers/regulator/pfuze100-regulator.c
* ENGR00303122-2 ARM: imx6q: fix ASRC related clocks in the clock treeNicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | | | | According to imx6q RM, there are three clock providers for ASRC: Module clock Clock root Gate asrck_clock_d spdif1_clk_root N/A ipg_clk ahb_clk_root asrc_clk_enable mem_clk ahb_clk_root asrc_clk_enable while the current clock tree describes a confusing clock named 'asrc' that combines this three clocks by rooting its rate from spdif1_clk_root but set its gate from ipg/mem_clk. Thus this patch first fixes the name asrc to the correct one -- spdif1 and adds the missing clocks to ASRC. [ Since we don't have the gate for asrck_clock_d, we can pass spdif0_clk to ASRC in the devicetree directly. ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* mtd: nand: Add a devicetree binding for ECC strength and ECC step sizeEzequiel Garcia2014-04-16
| | | | | | | | | | | | | | | | | | | | Some flashes can only be properly accessed when the ECC mode is specified, so a way to describe such mode is required. Together, the ECC strength and step size define the correction capability, so that we say we will correct "{strength} bit errors per {size} bytes". The interpretation of these parameters is implementation-defined, but they often have ramifications on the formation, interpretation, and placement of correction metadata on the flash. Not all implementations must support all possible combinations. Implementations are encouraged to further define the value(s) they support. Acked-by: Boris BREZILLON <b.brezillon.dev@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300430-6 Documentation: add the binding file for Freescale QuadSPI driverHuang Shijie2014-04-16
| | | | | | This patch adds the binding file for Freescale QuadSPI driver. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00300439-5 can: flexcan: parse stop mode control bits from device treeDong Aisheng2014-04-16
| | | | | | | | | | Starting from IMX6, the flexcan stop mode control bits is SoC specific, move it out of IP driver and parse it from devicetree. It's good from maintain perspective and can avoid adding too many SoC specifi bits in driver but with no IP changes when the IMX SoC series keep growing. Signed-off-by: Dong Aisheng <b29396@freescale.com>
* clk: add support for clock reparent on set_rateJames Hogan2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add core support to allow clock implementations to select the best parent clock when rounding a rate, e.g. the one which can provide the closest clock rate to that requested. This is by way of adding a new clock op, determine_rate(), which is like round_rate() but has an extra parameter to allow the clock implementation to optionally select a different parent clock. The core then takes care of reparenting the clock when setting the rate. The parent change takes place with the help of some new private data members. struct clk::new_parent specifies a clock's new parent (NULL indicates no change), and struct clk::new_child specifies a clock's new child (whose new_parent member points back to it). The purpose of these are to allow correct walking of the future tree for notifications prior to actually reparenting any clocks, specifically to skip child clocks who are being reparented to another clock (they will be notified via the new parent), and to include any new child clock. These pointers are set by clk_calc_subtree(), and the new_child pointer gets cleared when a child is actually reparented to avoid duplicate POST_RATE_CHANGE notifications. Each place where round_rate() is called, determine_rate() is checked first and called in preference. This restructures a few of the call sites to simplify the logic into if/else blocks. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Cc: Mike Turquette <mturquette@linaro.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Huang Shijie <b32955@freescale.com>
* Documentation: add the binding file for Freescale vf610 ADC driverFugang Duan2014-04-16
| | | | | | | | | | | | | The patch adds the binding file for Freescale vf610 ADC driver. CC: Shawn Guo <shawn.guo@linaro.org> CC: Jonathan Cameron <jic23@kernel.org> CC: Mark Rutland <mark.rutland@arm.com> CC: Otavio Salvador <otavio@ossystems.com.br> CC: Peter Meerwald <pmeerw@pmeerw.net> CC: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
* ENGR00299756-2 ARM: imx6q: Add missing lvds2 clock to the clock treeNicolin Chen2014-04-16
| | | | | | | | | | | | | | | We actually have lvds2 (analog clock2), an I/O clock like lvds1, in the SoC. And this lvds2, along with lvds1, can be used to provide external clock source to the internal pll, such as pll4_audio and pll5_video. So This patch mainly adds the lvds2 to the clock tree and fix its relationship with pll4 accordingly. [ To reduce the risk from code changing. This patch only takes care of pll4 related part. We might later need to add the relationship with pll5 too. ] Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00298052-2 Documentation: video: add Hannstar CABC dt bindingsLiu Ying2014-04-16
| | | | | | This patch documents the Hannstar CABC driver's device tree bindings. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00299323-16 ARM: Documentation: Update fec dts binding docFugang Duan2014-04-16
| | | | | | | This patch update fec devicetree binding doc that add Optional properties "fsl,num_tx_queues" and "fsl,num_rx_queues". Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00298524-4 pinctrl: imx: add pinctrl driver for imx6sxAnson Huang2014-04-16
| | | | | | | Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core driver. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00298524-2 ARM: imx: Add MSL support for i.mx6sxAnson Huang2014-04-16
| | | | | | | | | | | | | | It adds initial MSL support for i.mx6sx, including below features: 1. add cpu type check; 2. add system timer support; 3. add clock tree support; 4. add machine layer init support; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> Acked-by: Jason Liu
* ENGR00291282-1 usb: doc: ci13xxx-imx: update for hsic controllerPeter Chen2014-04-16
| | | | | | Update for hsic controller Signed-off-by: Peter Chen <peter.chen@freescale.com>
* mtd: add MTD_MLCNANDFLASH case for mtd_type_show()Huang Shijie2014-04-16
| | | | | | | | The current mtd_type_show() misses the MTD_MLCNANDFLASH case. This patch adds the case for it, and also updates the ABI. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* ENGR00288405: pcie: switch to upstreamed pcie driverRichard Zhu2014-04-16
| | | | | | | | | Based on community patch-set, re-setup pcie driver on imx6 platforms. * re-fine the pcie clks. * add the pcie support in dts files. Signed-off-by: Richard Zhu <r65037@freescale.com>
* PCI: imx6: Add support for i.MX6 PCIe controllerSean Cross2014-04-16
| | | | | | | | | | | Add support for the PCIe port present on the i.MX6 family of controllers. These use the Synopsis Designware core tied to their own PHY. Signed-off-by: Sean Cross <xobs@kosagi.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> (cherry picked from commit bb38919ec56e0758c3ae56dfc091dcde1391353e)
* ENGR00288568 Revert "ENGR00275213-1 arm: pcie: enable pcie on imx6 platforms"Richard Zhu2014-04-16
| | | | | | | | | | | | | switch to community upstreamed pcie driver. Revert "ENGR00275213-1 arm: pcie: enable pcie on imx6 platforms" This reverts commit d33370c77e57aed5a9b6733c9898418541fed54a. Conflicts: Documentation/devicetree/bindings/clock/imx6q-clock.txt arch/arm/mach-imx/clk-imx6q.c Signed-off-by: Richard Zhu <r65037@freescale.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-28 01:04:42 -0400