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authorMichael Grzeschik <m.grzeschik@pengutronix.de>2014-02-19 00:41:43 -0500
committerNitin Garg <nitin.garg@freescale.com>2014-04-16 09:58:01 -0400
commit1a72b128812847d2ab426e044b0db65b8c2e3d2a (patch)
tree57c2704ac7bfab68c3f7c6b073a5c785af072bbf /Documentation
parent4855dc3ae035df5313b61422a90c7055a2e60522 (diff)
usb: chipidea: udc: add maximum-speed = full-speed option
This patch makes it possible to set the chipidea udc into full-speed only mode. It is set by the oftree property "maximum-speed = full-speed". Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/usb/ci13xxx-imx.txt2
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
index 8d58c8ce91ca..881901a59604 100644
--- a/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
+++ b/Documentation/devicetree/bindings/usb/ci13xxx-imx.txt
@@ -30,6 +30,7 @@ at imx6 SoC series
30- osc-clkgate-delay: the delay between powering up the xtal 24MHz clock 30- osc-clkgate-delay: the delay between powering up the xtal 24MHz clock
31 and release the clock to the digital logic inside the analog block, 31 and release the clock to the digital logic inside the analog block,
32 0 <= osc-clkgate-delay <= 7. 32 0 <= osc-clkgate-delay <= 7.
33- maximum-speed: limit the maximum connection speed to "full-speed".
33 34
34Examples: 35Examples:
35usb@02184000 { /* USB OTG */ 36usb@02184000 { /* USB OTG */
@@ -46,4 +47,5 @@ usb@02184000 { /* USB OTG */
46 pinctrl-0 = <&pinctrl_usbh2_1>; 47 pinctrl-0 = <&pinctrl_usbh2_1>;
47 pinctrl-1 = <&pinctrl_usbh2_2>; 48 pinctrl-1 = <&pinctrl_usbh2_2>;
48 osc-clkgate-delay = <0x3>; 49 osc-clkgate-delay = <0x3>;
50 maximum-speed = "full-speed";
49}; 51};