ENGR00318063-2: ARM: imx6q: fix axi_sels mux setting

The current imx6q clock driver combines two mux clocks axi_alt_sel and
axi_sel into one, while axi_alt_sel is a glitchy mux and axi_sel is a
glitchless one.  Fix it to match the clock tree in Reference Manual,
and update busfreq driver regarding parent switching on that.  Note,
the parent checking before calling clk_set_parent() in busfreq driver
isn't really necessary, because clk API will make the check and do
nothing if the new parent is the same one as the old.

One thing clk API clients need to take care is that clk_set_parent()
can be called on glitchy axi_alt_sel only when axi_sel selects the other
path, i.e. periph.  Otherwise, a glitch could be generated on
axi_alt_sel and get propagated into the divider axi_podf.  In that case,
axi_podf gets locked up and axi clock has no output.

Signed-off-by: Shawn Guo <shawn.guo@freescale.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/clock/imx6q-clock.txt b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
index 622e5ac90d28..300946718ae7 100644
--- a/Documentation/devicetree/bindings/clock/imx6q-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx6q-clock.txt
@@ -240,6 +240,7 @@ clocks and IDs.
         asrc_mem                227
         esai_ipg                228
         esai_mem                229
+        axi_alt_sel             230
 
 Examples: