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* ENGR00299939-2 ARM: imx6sl: Add dummy LDO2p5 regulator to support VBUS wakeupRanjani Vaidyanathan2014-04-16
| | | | | | | | | | | LDO2p5 cannot be disabled in low power idle mode when the USB driver enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy regulator that the USB driver will enable when VBUS wakeup is required. This patch ensures that the low power idle code checks the status of the dummy ldo2p5 regulator before disabling LDO2p5. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00299939-1 ARM: dts: imx6sl:Add dummy LDO2p5 regulator to support vbus ↵Ranjani Vaidyanathan2014-04-16
| | | | | | | | | | | wakeup LDO2p5 cannot be disabled in low power idle mode when the USB driver enables VBUS wakeup. To identify when LDO2p5 can be disabled add a dummy regulator that the USB driver will enable when VBUS wakeup is required. This patch adds the dummy regulator to the dts files. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00303795-4 usb: chipidea: imx: add hsic support for imx6sxPeter Chen2014-04-16
| | | | | | | | | Some improvements and bug-fixes for imx6sx: - Add one bit for sending resume signal using 32K OSC - Add board level pad regulator - HSIC also needs host quirk, add this fix for imx6sl too Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00303795-3 usb: chipidea: imx: rename host quirk flag to reflect its ↵Peter Chen2014-04-16
| | | | | | | | | real meaning This flag is not only used for mxs phy's bug, but also for speical routine for other imx host operations. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00303795-2 usb: chipidea: coordinate usb phy initialization for ↵Peter Chen2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | different phy type For internal PHY (like UTMI), the phy clock may from internal pll, it is on/off on the fly, the access PORTSC.PTS will hang without phy clock. So, the usb_phy_init which will open phy clock needs to be called before hw_phymode_configure. See: http://marc.info/?l=linux-arm-kernel&m=139350618732108&w=2 For external PHY (like ulpi), it needs to configure portsc.pts before visit viewport, or the viewport can't be visited. so phy_phymode_configure needs to be called before usb_phy_init. See: cd0b42c2a6d2a74244f0053f8960f5dad5842278 It may not the best solution, but it can work for all situations. Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Chris Ruehl <chris.ruehl@gtsys.com.hk> Cc: shc_work@mail.ru Cc: denis@eukrea.com Cc: festevam@gmail.com Signed-off-by: Peter Chen <peter.chen@freescale.com>
* ENGR00303795-1 ARM: imx6sx: enable USB hsicPeter Chen2014-04-16
| | | | | | | | - Add USB hsic support for imx6sx - Enable hsic support at imx6sx 17x17 board - Enable usbotg1 and hsic support at imx6sx 19x19 board Signed-off-by: Peter Chen <peter.chen@freescale.com>
* usb: doc: rename ci13xxx-imx.txt to ci-hdrc-imx.txtPeter Chen2014-04-16
| | | | | | | | | | We have already renamed the file name, change doc name at this patch. Cc: devicetree@vger.kernel.org Cc: linux-doc@vger.kernel.org Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* usb: chipidea: Propagate the real error code on platform_get_irq() failureFabio Estevam2014-04-16
| | | | | | | | | | No need to return a 'fake' return value on platform_get_irq() failure. Just return the error code itself instead. Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* usb: chipidea: udc: add maximum-speed = full-speed optionMichael Grzeschik2014-04-16
| | | | | | | | | | This patch makes it possible to set the chipidea udc into full-speed only mode. It is set by the oftree property "maximum-speed = full-speed". Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Michael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* usb: chipidea: use dev_get_platdata()Jingoo Han2014-04-16
| | | | | | | | | | Use the wrapper function for retrieving the platform data instead of accessing dev->platform_data directly. This is a cosmetic change to make the code simpler and enhance the readability. Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* usb: chipidea: refine PHY operationPeter Chen2014-04-16
| | | | | | | | | - Delete global_phy due to we can get the phy from phy layer now - using devm_usb_get_phy to instead of usb_get_phy - delete the otg_set_peripheral, which should be handled by otg layer Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* usb: common: introduce of_usb_get_maximum_speed()Felipe Balbi2014-04-16
| | | | | | | | | | | | this helper will be used for controllers which want to work at a lower speed even though they support higher USB transfer rates. One such case is Texas Instruments' AM437x SoC where it uses a USB3 controller without a USB3 PHY, rendering the controller USB2-only. Signed-off-by: Felipe Balbi <balbi@ti.com>
* ENGR00304199 ARM: dtsi: add enet2 support for imx6sx arm2 platformsFugang Duan2014-04-16
| | | | | | | | | | | | | | | Add enet2 support for imx6sx 17x17/19x19 arm2 board. Since imx6sx has two enet interface, and all AR8031 ethernet daughter boards max7322 connect to same i2c bus, and same i2c slave address. Phy address also are the same in default. So need to change max7322 i2c slave address and phy address to others to avoid collision. Ar8031 ethernet daughter board rework: R9: switch to B, remove R22, install R21 with 10k. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00303791-1 ARM:imx6x: Add IRAM page table support for imx6sx.Ranjani Vaidyanathan2014-04-16
| | | | | | | | | | | | | Allocate page tables in IRAM that will be used when ever DDR is put into self-refresh. Add support for this to iMX6SX. Some common files are also changed to accomodate the OCRAM_S address that is used to store the IRAM page table in iMX6SX. This patch depends on the following two commits: ENGR297285-1 [MX6x] Support IRAM page table when DDR is in self-refresh. ENGR297285-2 [MX6x] Support IRAM page table when DDR is in self-refresh. Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00297285-2 [MX6x] Support IRAM page table when DDR is in self-refresh.Ranjani Vaidyanathan2014-04-16
| | | | | | | | | | The bottom 16KB of the IRAM is reserved for the IRAM page table. Reduce the available IRAM size for the other drivers by 16KB. This commit is cherry-picked: d43a087f363b5dc91ddc4fc401540050d7f55c7f Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00297285-1 [MX6x] Support IRAM page table when DDR is in self-refreshRanjani Vaidyanathan2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Whenever DDR is explicitly put into self-refresh, we need to ensure that no access are made to the DDR. All the bus masters excpet ARM are shutdown gracefully. The ARM core can continue to access the DDR due to: 1. Speculative accesses This can be prevented by flushing the Branch Target Address Cache 2. Aggressive Prefetching This can be minimized by adding nops. Apart from this the TLB architecture in ARM does not guarantee that an entry remains in the TLB unless its explicitly locked. Even if free slots are available an entry maybe evicted. So flushing the TLB does not guarantee a page table walk will not happen. The solution is to put a minimized page table in IRAM that can be used when DDR is in self-refresh. The IRAM page tables should have entries for IRAM, AIPS1 and AIPS2 as these entries will be needed by the code that puts DDR into self-refresh. It should not contain any entries that point to the DDR. This patch set accomplishes the following: 1. Set the IRAM to be mapped as 1M sections in the high mem region. This makes it possible to create entries for the IRAM code in the IRAM page table. We need to ensure that both the DDR and IRAM page table have mapping for the IRAM code. 2. Ensure the IRAM, AIPS1, AIPS2 have entries in the IRAM page table. 3. Save TTBR1 4. Set TTBR1 to point to the page tables stored in IRAM. Switch to using TTBR1 before DDR is put into self-refresh. Ensure the following settings: a. TTBCR.N = 1 This means the 0-2G virtual address space is translated using TTBR0 and 2G-4G is translated using TTBR1. b. Set TTBCR.PD0 = 1 With this setting page table walks using TTBR0 are disabled. 4. After the DDR has exited self-refresh, reset TTBCR to 0 (TTBR0 will be used for translations now). 5. Restore TTBR1 Even though TTBR1 is only used to decode the top 2G of virtual address space, ARM requires that we allocate the entire 16KB for the page table. To minimize IRAM/OCRAM required, we put the code in the bottom 8K and page table entries in the top 8K. This requires the low power code be optimized to occupy as little space as possible. This commit is cherry-picked: 93ae491d9dbe34a91e2dd5832b02b0f0a390ddbe Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
* ENGR00303820 [#887] refine physical address check for external memoryXianzhong2014-04-16
| | | | | | | | | 2G above address will cause system reboot and fixed in original patch, error check code is added based on the original logic. Signed-off-by: Xianzhong <b07117@freescale.com> Acked-by: Jason Liu (cherry picked from commit 7d85c98bf781eb047c2000bd82ea7559c24a2446)
* ENGR00303629-2 qspi: support SF25FL128S by enabling DDR Quad IO modeAllen Xu2014-04-16
| | | | | | Enalbe DDR Quad IO mode to support Spansion SF25FL128S NOR flash. Signed-off-by: Allen Xu <b45815@freescale.com>
* ENGR00303629-1: ARM: dts: imx6sx-sdb: support NOR Flash SF25FL128SAllen Xu2014-04-16
| | | | | | add Spansion SF25FL128S in sdb dts file. Signed-off-by: Allen Xu <b45815@freescale.com>
* net: fec: fix the error to get the previous BD entryFugang Duan2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bug: error to get the previous BD entry. When the current BD is the first BD, the previous BD entry must be the last BD, not "bdp - 1" in current logic. V4: * Optimize fec_enet_get_nextdesc() for code clean. Replace "ex_new_bd - ring_size" with "ex_base". Replace "new_bd - ring_size" with "base". V3: * Restore the API name because David suggest to use fec_enet_ prefix for all function in fec driver. So, change next_bd() -> fec_enet_get_nextdesc() change pre_bd() -> fec_enet_get_prevdesc() * Reduce the two APIs parameters for easy to call. V2: * Add tx_ring_size and rx_ring_size to struct fec_enet_private. * Replace api fec_enet_get_nextdesc() with next_bd(). Replace api fec_enet_get_prevdesc() with pre_bd(). * Move all ring size check logic to next_bd() and pre_bd(), which simplifies the code redundancy. V1: * Add BD ring size check to get the previous BD entry in correctly. Reviewed-by: Li Frank <B20596@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Acked-by: Frank Li <frank.li@freescale.net> Signed-off-by: David S. Miller <davem@davemloft.net>
* ENGR00303663 mxc v4l2 capture: Don't return error if we cannot get mipi csi2Liu Ying2014-04-16
| | | | | | | | | | | | | | | | | The mipi csi2 code is ugly present in the capture pipeline setup/disable routions with '#ifdef CONFIG_MXC_MIPI_CSI2/#endif' protected. Whenever it finds mipi_csi2_info is not gotten correctly, it will return error to callers. This breaks the normally routines in which mipi csi2 is not used and mipi csi2 driver is disabled in its devicetree node(but with the Kconfig CONFIG_MXC_MIPI_CSI2 defined). A real example is the capture feature on the MX6 Sabreauto platforms. We have only parallel CSI input on it and the mipi csi2 driver is disabled in its devicetree node but with the Kconfig CONFIG_MXC_MIPI_CSI2 defined. So, a reasonable choice at present is not to return error if mipi_csi2_info cannot be gotten, though we could eventually re-organize the capture code for a better total solution in the future. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* NET: fec: only enable napi if we are successfulFugang Duan2014-04-16
| | | | | | | | | | | | | | | | | | | | If napi is left enabled after a failed attempt to bring the interface up, we BUG: fec 2188000.ethernet eth0: no PHY, assuming direct connection to switch libphy: PHY fixed-0:00 not found fec 2188000.ethernet eth0: could not attach to PHY ------------[ cut here ]------------ kernel BUG at include/linux/netdevice.h:502! Internal error: Oops - BUG: 0 [#1] SMP ARM ... PC is at fec_enet_open+0x4d0/0x500 LR is at __dev_open+0xa4/0xfc Only enable napi after we are past all the failure paths. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
* ENGR00303308 hdmi:update default video mode setting required by xserverSandor Yu2014-04-16
| | | | | | | | | | | | | xserver will read default video mode in command line by sysfs node /sys/class/graphics/fb0/mode, but the sysfs node is not initialized when system bootup without hdmi cable plugin or frame buffer register in blank state. Fixed: - Remove unused previous_mode - Add default_mode, initialize in disp_init function. - Initialize fbi->mode in disp_init function and hdmi_setup function. Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00243315-4 MXC V4L2 Capture:Improve debug info for s_stdLiu Ying2014-04-16
| | | | | | | | | | | | | commit f8e1a3bb62eecf93a31a51c4dbe08a0214fa1d57 introduced an annoying kernel log by changing a pure debug info to error level. This patch reverts that change. Conflicts: drivers/media/video/mxc/capture/mxc_v4l2_capture.c Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 289cc885ae097bbf9849cb266679a2969e5c39a9)
* ENGR00243315-3 MXC V4L2 Capture:Remove unnecessary mclk settingLiu Ying2014-04-16
| | | | | | | | | | | | | | | | commit f8e1a3bb62eecf93a31a51c4dbe08a0214fa1d57 added a hard coding for csi_parma.mclk setting to 27MHz. The comment added by that commit is totally wrong by telling that csi_param.mclk would be a kind of 'pixel clock' set in 'csi_data_dest' register. This patch removes the unnecessary mclk setting for csi_param.mclk variable, since it is only valid for CSI test mode. Conflicts: drivers/media/video/mxc/capture/mxc_v4l2_capture.c Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 5fed1e3fde2d63c80f414f204734d35ceecef561)
* ENGR00243315-2 IPUv3 CSI:Remove test mode clock settingLiu Ying2014-04-16
| | | | | | | | | | | This patch removes test mode clock setting in function ipu_csi_init_interface(), since the setting is only necessary for function _ipu_csi_set_test_generator(). This unnecessary setting is added wrongly by commit f8e1a3bb62eecf93a31a51c4dbe08a0214fa1d57. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit 482c30821d0aad0ab500a9d5db95654917986a3c)
* ENGR00243315-1 IPUv3 CSI:Correct CCIR code1/2 for PAL and NTSCLiu Ying2014-04-16
| | | | | | | | | We reversed CCIR code1/2 setting before, which may brings captured frame quality issue(jaggy edge can be seen). This patch revert that change. Signed-off-by: Liu Ying <Ying.Liu@freescale.com> (cherry picked from commit abdb4369f6ebcd90656b5fc319ee79eeb3bec7c5)
* ENGR00303418 mtd: fsl-quadspi: set AHB transfer size to the maximum valueAllen Xu2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | Set AHB transfer size to 1K which significantly improved the read performance. Add ahb_buf_size field in fsl_qspi_devtype_data to denote the size for different SoC. Before: root@imx6qdlsolo:~# dd if=/dev/mtd1 of=/dev/null bs=1M count=16 16+0 records in 16+0 records out 16777216 bytes (17 MB) copied, 0.472183 s, 35.5 MB/s After: root@imx6qdlsolo:~# dd if=/dev/mtd1 of=/dev/null bs=1M count=16 16+0 records in 16+0 records out 16777216 bytes (17 MB) copied, 0.369439 s, 45.4 MB/s Signed-off-by: Allen Xu <b45815@freescale.com> Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00303533 mtd: fsl-quadspi: reset the module in the probeHuang Shijie2014-04-16
| | | | | | | | | | | The uboot may run the QuadSpi controler with command: #sf probe So we should reset the module in the probe. This patch also clear the pending interrupts which arised by the uboot code. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00298127-2 ARM: dtsi: imx6qdl sabreauto: Disable mipi csiLiu Ying2014-04-16
| | | | | | | | | As the sabreauto CPU board schematics mentions, the MIPI connector isn't mechanically compatible with Freescale MIPI display and camera board, then we have no way to support MIPI features currently on this platform. So, let's disable MIPI CSI. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00298127-1 ARM: dtsi: imx6qdl sabreauto: Remove v4l2_cap_1 nodeLiu Ying2014-04-16
| | | | | | | | | As the sabreauto CPU board schematics mentions, the MIPI connector isn't mechanically compatible with Freescale MIPI display and camera board, then we have only the parallel CSI video input that is supported by the v4l2_cap_0 node. So, let's remove the orphan one - v4l2_cap_1. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00303300-2 arm: dts: Add MLB50 dts support on i.MX6SX-17x17-arm2 board.Luwei Zhou2014-04-16
| | | | | | | | Add MLB50 devicetree support on i.MX6SX-17x17-arm2 platform. Since the MLB50 has pin conflict with usdhc2 on i.MX6SX-17x17-arm2 board, add an extra dts file to enable mlb and disable usdhc2. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00303300-1 mxc: mlb: Add MLB50 driver support on i.MX6SX chipLuwei Zhou2014-04-16
| | | | | | | Add MLB50 driver supported on i.MX6SX chip. MLB50 will not support frame rate over 1024 per second. Signed-off-by: Luwei Zhou <b45643@freescale.com>
* ENGR00302869-2 ARM: imx: imx6qdl: enable cfg_clk to make MIPI CSI2 workRobby Cai2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following error was reported. ----------------------------------------------------------- root@imx6qdlsolo:~# /unit_tests/mxc_v4l2_capture.out -d /dev/video1 1.yuv in_width = 176, in_height = 144 out_width = 176, out_height = 144 top = 0, left = 0 mipi csi2 can not receive sensor clk! sensor chip is ov5640_mipi_camera sensor supported frame size: 640x480 320x240 720x480 720x576 1280x720 1920x1080 2592x1944 176x144 1024x768 sensor frame format: UYVY sensor frame format: UYVY sensor frame format: UYVY sensor frame format: UYVY sensor frame format: UYVY sensor frame format: UYVY sensor frame format: UYVY sensor frame format: UYVY sensor frame format: UYVY mipi csi2 can not receive sensor clk! mxc_v4l2_s_param: vidioc_int_s_parm returned an error -1 VIDIOC_S_PARM failed get format failed ----------------------------------------------------------- Root cause analysis: It only happens when HDMI is not used/enabled. There is a clock named video_27m which are needed by HDMI (as isfrclk's parent) and MIPI-CSI2 (as cfg_clk's parent). MIPI-CSI2 driver is lack of enabling this clock before start to work and only happen to work when HDMI driver enables this clock. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00302869-1 ARM: dts: imx6qdl: add cfg_clk for MIPI CSI2Robby Cai2014-04-16
| | | | | | | MIPI CSI2 depends on this clock to work. This patch also updates the binding document. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00302472-17 ARM: dts: imx6sx-19x19-arm2: Support Hannstar CABCLiu Ying2014-04-16
| | | | | | | | | This patch adds a device tree node for the Hannstar CABC function. We currently disable the CABC feature since it makes a panel's backlight unstable when display content varies considerably from time to time. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-16 video: mxc ipuv3 fb: Report registered disp drv nicelyLiu Ying2014-04-16
| | | | | | | | | The mxc ipuv3 fb driver would report any display driver name that it is trying to register. To suppress the report, this patch has the driver provide the registered display driver name after register finishes. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-15 ARM: dts: imx6sx-19x19-arm2: Support LVDS outputLiu Ying2014-04-16
| | | | | | | This patch adds the Hannstar XGA LVDS panel support on the imx6sx-19x19-arm2 board. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-14 ARM: dtsi: imx6sx: Add LDB DT nodeLiu Ying2014-04-16
| | | | | | | There is one LDB module embedded in the imx6sx SoC. This patch adds LDB devicetree node into imx6sx.dtsi. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-13 ARM: dts: imx6sx-19x19-arm2: Enable LCDIF1/2Liu Ying2014-04-16
| | | | | | | | This patch enables LCDIF1 and LCDIF2. LCDIF1 will drive the SEIKO parallel WVGA panel and LCDIF2 will drive LDB to support a 18bit LVDS panel. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-12 ARM: dts: imx6sx-19x19-arm2: Enable PWM3Liu Ying2014-04-16
| | | | | | | This patch enables PWM3 so that PWM backlight could be supported. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-11 video: mxc LDB: Add FB_MXS to Kconfig dependencyLiu Ying2014-04-16
| | | | | | | Since LCDIF may drive LDB, let's add FB_MXS to LDB Kconfig dependency. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-10 video: mxsfb: Add mxc disp driver supportLiu Ying2014-04-16
| | | | | | | This patch adds mxc display driver support for the mxsfb driver so that it may interactive with encoder drivers. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-9 video: mxc disp: Drop post_init callbackLiu Ying2014-04-16
| | | | | | | Since there is no encoder driver using the post_init callback, let's drop it. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-8 ARM: dts: imx6qdl sabreauto: Remove LDB video mode stringLiu Ying2014-04-16
| | | | | | | This patch removes the video mode strings for framebuffers which are driven by LDB since they are specified in the lvds-channel DT node. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-7 ARM: dts: imx6qdl sabresd: Remove LDB video mode stringLiu Ying2014-04-16
| | | | | | | This patch removes the video mode strings for framebuffers which are driven by LDB since they are specified in the lvds-channel DT node. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-6 video: mxc: LDB driver refactorLiu Ying2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | This patch almost reworks the LDB driver to make the implementation simpler and clearer. The new version should support all the LDB modules embedded in imx53, imx6qdl and imx6sx. The lvds-channel subsidiary DT node is introduced to represent each LVDS channel. People may specify a channel's CRTC, working mode(dual mode or split mode), data width, data mapping, display timing and if it is a primary channel in the node. Change logs: * Use CTRC concept so that the driver may support both IPU and LCDIF as the display engines. * Add mxc dispdrv enable() callback. * Cache LDB ctrl register value at probe()/setup()/ enable() stages and finally write to the register at enable() stage. * Simplify logics for setting ctrl/bus muxing/clocks. * Use regmap to write crtl and bus muxing registers. * Remove LDB description in DT binding doc fsl_ipuv3_fb.txt. Instead, add a new one in fsl,ldb.txt. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-5 video: mxc disp: Let encoder know fbi when enable/disableLiu Ying2014-04-16
| | | | | | | | | | | This patch adds framebuffer info structure to the mxc display driver enable/disable callback parameters so that the encoder drivers may know the framebuffer information. In this way, the encoder drivers which may deal with more than one framebuffer are able to figure out the one it is handling. A real example is the LDB encoder, which may deal with two standalone framebuffers at most. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-4 video: mxc ipuv3 fb: Don't bail out if no DT mode strLiu Ying2014-04-16
| | | | | | | | The encoder drivers should decide if they need mode string for initialization or not. So, we don't have to provide mode string in the device tree node. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00302472-3 video: mxc: Introduce CRTC conceptLiu Ying2014-04-16
| | | | | | | | | | | As the mxc display system is getting more and more complex, various CRTCs(CRT controllers), such as IPUx DIy and LCDIFz, may drive various encoders. For example, imx6sx/imx6dl LCDIF may drive LDB while imx6dl IPU0 DI0/1 may drive LDB as well. This patch introduces CRTC concept to the display framework so that the core logic could be less IPU specific. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
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