ENGR00302472-13 ARM: dts: imx6sx-19x19-arm2: Enable LCDIF1/2

This patch enables LCDIF1 and LCDIF2.  LCDIF1 will drive
the SEIKO parallel WVGA panel and LCDIF2 will drive LDB
to support a 18bit LVDS panel.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>

1 files changed, 43 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/imx6sx-19x19-arm2.dts b/arch/arm/boot/dts/imx6sx-19x19-arm2.dts
index 8c18eac6ca4f..cf508c5a4fff 100644
--- a/arch/arm/boot/dts/imx6sx-19x19-arm2.dts
+++ b/arch/arm/boot/dts/imx6sx-19x19-arm2.dts
@@ -114,6 +114,49 @@
         };
 };
 
+&lcdif1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcdif_dat_0
+                     &pinctrl_lcdif_ctrl_0>;
+        display = <&display0>;
+        status = "okay";
+
+        display0: display {
+                bits-per-pixel = <16>;
+                bus-width = <24>;
+
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: timing0 {
+                                clock-frequency = <33500000>;
+                                hactive = <800>;
+                                vactive = <480>;
+                                hback-porch = <89>;
+                                hfront-porch = <164>;
+                                vback-porch = <23>;
+                                vfront-porch = <10>;
+                                hsync-len = <10>;
+                                vsync-len = <10>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <0>;
+                        };
+                };
+        };
+};
+
+&lcdif2 {
+        display = <&display1>;
+        disp-dev = "ldb";
+        status = "okay";
+
+        display1: display {
+                bits-per-pixel = <16>;
+                bus-width = <18>;
+        };
+};
+
 &pwm3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_pwm3_0>;