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* Merge tag 'mvebu-dt64-4.12-2' of git://git.infradead.org/linux-mvebu into ↵Olof Johansson2017-04-19
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | next/dt64 mvebu dt64 for 4.12 (part 2) - crypto engine description for the Armada 7k/8k SoCs and the boards using it - SDHCI description for the Armada 37xx and 7k/8k SoCs and the boards using it * tag 'mvebu-dt64-4.12-2' of git://git.infradead.org/linux-mvebu: arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB arm64: marvell: dts: add crypto engine description for 7k/8k arm64: dts: marvell: add sdhci support for Armada 7K/8K arm64: dts: marvell: add eMMC support for Armada 37xx Signed-off-by: Olof Johansson <olof@lixom.net>
| * arm64: marvell: dts: enable the crypto engine on the Armada 8040 DBAntoine Tenart2017-04-12
| | | | | | | | | | | | | | | | | | Enable the cryptographic engine available in the CP110 master on the Armada 8040 DB. Do not enable the one in the CP110 salve for now, as we do not support multiple cryptographic engines yet. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: marvell: dts: enable the crypto engine on the Armada 7040 DBAntoine Tenart2017-04-12
| | | | | | | | | | | | | | | | Enable the cryptographic engine available in the CP110 master on the Armada 7040 DB. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: marvell: dts: add crypto engine description for 7k/8kAntoine Tenart2017-04-12
| | | | | | | | | | | | | | | | Add the description of the crypto engine hardware block for the Marvell Armada 7k and Armada 8k processors; for both the CP110 slave and master. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: dts: marvell: add sdhci support for Armada 7K/8KGregory CLEMENT2017-04-11
| | | | | | | | | | | | Also enable it on the Armada 7040 DB and Armada 8040 DB boards. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
| * arm64: dts: marvell: add eMMC support for Armada 37xxGregory CLEMENT2017-04-11
| | | | | | | | | | | | | | Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720 DB board. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* | Merge tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi ↵Olof Johansson2017-04-19
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/dt64 ARM64: DT: Hisilicon SoC DT updates for 4.12 - Reset the hi6220 mmc hosts to avoid hang - Add the binding for the hi3798cv200 SoC and the poplar board - Add basic dts files to support the hi3798cv200 poplar board - Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board - Add driver strength MACRO for the hi3660 SoC - Add the pinctrl dtsi file for hikey960 board to configure the pins * tag 'hisi-arm64-dt-for-4.12' of git://github.com/hisilicon/linux-hisi: arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board arm64: dts: hisi: add SAS nodes for the hip07 SoC arm64: dts: hisi: add RoCE nodes for the hip07 SoC arm64: dts: hisi: add network related nodes for the hip07 SoC arm64: dts: hisi: add mbigen nodes for the hip07 SoC arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board arm64: dts: hi6220: Reset the mmc hosts Signed-off-by: Olof Johansson <olof@lixom.net>
| * | arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development boardWang Xiaoyin2017-04-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add pinctrl dtsi file for HiKey960 development board, enable 5 pinmux devices and 1 pinconf device, also include some nodes of configurations for pins. Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| * | arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoCWang Xiaoyin2017-04-10
| | | | | | | | | | | | | | | | | | | | | Extend drive strength levels of the pins for Hi3660 Soc. Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| * | arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 boardWei Xu2017-04-10
| | | | | | | | | | | | | | | | | | | | | Enable the NIC and SAS nodes for the hip07-d05 board to support related functions. Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| * | arm64: dts: hisi: add SAS nodes for the hip07 SoCWei Xu2017-04-08
| | | | | | | | | | | | | | | | | | | | | Add 3 SAS host controller nodes and the dependent subctrl node to enable the SAS and SATA function for the hip07 SoC. Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| * | arm64: dts: hisi: add RoCE nodes for the hip07 SoCWei Xu2017-04-07
| | | | | | | | | | | | | | | | | | | | | Add the infiniband node to support the RoCE function on the hip07 SoC. Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| * | arm64: dts: hisi: add network related nodes for the hip07 SoCWei Xu2017-04-07
| | | | | | | | | | | | | | | | | | | | | Add MDIO, SerDes, Port and realted HNS nodes to support the network on the hip07 SoC. Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| * | arm64: dts: hisi: add mbigen nodes for the hip07 SoCWei Xu2017-04-07
| | | | | | | | | | | | | | | | | | | | | Add mbigen nodes for the hip07 SoC those will be used for the SAS, XGE and PCIe host controllers. Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| * | arm64: dts: hisilicon: add dts files for hi3798cv200-poplar boardJiancheng Xue2017-04-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic dts files for hi3798cv200-poplar board. Poplar is the first development board compliant with the 96Boards Enterprise Edition TV Platform specification. The board features the Hi3798CV200 with an integrated quad-core 64-bit ARM Cortex A53 processor and high performance Mali T720 GPU. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Reviewed-by: Alex Elder <elder@linaro.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| * | dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar boardJiancheng Xue2017-04-06
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add bindings for HiSilicon hi3798cv200 SoC and Poplar Board. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Reviewed-by: Alex Elder <elder@linaro.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
| * | arm64: dts: hi6220: Reset the mmc hostsDaniel Lezcano2017-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MMC hosts could be left in an unconsistent or uninitialized state from the firmware. Instead of assuming, the firmware did the right things, let's reset the host controllers. This change fixes a bug when the mmc2/sdio is initialized leading to a hung task: [ 242.704294] INFO: task kworker/7:1:675 blocked for more than 120 seconds. [ 242.711129] Not tainted 4.9.0-rc8-00017-gcf0251f #3 [ 242.716571] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 242.724435] kworker/7:1 D 0 675 2 0x00000000 [ 242.729973] Workqueue: events_freezable mmc_rescan [ 242.734796] Call trace: [ 242.737269] [<ffff00000808611c>] __switch_to+0xa8/0xb4 [ 242.742437] [<ffff000008d07c04>] __schedule+0x1c0/0x67c [ 242.747689] [<ffff000008d08254>] schedule+0x40/0xa0 [ 242.752594] [<ffff000008d0b284>] schedule_timeout+0x1c4/0x35c [ 242.758366] [<ffff000008d08e38>] wait_for_common+0xd0/0x15c [ 242.763964] [<ffff000008d09008>] wait_for_completion+0x28/0x34 [ 242.769825] [<ffff000008a1a9f4>] mmc_wait_for_req_done+0x40/0x124 [ 242.775949] [<ffff000008a1ab98>] mmc_wait_for_req+0xc0/0xf8 [ 242.781549] [<ffff000008a1ac3c>] mmc_wait_for_cmd+0x6c/0x84 [ 242.787149] [<ffff000008a26610>] mmc_io_rw_direct_host+0x9c/0x114 [ 242.793270] [<ffff000008a26aa0>] sdio_reset+0x34/0x7c [ 242.798347] [<ffff000008a1d46c>] mmc_rescan+0x2fc/0x360 [ ... ] Cc: stable@vger.kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
* | | Merge tag 'zte-dt64-4.12' of ↵Olof Johansson2017-04-19
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64 ZTE arm64 device tree updates for 4.12: - Add mmc devices for ZX296718 SoC and enable those available on zx296718-evb board. - Add VOU controller device, output devices HDMI and TVENC, and enable display support for zx296718-evb board. - Remove pll_vga clock from ZX296718 device tree, as it's not a fixed rate clock. * tag 'zte-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: arm64: dts: zte: add tvenc device for zx296718 arm64: dts: zte: add vou and hdmi devices for zx296718 arm64: dts: zte: add mmc devices for zx296718 arm64: dts: zte: remove zx296718 pll_vga clock Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | arm64: dts: zte: add tvenc device for zx296718Shawn Guo2017-03-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It adds VOU tvenc device in zx296718.dtsi, so that boards with TV connector can enable the support by changing 'status' in board DTS file. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | arm64: dts: zte: add vou and hdmi devices for zx296718Shawn Guo2017-03-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | It adds VOU DPC device and enables HDMI support, which includes both display and audio through SPDIF interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | arm64: dts: zte: add mmc devices for zx296718Jun Nie2017-03-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add three mmc devices for zx296718 SoC, and enable the SD and eMMMC on zx296718-evb board. Signed-off-by: Jun Nie <jun.nie@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | arm64: dts: zte: remove zx296718 pll_vga clockShawn Guo2017-03-24
| |/ / | | | | | | | | | | | | | | | | | | | | | Rather than a fixed rate clock, pll_vga is a PLL can be programmed into different freqencies. Let's drop it from device tree and get it registered from clock driver. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | | Merge tag 'imx-dt64-4.12' of ↵Olof Johansson2017-04-19
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64 Freescale arm64 device tree updates for 4.12: - Add support of LS2088A SoC, which is a derivative of existing LS2080A SoC, and the major difference is on ARM cores. - Add support of LS1088A SoC which includes eight Cortex-A53 cores with 32 KB L1 D-cache and I-cache respectively. - Add crypto and thermal device support for LS1012A platform. - Add ECC register region for SATA device on LS1012A, LS1043A and LS1046A platforms. * tag 'imx-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: dt-bindings: arm: Add entry for FSL LS1088A RDB, QDS boards dt-bindings: clockgen: Add compatible string for LS1088A arm64: dts: Add support for FSL's LS1088A SoC arm64: dts: ls1012a: add crypto node arm64: dts: ls1012a: add thermal monitor node arm64: dts: updated sata node on ls1012a platform arm64: dts: added ecc register address to sata node on ls1046a arm64: dts: added ecc register address to sata node on ls1043a arm64: dts: freescale: ls2088a: Add DTS support for FSL's LS2088A SoC arm64: dts: freescale: ls2080a: Split devicetree for code resuability dt-bindings: Add compatible for LS2088A QDS and RDB board Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | dt-bindings: arm: Add entry for FSL LS1088A RDB, QDS boardsHarninder Rai2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | | dt-bindings: clockgen: Add compatible string for LS1088AHarninder Rai2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | | arm64: dts: Add support for FSL's LS1088A SoCHarninder Rai2017-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1088A contains eight ARM v8 CortexA53 processor cores with 32 KB L1-D cache and 32 KB L1-I cache Features summary Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs - Arranged as two clusters of four cores sharing a 1 MB L2 cache - Speed Up to 1.5 GHz - Support for cluster power-gating. Cache coherent interconnect (CCI-400) - Hardware-managed data coherency - Up to 700 MHz One 64-bit DDR4 SDRAM memory controller with ECC Data path acceleration architecture 2.0 (DPAA2) Three PCIe 3.0 controllers One serial ATA (SATA 3.0) controller Three high-speed USB 3.0 controllers with integrated PHY Following levels of DTSI/DTS files have been created for the LS1088A SoC family: - fsl-ls1088a.dtsi: DTS-Include file for NXP LS1088A SoC. - fsl-ls1088a-qds.dts: DTS file for NXP LS1088A QDS board. - fsl-ls1088a-rdb.dts: DTS file for NXP LS1088A RDB board Signed-off-by: Harninder Rai <harninder.rai@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>` Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | | arm64: dts: ls1012a: add crypto nodeHoria Geantă2017-03-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1012A has a SEC v5.4 security engine. Signed-off-by: Horia Geantă <horia.geanta@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | | arm64: dts: ls1012a: add thermal monitor nodeYuantian Tang2017-03-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a thermal monitoring unit on ls1012a soc which can monitor and record the temperature of cores so that appropriate actions can be taken or alarm the user when the temperature exceeds a programmed temperature threshold. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | | arm64: dts: updated sata node on ls1012a platformYuantian Tang2017-03-14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated sata node to add ecc register address and dma coherence property. Enable sata on ls1012a platforms as well. Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | | arm64: dts: added ecc register address to sata node on ls1046aTang Yuantian2017-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For ls1046 sata, ecc should be disabled due to a erratum. Provide the ecc register address for driver to use. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | | arm64: dts: added ecc register address to sata node on ls1043aTang Yuantian2017-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For ls1043 sata, ecc should be disabled due to a erratum. Provide the ecc register address for driver to use. Signed-off-by: Tang Yuantian <yuantian.tang@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | | arm64: dts: freescale: ls2088a: Add DTS support for FSL's LS2088A SoCAbhimanyu Saini2017-03-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the device tree support for FSL LS2088A SoC based on ARMv8 architecture. Following levels of DTSI/DTS files have been created for the LS2088A SoC family: - fsl-ls2088a.dtsi: DTS-Include file for FSL LS2088A SoC. - fsl-ls2088a-qds.dts: DTS file for FSL LS2088A QDS board. - fsl-ls2088a-rdb.dts: DTS file for FSL LS2088A RDB board. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | | arm64: dts: freescale: ls2080a: Split devicetree for code resuabilityAbhimanyu Saini2017-03-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2088A and LS2080A are similar SoCs with a few differences like ARM cores etc. Reorganize the LS2080A device tree to move the common nodes to: - fsl-ls208xa.dtsi - fsl-ls208xa-rdb.dtsi - fsl-ls208xa-qds.dtsi Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | | dt-bindings: Add compatible for LS2088A QDS and RDB boardAbhimanyu Saini2017-03-07
| |/ / | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Ashish Kumar <ashish.kumar@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | | Merge tag 'v4.12-rockchip-dts64-2' of ↵Olof Johansson2017-04-19
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64 Basic support for new rk3328, a 4-core Cortex-A53 soc and a fix for the default memory definition on the px5 eval board. While the bootloader should already override it with the actual amount, it's better to not carry around wrong values. * tag 'v4.12-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: fix the memory size of PX5 Evaluation board arm64: dts: rockchip: add RK3328 eavluation board devicetree dt-bindings: document rockchip rk3328-evb board arm64: dts: rockchip: add core dtsi file for RK3328 SoCs dt-bindings: add binding for rk3328-grf Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | arm64: dts: rockchip: fix the memory size of PX5 Evaluation boardAndy Yan2017-04-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board") sets the memory size to 2 GB, but this board only has 1 GB DRAM, so change it to the correct value here. Fixes: 122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board") Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | | arm64: dts: rockchip: add RK3328 eavluation board devicetreeLiang Chen2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add rk3328-evb.dts for RK3328 evaluation board. Tested on RK3328 evb. Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | | dt-bindings: document rockchip rk3328-evb boardLiang Chen2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use "rockchip,rk3328-evb" compatible string for Rockchip RK3328 evaluation board. Signed-off-by: Liang Chen <cl@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | | arm64: dts: rockchip: add core dtsi file for RK3328 SoCsLiang Chen2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds core dtsi file for Rockchip RK3328 SoCs. Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | | dt-bindings: add binding for rk3328-grfLiang Chen2017-04-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the compatible for the General Register Files on the new rk3328. Signed-off-by: Liang Chen <cl@rock-chips.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | | | Merge tag 'samsung-dt64-4.12' of ↵Olof Johansson2017-04-19
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64 Samsung DeviceTree ARM64 update for v4.12: 1. Add IR, touchscreen and panel to TM2/TM2E boards. 2. Add proper clock frequency properties to DSI nodes. * tag 'samsung-dt64-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: dts: exynos: Add the burst and esc clock frequency properties to DSI node arm64: dts: exynos: Add support for S6E3HA2 panel device on TM2 board arm64: dts: exynos: Add stmfts touchscreen node for TM2 and TM2E arm64: dts: exynos: Enable ir-spi in the TM2 and TM2E boards Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | arm64: dts: exynos: Add the burst and esc clock frequency properties to DSI nodeHoegeun Kwon2017-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the burst and esc clock frequency properties to the parent (DSI node). Currently the clock is parsed from the port node, while it should be taken from the dsi node. Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Reviewed-by: Andi Shyti <andi.shyti@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| * | | | arm64: dts: exynos: Add support for S6E3HA2 panel device on TM2 boardHyungwon Hwang2017-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add the panel device tree node for S6E3HA2 display controller to TM2 dts. Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| * | | | arm64: dts: exynos: Add stmfts touchscreen node for TM2 and TM2EAndi Shyti2017-03-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TM2 and TM2E devices are provided with a ST-Microelectronics Finger Tip S device with small differences: - screen size - TM2E uses the stmfts also as a touchkey for "back" and "menu" In this commit the initial value of the interrupt line is set to EXYNOS_PIN_PULL_UP as the interrupt is triggered when the line goes down. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
| * | | | arm64: dts: exynos: Enable ir-spi in the TM2 and TM2E boardsAndi Shyti2017-03-07
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the device tree node for the ir-spi driver which enables the IR LED for remote controlling. This patch sets first the GPR3[3] gpio line as a regulator-fixed for enabling an external regulator which powers the IR LED. Removes also the default assignment of GPG3[7] related to the MOSI line of the SPI3 bus. Signed-off-by: Andi Shyti <andi.shyti@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
* | | | Merge tag 'renesas-arm64-dt2-for-v4.12' of ↵Olof Johansson2017-04-19
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64 Second Round of Renesas ARM64 Based SoC DT Updates for v4.12 Corrections: * r8a7795: Correct SATA device size to 2MiB for r8a7795 SoC Cleanup: * Drop _clk suffix from X12 clock node name for r8a7795 SoC Enhancements: * Add reset control properties for r8a779[56] * tag 'renesas-arm64-dt2-for-v4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: arm64: dts: r8a7795: salvator-x: Drop _clk suffix from X12 clock node name arm64: dts: r8a7796: Add reset control properties arm64: dts: r8a7795: Add reset control properties arm64: dts: r8a7795: Correct SATA device size to 2MiB Signed-off-by: Olof Johansson <olof@lixom.net>
| * | | | arm64: dts: r8a7795: salvator-x: Drop _clk suffix from X12 clock node nameGeert Uytterhoeven2017-04-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current practice is to not add _clk suffixes to clock node names in DT, as these names are used as the actual clock names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | arm64: dts: r8a7796: Add reset control propertiesGeert Uytterhoeven2017-03-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that all resets added match the corresponding module clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | arm64: dts: r8a7795: Add reset control propertiesGeert Uytterhoeven2017-03-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that all resets added match the corresponding module clocks. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| * | | | arm64: dts: r8a7795: Correct SATA device size to 2MiBMagnus Damm2017-03-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the r8a7795 SATA device node to use a 2MiB I/O space as specified in the "72. Serial-ATA" section of R-Car-Gen3-rev0.52E.pdf Signed-off-by: Magnus Damm <damm+renesas@opensource.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-28 19:43:34 -0400