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authorOlof Johansson <olof@lixom.net>2017-04-19 09:33:03 -0400
committerOlof Johansson <olof@lixom.net>2017-04-19 09:33:03 -0400
commitab719074fa14666139376d6b6e5e0e75325d582f (patch)
tree99f7bcacfc960f3813ae477a5ebf231b99001461
parenteeef69c9eba4171397ea45db5a296775aa88e582 (diff)
parent2f513bd9eac1a2642b40387d4f89c3987641e59b (diff)
Merge tag 'v4.12-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
Basic support for new rk3328, a 4-core Cortex-A53 soc and a fix for the default memory definition on the px5 eval board. While the bootloader should already override it with the actual amount, it's better to not carry around wrong values. * tag 'v4.12-rockchip-dts64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm64: dts: rockchip: fix the memory size of PX5 Evaluation board arm64: dts: rockchip: add RK3328 eavluation board devicetree dt-bindings: document rockchip rk3328-evb board arm64: dts: rockchip: add core dtsi file for RK3328 SoCs dt-bindings: add binding for rk3328-grf Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/arm/rockchip.txt4
-rw-r--r--Documentation/devicetree/bindings/soc/rockchip/grf.txt1
-rw-r--r--arch/arm64/boot/dts/rockchip/Makefile1
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3328-evb.dts57
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3328.dtsi1264
-rw-r--r--arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts2
6 files changed, 1328 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index d05caa6ee89d..3ad9482f7859 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -154,6 +154,10 @@ Rockchip platforms device tree bindings
154 Required root node properties: 154 Required root node properties:
155 - compatible = "rockchip,rk3288-fennec", "rockchip,rk3288"; 155 - compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
156 156
157- Rockchip RK3328 evb:
158 Required root node properties:
159 - compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
160
157- Rockchip RK3399 evb: 161- Rockchip RK3399 evb:
158 Required root node properties: 162 Required root node properties:
159 - compatible = "rockchip,rk3399-evb", "rockchip,rk3399"; 163 - compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.txt b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
index a0685c209218..de8b983f2ccd 100644
--- a/Documentation/devicetree/bindings/soc/rockchip/grf.txt
+++ b/Documentation/devicetree/bindings/soc/rockchip/grf.txt
@@ -16,6 +16,7 @@ Required Properties:
16 - "rockchip,rk3188-grf", "syscon": for rk3188 16 - "rockchip,rk3188-grf", "syscon": for rk3188
17 - "rockchip,rk3228-grf", "syscon": for rk3228 17 - "rockchip,rk3228-grf", "syscon": for rk3228
18 - "rockchip,rk3288-grf", "syscon": for rk3288 18 - "rockchip,rk3288-grf", "syscon": for rk3288
19 - "rockchip,rk3328-grf", "syscon": for rk3328
19 - "rockchip,rk3368-grf", "syscon": for rk3368 20 - "rockchip,rk3368-grf", "syscon": for rk3368
20 - "rockchip,rk3399-grf", "syscon": for rk3399 21 - "rockchip,rk3399-grf", "syscon": for rk3399
21- compatible: PMUGRF should be one of the following: 22- compatible: PMUGRF should be one of the following:
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index b82f7b61ab6f..b5636bba6b1c 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -1,3 +1,4 @@
1dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
1dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb 2dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
2dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb 3dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
3dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb 4dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3328-evb.dts b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
new file mode 100644
index 000000000000..cf272392cebf
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328-evb.dts
@@ -0,0 +1,57 @@
1/*
2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/dts-v1/;
44#include "rk3328.dtsi"
45
46/ {
47 model = "Rockchip RK3328 EVB";
48 compatible = "rockchip,rk3328-evb", "rockchip,rk3328";
49
50 chosen {
51 stdout-path = "serial2:1500000n8";
52 };
53};
54
55&uart2 {
56 status = "okay";
57};
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
new file mode 100644
index 000000000000..7e69f1fe78d6
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
@@ -0,0 +1,1264 @@
1/*
2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43#include <dt-bindings/clock/rk3328-cru.h>
44#include <dt-bindings/gpio/gpio.h>
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46#include <dt-bindings/interrupt-controller/irq.h>
47#include <dt-bindings/pinctrl/rockchip.h>
48#include <dt-bindings/power/rk3328-power.h>
49#include <dt-bindings/soc/rockchip,boot-mode.h>
50
51/ {
52 compatible = "rockchip,rk3328";
53
54 interrupt-parent = <&gic>;
55 #address-cells = <2>;
56 #size-cells = <2>;
57
58 aliases {
59 serial0 = &uart0;
60 serial1 = &uart1;
61 serial2 = &uart2;
62 i2c0 = &i2c0;
63 i2c1 = &i2c1;
64 i2c2 = &i2c2;
65 i2c3 = &i2c3;
66 };
67
68 cpus {
69 #address-cells = <2>;
70 #size-cells = <0>;
71
72 cpu0: cpu@0 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a53", "arm,armv8";
75 reg = <0x0 0x0>;
76 clocks = <&cru ARMCLK>;
77 enable-method = "psci";
78 next-level-cache = <&l2>;
79 };
80
81 cpu1: cpu@1 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a53", "arm,armv8";
84 reg = <0x0 0x1>;
85 clocks = <&cru ARMCLK>;
86 enable-method = "psci";
87 next-level-cache = <&l2>;
88 };
89
90 cpu2: cpu@2 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a53", "arm,armv8";
93 reg = <0x0 0x2>;
94 clocks = <&cru ARMCLK>;
95 enable-method = "psci";
96 next-level-cache = <&l2>;
97 };
98
99 cpu3: cpu@3 {
100 device_type = "cpu";
101 compatible = "arm,cortex-a53", "arm,armv8";
102 reg = <0x0 0x3>;
103 clocks = <&cru ARMCLK>;
104 enable-method = "psci";
105 next-level-cache = <&l2>;
106 };
107
108 l2: l2-cache0 {
109 compatible = "cache";
110 };
111 };
112
113 amba {
114 compatible = "simple-bus";
115 #address-cells = <2>;
116 #size-cells = <2>;
117 ranges;
118
119 dmac: dmac@ff1f0000 {
120 compatible = "arm,pl330", "arm,primecell";
121 reg = <0x0 0xff1f0000 0x0 0x4000>;
122 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
124 clocks = <&cru ACLK_DMAC>;
125 clock-names = "apb_pclk";
126 #dma-cells = <1>;
127 };
128 };
129
130 arm-pmu {
131 compatible = "arm,cortex-a53-pmu";
132 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
136 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
137 };
138
139 psci {
140 compatible = "arm,psci-1.0", "arm,psci-0.2";
141 method = "smc";
142 };
143
144 timer {
145 compatible = "arm,armv8-timer";
146 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
147 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
148 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
149 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
150 };
151
152 xin24m: xin24m {
153 compatible = "fixed-clock";
154 #clock-cells = <0>;
155 clock-frequency = <24000000>;
156 clock-output-names = "xin24m";
157 };
158
159 grf: syscon@ff100000 {
160 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
161 reg = <0x0 0xff100000 0x0 0x1000>;
162 #address-cells = <1>;
163 #size-cells = <1>;
164
165 power: power-controller {
166 compatible = "rockchip,rk3328-power-controller";
167 #power-domain-cells = <1>;
168 #address-cells = <1>;
169 #size-cells = <0>;
170
171 pd_hevc@RK3328_PD_HEVC {
172 reg = <RK3328_PD_HEVC>;
173 };
174 pd_video@RK3328_PD_VIDEO {
175 reg = <RK3328_PD_VIDEO>;
176 };
177 pd_vpu@RK3328_PD_VPU {
178 reg = <RK3328_PD_VPU>;
179 };
180 };
181
182 reboot-mode {
183 compatible = "syscon-reboot-mode";
184 offset = <0x5c8>;
185 mode-normal = <BOOT_NORMAL>;
186 mode-recovery = <BOOT_RECOVERY>;
187 mode-bootloader = <BOOT_FASTBOOT>;
188 mode-loader = <BOOT_BL_DOWNLOAD>;
189 };
190
191 };
192
193 uart0: serial@ff110000 {
194 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
195 reg = <0x0 0xff110000 0x0 0x100>;
196 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
197 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
198 clock-names = "baudclk", "apb_pclk";
199 dmas = <&dmac 2>, <&dmac 3>;
200 #dma-cells = <2>;
201 pinctrl-names = "default";
202 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
203 reg-io-width = <4>;
204 reg-shift = <2>;
205 status = "disabled";
206 };
207
208 uart1: serial@ff120000 {
209 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
210 reg = <0x0 0xff120000 0x0 0x100>;
211 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
212 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
213 clock-names = "sclk_uart", "pclk_uart";
214 dmas = <&dmac 4>, <&dmac 5>;
215 #dma-cells = <2>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
218 reg-io-width = <4>;
219 reg-shift = <2>;
220 status = "disabled";
221 };
222
223 uart2: serial@ff130000 {
224 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
225 reg = <0x0 0xff130000 0x0 0x100>;
226 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
228 clock-names = "baudclk", "apb_pclk";
229 dmas = <&dmac 6>, <&dmac 7>;
230 #dma-cells = <2>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&uart2m1_xfer>;
233 reg-io-width = <4>;
234 reg-shift = <2>;
235 status = "disabled";
236 };
237
238 i2c0: i2c@ff150000 {
239 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
240 reg = <0x0 0xff150000 0x0 0x1000>;
241 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
242 #address-cells = <1>;
243 #size-cells = <0>;
244 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
245 clock-names = "i2c", "pclk";
246 pinctrl-names = "default";
247 pinctrl-0 = <&i2c0_xfer>;
248 status = "disabled";
249 };
250
251 i2c1: i2c@ff160000 {
252 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
253 reg = <0x0 0xff160000 0x0 0x1000>;
254 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
255 #address-cells = <1>;
256 #size-cells = <0>;
257 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
258 clock-names = "i2c", "pclk";
259 pinctrl-names = "default";
260 pinctrl-0 = <&i2c1_xfer>;
261 status = "disabled";
262 };
263
264 i2c2: i2c@ff170000 {
265 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
266 reg = <0x0 0xff170000 0x0 0x1000>;
267 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
268 #address-cells = <1>;
269 #size-cells = <0>;
270 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
271 clock-names = "i2c", "pclk";
272 pinctrl-names = "default";
273 pinctrl-0 = <&i2c2_xfer>;
274 status = "disabled";
275 };
276
277 i2c3: i2c@ff180000 {
278 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
279 reg = <0x0 0xff180000 0x0 0x1000>;
280 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
284 clock-names = "i2c", "pclk";
285 pinctrl-names = "default";
286 pinctrl-0 = <&i2c3_xfer>;
287 status = "disabled";
288 };
289
290 spi0: spi@ff190000 {
291 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
292 reg = <0x0 0xff190000 0x0 0x1000>;
293 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
294 #address-cells = <1>;
295 #size-cells = <0>;
296 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
297 clock-names = "spiclk", "apb_pclk";
298 dmas = <&dmac 8>, <&dmac 9>;
299 dma-names = "tx", "rx";
300 pinctrl-names = "default";
301 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
302 status = "disabled";
303 };
304
305 wdt: watchdog@ff1a0000 {
306 compatible = "snps,dw-wdt";
307 reg = <0x0 0xff1a0000 0x0 0x100>;
308 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
309 };
310
311 saradc: adc@ff280000 {
312 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
313 reg = <0x0 0xff280000 0x0 0x100>;
314 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
315 #io-channel-cells = <1>;
316 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
317 clock-names = "saradc", "apb_pclk";
318 resets = <&cru SRST_SARADC_P>;
319 reset-names = "saradc-apb";
320 status = "disabled";
321 };
322
323 cru: clock-controller@ff440000 {
324 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
325 reg = <0x0 0xff440000 0x0 0x1000>;
326 rockchip,grf = <&grf>;
327 #clock-cells = <1>;
328 #reset-cells = <1>;
329 assigned-clocks =
330 /*
331 * CPLL should run at 1200, but that is to high for
332 * the initial dividers of most of its children.
333 * We need set cpll child clk div first,
334 * and then set the cpll frequency.
335 */
336 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
337 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
338 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
339 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
340 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
341 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
342 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
343 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
344 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
345 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
346 <&cru SCLK_WIFI>, <&cru ARMCLK>,
347 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
348 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
349 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
350 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
351 <&cru SCLK_RTC32K>;
352 assigned-clock-parents =
353 <&cru HDMIPHY>, <&cru PLL_APLL>,
354 <&cru PLL_GPLL>, <&xin24m>,
355 <&xin24m>, <&xin24m>;
356 assigned-clock-rates =
357 <0>, <61440000>,
358 <0>, <24000000>,
359 <24000000>, <24000000>,
360 <15000000>, <15000000>,
361 <100000000>, <100000000>,
362 <100000000>, <100000000>,
363 <50000000>, <100000000>,
364 <100000000>, <100000000>,
365 <50000000>, <50000000>,
366 <50000000>, <50000000>,
367 <24000000>, <600000000>,
368 <491520000>, <1200000000>,
369 <150000000>, <75000000>,
370 <75000000>, <150000000>,
371 <75000000>, <75000000>,
372 <32768>;
373 };
374
375 gmac2io: ethernet@ff540000 {
376 compatible = "rockchip,rk3328-gmac";
377 reg = <0x0 0xff540000 0x0 0x10000>;
378 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
379 interrupt-names = "macirq";
380 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
381 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
382 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
383 <&cru PCLK_MAC2IO>;
384 clock-names = "stmmaceth", "mac_clk_rx",
385 "mac_clk_tx", "clk_mac_ref",
386 "clk_mac_refout", "aclk_mac",
387 "pclk_mac";
388 resets = <&cru SRST_GMAC2IO_A>;
389 reset-names = "stmmaceth";
390 rockchip,grf = <&grf>;
391 status = "disabled";
392 };
393
394 gic: interrupt-controller@ff811000 {
395 compatible = "arm,gic-400";
396 #interrupt-cells = <3>;
397 #address-cells = <0>;
398 interrupt-controller;
399 reg = <0x0 0xff811000 0 0x1000>,
400 <0x0 0xff812000 0 0x2000>,
401 <0x0 0xff814000 0 0x2000>,
402 <0x0 0xff816000 0 0x2000>;
403 interrupts = <GIC_PPI 9
404 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
405 };
406
407 pinctrl: pinctrl {
408 compatible = "rockchip,rk3328-pinctrl";
409 rockchip,grf = <&grf>;
410 #address-cells = <2>;
411 #size-cells = <2>;
412 ranges;
413
414 gpio0: gpio0@ff210000 {
415 compatible = "rockchip,gpio-bank";
416 reg = <0x0 0xff210000 0x0 0x100>;
417 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&cru PCLK_GPIO0>;
419
420 gpio-controller;
421 #gpio-cells = <2>;
422
423 interrupt-controller;
424 #interrupt-cells = <2>;
425 };
426
427 gpio1: gpio1@ff220000 {
428 compatible = "rockchip,gpio-bank";
429 reg = <0x0 0xff220000 0x0 0x100>;
430 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&cru PCLK_GPIO1>;
432
433 gpio-controller;
434 #gpio-cells = <2>;
435
436 interrupt-controller;
437 #interrupt-cells = <2>;
438 };
439
440 gpio2: gpio2@ff230000 {
441 compatible = "rockchip,gpio-bank";
442 reg = <0x0 0xff230000 0x0 0x100>;
443 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
444 clocks = <&cru PCLK_GPIO2>;
445
446 gpio-controller;
447 #gpio-cells = <2>;
448
449 interrupt-controller;
450 #interrupt-cells = <2>;
451 };
452
453 gpio3: gpio3@ff240000 {
454 compatible = "rockchip,gpio-bank";
455 reg = <0x0 0xff240000 0x0 0x100>;
456 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&cru PCLK_GPIO3>;
458
459 gpio-controller;
460 #gpio-cells = <2>;
461
462 interrupt-controller;
463 #interrupt-cells = <2>;
464 };
465
466 pcfg_pull_up: pcfg-pull-up {
467 bias-pull-up;
468 };
469
470 pcfg_pull_down: pcfg-pull-down {
471 bias-pull-down;
472 };
473
474 pcfg_pull_none: pcfg-pull-none {
475 bias-disable;
476 };
477
478 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
479 bias-disable;
480 drive-strength = <2>;
481 };
482
483 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
484 bias-pull-up;
485 drive-strength = <2>;
486 };
487
488 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
489 bias-pull-up;
490 drive-strength = <4>;
491 };
492
493 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
494 bias-disable;
495 drive-strength = <4>;
496 };
497
498 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
499 bias-pull-down;
500 drive-strength = <4>;
501 };
502
503 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
504 bias-disable;
505 drive-strength = <8>;
506 };
507
508 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
509 bias-pull-up;
510 drive-strength = <8>;
511 };
512
513 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
514 bias-disable;
515 drive-strength = <12>;
516 };
517
518 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
519 bias-pull-up;
520 drive-strength = <12>;
521 };
522
523 pcfg_output_high: pcfg-output-high {
524 output-high;
525 };
526
527 pcfg_output_low: pcfg-output-low {
528 output-low;
529 };
530
531 pcfg_input_high: pcfg-input-high {
532 bias-pull-up;
533 input-enable;
534 };
535
536 pcfg_input: pcfg-input {
537 input-enable;
538 };
539
540 i2c0 {
541 i2c0_xfer: i2c0-xfer {
542 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
543 <2 RK_PD1 1 &pcfg_pull_none>;
544 };
545 };
546
547 i2c1 {
548 i2c1_xfer: i2c1-xfer {
549 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
550 <2 RK_PA5 2 &pcfg_pull_none>;
551 };
552 };
553
554 i2c2 {
555 i2c2_xfer: i2c2-xfer {
556 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
557 <2 RK_PB6 1 &pcfg_pull_none>;
558 };
559 };
560
561 i2c3 {
562 i2c3_xfer: i2c3-xfer {
563 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
564 <0 RK_PA6 2 &pcfg_pull_none>;
565 };
566 i2c3_gpio: i2c3-gpio {
567 rockchip,pins =
568 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
569 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
570 };
571 };
572
573 hdmi_i2c {
574 hdmii2c_xfer: hdmii2c-xfer {
575 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
576 <0 RK_PA6 1 &pcfg_pull_none>;
577 };
578 };
579
580 tsadc {
581 otp_gpio: otp-gpio {
582 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
583 };
584
585 otp_out: otp-out {
586 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
587 };
588 };
589
590 uart0 {
591 uart0_xfer: uart0-xfer {
592 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
593 <1 RK_PB0 1 &pcfg_pull_none>;
594 };
595
596 uart0_cts: uart0-cts {
597 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
598 };
599
600 uart0_rts: uart0-rts {
601 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
602 };
603
604 uart0_rts_gpio: uart0-rts-gpio {
605 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
606 };
607 };
608
609 uart1 {
610 uart1_xfer: uart1-xfer {
611 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
612 <3 RK_PA6 4 &pcfg_pull_none>;
613 };
614
615 uart1_cts: uart1-cts {
616 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
617 };
618
619 uart1_rts: uart1-rts {
620 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
621 };
622
623 uart1_rts_gpio: uart1-rts-gpio {
624 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
625 };
626 };
627
628 uart2-0 {
629 uart2m0_xfer: uart2m0-xfer {
630 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
631 <1 RK_PA1 2 &pcfg_pull_none>;
632 };
633 };
634
635 uart2-1 {
636 uart2m1_xfer: uart2m1-xfer {
637 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
638 <2 RK_PA1 1 &pcfg_pull_none>;
639 };
640 };
641
642 spi0-0 {
643 spi0m0_clk: spi0m0-clk {
644 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
645 };
646
647 spi0m0_cs0: spi0m0-cs0 {
648 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
649 };
650
651 spi0m0_tx: spi0m0-tx {
652 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
653 };
654
655 spi0m0_rx: spi0m0-rx {
656 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
657 };
658
659 spi0m0_cs1: spi0m0-cs1 {
660 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
661 };
662 };
663
664 spi0-1 {
665 spi0m1_clk: spi0m1-clk {
666 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
667 };
668
669 spi0m1_cs0: spi0m1-cs0 {
670 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
671 };
672
673 spi0m1_tx: spi0m1-tx {
674 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
675 };
676
677 spi0m1_rx: spi0m1-rx {
678 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
679 };
680
681 spi0m1_cs1: spi0m1-cs1 {
682 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
683 };
684 };
685
686 spi0-2 {
687 spi0m2_clk: spi0m2-clk {
688 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
689 };
690
691 spi0m2_cs0: spi0m2-cs0 {
692 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
693 };
694
695 spi0m2_tx: spi0m2-tx {
696 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
697 };
698
699 spi0m2_rx: spi0m2-rx {
700 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
701 };
702 };
703
704 i2s1 {
705 i2s1_mclk: i2s1-mclk {
706 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
707 };
708
709 i2s1_sclk: i2s1-sclk {
710 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
711 };
712
713 i2s1_lrckrx: i2s1-lrckrx {
714 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
715 };
716
717 i2s1_lrcktx: i2s1-lrcktx {
718 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
719 };
720
721 i2s1_sdi: i2s1-sdi {
722 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
723 };
724
725 i2s1_sdo: i2s1-sdo {
726 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
727 };
728
729 i2s1_sdio1: i2s1-sdio1 {
730 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
731 };
732
733 i2s1_sdio2: i2s1-sdio2 {
734 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
735 };
736
737 i2s1_sdio3: i2s1-sdio3 {
738 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
739 };
740
741 i2s1_sleep: i2s1-sleep {
742 rockchip,pins =
743 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
744 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
745 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
746 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
747 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
748 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
749 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
750 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
751 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
752 };
753 };
754
755 i2s2-0 {
756 i2s2m0_mclk: i2s2m0-mclk {
757 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
758 };
759
760 i2s2m0_sclk: i2s2m0-sclk {
761 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
762 };
763
764 i2s2m0_lrckrx: i2s2m0-lrckrx {
765 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
766 };
767
768 i2s2m0_lrcktx: i2s2m0-lrcktx {
769 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
770 };
771
772 i2s2m0_sdi: i2s2m0-sdi {
773 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
774 };
775
776 i2s2m0_sdo: i2s2m0-sdo {
777 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
778 };
779
780 i2s2m0_sleep: i2s2m0-sleep {
781 rockchip,pins =
782 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
783 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
784 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
785 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
786 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
787 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
788 };
789 };
790
791 i2s2-1 {
792 i2s2m1_mclk: i2s2m1-mclk {
793 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
794 };
795
796 i2s2m1_sclk: i2s2m1-sclk {
797 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
798 };
799
800 i2s2m1_lrckrx: i2sm1-lrckrx {
801 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
802 };
803
804 i2s2m1_lrcktx: i2s2m1-lrcktx {
805 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
806 };
807
808 i2s2m1_sdi: i2s2m1-sdi {
809 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
810 };
811
812 i2s2m1_sdo: i2s2m1-sdo {
813 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
814 };
815
816 i2s2m1_sleep: i2s2m1-sleep {
817 rockchip,pins =
818 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
819 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
820 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
821 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
822 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
823 };
824 };
825
826 spdif-0 {
827 spdifm0_tx: spdifm0-tx {
828 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
829 };
830 };
831
832 spdif-1 {
833 spdifm1_tx: spdifm1-tx {
834 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
835 };
836 };
837
838 spdif-2 {
839 spdifm2_tx: spdifm2-tx {
840 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
841 };
842 };
843
844 sdmmc0-0 {
845 sdmmc0m0_pwren: sdmmc0m0-pwren {
846 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
847 };
848
849 sdmmc0m0_gpio: sdmmc0m0-gpio {
850 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
851 };
852 };
853
854 sdmmc0-1 {
855 sdmmc0m1_pwren: sdmmc0m1-pwren {
856 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
857 };
858
859 sdmmc0m1_gpio: sdmmc0m1-gpio {
860 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
861 };
862 };
863
864 sdmmc0 {
865 sdmmc0_clk: sdmmc0-clk {
866 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_4ma>;
867 };
868
869 sdmmc0_cmd: sdmmc0-cmd {
870 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
871 };
872
873 sdmmc0_dectn: sdmmc0-dectn {
874 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
875 };
876
877 sdmmc0_wrprt: sdmmc0-wrprt {
878 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
879 };
880
881 sdmmc0_bus1: sdmmc0-bus1 {
882 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
883 };
884
885 sdmmc0_bus4: sdmmc0-bus4 {
886 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
887 <1 RK_PA1 1 &pcfg_pull_up_4ma>,
888 <1 RK_PA2 1 &pcfg_pull_up_4ma>,
889 <1 RK_PA3 1 &pcfg_pull_up_4ma>;
890 };
891
892 sdmmc0_gpio: sdmmc0-gpio {
893 rockchip,pins =
894 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
895 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
896 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
897 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
898 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
899 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
900 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
901 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
902 };
903 };
904
905 sdmmc0ext {
906 sdmmc0ext_clk: sdmmc0ext-clk {
907 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
908 };
909
910 sdmmc0ext_cmd: sdmmc0ext-cmd {
911 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
912 };
913
914 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
915 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
916 };
917
918 sdmmc0ext_dectn: sdmmc0ext-dectn {
919 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
920 };
921
922 sdmmc0ext_bus1: sdmmc0ext-bus1 {
923 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
924 };
925
926 sdmmc0ext_bus4: sdmmc0ext-bus4 {
927 rockchip,pins =
928 <3 RK_PA4 3 &pcfg_pull_up_4ma>,
929 <3 RK_PA5 3 &pcfg_pull_up_4ma>,
930 <3 RK_PA6 3 &pcfg_pull_up_4ma>,
931 <3 RK_PA7 3 &pcfg_pull_up_4ma>;
932 };
933
934 sdmmc0ext_gpio: sdmmc0ext-gpio {
935 rockchip,pins =
936 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
937 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
938 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
939 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
940 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
941 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
942 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
943 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
944 };
945 };
946
947 sdmmc1 {
948 sdmmc1_clk: sdmmc1-clk {
949 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
950 };
951
952 sdmmc1_cmd: sdmmc1-cmd {
953 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
954 };
955
956 sdmmc1_pwren: sdmmc1-pwren {
957 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
958 };
959
960 sdmmc1_wrprt: sdmmc1-wrprt {
961 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
962 };
963
964 sdmmc1_dectn: sdmmc1-dectn {
965 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
966 };
967
968 sdmmc1_bus1: sdmmc1-bus1 {
969 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
970 };
971
972 sdmmc1_bus4: sdmmc1-bus4 {
973 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
974 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
975 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
976 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
977 };
978
979 sdmmc1_gpio: sdmmc1-gpio {
980 rockchip,pins =
981 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
982 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
983 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
984 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
985 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
986 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
987 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
988 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
989 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
990 };
991 };
992
993 emmc {
994 emmc_clk: emmc-clk {
995 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
996 };
997
998 emmc_cmd: emmc-cmd {
999 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1000 };
1001
1002 emmc_pwren: emmc-pwren {
1003 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1004 };
1005
1006 emmc_rstnout: emmc-rstnout {
1007 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1008 };
1009
1010 emmc_bus1: emmc-bus1 {
1011 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1012 };
1013
1014 emmc_bus4: emmc-bus4 {
1015 rockchip,pins =
1016 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1017 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1018 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1019 <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1020 };
1021
1022 emmc_bus8: emmc-bus8 {
1023 rockchip,pins =
1024 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1025 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1026 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1027 <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1028 <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1029 <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1030 <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1031 <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1032 };
1033 };
1034
1035 pwm0 {
1036 pwm0_pin: pwm0-pin {
1037 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1038 };
1039 };
1040
1041 pwm1 {
1042 pwm1_pin: pwm1-pin {
1043 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1044 };
1045 };
1046
1047 pwm2 {
1048 pwm2_pin: pwm2-pin {
1049 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1050 };
1051 };
1052
1053 pwmir {
1054 pwmir_pin: pwmir-pin {
1055 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1056 };
1057 };
1058
1059 gmac-1 {
1060 rgmiim1_pins: rgmiim1-pins {
1061 rockchip,pins =
1062 /* mac_txclk */
1063 <1 RK_PB4 2 &pcfg_pull_none_12ma>,
1064 /* mac_rxclk */
1065 <1 RK_PB5 2 &pcfg_pull_none_2ma>,
1066 /* mac_mdio */
1067 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1068 /* mac_txen */
1069 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1070 /* mac_clk */
1071 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1072 /* mac_rxdv */
1073 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1074 /* mac_mdc */
1075 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1076 /* mac_rxd1 */
1077 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1078 /* mac_rxd0 */
1079 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1080 /* mac_txd1 */
1081 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1082 /* mac_txd0 */
1083 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1084 /* mac_rxd3 */
1085 <1 RK_PB6 2 &pcfg_pull_none_2ma>,
1086 /* mac_rxd2 */
1087 <1 RK_PB7 2 &pcfg_pull_none_2ma>,
1088 /* mac_txd3 */
1089 <1 RK_PC0 2 &pcfg_pull_none_12ma>,
1090 /* mac_txd2 */
1091 <1 RK_PC1 2 &pcfg_pull_none_12ma>,
1092
1093 /* mac_txclk */
1094 <0 RK_PB0 1 &pcfg_pull_none>,
1095 /* mac_txen */
1096 <0 RK_PB4 1 &pcfg_pull_none>,
1097 /* mac_clk */
1098 <0 RK_PD0 1 &pcfg_pull_none>,
1099 /* mac_txd1 */
1100 <0 RK_PC0 1 &pcfg_pull_none>,
1101 /* mac_txd0 */
1102 <0 RK_PC1 1 &pcfg_pull_none>,
1103 /* mac_txd3 */
1104 <0 RK_PC7 1 &pcfg_pull_none>,
1105 /* mac_txd2 */
1106 <0 RK_PC6 1 &pcfg_pull_none>;
1107 };
1108
1109 rmiim1_pins: rmiim1-pins {
1110 rockchip,pins =
1111 /* mac_mdio */
1112 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1113 /* mac_txen */
1114 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1115 /* mac_clk */
1116 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1117 /* mac_rxer */
1118 <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1119 /* mac_rxdv */
1120 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1121 /* mac_mdc */
1122 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1123 /* mac_rxd1 */
1124 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1125 /* mac_rxd0 */
1126 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1127 /* mac_txd1 */
1128 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1129 /* mac_txd0 */
1130 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1131
1132 /* mac_mdio */
1133 <0 RK_PB3 1 &pcfg_pull_none>,
1134 /* mac_txen */
1135 <0 RK_PB4 1 &pcfg_pull_none>,
1136 /* mac_clk */
1137 <0 RK_PD0 1 &pcfg_pull_none>,
1138 /* mac_mdc */
1139 <0 RK_PC3 1 &pcfg_pull_none>,
1140 /* mac_txd1 */
1141 <0 RK_PC0 1 &pcfg_pull_none>,
1142 /* mac_txd0 */
1143 <0 RK_PC1 1 &pcfg_pull_none>;
1144 };
1145 };
1146
1147 gmac2phy {
1148 fephyled_speed100: fephyled-speed100 {
1149 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1150 };
1151
1152 fephyled_speed10: fephyled-speed10 {
1153 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1154 };
1155
1156 fephyled_duplex: fephyled-duplex {
1157 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1158 };
1159
1160 fephyled_rxm0: fephyled-rxm0 {
1161 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1162 };
1163
1164 fephyled_txm0: fephyled-txm0 {
1165 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1166 };
1167
1168 fephyled_linkm0: fephyled-linkm0 {
1169 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1170 };
1171
1172 fephyled_rxm1: fephyled-rxm1 {
1173 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1174 };
1175
1176 fephyled_txm1: fephyled-txm1 {
1177 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1178 };
1179
1180 fephyled_linkm1: fephyled-linkm1 {
1181 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1182 };
1183 };
1184
1185 tsadc_pin {
1186 tsadc_int: tsadc-int {
1187 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1188 };
1189 tsadc_gpio: tsadc-gpio {
1190 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1191 };
1192 };
1193
1194 hdmi_pin {
1195 hdmi_cec: hdmi-cec {
1196 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1197 };
1198
1199 hdmi_hpd: hdmi-hpd {
1200 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1201 };
1202 };
1203
1204 cif-0 {
1205 dvp_d2d9_m0:dvp-d2d9-m0 {
1206 rockchip,pins =
1207 /* cif_d0 */
1208 <3 RK_PA4 2 &pcfg_pull_none>,
1209 /* cif_d1 */
1210 <3 RK_PA5 2 &pcfg_pull_none>,
1211 /* cif_d2 */
1212 <3 RK_PA6 2 &pcfg_pull_none>,
1213 /* cif_d3 */
1214 <3 RK_PA7 2 &pcfg_pull_none>,
1215 /* cif_d4 */
1216 <3 RK_PB0 2 &pcfg_pull_none>,
1217 /* cif_d5m0 */
1218 <3 RK_PB1 2 &pcfg_pull_none>,
1219 /* cif_d6m0 */
1220 <3 RK_PB2 2 &pcfg_pull_none>,
1221 /* cif_d7m0 */
1222 <3 RK_PB3 2 &pcfg_pull_none>,
1223 /* cif_href */
1224 <3 RK_PA1 2 &pcfg_pull_none>,
1225 /* cif_vsync */
1226 <3 RK_PA0 2 &pcfg_pull_none>,
1227 /* cif_clkoutm0 */
1228 <3 RK_PA3 2 &pcfg_pull_none>,
1229 /* cif_clkin */
1230 <3 RK_PA2 2 &pcfg_pull_none>;
1231 };
1232 };
1233
1234 cif-1 {
1235 dvp_d2d9_m1:dvp-d2d9-m1 {
1236 rockchip,pins =
1237 /* cif_d0 */
1238 <3 RK_PA4 2 &pcfg_pull_none>,
1239 /* cif_d1 */
1240 <3 RK_PA5 2 &pcfg_pull_none>,
1241 /* cif_d2 */
1242 <3 RK_PA6 2 &pcfg_pull_none>,
1243 /* cif_d3 */
1244 <3 RK_PA7 2 &pcfg_pull_none>,
1245 /* cif_d4 */
1246 <3 RK_PB0 2 &pcfg_pull_none>,
1247 /* cif_d5m1 */
1248 <2 RK_PC0 4 &pcfg_pull_none>,
1249 /* cif_d6m1 */
1250 <2 RK_PC1 4 &pcfg_pull_none>,
1251 /* cif_d7m1 */
1252 <2 RK_PC2 4 &pcfg_pull_none>,
1253 /* cif_href */
1254 <3 RK_PA1 2 &pcfg_pull_none>,
1255 /* cif_vsync */
1256 <3 RK_PA0 2 &pcfg_pull_none>,
1257 /* cif_clkoutm1 */
1258 <2 RK_PB7 4 &pcfg_pull_none>,
1259 /* cif_clkin */
1260 <3 RK_PA2 2 &pcfg_pull_none>;
1261 };
1262 };
1263 };
1264};
diff --git a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
index 8cdb3bff9c55..ff48edd8e348 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3368-px5-evb.dts
@@ -53,7 +53,7 @@
53 }; 53 };
54 54
55 memory@0 { 55 memory@0 {
56 reg = <0x0 0x0 0x0 0x80000000>; 56 reg = <0x0 0x0 0x0 0x40000000>;
57 device_type = "memory"; 57 device_type = "memory";
58 }; 58 };
59 59
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-15 10:15:59 -0400