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* drm/msm: Trigger fence completion from GPUBjorn Andersson2018-03-19
| | | | | | | | | | | | | | | | | | | | Interrupt commands causes the CP to trigger an interrupt as the command is processed, regardless of the GPU being done processing previous commands. This is seen by the interrupt being delivered before the fence is written on 8974 and is likely the cause of the additional CP_WAIT_FOR_IDLE workaround found for a306, which would cause the CP to wait for the GPU to go idle before triggering the interrupt. Instead we can set the (undocumented) BIT(31) of the CACHE_FLUSH_TS which will cause a special CACHE_FLUSH_TS interrupt to be triggered from the GPU as the write event is processed. Add CACHE_FLUSH_TS to the IRQ masks of A3xx and A4xx and remove the workaround for A306. Suggested-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: fix direct caller of msm_gem_free_object()Rob Clark2018-03-19
| | | | | | | | This should be using drm_gem_object_put(). Also since this is done only in driver unload path, we don't need to synchronize setting tx_gem_obj to NULL, so juse use the _unlocked() variant. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: strip out msm_fence_cbRob Clark2018-03-19
| | | | | | Remnants of pre-dma_fence fencing which got left behind by mistake. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: rename mdp->dispRob Clark2018-03-19
| | | | | | | | | Since new display controller is called "dpu" instead of "mdp". Lets make the name of the toplevel directory for the display controllers a bit more generic. Signed-off-by: Rob Clark <robdclark@gmail.com> Reviewed-by: Sean Paul <seanpaul@chromium.org>
* drm/msm/dsi: Fix potential NULL pointer dereference in msm_dsi_modeset_initGustavo A. R. Silva2018-03-19
| | | | | | | | | | | | _dev_ is being dereferenced before it is null checked, hence there is a potential null pointer dereference. Fix this by moving the pointer dereference after _dev_ has been null checked. Fixes: d4e7f38d70ef ("drm/msm/dsi: check msm_dsi and dsi pointers before use") Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno/a5xx_debugfs: fix potential NULL pointer dereferenceGustavo A. R. Silva2018-03-19
| | | | | | | | | | _minor_ is being dereferenced before it is null checked, hence there is a potential null pointer dereference. Fix this by moving the pointer dereference after _minor_ has been null checked. Fixes: 024ad8df763f ("drm/msm: add a5xx specific debugfs") Signed-off-by: Gustavo A. R. Silva <garsilva@embeddedor.com> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Get byte_intf_clk only for versions that need itArchit Taneja2018-02-20
| | | | | | | | | | | | | | Newer DSI host controllers (SDM845 in particular) require a new clock called byte_intf_clk. A recent patch tried to add this as an optional clock, but it still set 'ret' to an error number if it didn't find it. This breaks the host's probe for all previous DSI host versions. Instead of setting this up as an optional clock, try to get the clock only for the DSI version that supports it. Fixes: 56558fb ("drm/msm/dsi: Add byte_intf_clk") Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: Use generic function to load firmware to a buffer objectJordan Crouse2018-02-20
| | | | | | | | Move a5xx specific code to load firmware into a buffer object to the generic Adreno code. This will come in useful for future targets. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: Define a list of firmware files to load per targetJordan Crouse2018-02-20
| | | | | | | | | | | The number and type of firmware files required differs for each target. Instead of using a fixed struct member for each possible firmware file use a generic list of files that should be loaded on boot. Use some semi-target specific enums to help each target find the appropriate firmware(s) that it needs to load. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/adreno: Rename gpmufw to powerfwJordan Crouse2018-02-20
| | | | | | | | | | | The power management device on the a5xx cores is known as the GPMU (Graphics Power Management Unit). On a6xx cores the device was expanded and renamed as the GMU (Graphics Management Unit). Rename the 'gpmufw' name struct adreno_info as 'powerfw' to avoid confusion. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Pass the correct aperture end to drm_mm_initJordan Crouse2018-02-20
| | | | | | | | | | | | drm_mm_init() takes the start and length of the intended virtual memory address region but the msm code is passing the end of the region instead. That would work out if the region started at 0 but it doesn't so the top of the region sneaks above the 32 bit boundary which won't work because the driver doesn't support 64 bit addresses for the GPU yet. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/gpu: Set number of clocks to 0 if the list allocation failsJordan Crouse2018-02-20
| | | | | | | | If we fail to allocate gpu->grp_clks reset the number of available clocks to zero to avoid referencing the missing array later. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: Replace gem_object deprecated functionsSteve Kowalik2018-02-20
| | | | | | | | | drm_gem_object_{reference,unreference,unreference_unlocked} are deprecated functions, and merely alias to the get/put functions. Switch to the new names. Signed-off-by: Steve Kowalik <steven@wedontsleep.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/hdmi: fix semicolon.cocci warningsFengguang Wu2018-02-20
| | | | | | | | | | | Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci CC: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/mdp5: Fix trailing semicolonLuis de Bethencourt2018-02-20
| | | | | | | | The trailing semicolon is an empty statement that does no operation. Removing it since it doesn't do anything. Signed-off-by: Luis de Bethencourt <luisbg@kernel.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* dt-bindings: display: msm/dsi: Add updates for SDM845Archit Taneja2018-02-20
| | | | | | | | | | | | | | | SDM845 uses a newer revision (v2.0+) of the 6G DSI controller. This revision has another clock input at the block boundary called the byte interface clock. Specify this new clock in the binding. A 10nm DSI PHY is used along with the controller. Add a compatible string for it and specify its base address/regulator supply needs. Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja <architt@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* dt-bindings: display: msm/dsi: Add compatible for 14nm DSI PHYArchit Taneja2018-02-20
| | | | | | | | | | | | | Add the compatible string for 14nm DSI PHY (used in MSM8996/APQ8096). >From 14nm PHY onwards, the "dsi_phy_regulator" reg-name is not required, but "dsi_phy_lane" reg-name is. Update the doc to specify the reg-names each PHY revision needs. Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja <architt@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* dt-bindings: display: msm/dsi: Fix the PHY regulator supply propsArchit Taneja2018-02-20
| | | | | | | | | | | The PHY regulator supply names vary across different PHY versions. Mention explicitly which PHYs require which supplies. Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja <architt@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* dt-bindings: display: msm/dsi: Remove unused propertiesArchit Taneja2018-02-20
| | | | | | | | | | | "qcom,dsi-host-index" and "qcom,dsi-phy-index" DT props aren't acceptable and have never been used in any DT files. Remove them. Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Archit Taneja <architt@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Add byte_intf_clkArchit Taneja2018-02-20
| | | | | | | | | | | | | | | | DSI6G v2.0+ blocks have a new clock input to them called byte_intf_clk. It's rate is to be set as byte_clk / 2. Within the clock controller (CC) subsystem, this clock is a child/descendant of the byte_clk. Set it up as an optional clock in the DSI host driver. Make sure that we enable/set its rate only after we configure byte_clk. This is required for the ancestor clocks in the CC to be configured correctly. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Add SDM845 in dsi_cfgArchit Taneja2018-02-20
| | | | | | | | SDM845 contains 2 DSI6G v2.2.1 host controllers. Add them in dsi_cfg. Cc: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Use msm_clk_get in dsi_get_configArchit Taneja2018-02-20
| | | | | | | | | We try to get the interface clock in dsi_get_config early during DSI's component bind. Try getting both the "iface" and "iface_clk" clock name variants so that we are compatible with both new and legacy DT. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Populate the 10nm PHY funcsArchit Taneja2018-02-20
| | | | | | | | | | | | | | | Populate the PHY ops with the downstream driver as reference. There are a couple of TODOs which need to be resolved: - The PHY timings are all hardcoded for now. This needs to be replaced with automatic calculations once we get/understand them. - There are some lane configuration registers which use a new representation between physical and logical lane mappings. For now, we've hardcoced them to follow the default mapping (i.e logical 0 -> phy 0, logical 1 -> phy 1 etc). Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Populate PLL 10nm clock opsArchit Taneja2018-02-20
| | | | | | | | | | | | | | | | Populate PLL clock ops from downstream. This contains the VCO PLL ops and the registration of standard clk_divider and clk_mux clocks. Unlike 14nm PLL, the postdividers/mux of the slave PLL doesn't need to be set to the same values of the postdivs/mux of the master PLL. Hence, we don't need special postdivider clock ops like we did with the 14nm PLL driver. Like the previous PLL drivers, the implementation is slightly different from downstream. We don't use shadow clocks, but have the ability to reparent the RCGs to a different source. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Add skeleton 10nm PHY/PLL codeArchit Taneja2018-02-20
| | | | | | | | | | Add new 10nm DSI PLL/PHY files that will be used on SDM845. Just populate empty pll/phy funcs for now. These will be filled up later. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: Update generated headers for 10nm PLL/PHYArchit Taneja2018-02-20
| | | | | Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add sudo flag to submit ioctlRob Clark2018-02-20
| | | | | | | | | | | | This flags cause cmdstream to be executed from the ringbuffer (RB) instead of IB1. Normally not something you'd ever want to do, but it is super useful for firmware debugging. Hidden behind CAP_SYS_RAWIO and a default=n kconfig option which depends on EXPERT (and has a suitably scary warning), to prevent it from being used on accident. Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm: add a5xx specific debugfsRob Clark2018-02-20
| | | | | | | | Add some debugfs to dump out PFP and ME microcontroller state, as well as some of the queues (MEQ and ROQ). Also add a debugfs file to trigger a GPU reset (and reloading the firmware on next submit). Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: check msm_dsi and dsi pointers before useLloyd Atkinson2018-02-20
| | | | | | | | | Move null checks of pointer arguments to the beginning of the modeset init function since they are referenced immediately instead of after they have already been used. Signed-off-by: Lloyd Atkinson <latkinso@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: correct DSI id bounds check during registrationLloyd Atkinson2018-02-20
| | | | | | | | Check DSI instance id argument against the proper boundary size to protect against invalid configuration of the DSI id. Signed-off-by: Lloyd Atkinson <latkinso@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* drm/msm/dsi: check for failure on retrieving pll in dsi managerLloyd Atkinson2018-02-20
| | | | | | | | | | | Make msm_dsi_pll_init consistently return an error code instead of NULL when pll initialization fails so that later pll retrieval can check against an error code. Add checks for these failures after retrieval of src_pll to avoid invalid pointer dereferences later in msm_dsi_pll_get_clk_provider. Signed-off-by: Lloyd Atkinson <latkinso@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
* Merge tag 'topic/hdcp-2018-02-13' of ↵Dave Airlie2018-02-15
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/drm/drm-misc into drm-next Add HDCP support to i915 drm driver. * tag 'topic/hdcp-2018-02-13' of git://anongit.freedesktop.org/drm/drm-misc: (26 commits) drm/i915: fix misalignment in HDCP register def drm/i915: Reauthenticate HDCP on failure drm/i915: Detect panel's hdcp capability drm/i915: Optimize HDCP key load drm/i915: Retry HDCP bksv read drm/i915: Connector info in HDCP debug msgs drm/i915: Stop encryption for repeater with no sink drm/i915: Handle failure from 2nd stage HDCP auth drm/i915: Downgrade hdcp logs from INFO to DEBUG_KMS drm/i915: Restore HDCP DRM_INFO when with no downstream drm/i915: Check for downstream topology errors drm/i915: Start repeater auth on READY/CP_IRQ drm/i915: II stage HDCP auth for repeater only drm/i915: Extending HDCP for HSW, BDW and BXT+ drm/i915/dp: Fix compilation of intel_dp_hdcp_check_link drm/i915: Only disable HDCP when it's active drm/i915: Don't allow HDCP on PORT E/F drm/i915: Implement HDCP for DisplayPort drm/i915: Implement HDCP for HDMI drm/i915: Add function to output Aksv over GMBUS ...
| * drm/i915: fix misalignment in HDCP register defRamalingam C2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch aligns all definitions of hdcp registers and their bits. v2: No changes. Added reviewed-by tag. v3: No change. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/1517609350-10698-9-git-send-email-ramalingam.c@intel.com
| * drm/i915: Reauthenticate HDCP on failureRamalingam C2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Incase of HDCP authentication failure, HDCP spec expects reauthentication. Hence this patch adds the reauthentications to be compliance with spec. v2: do-while to for loop for simplicity. [Seanpaul] v3: positioning the logs effectively. [Seanpaul] Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/1517609350-10698-8-git-send-email-ramalingam.c@intel.com
| * drm/i915: Detect panel's hdcp capabilityRamalingam C2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DP HDCP1.4 spec mandates that An can be written to panel only after detecting the panel's hdcp capability. For DP 0th Bit of Bcaps register indicates the panel's hdcp capability For HDMI valid BKSV indicates the panel's hdcp capability. For HDMI it is optional to detect the panel's hdcp capability before An Write. v2: Added comments explaining the need for action [Seanpaul]. Made panel's hdcp capability detection optional for hdmi [Seanpaul]. Defined a func for reading bcaps for DP [Seanpaul]. v3: Removed the NULL initialization [Seanpaul]. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/1517609350-10698-7-git-send-email-ramalingam.c@intel.com
| * drm/i915: Optimize HDCP key loadRamalingam C2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HDCP key need not be cleared on each hdcp disable. And HDCP key Load is skipped if key is already loaded. v2: No change. Added Reviewed-by tag. v3: No change. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/1517609350-10698-6-git-send-email-ramalingam.c@intel.com
| * drm/i915: Retry HDCP bksv readRamalingam C2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HDCP specification says that when bksv is identified as invalid (not with 20 1s), bksv should be re-read and verified. This patch adds the above mentioned re-read for bksv. v2: Rephrased the commit msg [Seanpaul] v3: do-while to for-loop [Seanpaul] v4: retry only if bksv is invalid and no error msg on each attempt [Seanpaul] v5: Correcting the return value [Seanpaul]. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/1517851922-30547-1-git-send-email-ramalingam.c@intel.com
| * drm/i915: Connector info in HDCP debug msgsRamalingam C2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When HDCP authentication is triggered on multiple connector, having connector name and ID in debug message will be more informative. v2: Added logs with connector info at the start of en/disable [Seanpaul] Added the connector info into Check link failure msgs too. v3: No Changes. Added Reviewed-by tag. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/1517609350-10698-4-git-send-email-ramalingam.c@intel.com
| * drm/i915: Stop encryption for repeater with no sinkRamalingam C2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a HDCP repeater is detected with zero downstream devices, HDCP spec approves either of below actions: 1. Dont continue on second stage authentication. Disable encryption. 2. Continue with second stage authentication excluding the KSV list and on success, continue encryption. Since disable encryption is agreed, repeater is not expected to have its own display. So there is no consumption of the display content in such setup. Hence, incase of repeater with zero device count, this patch fails the HDCP authentication and stops the HDCP encryption. v2: Rephrased commit msg and added comments in code [Seanpaul] v3: No changes. Added Reviewed-by tag. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/1517609350-10698-3-git-send-email-ramalingam.c@intel.com
| * drm/i915: Handle failure from 2nd stage HDCP authRamalingam C2018-02-05
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We enable the HDCP encryption as a part of first stage authentication. So when second stage authentication fails, we need to disable the HDCP encryption and signalling. This patch ensures that, when hdcp authentication fails, HDCP encryption and signalling is turned off. v2: Dropped connector ref passing to auth [Seanpaul] Moved the call to disable_hdcp() to enable_hdcp() [Seanpaul] v3: No Changes. Added the Reveiwed-by tag. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/1517609350-10698-2-git-send-email-ramalingam.c@intel.com
| * drm/i915: Downgrade hdcp logs from INFO to DEBUG_KMSSean Paul2018-01-30
| | | | | | | | | | | | | | | | | | HDCP was a bit too chatty to get along with the rest of the i915 driver. Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180130144707.171657-1-seanpaul@chromium.org
| * drm/i915: Restore HDCP DRM_INFO when with no downstreamSean Paul2018-01-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit below returned earlier than before, but failed to move the info message when authenticating without downstream devices. This patch restores the message on authentication success. Changes in v2: - s/no downstream devices/no repeater present/ (Ram) Fixes: 87eb3ec818fa ("drm/i915: II stage HDCP auth for repeater only") Cc: Ramalingam C <ramalingam.c@intel.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: intel-gfx@lists.freedesktop.org Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180130142943.168314-1-seanpaul@chromium.org Link: https://patchwork.freedesktop.org/patch/msgid/20180130142943.168314-1-seanpaul@chromium.org
| * drm/i915: Check for downstream topology errorsRamalingam C2018-01-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HDCP compliant Repeaters can support max of 127 devices and max depth of 7 for downstream topology. If these max limits are exceeded, repeater will set the topology error flags MAX_CASCADE_EXCEEDED and/or MAX_DEVS_EXCEEDED in Bstatus followed by asserting READY/CP_IRQ for HDCP transmitter. This patch check for these error flags as soon as READY bit is asserted. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> [seanpaul fixed checkpatch alignment issue] Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/1516254488-4971-5-git-send-email-ramalingam.c@intel.com
| * drm/i915: Start repeater auth on READY/CP_IRQRamalingam C2018-01-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Second stage of HDCP authentication starts at CP_IRQ or at the assertion of READY bit from Repeater. Till then repeater will be authenticating with its downstream devices. So authenticated device count, depth and ksv_list readable from repeaters are valid only after assertion of READY/CP_IRQ. This patch makes sure that READY is polled before reading any topology information. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/1516254488-4971-4-git-send-email-ramalingam.c@intel.com
| * drm/i915: II stage HDCP auth for repeater onlyRamalingam C2018-01-18
| | | | | | | | | | | | | | | | | | | | | | Second stage of HDCP authentication required only if the HDCP sink is a repeater. This patch imposes above condition on second stage HDCP authentication. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/1516254488-4971-3-git-send-email-ramalingam.c@intel.com
| * drm/i915: Extending HDCP for HSW, BDW and BXT+Ramalingam C2018-01-18
| | | | | | | | | | | | | | | | | | | | This patch extends the Key load process and hdcp initialization for few more capable intel platforms i.e. HSW, BDW and BXT+. Signed-off-by: Ramalingam C <ramalingam.c@intel.com> [seanpaul fixed checkpatch issues] Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/1516254488-4971-2-git-send-email-ramalingam.c@intel.com
| * drm/i915/dp: Fix compilation of intel_dp_hdcp_check_linkChris Wilson2018-01-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/gpu/drm/i915/intel_dp.c: In function ‘intel_dp_hdcp_check_link’: drivers/gpu/drm/i915/intel_dp.c:5191:26: error: ?: using integer constants in boolean context [-Werror=int-in-bool-context] return ret >= 0 ? -EIO : ret; Fixes: 20f24d776d1b ("drm/i915: Implement HDCP for DisplayPort") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Ramalingam C <ramalingam.c@intel.com> Cc: Sean Paul <seanpaul@chromium.org> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180118161025.22700-1-chris@chris-wilson.co.uk
| * drm/i915: Only disable HDCP when it's activeSean Paul2018-01-09
| | | | | | | | | | | | | | | | | | | | | | | | | | Instead of always trying to disable HDCP. Only run hdcp_disable when the state is not UNDESIRED. This will catch cases where it's enabled and also cases where enable failed and the state is left in DESIRED mode. Note that things won't blow up if disable is attempted while already disabled, it's just bad form. Reviewed-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180109185330.16853-1-seanpaul@chromium.org
| * drm/i915: Don't allow HDCP on PORT E/FSean Paul2018-01-09
| | | | | | | | | | | | | | | | | | Port E doesn't have HDCP support, and Port F is disabled. Don't setup the hdcp shim on those. Reviewed-by: Daniel Vetter <daniel@ffwll.ch> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180109185401.16911-1-seanpaul@chromium.org
| * drm/i915: Implement HDCP for DisplayPortSean Paul2018-01-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds HDCP support for DisplayPort connectors by implementing the intel_hdcp_shim. Most of this is straightforward read/write from/to DPCD registers. One thing worth pointing out is the Aksv output bit. It wasn't easily separable like it's HDMI counterpart, so it's crammed in with the rest of it. Changes in v2: - Moved intel_hdcp_check_link out of intel_dp_check_link and only call it on short pulse. Since intel_hdcp_check_link does its own locking, this ensures we don't deadlock when intel_dp_check_link is called holding connection_mutex. - Rebased on drm-intel-next Changes in v3: - Initialize new worker Changes in v4: - Use intel_hdcp_init (Daniel) - Check for reauth requests in check_link (Ram) Changes in v5: - None Changes in v6: - Fix build warnings when printing ssize_t Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: Ramalingam C <ramalingam.c@intel.com> Signed-off-by: Sean Paul <seanpaul@chromium.org> Link: https://patchwork.freedesktop.org/patch/msgid/20180108195545.218615-10-seanpaul@chromium.org
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-27 16:54:15 -0400