diff options
author | Archit Taneja <architt@codeaurora.org> | 2018-01-17 04:34:48 -0500 |
---|---|---|
committer | Rob Clark <robdclark@gmail.com> | 2018-02-20 10:41:21 -0500 |
commit | 35f135a3b1cfeee4ef2bd92755debd0bcf60cb9f (patch) | |
tree | 6f36d3ae1a9ffaf6ce2caf335c2b309cd27738d4 | |
parent | 31767e00e428c891343f94e5a94909bb7a642bcf (diff) |
dt-bindings: display: msm/dsi: Add updates for SDM845
SDM845 uses a newer revision (v2.0+) of the 6G DSI controller. This
revision has another clock input at the block boundary called the byte
interface clock. Specify this new clock in the binding.
A 10nm DSI PHY is used along with the controller. Add a compatible
string for it and specify its base address/regulator supply needs.
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
-rw-r--r-- | Documentation/devicetree/bindings/display/msm/dsi.txt | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index 26a1796b7145..518e9cdf0d4b 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt | |||
@@ -20,6 +20,8 @@ Required properties: | |||
20 | * "core" | 20 | * "core" |
21 | For DSIv2, we need an additional clock: | 21 | For DSIv2, we need an additional clock: |
22 | * "src" | 22 | * "src" |
23 | For DSI6G v2.0 onwards, we need also need the clock: | ||
24 | * "byte_intf" | ||
23 | - assigned-clocks: Parents of "byte" and "pixel" for the given platform. | 25 | - assigned-clocks: Parents of "byte" and "pixel" for the given platform. |
24 | - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided | 26 | - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided |
25 | by a DSI PHY block. See [1] for details on clock bindings. | 27 | by a DSI PHY block. See [1] for details on clock bindings. |
@@ -87,6 +89,7 @@ Required properties: | |||
87 | * "qcom,dsi-phy-20nm" | 89 | * "qcom,dsi-phy-20nm" |
88 | * "qcom,dsi-phy-28nm-8960" | 90 | * "qcom,dsi-phy-28nm-8960" |
89 | * "qcom,dsi-phy-14nm" | 91 | * "qcom,dsi-phy-14nm" |
92 | * "qcom,dsi-phy-10nm" | ||
90 | - reg: Physical base address and length of the registers of PLL, PHY. Some | 93 | - reg: Physical base address and length of the registers of PLL, PHY. Some |
91 | revisions require the PHY regulator base address, whereas others require the | 94 | revisions require the PHY regulator base address, whereas others require the |
92 | PHY lane base address. See below for each PHY revision. | 95 | PHY lane base address. See below for each PHY revision. |
@@ -95,7 +98,7 @@ Required properties: | |||
95 | * "dsi_pll" | 98 | * "dsi_pll" |
96 | * "dsi_phy" | 99 | * "dsi_phy" |
97 | * "dsi_phy_regulator" | 100 | * "dsi_phy_regulator" |
98 | For DSI 14nm PHY: | 101 | For DSI 14nm and 10nm PHYs: |
99 | * "dsi_pll" | 102 | * "dsi_pll" |
100 | * "dsi_phy" | 103 | * "dsi_phy" |
101 | * "dsi_phy_lane" | 104 | * "dsi_phy_lane" |
@@ -112,6 +115,8 @@ Required properties: | |||
112 | - vcca-supply: phandle to vcca regulator device node | 115 | - vcca-supply: phandle to vcca regulator device node |
113 | For 14nm PHY: | 116 | For 14nm PHY: |
114 | - vcca-supply: phandle to vcca regulator device node | 117 | - vcca-supply: phandle to vcca regulator device node |
118 | For 10nm PHY: | ||
119 | - vdds-supply: phandle to vdds regulator device node | ||
115 | 120 | ||
116 | Optional properties: | 121 | Optional properties: |
117 | - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY | 122 | - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY |