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authorBjorn Andersson <bjorn.andersson@linaro.org>2018-02-14 01:46:58 -0500
committerRob Clark <robdclark@gmail.com>2018-03-19 06:33:36 -0400
commit79d57bf6fa3bcc0ec5fc3b8140c4df1d696f593b (patch)
treec20212435e790f667767102715aed3eeaeb8bee3
parentd71b6bd80d96f15f4ae393d3bec0636c960e289a (diff)
drm/msm: Trigger fence completion from GPU
Interrupt commands causes the CP to trigger an interrupt as the command is processed, regardless of the GPU being done processing previous commands. This is seen by the interrupt being delivered before the fence is written on 8974 and is likely the cause of the additional CP_WAIT_FOR_IDLE workaround found for a306, which would cause the CP to wait for the GPU to go idle before triggering the interrupt. Instead we can set the (undocumented) BIT(31) of the CACHE_FLUSH_TS which will cause a special CACHE_FLUSH_TS interrupt to be triggered from the GPU as the write event is processed. Add CACHE_FLUSH_TS to the IRQ masks of A3xx and A4xx and remove the workaround for A306. Suggested-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
-rw-r--r--drivers/gpu/drm/msm/adreno/a3xx_gpu.c1
-rw-r--r--drivers/gpu/drm/msm/adreno/a4xx_gpu.c1
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_gpu.c18
3 files changed, 4 insertions, 16 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 1dd84d3489ae..3ebbeb3a9b68 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -35,6 +35,7 @@
35 A3XX_INT0_CP_RB_INT | \ 35 A3XX_INT0_CP_RB_INT | \
36 A3XX_INT0_CP_REG_PROTECT_FAULT | \ 36 A3XX_INT0_CP_REG_PROTECT_FAULT | \
37 A3XX_INT0_CP_AHB_ERROR_HALT | \ 37 A3XX_INT0_CP_AHB_ERROR_HALT | \
38 A3XX_INT0_CACHE_FLUSH_TS | \
38 A3XX_INT0_UCHE_OOB_ACCESS) 39 A3XX_INT0_UCHE_OOB_ACCESS)
39 40
40extern bool hang_debug; 41extern bool hang_debug;
diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index 2884b1b1660c..16d3d596638e 100644
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -27,6 +27,7 @@
27 A4XX_INT0_CP_RB_INT | \ 27 A4XX_INT0_CP_RB_INT | \
28 A4XX_INT0_CP_REG_PROTECT_FAULT | \ 28 A4XX_INT0_CP_REG_PROTECT_FAULT | \
29 A4XX_INT0_CP_AHB_ERROR_HALT | \ 29 A4XX_INT0_CP_AHB_ERROR_HALT | \
30 A4XX_INT0_CACHE_FLUSH_TS | \
30 A4XX_INT0_UCHE_OOB_ACCESS) 31 A4XX_INT0_UCHE_OOB_ACCESS)
31 32
32extern bool hang_debug; 33extern bool hang_debug;
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index 87133c6c6f91..17d0506d058c 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -313,26 +313,12 @@ void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
313 OUT_RING(ring, 0x00000000); 313 OUT_RING(ring, 0x00000000);
314 } 314 }
315 315
316 /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */
316 OUT_PKT3(ring, CP_EVENT_WRITE, 3); 317 OUT_PKT3(ring, CP_EVENT_WRITE, 3);
317 OUT_RING(ring, CACHE_FLUSH_TS); 318 OUT_RING(ring, CACHE_FLUSH_TS | BIT(31));
318 OUT_RING(ring, rbmemptr(ring, fence)); 319 OUT_RING(ring, rbmemptr(ring, fence));
319 OUT_RING(ring, submit->seqno); 320 OUT_RING(ring, submit->seqno);
320 321
321 /* we could maybe be clever and only CP_COND_EXEC the interrupt: */
322 OUT_PKT3(ring, CP_INTERRUPT, 1);
323 OUT_RING(ring, 0x80000000);
324
325 /* Workaround for missing irq issue on 8x16/a306. Unsure if the
326 * root cause is a platform issue or some a306 quirk, but this
327 * keeps things humming along:
328 */
329 if (adreno_is_a306(adreno_gpu)) {
330 OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
331 OUT_RING(ring, 0x00000000);
332 OUT_PKT3(ring, CP_INTERRUPT, 1);
333 OUT_RING(ring, 0x80000000);
334 }
335
336#if 0 322#if 0
337 if (adreno_is_a3xx(adreno_gpu)) { 323 if (adreno_is_a3xx(adreno_gpu)) {
338 /* Dummy set-constant to trigger context rollover */ 324 /* Dummy set-constant to trigger context rollover */