1 files changed, 8 insertions, 28 deletions

diff --git a/arch/powerpc/platforms/powernv/pci.h b/arch/powerpc/platforms/powernv/pci.h
index 8b37b28e3831..8e36da379252 100644
--- a/arch/powerpc/platforms/powernv/pci.h
+++ b/arch/powerpc/platforms/powernv/pci.h
@@ -8,9 +8,6 @@
 
 struct pci_dn;
 
-/* Maximum possible number of ATSD MMIO registers per NPU */
-#define NV_NMMU_ATSD_REGS 8
-
 enum pnv_phb_type {
         PNV_PHB_IODA1           = 0,
         PNV_PHB_IODA2           = 1,
@@ -65,6 +62,7 @@ struct pnv_ioda_pe {
 
         /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
         struct iommu_table_group table_group;
+        struct npu_comp         *npucomp;
 
         /* 64-bit TCE bypass region */
         bool                    tce_bypass_enabled;
@@ -106,20 +104,14 @@ struct pnv_phb {
         struct dentry           *dbgfs;
 #endif
 
-#ifdef CONFIG_PCI_MSI
         unsigned int            msi_base;
         unsigned int            msi32_support;
         struct msi_bitmap       msi_bmp;
-#endif
         int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
                          unsigned int hwirq, unsigned int virq,
                          unsigned int is_64, struct msi_msg *msg);
         void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
-        void (*fixup_phb)(struct pci_controller *hose);
         int (*init_m64)(struct pnv_phb *phb);
-        void (*reserve_m64_pe)(struct pci_bus *bus,
-                               unsigned long *pe_bitmap, bool all);
-        struct pnv_ioda_pe *(*pick_m64_pe)(struct pci_bus *bus, bool all);
         int (*get_pe_state)(struct pnv_phb *phb, int pe_no);
         void (*freeze_pe)(struct pnv_phb *phb, int pe_no);
         int (*unfreeze_pe)(struct pnv_phb *phb, int pe_no, int opt);
@@ -180,19 +172,6 @@ struct pnv_phb {
         unsigned int            diag_data_size;
         u8                      *diag_data;
 
-        /* Nvlink2 data */
-        struct npu {
-                int index;
-                __be64 *mmio_atsd_regs[NV_NMMU_ATSD_REGS];
-                unsigned int mmio_atsd_count;
-
-                /* Bitmask for MMIO register usage */
-                unsigned long mmio_atsd_usage;
-
-                /* Do we need to explicitly flush the nest mmu? */
-                bool nmmu_flush;
-        } npu;
-
         int p2p_target_count;
 };
 
@@ -210,6 +189,7 @@ extern void pnv_pci_init_ioda_hub(struct device_node *np);
 extern void pnv_pci_init_ioda2_phb(struct device_node *np);
 extern void pnv_pci_init_npu_phb(struct device_node *np);
 extern void pnv_pci_init_npu2_opencapi_phb(struct device_node *np);
+extern void pnv_npu2_map_lpar(struct pnv_ioda_pe *gpe, unsigned long msr);
 extern void pnv_pci_reset_secondary_bus(struct pci_dev *dev);
 extern int pnv_eeh_phb_reset(struct pci_controller *hose, int option);
 
@@ -220,6 +200,8 @@ extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
 extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
 extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
 extern void pnv_pci_ioda2_set_bypass(struct pnv_ioda_pe *pe, bool enable);
+extern unsigned long pnv_pci_ioda2_get_table_size(__u32 page_shift,
+                __u64 window_size, __u32 levels);
 extern int pnv_eeh_post_init(void);
 
 extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
@@ -235,12 +217,10 @@ extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
 extern void pnv_npu_try_dma_set_bypass(struct pci_dev *gpdev, bool bypass);
 extern void pnv_pci_ioda2_tce_invalidate_entire(struct pnv_phb *phb, bool rm);
 extern struct pnv_ioda_pe *pnv_pci_npu_setup_iommu(struct pnv_ioda_pe *npe);
-extern long pnv_npu_set_window(struct pnv_ioda_pe *npe, int num,
-                struct iommu_table *tbl);
-extern long pnv_npu_unset_window(struct pnv_ioda_pe *npe, int num);
-extern void pnv_npu_take_ownership(struct pnv_ioda_pe *npe);
-extern void pnv_npu_release_ownership(struct pnv_ioda_pe *npe);
-extern int pnv_npu2_init(struct pnv_phb *phb);
+extern struct iommu_table_group *pnv_try_setup_npu_table_group(
+                struct pnv_ioda_pe *pe);
+extern struct iommu_table_group *pnv_npu_compound_attach(
+                struct pnv_ioda_pe *pe);
 
 /* pci-ioda-tce.c */
 #define POWERNV_IOMMU_DEFAULT_LEVELS    1