1 files changed, 6 insertions, 16 deletions

diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c
index e012b1030a5b..0ff9c43733e9 100644
--- a/arch/powerpc/perf/power9-pmu.c
+++ b/arch/powerpc/perf/power9-pmu.c
@@ -63,16 +63,8 @@
  *      MMCRA[9:11] = thresh_cmp[0:2]
  *      MMCRA[12:18] = thresh_cmp[3:9]
  *
- * if unit == 6 or unit == 7
- *      MMCRC[53:55] = cache_sel[1:3]      (L2EVENT_SEL)
- * else if unit == 8 or unit == 9:
- *      if cache_sel[0] == 0: # L3 bank
- *              MMCRC[47:49] = cache_sel[1:3]  (L3EVENT_SEL0)
- *      else if cache_sel[0] == 1:
- *              MMCRC[50:51] = cache_sel[2:3]  (L3EVENT_SEL1)
- * else if cache_sel[1]: # L1 event
- *      MMCR1[16] = cache_sel[2]
- *     MMCR1[17] = cache_sel[3]
+ * MMCR1[16] = cache_sel[2]
+ * MMCR1[17] = cache_sel[3]
  *
  * if mark:
  *      MMCRA[63]    = 1                (SAMPLE_ENABLE)
@@ -179,8 +171,6 @@ CACHE_EVENT_ATTR(L1-icache-prefetches,		PM_IC_PREF_WRITE);
 CACHE_EVENT_ATTR(LLC-load-misses,               PM_DATA_FROM_L3MISS);
 CACHE_EVENT_ATTR(LLC-loads,                     PM_DATA_FROM_L3);
 CACHE_EVENT_ATTR(LLC-prefetches,                PM_L3_PREF_ALL);
-CACHE_EVENT_ATTR(LLC-store-misses,              PM_L2_ST_MISS);
-CACHE_EVENT_ATTR(LLC-stores,                    PM_L2_ST);
 CACHE_EVENT_ATTR(branch-load-misses,            PM_BR_MPRED_CMPL);
 CACHE_EVENT_ATTR(branch-loads,                  PM_BR_CMPL);
 CACHE_EVENT_ATTR(dTLB-load-misses,              PM_DTLB_MISS);
@@ -205,8 +195,6 @@ static struct attribute *power9_events_attr[] = {
         CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
         CACHE_EVENT_PTR(PM_DATA_FROM_L3),
         CACHE_EVENT_PTR(PM_L3_PREF_ALL),
-        CACHE_EVENT_PTR(PM_L2_ST_MISS),
-        CACHE_EVENT_PTR(PM_L2_ST),
         CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
         CACHE_EVENT_PTR(PM_BR_CMPL),
         CACHE_EVENT_PTR(PM_DTLB_MISS),
@@ -354,8 +342,8 @@ static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
                         [ C(RESULT_MISS)   ] = PM_DATA_FROM_L3MISS,
                 },
                 [ C(OP_WRITE) ] = {
-                        [ C(RESULT_ACCESS) ] = PM_L2_ST,
-                        [ C(RESULT_MISS)   ] = PM_L2_ST_MISS,
+                        [ C(RESULT_ACCESS) ] = 0,
+                        [ C(RESULT_MISS)   ] = 0,
                 },
                 [ C(OP_PREFETCH) ] = {
                         [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
@@ -427,6 +415,8 @@ static struct power_pmu power9_pmu = {
         .n_counter              = MAX_PMU_COUNTERS,
         .add_fields             = ISA207_ADD_FIELDS,
         .test_adder             = ISA207_TEST_ADDER,
+        .group_constraint_mask  = CNST_CACHE_PMC4_MASK,
+        .group_constraint_val   = CNST_CACHE_PMC4_VAL,
         .compute_mmcr           = isa207_compute_mmcr,
         .config_bhrb            = power9_config_bhrb,
         .bhrb_filter_map        = power9_bhrb_filter_map,