diff options
Diffstat (limited to 'arch/powerpc/kernel/cpu_setup_power.S')
-rw-r--r-- | arch/powerpc/kernel/cpu_setup_power.S | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S index 584e119fa8b0..52ff3f025437 100644 --- a/arch/powerpc/kernel/cpu_setup_power.S +++ b/arch/powerpc/kernel/cpu_setup_power.S | |||
@@ -51,6 +51,7 @@ _GLOBAL(__setup_cpu_power8) | |||
51 | mflr r11 | 51 | mflr r11 |
52 | bl __init_FSCR | 52 | bl __init_FSCR |
53 | bl __init_PMU | 53 | bl __init_PMU |
54 | bl __init_PMU_ISA207 | ||
54 | bl __init_hvmode_206 | 55 | bl __init_hvmode_206 |
55 | mtlr r11 | 56 | mtlr r11 |
56 | beqlr | 57 | beqlr |
@@ -62,6 +63,7 @@ _GLOBAL(__setup_cpu_power8) | |||
62 | bl __init_HFSCR | 63 | bl __init_HFSCR |
63 | bl __init_tlb_power8 | 64 | bl __init_tlb_power8 |
64 | bl __init_PMU_HV | 65 | bl __init_PMU_HV |
66 | bl __init_PMU_HV_ISA207 | ||
65 | mtlr r11 | 67 | mtlr r11 |
66 | blr | 68 | blr |
67 | 69 | ||
@@ -69,6 +71,7 @@ _GLOBAL(__restore_cpu_power8) | |||
69 | mflr r11 | 71 | mflr r11 |
70 | bl __init_FSCR | 72 | bl __init_FSCR |
71 | bl __init_PMU | 73 | bl __init_PMU |
74 | bl __init_PMU_ISA207 | ||
72 | mfmsr r3 | 75 | mfmsr r3 |
73 | rldicl. r0,r3,4,63 | 76 | rldicl. r0,r3,4,63 |
74 | mtlr r11 | 77 | mtlr r11 |
@@ -81,12 +84,14 @@ _GLOBAL(__restore_cpu_power8) | |||
81 | bl __init_HFSCR | 84 | bl __init_HFSCR |
82 | bl __init_tlb_power8 | 85 | bl __init_tlb_power8 |
83 | bl __init_PMU_HV | 86 | bl __init_PMU_HV |
87 | bl __init_PMU_HV_ISA207 | ||
84 | mtlr r11 | 88 | mtlr r11 |
85 | blr | 89 | blr |
86 | 90 | ||
87 | _GLOBAL(__setup_cpu_power9) | 91 | _GLOBAL(__setup_cpu_power9) |
88 | mflr r11 | 92 | mflr r11 |
89 | bl __init_FSCR | 93 | bl __init_FSCR |
94 | bl __init_PMU | ||
90 | bl __init_hvmode_206 | 95 | bl __init_hvmode_206 |
91 | mtlr r11 | 96 | mtlr r11 |
92 | beqlr | 97 | beqlr |
@@ -94,15 +99,18 @@ _GLOBAL(__setup_cpu_power9) | |||
94 | mtspr SPRN_LPID,r0 | 99 | mtspr SPRN_LPID,r0 |
95 | mfspr r3,SPRN_LPCR | 100 | mfspr r3,SPRN_LPCR |
96 | ori r3, r3, LPCR_PECEDH | 101 | ori r3, r3, LPCR_PECEDH |
102 | ori r3, r3, LPCR_HVICE | ||
97 | bl __init_LPCR | 103 | bl __init_LPCR |
98 | bl __init_HFSCR | 104 | bl __init_HFSCR |
99 | bl __init_tlb_power9 | 105 | bl __init_tlb_power9 |
106 | bl __init_PMU_HV | ||
100 | mtlr r11 | 107 | mtlr r11 |
101 | blr | 108 | blr |
102 | 109 | ||
103 | _GLOBAL(__restore_cpu_power9) | 110 | _GLOBAL(__restore_cpu_power9) |
104 | mflr r11 | 111 | mflr r11 |
105 | bl __init_FSCR | 112 | bl __init_FSCR |
113 | bl __init_PMU | ||
106 | mfmsr r3 | 114 | mfmsr r3 |
107 | rldicl. r0,r3,4,63 | 115 | rldicl. r0,r3,4,63 |
108 | mtlr r11 | 116 | mtlr r11 |
@@ -111,9 +119,11 @@ _GLOBAL(__restore_cpu_power9) | |||
111 | mtspr SPRN_LPID,r0 | 119 | mtspr SPRN_LPID,r0 |
112 | mfspr r3,SPRN_LPCR | 120 | mfspr r3,SPRN_LPCR |
113 | ori r3, r3, LPCR_PECEDH | 121 | ori r3, r3, LPCR_PECEDH |
122 | ori r3, r3, LPCR_HVICE | ||
114 | bl __init_LPCR | 123 | bl __init_LPCR |
115 | bl __init_HFSCR | 124 | bl __init_HFSCR |
116 | bl __init_tlb_power9 | 125 | bl __init_tlb_power9 |
126 | bl __init_PMU_HV | ||
117 | mtlr r11 | 127 | mtlr r11 |
118 | blr | 128 | blr |
119 | 129 | ||
@@ -208,14 +218,22 @@ __init_tlb_power9: | |||
208 | __init_PMU_HV: | 218 | __init_PMU_HV: |
209 | li r5,0 | 219 | li r5,0 |
210 | mtspr SPRN_MMCRC,r5 | 220 | mtspr SPRN_MMCRC,r5 |
221 | blr | ||
222 | |||
223 | __init_PMU_HV_ISA207: | ||
224 | li r5,0 | ||
211 | mtspr SPRN_MMCRH,r5 | 225 | mtspr SPRN_MMCRH,r5 |
212 | blr | 226 | blr |
213 | 227 | ||
214 | __init_PMU: | 228 | __init_PMU: |
215 | li r5,0 | 229 | li r5,0 |
216 | mtspr SPRN_MMCRS,r5 | ||
217 | mtspr SPRN_MMCRA,r5 | 230 | mtspr SPRN_MMCRA,r5 |
218 | mtspr SPRN_MMCR0,r5 | 231 | mtspr SPRN_MMCR0,r5 |
219 | mtspr SPRN_MMCR1,r5 | 232 | mtspr SPRN_MMCR1,r5 |
220 | mtspr SPRN_MMCR2,r5 | 233 | mtspr SPRN_MMCR2,r5 |
221 | blr | 234 | blr |
235 | |||
236 | __init_PMU_ISA207: | ||
237 | li r5,0 | ||
238 | mtspr SPRN_MMCRS,r5 | ||
239 | blr | ||