Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next

Pull networking updates from David Miller:

 1) BBR TCP congestion control, from Neal Cardwell, Yuchung Cheng and
    co. at Google. https://lwn.net/Articles/701165/

 2) Do TCP Small Queues for retransmits, from Eric Dumazet.

 3) Support collect_md mode for all IPV4 and IPV6 tunnels, from Alexei
    Starovoitov.

 4) Allow cls_flower to classify packets in ip tunnels, from Amir Vadai.

 5) Support DSA tagging in older mv88e6xxx switches, from Andrew Lunn.

 6) Support GMAC protocol in iwlwifi mwm, from Ayala Beker.

 7) Support ndo_poll_controller in mlx5, from Calvin Owens.

 8) Move VRF processing to an output hook and allow l3mdev to be
    loopback, from David Ahern.

 9) Support SOCK_DESTROY for UDP sockets. Also from David Ahern.

10) Congestion control in RXRPC, from David Howells.

11) Support geneve RX offload in ixgbe, from Emil Tantilov.

12) When hitting pressure for new incoming TCP data SKBs, perform a
    partial rathern than a full purge of the OFO queue (which could be
    huge). From Eric Dumazet.

13) Convert XFRM state and policy lookups to RCU, from Florian Westphal.

14) Support RX network flow classification to igb, from Gangfeng Huang.

15) Hardware offloading of eBPF in nfp driver, from Jakub Kicinski.

16) New skbmod packet action, from Jamal Hadi Salim.

17) Remove some inefficiencies in snmp proc output, from Jia He.

18) Add FIB notifications to properly propagate route changes to
    hardware which is doing forwarding offloading. From Jiri Pirko.

19) New dsa driver for qca8xxx chips, from John Crispin.

20) Implement RFC7559 ipv6 router solicitation backoff, from Maciej
    Żenczykowski.

21) Add L3 mode to ipvlan, from Mahesh Bandewar.

22) Support 802.1ad in mlx4, from Moshe Shemesh.

23) Support hardware LRO in mediatek driver, from Nelson Chang.

24) Add TC offloading to mlx5, from Or Gerlitz.

25) Convert various drivers to ethtool ksettings interfaces, from
    Philippe Reynes.

26) TX max rate limiting for cxgb4, from Rahul Lakkireddy.

27) NAPI support for ath10k, from Rajkumar Manoharan.

28) Support XDP in mlx5, from Rana Shahout and Saeed Mahameed.

29) UDP replicast support in TIPC, from Richard Alpe.

30) Per-queue statistics for qed driver, from Sudarsana Reddy Kalluru.

31) Support BQL in thunderx driver, from Sunil Goutham.

32) TSO support in alx driver, from Tobias Regnery.

33) Add stream parser engine and use it in kcm.

34) Support async DHCP replies in ipconfig module, from Uwe
    Kleine-König.

35) DSA port fast aging for mv88e6xxx driver, from Vivien Didelot.

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1715 commits)
  mlxsw: switchx2: Fix misuse of hard_header_len
  mlxsw: spectrum: Fix misuse of hard_header_len
  net/faraday: Stop NCSI device on shutdown
  net/ncsi: Introduce ncsi_stop_dev()
  net/ncsi: Rework the channel monitoring
  net/ncsi: Allow to extend NCSI request properties
  net/ncsi: Rework request index allocation
  net/ncsi: Don't probe on the reserved channel ID (0x1f)
  net/ncsi: Introduce NCSI_RESERVED_CHANNEL
  net/ncsi: Avoid unused-value build warning from ia64-linux-gcc
  net: Add netdev all_adj_list refcnt propagation to fix panic
  net: phy: Add Edge-rate driver for Microsemi PHYs.
  vmxnet3: Wake queue from reset work
  i40e: avoid NULL pointer dereference and recursive errors on early PCI error
  qed: Add RoCE ll2 & GSI support
  qed: Add support for memory registeration verbs
  qed: Add support for QP verbs
  qed: PD,PKEY and CQ verb support
  qed: Add support for RoCE hw init
  qede: Add qedr framework
  ...

1 files changed, 18 insertions, 423 deletions

diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index 0b6d15cddb2f..77c141797152 100644
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -198,19 +198,6 @@ enum {
 };
 
 enum {
-        MLX5_ACCESS_MODE_PA     = 0,
-        MLX5_ACCESS_MODE_MTT    = 1,
-        MLX5_ACCESS_MODE_KLM    = 2
-};
-
-enum {
-        MLX5_MKEY_REMOTE_INVAL  = 1 << 24,
-        MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
-        MLX5_MKEY_BSF_EN        = 1 << 30,
-        MLX5_MKEY_LEN64         = 1 << 31,
-};
-
-enum {
         MLX5_EN_RD      = (u64)1,
         MLX5_EN_WR      = (u64)2
 };
@@ -411,33 +398,6 @@ enum {
         MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
 };
 
-struct mlx5_inbox_hdr {
-        __be16          opcode;
-        u8              rsvd[4];
-        __be16          opmod;
-};
-
-struct mlx5_outbox_hdr {
-        u8              status;
-        u8              rsvd[3];
-        __be32          syndrome;
-};
-
-struct mlx5_cmd_query_adapter_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        u8                      rsvd[8];
-};
-
-struct mlx5_cmd_query_adapter_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd0[24];
-        u8                      intapin;
-        u8                      rsvd1[13];
-        __be16                  vsd_vendor_id;
-        u8                      vsd[208];
-        u8                      vsd_psid[16];
-};
-
 enum mlx5_odp_transport_cap_bits {
         MLX5_ODP_SUPPORT_SEND    = 1 << 31,
         MLX5_ODP_SUPPORT_RECV    = 1 << 30,
@@ -455,30 +415,6 @@ struct mlx5_odp_caps {
         char reserved2[0xe4];
 };
 
-struct mlx5_cmd_init_hca_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        u8                      rsvd0[2];
-        __be16                  profile;
-        u8                      rsvd1[4];
-};
-
-struct mlx5_cmd_init_hca_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd[8];
-};
-
-struct mlx5_cmd_teardown_hca_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        u8                      rsvd0[2];
-        __be16                  profile;
-        u8                      rsvd1[4];
-};
-
-struct mlx5_cmd_teardown_hca_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd[8];
-};
-
 struct mlx5_cmd_layout {
         u8              type;
         u8              rsvd0[3];
@@ -494,7 +430,6 @@ struct mlx5_cmd_layout {
         u8              status_own;
 };
 
-
 struct health_buffer {
         __be32          assert_var[5];
         __be32          rsvd0[3];
@@ -856,245 +791,15 @@ struct mlx5_cqe128 {
         struct mlx5_cqe64       cqe64;
 };
 
-struct mlx5_srq_ctx {
-        u8                      state_log_sz;
-        u8                      rsvd0[3];
-        __be32                  flags_xrcd;
-        __be32                  pgoff_cqn;
-        u8                      rsvd1[4];
-        u8                      log_pg_sz;
-        u8                      rsvd2[7];
-        __be32                  pd;
-        __be16                  lwm;
-        __be16                  wqe_cnt;
-        u8                      rsvd3[8];
-        __be64                  db_record;
-};
-
-struct mlx5_create_srq_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be32                  input_srqn;
-        u8                      rsvd0[4];
-        struct mlx5_srq_ctx     ctx;
-        u8                      rsvd1[208];
-        __be64                  pas[0];
-};
-
-struct mlx5_create_srq_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        __be32                  srqn;
-        u8                      rsvd[4];
-};
-
-struct mlx5_destroy_srq_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be32                  srqn;
-        u8                      rsvd[4];
-};
-
-struct mlx5_destroy_srq_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd[8];
-};
-
-struct mlx5_query_srq_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be32                  srqn;
-        u8                      rsvd0[4];
-};
-
-struct mlx5_query_srq_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd0[8];
-        struct mlx5_srq_ctx     ctx;
-        u8                      rsvd1[32];
-        __be64                  pas[0];
-};
-
-struct mlx5_arm_srq_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be32                  srqn;
-        __be16                  rsvd;
-        __be16                  lwm;
-};
-
-struct mlx5_arm_srq_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd[8];
-};
-
-struct mlx5_cq_context {
-        u8                      status;
-        u8                      cqe_sz_flags;
-        u8                      st;
-        u8                      rsvd3;
-        u8                      rsvd4[6];
-        __be16                  page_offset;
-        __be32                  log_sz_usr_page;
-        __be16                  cq_period;
-        __be16                  cq_max_count;
-        __be16                  rsvd20;
-        __be16                  c_eqn;
-        u8                      log_pg_sz;
-        u8                      rsvd25[7];
-        __be32                  last_notified_index;
-        __be32                  solicit_producer_index;
-        __be32                  consumer_counter;
-        __be32                  producer_counter;
-        u8                      rsvd48[8];
-        __be64                  db_record_addr;
-};
-
-struct mlx5_create_cq_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be32                  input_cqn;
-        u8                      rsvdx[4];
-        struct mlx5_cq_context  ctx;
-        u8                      rsvd6[192];
-        __be64                  pas[0];
-};
-
-struct mlx5_create_cq_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        __be32                  cqn;
-        u8                      rsvd0[4];
-};
-
-struct mlx5_destroy_cq_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be32                  cqn;
-        u8                      rsvd0[4];
-};
-
-struct mlx5_destroy_cq_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd0[8];
-};
-
-struct mlx5_query_cq_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be32                  cqn;
-        u8                      rsvd0[4];
-};
-
-struct mlx5_query_cq_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd0[8];
-        struct mlx5_cq_context  ctx;
-        u8                      rsvd6[16];
-        __be64                  pas[0];
-};
-
-struct mlx5_modify_cq_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be32                  cqn;
-        __be32                  field_select;
-        struct mlx5_cq_context  ctx;
-        u8                      rsvd[192];
-        __be64                  pas[0];
-};
-
-struct mlx5_modify_cq_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd[8];
-};
-
-struct mlx5_enable_hca_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        u8                      rsvd[8];
-};
-
-struct mlx5_enable_hca_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd[8];
-};
-
-struct mlx5_disable_hca_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        u8                      rsvd[8];
-};
-
-struct mlx5_disable_hca_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd[8];
-};
-
-struct mlx5_eq_context {
-        u8                      status;
-        u8                      ec_oi;
-        u8                      st;
-        u8                      rsvd2[7];
-        __be16                  page_pffset;
-        __be32                  log_sz_usr_page;
-        u8                      rsvd3[7];
-        u8                      intr;
-        u8                      log_page_size;
-        u8                      rsvd4[15];
-        __be32                  consumer_counter;
-        __be32                  produser_counter;
-        u8                      rsvd5[16];
-};
-
-struct mlx5_create_eq_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        u8                      rsvd0[3];
-        u8                      input_eqn;
-        u8                      rsvd1[4];
-        struct mlx5_eq_context  ctx;
-        u8                      rsvd2[8];
-        __be64                  events_mask;
-        u8                      rsvd3[176];
-        __be64                  pas[0];
-};
-
-struct mlx5_create_eq_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd0[3];
-        u8                      eq_number;
-        u8                      rsvd1[4];
-};
-
-struct mlx5_destroy_eq_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        u8                      rsvd0[3];
-        u8                      eqn;
-        u8                      rsvd1[4];
-};
-
-struct mlx5_destroy_eq_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd[8];
-};
-
-struct mlx5_map_eq_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be64                  mask;
-        u8                      mu;
-        u8                      rsvd0[2];
-        u8                      eqn;
-        u8                      rsvd1[24];
-};
-
-struct mlx5_map_eq_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd[8];
-};
-
-struct mlx5_query_eq_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        u8                      rsvd0[3];
-        u8                      eqn;
-        u8                      rsvd1[4];
-};
-
-struct mlx5_query_eq_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd[8];
-        struct mlx5_eq_context  ctx;
+enum {
+        MLX5_MKEY_STATUS_FREE = 1 << 6,
 };
 
 enum {
-        MLX5_MKEY_STATUS_FREE = 1 << 6,
+        MLX5_MKEY_REMOTE_INVAL  = 1 << 24,
+        MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
+        MLX5_MKEY_BSF_EN        = 1 << 30,
+        MLX5_MKEY_LEN64         = 1 << 31,
 };
 
 struct mlx5_mkey_seg {
@@ -1119,134 +824,12 @@ struct mlx5_mkey_seg {
         u8              rsvd4[4];
 };
 
-struct mlx5_query_special_ctxs_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        u8                      rsvd[8];
-};
-
-struct mlx5_query_special_ctxs_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        __be32                  dump_fill_mkey;
-        __be32                  reserved_lkey;
-};
-
-struct mlx5_create_mkey_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be32                  input_mkey_index;
-        __be32                  flags;
-        struct mlx5_mkey_seg    seg;
-        u8                      rsvd1[16];
-        __be32                  xlat_oct_act_size;
-        __be32                  rsvd2;
-        u8                      rsvd3[168];
-        __be64                  pas[0];
-};
-
-struct mlx5_create_mkey_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        __be32                  mkey;
-        u8                      rsvd[4];
-};
-
-struct mlx5_destroy_mkey_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be32                  mkey;
-        u8                      rsvd[4];
-};
-
-struct mlx5_destroy_mkey_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd[8];
-};
-
-struct mlx5_query_mkey_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be32                  mkey;
-};
-
-struct mlx5_query_mkey_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        __be64                  pas[0];
-};
-
-struct mlx5_modify_mkey_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be32                  mkey;
-        __be64                  pas[0];
-};
-
-struct mlx5_modify_mkey_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd[8];
-};
-
-struct mlx5_dump_mkey_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-};
-
-struct mlx5_dump_mkey_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        __be32                  mkey;
-};
-
-struct mlx5_mad_ifc_mbox_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be16                  remote_lid;
-        u8                      rsvd0;
-        u8                      port;
-        u8                      rsvd1[4];
-        u8                      data[256];
-};
-
-struct mlx5_mad_ifc_mbox_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd[8];
-        u8                      data[256];
-};
-
-struct mlx5_access_reg_mbox_in {
-        struct mlx5_inbox_hdr           hdr;
-        u8                              rsvd0[2];
-        __be16                          register_id;
-        __be32                          arg;
-        __be32                          data[0];
-};
-
-struct mlx5_access_reg_mbox_out {
-        struct mlx5_outbox_hdr          hdr;
-        u8                              rsvd[8];
-        __be32                          data[0];
-};
-
 #define MLX5_ATTR_EXTENDED_PORT_INFO    cpu_to_be16(0xff90)
 
 enum {
         MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO        = 1 <<  0
 };
 
-struct mlx5_allocate_psv_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be32                  npsv_pd;
-        __be32                  rsvd_psv0;
-};
-
-struct mlx5_allocate_psv_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd[8];
-        __be32                  psv_idx[4];
-};
-
-struct mlx5_destroy_psv_in {
-        struct mlx5_inbox_hdr   hdr;
-        __be32                  psv_number;
-        u8                      rsvd[4];
-};
-
-struct mlx5_destroy_psv_out {
-        struct mlx5_outbox_hdr  hdr;
-        u8                      rsvd[8];
-};
-
 enum {
         VPORT_STATE_DOWN                = 0x0,
         VPORT_STATE_UP                  = 0x1,
@@ -1381,6 +964,18 @@ enum mlx5_cap_type {
 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
 
+#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
+        MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
+
+#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
+        MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
+
+#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
+        MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
+
+#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
+        MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
+
 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
         MLX5_GET(flow_table_eswitch_cap, \
                  mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)