aboutsummaryrefslogtreecommitdiffstats
path: root/include/linux/mlx5/device.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/linux/mlx5/device.h')
-rw-r--r--include/linux/mlx5/device.h441
1 files changed, 18 insertions, 423 deletions
diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index 0b6d15cddb2f..77c141797152 100644
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -198,19 +198,6 @@ enum {
198}; 198};
199 199
200enum { 200enum {
201 MLX5_ACCESS_MODE_PA = 0,
202 MLX5_ACCESS_MODE_MTT = 1,
203 MLX5_ACCESS_MODE_KLM = 2
204};
205
206enum {
207 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
208 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
209 MLX5_MKEY_BSF_EN = 1 << 30,
210 MLX5_MKEY_LEN64 = 1 << 31,
211};
212
213enum {
214 MLX5_EN_RD = (u64)1, 201 MLX5_EN_RD = (u64)1,
215 MLX5_EN_WR = (u64)2 202 MLX5_EN_WR = (u64)2
216}; 203};
@@ -411,33 +398,6 @@ enum {
411 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 398 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
412}; 399};
413 400
414struct mlx5_inbox_hdr {
415 __be16 opcode;
416 u8 rsvd[4];
417 __be16 opmod;
418};
419
420struct mlx5_outbox_hdr {
421 u8 status;
422 u8 rsvd[3];
423 __be32 syndrome;
424};
425
426struct mlx5_cmd_query_adapter_mbox_in {
427 struct mlx5_inbox_hdr hdr;
428 u8 rsvd[8];
429};
430
431struct mlx5_cmd_query_adapter_mbox_out {
432 struct mlx5_outbox_hdr hdr;
433 u8 rsvd0[24];
434 u8 intapin;
435 u8 rsvd1[13];
436 __be16 vsd_vendor_id;
437 u8 vsd[208];
438 u8 vsd_psid[16];
439};
440
441enum mlx5_odp_transport_cap_bits { 401enum mlx5_odp_transport_cap_bits {
442 MLX5_ODP_SUPPORT_SEND = 1 << 31, 402 MLX5_ODP_SUPPORT_SEND = 1 << 31,
443 MLX5_ODP_SUPPORT_RECV = 1 << 30, 403 MLX5_ODP_SUPPORT_RECV = 1 << 30,
@@ -455,30 +415,6 @@ struct mlx5_odp_caps {
455 char reserved2[0xe4]; 415 char reserved2[0xe4];
456}; 416};
457 417
458struct mlx5_cmd_init_hca_mbox_in {
459 struct mlx5_inbox_hdr hdr;
460 u8 rsvd0[2];
461 __be16 profile;
462 u8 rsvd1[4];
463};
464
465struct mlx5_cmd_init_hca_mbox_out {
466 struct mlx5_outbox_hdr hdr;
467 u8 rsvd[8];
468};
469
470struct mlx5_cmd_teardown_hca_mbox_in {
471 struct mlx5_inbox_hdr hdr;
472 u8 rsvd0[2];
473 __be16 profile;
474 u8 rsvd1[4];
475};
476
477struct mlx5_cmd_teardown_hca_mbox_out {
478 struct mlx5_outbox_hdr hdr;
479 u8 rsvd[8];
480};
481
482struct mlx5_cmd_layout { 418struct mlx5_cmd_layout {
483 u8 type; 419 u8 type;
484 u8 rsvd0[3]; 420 u8 rsvd0[3];
@@ -494,7 +430,6 @@ struct mlx5_cmd_layout {
494 u8 status_own; 430 u8 status_own;
495}; 431};
496 432
497
498struct health_buffer { 433struct health_buffer {
499 __be32 assert_var[5]; 434 __be32 assert_var[5];
500 __be32 rsvd0[3]; 435 __be32 rsvd0[3];
@@ -856,245 +791,15 @@ struct mlx5_cqe128 {
856 struct mlx5_cqe64 cqe64; 791 struct mlx5_cqe64 cqe64;
857}; 792};
858 793
859struct mlx5_srq_ctx { 794enum {
860 u8 state_log_sz; 795 MLX5_MKEY_STATUS_FREE = 1 << 6,
861 u8 rsvd0[3];
862 __be32 flags_xrcd;
863 __be32 pgoff_cqn;
864 u8 rsvd1[4];
865 u8 log_pg_sz;
866 u8 rsvd2[7];
867 __be32 pd;
868 __be16 lwm;
869 __be16 wqe_cnt;
870 u8 rsvd3[8];
871 __be64 db_record;
872};
873
874struct mlx5_create_srq_mbox_in {
875 struct mlx5_inbox_hdr hdr;
876 __be32 input_srqn;
877 u8 rsvd0[4];
878 struct mlx5_srq_ctx ctx;
879 u8 rsvd1[208];
880 __be64 pas[0];
881};
882
883struct mlx5_create_srq_mbox_out {
884 struct mlx5_outbox_hdr hdr;
885 __be32 srqn;
886 u8 rsvd[4];
887};
888
889struct mlx5_destroy_srq_mbox_in {
890 struct mlx5_inbox_hdr hdr;
891 __be32 srqn;
892 u8 rsvd[4];
893};
894
895struct mlx5_destroy_srq_mbox_out {
896 struct mlx5_outbox_hdr hdr;
897 u8 rsvd[8];
898};
899
900struct mlx5_query_srq_mbox_in {
901 struct mlx5_inbox_hdr hdr;
902 __be32 srqn;
903 u8 rsvd0[4];
904};
905
906struct mlx5_query_srq_mbox_out {
907 struct mlx5_outbox_hdr hdr;
908 u8 rsvd0[8];
909 struct mlx5_srq_ctx ctx;
910 u8 rsvd1[32];
911 __be64 pas[0];
912};
913
914struct mlx5_arm_srq_mbox_in {
915 struct mlx5_inbox_hdr hdr;
916 __be32 srqn;
917 __be16 rsvd;
918 __be16 lwm;
919};
920
921struct mlx5_arm_srq_mbox_out {
922 struct mlx5_outbox_hdr hdr;
923 u8 rsvd[8];
924};
925
926struct mlx5_cq_context {
927 u8 status;
928 u8 cqe_sz_flags;
929 u8 st;
930 u8 rsvd3;
931 u8 rsvd4[6];
932 __be16 page_offset;
933 __be32 log_sz_usr_page;
934 __be16 cq_period;
935 __be16 cq_max_count;
936 __be16 rsvd20;
937 __be16 c_eqn;
938 u8 log_pg_sz;
939 u8 rsvd25[7];
940 __be32 last_notified_index;
941 __be32 solicit_producer_index;
942 __be32 consumer_counter;
943 __be32 producer_counter;
944 u8 rsvd48[8];
945 __be64 db_record_addr;
946};
947
948struct mlx5_create_cq_mbox_in {
949 struct mlx5_inbox_hdr hdr;
950 __be32 input_cqn;
951 u8 rsvdx[4];
952 struct mlx5_cq_context ctx;
953 u8 rsvd6[192];
954 __be64 pas[0];
955};
956
957struct mlx5_create_cq_mbox_out {
958 struct mlx5_outbox_hdr hdr;
959 __be32 cqn;
960 u8 rsvd0[4];
961};
962
963struct mlx5_destroy_cq_mbox_in {
964 struct mlx5_inbox_hdr hdr;
965 __be32 cqn;
966 u8 rsvd0[4];
967};
968
969struct mlx5_destroy_cq_mbox_out {
970 struct mlx5_outbox_hdr hdr;
971 u8 rsvd0[8];
972};
973
974struct mlx5_query_cq_mbox_in {
975 struct mlx5_inbox_hdr hdr;
976 __be32 cqn;
977 u8 rsvd0[4];
978};
979
980struct mlx5_query_cq_mbox_out {
981 struct mlx5_outbox_hdr hdr;
982 u8 rsvd0[8];
983 struct mlx5_cq_context ctx;
984 u8 rsvd6[16];
985 __be64 pas[0];
986};
987
988struct mlx5_modify_cq_mbox_in {
989 struct mlx5_inbox_hdr hdr;
990 __be32 cqn;
991 __be32 field_select;
992 struct mlx5_cq_context ctx;
993 u8 rsvd[192];
994 __be64 pas[0];
995};
996
997struct mlx5_modify_cq_mbox_out {
998 struct mlx5_outbox_hdr hdr;
999 u8 rsvd[8];
1000};
1001
1002struct mlx5_enable_hca_mbox_in {
1003 struct mlx5_inbox_hdr hdr;
1004 u8 rsvd[8];
1005};
1006
1007struct mlx5_enable_hca_mbox_out {
1008 struct mlx5_outbox_hdr hdr;
1009 u8 rsvd[8];
1010};
1011
1012struct mlx5_disable_hca_mbox_in {
1013 struct mlx5_inbox_hdr hdr;
1014 u8 rsvd[8];
1015};
1016
1017struct mlx5_disable_hca_mbox_out {
1018 struct mlx5_outbox_hdr hdr;
1019 u8 rsvd[8];
1020};
1021
1022struct mlx5_eq_context {
1023 u8 status;
1024 u8 ec_oi;
1025 u8 st;
1026 u8 rsvd2[7];
1027 __be16 page_pffset;
1028 __be32 log_sz_usr_page;
1029 u8 rsvd3[7];
1030 u8 intr;
1031 u8 log_page_size;
1032 u8 rsvd4[15];
1033 __be32 consumer_counter;
1034 __be32 produser_counter;
1035 u8 rsvd5[16];
1036};
1037
1038struct mlx5_create_eq_mbox_in {
1039 struct mlx5_inbox_hdr hdr;
1040 u8 rsvd0[3];
1041 u8 input_eqn;
1042 u8 rsvd1[4];
1043 struct mlx5_eq_context ctx;
1044 u8 rsvd2[8];
1045 __be64 events_mask;
1046 u8 rsvd3[176];
1047 __be64 pas[0];
1048};
1049
1050struct mlx5_create_eq_mbox_out {
1051 struct mlx5_outbox_hdr hdr;
1052 u8 rsvd0[3];
1053 u8 eq_number;
1054 u8 rsvd1[4];
1055};
1056
1057struct mlx5_destroy_eq_mbox_in {
1058 struct mlx5_inbox_hdr hdr;
1059 u8 rsvd0[3];
1060 u8 eqn;
1061 u8 rsvd1[4];
1062};
1063
1064struct mlx5_destroy_eq_mbox_out {
1065 struct mlx5_outbox_hdr hdr;
1066 u8 rsvd[8];
1067};
1068
1069struct mlx5_map_eq_mbox_in {
1070 struct mlx5_inbox_hdr hdr;
1071 __be64 mask;
1072 u8 mu;
1073 u8 rsvd0[2];
1074 u8 eqn;
1075 u8 rsvd1[24];
1076};
1077
1078struct mlx5_map_eq_mbox_out {
1079 struct mlx5_outbox_hdr hdr;
1080 u8 rsvd[8];
1081};
1082
1083struct mlx5_query_eq_mbox_in {
1084 struct mlx5_inbox_hdr hdr;
1085 u8 rsvd0[3];
1086 u8 eqn;
1087 u8 rsvd1[4];
1088};
1089
1090struct mlx5_query_eq_mbox_out {
1091 struct mlx5_outbox_hdr hdr;
1092 u8 rsvd[8];
1093 struct mlx5_eq_context ctx;
1094}; 796};
1095 797
1096enum { 798enum {
1097 MLX5_MKEY_STATUS_FREE = 1 << 6, 799 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
800 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
801 MLX5_MKEY_BSF_EN = 1 << 30,
802 MLX5_MKEY_LEN64 = 1 << 31,
1098}; 803};
1099 804
1100struct mlx5_mkey_seg { 805struct mlx5_mkey_seg {
@@ -1119,134 +824,12 @@ struct mlx5_mkey_seg {
1119 u8 rsvd4[4]; 824 u8 rsvd4[4];
1120}; 825};
1121 826
1122struct mlx5_query_special_ctxs_mbox_in {
1123 struct mlx5_inbox_hdr hdr;
1124 u8 rsvd[8];
1125};
1126
1127struct mlx5_query_special_ctxs_mbox_out {
1128 struct mlx5_outbox_hdr hdr;
1129 __be32 dump_fill_mkey;
1130 __be32 reserved_lkey;
1131};
1132
1133struct mlx5_create_mkey_mbox_in {
1134 struct mlx5_inbox_hdr hdr;
1135 __be32 input_mkey_index;
1136 __be32 flags;
1137 struct mlx5_mkey_seg seg;
1138 u8 rsvd1[16];
1139 __be32 xlat_oct_act_size;
1140 __be32 rsvd2;
1141 u8 rsvd3[168];
1142 __be64 pas[0];
1143};
1144
1145struct mlx5_create_mkey_mbox_out {
1146 struct mlx5_outbox_hdr hdr;
1147 __be32 mkey;
1148 u8 rsvd[4];
1149};
1150
1151struct mlx5_destroy_mkey_mbox_in {
1152 struct mlx5_inbox_hdr hdr;
1153 __be32 mkey;
1154 u8 rsvd[4];
1155};
1156
1157struct mlx5_destroy_mkey_mbox_out {
1158 struct mlx5_outbox_hdr hdr;
1159 u8 rsvd[8];
1160};
1161
1162struct mlx5_query_mkey_mbox_in {
1163 struct mlx5_inbox_hdr hdr;
1164 __be32 mkey;
1165};
1166
1167struct mlx5_query_mkey_mbox_out {
1168 struct mlx5_outbox_hdr hdr;
1169 __be64 pas[0];
1170};
1171
1172struct mlx5_modify_mkey_mbox_in {
1173 struct mlx5_inbox_hdr hdr;
1174 __be32 mkey;
1175 __be64 pas[0];
1176};
1177
1178struct mlx5_modify_mkey_mbox_out {
1179 struct mlx5_outbox_hdr hdr;
1180 u8 rsvd[8];
1181};
1182
1183struct mlx5_dump_mkey_mbox_in {
1184 struct mlx5_inbox_hdr hdr;
1185};
1186
1187struct mlx5_dump_mkey_mbox_out {
1188 struct mlx5_outbox_hdr hdr;
1189 __be32 mkey;
1190};
1191
1192struct mlx5_mad_ifc_mbox_in {
1193 struct mlx5_inbox_hdr hdr;
1194 __be16 remote_lid;
1195 u8 rsvd0;
1196 u8 port;
1197 u8 rsvd1[4];
1198 u8 data[256];
1199};
1200
1201struct mlx5_mad_ifc_mbox_out {
1202 struct mlx5_outbox_hdr hdr;
1203 u8 rsvd[8];
1204 u8 data[256];
1205};
1206
1207struct mlx5_access_reg_mbox_in {
1208 struct mlx5_inbox_hdr hdr;
1209 u8 rsvd0[2];
1210 __be16 register_id;
1211 __be32 arg;
1212 __be32 data[0];
1213};
1214
1215struct mlx5_access_reg_mbox_out {
1216 struct mlx5_outbox_hdr hdr;
1217 u8 rsvd[8];
1218 __be32 data[0];
1219};
1220
1221#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 827#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1222 828
1223enum { 829enum {
1224 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 830 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1225}; 831};
1226 832
1227struct mlx5_allocate_psv_in {
1228 struct mlx5_inbox_hdr hdr;
1229 __be32 npsv_pd;
1230 __be32 rsvd_psv0;
1231};
1232
1233struct mlx5_allocate_psv_out {
1234 struct mlx5_outbox_hdr hdr;
1235 u8 rsvd[8];
1236 __be32 psv_idx[4];
1237};
1238
1239struct mlx5_destroy_psv_in {
1240 struct mlx5_inbox_hdr hdr;
1241 __be32 psv_number;
1242 u8 rsvd[4];
1243};
1244
1245struct mlx5_destroy_psv_out {
1246 struct mlx5_outbox_hdr hdr;
1247 u8 rsvd[8];
1248};
1249
1250enum { 833enum {
1251 VPORT_STATE_DOWN = 0x0, 834 VPORT_STATE_DOWN = 0x0,
1252 VPORT_STATE_UP = 0x1, 835 VPORT_STATE_UP = 0x1,
@@ -1381,6 +964,18 @@ enum mlx5_cap_type {
1381#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \ 964#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1382 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap) 965 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1383 966
967#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
968 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
969
970#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
971 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
972
973#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
974 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
975
976#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
977 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
978
1384#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 979#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1385 MLX5_GET(flow_table_eswitch_cap, \ 980 MLX5_GET(flow_table_eswitch_cap, \
1386 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 981 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-12 06:47:02 -0400