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authorLinus Torvalds <torvalds@linux-foundation.org>2016-10-05 13:11:24 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2016-10-05 13:11:24 -0400
commit687ee0ad4e897e29f4b41f7a20c866d74c5e0660 (patch)
treeb31a2af35c24a54823674cdd126993b80daeac67 /include/linux/mlx5
parent3ddf40e8c31964b744ff10abb48c8e36a83ec6e7 (diff)
parent03a1eabc3f54469abd4f1784182851b2e29630cc (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next
Pull networking updates from David Miller: 1) BBR TCP congestion control, from Neal Cardwell, Yuchung Cheng and co. at Google. https://lwn.net/Articles/701165/ 2) Do TCP Small Queues for retransmits, from Eric Dumazet. 3) Support collect_md mode for all IPV4 and IPV6 tunnels, from Alexei Starovoitov. 4) Allow cls_flower to classify packets in ip tunnels, from Amir Vadai. 5) Support DSA tagging in older mv88e6xxx switches, from Andrew Lunn. 6) Support GMAC protocol in iwlwifi mwm, from Ayala Beker. 7) Support ndo_poll_controller in mlx5, from Calvin Owens. 8) Move VRF processing to an output hook and allow l3mdev to be loopback, from David Ahern. 9) Support SOCK_DESTROY for UDP sockets. Also from David Ahern. 10) Congestion control in RXRPC, from David Howells. 11) Support geneve RX offload in ixgbe, from Emil Tantilov. 12) When hitting pressure for new incoming TCP data SKBs, perform a partial rathern than a full purge of the OFO queue (which could be huge). From Eric Dumazet. 13) Convert XFRM state and policy lookups to RCU, from Florian Westphal. 14) Support RX network flow classification to igb, from Gangfeng Huang. 15) Hardware offloading of eBPF in nfp driver, from Jakub Kicinski. 16) New skbmod packet action, from Jamal Hadi Salim. 17) Remove some inefficiencies in snmp proc output, from Jia He. 18) Add FIB notifications to properly propagate route changes to hardware which is doing forwarding offloading. From Jiri Pirko. 19) New dsa driver for qca8xxx chips, from John Crispin. 20) Implement RFC7559 ipv6 router solicitation backoff, from Maciej Żenczykowski. 21) Add L3 mode to ipvlan, from Mahesh Bandewar. 22) Support 802.1ad in mlx4, from Moshe Shemesh. 23) Support hardware LRO in mediatek driver, from Nelson Chang. 24) Add TC offloading to mlx5, from Or Gerlitz. 25) Convert various drivers to ethtool ksettings interfaces, from Philippe Reynes. 26) TX max rate limiting for cxgb4, from Rahul Lakkireddy. 27) NAPI support for ath10k, from Rajkumar Manoharan. 28) Support XDP in mlx5, from Rana Shahout and Saeed Mahameed. 29) UDP replicast support in TIPC, from Richard Alpe. 30) Per-queue statistics for qed driver, from Sudarsana Reddy Kalluru. 31) Support BQL in thunderx driver, from Sunil Goutham. 32) TSO support in alx driver, from Tobias Regnery. 33) Add stream parser engine and use it in kcm. 34) Support async DHCP replies in ipconfig module, from Uwe Kleine-König. 35) DSA port fast aging for mv88e6xxx driver, from Vivien Didelot. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1715 commits) mlxsw: switchx2: Fix misuse of hard_header_len mlxsw: spectrum: Fix misuse of hard_header_len net/faraday: Stop NCSI device on shutdown net/ncsi: Introduce ncsi_stop_dev() net/ncsi: Rework the channel monitoring net/ncsi: Allow to extend NCSI request properties net/ncsi: Rework request index allocation net/ncsi: Don't probe on the reserved channel ID (0x1f) net/ncsi: Introduce NCSI_RESERVED_CHANNEL net/ncsi: Avoid unused-value build warning from ia64-linux-gcc net: Add netdev all_adj_list refcnt propagation to fix panic net: phy: Add Edge-rate driver for Microsemi PHYs. vmxnet3: Wake queue from reset work i40e: avoid NULL pointer dereference and recursive errors on early PCI error qed: Add RoCE ll2 & GSI support qed: Add support for memory registeration verbs qed: Add support for QP verbs qed: PD,PKEY and CQ verb support qed: Add support for RoCE hw init qede: Add qedr framework ...
Diffstat (limited to 'include/linux/mlx5')
-rw-r--r--include/linux/mlx5/cq.h6
-rw-r--r--include/linux/mlx5/device.h441
-rw-r--r--include/linux/mlx5/driver.h35
-rw-r--r--include/linux/mlx5/fs.h6
-rw-r--r--include/linux/mlx5/mlx5_ifc.h297
-rw-r--r--include/linux/mlx5/port.h40
-rw-r--r--include/linux/mlx5/qp.h128
-rw-r--r--include/linux/mlx5/vport.h2
8 files changed, 376 insertions, 579 deletions
diff --git a/include/linux/mlx5/cq.h b/include/linux/mlx5/cq.h
index 2566f6d6444f..7c3c0d3aca37 100644
--- a/include/linux/mlx5/cq.h
+++ b/include/linux/mlx5/cq.h
@@ -170,12 +170,12 @@ static inline void mlx5_cq_arm(struct mlx5_core_cq *cq, u32 cmd,
170int mlx5_init_cq_table(struct mlx5_core_dev *dev); 170int mlx5_init_cq_table(struct mlx5_core_dev *dev);
171void mlx5_cleanup_cq_table(struct mlx5_core_dev *dev); 171void mlx5_cleanup_cq_table(struct mlx5_core_dev *dev);
172int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, 172int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
173 struct mlx5_create_cq_mbox_in *in, int inlen); 173 u32 *in, int inlen);
174int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq); 174int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
175int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, 175int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
176 struct mlx5_query_cq_mbox_out *out); 176 u32 *out, int outlen);
177int mlx5_core_modify_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq, 177int mlx5_core_modify_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
178 struct mlx5_modify_cq_mbox_in *in, int in_sz); 178 u32 *in, int inlen);
179int mlx5_core_modify_cq_moderation(struct mlx5_core_dev *dev, 179int mlx5_core_modify_cq_moderation(struct mlx5_core_dev *dev,
180 struct mlx5_core_cq *cq, u16 cq_period, 180 struct mlx5_core_cq *cq, u16 cq_period,
181 u16 cq_max_count); 181 u16 cq_max_count);
diff --git a/include/linux/mlx5/device.h b/include/linux/mlx5/device.h
index 0b6d15cddb2f..77c141797152 100644
--- a/include/linux/mlx5/device.h
+++ b/include/linux/mlx5/device.h
@@ -198,19 +198,6 @@ enum {
198}; 198};
199 199
200enum { 200enum {
201 MLX5_ACCESS_MODE_PA = 0,
202 MLX5_ACCESS_MODE_MTT = 1,
203 MLX5_ACCESS_MODE_KLM = 2
204};
205
206enum {
207 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
208 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
209 MLX5_MKEY_BSF_EN = 1 << 30,
210 MLX5_MKEY_LEN64 = 1 << 31,
211};
212
213enum {
214 MLX5_EN_RD = (u64)1, 201 MLX5_EN_RD = (u64)1,
215 MLX5_EN_WR = (u64)2 202 MLX5_EN_WR = (u64)2
216}; 203};
@@ -411,33 +398,6 @@ enum {
411 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16 398 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
412}; 399};
413 400
414struct mlx5_inbox_hdr {
415 __be16 opcode;
416 u8 rsvd[4];
417 __be16 opmod;
418};
419
420struct mlx5_outbox_hdr {
421 u8 status;
422 u8 rsvd[3];
423 __be32 syndrome;
424};
425
426struct mlx5_cmd_query_adapter_mbox_in {
427 struct mlx5_inbox_hdr hdr;
428 u8 rsvd[8];
429};
430
431struct mlx5_cmd_query_adapter_mbox_out {
432 struct mlx5_outbox_hdr hdr;
433 u8 rsvd0[24];
434 u8 intapin;
435 u8 rsvd1[13];
436 __be16 vsd_vendor_id;
437 u8 vsd[208];
438 u8 vsd_psid[16];
439};
440
441enum mlx5_odp_transport_cap_bits { 401enum mlx5_odp_transport_cap_bits {
442 MLX5_ODP_SUPPORT_SEND = 1 << 31, 402 MLX5_ODP_SUPPORT_SEND = 1 << 31,
443 MLX5_ODP_SUPPORT_RECV = 1 << 30, 403 MLX5_ODP_SUPPORT_RECV = 1 << 30,
@@ -455,30 +415,6 @@ struct mlx5_odp_caps {
455 char reserved2[0xe4]; 415 char reserved2[0xe4];
456}; 416};
457 417
458struct mlx5_cmd_init_hca_mbox_in {
459 struct mlx5_inbox_hdr hdr;
460 u8 rsvd0[2];
461 __be16 profile;
462 u8 rsvd1[4];
463};
464
465struct mlx5_cmd_init_hca_mbox_out {
466 struct mlx5_outbox_hdr hdr;
467 u8 rsvd[8];
468};
469
470struct mlx5_cmd_teardown_hca_mbox_in {
471 struct mlx5_inbox_hdr hdr;
472 u8 rsvd0[2];
473 __be16 profile;
474 u8 rsvd1[4];
475};
476
477struct mlx5_cmd_teardown_hca_mbox_out {
478 struct mlx5_outbox_hdr hdr;
479 u8 rsvd[8];
480};
481
482struct mlx5_cmd_layout { 418struct mlx5_cmd_layout {
483 u8 type; 419 u8 type;
484 u8 rsvd0[3]; 420 u8 rsvd0[3];
@@ -494,7 +430,6 @@ struct mlx5_cmd_layout {
494 u8 status_own; 430 u8 status_own;
495}; 431};
496 432
497
498struct health_buffer { 433struct health_buffer {
499 __be32 assert_var[5]; 434 __be32 assert_var[5];
500 __be32 rsvd0[3]; 435 __be32 rsvd0[3];
@@ -856,245 +791,15 @@ struct mlx5_cqe128 {
856 struct mlx5_cqe64 cqe64; 791 struct mlx5_cqe64 cqe64;
857}; 792};
858 793
859struct mlx5_srq_ctx { 794enum {
860 u8 state_log_sz; 795 MLX5_MKEY_STATUS_FREE = 1 << 6,
861 u8 rsvd0[3];
862 __be32 flags_xrcd;
863 __be32 pgoff_cqn;
864 u8 rsvd1[4];
865 u8 log_pg_sz;
866 u8 rsvd2[7];
867 __be32 pd;
868 __be16 lwm;
869 __be16 wqe_cnt;
870 u8 rsvd3[8];
871 __be64 db_record;
872};
873
874struct mlx5_create_srq_mbox_in {
875 struct mlx5_inbox_hdr hdr;
876 __be32 input_srqn;
877 u8 rsvd0[4];
878 struct mlx5_srq_ctx ctx;
879 u8 rsvd1[208];
880 __be64 pas[0];
881};
882
883struct mlx5_create_srq_mbox_out {
884 struct mlx5_outbox_hdr hdr;
885 __be32 srqn;
886 u8 rsvd[4];
887};
888
889struct mlx5_destroy_srq_mbox_in {
890 struct mlx5_inbox_hdr hdr;
891 __be32 srqn;
892 u8 rsvd[4];
893};
894
895struct mlx5_destroy_srq_mbox_out {
896 struct mlx5_outbox_hdr hdr;
897 u8 rsvd[8];
898};
899
900struct mlx5_query_srq_mbox_in {
901 struct mlx5_inbox_hdr hdr;
902 __be32 srqn;
903 u8 rsvd0[4];
904};
905
906struct mlx5_query_srq_mbox_out {
907 struct mlx5_outbox_hdr hdr;
908 u8 rsvd0[8];
909 struct mlx5_srq_ctx ctx;
910 u8 rsvd1[32];
911 __be64 pas[0];
912};
913
914struct mlx5_arm_srq_mbox_in {
915 struct mlx5_inbox_hdr hdr;
916 __be32 srqn;
917 __be16 rsvd;
918 __be16 lwm;
919};
920
921struct mlx5_arm_srq_mbox_out {
922 struct mlx5_outbox_hdr hdr;
923 u8 rsvd[8];
924};
925
926struct mlx5_cq_context {
927 u8 status;
928 u8 cqe_sz_flags;
929 u8 st;
930 u8 rsvd3;
931 u8 rsvd4[6];
932 __be16 page_offset;
933 __be32 log_sz_usr_page;
934 __be16 cq_period;
935 __be16 cq_max_count;
936 __be16 rsvd20;
937 __be16 c_eqn;
938 u8 log_pg_sz;
939 u8 rsvd25[7];
940 __be32 last_notified_index;
941 __be32 solicit_producer_index;
942 __be32 consumer_counter;
943 __be32 producer_counter;
944 u8 rsvd48[8];
945 __be64 db_record_addr;
946};
947
948struct mlx5_create_cq_mbox_in {
949 struct mlx5_inbox_hdr hdr;
950 __be32 input_cqn;
951 u8 rsvdx[4];
952 struct mlx5_cq_context ctx;
953 u8 rsvd6[192];
954 __be64 pas[0];
955};
956
957struct mlx5_create_cq_mbox_out {
958 struct mlx5_outbox_hdr hdr;
959 __be32 cqn;
960 u8 rsvd0[4];
961};
962
963struct mlx5_destroy_cq_mbox_in {
964 struct mlx5_inbox_hdr hdr;
965 __be32 cqn;
966 u8 rsvd0[4];
967};
968
969struct mlx5_destroy_cq_mbox_out {
970 struct mlx5_outbox_hdr hdr;
971 u8 rsvd0[8];
972};
973
974struct mlx5_query_cq_mbox_in {
975 struct mlx5_inbox_hdr hdr;
976 __be32 cqn;
977 u8 rsvd0[4];
978};
979
980struct mlx5_query_cq_mbox_out {
981 struct mlx5_outbox_hdr hdr;
982 u8 rsvd0[8];
983 struct mlx5_cq_context ctx;
984 u8 rsvd6[16];
985 __be64 pas[0];
986};
987
988struct mlx5_modify_cq_mbox_in {
989 struct mlx5_inbox_hdr hdr;
990 __be32 cqn;
991 __be32 field_select;
992 struct mlx5_cq_context ctx;
993 u8 rsvd[192];
994 __be64 pas[0];
995};
996
997struct mlx5_modify_cq_mbox_out {
998 struct mlx5_outbox_hdr hdr;
999 u8 rsvd[8];
1000};
1001
1002struct mlx5_enable_hca_mbox_in {
1003 struct mlx5_inbox_hdr hdr;
1004 u8 rsvd[8];
1005};
1006
1007struct mlx5_enable_hca_mbox_out {
1008 struct mlx5_outbox_hdr hdr;
1009 u8 rsvd[8];
1010};
1011
1012struct mlx5_disable_hca_mbox_in {
1013 struct mlx5_inbox_hdr hdr;
1014 u8 rsvd[8];
1015};
1016
1017struct mlx5_disable_hca_mbox_out {
1018 struct mlx5_outbox_hdr hdr;
1019 u8 rsvd[8];
1020};
1021
1022struct mlx5_eq_context {
1023 u8 status;
1024 u8 ec_oi;
1025 u8 st;
1026 u8 rsvd2[7];
1027 __be16 page_pffset;
1028 __be32 log_sz_usr_page;
1029 u8 rsvd3[7];
1030 u8 intr;
1031 u8 log_page_size;
1032 u8 rsvd4[15];
1033 __be32 consumer_counter;
1034 __be32 produser_counter;
1035 u8 rsvd5[16];
1036};
1037
1038struct mlx5_create_eq_mbox_in {
1039 struct mlx5_inbox_hdr hdr;
1040 u8 rsvd0[3];
1041 u8 input_eqn;
1042 u8 rsvd1[4];
1043 struct mlx5_eq_context ctx;
1044 u8 rsvd2[8];
1045 __be64 events_mask;
1046 u8 rsvd3[176];
1047 __be64 pas[0];
1048};
1049
1050struct mlx5_create_eq_mbox_out {
1051 struct mlx5_outbox_hdr hdr;
1052 u8 rsvd0[3];
1053 u8 eq_number;
1054 u8 rsvd1[4];
1055};
1056
1057struct mlx5_destroy_eq_mbox_in {
1058 struct mlx5_inbox_hdr hdr;
1059 u8 rsvd0[3];
1060 u8 eqn;
1061 u8 rsvd1[4];
1062};
1063
1064struct mlx5_destroy_eq_mbox_out {
1065 struct mlx5_outbox_hdr hdr;
1066 u8 rsvd[8];
1067};
1068
1069struct mlx5_map_eq_mbox_in {
1070 struct mlx5_inbox_hdr hdr;
1071 __be64 mask;
1072 u8 mu;
1073 u8 rsvd0[2];
1074 u8 eqn;
1075 u8 rsvd1[24];
1076};
1077
1078struct mlx5_map_eq_mbox_out {
1079 struct mlx5_outbox_hdr hdr;
1080 u8 rsvd[8];
1081};
1082
1083struct mlx5_query_eq_mbox_in {
1084 struct mlx5_inbox_hdr hdr;
1085 u8 rsvd0[3];
1086 u8 eqn;
1087 u8 rsvd1[4];
1088};
1089
1090struct mlx5_query_eq_mbox_out {
1091 struct mlx5_outbox_hdr hdr;
1092 u8 rsvd[8];
1093 struct mlx5_eq_context ctx;
1094}; 796};
1095 797
1096enum { 798enum {
1097 MLX5_MKEY_STATUS_FREE = 1 << 6, 799 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
800 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
801 MLX5_MKEY_BSF_EN = 1 << 30,
802 MLX5_MKEY_LEN64 = 1 << 31,
1098}; 803};
1099 804
1100struct mlx5_mkey_seg { 805struct mlx5_mkey_seg {
@@ -1119,134 +824,12 @@ struct mlx5_mkey_seg {
1119 u8 rsvd4[4]; 824 u8 rsvd4[4];
1120}; 825};
1121 826
1122struct mlx5_query_special_ctxs_mbox_in {
1123 struct mlx5_inbox_hdr hdr;
1124 u8 rsvd[8];
1125};
1126
1127struct mlx5_query_special_ctxs_mbox_out {
1128 struct mlx5_outbox_hdr hdr;
1129 __be32 dump_fill_mkey;
1130 __be32 reserved_lkey;
1131};
1132
1133struct mlx5_create_mkey_mbox_in {
1134 struct mlx5_inbox_hdr hdr;
1135 __be32 input_mkey_index;
1136 __be32 flags;
1137 struct mlx5_mkey_seg seg;
1138 u8 rsvd1[16];
1139 __be32 xlat_oct_act_size;
1140 __be32 rsvd2;
1141 u8 rsvd3[168];
1142 __be64 pas[0];
1143};
1144
1145struct mlx5_create_mkey_mbox_out {
1146 struct mlx5_outbox_hdr hdr;
1147 __be32 mkey;
1148 u8 rsvd[4];
1149};
1150
1151struct mlx5_destroy_mkey_mbox_in {
1152 struct mlx5_inbox_hdr hdr;
1153 __be32 mkey;
1154 u8 rsvd[4];
1155};
1156
1157struct mlx5_destroy_mkey_mbox_out {
1158 struct mlx5_outbox_hdr hdr;
1159 u8 rsvd[8];
1160};
1161
1162struct mlx5_query_mkey_mbox_in {
1163 struct mlx5_inbox_hdr hdr;
1164 __be32 mkey;
1165};
1166
1167struct mlx5_query_mkey_mbox_out {
1168 struct mlx5_outbox_hdr hdr;
1169 __be64 pas[0];
1170};
1171
1172struct mlx5_modify_mkey_mbox_in {
1173 struct mlx5_inbox_hdr hdr;
1174 __be32 mkey;
1175 __be64 pas[0];
1176};
1177
1178struct mlx5_modify_mkey_mbox_out {
1179 struct mlx5_outbox_hdr hdr;
1180 u8 rsvd[8];
1181};
1182
1183struct mlx5_dump_mkey_mbox_in {
1184 struct mlx5_inbox_hdr hdr;
1185};
1186
1187struct mlx5_dump_mkey_mbox_out {
1188 struct mlx5_outbox_hdr hdr;
1189 __be32 mkey;
1190};
1191
1192struct mlx5_mad_ifc_mbox_in {
1193 struct mlx5_inbox_hdr hdr;
1194 __be16 remote_lid;
1195 u8 rsvd0;
1196 u8 port;
1197 u8 rsvd1[4];
1198 u8 data[256];
1199};
1200
1201struct mlx5_mad_ifc_mbox_out {
1202 struct mlx5_outbox_hdr hdr;
1203 u8 rsvd[8];
1204 u8 data[256];
1205};
1206
1207struct mlx5_access_reg_mbox_in {
1208 struct mlx5_inbox_hdr hdr;
1209 u8 rsvd0[2];
1210 __be16 register_id;
1211 __be32 arg;
1212 __be32 data[0];
1213};
1214
1215struct mlx5_access_reg_mbox_out {
1216 struct mlx5_outbox_hdr hdr;
1217 u8 rsvd[8];
1218 __be32 data[0];
1219};
1220
1221#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 827#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
1222 828
1223enum { 829enum {
1224 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 830 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
1225}; 831};
1226 832
1227struct mlx5_allocate_psv_in {
1228 struct mlx5_inbox_hdr hdr;
1229 __be32 npsv_pd;
1230 __be32 rsvd_psv0;
1231};
1232
1233struct mlx5_allocate_psv_out {
1234 struct mlx5_outbox_hdr hdr;
1235 u8 rsvd[8];
1236 __be32 psv_idx[4];
1237};
1238
1239struct mlx5_destroy_psv_in {
1240 struct mlx5_inbox_hdr hdr;
1241 __be32 psv_number;
1242 u8 rsvd[4];
1243};
1244
1245struct mlx5_destroy_psv_out {
1246 struct mlx5_outbox_hdr hdr;
1247 u8 rsvd[8];
1248};
1249
1250enum { 833enum {
1251 VPORT_STATE_DOWN = 0x0, 834 VPORT_STATE_DOWN = 0x0,
1252 VPORT_STATE_UP = 0x1, 835 VPORT_STATE_UP = 0x1,
@@ -1381,6 +964,18 @@ enum mlx5_cap_type {
1381#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \ 964#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1382 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap) 965 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1383 966
967#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
968 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
969
970#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
971 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
972
973#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
974 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
975
976#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
977 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
978
1384#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 979#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1385 MLX5_GET(flow_table_eswitch_cap, \ 980 MLX5_GET(flow_table_eswitch_cap, \
1386 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 981 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h
index ccea6fb16482..85c4786427e4 100644
--- a/include/linux/mlx5/driver.h
+++ b/include/linux/mlx5/driver.h
@@ -49,10 +49,6 @@
49#include <linux/mlx5/srq.h> 49#include <linux/mlx5/srq.h>
50 50
51enum { 51enum {
52 MLX5_RQ_BITMASK_VSD = 1 << 1,
53};
54
55enum {
56 MLX5_BOARD_ID_LEN = 64, 52 MLX5_BOARD_ID_LEN = 64,
57 MLX5_MAX_NAME_LEN = 16, 53 MLX5_MAX_NAME_LEN = 16,
58}; 54};
@@ -481,6 +477,7 @@ struct mlx5_fc_stats {
481}; 477};
482 478
483struct mlx5_eswitch; 479struct mlx5_eswitch;
480struct mlx5_lag;
484 481
485struct mlx5_rl_entry { 482struct mlx5_rl_entry {
486 u32 rate; 483 u32 rate;
@@ -554,6 +551,7 @@ struct mlx5_priv {
554 struct mlx5_flow_steering *steering; 551 struct mlx5_flow_steering *steering;
555 struct mlx5_eswitch *eswitch; 552 struct mlx5_eswitch *eswitch;
556 struct mlx5_core_sriov sriov; 553 struct mlx5_core_sriov sriov;
554 struct mlx5_lag *lag;
557 unsigned long pci_dev_data; 555 unsigned long pci_dev_data;
558 struct mlx5_fc_stats fc_stats; 556 struct mlx5_fc_stats fc_stats;
559 struct mlx5_rl_table rl_table; 557 struct mlx5_rl_table rl_table;
@@ -771,14 +769,15 @@ int mlx5_cmd_init(struct mlx5_core_dev *dev);
771void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); 769void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
772void mlx5_cmd_use_events(struct mlx5_core_dev *dev); 770void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
773void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); 771void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
774int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr); 772
775int mlx5_cmd_status_to_err_v2(void *ptr);
776int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
777int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, 773int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
778 int out_size); 774 int out_size);
779int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, 775int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
780 void *out, int out_size, mlx5_cmd_cbk_t callback, 776 void *out, int out_size, mlx5_cmd_cbk_t callback,
781 void *context); 777 void *context);
778void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
779
780int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
782int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); 781int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
783int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); 782int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
784int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); 783int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
@@ -807,15 +806,18 @@ int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
807 u16 lwm, int is_srq); 806 u16 lwm, int is_srq);
808void mlx5_init_mkey_table(struct mlx5_core_dev *dev); 807void mlx5_init_mkey_table(struct mlx5_core_dev *dev);
809void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); 808void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev);
809int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
810 struct mlx5_core_mkey *mkey,
811 u32 *in, int inlen,
812 u32 *out, int outlen,
813 mlx5_cmd_cbk_t callback, void *context);
810int mlx5_core_create_mkey(struct mlx5_core_dev *dev, 814int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
811 struct mlx5_core_mkey *mkey, 815 struct mlx5_core_mkey *mkey,
812 struct mlx5_create_mkey_mbox_in *in, int inlen, 816 u32 *in, int inlen);
813 mlx5_cmd_cbk_t callback, void *context,
814 struct mlx5_create_mkey_mbox_out *out);
815int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, 817int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
816 struct mlx5_core_mkey *mkey); 818 struct mlx5_core_mkey *mkey);
817int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, 819int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
818 struct mlx5_query_mkey_mbox_out *out, int outlen); 820 u32 *out, int outlen);
819int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey, 821int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *_mkey,
820 u32 *mkey); 822 u32 *mkey);
821int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); 823int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
@@ -826,8 +828,6 @@ void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
826void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); 828void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
827int mlx5_pagealloc_start(struct mlx5_core_dev *dev); 829int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
828void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); 830void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
829int mlx5_sriov_init(struct mlx5_core_dev *dev);
830int mlx5_sriov_cleanup(struct mlx5_core_dev *dev);
831void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, 831void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
832 s32 npages); 832 s32 npages);
833int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); 833int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
@@ -865,7 +865,7 @@ int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
865int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 865int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
866void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); 866void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
867int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 867int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
868 struct mlx5_query_eq_mbox_out *out, int outlen); 868 u32 *out, int outlen);
869int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); 869int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
870void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); 870void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
871int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); 871int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
@@ -930,6 +930,8 @@ enum {
930struct mlx5_interface { 930struct mlx5_interface {
931 void * (*add)(struct mlx5_core_dev *dev); 931 void * (*add)(struct mlx5_core_dev *dev);
932 void (*remove)(struct mlx5_core_dev *dev, void *context); 932 void (*remove)(struct mlx5_core_dev *dev, void *context);
933 int (*attach)(struct mlx5_core_dev *dev, void *context);
934 void (*detach)(struct mlx5_core_dev *dev, void *context);
933 void (*event)(struct mlx5_core_dev *dev, void *context, 935 void (*event)(struct mlx5_core_dev *dev, void *context,
934 enum mlx5_dev_event event, unsigned long param); 936 enum mlx5_dev_event event, unsigned long param);
935 void * (*get_dev)(void *context); 937 void * (*get_dev)(void *context);
@@ -942,6 +944,11 @@ int mlx5_register_interface(struct mlx5_interface *intf);
942void mlx5_unregister_interface(struct mlx5_interface *intf); 944void mlx5_unregister_interface(struct mlx5_interface *intf);
943int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); 945int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
944 946
947int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
948int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
949bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
950struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
951
945struct mlx5_profile { 952struct mlx5_profile {
946 u64 mask; 953 u64 mask;
947 u8 log_max_qp; 954 u8 log_max_qp;
diff --git a/include/linux/mlx5/fs.h b/include/linux/mlx5/fs.h
index e036d6030867..93ebc5e21334 100644
--- a/include/linux/mlx5/fs.h
+++ b/include/linux/mlx5/fs.h
@@ -54,6 +54,7 @@ static inline void build_leftovers_ft_param(int *priority,
54 54
55enum mlx5_flow_namespace_type { 55enum mlx5_flow_namespace_type {
56 MLX5_FLOW_NAMESPACE_BYPASS, 56 MLX5_FLOW_NAMESPACE_BYPASS,
57 MLX5_FLOW_NAMESPACE_LAG,
57 MLX5_FLOW_NAMESPACE_OFFLOADS, 58 MLX5_FLOW_NAMESPACE_OFFLOADS,
58 MLX5_FLOW_NAMESPACE_ETHTOOL, 59 MLX5_FLOW_NAMESPACE_ETHTOOL,
59 MLX5_FLOW_NAMESPACE_KERNEL, 60 MLX5_FLOW_NAMESPACE_KERNEL,
@@ -62,6 +63,8 @@ enum mlx5_flow_namespace_type {
62 MLX5_FLOW_NAMESPACE_FDB, 63 MLX5_FLOW_NAMESPACE_FDB,
63 MLX5_FLOW_NAMESPACE_ESW_EGRESS, 64 MLX5_FLOW_NAMESPACE_ESW_EGRESS,
64 MLX5_FLOW_NAMESPACE_ESW_INGRESS, 65 MLX5_FLOW_NAMESPACE_ESW_INGRESS,
66 MLX5_FLOW_NAMESPACE_SNIFFER_RX,
67 MLX5_FLOW_NAMESPACE_SNIFFER_TX,
65}; 68};
66 69
67struct mlx5_flow_table; 70struct mlx5_flow_table;
@@ -106,6 +109,9 @@ mlx5_create_vport_flow_table(struct mlx5_flow_namespace *ns,
106 int prio, 109 int prio,
107 int num_flow_table_entries, 110 int num_flow_table_entries,
108 u32 level, u16 vport); 111 u32 level, u16 vport);
112struct mlx5_flow_table *mlx5_create_lag_demux_flow_table(
113 struct mlx5_flow_namespace *ns,
114 int prio, u32 level);
109int mlx5_destroy_flow_table(struct mlx5_flow_table *ft); 115int mlx5_destroy_flow_table(struct mlx5_flow_table *ft);
110 116
111/* inbox should be set with the following values: 117/* inbox should be set with the following values:
diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index d1f9a581aca8..6045d4d58065 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -152,7 +152,7 @@ enum {
152 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 152 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
153 MLX5_CMD_OP_ACCESS_REG = 0x805, 153 MLX5_CMD_OP_ACCESS_REG = 0x805,
154 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 154 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
155 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807, 155 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
156 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 156 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
157 MLX5_CMD_OP_MAD_IFC = 0x50d, 157 MLX5_CMD_OP_MAD_IFC = 0x50d,
158 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 158 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
@@ -174,6 +174,12 @@ enum {
174 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 174 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
175 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 175 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
176 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 176 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
177 MLX5_CMD_OP_CREATE_LAG = 0x840,
178 MLX5_CMD_OP_MODIFY_LAG = 0x841,
179 MLX5_CMD_OP_QUERY_LAG = 0x842,
180 MLX5_CMD_OP_DESTROY_LAG = 0x843,
181 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
182 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
177 MLX5_CMD_OP_CREATE_TIR = 0x900, 183 MLX5_CMD_OP_CREATE_TIR = 0x900,
178 MLX5_CMD_OP_MODIFY_TIR = 0x901, 184 MLX5_CMD_OP_MODIFY_TIR = 0x901,
179 MLX5_CMD_OP_DESTROY_TIR = 0x902, 185 MLX5_CMD_OP_DESTROY_TIR = 0x902,
@@ -212,6 +218,8 @@ enum {
212 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 218 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
213 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 219 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
214 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 220 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
221 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
222 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
215 MLX5_CMD_OP_MAX 223 MLX5_CMD_OP_MAX
216}; 224};
217 225
@@ -281,7 +289,9 @@ struct mlx5_ifc_flow_table_prop_layout_bits {
281 u8 modify_root[0x1]; 289 u8 modify_root[0x1];
282 u8 identified_miss_table_mode[0x1]; 290 u8 identified_miss_table_mode[0x1];
283 u8 flow_table_modify[0x1]; 291 u8 flow_table_modify[0x1];
284 u8 reserved_at_7[0x19]; 292 u8 encap[0x1];
293 u8 decap[0x1];
294 u8 reserved_at_9[0x17];
285 295
286 u8 reserved_at_20[0x2]; 296 u8 reserved_at_20[0x2];
287 u8 log_max_ft_size[0x6]; 297 u8 log_max_ft_size[0x6];
@@ -473,7 +483,9 @@ struct mlx5_ifc_ads_bits {
473 483
474struct mlx5_ifc_flow_table_nic_cap_bits { 484struct mlx5_ifc_flow_table_nic_cap_bits {
475 u8 nic_rx_multi_path_tirs[0x1]; 485 u8 nic_rx_multi_path_tirs[0x1];
476 u8 reserved_at_1[0x1ff]; 486 u8 nic_rx_multi_path_tirs_fts[0x1];
487 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
488 u8 reserved_at_3[0x1fd];
477 489
478 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 490 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
479 491
@@ -512,7 +524,15 @@ struct mlx5_ifc_e_switch_cap_bits {
512 u8 nic_vport_node_guid_modify[0x1]; 524 u8 nic_vport_node_guid_modify[0x1];
513 u8 nic_vport_port_guid_modify[0x1]; 525 u8 nic_vport_port_guid_modify[0x1];
514 526
515 u8 reserved_at_20[0x7e0]; 527 u8 vxlan_encap_decap[0x1];
528 u8 nvgre_encap_decap[0x1];
529 u8 reserved_at_22[0x9];
530 u8 log_max_encap_headers[0x5];
531 u8 reserved_2b[0x6];
532 u8 max_encap_header_size[0xa];
533
534 u8 reserved_40[0x7c0];
535
516}; 536};
517 537
518struct mlx5_ifc_qos_cap_bits { 538struct mlx5_ifc_qos_cap_bits {
@@ -767,7 +787,9 @@ struct mlx5_ifc_cmd_hca_cap_bits {
767 u8 out_of_seq_cnt[0x1]; 787 u8 out_of_seq_cnt[0x1];
768 u8 vport_counters[0x1]; 788 u8 vport_counters[0x1];
769 u8 retransmission_q_counters[0x1]; 789 u8 retransmission_q_counters[0x1];
770 u8 reserved_at_183[0x3]; 790 u8 reserved_at_183[0x1];
791 u8 modify_rq_counter_set_id[0x1];
792 u8 reserved_at_185[0x1];
771 u8 max_qp_cnt[0xa]; 793 u8 max_qp_cnt[0xa];
772 u8 pkey_table_size[0x10]; 794 u8 pkey_table_size[0x10];
773 795
@@ -870,7 +892,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {
870 u8 pad_tx_eth_packet[0x1]; 892 u8 pad_tx_eth_packet[0x1];
871 u8 reserved_at_263[0x8]; 893 u8 reserved_at_263[0x8];
872 u8 log_bf_reg_size[0x5]; 894 u8 log_bf_reg_size[0x5];
873 u8 reserved_at_270[0x10]; 895
896 u8 reserved_at_270[0xb];
897 u8 lag_master[0x1];
898 u8 num_lag_ports[0x4];
874 899
875 u8 reserved_at_280[0x10]; 900 u8 reserved_at_280[0x10];
876 u8 max_wqe_sz_sq[0x10]; 901 u8 max_wqe_sz_sq[0x10];
@@ -1904,7 +1929,7 @@ enum {
1904 1929
1905struct mlx5_ifc_qpc_bits { 1930struct mlx5_ifc_qpc_bits {
1906 u8 state[0x4]; 1931 u8 state[0x4];
1907 u8 reserved_at_4[0x4]; 1932 u8 lag_tx_port_affinity[0x4];
1908 u8 st[0x8]; 1933 u8 st[0x8];
1909 u8 reserved_at_10[0x3]; 1934 u8 reserved_at_10[0x3];
1910 u8 pm_state[0x2]; 1935 u8 pm_state[0x2];
@@ -1966,7 +1991,10 @@ struct mlx5_ifc_qpc_bits {
1966 u8 reserved_at_3e0[0x8]; 1991 u8 reserved_at_3e0[0x8];
1967 u8 cqn_snd[0x18]; 1992 u8 cqn_snd[0x18];
1968 1993
1969 u8 reserved_at_400[0x40]; 1994 u8 reserved_at_400[0x8];
1995 u8 deth_sqpn[0x18];
1996
1997 u8 reserved_at_420[0x20];
1970 1998
1971 u8 reserved_at_440[0x8]; 1999 u8 reserved_at_440[0x8];
1972 u8 last_acked_psn[0x18]; 2000 u8 last_acked_psn[0x18];
@@ -2064,6 +2092,8 @@ enum {
2064 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 2092 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2065 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 2093 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
2066 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 2094 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
2095 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2096 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2067}; 2097};
2068 2098
2069struct mlx5_ifc_flow_context_bits { 2099struct mlx5_ifc_flow_context_bits {
@@ -2083,7 +2113,9 @@ struct mlx5_ifc_flow_context_bits {
2083 u8 reserved_at_a0[0x8]; 2113 u8 reserved_at_a0[0x8];
2084 u8 flow_counter_list_size[0x18]; 2114 u8 flow_counter_list_size[0x18];
2085 2115
2086 u8 reserved_at_c0[0x140]; 2116 u8 encap_id[0x20];
2117
2118 u8 reserved_at_e0[0x120];
2087 2119
2088 struct mlx5_ifc_fte_match_param_bits match_value; 2120 struct mlx5_ifc_fte_match_param_bits match_value;
2089 2121
@@ -2146,7 +2178,11 @@ struct mlx5_ifc_traffic_counter_bits {
2146}; 2178};
2147 2179
2148struct mlx5_ifc_tisc_bits { 2180struct mlx5_ifc_tisc_bits {
2149 u8 reserved_at_0[0xc]; 2181 u8 strict_lag_tx_port_affinity[0x1];
2182 u8 reserved_at_1[0x3];
2183 u8 lag_tx_port_affinity[0x04];
2184
2185 u8 reserved_at_8[0x4];
2150 u8 prio[0x4]; 2186 u8 prio[0x4];
2151 u8 reserved_at_10[0x10]; 2187 u8 reserved_at_10[0x10];
2152 2188
@@ -2808,7 +2844,7 @@ struct mlx5_ifc_xrqc_bits {
2808 2844
2809 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 2845 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2810 2846
2811 u8 reserved_at_180[0x180]; 2847 u8 reserved_at_180[0x200];
2812 2848
2813 struct mlx5_ifc_wq_bits wq; 2849 struct mlx5_ifc_wq_bits wq;
2814}; 2850};
@@ -3489,7 +3525,7 @@ struct mlx5_ifc_query_special_contexts_out_bits {
3489 3525
3490 u8 syndrome[0x20]; 3526 u8 syndrome[0x20];
3491 3527
3492 u8 reserved_at_40[0x20]; 3528 u8 dump_fill_mkey[0x20];
3493 3529
3494 u8 resd_lkey[0x20]; 3530 u8 resd_lkey[0x20];
3495}; 3531};
@@ -4213,6 +4249,85 @@ struct mlx5_ifc_query_eq_in_bits {
4213 u8 reserved_at_60[0x20]; 4249 u8 reserved_at_60[0x20];
4214}; 4250};
4215 4251
4252struct mlx5_ifc_encap_header_in_bits {
4253 u8 reserved_at_0[0x5];
4254 u8 header_type[0x3];
4255 u8 reserved_at_8[0xe];
4256 u8 encap_header_size[0xa];
4257
4258 u8 reserved_at_20[0x10];
4259 u8 encap_header[2][0x8];
4260
4261 u8 more_encap_header[0][0x8];
4262};
4263
4264struct mlx5_ifc_query_encap_header_out_bits {
4265 u8 status[0x8];
4266 u8 reserved_at_8[0x18];
4267
4268 u8 syndrome[0x20];
4269
4270 u8 reserved_at_40[0xa0];
4271
4272 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4273};
4274
4275struct mlx5_ifc_query_encap_header_in_bits {
4276 u8 opcode[0x10];
4277 u8 reserved_at_10[0x10];
4278
4279 u8 reserved_at_20[0x10];
4280 u8 op_mod[0x10];
4281
4282 u8 encap_id[0x20];
4283
4284 u8 reserved_at_60[0xa0];
4285};
4286
4287struct mlx5_ifc_alloc_encap_header_out_bits {
4288 u8 status[0x8];
4289 u8 reserved_at_8[0x18];
4290
4291 u8 syndrome[0x20];
4292
4293 u8 encap_id[0x20];
4294
4295 u8 reserved_at_60[0x20];
4296};
4297
4298struct mlx5_ifc_alloc_encap_header_in_bits {
4299 u8 opcode[0x10];
4300 u8 reserved_at_10[0x10];
4301
4302 u8 reserved_at_20[0x10];
4303 u8 op_mod[0x10];
4304
4305 u8 reserved_at_40[0xa0];
4306
4307 struct mlx5_ifc_encap_header_in_bits encap_header;
4308};
4309
4310struct mlx5_ifc_dealloc_encap_header_out_bits {
4311 u8 status[0x8];
4312 u8 reserved_at_8[0x18];
4313
4314 u8 syndrome[0x20];
4315
4316 u8 reserved_at_40[0x40];
4317};
4318
4319struct mlx5_ifc_dealloc_encap_header_in_bits {
4320 u8 opcode[0x10];
4321 u8 reserved_at_10[0x10];
4322
4323 u8 reserved_20[0x10];
4324 u8 op_mod[0x10];
4325
4326 u8 encap_id[0x20];
4327
4328 u8 reserved_60[0x20];
4329};
4330
4216struct mlx5_ifc_query_dct_out_bits { 4331struct mlx5_ifc_query_dct_out_bits {
4217 u8 status[0x8]; 4332 u8 status[0x8];
4218 u8 reserved_at_8[0x18]; 4333 u8 reserved_at_8[0x18];
@@ -4517,7 +4632,9 @@ struct mlx5_ifc_modify_tis_out_bits {
4517struct mlx5_ifc_modify_tis_bitmask_bits { 4632struct mlx5_ifc_modify_tis_bitmask_bits {
4518 u8 reserved_at_0[0x20]; 4633 u8 reserved_at_0[0x20];
4519 4634
4520 u8 reserved_at_20[0x1f]; 4635 u8 reserved_at_20[0x1d];
4636 u8 lag_tx_port_affinity[0x1];
4637 u8 strict_lag_tx_port_affinity[0x1];
4521 u8 prio[0x1]; 4638 u8 prio[0x1];
4522}; 4639};
4523 4640
@@ -4652,6 +4769,11 @@ struct mlx5_ifc_modify_rq_out_bits {
4652 u8 reserved_at_40[0x40]; 4769 u8 reserved_at_40[0x40];
4653}; 4770};
4654 4771
4772enum {
4773 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
4774 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
4775};
4776
4655struct mlx5_ifc_modify_rq_in_bits { 4777struct mlx5_ifc_modify_rq_in_bits {
4656 u8 opcode[0x10]; 4778 u8 opcode[0x10];
4657 u8 reserved_at_10[0x10]; 4779 u8 reserved_at_10[0x10];
@@ -4721,7 +4843,7 @@ struct mlx5_ifc_modify_nic_vport_field_select_bits {
4721 u8 reserved_at_0[0x16]; 4843 u8 reserved_at_0[0x16];
4722 u8 node_guid[0x1]; 4844 u8 node_guid[0x1];
4723 u8 port_guid[0x1]; 4845 u8 port_guid[0x1];
4724 u8 reserved_at_18[0x1]; 4846 u8 min_inline[0x1];
4725 u8 mtu[0x1]; 4847 u8 mtu[0x1];
4726 u8 change_event[0x1]; 4848 u8 change_event[0x1];
4727 u8 promisc[0x1]; 4849 u8 promisc[0x1];
@@ -6099,7 +6221,9 @@ struct mlx5_ifc_create_flow_table_in_bits {
6099 6221
6100 u8 reserved_at_a0[0x20]; 6222 u8 reserved_at_a0[0x20];
6101 6223
6102 u8 reserved_at_c0[0x4]; 6224 u8 encap_en[0x1];
6225 u8 decap_en[0x1];
6226 u8 reserved_at_c2[0x2];
6103 u8 table_miss_mode[0x4]; 6227 u8 table_miss_mode[0x4];
6104 u8 level[0x8]; 6228 u8 level[0x8];
6105 u8 reserved_at_d0[0x8]; 6229 u8 reserved_at_d0[0x8];
@@ -6108,7 +6232,10 @@ struct mlx5_ifc_create_flow_table_in_bits {
6108 u8 reserved_at_e0[0x8]; 6232 u8 reserved_at_e0[0x8];
6109 u8 table_miss_id[0x18]; 6233 u8 table_miss_id[0x18];
6110 6234
6111 u8 reserved_at_100[0x100]; 6235 u8 reserved_at_100[0x8];
6236 u8 lag_master_next_table_id[0x18];
6237
6238 u8 reserved_at_120[0x80];
6112}; 6239};
6113 6240
6114struct mlx5_ifc_create_flow_group_out_bits { 6241struct mlx5_ifc_create_flow_group_out_bits {
@@ -7563,7 +7690,8 @@ struct mlx5_ifc_set_flow_table_root_in_bits {
7563}; 7690};
7564 7691
7565enum { 7692enum {
7566 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1, 7693 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
7694 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
7567}; 7695};
7568 7696
7569struct mlx5_ifc_modify_flow_table_out_bits { 7697struct mlx5_ifc_modify_flow_table_out_bits {
@@ -7602,7 +7730,10 @@ struct mlx5_ifc_modify_flow_table_in_bits {
7602 u8 reserved_at_e0[0x8]; 7730 u8 reserved_at_e0[0x8];
7603 u8 table_miss_id[0x18]; 7731 u8 table_miss_id[0x18];
7604 7732
7605 u8 reserved_at_100[0x100]; 7733 u8 reserved_at_100[0x8];
7734 u8 lag_master_next_table_id[0x18];
7735
7736 u8 reserved_at_120[0x80];
7606}; 7737};
7607 7738
7608struct mlx5_ifc_ets_tcn_config_reg_bits { 7739struct mlx5_ifc_ets_tcn_config_reg_bits {
@@ -7710,4 +7841,134 @@ struct mlx5_ifc_dcbx_param_bits {
7710 u8 error[0x8]; 7841 u8 error[0x8];
7711 u8 reserved_at_a0[0x160]; 7842 u8 reserved_at_a0[0x160];
7712}; 7843};
7844
7845struct mlx5_ifc_lagc_bits {
7846 u8 reserved_at_0[0x1d];
7847 u8 lag_state[0x3];
7848
7849 u8 reserved_at_20[0x14];
7850 u8 tx_remap_affinity_2[0x4];
7851 u8 reserved_at_38[0x4];
7852 u8 tx_remap_affinity_1[0x4];
7853};
7854
7855struct mlx5_ifc_create_lag_out_bits {
7856 u8 status[0x8];
7857 u8 reserved_at_8[0x18];
7858
7859 u8 syndrome[0x20];
7860
7861 u8 reserved_at_40[0x40];
7862};
7863
7864struct mlx5_ifc_create_lag_in_bits {
7865 u8 opcode[0x10];
7866 u8 reserved_at_10[0x10];
7867
7868 u8 reserved_at_20[0x10];
7869 u8 op_mod[0x10];
7870
7871 struct mlx5_ifc_lagc_bits ctx;
7872};
7873
7874struct mlx5_ifc_modify_lag_out_bits {
7875 u8 status[0x8];
7876 u8 reserved_at_8[0x18];
7877
7878 u8 syndrome[0x20];
7879
7880 u8 reserved_at_40[0x40];
7881};
7882
7883struct mlx5_ifc_modify_lag_in_bits {
7884 u8 opcode[0x10];
7885 u8 reserved_at_10[0x10];
7886
7887 u8 reserved_at_20[0x10];
7888 u8 op_mod[0x10];
7889
7890 u8 reserved_at_40[0x20];
7891 u8 field_select[0x20];
7892
7893 struct mlx5_ifc_lagc_bits ctx;
7894};
7895
7896struct mlx5_ifc_query_lag_out_bits {
7897 u8 status[0x8];
7898 u8 reserved_at_8[0x18];
7899
7900 u8 syndrome[0x20];
7901
7902 u8 reserved_at_40[0x40];
7903
7904 struct mlx5_ifc_lagc_bits ctx;
7905};
7906
7907struct mlx5_ifc_query_lag_in_bits {
7908 u8 opcode[0x10];
7909 u8 reserved_at_10[0x10];
7910
7911 u8 reserved_at_20[0x10];
7912 u8 op_mod[0x10];
7913
7914 u8 reserved_at_40[0x40];
7915};
7916
7917struct mlx5_ifc_destroy_lag_out_bits {
7918 u8 status[0x8];
7919 u8 reserved_at_8[0x18];
7920
7921 u8 syndrome[0x20];
7922
7923 u8 reserved_at_40[0x40];
7924};
7925
7926struct mlx5_ifc_destroy_lag_in_bits {
7927 u8 opcode[0x10];
7928 u8 reserved_at_10[0x10];
7929
7930 u8 reserved_at_20[0x10];
7931 u8 op_mod[0x10];
7932
7933 u8 reserved_at_40[0x40];
7934};
7935
7936struct mlx5_ifc_create_vport_lag_out_bits {
7937 u8 status[0x8];
7938 u8 reserved_at_8[0x18];
7939
7940 u8 syndrome[0x20];
7941
7942 u8 reserved_at_40[0x40];
7943};
7944
7945struct mlx5_ifc_create_vport_lag_in_bits {
7946 u8 opcode[0x10];
7947 u8 reserved_at_10[0x10];
7948
7949 u8 reserved_at_20[0x10];
7950 u8 op_mod[0x10];
7951
7952 u8 reserved_at_40[0x40];
7953};
7954
7955struct mlx5_ifc_destroy_vport_lag_out_bits {
7956 u8 status[0x8];
7957 u8 reserved_at_8[0x18];
7958
7959 u8 syndrome[0x20];
7960
7961 u8 reserved_at_40[0x40];
7962};
7963
7964struct mlx5_ifc_destroy_vport_lag_in_bits {
7965 u8 opcode[0x10];
7966 u8 reserved_at_10[0x10];
7967
7968 u8 reserved_at_20[0x10];
7969 u8 op_mod[0x10];
7970
7971 u8 reserved_at_40[0x40];
7972};
7973
7713#endif /* MLX5_IFC_H */ 7974#endif /* MLX5_IFC_H */
diff --git a/include/linux/mlx5/port.h b/include/linux/mlx5/port.h
index e3012cc64b8a..b3065acd20b4 100644
--- a/include/linux/mlx5/port.h
+++ b/include/linux/mlx5/port.h
@@ -61,6 +61,39 @@ enum mlx5_an_status {
61#define MLX5_I2C_ADDR_HIGH 0x51 61#define MLX5_I2C_ADDR_HIGH 0x51
62#define MLX5_EEPROM_PAGE_LENGTH 256 62#define MLX5_EEPROM_PAGE_LENGTH 256
63 63
64enum mlx5e_link_mode {
65 MLX5E_1000BASE_CX_SGMII = 0,
66 MLX5E_1000BASE_KX = 1,
67 MLX5E_10GBASE_CX4 = 2,
68 MLX5E_10GBASE_KX4 = 3,
69 MLX5E_10GBASE_KR = 4,
70 MLX5E_20GBASE_KR2 = 5,
71 MLX5E_40GBASE_CR4 = 6,
72 MLX5E_40GBASE_KR4 = 7,
73 MLX5E_56GBASE_R4 = 8,
74 MLX5E_10GBASE_CR = 12,
75 MLX5E_10GBASE_SR = 13,
76 MLX5E_10GBASE_ER = 14,
77 MLX5E_40GBASE_SR4 = 15,
78 MLX5E_40GBASE_LR4 = 16,
79 MLX5E_50GBASE_SR2 = 18,
80 MLX5E_100GBASE_CR4 = 20,
81 MLX5E_100GBASE_SR4 = 21,
82 MLX5E_100GBASE_KR4 = 22,
83 MLX5E_100GBASE_LR4 = 23,
84 MLX5E_100BASE_TX = 24,
85 MLX5E_1000BASE_T = 25,
86 MLX5E_10GBASE_T = 26,
87 MLX5E_25GBASE_CR = 27,
88 MLX5E_25GBASE_KR = 28,
89 MLX5E_25GBASE_SR = 29,
90 MLX5E_50GBASE_CR2 = 30,
91 MLX5E_50GBASE_KR2 = 31,
92 MLX5E_LINK_MODES_NUMBER,
93};
94
95#define MLX5E_PROT_MASK(link_mode) (1 << link_mode)
96
64int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); 97int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
65int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, 98int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
66 int ptys_size, int proto_mask, u8 local_port); 99 int ptys_size, int proto_mask, u8 local_port);
@@ -70,9 +103,10 @@ int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
70 u32 *proto_admin, int proto_mask); 103 u32 *proto_admin, int proto_mask);
71int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev, 104int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev,
72 u8 *link_width_oper, u8 local_port); 105 u8 *link_width_oper, u8 local_port);
73int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev, 106int mlx5_query_port_ib_proto_oper(struct mlx5_core_dev *dev,
74 u8 *proto_oper, int proto_mask, 107 u8 *proto_oper, u8 local_port);
75 u8 local_port); 108int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev *dev,
109 u32 *proto_oper, u8 local_port);
76int mlx5_set_port_ptys(struct mlx5_core_dev *dev, bool an_disable, 110int mlx5_set_port_ptys(struct mlx5_core_dev *dev, bool an_disable,
77 u32 proto_admin, int proto_mask); 111 u32 proto_admin, int proto_mask);
78void mlx5_toggle_port_link(struct mlx5_core_dev *dev); 112void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
diff --git a/include/linux/mlx5/qp.h b/include/linux/mlx5/qp.h
index 7879bf411891..0aacb2a7480d 100644
--- a/include/linux/mlx5/qp.h
+++ b/include/linux/mlx5/qp.h
@@ -123,12 +123,13 @@ enum {
123}; 123};
124 124
125enum { 125enum {
126 MLX5_NON_ZERO_RQ = 0 << 24, 126 MLX5_NON_ZERO_RQ = 0x0,
127 MLX5_SRQ_RQ = 1 << 24, 127 MLX5_SRQ_RQ = 0x1,
128 MLX5_CRQ_RQ = 2 << 24, 128 MLX5_CRQ_RQ = 0x2,
129 MLX5_ZERO_LEN_RQ = 3 << 24 129 MLX5_ZERO_LEN_RQ = 0x3
130}; 130};
131 131
132/* TODO REM */
132enum { 133enum {
133 /* params1 */ 134 /* params1 */
134 MLX5_QP_BIT_SRE = 1 << 15, 135 MLX5_QP_BIT_SRE = 1 << 15,
@@ -178,12 +179,6 @@ enum {
178}; 179};
179 180
180enum { 181enum {
181 MLX5_QP_LAT_SENSITIVE = 1 << 28,
182 MLX5_QP_BLOCK_MCAST = 1 << 30,
183 MLX5_QP_ENABLE_SIG = 1 << 31,
184};
185
186enum {
187 MLX5_RCV_DBR = 0, 182 MLX5_RCV_DBR = 0,
188 MLX5_SND_DBR = 1, 183 MLX5_SND_DBR = 1,
189}; 184};
@@ -484,6 +479,7 @@ struct mlx5_qp_path {
484 u8 rmac[6]; 479 u8 rmac[6];
485}; 480};
486 481
482/* FIXME: use mlx5_ifc.h qpc */
487struct mlx5_qp_context { 483struct mlx5_qp_context {
488 __be32 flags; 484 __be32 flags;
489 __be32 flags_pd; 485 __be32 flags_pd;
@@ -525,99 +521,6 @@ struct mlx5_qp_context {
525 u8 rsvd1[24]; 521 u8 rsvd1[24];
526}; 522};
527 523
528struct mlx5_create_qp_mbox_in {
529 struct mlx5_inbox_hdr hdr;
530 __be32 input_qpn;
531 u8 rsvd0[4];
532 __be32 opt_param_mask;
533 u8 rsvd1[4];
534 struct mlx5_qp_context ctx;
535 u8 rsvd3[16];
536 __be64 pas[0];
537};
538
539struct mlx5_create_qp_mbox_out {
540 struct mlx5_outbox_hdr hdr;
541 __be32 qpn;
542 u8 rsvd0[4];
543};
544
545struct mlx5_destroy_qp_mbox_in {
546 struct mlx5_inbox_hdr hdr;
547 __be32 qpn;
548 u8 rsvd0[4];
549};
550
551struct mlx5_destroy_qp_mbox_out {
552 struct mlx5_outbox_hdr hdr;
553 u8 rsvd0[8];
554};
555
556struct mlx5_modify_qp_mbox_in {
557 struct mlx5_inbox_hdr hdr;
558 __be32 qpn;
559 u8 rsvd0[4];
560 __be32 optparam;
561 u8 rsvd1[4];
562 struct mlx5_qp_context ctx;
563 u8 rsvd2[16];
564};
565
566struct mlx5_modify_qp_mbox_out {
567 struct mlx5_outbox_hdr hdr;
568 u8 rsvd0[8];
569};
570
571struct mlx5_query_qp_mbox_in {
572 struct mlx5_inbox_hdr hdr;
573 __be32 qpn;
574 u8 rsvd[4];
575};
576
577struct mlx5_query_qp_mbox_out {
578 struct mlx5_outbox_hdr hdr;
579 u8 rsvd1[8];
580 __be32 optparam;
581 u8 rsvd0[4];
582 struct mlx5_qp_context ctx;
583 u8 rsvd2[16];
584 __be64 pas[0];
585};
586
587struct mlx5_conf_sqp_mbox_in {
588 struct mlx5_inbox_hdr hdr;
589 __be32 qpn;
590 u8 rsvd[3];
591 u8 type;
592};
593
594struct mlx5_conf_sqp_mbox_out {
595 struct mlx5_outbox_hdr hdr;
596 u8 rsvd[8];
597};
598
599struct mlx5_alloc_xrcd_mbox_in {
600 struct mlx5_inbox_hdr hdr;
601 u8 rsvd[8];
602};
603
604struct mlx5_alloc_xrcd_mbox_out {
605 struct mlx5_outbox_hdr hdr;
606 __be32 xrcdn;
607 u8 rsvd[4];
608};
609
610struct mlx5_dealloc_xrcd_mbox_in {
611 struct mlx5_inbox_hdr hdr;
612 __be32 xrcdn;
613 u8 rsvd[4];
614};
615
616struct mlx5_dealloc_xrcd_mbox_out {
617 struct mlx5_outbox_hdr hdr;
618 u8 rsvd[8];
619};
620
621static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn) 524static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
622{ 525{
623 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn); 526 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
@@ -628,28 +531,17 @@ static inline struct mlx5_core_mkey *__mlx5_mr_lookup(struct mlx5_core_dev *dev,
628 return radix_tree_lookup(&dev->priv.mkey_table.tree, key); 531 return radix_tree_lookup(&dev->priv.mkey_table.tree, key);
629} 532}
630 533
631struct mlx5_page_fault_resume_mbox_in {
632 struct mlx5_inbox_hdr hdr;
633 __be32 flags_qpn;
634 u8 reserved[4];
635};
636
637struct mlx5_page_fault_resume_mbox_out {
638 struct mlx5_outbox_hdr hdr;
639 u8 rsvd[8];
640};
641
642int mlx5_core_create_qp(struct mlx5_core_dev *dev, 534int mlx5_core_create_qp(struct mlx5_core_dev *dev,
643 struct mlx5_core_qp *qp, 535 struct mlx5_core_qp *qp,
644 struct mlx5_create_qp_mbox_in *in, 536 u32 *in,
645 int inlen); 537 int inlen);
646int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 operation, 538int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 opcode,
647 struct mlx5_modify_qp_mbox_in *in, int sqd_event, 539 u32 opt_param_mask, void *qpc,
648 struct mlx5_core_qp *qp); 540 struct mlx5_core_qp *qp);
649int mlx5_core_destroy_qp(struct mlx5_core_dev *dev, 541int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
650 struct mlx5_core_qp *qp); 542 struct mlx5_core_qp *qp);
651int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp, 543int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
652 struct mlx5_query_qp_mbox_out *out, int outlen); 544 u32 *out, int outlen);
653 545
654int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn); 546int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
655int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn); 547int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
diff --git a/include/linux/mlx5/vport.h b/include/linux/mlx5/vport.h
index e087b7d047ac..451b0bde9083 100644
--- a/include/linux/mlx5/vport.h
+++ b/include/linux/mlx5/vport.h
@@ -45,6 +45,8 @@ int mlx5_query_nic_vport_mac_address(struct mlx5_core_dev *mdev,
45 u16 vport, u8 *addr); 45 u16 vport, u8 *addr);
46void mlx5_query_nic_vport_min_inline(struct mlx5_core_dev *mdev, 46void mlx5_query_nic_vport_min_inline(struct mlx5_core_dev *mdev,
47 u8 *min_inline); 47 u8 *min_inline);
48int mlx5_modify_nic_vport_min_inline(struct mlx5_core_dev *mdev,
49 u16 vport, u8 min_inline);
48int mlx5_modify_nic_vport_mac_address(struct mlx5_core_dev *dev, 50int mlx5_modify_nic_vport_mac_address(struct mlx5_core_dev *dev,
49 u16 vport, u8 *addr); 51 u16 vport, u8 *addr);
50int mlx5_query_nic_vport_mtu(struct mlx5_core_dev *mdev, u16 *mtu); 52int mlx5_query_nic_vport_mtu(struct mlx5_core_dev *mdev, u16 *mtu);
generated by cgit v1.2.2 (git 2.25.0) at 2026-05-12 22:51:30 -0400