Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux

Pull drm updates from Dave Airlie:
 "I Was Almost Tempted To Capitalise Every Word, but then I decided I
  couldn't read it myself!

  I've also got one pull request for the sti driver outstanding.  It
  relied on a commit in Greg's tree and I didn't find out in time, that
  commit is in your tree now so I might send that along once this is
  merged.

  I also had the accidental misfortune to have access to a Skylake on my
  desk for a few days, and I've had to encourage Intel to try harder,
  which seems to be happening now.

  Here is the main drm-next pull request for 4.4.

  Highlights:

  New driver:
        vc4 driver for the Rasberry Pi VPU.
        (From Eric Anholt at Broadcom.)

  Core:
        Atomic fbdev support
        Atomic helpers for runtime pm
        dp/aux i2c STATUS_UPDATE handling
        struct_mutex usage cleanups.
        Generic of probing support.

  Documentation:
        Kerneldoc for VGA switcheroo code.
        Rename to gpu instead of drm to reflect scope.

  i915:
        Skylake GuC firmware fixes
        HPD A support
        VBT backlight fallbacks
        Fastboot by default for some systems
        FBC work
        BXT/SKL workarounds
        Skylake deeper sleep state fixes

  amdgpu:
        Enable GPU scheduler by default
        New atombios opcodes
        GPUVM debugging options
        Stoney support.
        Fencing cleanups.

  radeon:
        More efficient CS checking

  nouveau:
        gk20a instance memory handling improvements.
        Improved PGOB detection and GK107 support
        Kepler GDDR5 PLL statbility improvement
        G8x/GT2xx reclock improvements
        new userspace API compatiblity fixes.

  virtio-gpu:
        Add 3D support - qemu 2.5 has it merged for it's gtk backend.

  msm:
        Initial msm88896 (snapdragon 8200)

  exynos:
        HDMI cleanups
        Enable mixer driver byt default
        Add DECON-TV support

  vmwgfx:
        Move to using memremap + fixes.

  rcar-du:
        Add support for R8A7793/4 DU

  armada:
        Remove support for non-component mode
        Improved plane handling
        Power savings while in DPMS off.

  tda998x:
        Remove unused slave encoder support
        Use more HDMI helpers
        Fix EDID read handling

  dwhdmi:
        Interlace video mode support for ipu-v3/dw_hdmi
        Hotplug state fixes
        Audio driver integration

  imx:
        More color formats support.

  tegra:
        Minor fixes/improvements"

[ Merge fixup: remove unused variable 'dev' that had all uses removed in
  commit 4e270f088011: "drm/gem: Drop struct_mutex requirement from
  drm_gem_mmap_obj" ]

* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (764 commits)
  drm/vmwgfx: Relax irq locking somewhat
  drm/vmwgfx: Properly flush cursor updates and page-flips
  drm/i915/skl: disable display side power well support for now
  drm/i915: Extend DSL readout fix to BDW and SKL.
  drm/i915: Do graphics device reset under forcewake
  drm/i915: Skip fence installation for objects with rotated views (v4)
  vga_switcheroo: Drop client power state VGA_SWITCHEROO_INIT
  drm/amdgpu: group together common fence implementation
  drm/amdgpu: remove AMDGPU_FENCE_OWNER_MOVE
  drm/amdgpu: remove now unused fence functions
  drm/amdgpu: fix fence fallback check
  drm/amdgpu: fix stoping the scheduler timeout
  drm/amdgpu: cleanup on error in amdgpu_cs_ioctl()
  drm/i915: Fix locking around GuC firmware load
  drm/amdgpu: update Fiji's Golden setting
  drm/amdgpu: update Fiji's rev id
  drm/amdgpu: extract common code in vi_common_early_init
  drm/amd/scheduler: don't oops on failure to load
  drm/amdgpu: don't oops on failure to load (v2)
  drm/amdgpu: don't VT switch on suspend
  ...

47 files changed, 1871 insertions, 1617 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 0d13e6368b96..615ce6d464fb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -79,6 +79,8 @@ extern int amdgpu_bapm;
 extern int amdgpu_deep_color;
 extern int amdgpu_vm_size;
 extern int amdgpu_vm_block_size;
+extern int amdgpu_vm_fault_stop;
+extern int amdgpu_vm_debug;
 extern int amdgpu_enable_scheduler;
 extern int amdgpu_sched_jobs;
 extern int amdgpu_sched_hw_submission;
@@ -343,7 +345,6 @@ struct amdgpu_ring_funcs {
         /* testing functions */
         int (*test_ring)(struct amdgpu_ring *ring);
         int (*test_ib)(struct amdgpu_ring *ring);
-        bool (*is_lockup)(struct amdgpu_ring *ring);
         /* insert NOP packets */
         void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
 };
@@ -404,7 +405,6 @@ struct amdgpu_fence_driver {
 /* some special values for the owner field */
 #define AMDGPU_FENCE_OWNER_UNDEFINED    ((void*)0ul)
 #define AMDGPU_FENCE_OWNER_VM           ((void*)1ul)
-#define AMDGPU_FENCE_OWNER_MOVE         ((void*)2ul)
 
 #define AMDGPU_FENCE_FLAG_64BIT         (1 << 0)
 #define AMDGPU_FENCE_FLAG_INT           (1 << 1)
@@ -446,58 +446,11 @@ int amdgpu_fence_wait_next(struct amdgpu_ring *ring);
 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
 
-signed long amdgpu_fence_wait_any(struct amdgpu_device *adev,
-                                  struct fence **array,
-                                  uint32_t count,
-                                  bool intr,
-                                  signed long t);
-struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence);
-void amdgpu_fence_unref(struct amdgpu_fence **fence);
-
 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence,
                             struct amdgpu_ring *ring);
 void amdgpu_fence_note_sync(struct amdgpu_fence *fence,
                             struct amdgpu_ring *ring);
 
-static inline struct amdgpu_fence *amdgpu_fence_later(struct amdgpu_fence *a,
-                                                      struct amdgpu_fence *b)
-{
-        if (!a) {
-                return b;
-        }
-
-        if (!b) {
-                return a;
-        }
-
-        BUG_ON(a->ring != b->ring);
-
-        if (a->seq > b->seq) {
-                return a;
-        } else {
-                return b;
-        }
-}
-
-static inline bool amdgpu_fence_is_earlier(struct amdgpu_fence *a,
-                                           struct amdgpu_fence *b)
-{
-        if (!a) {
-                return false;
-        }
-
-        if (!b) {
-                return true;
-        }
-
-        BUG_ON(a->ring != b->ring);
-
-        return a->seq < b->seq;
-}
-
-int amdgpu_user_fence_emit(struct amdgpu_ring *ring, struct amdgpu_user_fence *user,
-                           void *owner, struct amdgpu_fence **fence);
-
 /*
  * TTM.
  */
@@ -708,7 +661,7 @@ void amdgpu_semaphore_free(struct amdgpu_device *adev,
  */
 struct amdgpu_sync {
         struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS];
-        struct amdgpu_fence     *sync_to[AMDGPU_MAX_RINGS];
+        struct fence            *sync_to[AMDGPU_MAX_RINGS];
         DECLARE_HASHTABLE(fences, 4);
         struct fence            *last_vm_update;
 };
@@ -905,8 +858,6 @@ struct amdgpu_ring {
         unsigned                ring_size;
         unsigned                ring_free_dw;
         int                     count_dw;
-        atomic_t                last_rptr;
-        atomic64_t              last_activity;
         uint64_t                gpu_addr;
         uint32_t                align_mask;
         uint32_t                ptr_mask;
@@ -960,6 +911,11 @@ struct amdgpu_ring {
 #define AMDGPU_PTE_FRAG_64KB    (4 << 7)
 #define AMDGPU_LOG2_PAGES_PER_FRAG 4
 
+/* How to programm VM fault handling */
+#define AMDGPU_VM_FAULT_STOP_NEVER      0
+#define AMDGPU_VM_FAULT_STOP_FIRST      1
+#define AMDGPU_VM_FAULT_STOP_ALWAYS     2
+
 struct amdgpu_vm_pt {
         struct amdgpu_bo                *bo;
         uint64_t                        addr;
@@ -971,7 +927,7 @@ struct amdgpu_vm_id {
         /* last flushed PD/PT update */
         struct fence            *flushed_updates;
         /* last use of vmid */
-        struct amdgpu_fence     *last_id_use;
+        struct fence            *last_id_use;
 };
 
 struct amdgpu_vm {
@@ -1004,7 +960,7 @@ struct amdgpu_vm {
 };
 
 struct amdgpu_vm_manager {
-        struct amdgpu_fence             *active[AMDGPU_NUM_VM];
+        struct fence                    *active[AMDGPU_NUM_VM];
         uint32_t                        max_pfn;
         /* number of VMIDs */
         unsigned                        nvm;
@@ -1223,8 +1179,6 @@ void amdgpu_ring_commit(struct amdgpu_ring *ring);
 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring);
 void amdgpu_ring_undo(struct amdgpu_ring *ring);
 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring);
-void amdgpu_ring_lockup_update(struct amdgpu_ring *ring);
-bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring);
 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring,
                             uint32_t **data);
 int amdgpu_ring_restore(struct amdgpu_ring *ring,
@@ -1234,6 +1188,7 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
                      struct amdgpu_irq_src *irq_src, unsigned irq_type,
                      enum amdgpu_ring_type ring_type);
 void amdgpu_ring_fini(struct amdgpu_ring *ring);
+struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f);
 
 /*
  * CS.
@@ -1709,7 +1664,7 @@ struct amdgpu_vce {
 /*
  * SDMA
  */
-struct amdgpu_sdma {
+struct amdgpu_sdma_instance {
         /* SDMA firmware */
         const struct firmware   *fw;
         uint32_t                fw_version;
@@ -1719,6 +1674,13 @@ struct amdgpu_sdma {
         bool                    burst_nop;
 };
 
+struct amdgpu_sdma {
+        struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
+        struct amdgpu_irq_src   trap_irq;
+        struct amdgpu_irq_src   illegal_inst_irq;
+        int                     num_instances;
+};
+
 /*
  * Firmware
  */
@@ -1751,11 +1713,11 @@ void amdgpu_test_syncing(struct amdgpu_device *adev);
 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
 #else
-static int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
+static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
 {
         return -ENODEV;
 }
-static void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
+static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
 #endif
 
 /*
@@ -1947,7 +1909,6 @@ struct amdgpu_device {
         struct device                   *dev;
         struct drm_device               *ddev;
         struct pci_dev                  *pdev;
-        struct rw_semaphore             exclusive_lock;
 
         /* ASIC */
         enum amd_asic_type              asic_type;
@@ -1961,7 +1922,6 @@ struct amdgpu_device {
         bool                            suspend;
         bool                            need_dma32;
         bool                            accel_working;
-        bool                            needs_reset;
         struct work_struct              reset_work;
         struct notifier_block           acpi_nb;
         struct amdgpu_i2c_chan          *i2c_bus[AMDGPU_MAX_I2C_BUS];
@@ -2065,9 +2025,7 @@ struct amdgpu_device {
         struct amdgpu_gfx               gfx;
 
         /* sdma */
-        struct amdgpu_sdma              sdma[AMDGPU_MAX_SDMA_INSTANCES];
-        struct amdgpu_irq_src           sdma_trap_irq;
-        struct amdgpu_irq_src           sdma_illegal_inst_irq;
+        struct amdgpu_sdma              sdma;
 
         /* uvd */
         bool                            has_uvd;
@@ -2204,17 +2162,18 @@ static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
         ring->ring_free_dw--;
 }
 
-static inline struct amdgpu_sdma * amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
+static inline struct amdgpu_sdma_instance *
+amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
         int i;
 
-        for (i = 0; i < AMDGPU_MAX_SDMA_INSTANCES; i++)
-                if (&adev->sdma[i].ring == ring)
+        for (i = 0; i < adev->sdma.num_instances; i++)
+                if (&adev->sdma.instance[i].ring == ring)
                         break;
 
         if (i < AMDGPU_MAX_SDMA_INSTANCES)
-                return &adev->sdma[i];
+                return &adev->sdma.instance[i];
         else
                 return NULL;
 }
@@ -2241,7 +2200,6 @@ static inline struct amdgpu_sdma * amdgpu_get_sdma_instance(struct amdgpu_ring *
 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r))
-#define amdgpu_ring_is_lockup(r) (r)->funcs->is_lockup((r))
 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
@@ -2350,10 +2308,10 @@ void amdgpu_driver_preclose_kms(struct drm_device *dev,
                                 struct drm_file *file_priv);
 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
-u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc);
-int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc);
-void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc);
-int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
+u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
+int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
+void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
+int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
                                     int *max_error,
                                     struct timeval *vblank_time,
                                     unsigned flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
index aef4a7aac0f7..a142d5ae148d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c
@@ -25,7 +25,6 @@
 #include <linux/acpi.h>
 #include <linux/slab.h>
 #include <linux/power_supply.h>
-#include <linux/vga_switcheroo.h>
 #include <acpi/video.h>
 #include <drm/drmP.h>
 #include <drm/drm_crtc_helper.h>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
index dd2037bc0b4a..0e1376317683 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
@@ -649,12 +649,12 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
 
         case KGD_ENGINE_SDMA1:
                 hdr = (const union amdgpu_firmware_header *)
-                                                        adev->sdma[0].fw->data;
+                                                        adev->sdma.instance[0].fw->data;
                 break;
 
         case KGD_ENGINE_SDMA2:
                 hdr = (const union amdgpu_firmware_header *)
-                                                        adev->sdma[1].fw->data;
+                                                        adev->sdma.instance[1].fw->data;
                 break;
 
         default:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
index dfd1d503bccf..79fa5c7de856 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -523,12 +523,12 @@ static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
 
         case KGD_ENGINE_SDMA1:
                 hdr = (const union amdgpu_firmware_header *)
-                                                        adev->sdma[0].fw->data;
+                                                        adev->sdma.instance[0].fw->data;
                 break;
 
         case KGD_ENGINE_SDMA2:
                 hdr = (const union amdgpu_firmware_header *)
-                                                        adev->sdma[1].fw->data;
+                                                        adev->sdma.instance[1].fw->data;
                 break;
 
         default:
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
index 3f7aaa45bf8e..5a8fbadbd27b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c
@@ -501,7 +501,7 @@ static int amdgpu_atpx_get_client_id(struct pci_dev *pdev)
                 return VGA_SWITCHEROO_DIS;
 }
 
-static struct vga_switcheroo_handler amdgpu_atpx_handler = {
+static const struct vga_switcheroo_handler amdgpu_atpx_handler = {
         .switchto = amdgpu_atpx_switchto,
         .power_state = amdgpu_atpx_power_state,
         .init = amdgpu_atpx_init,
@@ -536,7 +536,7 @@ static bool amdgpu_atpx_detect(void)
 
         if (has_atpx && vga_count == 2) {
                 acpi_get_name(amdgpu_atpx_priv.atpx.handle, ACPI_FULL_PATHNAME, &buffer);
-                printk(KERN_INFO "VGA switcheroo: detected switching method %s handle\n",
+                printk(KERN_INFO "vga_switcheroo: detected switching method %s handle\n",
                        acpi_method_name);
                 amdgpu_atpx_priv.atpx_detected = true;
                 return true;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index 02add0a508cb..c44c0c6afd1b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -29,7 +29,6 @@
 #include "amdgpu.h"
 #include "atom.h"
 
-#include <linux/vga_switcheroo.h>
 #include <linux/slab.h>
 #include <linux/acpi.h>
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index fd16652aa277..dfc4d02c7a38 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -104,10 +104,11 @@ int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
                 }
                 break;
         case AMDGPU_HW_IP_DMA:
-                if (ring < 2) {
-                        *out_ring = &adev->sdma[ring].ring;
+                if (ring < adev->sdma.num_instances) {
+                        *out_ring = &adev->sdma.instance[ring].ring;
                 } else {
-                        DRM_ERROR("only two SDMA rings are supported\n");
+                        DRM_ERROR("only %d SDMA rings are supported\n",
+                                  adev->sdma.num_instances);
                         return -EINVAL;
                 }
                 break;
@@ -567,9 +568,24 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
                         if (r)
                                 return r;
                 }
+
+        }
+
+        r = amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync);
+
+        if (amdgpu_vm_debug && p->bo_list) {
+                /* Invalidate all BOs to test for userspace bugs */
+                for (i = 0; i < p->bo_list->num_entries; i++) {
+                        /* ignore duplicates */
+                        bo = p->bo_list->array[i].robj;
+                        if (!bo)
+                                continue;
+
+                        amdgpu_vm_bo_invalidate(adev, bo);
+                }
         }
 
-        return amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync);
+        return r;
 }
 
 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
@@ -593,7 +609,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
                 }
         }
 
-        mutex_lock(&vm->mutex);
         r = amdgpu_bo_vm_update_pte(parser, vm);
         if (r) {
                 goto out;
@@ -604,7 +619,6 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
                                        parser->filp);
 
 out:
-        mutex_unlock(&vm->mutex);
         return r;
 }
 
@@ -812,15 +826,14 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 {
         struct amdgpu_device *adev = dev->dev_private;
         union drm_amdgpu_cs *cs = data;
+        struct amdgpu_fpriv *fpriv = filp->driver_priv;
+        struct amdgpu_vm *vm = &fpriv->vm;
         struct amdgpu_cs_parser *parser;
         bool reserved_buffers = false;
         int i, r;
 
-        down_read(&adev->exclusive_lock);
-        if (!adev->accel_working) {
-                up_read(&adev->exclusive_lock);
+        if (!adev->accel_working)
                 return -EBUSY;
-        }
 
         parser = amdgpu_cs_parser_create(adev, filp, NULL, NULL, 0);
         if (!parser)
@@ -828,12 +841,11 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
         r = amdgpu_cs_parser_init(parser, data);
         if (r) {
                 DRM_ERROR("Failed to initialize parser !\n");
-                kfree(parser);
-                up_read(&adev->exclusive_lock);
+                amdgpu_cs_parser_fini(parser, r, false);
                 r = amdgpu_cs_handle_lockup(adev, r);
                 return r;
         }
-
+        mutex_lock(&vm->mutex);
         r = amdgpu_cs_parser_relocs(parser);
         if (r == -ENOMEM)
                 DRM_ERROR("Not enough memory for command submission!\n");
@@ -864,8 +876,10 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                 struct amdgpu_job *job;
                 struct amdgpu_ring * ring =  parser->ibs->ring;
                 job = kzalloc(sizeof(struct amdgpu_job), GFP_KERNEL);
-                if (!job)
-                        return -ENOMEM;
+                if (!job) {
+                        r = -ENOMEM;
+                        goto out;
+                }
                 job->base.sched = &ring->sched;
                 job->base.s_entity = &parser->ctx->rings[ring->idx].entity;
                 job->adev = parser->adev;
@@ -900,14 +914,14 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 
                 mutex_unlock(&job->job_lock);
                 amdgpu_cs_parser_fini_late(parser);
-                up_read(&adev->exclusive_lock);
+                mutex_unlock(&vm->mutex);
                 return 0;
         }
 
         cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence;
 out:
         amdgpu_cs_parser_fini(parser, r, reserved_buffers);
-        up_read(&adev->exclusive_lock);
+        mutex_unlock(&vm->mutex);
         r = amdgpu_cs_handle_lockup(adev, r);
         return r;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
index e0b80ccdfe8a..fec65f01c031 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
@@ -69,6 +69,9 @@ void amdgpu_ctx_fini(struct amdgpu_ctx *ctx)
         struct amdgpu_device *adev = ctx->adev;
         unsigned i, j;
 
+        if (!adev)
+                return;
+
         for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
                 for (j = 0; j < AMDGPU_CTX_MAX_CS_PENDING; ++j)
                         fence_put(ctx->rings[i].fences[j]);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 6068d8207d10..d5b421330145 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -57,6 +57,7 @@ static const char *amdgpu_asic_name[] = {
         "TONGA",
         "FIJI",
         "CARRIZO",
+        "STONEY",
         "LAST",
 };
 
@@ -1022,7 +1023,7 @@ static void amdgpu_check_arguments(struct amdgpu_device *adev)
  * amdgpu_switcheroo_set_state - set switcheroo state
  *
  * @pdev: pci dev pointer
- * @state: vga switcheroo state
+ * @state: vga_switcheroo state
  *
  * Callback for the switcheroo driver.  Suspends or resumes the
  * the asics before or after it is powered up using ACPI methods.
@@ -1165,7 +1166,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev)
         case CHIP_TONGA:
         case CHIP_FIJI:
         case CHIP_CARRIZO:
-                if (adev->asic_type == CHIP_CARRIZO)
+        case CHIP_STONEY:
+                if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
                         adev->family = AMDGPU_FAMILY_CZ;
                 else
                         adev->family = AMDGPU_FAMILY_VI;
@@ -1418,7 +1420,6 @@ int amdgpu_device_init(struct amdgpu_device *adev,
         mutex_init(&adev->gfx.gpu_clock_mutex);
         mutex_init(&adev->srbm_mutex);
         mutex_init(&adev->grbm_idx_mutex);
-        init_rwsem(&adev->exclusive_lock);
         mutex_init(&adev->mn_lock);
         hash_init(adev->mn_hash);
 
@@ -1657,11 +1658,21 @@ int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon)
         }
         drm_modeset_unlock_all(dev);
 
-        /* unpin the front buffers */
+        /* unpin the front buffers and cursors */
         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
                 struct amdgpu_bo *robj;
 
+                if (amdgpu_crtc->cursor_bo) {
+                        struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
+                        r = amdgpu_bo_reserve(aobj, false);
+                        if (r == 0) {
+                                amdgpu_bo_unpin(aobj);
+                                amdgpu_bo_unreserve(aobj);
+                        }
+                }
+
                 if (rfb == NULL || rfb->obj == NULL) {
                         continue;
                 }
@@ -1713,6 +1724,7 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
 {
         struct drm_connector *connector;
         struct amdgpu_device *adev = dev->dev_private;
+        struct drm_crtc *crtc;
         int r;
 
         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
@@ -1746,6 +1758,24 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
         if (r)
                 return r;
 
+        /* pin cursors */
+        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
+                struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
+
+                if (amdgpu_crtc->cursor_bo) {
+                        struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
+                        r = amdgpu_bo_reserve(aobj, false);
+                        if (r == 0) {
+                                r = amdgpu_bo_pin(aobj,
+                                                  AMDGPU_GEM_DOMAIN_VRAM,
+                                                  &amdgpu_crtc->cursor_addr);
+                                if (r != 0)
+                                        DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
+                                amdgpu_bo_unreserve(aobj);
+                        }
+                }
+        }
+
         /* blat the mode back in */
         if (fbcon) {
                 drm_helper_resume_force_mode(dev);
@@ -1785,14 +1815,6 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
         int i, r;
         int resched;
 
-        down_write(&adev->exclusive_lock);
-
-        if (!adev->needs_reset) {
-                up_write(&adev->exclusive_lock);
-                return 0;
-        }
-
-        adev->needs_reset = false;
         atomic_inc(&adev->gpu_reset_counter);
 
         /* block TTM */
@@ -1856,7 +1878,6 @@ retry:
                 dev_info(adev->dev, "GPU reset failed\n");
         }
 
-        up_write(&adev->exclusive_lock);
         return r;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
index 6c9e0902a414..e173a5a02f0d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
@@ -47,11 +47,8 @@ static void amdgpu_flip_wait_fence(struct amdgpu_device *adev,
         fence = to_amdgpu_fence(*f);
         if (fence) {
                 r = fence_wait(&fence->base, false);
-                if (r == -EDEADLK) {
-                        up_read(&adev->exclusive_lock);
+                if (r == -EDEADLK)
                         r = amdgpu_gpu_reset(adev);
-                        down_read(&adev->exclusive_lock);
-                }
         } else
                 r = fence_wait(*f, false);
 
@@ -77,7 +74,6 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
         unsigned long flags;
         unsigned i;
 
-        down_read(&adev->exclusive_lock);
         amdgpu_flip_wait_fence(adev, &work->excl);
         for (i = 0; i < work->shared_count; ++i)
                 amdgpu_flip_wait_fence(adev, &work->shared[i]);
@@ -91,7 +87,6 @@ static void amdgpu_flip_work_func(struct work_struct *__work)
         amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED;
 
         spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
-        up_read(&adev->exclusive_lock);
 }
 
 /*
@@ -715,7 +710,7 @@ bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
  * an optional accurate timestamp of when query happened.
  *
  * \param dev Device to query.
- * \param crtc Crtc to query.
+ * \param pipe Crtc to query.
  * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).
  * \param *vpos Location where vertical scanout position should be stored.
  * \param *hpos Location where horizontal scanout position should go.
@@ -738,8 +733,10 @@ bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
  * unknown small number of scanlines wrt. real scanout position.
  *
  */
-int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int flags,
-                               int *vpos, int *hpos, ktime_t *stime, ktime_t *etime)
+int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
+                               unsigned int flags, int *vpos, int *hpos,
+                               ktime_t *stime, ktime_t *etime,
+                               const struct drm_display_mode *mode)
 {
         u32 vbl = 0, position = 0;
         int vbl_start, vbl_end, vtotal, ret = 0;
@@ -753,7 +750,7 @@ int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int fl
         if (stime)
                 *stime = ktime_get();
 
-        if (amdgpu_display_page_flip_get_scanoutpos(adev, crtc, &vbl, &position) == 0)
+        if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0)
                 ret |= DRM_SCANOUTPOS_VALID;
 
         /* Get optional system timestamp after query. */
@@ -775,7 +772,7 @@ int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int fl
         }
         else {
                 /* No: Fake something reasonable which gives at least ok results. */
-                vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
+                vbl_start = mode->crtc_vdisplay;
                 vbl_end = 0;
         }
 
@@ -791,7 +788,7 @@ int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int fl
 
         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
         if (in_vbl && (*vpos >= vbl_start)) {
-                vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
+                vtotal = mode->crtc_vtotal;
                 *vpos = *vpos - vtotal;
         }
 
@@ -813,8 +810,8 @@ int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc, unsigned int fl
          * We only do this if DRM_CALLED_FROM_VBLIRQ.
          */
         if ((flags & DRM_CALLED_FROM_VBLIRQ) && !in_vbl) {
-                vbl_start = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
-                vtotal = adev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
+                vbl_start = mode->crtc_vdisplay;
+                vtotal = mode->crtc_vtotal;
 
                 if (vbl_start - *vpos < vtotal / 100) {
                         *vpos -= vtotal;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index b190c2a83680..0508c5cd103a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -73,13 +73,15 @@ int amdgpu_hard_reset = 0;
 unsigned amdgpu_ip_block_mask = 0xffffffff;
 int amdgpu_bapm = -1;
 int amdgpu_deep_color = 0;
-int amdgpu_vm_size = 8;
+int amdgpu_vm_size = 64;
 int amdgpu_vm_block_size = -1;
+int amdgpu_vm_fault_stop = 0;
+int amdgpu_vm_debug = 0;
 int amdgpu_exp_hw_support = 0;
-int amdgpu_enable_scheduler = 0;
+int amdgpu_enable_scheduler = 1;
 int amdgpu_sched_jobs = 16;
 int amdgpu_sched_hw_submission = 2;
-int amdgpu_enable_semaphores = 1;
+int amdgpu_enable_semaphores = 0;
 
 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
@@ -135,16 +137,22 @@ module_param_named(bapm, amdgpu_bapm, int, 0444);
 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
 module_param_named(deep_color, amdgpu_deep_color, int, 0444);
 
-MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 8GB)");
+MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
 module_param_named(vm_size, amdgpu_vm_size, int, 0444);
 
 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
 
+MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
+module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
+
+MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
+module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
+
 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
 
-MODULE_PARM_DESC(enable_scheduler, "enable SW GPU scheduler (1 = enable, 0 = disable ((default))");
+MODULE_PARM_DESC(enable_scheduler, "enable SW GPU scheduler (1 = enable (default), 0 = disable)");
 module_param_named(enable_scheduler, amdgpu_enable_scheduler, int, 0444);
 
 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 16)");
@@ -153,7 +161,7 @@ module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
 
-MODULE_PARM_DESC(enable_semaphores, "Enable semaphores (1 = enable (default), 0 = disable)");
+MODULE_PARM_DESC(enable_semaphores, "Enable semaphores (1 = enable, 0 = disable (default))");
 module_param_named(enable_semaphores, amdgpu_enable_semaphores, int, 0644);
 
 static struct pci_device_id pciidlist[] = {
@@ -265,6 +273,8 @@ static struct pci_device_id pciidlist[] = {
         {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
         {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
         {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
+        /* stoney */
+        {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
 
         {0, 0, 0}
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index 96290d9cddca..093a8c618931 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -207,6 +207,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
         }
 
         info->par = rfbdev;
+        info->skip_vt_switch = true;
 
         ret = amdgpu_framebuffer_init(adev->ddev, &rfbdev->rfb, &mode_cmd, gobj);
         if (ret) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
index b3fc26c59787..257d72205bb5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
@@ -137,42 +137,6 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner,
 }
 
 /**
- * amdgpu_fence_check_signaled - callback from fence_queue
- *
- * this function is called with fence_queue lock held, which is also used
- * for the fence locking itself, so unlocked variants are used for
- * fence_signal, and remove_wait_queue.
- */
-static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key)
-{
-        struct amdgpu_fence *fence;
-        struct amdgpu_device *adev;
-        u64 seq;
-        int ret;
-
-        fence = container_of(wait, struct amdgpu_fence, fence_wake);
-        adev = fence->ring->adev;
-
-        /*
-         * We cannot use amdgpu_fence_process here because we're already
-         * in the waitqueue, in a call from wake_up_all.
-         */
-        seq = atomic64_read(&fence->ring->fence_drv.last_seq);
-        if (seq >= fence->seq) {
-                ret = fence_signal_locked(&fence->base);
-                if (!ret)
-                        FENCE_TRACE(&fence->base, "signaled from irq context\n");
-                else
-                        FENCE_TRACE(&fence->base, "was already signaled\n");
-
-                __remove_wait_queue(&fence->ring->fence_drv.fence_queue, &fence->fence_wake);
-                fence_put(&fence->base);
-        } else
-                FENCE_TRACE(&fence->base, "pending\n");
-        return 0;
-}
-
-/**
  * amdgpu_fence_activity - check for fence activity
  *
  * @ring: pointer to struct amdgpu_ring
@@ -260,27 +224,8 @@ static void amdgpu_fence_check_lockup(struct work_struct *work)
                                 lockup_work.work);
         ring = fence_drv->ring;
 
-        if (!down_read_trylock(&ring->adev->exclusive_lock)) {
-                /* just reschedule the check if a reset is going on */
-                amdgpu_fence_schedule_check(ring);
-                return;
-        }
-
-        if (amdgpu_fence_activity(ring)) {
-                wake_up_all(&ring->fence_drv.fence_queue);
-        }
-        else if (amdgpu_ring_is_lockup(ring)) {
-                /* good news we believe it's a lockup */
-                dev_warn(ring->adev->dev, "GPU lockup (current fence id "
-                        "0x%016llx last fence id 0x%016llx on ring %d)\n",
-                        (uint64_t)atomic64_read(&fence_drv->last_seq),
-                        fence_drv->sync_seq[ring->idx], ring->idx);
-
-                /* remember that we need an reset */
-                ring->adev->needs_reset = true;
+        if (amdgpu_fence_activity(ring))
                 wake_up_all(&ring->fence_drv.fence_queue);
-        }
-        up_read(&ring->adev->exclusive_lock);
 }
 
 /**
@@ -324,50 +269,6 @@ static bool amdgpu_fence_seq_signaled(struct amdgpu_ring *ring, u64 seq)
         return false;
 }
 
-static bool amdgpu_fence_is_signaled(struct fence *f)
-{
-        struct amdgpu_fence *fence = to_amdgpu_fence(f);
-        struct amdgpu_ring *ring = fence->ring;
-        struct amdgpu_device *adev = ring->adev;
-
-        if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
-                return true;
-
-        if (down_read_trylock(&adev->exclusive_lock)) {
-                amdgpu_fence_process(ring);
-                up_read(&adev->exclusive_lock);
-
-                if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
-                        return true;
-        }
-        return false;
-}
-
-/**
- * amdgpu_fence_enable_signaling - enable signalling on fence
- * @fence: fence
- *
- * This function is called with fence_queue lock held, and adds a callback
- * to fence_queue that checks if this fence is signaled, and if so it
- * signals the fence and removes itself.
- */
-static bool amdgpu_fence_enable_signaling(struct fence *f)
-{
-        struct amdgpu_fence *fence = to_amdgpu_fence(f);
-        struct amdgpu_ring *ring = fence->ring;
-
-        if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
-                return false;
-
-        fence->fence_wake.flags = 0;
-        fence->fence_wake.private = NULL;
-        fence->fence_wake.func = amdgpu_fence_check_signaled;
-        __add_wait_queue(&ring->fence_drv.fence_queue, &fence->fence_wake);
-        fence_get(f);
-        FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
-        return true;
-}
-
 /*
  * amdgpu_ring_wait_seq_timeout - wait for seq of the specific ring to signal
  * @ring: ring to wait on for the seq number
@@ -380,7 +281,6 @@ static bool amdgpu_fence_enable_signaling(struct fence *f)
  */
 static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq)
 {
-        struct amdgpu_device *adev = ring->adev;
         bool signaled = false;
 
         BUG_ON(!ring);
@@ -390,9 +290,9 @@ static int amdgpu_fence_ring_wait_seq(struct amdgpu_ring *ring, uint64_t seq)
         if (atomic64_read(&ring->fence_drv.last_seq) >= seq)
                 return 0;
 
+        amdgpu_fence_schedule_check(ring);
         wait_event(ring->fence_drv.fence_queue, (
-                   (signaled = amdgpu_fence_seq_signaled(ring, seq))
-                   || adev->needs_reset));
+                   (signaled = amdgpu_fence_seq_signaled(ring, seq))));
 
         if (signaled)
                 return 0;
@@ -441,36 +341,6 @@ int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
 }
 
 /**
- * amdgpu_fence_ref - take a ref on a fence
- *
- * @fence: amdgpu fence object
- *
- * Take a reference on a fence (all asics).
- * Returns the fence.
- */
-struct amdgpu_fence *amdgpu_fence_ref(struct amdgpu_fence *fence)
-{
-        fence_get(&fence->base);
-        return fence;
-}
-
-/**
- * amdgpu_fence_unref - remove a ref on a fence
- *
- * @fence: amdgpu fence object
- *
- * Remove a reference on a fence (all asics).
- */
-void amdgpu_fence_unref(struct amdgpu_fence **fence)
-{
-        struct amdgpu_fence *tmp = *fence;
-
-        *fence = NULL;
-        if (tmp)
-                fence_put(&tmp->base);
-}
-
-/**
  * amdgpu_fence_count_emitted - get the count of emitted fences
  *
  * @ring: ring the fence is associated with
@@ -628,8 +498,20 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
         init_waitqueue_head(&ring->fence_drv.fence_queue);
 
         if (amdgpu_enable_scheduler) {
+                long timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
+                if (timeout == 0) {
+                        /*
+                         * FIXME:
+                         * Delayed workqueue cannot use it directly,
+                         * so the scheduler will not use delayed workqueue if
+                         * MAX_SCHEDULE_TIMEOUT is set.
+                         * Currently keep it simple and silly.
+                         */
+                        timeout = MAX_SCHEDULE_TIMEOUT;
+                }
                 r = amd_sched_init(&ring->sched, &amdgpu_sched_ops,
-                                   amdgpu_sched_hw_submission, ring->name);
+                                   amdgpu_sched_hw_submission,
+                                   timeout, ring->name);
                 if (r) {
                         DRM_ERROR("Failed to create scheduler on ring %s.\n",
                                   ring->name);
@@ -773,6 +655,115 @@ void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev)
         }
 }
 
+/*
+ * Common fence implementation
+ */
+
+static const char *amdgpu_fence_get_driver_name(struct fence *fence)
+{
+        return "amdgpu";
+}
+
+static const char *amdgpu_fence_get_timeline_name(struct fence *f)
+{
+        struct amdgpu_fence *fence = to_amdgpu_fence(f);
+        return (const char *)fence->ring->name;
+}
+
+/**
+ * amdgpu_fence_is_signaled - test if fence is signaled
+ *
+ * @f: fence to test
+ *
+ * Test the fence sequence number if it is already signaled. If it isn't
+ * signaled start fence processing. Returns True if the fence is signaled.
+ */
+static bool amdgpu_fence_is_signaled(struct fence *f)
+{
+        struct amdgpu_fence *fence = to_amdgpu_fence(f);
+        struct amdgpu_ring *ring = fence->ring;
+
+        if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
+                return true;
+
+        amdgpu_fence_process(ring);
+
+        if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
+                return true;
+
+        return false;
+}
+
+/**
+ * amdgpu_fence_check_signaled - callback from fence_queue
+ *
+ * this function is called with fence_queue lock held, which is also used
+ * for the fence locking itself, so unlocked variants are used for
+ * fence_signal, and remove_wait_queue.
+ */
+static int amdgpu_fence_check_signaled(wait_queue_t *wait, unsigned mode, int flags, void *key)
+{
+        struct amdgpu_fence *fence;
+        struct amdgpu_device *adev;
+        u64 seq;
+        int ret;
+
+        fence = container_of(wait, struct amdgpu_fence, fence_wake);
+        adev = fence->ring->adev;
+
+        /*
+         * We cannot use amdgpu_fence_process here because we're already
+         * in the waitqueue, in a call from wake_up_all.
+         */
+        seq = atomic64_read(&fence->ring->fence_drv.last_seq);
+        if (seq >= fence->seq) {
+                ret = fence_signal_locked(&fence->base);
+                if (!ret)
+                        FENCE_TRACE(&fence->base, "signaled from irq context\n");
+                else
+                        FENCE_TRACE(&fence->base, "was already signaled\n");
+
+                __remove_wait_queue(&fence->ring->fence_drv.fence_queue, &fence->fence_wake);
+                fence_put(&fence->base);
+        } else
+                FENCE_TRACE(&fence->base, "pending\n");
+        return 0;
+}
+
+/**
+ * amdgpu_fence_enable_signaling - enable signalling on fence
+ * @fence: fence
+ *
+ * This function is called with fence_queue lock held, and adds a callback
+ * to fence_queue that checks if this fence is signaled, and if so it
+ * signals the fence and removes itself.
+ */
+static bool amdgpu_fence_enable_signaling(struct fence *f)
+{
+        struct amdgpu_fence *fence = to_amdgpu_fence(f);
+        struct amdgpu_ring *ring = fence->ring;
+
+        if (atomic64_read(&ring->fence_drv.last_seq) >= fence->seq)
+                return false;
+
+        fence->fence_wake.flags = 0;
+        fence->fence_wake.private = NULL;
+        fence->fence_wake.func = amdgpu_fence_check_signaled;
+        __add_wait_queue(&ring->fence_drv.fence_queue, &fence->fence_wake);
+        fence_get(f);
+        amdgpu_fence_schedule_check(ring);
+        FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
+        return true;
+}
+
+const struct fence_ops amdgpu_fence_ops = {
+        .get_driver_name = amdgpu_fence_get_driver_name,
+        .get_timeline_name = amdgpu_fence_get_timeline_name,
+        .enable_signaling = amdgpu_fence_enable_signaling,
+        .signaled = amdgpu_fence_is_signaled,
+        .wait = fence_default_wait,
+        .release = NULL,
+};
 
 /*
  * Fence debugfs
@@ -823,141 +814,3 @@ int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
 #endif
 }
 
-static const char *amdgpu_fence_get_driver_name(struct fence *fence)
-{
-        return "amdgpu";
-}
-
-static const char *amdgpu_fence_get_timeline_name(struct fence *f)
-{
-        struct amdgpu_fence *fence = to_amdgpu_fence(f);
-        return (const char *)fence->ring->name;
-}
-
-static inline bool amdgpu_test_signaled(struct amdgpu_fence *fence)
-{
-        return test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);
-}
-
-static bool amdgpu_test_signaled_any(struct fence **fences, uint32_t count)
-{
-        int idx;
-        struct fence *fence;
-
-        for (idx = 0; idx < count; ++idx) {
-                fence = fences[idx];
-                if (fence) {
-                        if (test_bit(FENCE_FLAG_SIGNALED_BIT, &fence->flags))
-                                return true;
-                }
-        }
-        return false;
-}
-
-struct amdgpu_wait_cb {
-        struct fence_cb base;
-        struct task_struct *task;
-};
-
-static void amdgpu_fence_wait_cb(struct fence *fence, struct fence_cb *cb)
-{
-        struct amdgpu_wait_cb *wait =
-                container_of(cb, struct amdgpu_wait_cb, base);
-        wake_up_process(wait->task);
-}
-
-static signed long amdgpu_fence_default_wait(struct fence *f, bool intr,
-                                             signed long t)
-{
-        struct amdgpu_fence *fence = to_amdgpu_fence(f);
-        struct amdgpu_device *adev = fence->ring->adev;
-
-        return amdgpu_fence_wait_any(adev, &f, 1, intr, t);
-}
-
-/**
- * Wait the fence array with timeout
- *
- * @adev:     amdgpu device
- * @array:    the fence array with amdgpu fence pointer
- * @count:    the number of the fence array
- * @intr:     when sleep, set the current task interruptable or not
- * @t:        timeout to wait
- *
- * It will return when any fence is signaled or timeout.
- */
-signed long amdgpu_fence_wait_any(struct amdgpu_device *adev,
-                                  struct fence **array, uint32_t count,
-                                  bool intr, signed long t)
-{
-        struct amdgpu_wait_cb *cb;
-        struct fence *fence;
-        unsigned idx;
-
-        BUG_ON(!array);
-
-        cb = kcalloc(count, sizeof(struct amdgpu_wait_cb), GFP_KERNEL);
-        if (cb == NULL) {
-                t = -ENOMEM;
-                goto err_free_cb;
-        }
-
-        for (idx = 0; idx < count; ++idx) {
-                fence = array[idx];
-                if (fence) {
-                        cb[idx].task = current;
-                        if (fence_add_callback(fence,
-                                        &cb[idx].base, amdgpu_fence_wait_cb)) {
-                                /* The fence is already signaled */
-                                goto fence_rm_cb;
-                        }
-                }
-        }
-
-        while (t > 0) {
-                if (intr)
-                        set_current_state(TASK_INTERRUPTIBLE);
-                else
-                        set_current_state(TASK_UNINTERRUPTIBLE);
-
-                /*
-                 * amdgpu_test_signaled_any must be called after
-                 * set_current_state to prevent a race with wake_up_process
-                 */
-                if (amdgpu_test_signaled_any(array, count))
-                        break;
-
-                if (adev->needs_reset) {
-                        t = -EDEADLK;
-                        break;
-                }
-
-                t = schedule_timeout(t);
-
-                if (t > 0 && intr && signal_pending(current))
-                        t = -ERESTARTSYS;
-        }
-
-        __set_current_state(TASK_RUNNING);
-
-fence_rm_cb:
-        for (idx = 0; idx < count; ++idx) {
-                fence = array[idx];
-                if (fence && cb[idx].base.func)
-                        fence_remove_callback(fence, &cb[idx].base);
-        }
-
-err_free_cb:
-        kfree(cb);
-
-        return t;
-}
-
-const struct fence_ops amdgpu_fence_ops = {
-        .get_driver_name = amdgpu_fence_get_driver_name,
-        .get_timeline_name = amdgpu_fence_get_timeline_name,
-        .enable_signaling = amdgpu_fence_enable_signaling,
-        .signaled = amdgpu_fence_is_signaled,
-        .wait = amdgpu_fence_default_wait,
-        .release = NULL,
-};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 7297ca3a0ba7..087332858853 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -115,9 +115,10 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri
         struct amdgpu_vm *vm = &fpriv->vm;
         struct amdgpu_bo_va *bo_va;
         int r;
-
+        mutex_lock(&vm->mutex);
         r = amdgpu_bo_reserve(rbo, false);
         if (r) {
+                mutex_unlock(&vm->mutex);
                 return r;
         }
 
@@ -128,7 +129,7 @@ int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_pri
                 ++bo_va->ref_count;
         }
         amdgpu_bo_unreserve(rbo);
-
+        mutex_unlock(&vm->mutex);
         return 0;
 }
 
@@ -141,9 +142,10 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
         struct amdgpu_vm *vm = &fpriv->vm;
         struct amdgpu_bo_va *bo_va;
         int r;
-
+        mutex_lock(&vm->mutex);
         r = amdgpu_bo_reserve(rbo, true);
         if (r) {
+                mutex_unlock(&vm->mutex);
                 dev_err(adev->dev, "leaking bo va because "
                         "we fail to reserve bo (%d)\n", r);
                 return;
@@ -155,6 +157,7 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj,
                 }
         }
         amdgpu_bo_unreserve(rbo);
+        mutex_unlock(&vm->mutex);
 }
 
 static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r)
@@ -181,7 +184,6 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
         bool kernel = false;
         int r;
 
-        down_read(&adev->exclusive_lock);
         /* create a gem object to contain this object in */
         if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS |
             AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
@@ -214,11 +216,9 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
 
         memset(args, 0, sizeof(*args));
         args->out.handle = handle;
-        up_read(&adev->exclusive_lock);
         return 0;
 
 error_unlock:
-        up_read(&adev->exclusive_lock);
         r = amdgpu_gem_handle_lockup(adev, r);
         return r;
 }
@@ -250,8 +250,6 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
                 return -EACCES;
         }
 
-        down_read(&adev->exclusive_lock);
-
         /* create a gem object to contain this object in */
         r = amdgpu_gem_object_create(adev, args->size, 0,
                                      AMDGPU_GEM_DOMAIN_CPU, 0,
@@ -293,14 +291,12 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
                 goto handle_lockup;
 
         args->handle = handle;
-        up_read(&adev->exclusive_lock);
         return 0;
 
 release_object:
         drm_gem_object_unreference_unlocked(gobj);
 
 handle_lockup:
-        up_read(&adev->exclusive_lock);
         r = amdgpu_gem_handle_lockup(adev, r);
 
         return r;
@@ -488,18 +484,13 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev,
                         goto error_unreserve;
         }
 
-        mutex_lock(&bo_va->vm->mutex);
         r = amdgpu_vm_clear_freed(adev, bo_va->vm);
         if (r)
-                goto error_unlock;
-
+                goto error_unreserve;
 
         if (operation == AMDGPU_VA_OP_MAP)
                 r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem);
 
-error_unlock:
-        mutex_unlock(&bo_va->vm->mutex);
-
 error_unreserve:
         ttm_eu_backoff_reservation(&ticket, &list);
 
@@ -556,10 +547,11 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
         gobj = drm_gem_object_lookup(dev, filp, args->handle);
         if (gobj == NULL)
                 return -ENOENT;
-
+        mutex_lock(&fpriv->vm.mutex);
         rbo = gem_to_amdgpu_bo(gobj);
         r = amdgpu_bo_reserve(rbo, false);
         if (r) {
+                mutex_unlock(&fpriv->vm.mutex);
                 drm_gem_object_unreference_unlocked(gobj);
                 return r;
         }
@@ -567,6 +559,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
         bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo);
         if (!bo_va) {
                 amdgpu_bo_unreserve(rbo);
+                mutex_unlock(&fpriv->vm.mutex);
                 return -ENOENT;
         }
 
@@ -591,7 +584,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
 
         if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE))
                 amdgpu_gem_va_update_vm(adev, bo_va, args->operation);
-
+        mutex_unlock(&fpriv->vm.mutex);
         drm_gem_object_unreference_unlocked(gobj);
         return r;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index c439735ee670..e65987743871 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -95,7 +95,8 @@ void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib)
 {
         amdgpu_sync_free(adev, &ib->sync, &ib->fence->base);
         amdgpu_sa_bo_free(adev, &ib->sa_bo, &ib->fence->base);
-        amdgpu_fence_unref(&ib->fence);
+        if (ib->fence)
+                fence_put(&ib->fence->base);
 }
 
 /**
@@ -298,7 +299,6 @@ int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
                 r = amdgpu_ring_test_ib(ring);
                 if (r) {
                         ring->ready = false;
-                        adev->needs_reset = false;
 
                         if (ring == &adev->gfx.gfx_ring[0]) {
                                 /* oh, oh, that's really bad */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 5d11e798230c..1618e2294a16 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -218,8 +218,8 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                         break;
                 case AMDGPU_HW_IP_DMA:
                         type = AMD_IP_BLOCK_TYPE_SDMA;
-                        ring_mask = adev->sdma[0].ring.ready ? 1 : 0;
-                        ring_mask |= ((adev->sdma[1].ring.ready ? 1 : 0) << 1);
+                        for (i = 0; i < adev->sdma.num_instances; i++)
+                                ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
                         ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
                         ib_size_alignment = 1;
                         break;
@@ -341,10 +341,10 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
                         fw_info.feature = 0;
                         break;
                 case AMDGPU_INFO_FW_SDMA:
-                        if (info->query_fw.index >= 2)
+                        if (info->query_fw.index >= adev->sdma.num_instances)
                                 return -EINVAL;
-                        fw_info.ver = adev->sdma[info->query_fw.index].fw_version;
-                        fw_info.feature = adev->sdma[info->query_fw.index].feature_version;
+                        fw_info.ver = adev->sdma.instance[info->query_fw.index].fw_version;
+                        fw_info.feature = adev->sdma.instance[info->query_fw.index].feature_version;
                         break;
                 default:
                         return -EINVAL;
@@ -489,7 +489,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
  *
  * @dev: drm dev pointer
  *
- * Switch vga switcheroo state after last close (all asics).
+ * Switch vga_switcheroo state after last close (all asics).
  */
 void amdgpu_driver_lastclose_kms(struct drm_device *dev)
 {
@@ -603,36 +603,36 @@ void amdgpu_driver_preclose_kms(struct drm_device *dev,
  * amdgpu_get_vblank_counter_kms - get frame count
  *
  * @dev: drm dev pointer
- * @crtc: crtc to get the frame count from
+ * @pipe: crtc to get the frame count from
  *
  * Gets the frame count on the requested crtc (all asics).
  * Returns frame count on success, -EINVAL on failure.
  */
-u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc)
+u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe)
 {
         struct amdgpu_device *adev = dev->dev_private;
 
-        if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
-                DRM_ERROR("Invalid crtc %d\n", crtc);
+        if (pipe >= adev->mode_info.num_crtc) {
+                DRM_ERROR("Invalid crtc %u\n", pipe);
                 return -EINVAL;
         }
 
-        return amdgpu_display_vblank_get_counter(adev, crtc);
+        return amdgpu_display_vblank_get_counter(adev, pipe);
 }
 
 /**
  * amdgpu_enable_vblank_kms - enable vblank interrupt
  *
  * @dev: drm dev pointer
- * @crtc: crtc to enable vblank interrupt for
+ * @pipe: crtc to enable vblank interrupt for
  *
  * Enable the interrupt on the requested crtc (all asics).
  * Returns 0 on success, -EINVAL on failure.
  */
-int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc)
+int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe)
 {
         struct amdgpu_device *adev = dev->dev_private;
-        int idx = amdgpu_crtc_idx_to_irq_type(adev, crtc);
+        int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
 
         return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
 }
@@ -641,14 +641,14 @@ int amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc)
  * amdgpu_disable_vblank_kms - disable vblank interrupt
  *
  * @dev: drm dev pointer
- * @crtc: crtc to disable vblank interrupt for
+ * @pipe: crtc to disable vblank interrupt for
  *
  * Disable the interrupt on the requested crtc (all asics).
  */
-void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc)
+void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe)
 {
         struct amdgpu_device *adev = dev->dev_private;
-        int idx = amdgpu_crtc_idx_to_irq_type(adev, crtc);
+        int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe);
 
         amdgpu_irq_put(adev, &adev->crtc_irq, idx);
 }
@@ -666,41 +666,41 @@ void amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc)
  * scanout position.  (all asics).
  * Returns postive status flags on success, negative error on failure.
  */
-int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
+int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
                                     int *max_error,
                                     struct timeval *vblank_time,
                                     unsigned flags)
 {
-        struct drm_crtc *drmcrtc;
+        struct drm_crtc *crtc;
         struct amdgpu_device *adev = dev->dev_private;
 
-        if (crtc < 0 || crtc >= dev->num_crtcs) {
-                DRM_ERROR("Invalid crtc %d\n", crtc);
+        if (pipe >= dev->num_crtcs) {
+                DRM_ERROR("Invalid crtc %u\n", pipe);
                 return -EINVAL;
         }
 
         /* Get associated drm_crtc: */
-        drmcrtc = &adev->mode_info.crtcs[crtc]->base;
+        crtc = &adev->mode_info.crtcs[pipe]->base;
 
         /* Helper routine in DRM core does all the work: */
-        return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
+        return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
                                                      vblank_time, flags,
-                                                     drmcrtc, &drmcrtc->hwmode);
+                                                     &crtc->hwmode);
 }
 
 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
-        DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
-        DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
-        DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
         /* KMS */
-        DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
-        DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
-        DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
-        DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
-        DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
-        DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
-        DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
-        DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
-        DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
+        DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
 };
 int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 7bd470d9ac30..b62c1710cab6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -373,6 +373,10 @@ struct amdgpu_crtc {
         uint32_t crtc_offset;
         struct drm_gem_object *cursor_bo;
         uint64_t cursor_addr;
+        int cursor_x;
+        int cursor_y;
+        int cursor_hot_x;
+        int cursor_hot_y;
         int cursor_width;
         int cursor_height;
         int max_cursor_width;
@@ -540,10 +544,10 @@ bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux);
 
 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
 
-int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
-                                      unsigned int flags,
-                                      int *vpos, int *hpos, ktime_t *stime,
-                                      ktime_t *etime);
+int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
+                               unsigned int flags, int *vpos, int *hpos,
+                               ktime_t *stime, ktime_t *etime,
+                               const struct drm_display_mode *mode);
 
 int amdgpu_framebuffer_init(struct drm_device *dev,
                              struct amdgpu_framebuffer *rfb,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 1a7708f365f3..0d524384ff79 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -132,6 +132,8 @@ static void amdgpu_ttm_placement_init(struct amdgpu_device *adev,
                 placements[c].fpfn = 0;
                 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
                         TTM_PL_FLAG_VRAM;
+                if (!(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED))
+                        placements[c - 1].flags |= TTM_PL_FLAG_TOPDOWN;
         }
 
         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
index 30dce235ddeb..78e9b0f14661 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
@@ -67,8 +67,6 @@ void amdgpu_ring_free_size(struct amdgpu_ring *ring)
         if (!ring->ring_free_dw) {
                 /* this is an empty ring */
                 ring->ring_free_dw = ring->ring_size / 4;
-                /*  update lockup info to avoid false positive */
-                amdgpu_ring_lockup_update(ring);
         }
 }
 
@@ -209,46 +207,6 @@ void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring)
 }
 
 /**
- * amdgpu_ring_lockup_update - update lockup variables
- *
- * @ring: amdgpu_ring structure holding ring information
- *
- * Update the last rptr value and timestamp (all asics).
- */
-void amdgpu_ring_lockup_update(struct amdgpu_ring *ring)
-{
-        atomic_set(&ring->last_rptr, amdgpu_ring_get_rptr(ring));
-        atomic64_set(&ring->last_activity, jiffies_64);
-}
-
-/**
- * amdgpu_ring_test_lockup() - check if ring is lockedup by recording information
- * @ring:       amdgpu_ring structure holding ring information
- *
- */
-bool amdgpu_ring_test_lockup(struct amdgpu_ring *ring)
-{
-        uint32_t rptr = amdgpu_ring_get_rptr(ring);
-        uint64_t last = atomic64_read(&ring->last_activity);
-        uint64_t elapsed;
-
-        if (rptr != atomic_read(&ring->last_rptr)) {
-                /* ring is still working, no lockup */
-                amdgpu_ring_lockup_update(ring);
-                return false;
-        }
-
-        elapsed = jiffies_to_msecs(jiffies_64 - last);
-        if (amdgpu_lockup_timeout && elapsed >= amdgpu_lockup_timeout) {
-                dev_err(ring->adev->dev, "ring %d stalled for more than %llumsec\n",
-                        ring->idx, elapsed);
-                return true;
-        }
-        /* give a chance to the GPU ... */
-        return false;
-}
-
-/**
  * amdgpu_ring_backup - Back up the content of a ring
  *
  * @ring: the ring we want to back up
@@ -436,7 +394,6 @@ int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
         if (amdgpu_debugfs_ring_init(adev, ring)) {
                 DRM_ERROR("Failed to register debugfs file for rings !\n");
         }
-        amdgpu_ring_lockup_update(ring);
         return 0;
 }
 
@@ -479,6 +436,30 @@ void amdgpu_ring_fini(struct amdgpu_ring *ring)
         }
 }
 
+/**
+ * amdgpu_ring_from_fence - get ring from fence
+ *
+ * @f: fence structure
+ *
+ * Extract the ring a fence belongs to. Handles both scheduler as
+ * well as hardware fences.
+ */
+struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f)
+{
+        struct amdgpu_fence *a_fence;
+        struct amd_sched_fence *s_fence;
+
+        s_fence = to_amd_sched_fence(f);
+        if (s_fence)
+                return container_of(s_fence->sched, struct amdgpu_ring, sched);
+
+        a_fence = to_amdgpu_fence(f);
+        if (a_fence)
+                return a_fence->ring;
+
+        return NULL;
+}
+
 /*
  * Debugfs info
  */
@@ -540,8 +521,8 @@ static int amdgpu_debugfs_ring_info(struct seq_file *m, void *data)
 static int amdgpu_gfx_index = offsetof(struct amdgpu_device, gfx.gfx_ring[0]);
 static int cayman_cp1_index = offsetof(struct amdgpu_device, gfx.compute_ring[0]);
 static int cayman_cp2_index = offsetof(struct amdgpu_device, gfx.compute_ring[1]);
-static int amdgpu_dma1_index = offsetof(struct amdgpu_device, sdma[0].ring);
-static int amdgpu_dma2_index = offsetof(struct amdgpu_device, sdma[1].ring);
+static int amdgpu_dma1_index = offsetof(struct amdgpu_device, sdma.instance[0].ring);
+static int amdgpu_dma2_index = offsetof(struct amdgpu_device, sdma.instance[1].ring);
 static int r600_uvd_index = offsetof(struct amdgpu_device, uvd.ring);
 static int si_vce1_index = offsetof(struct amdgpu_device, vce.ring[0]);
 static int si_vce2_index = offsetof(struct amdgpu_device, vce.ring[1]);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
index e90712443fe9..0212b31dc194 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sa.c
@@ -139,25 +139,6 @@ int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
         return r;
 }
 
-static uint32_t amdgpu_sa_get_ring_from_fence(struct fence *f)
-{
-        struct amdgpu_fence *a_fence;
-        struct amd_sched_fence *s_fence;
-
-        s_fence = to_amd_sched_fence(f);
-        if (s_fence) {
-                struct amdgpu_ring *ring;
-
-                ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
-                return ring->idx;
-        }
-
-        a_fence = to_amdgpu_fence(f);
-        if (a_fence)
-                return a_fence->ring->idx;
-        return 0;
-}
-
 static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo)
 {
         struct amdgpu_sa_manager *sa_manager = sa_bo->manager;
@@ -318,7 +299,7 @@ static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager,
         }
 
         if (best_bo) {
-                uint32_t idx = amdgpu_sa_get_ring_from_fence(best_bo->fence);
+                uint32_t idx = amdgpu_ring_from_fence(best_bo->fence)->idx;
                 ++tries[idx];
                 sa_manager->hole = best_bo->olist.prev;
 
@@ -337,6 +318,7 @@ int amdgpu_sa_bo_new(struct amdgpu_device *adev,
 {
         struct fence *fences[AMDGPU_MAX_RINGS];
         unsigned tries[AMDGPU_MAX_RINGS];
+        unsigned count;
         int i, r;
         signed long t;
 
@@ -371,13 +353,18 @@ int amdgpu_sa_bo_new(struct amdgpu_device *adev,
                         /* see if we can skip over some allocations */
                 } while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries));
 
-                spin_unlock(&sa_manager->wq.lock);
-                t = amdgpu_fence_wait_any(adev, fences, AMDGPU_MAX_RINGS,
-                                          false, MAX_SCHEDULE_TIMEOUT);
-                r = (t > 0) ? 0 : t;
-                spin_lock(&sa_manager->wq.lock);
-                /* if we have nothing to wait for block */
-                if (r == -ENOENT) {
+                for (i = 0, count = 0; i < AMDGPU_MAX_RINGS; ++i)
+                        if (fences[i])
+                                fences[count++] = fences[i];
+
+                if (count) {
+                        spin_unlock(&sa_manager->wq.lock);
+                        t = fence_wait_any_timeout(fences, count, false,
+                                                   MAX_SCHEDULE_TIMEOUT);
+                        r = (t > 0) ? 0 : t;
+                        spin_lock(&sa_manager->wq.lock);
+                } else {
+                        /* if we have nothing to wait for block */
                         r = wait_event_interruptible_locked(
                                 sa_manager->wq,
                                 amdgpu_sa_event(sa_manager, size, align)
@@ -406,7 +393,7 @@ void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo,
         if (fence && !fence_is_signaled(fence)) {
                 uint32_t idx;
                 (*sa_bo)->fence = fence_get(fence);
-                idx = amdgpu_sa_get_ring_from_fence(fence);
+                idx = amdgpu_ring_from_fence(fence)->idx;
                 list_add_tail(&(*sa_bo)->flist, &sa_manager->flist[idx]);
         } else {
                 amdgpu_sa_bo_remove_locked(*sa_bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
index 2e946b2cad88..dcf4a8aca680 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c
@@ -54,7 +54,8 @@ static struct fence *amdgpu_sched_run_job(struct amd_sched_job *sched_job)
                 goto err;
         }
 
-        fence = amdgpu_fence_ref(job->ibs[job->num_ibs - 1].fence);
+        fence = job->ibs[job->num_ibs - 1].fence;
+        fence_get(&fence->base);
 
 err:
         if (job->free_job)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
index 4921de15b451..a6697fd05217 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c
@@ -87,6 +87,15 @@ static bool amdgpu_sync_test_owner(struct fence *f, void *owner)
         return false;
 }
 
+static void amdgpu_sync_keep_later(struct fence **keep, struct fence *fence)
+{
+        if (*keep && fence_is_later(*keep, fence))
+                return;
+
+        fence_put(*keep);
+        *keep = fence_get(fence);
+}
+
 /**
  * amdgpu_sync_fence - remember to sync to this fence
  *
@@ -99,35 +108,21 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
 {
         struct amdgpu_sync_entry *e;
         struct amdgpu_fence *fence;
-        struct amdgpu_fence *other;
-        struct fence *tmp, *later;
 
         if (!f)
                 return 0;
 
         if (amdgpu_sync_same_dev(adev, f) &&
-            amdgpu_sync_test_owner(f, AMDGPU_FENCE_OWNER_VM)) {
-                if (sync->last_vm_update) {
-                        tmp = sync->last_vm_update;
-                        BUG_ON(f->context != tmp->context);
-                        later = (f->seqno - tmp->seqno <= INT_MAX) ? f : tmp;
-                        sync->last_vm_update = fence_get(later);
-                        fence_put(tmp);
-                } else
-                        sync->last_vm_update = fence_get(f);
-        }
+            amdgpu_sync_test_owner(f, AMDGPU_FENCE_OWNER_VM))
+                amdgpu_sync_keep_later(&sync->last_vm_update, f);
 
         fence = to_amdgpu_fence(f);
         if (!fence || fence->ring->adev != adev) {
                 hash_for_each_possible(sync->fences, e, node, f->context) {
-                        struct fence *new;
                         if (unlikely(e->fence->context != f->context))
                                 continue;
-                        new = fence_get(fence_later(e->fence, f));
-                        if (new) {
-                                fence_put(e->fence);
-                                e->fence = new;
-                        }
+
+                        amdgpu_sync_keep_later(&e->fence, f);
                         return 0;
                 }
 
@@ -140,10 +135,7 @@ int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
                 return 0;
         }
 
-        other = sync->sync_to[fence->ring->idx];
-        sync->sync_to[fence->ring->idx] = amdgpu_fence_ref(
-                amdgpu_fence_later(fence, other));
-        amdgpu_fence_unref(&other);
+        amdgpu_sync_keep_later(&sync->sync_to[fence->ring->idx], f);
 
         return 0;
 }
@@ -199,8 +191,8 @@ int amdgpu_sync_resv(struct amdgpu_device *adev,
                          * for other VM updates and moves.
                          */
                         fence_owner = amdgpu_sync_get_owner(f);
-                        if ((owner != AMDGPU_FENCE_OWNER_MOVE) &&
-                            (fence_owner != AMDGPU_FENCE_OWNER_MOVE) &&
+                        if ((owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
+                            (fence_owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
                             ((owner == AMDGPU_FENCE_OWNER_VM) !=
                              (fence_owner == AMDGPU_FENCE_OWNER_VM)))
                                 continue;
@@ -262,11 +254,11 @@ int amdgpu_sync_wait(struct amdgpu_sync *sync)
                 return 0;
 
         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
-                struct amdgpu_fence *fence = sync->sync_to[i];
+                struct fence *fence = sync->sync_to[i];
                 if (!fence)
                         continue;
 
-                r = fence_wait(&fence->base, false);
+                r = fence_wait(fence, false);
                 if (r)
                         return r;
         }
@@ -291,9 +283,14 @@ int amdgpu_sync_rings(struct amdgpu_sync *sync,
         int i, r;
 
         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
-                struct amdgpu_fence *fence = sync->sync_to[i];
-                struct amdgpu_semaphore *semaphore;
                 struct amdgpu_ring *other = adev->rings[i];
+                struct amdgpu_semaphore *semaphore;
+                struct amdgpu_fence *fence;
+
+                if (!sync->sync_to[i])
+                        continue;
+
+                fence = to_amdgpu_fence(sync->sync_to[i]);
 
                 /* check if we really need to sync */
                 if (!amdgpu_fence_need_sync(fence, ring))
@@ -378,7 +375,7 @@ void amdgpu_sync_free(struct amdgpu_device *adev,
                 amdgpu_semaphore_free(adev, &sync->semaphores[i], fence);
 
         for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
-                amdgpu_fence_unref(&sync->sync_to[i]);
+                fence_put(sync->sync_to[i]);
 
         fence_put(sync->last_vm_update);
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 961d7265c286..76ecbaf72a2e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -111,7 +111,7 @@ TRACE_EVENT(amdgpu_vm_bo_unmap,
                       __entry->offset, __entry->flags)
 );
 
-TRACE_EVENT(amdgpu_vm_bo_update,
+DECLARE_EVENT_CLASS(amdgpu_vm_mapping,
             TP_PROTO(struct amdgpu_bo_va_mapping *mapping),
             TP_ARGS(mapping),
             TP_STRUCT__entry(
@@ -129,6 +129,16 @@ TRACE_EVENT(amdgpu_vm_bo_update,
                       __entry->soffset, __entry->eoffset, __entry->flags)
 );
 
+DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_update,
+            TP_PROTO(struct amdgpu_bo_va_mapping *mapping),
+            TP_ARGS(mapping)
+);
+
+DEFINE_EVENT(amdgpu_vm_mapping, amdgpu_vm_bo_mapping,
+            TP_PROTO(struct amdgpu_bo_va_mapping *mapping),
+            TP_ARGS(mapping)
+);
+
 TRACE_EVENT(amdgpu_vm_set_page,
             TP_PROTO(uint64_t pe, uint64_t addr, unsigned count,
                      uint32_t incr, uint32_t flags),
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 364cbe975332..81bb8e9fc26d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1041,7 +1041,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
         WARN_ON(ib->length_dw > num_dw);
         r = amdgpu_sched_ib_submit_kernel_helper(adev, ring, ib, 1,
                                                  &amdgpu_vm_free_job,
-                                                 AMDGPU_FENCE_OWNER_MOVE,
+                                                 AMDGPU_FENCE_OWNER_UNDEFINED,
                                                  fence);
         if (r)
                 goto error_free;
@@ -1072,6 +1072,11 @@ static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
         spin_lock(&glob->lru_lock);
         ret = drm_mm_dump_table(m, mm);
         spin_unlock(&glob->lru_lock);
+        if (ttm_pl == TTM_PL_VRAM)
+                seq_printf(m, "man size:%llu pages, ram usage:%luMB, vis usage:%luMB\n",
+                           adev->mman.bdev.man[ttm_pl].size,
+                           atomic64_read(&adev->vram_usage) >> 20,
+                           atomic64_read(&adev->vram_vis_usage) >> 20);
         return ret;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index d0312364d950..53f987aeeacf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -53,6 +53,7 @@
 #define FIRMWARE_TONGA          "amdgpu/tonga_uvd.bin"
 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_uvd.bin"
 #define FIRMWARE_FIJI           "amdgpu/fiji_uvd.bin"
+#define FIRMWARE_STONEY         "amdgpu/stoney_uvd.bin"
 
 /**
  * amdgpu_uvd_cs_ctx - Command submission parser context
@@ -83,6 +84,7 @@ MODULE_FIRMWARE(FIRMWARE_MULLINS);
 MODULE_FIRMWARE(FIRMWARE_TONGA);
 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
 MODULE_FIRMWARE(FIRMWARE_FIJI);
+MODULE_FIRMWARE(FIRMWARE_STONEY);
 
 static void amdgpu_uvd_note_usage(struct amdgpu_device *adev);
 static void amdgpu_uvd_idle_work_handler(struct work_struct *work);
@@ -124,6 +126,9 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev)
         case CHIP_CARRIZO:
                 fw_name = FIRMWARE_CARRIZO;
                 break;
+        case CHIP_STONEY:
+                fw_name = FIRMWARE_STONEY;
+                break;
         default:
                 return -EINVAL;
         }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 74f2038ac747..03f0c3bae516 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -49,6 +49,7 @@
 #define FIRMWARE_TONGA          "amdgpu/tonga_vce.bin"
 #define FIRMWARE_CARRIZO        "amdgpu/carrizo_vce.bin"
 #define FIRMWARE_FIJI           "amdgpu/fiji_vce.bin"
+#define FIRMWARE_STONEY         "amdgpu/stoney_vce.bin"
 
 #ifdef CONFIG_DRM_AMDGPU_CIK
 MODULE_FIRMWARE(FIRMWARE_BONAIRE);
@@ -60,6 +61,7 @@ MODULE_FIRMWARE(FIRMWARE_MULLINS);
 MODULE_FIRMWARE(FIRMWARE_TONGA);
 MODULE_FIRMWARE(FIRMWARE_CARRIZO);
 MODULE_FIRMWARE(FIRMWARE_FIJI);
+MODULE_FIRMWARE(FIRMWARE_STONEY);
 
 static void amdgpu_vce_idle_work_handler(struct work_struct *work);
 
@@ -106,6 +108,9 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size)
         case CHIP_FIJI:
                 fw_name = FIRMWARE_FIJI;
                 break;
+        case CHIP_STONEY:
+                fw_name = FIRMWARE_STONEY;
+                break;
 
         default:
                 return -EINVAL;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 53d551f2d839..633a32a48560 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -90,11 +90,9 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
         struct amdgpu_bo_list_entry *list;
         unsigned i, idx;
 
-        mutex_lock(&vm->mutex);
         list = drm_malloc_ab(vm->max_pde_used + 2,
                              sizeof(struct amdgpu_bo_list_entry));
         if (!list) {
-                mutex_unlock(&vm->mutex);
                 return NULL;
         }
 
@@ -119,7 +117,6 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
                 list[idx].tv.shared = true;
                 list_add(&list[idx++].tv.head, head);
         }
-        mutex_unlock(&vm->mutex);
 
         return list;
 }
@@ -138,7 +135,7 @@ struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev,
 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
                       struct amdgpu_sync *sync)
 {
-        struct amdgpu_fence *best[AMDGPU_MAX_RINGS] = {};
+        struct fence *best[AMDGPU_MAX_RINGS] = {};
         struct amdgpu_vm_id *vm_id = &vm->ids[ring->idx];
         struct amdgpu_device *adev = ring->adev;
 
@@ -147,15 +144,18 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
 
         /* check if the id is still valid */
         if (vm_id->id && vm_id->last_id_use &&
-            vm_id->last_id_use == adev->vm_manager.active[vm_id->id])
+            vm_id->last_id_use == adev->vm_manager.active[vm_id->id]) {
+                trace_amdgpu_vm_grab_id(vm_id->id, ring->idx);
                 return 0;
+        }
 
         /* we definately need to flush */
         vm_id->pd_gpu_addr = ~0ll;
 
         /* skip over VMID 0, since it is the system VM */
         for (i = 1; i < adev->vm_manager.nvm; ++i) {
-                struct amdgpu_fence *fence = adev->vm_manager.active[i];
+                struct fence *fence = adev->vm_manager.active[i];
+                struct amdgpu_ring *fring;
 
                 if (fence == NULL) {
                         /* found a free one */
@@ -164,21 +164,23 @@ int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring,
                         return 0;
                 }
 
-                if (amdgpu_fence_is_earlier(fence, best[fence->ring->idx])) {
-                        best[fence->ring->idx] = fence;
-                        choices[fence->ring == ring ? 0 : 1] = i;
+                fring = amdgpu_ring_from_fence(fence);
+                if (best[fring->idx] == NULL ||
+                    fence_is_later(best[fring->idx], fence)) {
+                        best[fring->idx] = fence;
+                        choices[fring == ring ? 0 : 1] = i;
                 }
         }
 
         for (i = 0; i < 2; ++i) {
                 if (choices[i]) {
-                        struct amdgpu_fence *fence;
+                        struct fence *fence;
 
                         fence  = adev->vm_manager.active[choices[i]];
                         vm_id->id = choices[i];
 
                         trace_amdgpu_vm_grab_id(choices[i], ring->idx);
-                        return amdgpu_sync_fence(ring->adev, sync, &fence->base);
+                        return amdgpu_sync_fence(ring->adev, sync, fence);
                 }
         }
 
@@ -247,11 +249,11 @@ void amdgpu_vm_fence(struct amdgpu_device *adev,
         unsigned ridx = fence->ring->idx;
         unsigned vm_id = vm->ids[ridx].id;
 
-        amdgpu_fence_unref(&adev->vm_manager.active[vm_id]);
-        adev->vm_manager.active[vm_id] = amdgpu_fence_ref(fence);
+        fence_put(adev->vm_manager.active[vm_id]);
+        adev->vm_manager.active[vm_id] = fence_get(&fence->base);
 
-        amdgpu_fence_unref(&vm->ids[ridx].last_id_use);
-        vm->ids[ridx].last_id_use = amdgpu_fence_ref(fence);
+        fence_put(vm->ids[ridx].last_id_use);
+        vm->ids[ridx].last_id_use = fence_get(&fence->base);
 }
 
 /**
@@ -852,6 +854,14 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
                         return r;
         }
 
+        if (trace_amdgpu_vm_bo_mapping_enabled()) {
+                list_for_each_entry(mapping, &bo_va->valids, list)
+                        trace_amdgpu_vm_bo_mapping(mapping);
+
+                list_for_each_entry(mapping, &bo_va->invalids, list)
+                        trace_amdgpu_vm_bo_mapping(mapping);
+        }
+
         spin_lock(&vm->status_lock);
         list_splice_init(&bo_va->invalids, &bo_va->valids);
         list_del_init(&bo_va->vm_status);
@@ -962,9 +972,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
         INIT_LIST_HEAD(&bo_va->invalids);
         INIT_LIST_HEAD(&bo_va->vm_status);
 
-        mutex_lock(&vm->mutex);
         list_add_tail(&bo_va->bo_list, &bo->va);
-        mutex_unlock(&vm->mutex);
 
         return bo_va;
 }
@@ -1017,8 +1025,6 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
                 return -EINVAL;
         }
 
-        mutex_lock(&vm->mutex);
-
         saddr /= AMDGPU_GPU_PAGE_SIZE;
         eaddr /= AMDGPU_GPU_PAGE_SIZE;
 
@@ -1032,14 +1038,14 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
                         tmp->it.start, tmp->it.last + 1);
                 amdgpu_bo_unreserve(bo_va->bo);
                 r = -EINVAL;
-                goto error_unlock;
+                goto error;
         }
 
         mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
         if (!mapping) {
                 amdgpu_bo_unreserve(bo_va->bo);
                 r = -ENOMEM;
-                goto error_unlock;
+                goto error;
         }
 
         INIT_LIST_HEAD(&mapping->list);
@@ -1071,9 +1077,6 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
                 if (vm->page_tables[pt_idx].bo)
                         continue;
 
-                /* drop mutex to allocate and clear page table */
-                mutex_unlock(&vm->mutex);
-
                 ww_mutex_lock(&resv->lock, NULL);
                 r = amdgpu_bo_create(adev, AMDGPU_VM_PTE_COUNT * 8,
                                      AMDGPU_GPU_PAGE_SIZE, true,
@@ -1090,32 +1093,19 @@ int amdgpu_vm_bo_map(struct amdgpu_device *adev,
                         goto error_free;
                 }
 
-                /* aquire mutex again */
-                mutex_lock(&vm->mutex);
-                if (vm->page_tables[pt_idx].bo) {
-                        /* someone else allocated the pt in the meantime */
-                        mutex_unlock(&vm->mutex);
-                        amdgpu_bo_unref(&pt);
-                        mutex_lock(&vm->mutex);
-                        continue;
-                }
-
                 vm->page_tables[pt_idx].addr = 0;
                 vm->page_tables[pt_idx].bo = pt;
         }
 
-        mutex_unlock(&vm->mutex);
         return 0;
 
 error_free:
-        mutex_lock(&vm->mutex);
         list_del(&mapping->list);
         interval_tree_remove(&mapping->it, &vm->va);
         trace_amdgpu_vm_bo_unmap(bo_va, mapping);
         kfree(mapping);
 
-error_unlock:
-        mutex_unlock(&vm->mutex);
+error:
         return r;
 }
 
@@ -1160,7 +1150,6 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
                 }
         }
 
-        mutex_lock(&vm->mutex);
         list_del(&mapping->list);
         interval_tree_remove(&mapping->it, &vm->va);
         trace_amdgpu_vm_bo_unmap(bo_va, mapping);
@@ -1169,7 +1158,6 @@ int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
                 list_add(&mapping->list, &vm->freed);
         else
                 kfree(mapping);
-        mutex_unlock(&vm->mutex);
         amdgpu_bo_unreserve(bo_va->bo);
 
         return 0;
@@ -1193,8 +1181,6 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
 
         list_del(&bo_va->bo_list);
 
-        mutex_lock(&vm->mutex);
-
         spin_lock(&vm->status_lock);
         list_del(&bo_va->vm_status);
         spin_unlock(&vm->status_lock);
@@ -1213,8 +1199,6 @@ void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
 
         fence_put(bo_va->last_pt_update);
         kfree(bo_va);
-
-        mutex_unlock(&vm->mutex);
 }
 
 /**
@@ -1332,7 +1316,7 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 
         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
                 fence_put(vm->ids[i].flushed_updates);
-                amdgpu_fence_unref(&vm->ids[i].last_id_use);
+                fence_put(vm->ids[i].last_id_use);
         }
 
         mutex_destroy(&vm->mutex);
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.c b/drivers/gpu/drm/amd/amdgpu/atom.c
index a0346a90d805..1b50e6c13fb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.c
+++ b/drivers/gpu/drm/amd/amdgpu/atom.c
@@ -685,6 +685,27 @@ static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
         }
 }
 
+static void atom_op_div32(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint64_t val64;
+        uint8_t attr = U8((*ptr)++);
+        uint32_t dst, src;
+        SDEBUG("   src1: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
+        SDEBUG("   src2: ");
+        src = atom_get_src(ctx, attr, ptr);
+        if (src != 0) {
+                val64 = dst;
+                val64 |= ((uint64_t)ctx->ctx->divmul[1]) << 32;
+                do_div(val64, src);
+                ctx->ctx->divmul[0] = lower_32_bits(val64);
+                ctx->ctx->divmul[1] = upper_32_bits(val64);
+        } else {
+                ctx->ctx->divmul[0] = 0;
+                ctx->ctx->divmul[1] = 0;
+        }
+}
+
 static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg)
 {
         /* functionally, a nop */
@@ -788,6 +809,20 @@ static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg)
         ctx->ctx->divmul[0] = dst * src;
 }
 
+static void atom_op_mul32(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint64_t val64;
+        uint8_t attr = U8((*ptr)++);
+        uint32_t dst, src;
+        SDEBUG("   src1: ");
+        dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
+        SDEBUG("   src2: ");
+        src = atom_get_src(ctx, attr, ptr);
+        val64 = (uint64_t)dst * (uint64_t)src;
+        ctx->ctx->divmul[0] = lower_32_bits(val64);
+        ctx->ctx->divmul[1] = upper_32_bits(val64);
+}
+
 static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg)
 {
         /* nothing */
@@ -1022,7 +1057,15 @@ static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg)
 
 static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg)
 {
-        printk(KERN_INFO "unimplemented!\n");
+        uint8_t val = U8((*ptr)++);
+        SDEBUG("DEBUG output: 0x%02X\n", val);
+}
+
+static void atom_op_processds(atom_exec_context *ctx, int *ptr, int arg)
+{
+        uint16_t val = U16(*ptr);
+        (*ptr) += val + 2;
+        SDEBUG("PROCESSDS output: 0x%02X\n", val);
 }
 
 static struct {
@@ -1151,7 +1194,13 @@ static struct {
         atom_op_shr, ATOM_ARG_FB}, {
         atom_op_shr, ATOM_ARG_PLL}, {
         atom_op_shr, ATOM_ARG_MC}, {
-atom_op_debug, 0},};
+        atom_op_debug, 0}, {
+        atom_op_processds, 0}, {
+        atom_op_mul32, ATOM_ARG_PS}, {
+        atom_op_mul32, ATOM_ARG_WS}, {
+        atom_op_div32, ATOM_ARG_PS}, {
+        atom_op_div32, ATOM_ARG_WS},
+};
 
 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/atom.h b/drivers/gpu/drm/amd/amdgpu/atom.h
index 09d0f8230708..fece8f45dc7a 100644
--- a/drivers/gpu/drm/amd/amdgpu/atom.h
+++ b/drivers/gpu/drm/amd/amdgpu/atom.h
@@ -60,7 +60,7 @@
 #define ATOM_CT_PS_MASK         0x7F
 #define ATOM_CT_CODE_PTR        6
 
-#define ATOM_OP_CNT             123
+#define ATOM_OP_CNT             127
 #define ATOM_OP_EOT             91
 
 #define ATOM_CASE_MAGIC         0x63
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 9ea9de457da3..5f712ceddf08 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -96,7 +96,7 @@ static int cik_sdma_init_microcode(struct amdgpu_device *adev)
 {
         const char *chip_name;
         char fw_name[30];
-        int err, i;
+        int err = 0, i;
 
         DRM_DEBUG("\n");
 
@@ -119,24 +119,24 @@ static int cik_sdma_init_microcode(struct amdgpu_device *adev)
         default: BUG();
         }
 
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
+        for (i = 0; i < adev->sdma.num_instances; i++) {
                 if (i == 0)
                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
                 else
                         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma1.bin", chip_name);
-                err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
+                err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
                 if (err)
                         goto out;
-                err = amdgpu_ucode_validate(adev->sdma[i].fw);
+                err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
         }
 out:
         if (err) {
                 printk(KERN_ERR
                        "cik_sdma: Failed to load firmware \"%s\"\n",
                        fw_name);
-                for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
-                        release_firmware(adev->sdma[i].fw);
-                        adev->sdma[i].fw = NULL;
+                for (i = 0; i < adev->sdma.num_instances; i++) {
+                        release_firmware(adev->sdma.instance[i].fw);
+                        adev->sdma.instance[i].fw = NULL;
                 }
         }
         return err;
@@ -168,7 +168,7 @@ static uint32_t cik_sdma_ring_get_rptr(struct amdgpu_ring *ring)
 static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
-        u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1;
+        u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 
         return (RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) & 0x3fffc) >> 2;
 }
@@ -183,14 +183,14 @@ static uint32_t cik_sdma_ring_get_wptr(struct amdgpu_ring *ring)
 static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
-        u32 me = (ring == &adev->sdma[0].ring) ? 0 : 1;
+        u32 me = (ring == &adev->sdma.instance[0].ring) ? 0 : 1;
 
         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc);
 }
 
 static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 {
-        struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ring);
+        struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
         int i;
 
         for (i = 0; i < count; i++)
@@ -248,7 +248,7 @@ static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring)
                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
         u32 ref_and_mask;
 
-        if (ring == &ring->adev->sdma[0].ring)
+        if (ring == &ring->adev->sdma.instance[0].ring)
                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
         else
                 ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
@@ -327,8 +327,8 @@ static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring *ring,
  */
 static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
 {
-        struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
-        struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
+        struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
+        struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
         u32 rb_cntl;
         int i;
 
@@ -336,7 +336,7 @@ static void cik_sdma_gfx_stop(struct amdgpu_device *adev)
             (adev->mman.buffer_funcs_ring == sdma1))
                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
+        for (i = 0; i < adev->sdma.num_instances; i++) {
                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
                 rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK;
                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
@@ -376,7 +376,7 @@ static void cik_sdma_enable(struct amdgpu_device *adev, bool enable)
                 cik_sdma_rlc_stop(adev);
         }
 
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
+        for (i = 0; i < adev->sdma.num_instances; i++) {
                 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
                 if (enable)
                         me_cntl &= ~SDMA0_F32_CNTL__HALT_MASK;
@@ -402,8 +402,8 @@ static int cik_sdma_gfx_resume(struct amdgpu_device *adev)
         u32 wb_offset;
         int i, j, r;
 
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
-                ring = &adev->sdma[i].ring;
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                ring = &adev->sdma.instance[i].ring;
                 wb_offset = (ring->rptr_offs * 4);
 
                 mutex_lock(&adev->srbm_mutex);
@@ -502,26 +502,25 @@ static int cik_sdma_load_microcode(struct amdgpu_device *adev)
         u32 fw_size;
         int i, j;
 
-        if (!adev->sdma[0].fw || !adev->sdma[1].fw)
-                return -EINVAL;
-
         /* halt the MEs */
         cik_sdma_enable(adev, false);
 
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
-                hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                if (!adev->sdma.instance[i].fw)
+                        return -EINVAL;
+                hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
-                adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
-                adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
-                if (adev->sdma[i].feature_version >= 20)
-                        adev->sdma[i].burst_nop = true;
+                adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
+                adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
+                if (adev->sdma.instance[i].feature_version >= 20)
+                        adev->sdma.instance[i].burst_nop = true;
                 fw_data = (const __le32 *)
-                        (adev->sdma[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+                        (adev->sdma.instance[i].fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
                 for (j = 0; j < fw_size; j++)
                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
-                WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
+                WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
         }
 
         return 0;
@@ -830,7 +829,7 @@ static void cik_sdma_vm_set_pte_pde(struct amdgpu_ib *ib,
  */
 static void cik_sdma_vm_pad_ib(struct amdgpu_ib *ib)
 {
-        struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ib->ring);
+        struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);
         u32 pad_count;
         int i;
 
@@ -934,6 +933,8 @@ static int cik_sdma_early_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+        adev->sdma.num_instances = SDMA_MAX_INSTANCE;
+
         cik_sdma_set_ring_funcs(adev);
         cik_sdma_set_irq_funcs(adev);
         cik_sdma_set_buffer_funcs(adev);
@@ -946,7 +947,7 @@ static int cik_sdma_sw_init(void *handle)
 {
         struct amdgpu_ring *ring;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-        int r;
+        int r, i;
 
         r = cik_sdma_init_microcode(adev);
         if (r) {
@@ -955,43 +956,33 @@ static int cik_sdma_sw_init(void *handle)
         }
 
         /* SDMA trap event */
-        r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
+        r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
         if (r)
                 return r;
 
         /* SDMA Privileged inst */
-        r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
+        r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
         if (r)
                 return r;
 
         /* SDMA Privileged inst */
-        r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
+        r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
         if (r)
                 return r;
 
-        ring = &adev->sdma[0].ring;
-        ring->ring_obj = NULL;
-
-        ring = &adev->sdma[1].ring;
-        ring->ring_obj = NULL;
-
-        ring = &adev->sdma[0].ring;
-        sprintf(ring->name, "sdma0");
-        r = amdgpu_ring_init(adev, ring, 256 * 1024,
-                             SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
-                             &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
-                             AMDGPU_RING_TYPE_SDMA);
-        if (r)
-                return r;
-
-        ring = &adev->sdma[1].ring;
-        sprintf(ring->name, "sdma1");
-        r = amdgpu_ring_init(adev, ring, 256 * 1024,
-                             SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
-                             &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
-                             AMDGPU_RING_TYPE_SDMA);
-        if (r)
-                return r;
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                ring = &adev->sdma.instance[i].ring;
+                ring->ring_obj = NULL;
+                sprintf(ring->name, "sdma%d", i);
+                r = amdgpu_ring_init(adev, ring, 256 * 1024,
+                                     SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0), 0xf,
+                                     &adev->sdma.trap_irq,
+                                     (i == 0) ?
+                                     AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
+                                     AMDGPU_RING_TYPE_SDMA);
+                if (r)
+                        return r;
+        }
 
         return r;
 }
@@ -999,9 +990,10 @@ static int cik_sdma_sw_init(void *handle)
 static int cik_sdma_sw_fini(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        int i;
 
-        amdgpu_ring_fini(&adev->sdma[0].ring);
-        amdgpu_ring_fini(&adev->sdma[1].ring);
+        for (i = 0; i < adev->sdma.num_instances; i++)
+                amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 
         return 0;
 }
@@ -1078,7 +1070,7 @@ static void cik_sdma_print_status(void *handle)
         dev_info(adev->dev, "CIK SDMA registers\n");
         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
                  RREG32(mmSRBM_STATUS2));
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
+        for (i = 0; i < adev->sdma.num_instances; i++) {
                 dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
                          i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
                 dev_info(adev->dev, "  SDMA%d_ME_CNTL=0x%08X\n",
@@ -1223,7 +1215,7 @@ static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
         case 0:
                 switch (queue_id) {
                 case 0:
-                        amdgpu_fence_process(&adev->sdma[0].ring);
+                        amdgpu_fence_process(&adev->sdma.instance[0].ring);
                         break;
                 case 1:
                         /* XXX compute */
@@ -1236,7 +1228,7 @@ static int cik_sdma_process_trap_irq(struct amdgpu_device *adev,
         case 1:
                 switch (queue_id) {
                 case 0:
-                        amdgpu_fence_process(&adev->sdma[1].ring);
+                        amdgpu_fence_process(&adev->sdma.instance[1].ring);
                         break;
                 case 1:
                         /* XXX compute */
@@ -1298,24 +1290,6 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = {
         .set_powergating_state = cik_sdma_set_powergating_state,
 };
 
-/**
- * cik_sdma_ring_is_lockup - Check if the DMA engine is locked up
- *
- * @ring: amdgpu_ring structure holding ring information
- *
- * Check if the async DMA engine is locked up (CIK).
- * Returns true if the engine appears to be locked up, false if not.
- */
-static bool cik_sdma_ring_is_lockup(struct amdgpu_ring *ring)
-{
-
-        if (cik_sdma_is_idle(ring->adev)) {
-                amdgpu_ring_lockup_update(ring);
-                return false;
-        }
-        return amdgpu_ring_test_lockup(ring);
-}
-
 static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
         .get_rptr = cik_sdma_ring_get_rptr,
         .get_wptr = cik_sdma_ring_get_wptr,
@@ -1328,14 +1302,15 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = {
         .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush,
         .test_ring = cik_sdma_ring_test_ring,
         .test_ib = cik_sdma_ring_test_ib,
-        .is_lockup = cik_sdma_ring_is_lockup,
         .insert_nop = cik_sdma_ring_insert_nop,
 };
 
 static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev)
 {
-        adev->sdma[0].ring.funcs = &cik_sdma_ring_funcs;
-        adev->sdma[1].ring.funcs = &cik_sdma_ring_funcs;
+        int i;
+
+        for (i = 0; i < adev->sdma.num_instances; i++)
+                adev->sdma.instance[i].ring.funcs = &cik_sdma_ring_funcs;
 }
 
 static const struct amdgpu_irq_src_funcs cik_sdma_trap_irq_funcs = {
@@ -1349,9 +1324,9 @@ static const struct amdgpu_irq_src_funcs cik_sdma_illegal_inst_irq_funcs = {
 
 static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev)
 {
-        adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
-        adev->sdma_trap_irq.funcs = &cik_sdma_trap_irq_funcs;
-        adev->sdma_illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
+        adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
+        adev->sdma.trap_irq.funcs = &cik_sdma_trap_irq_funcs;
+        adev->sdma.illegal_inst_irq.funcs = &cik_sdma_illegal_inst_irq_funcs;
 }
 
 /**
@@ -1416,7 +1391,7 @@ static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
 {
         if (adev->mman.buffer_funcs == NULL) {
                 adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
-                adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
+                adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
         }
 }
 
@@ -1431,7 +1406,7 @@ static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
 {
         if (adev->vm_manager.vm_pte_funcs == NULL) {
                 adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
-                adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
+                adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
                 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
         }
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index 2e3373ed4c94..8035d4d6a4f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -1264,6 +1264,7 @@ static void cz_apply_state_adjust_rules(struct amdgpu_device *adev,
 
 static int cz_dpm_enable(struct amdgpu_device *adev)
 {
+        const char *chip_name;
         int ret = 0;
 
         /* renable will hang up SMU, so check first */
@@ -1272,21 +1273,33 @@ static int cz_dpm_enable(struct amdgpu_device *adev)
 
         cz_program_voting_clients(adev);
 
+        switch (adev->asic_type) {
+        case CHIP_CARRIZO:
+                chip_name = "carrizo";
+                break;
+        case CHIP_STONEY:
+                chip_name = "stoney";
+                break;
+        default:
+                BUG();
+        }
+
+
         ret = cz_start_dpm(adev);
         if (ret) {
-                DRM_ERROR("Carrizo DPM enable failed\n");
+                DRM_ERROR("%s DPM enable failed\n", chip_name);
                 return -EINVAL;
         }
 
         ret = cz_program_bootup_state(adev);
         if (ret) {
-                DRM_ERROR("Carrizo bootup state program failed\n");
+                DRM_ERROR("%s bootup state program failed\n", chip_name);
                 return -EINVAL;
         }
 
         ret = cz_enable_didt(adev, true);
         if (ret) {
-                DRM_ERROR("Carrizo enable di/dt failed\n");
+                DRM_ERROR("%s enable di/dt failed\n", chip_name);
                 return -EINVAL;
         }
 
@@ -1353,7 +1366,7 @@ static int cz_dpm_disable(struct amdgpu_device *adev)
 
         ret = cz_enable_didt(adev, false);
         if (ret) {
-                DRM_ERROR("Carrizo disable di/dt failed\n");
+                DRM_ERROR("disable di/dt failed\n");
                 return -EINVAL;
         }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_smc.c b/drivers/gpu/drm/amd/amdgpu/cz_smc.c
index e33180d3314a..ac7fee7b7eca 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_smc.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_smc.c
@@ -312,13 +312,16 @@ int cz_smu_start(struct amdgpu_device *adev)
                                 UCODE_ID_CP_MEC_JT1_MASK |
                                 UCODE_ID_CP_MEC_JT2_MASK;
 
+        if (adev->asic_type == CHIP_STONEY)
+                fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);
+
         cz_smu_request_load_fw(adev);
         ret = cz_smu_check_fw_load_finish(adev, fw_to_check);
         if (ret)
                 return ret;
 
         /* manually load MEC firmware for CZ */
-        if (adev->asic_type == CHIP_CARRIZO) {
+        if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
                 ret = cz_load_mec_firmware(adev);
                 if (ret) {
                         dev_err(adev->dev, "(%d) Mec Firmware load failed\n", ret);
@@ -336,6 +339,9 @@ int cz_smu_start(struct amdgpu_device *adev)
                                 AMDGPU_CPMEC2_UCODE_LOADED |
                                 AMDGPU_CPRLC_UCODE_LOADED;
 
+        if (adev->asic_type == CHIP_STONEY)
+                adev->smu.fw_flags &= ~(AMDGPU_SDMA1_UCODE_LOADED | AMDGPU_CPMEC2_UCODE_LOADED);
+
         return ret;
 }
 
@@ -601,8 +607,13 @@ static int cz_smu_construct_toc_for_vddgfx_exit(struct amdgpu_device *adev)
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
                 cz_smu_populate_single_ucode_load_task(adev,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
-                cz_smu_populate_single_ucode_load_task(adev,
+                if (adev->asic_type == CHIP_STONEY) {
+                        cz_smu_populate_single_ucode_load_task(adev,
+                                CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
+                } else {
+                        cz_smu_populate_single_ucode_load_task(adev,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
+                }
                 cz_smu_populate_single_ucode_load_task(adev,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);
         }
@@ -642,8 +653,13 @@ static int cz_smu_construct_toc_for_bootup(struct amdgpu_device *adev)
         if (adev->firmware.smu_load) {
                 cz_smu_populate_single_ucode_load_task(adev,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
-                cz_smu_populate_single_ucode_load_task(adev,
+                if (adev->asic_type == CHIP_STONEY) {
+                        cz_smu_populate_single_ucode_load_task(adev,
+                                CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);
+                } else {
+                        cz_smu_populate_single_ucode_load_task(adev,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);
+                }
                 cz_smu_populate_single_ucode_load_task(adev,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);
                 cz_smu_populate_single_ucode_load_task(adev,
@@ -652,8 +668,13 @@ static int cz_smu_construct_toc_for_bootup(struct amdgpu_device *adev)
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);
                 cz_smu_populate_single_ucode_load_task(adev,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
-                cz_smu_populate_single_ucode_load_task(adev,
+                if (adev->asic_type == CHIP_STONEY) {
+                        cz_smu_populate_single_ucode_load_task(adev,
+                                CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);
+                } else {
+                        cz_smu_populate_single_ucode_load_task(adev,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);
+                }
                 cz_smu_populate_single_ucode_load_task(adev,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);
         }
@@ -888,10 +909,18 @@ int cz_smu_init(struct amdgpu_device *adev)
                                 CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
                                 &priv->driver_buffer[priv->driver_buffer_length++]))
                         goto smu_init_failed;
-                if (cz_smu_populate_single_firmware_entry(adev,
-                                CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
-                                &priv->driver_buffer[priv->driver_buffer_length++]))
-                        goto smu_init_failed;
+
+                if (adev->asic_type == CHIP_STONEY) {
+                        if (cz_smu_populate_single_firmware_entry(adev,
+                                        CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,
+                                        &priv->driver_buffer[priv->driver_buffer_length++]))
+                                goto smu_init_failed;
+                } else {
+                        if (cz_smu_populate_single_firmware_entry(adev,
+                                        CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,
+                                        &priv->driver_buffer[priv->driver_buffer_length++]))
+                                goto smu_init_failed;
+                }
                 if (cz_smu_populate_single_firmware_entry(adev,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,
                                 &priv->driver_buffer[priv->driver_buffer_length++]))
@@ -908,10 +937,17 @@ int cz_smu_init(struct amdgpu_device *adev)
                                 CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
                                 &priv->driver_buffer[priv->driver_buffer_length++]))
                         goto smu_init_failed;
-                if (cz_smu_populate_single_firmware_entry(adev,
-                                CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
-                                &priv->driver_buffer[priv->driver_buffer_length++]))
-                        goto smu_init_failed;
+                if (adev->asic_type == CHIP_STONEY) {
+                        if (cz_smu_populate_single_firmware_entry(adev,
+                                        CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,
+                                        &priv->driver_buffer[priv->driver_buffer_length++]))
+                                goto smu_init_failed;
+                } else {
+                        if (cz_smu_populate_single_firmware_entry(adev,
+                                        CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,
+                                        &priv->driver_buffer[priv->driver_buffer_length++]))
+                                goto smu_init_failed;
+                }
                 if (cz_smu_populate_single_firmware_entry(adev,
                                 CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,
                                 &priv->driver_buffer[priv->driver_buffer_length++]))
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index d4c82b625727..cb0f7747e3dc 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -280,46 +280,22 @@ static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
  * @crtc_id: crtc to cleanup pageflip on
  * @crtc_base: new address of the crtc (GPU MC address)
  *
- * Does the actual pageflip (evergreen+).
- * During vblank we take the crtc lock and wait for the update_pending
- * bit to go high, when it does, we release the lock, and allow the
- * double buffered update to take place.
- * Returns the current update pending status.
+ * Triggers the actual pageflip by updating the primary
+ * surface base address.
  */
 static void dce_v10_0_page_flip(struct amdgpu_device *adev,
                               int crtc_id, u64 crtc_base)
 {
         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
-        u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset);
-        int i;
-
-        /* Lock the graphics update lock */
-        tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
-        WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
-
-        /* update the scanout addresses */
-        WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
-               upper_32_bits(crtc_base));
-        WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
-               lower_32_bits(crtc_base));
 
+        /* update the primary scanout address */
         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
                upper_32_bits(crtc_base));
+        /* writing to the low address triggers the update */
         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
                lower_32_bits(crtc_base));
-
-        /* Wait for update_pending to go high. */
-        for (i = 0; i < adev->usec_timeout; i++) {
-                if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) &
-                                GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK)
-                        break;
-                udelay(1);
-        }
-        DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
-
-        /* Unlock the lock, so double-buffering can take place inside vblank */
-        tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
-        WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
+        /* post the write */
+        RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 }
 
 static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
@@ -2517,26 +2493,19 @@ static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
         struct amdgpu_device *adev = crtc->dev->dev_private;
         u32 tmp;
 
+        WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
+               upper_32_bits(amdgpu_crtc->cursor_addr));
+        WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
+               lower_32_bits(amdgpu_crtc->cursor_addr));
+
         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 }
 
-static void dce_v10_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
-                              uint64_t gpu_addr)
-{
-        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-        struct amdgpu_device *adev = crtc->dev->dev_private;
-
-        WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
-               upper_32_bits(gpu_addr));
-        WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
-               lower_32_bits(gpu_addr));
-}
-
-static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
-                                     int x, int y)
+static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
+                                        int x, int y)
 {
         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
         struct amdgpu_device *adev = crtc->dev->dev_private;
@@ -2556,26 +2525,40 @@ static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
                 y = 0;
         }
 
-        dce_v10_0_lock_cursor(crtc, true);
         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
-        dce_v10_0_lock_cursor(crtc, false);
+
+        amdgpu_crtc->cursor_x = x;
+        amdgpu_crtc->cursor_y = y;
 
         return 0;
 }
 
-static int dce_v10_0_crtc_cursor_set(struct drm_crtc *crtc,
-                                    struct drm_file *file_priv,
-                                    uint32_t handle,
-                                    uint32_t width,
-                                    uint32_t height)
+static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
+                                      int x, int y)
+{
+        int ret;
+
+        dce_v10_0_lock_cursor(crtc, true);
+        ret = dce_v10_0_cursor_move_locked(crtc, x, y);
+        dce_v10_0_lock_cursor(crtc, false);
+
+        return ret;
+}
+
+static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
+                                      struct drm_file *file_priv,
+                                      uint32_t handle,
+                                      uint32_t width,
+                                      uint32_t height,
+                                      int32_t hot_x,
+                                      int32_t hot_y)
 {
         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
         struct drm_gem_object *obj;
-        struct amdgpu_bo *robj;
-        uint64_t gpu_addr;
+        struct amdgpu_bo *aobj;
         int ret;
 
         if (!handle) {
@@ -2597,41 +2580,71 @@ static int dce_v10_0_crtc_cursor_set(struct drm_crtc *crtc,
                 return -ENOENT;
         }
 
-        robj = gem_to_amdgpu_bo(obj);
-        ret = amdgpu_bo_reserve(robj, false);
-        if (unlikely(ret != 0))
-                goto fail;
-        ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM,
-                                       0, 0, &gpu_addr);
-        amdgpu_bo_unreserve(robj);
-        if (ret)
-                goto fail;
+        aobj = gem_to_amdgpu_bo(obj);
+        ret = amdgpu_bo_reserve(aobj, false);
+        if (ret != 0) {
+                drm_gem_object_unreference_unlocked(obj);
+                return ret;
+        }
+
+        ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
+        amdgpu_bo_unreserve(aobj);
+        if (ret) {
+                DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
+                drm_gem_object_unreference_unlocked(obj);
+                return ret;
+        }
 
         amdgpu_crtc->cursor_width = width;
         amdgpu_crtc->cursor_height = height;
 
         dce_v10_0_lock_cursor(crtc, true);
-        dce_v10_0_set_cursor(crtc, obj, gpu_addr);
+
+        if (hot_x != amdgpu_crtc->cursor_hot_x ||
+            hot_y != amdgpu_crtc->cursor_hot_y) {
+                int x, y;
+
+                x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
+                y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
+
+                dce_v10_0_cursor_move_locked(crtc, x, y);
+
+                amdgpu_crtc->cursor_hot_x = hot_x;
+                amdgpu_crtc->cursor_hot_y = hot_y;
+        }
+
         dce_v10_0_show_cursor(crtc);
         dce_v10_0_lock_cursor(crtc, false);
 
 unpin:
         if (amdgpu_crtc->cursor_bo) {
-                robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
-                ret = amdgpu_bo_reserve(robj, false);
+                struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
+                ret = amdgpu_bo_reserve(aobj, false);
                 if (likely(ret == 0)) {
-                        amdgpu_bo_unpin(robj);
-                        amdgpu_bo_unreserve(robj);
+                        amdgpu_bo_unpin(aobj);
+                        amdgpu_bo_unreserve(aobj);
                 }
                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
         }
 
         amdgpu_crtc->cursor_bo = obj;
         return 0;
-fail:
-        drm_gem_object_unreference_unlocked(obj);
+}
 
-        return ret;
+static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
+{
+        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
+
+        if (amdgpu_crtc->cursor_bo) {
+                dce_v10_0_lock_cursor(crtc, true);
+
+                dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
+                                             amdgpu_crtc->cursor_y);
+
+                dce_v10_0_show_cursor(crtc);
+
+                dce_v10_0_lock_cursor(crtc, false);
+        }
 }
 
 static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
@@ -2659,7 +2672,7 @@ static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
 }
 
 static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
-        .cursor_set = dce_v10_0_crtc_cursor_set,
+        .cursor_set2 = dce_v10_0_crtc_cursor_set2,
         .cursor_move = dce_v10_0_crtc_cursor_move,
         .gamma_set = dce_v10_0_crtc_gamma_set,
         .set_config = amdgpu_crtc_set_config,
@@ -2793,6 +2806,7 @@ static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
         dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
         amdgpu_atombios_crtc_scaler_setup(crtc);
+        dce_v10_0_cursor_reset(crtc);
         /* update the hw version fpr dpm */
         amdgpu_crtc->hw_mode = *adjusted_mode;
 
@@ -3071,24 +3085,18 @@ static int dce_v10_0_suspend(void *handle)
 
         amdgpu_atombios_scratch_regs_save(adev);
 
-        dce_v10_0_hpd_fini(adev);
-
-        dce_v10_0_pageflip_interrupt_fini(adev);
-
-        return 0;
+        return dce_v10_0_hw_fini(handle);
 }
 
 static int dce_v10_0_resume(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        int ret;
 
-        dce_v10_0_init_golden_registers(adev);
+        ret = dce_v10_0_hw_init(handle);
 
         amdgpu_atombios_scratch_regs_restore(adev);
 
-        /* init dig PHYs, disp eng pll */
-        amdgpu_atombios_encoder_init_dig(adev);
-        amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
         /* turn on the BL */
         if (adev->mode_info.bl_encoder) {
                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
@@ -3097,12 +3105,7 @@ static int dce_v10_0_resume(void *handle)
                                                     bl_level);
         }
 
-        /* initialize hpd */
-        dce_v10_0_hpd_init(adev);
-
-        dce_v10_0_pageflip_interrupt_init(adev);
-
-        return 0;
+        return ret;
 }
 
 static bool dce_v10_0_is_idle(void *handle)
@@ -3294,37 +3297,20 @@ static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
                                             unsigned type,
                                             enum amdgpu_interrupt_state state)
 {
-        u32 reg, reg_block;
-        /* now deal with page flip IRQ */
-        switch (type) {
-                case AMDGPU_PAGEFLIP_IRQ_D1:
-                        reg_block = CRTC0_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D2:
-                        reg_block = CRTC1_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D3:
-                        reg_block = CRTC2_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D4:
-                        reg_block = CRTC3_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D5:
-                        reg_block = CRTC4_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D6:
-                        reg_block = CRTC5_REGISTER_OFFSET;
-                        break;
-                default:
-                        DRM_ERROR("invalid pageflip crtc %d\n", type);
-                        return -EINVAL;
+        u32 reg;
+
+        if (type >= adev->mode_info.num_crtc) {
+                DRM_ERROR("invalid pageflip crtc %d\n", type);
+                return -EINVAL;
         }
 
-        reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block);
+        reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
         if (state == AMDGPU_IRQ_STATE_DISABLE)
-                WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
+                WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
+                       reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
         else
-                WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
+                WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
+                       reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
 
         return 0;
 }
@@ -3333,7 +3319,6 @@ static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
                                   struct amdgpu_irq_src *source,
                                   struct amdgpu_iv_entry *entry)
 {
-        int reg_block;
         unsigned long flags;
         unsigned crtc_id;
         struct amdgpu_crtc *amdgpu_crtc;
@@ -3342,33 +3327,15 @@ static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
         crtc_id = (entry->src_id - 8) >> 1;
         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 
-        /* ack the interrupt */
-        switch(crtc_id){
-                case AMDGPU_PAGEFLIP_IRQ_D1:
-                        reg_block = CRTC0_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D2:
-                        reg_block = CRTC1_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D3:
-                        reg_block = CRTC2_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D4:
-                        reg_block = CRTC3_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D5:
-                        reg_block = CRTC4_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D6:
-                        reg_block = CRTC5_REGISTER_OFFSET;
-                        break;
-                default:
-                        DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
-                        return -EINVAL;
+        if (crtc_id >= adev->mode_info.num_crtc) {
+                DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
+                return -EINVAL;
         }
 
-        if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
-                WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
+        if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
+            GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
+                WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
+                       GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
 
         /* IRQ could occur when in initial stage */
         if (amdgpu_crtc == NULL)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 7e1cf5e4eebf..5af3721851d6 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -126,6 +126,13 @@ static const u32 cz_mgcg_cgcg_init[] =
         mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 };
 
+static const u32 stoney_golden_settings_a11[] =
+{
+        mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
+        mmFBC_MISC, 0x1f311fff, 0x14302000,
+};
+
+
 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
 {
         switch (adev->asic_type) {
@@ -137,6 +144,11 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
                                                  cz_golden_settings_a11,
                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
                 break;
+        case CHIP_STONEY:
+                amdgpu_program_register_sequence(adev,
+                                                 stoney_golden_settings_a11,
+                                                 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
+                break;
         default:
                 break;
         }
@@ -258,46 +270,22 @@ static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
  * @crtc_id: crtc to cleanup pageflip on
  * @crtc_base: new address of the crtc (GPU MC address)
  *
- * Does the actual pageflip (evergreen+).
- * During vblank we take the crtc lock and wait for the update_pending
- * bit to go high, when it does, we release the lock, and allow the
- * double buffered update to take place.
- * Returns the current update pending status.
+ * Triggers the actual pageflip by updating the primary
+ * surface base address.
  */
 static void dce_v11_0_page_flip(struct amdgpu_device *adev,
                               int crtc_id, u64 crtc_base)
 {
         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
-        u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset);
-        int i;
-
-        /* Lock the graphics update lock */
-        tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 1);
-        WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
 
         /* update the scanout addresses */
-        WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
-               upper_32_bits(crtc_base));
-        WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
-               lower_32_bits(crtc_base));
-
         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
                upper_32_bits(crtc_base));
+        /* writing to the low address triggers the update */
         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
                lower_32_bits(crtc_base));
-
-        /* Wait for update_pending to go high. */
-        for (i = 0; i < adev->usec_timeout; i++) {
-                if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) &
-                                GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK)
-                        break;
-                udelay(1);
-        }
-        DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
-
-        /* Unlock the lock, so double-buffering can take place inside vblank */
-        tmp = REG_SET_FIELD(tmp, GRPH_UPDATE, GRPH_UPDATE_LOCK, 0);
-        WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);  
+        /* post the write */
+        RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 }
 
 static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
@@ -2443,7 +2431,7 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
 
         /* XXX need to determine what plls are available on each DCE11 part */
         pll_in_use = amdgpu_pll_get_use_mask(crtc);
-        if (adev->asic_type == CHIP_CARRIZO) {
+        if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
                 if (!(pll_in_use & (1 << ATOM_PPLL1)))
                         return ATOM_PPLL1;
                 if (!(pll_in_use & (1 << ATOM_PPLL0)))
@@ -2494,26 +2482,19 @@ static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
         struct amdgpu_device *adev = crtc->dev->dev_private;
         u32 tmp;
 
+        WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
+               upper_32_bits(amdgpu_crtc->cursor_addr));
+        WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
+               lower_32_bits(amdgpu_crtc->cursor_addr));
+
         tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
         tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
 }
 
-static void dce_v11_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
-                              uint64_t gpu_addr)
-{
-        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-        struct amdgpu_device *adev = crtc->dev->dev_private;
-
-        WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
-               upper_32_bits(gpu_addr));
-        WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
-               lower_32_bits(gpu_addr));
-}
-
-static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
-                                     int x, int y)
+static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
+                                        int x, int y)
 {
         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
         struct amdgpu_device *adev = crtc->dev->dev_private;
@@ -2533,26 +2514,40 @@ static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
                 y = 0;
         }
 
-        dce_v11_0_lock_cursor(crtc, true);
         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
-        dce_v11_0_lock_cursor(crtc, false);
+
+        amdgpu_crtc->cursor_x = x;
+        amdgpu_crtc->cursor_y = y;
 
         return 0;
 }
 
-static int dce_v11_0_crtc_cursor_set(struct drm_crtc *crtc,
-                                    struct drm_file *file_priv,
-                                    uint32_t handle,
-                                    uint32_t width,
-                                    uint32_t height)
+static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
+                                      int x, int y)
+{
+        int ret;
+
+        dce_v11_0_lock_cursor(crtc, true);
+        ret = dce_v11_0_cursor_move_locked(crtc, x, y);
+        dce_v11_0_lock_cursor(crtc, false);
+
+        return ret;
+}
+
+static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
+                                      struct drm_file *file_priv,
+                                      uint32_t handle,
+                                      uint32_t width,
+                                      uint32_t height,
+                                      int32_t hot_x,
+                                      int32_t hot_y)
 {
         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
         struct drm_gem_object *obj;
-        struct amdgpu_bo *robj;
-        uint64_t gpu_addr;
+        struct amdgpu_bo *aobj;
         int ret;
 
         if (!handle) {
@@ -2574,41 +2569,71 @@ static int dce_v11_0_crtc_cursor_set(struct drm_crtc *crtc,
                 return -ENOENT;
         }
 
-        robj = gem_to_amdgpu_bo(obj);
-        ret = amdgpu_bo_reserve(robj, false);
-        if (unlikely(ret != 0))
-                goto fail;
-        ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM,
-                                       0, 0, &gpu_addr);
-        amdgpu_bo_unreserve(robj);
-        if (ret)
-                goto fail;
+        aobj = gem_to_amdgpu_bo(obj);
+        ret = amdgpu_bo_reserve(aobj, false);
+        if (ret != 0) {
+                drm_gem_object_unreference_unlocked(obj);
+                return ret;
+        }
+
+        ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
+        amdgpu_bo_unreserve(aobj);
+        if (ret) {
+                DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
+                drm_gem_object_unreference_unlocked(obj);
+                return ret;
+        }
 
         amdgpu_crtc->cursor_width = width;
         amdgpu_crtc->cursor_height = height;
 
         dce_v11_0_lock_cursor(crtc, true);
-        dce_v11_0_set_cursor(crtc, obj, gpu_addr);
+
+        if (hot_x != amdgpu_crtc->cursor_hot_x ||
+            hot_y != amdgpu_crtc->cursor_hot_y) {
+                int x, y;
+
+                x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
+                y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
+
+                dce_v11_0_cursor_move_locked(crtc, x, y);
+
+                amdgpu_crtc->cursor_hot_x = hot_x;
+                amdgpu_crtc->cursor_hot_y = hot_y;
+        }
+
         dce_v11_0_show_cursor(crtc);
         dce_v11_0_lock_cursor(crtc, false);
 
 unpin:
         if (amdgpu_crtc->cursor_bo) {
-                robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
-                ret = amdgpu_bo_reserve(robj, false);
+                struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
+                ret = amdgpu_bo_reserve(aobj, false);
                 if (likely(ret == 0)) {
-                        amdgpu_bo_unpin(robj);
-                        amdgpu_bo_unreserve(robj);
+                        amdgpu_bo_unpin(aobj);
+                        amdgpu_bo_unreserve(aobj);
                 }
                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
         }
 
         amdgpu_crtc->cursor_bo = obj;
         return 0;
-fail:
-        drm_gem_object_unreference_unlocked(obj);
+}
 
-        return ret;
+static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
+{
+        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
+
+        if (amdgpu_crtc->cursor_bo) {
+                dce_v11_0_lock_cursor(crtc, true);
+
+                dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
+                                             amdgpu_crtc->cursor_y);
+
+                dce_v11_0_show_cursor(crtc);
+
+                dce_v11_0_lock_cursor(crtc, false);
+        }
 }
 
 static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
@@ -2636,7 +2661,7 @@ static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
 }
 
 static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
-        .cursor_set = dce_v11_0_crtc_cursor_set,
+        .cursor_set2 = dce_v11_0_crtc_cursor_set2,
         .cursor_move = dce_v11_0_crtc_cursor_move,
         .gamma_set = dce_v11_0_crtc_gamma_set,
         .set_config = amdgpu_crtc_set_config,
@@ -2770,6 +2795,7 @@ static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
         dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
         amdgpu_atombios_crtc_scaler_setup(crtc);
+        dce_v11_0_cursor_reset(crtc);
         /* update the hw version fpr dpm */
         amdgpu_crtc->hw_mode = *adjusted_mode;
 
@@ -2911,6 +2937,11 @@ static int dce_v11_0_early_init(void *handle)
                 adev->mode_info.num_hpd = 6;
                 adev->mode_info.num_dig = 9;
                 break;
+        case CHIP_STONEY:
+                adev->mode_info.num_crtc = 2;
+                adev->mode_info.num_hpd = 6;
+                adev->mode_info.num_dig = 9;
+                break;
         default:
                 /* FIXME: not supported yet */
                 return -EINVAL;
@@ -3009,6 +3040,7 @@ static int dce_v11_0_hw_init(void *handle)
         dce_v11_0_init_golden_registers(adev);
 
         /* init dig PHYs, disp eng pll */
+        amdgpu_atombios_crtc_powergate_init(adev);
         amdgpu_atombios_encoder_init_dig(adev);
         amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
 
@@ -3046,25 +3078,18 @@ static int dce_v11_0_suspend(void *handle)
 
         amdgpu_atombios_scratch_regs_save(adev);
 
-        dce_v11_0_hpd_fini(adev);
-
-        dce_v11_0_pageflip_interrupt_fini(adev);
-
-        return 0;
+        return dce_v11_0_hw_fini(handle);
 }
 
 static int dce_v11_0_resume(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        int ret;
 
-        dce_v11_0_init_golden_registers(adev);
+        ret = dce_v11_0_hw_init(handle);
 
         amdgpu_atombios_scratch_regs_restore(adev);
 
-        /* init dig PHYs, disp eng pll */
-        amdgpu_atombios_crtc_powergate_init(adev);
-        amdgpu_atombios_encoder_init_dig(adev);
-        amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
         /* turn on the BL */
         if (adev->mode_info.bl_encoder) {
                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
@@ -3073,12 +3098,7 @@ static int dce_v11_0_resume(void *handle)
                                                     bl_level);
         }
 
-        /* initialize hpd */
-        dce_v11_0_hpd_init(adev);
-
-        dce_v11_0_pageflip_interrupt_init(adev);
-
-        return 0;
+        return ret;
 }
 
 static bool dce_v11_0_is_idle(void *handle)
@@ -3270,37 +3290,20 @@ static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
                                             unsigned type,
                                             enum amdgpu_interrupt_state state)
 {
-        u32 reg, reg_block;
-        /* now deal with page flip IRQ */
-        switch (type) {
-                case AMDGPU_PAGEFLIP_IRQ_D1:
-                        reg_block = CRTC0_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D2:
-                        reg_block = CRTC1_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D3:
-                        reg_block = CRTC2_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D4:
-                        reg_block = CRTC3_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D5:
-                        reg_block = CRTC4_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D6:
-                        reg_block = CRTC5_REGISTER_OFFSET;
-                        break;
-                default:
-                        DRM_ERROR("invalid pageflip crtc %d\n", type);
-                        return -EINVAL;
+        u32 reg;
+
+        if (type >= adev->mode_info.num_crtc) {
+                DRM_ERROR("invalid pageflip crtc %d\n", type);
+                return -EINVAL;
         }
 
-        reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block);
+        reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
         if (state == AMDGPU_IRQ_STATE_DISABLE)
-                WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
+                WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
+                       reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
         else
-                WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
+                WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
+                       reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
 
         return 0;
 }
@@ -3309,7 +3312,6 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
                                   struct amdgpu_irq_src *source,
                                   struct amdgpu_iv_entry *entry)
 {
-        int reg_block;
         unsigned long flags;
         unsigned crtc_id;
         struct amdgpu_crtc *amdgpu_crtc;
@@ -3318,33 +3320,15 @@ static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
         crtc_id = (entry->src_id - 8) >> 1;
         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 
-        /* ack the interrupt */
-        switch(crtc_id){
-                case AMDGPU_PAGEFLIP_IRQ_D1:
-                        reg_block = CRTC0_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D2:
-                        reg_block = CRTC1_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D3:
-                        reg_block = CRTC2_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D4:
-                        reg_block = CRTC3_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D5:
-                        reg_block = CRTC4_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D6:
-                        reg_block = CRTC5_REGISTER_OFFSET;
-                        break;
-                default:
-                        DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
-                        return -EINVAL;
+        if (crtc_id >= adev->mode_info.num_crtc) {
+                DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
+                return -EINVAL;
         }
 
-        if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
-                WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
+        if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
+            GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
+                WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
+                       GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
 
         /* IRQ could occur when in initial stage */
         if(amdgpu_crtc == NULL)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 34b9c2a9d8d4..4f7b49a6dc50 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -229,46 +229,22 @@ static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
  * @crtc_id: crtc to cleanup pageflip on
  * @crtc_base: new address of the crtc (GPU MC address)
  *
- * Does the actual pageflip (evergreen+).
- * During vblank we take the crtc lock and wait for the update_pending
- * bit to go high, when it does, we release the lock, and allow the
- * double buffered update to take place.
- * Returns the current update pending status.
+ * Triggers the actual pageflip by updating the primary
+ * surface base address.
  */
 static void dce_v8_0_page_flip(struct amdgpu_device *adev,
                               int crtc_id, u64 crtc_base)
 {
         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
-        u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset);
-        int i;
-
-        /* Lock the graphics update lock */
-        tmp |= GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK;
-        WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
-
-        /* update the scanout addresses */
-        WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
-               upper_32_bits(crtc_base));
-        WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
-               (u32)crtc_base);
 
+        /* update the primary scanout addresses */
         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
                upper_32_bits(crtc_base));
+        /* writing to the low address triggers the update */
         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
-               (u32)crtc_base);
-
-        /* Wait for update_pending to go high. */
-        for (i = 0; i < adev->usec_timeout; i++) {
-                if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) &
-                                GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK)
-                        break;
-                udelay(1);
-        }
-        DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
-
-        /* Unlock the lock, so double-buffering can take place inside vblank */
-        tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK;
-        WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
+               lower_32_bits(crtc_base));
+        /* post the write */
+        RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 }
 
 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
@@ -2429,26 +2405,19 @@ static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
         struct amdgpu_device *adev = crtc->dev->dev_private;
 
+        WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
+               upper_32_bits(amdgpu_crtc->cursor_addr));
+        WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
+               lower_32_bits(amdgpu_crtc->cursor_addr));
+
         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
                    CUR_CONTROL__CURSOR_EN_MASK |
                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
 }
 
-static void dce_v8_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
-                              uint64_t gpu_addr)
-{
-        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-        struct amdgpu_device *adev = crtc->dev->dev_private;
-
-        WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
-               upper_32_bits(gpu_addr));
-        WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
-               gpu_addr & 0xffffffff);
-}
-
-static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
-                                     int x, int y)
+static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
+                                       int x, int y)
 {
         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
         struct amdgpu_device *adev = crtc->dev->dev_private;
@@ -2468,26 +2437,40 @@ static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
                 y = 0;
         }
 
-        dce_v8_0_lock_cursor(crtc, true);
         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
-        dce_v8_0_lock_cursor(crtc, false);
+
+        amdgpu_crtc->cursor_x = x;
+        amdgpu_crtc->cursor_y = y;
 
         return 0;
 }
 
-static int dce_v8_0_crtc_cursor_set(struct drm_crtc *crtc,
-                                    struct drm_file *file_priv,
-                                    uint32_t handle,
-                                    uint32_t width,
-                                    uint32_t height)
+static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
+                                     int x, int y)
+{
+        int ret;
+
+        dce_v8_0_lock_cursor(crtc, true);
+        ret = dce_v8_0_cursor_move_locked(crtc, x, y);
+        dce_v8_0_lock_cursor(crtc, false);
+
+        return ret;
+}
+
+static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
+                                     struct drm_file *file_priv,
+                                     uint32_t handle,
+                                     uint32_t width,
+                                     uint32_t height,
+                                     int32_t hot_x,
+                                     int32_t hot_y)
 {
         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
         struct drm_gem_object *obj;
-        struct amdgpu_bo *robj;
-        uint64_t gpu_addr;
+        struct amdgpu_bo *aobj;
         int ret;
 
         if (!handle) {
@@ -2509,41 +2492,71 @@ static int dce_v8_0_crtc_cursor_set(struct drm_crtc *crtc,
                 return -ENOENT;
         }
 
-        robj = gem_to_amdgpu_bo(obj);
-        ret = amdgpu_bo_reserve(robj, false);
-        if (unlikely(ret != 0))
-                goto fail;
-        ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM,
-                                       0, 0, &gpu_addr);
-        amdgpu_bo_unreserve(robj);
-        if (ret)
-                goto fail;
+        aobj = gem_to_amdgpu_bo(obj);
+        ret = amdgpu_bo_reserve(aobj, false);
+        if (ret != 0) {
+                drm_gem_object_unreference_unlocked(obj);
+                return ret;
+        }
+
+        ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
+        amdgpu_bo_unreserve(aobj);
+        if (ret) {
+                DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
+                drm_gem_object_unreference_unlocked(obj);
+                return ret;
+        }
 
         amdgpu_crtc->cursor_width = width;
         amdgpu_crtc->cursor_height = height;
 
         dce_v8_0_lock_cursor(crtc, true);
-        dce_v8_0_set_cursor(crtc, obj, gpu_addr);
+
+        if (hot_x != amdgpu_crtc->cursor_hot_x ||
+            hot_y != amdgpu_crtc->cursor_hot_y) {
+                int x, y;
+
+                x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
+                y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
+
+                dce_v8_0_cursor_move_locked(crtc, x, y);
+
+                amdgpu_crtc->cursor_hot_x = hot_x;
+                amdgpu_crtc->cursor_hot_y = hot_y;
+        }
+
         dce_v8_0_show_cursor(crtc);
         dce_v8_0_lock_cursor(crtc, false);
 
 unpin:
         if (amdgpu_crtc->cursor_bo) {
-                robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
-                ret = amdgpu_bo_reserve(robj, false);
+                struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
+                ret = amdgpu_bo_reserve(aobj, false);
                 if (likely(ret == 0)) {
-                        amdgpu_bo_unpin(robj);
-                        amdgpu_bo_unreserve(robj);
+                        amdgpu_bo_unpin(aobj);
+                        amdgpu_bo_unreserve(aobj);
                 }
                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
         }
 
         amdgpu_crtc->cursor_bo = obj;
         return 0;
-fail:
-        drm_gem_object_unreference_unlocked(obj);
+}
 
-        return ret;
+static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
+{
+        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
+
+        if (amdgpu_crtc->cursor_bo) {
+                dce_v8_0_lock_cursor(crtc, true);
+
+                dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
+                                            amdgpu_crtc->cursor_y);
+
+                dce_v8_0_show_cursor(crtc);
+
+                dce_v8_0_lock_cursor(crtc, false);
+        }
 }
 
 static void dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
@@ -2571,7 +2584,7 @@ static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
 }
 
 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
-        .cursor_set = dce_v8_0_crtc_cursor_set,
+        .cursor_set2 = dce_v8_0_crtc_cursor_set2,
         .cursor_move = dce_v8_0_crtc_cursor_move,
         .gamma_set = dce_v8_0_crtc_gamma_set,
         .set_config = amdgpu_crtc_set_config,
@@ -2712,6 +2725,7 @@ static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
         dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
         amdgpu_atombios_crtc_scaler_setup(crtc);
+        dce_v8_0_cursor_reset(crtc);
         /* update the hw version fpr dpm */
         amdgpu_crtc->hw_mode = *adjusted_mode;
 
@@ -2979,22 +2993,18 @@ static int dce_v8_0_suspend(void *handle)
 
         amdgpu_atombios_scratch_regs_save(adev);
 
-        dce_v8_0_hpd_fini(adev);
-
-        dce_v8_0_pageflip_interrupt_fini(adev);
-
-        return 0;
+        return dce_v8_0_hw_fini(handle);
 }
 
 static int dce_v8_0_resume(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        int ret;
+
+        ret = dce_v8_0_hw_init(handle);
 
         amdgpu_atombios_scratch_regs_restore(adev);
 
-        /* init dig PHYs, disp eng pll */
-        amdgpu_atombios_encoder_init_dig(adev);
-        amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
         /* turn on the BL */
         if (adev->mode_info.bl_encoder) {
                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
@@ -3003,12 +3013,7 @@ static int dce_v8_0_resume(void *handle)
                                                     bl_level);
         }
 
-        /* initialize hpd */
-        dce_v8_0_hpd_init(adev);
-
-        dce_v8_0_pageflip_interrupt_init(adev);
-
-        return 0;
+        return ret;
 }
 
 static bool dce_v8_0_is_idle(void *handle)
@@ -3301,37 +3306,20 @@ static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
                                                  unsigned type,
                                                  enum amdgpu_interrupt_state state)
 {
-        u32 reg, reg_block;
-        /* now deal with page flip IRQ */
-        switch (type) {
-                case AMDGPU_PAGEFLIP_IRQ_D1:
-                        reg_block = CRTC0_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D2:
-                        reg_block = CRTC1_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D3:
-                        reg_block = CRTC2_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D4:
-                        reg_block = CRTC3_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D5:
-                        reg_block = CRTC4_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D6:
-                        reg_block = CRTC5_REGISTER_OFFSET;
-                        break;
-                default:
-                        DRM_ERROR("invalid pageflip crtc %d\n", type);
-                        return -EINVAL;
+        u32 reg;
+
+        if (type >= adev->mode_info.num_crtc) {
+                DRM_ERROR("invalid pageflip crtc %d\n", type);
+                return -EINVAL;
         }
 
-        reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block);
+        reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
         if (state == AMDGPU_IRQ_STATE_DISABLE)
-                WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
+                WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
+                       reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
         else
-                WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
+                WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
+                       reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
 
         return 0;
 }
@@ -3340,7 +3328,6 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
                                 struct amdgpu_irq_src *source,
                                 struct amdgpu_iv_entry *entry)
 {
-        int reg_block;
         unsigned long flags;
         unsigned crtc_id;
         struct amdgpu_crtc *amdgpu_crtc;
@@ -3349,33 +3336,15 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
         crtc_id = (entry->src_id - 8) >> 1;
         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 
-        /* ack the interrupt */
-        switch(crtc_id){
-                case AMDGPU_PAGEFLIP_IRQ_D1:
-                        reg_block = CRTC0_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D2:
-                        reg_block = CRTC1_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D3:
-                        reg_block = CRTC2_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D4:
-                        reg_block = CRTC3_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D5:
-                        reg_block = CRTC4_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D6:
-                        reg_block = CRTC5_REGISTER_OFFSET;
-                        break;
-                default:
-                        DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
-                        return -EINVAL;
+        if (crtc_id >= adev->mode_info.num_crtc) {
+                DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
+                return -EINVAL;
         }
 
-        if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
-                WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
+        if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
+            GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
+                WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
+                       GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
 
         /* IRQ could occur when in initial stage */
         if (amdgpu_crtc == NULL)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index e992bf2ff66c..72793f93e2fc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -5542,24 +5542,6 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
         .set_powergating_state = gfx_v7_0_set_powergating_state,
 };
 
-/**
- * gfx_v7_0_ring_is_lockup - check if the 3D engine is locked up
- *
- * @adev: amdgpu_device pointer
- * @ring: amdgpu_ring structure holding ring information
- *
- * Check if the 3D engine is locked up (CIK).
- * Returns true if the engine is locked, false if not.
- */
-static bool gfx_v7_0_ring_is_lockup(struct amdgpu_ring *ring)
-{
-        if (gfx_v7_0_is_idle(ring->adev)) {
-                amdgpu_ring_lockup_update(ring);
-                return false;
-        }
-        return amdgpu_ring_test_lockup(ring);
-}
-
 static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
         .get_rptr = gfx_v7_0_ring_get_rptr_gfx,
         .get_wptr = gfx_v7_0_ring_get_wptr_gfx,
@@ -5573,7 +5555,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = {
         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
         .test_ring = gfx_v7_0_ring_test_ring,
         .test_ib = gfx_v7_0_ring_test_ib,
-        .is_lockup = gfx_v7_0_ring_is_lockup,
         .insert_nop = amdgpu_ring_insert_nop,
 };
 
@@ -5590,7 +5571,6 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = {
         .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush,
         .test_ring = gfx_v7_0_ring_test_ring,
         .test_ib = gfx_v7_0_ring_test_ib,
-        .is_lockup = gfx_v7_0_ring_is_lockup,
         .insert_nop = amdgpu_ring_insert_nop,
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index cb4f68f53f24..6776cf756d40 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -73,6 +73,12 @@ MODULE_FIRMWARE("amdgpu/carrizo_mec.bin");
 MODULE_FIRMWARE("amdgpu/carrizo_mec2.bin");
 MODULE_FIRMWARE("amdgpu/carrizo_rlc.bin");
 
+MODULE_FIRMWARE("amdgpu/stoney_ce.bin");
+MODULE_FIRMWARE("amdgpu/stoney_pfp.bin");
+MODULE_FIRMWARE("amdgpu/stoney_me.bin");
+MODULE_FIRMWARE("amdgpu/stoney_mec.bin");
+MODULE_FIRMWARE("amdgpu/stoney_rlc.bin");
+
 MODULE_FIRMWARE("amdgpu/tonga_ce.bin");
 MODULE_FIRMWARE("amdgpu/tonga_pfp.bin");
 MODULE_FIRMWARE("amdgpu/tonga_me.bin");
@@ -229,11 +235,13 @@ static const u32 fiji_golden_common_all[] =
         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
         mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x3a00161a,
         mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x0000002e,
-        mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003,
+        mmGB_ADDR_CONFIG, 0xffffffff, 0x22011003,
         mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
         mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
         mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
-        mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF
+        mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
+        mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
+        mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x00000009,
 };
 
 static const u32 golden_settings_fiji_a10[] =
@@ -241,24 +249,26 @@ static const u32 golden_settings_fiji_a10[] =
         mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040,
         mmDB_DEBUG2, 0xf00fffff, 0x00000400,
         mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
-        mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x00000100,
         mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
+        mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
+        mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
         mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
-        mmTCC_CTRL, 0x00100000, 0xf30fff7f,
+        mmTCC_CTRL, 0x00100000, 0xf31fff7f,
+        mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
         mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000ff,
-        mmTCP_CHAN_STEER_HI, 0xffffffff, 0x7d6cf5e4,
-        mmTCP_CHAN_STEER_LO, 0xffffffff, 0x3928b1a0,
+        mmVGT_RESET_DEBUG, 0x00000004, 0x00000004,
 };
 
 static const u32 fiji_mgcg_cgcg_init[] =
 {
-        mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffc0,
+        mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xffffffff,
         mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
         mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100,
         mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100,
         mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100,
         mmCGTT_CPC_CLK_CTRL, 0xffffffff, 0x00000100,
         mmCGTT_CPF_CLK_CTRL, 0xffffffff, 0x40000100,
+        mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
         mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100,
         mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100,
         mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100,
@@ -286,6 +296,10 @@ static const u32 fiji_mgcg_cgcg_init[] =
         mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96e00200,
         mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
         mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003c,
+        mmPCIE_INDEX, 0xffffffff, 0x0140001c,
+        mmPCIE_DATA, 0x000f0000, 0x00000000,
+        mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100,
+        mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 };
 
@@ -493,6 +507,42 @@ static const u32 cz_mgcg_cgcg_init[] =
         mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001,
 };
 
+static const u32 stoney_golden_settings_a11[] =
+{
+        mmDB_DEBUG2, 0xf00fffff, 0x00000400,
+        mmGB_GPU_ID, 0x0000000f, 0x00000000,
+        mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
+        mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
+        mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0001003c,
+        mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
+        mmTCC_CTRL, 0x00100000, 0xf31fff7f,
+        mmTCC_EXE_DISABLE, 0x00000002, 0x00000002,
+        mmTCP_ADDR_CONFIG, 0x0000000f, 0x000000f1,
+        mmTCP_CHAN_STEER_LO, 0xffffffff, 0x10101010,
+};
+
+static const u32 stoney_golden_common_all[] =
+{
+        mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
+        mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x00000000,
+        mmPA_SC_RASTER_CONFIG_1, 0xffffffff, 0x00000000,
+        mmGB_ADDR_CONFIG, 0xffffffff, 0x12010001,
+        mmSPI_RESOURCE_RESERVE_CU_0, 0xffffffff, 0x00000800,
+        mmSPI_RESOURCE_RESERVE_CU_1, 0xffffffff, 0x00000800,
+        mmSPI_RESOURCE_RESERVE_EN_CU_0, 0xffffffff, 0x00007FBF,
+        mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF,
+};
+
+static const u32 stoney_mgcg_cgcg_init[] =
+{
+        mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000,
+        mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f,
+        mmCP_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
+        mmRLC_MEM_SLP_CNTL, 0xffffffff, 0x00020201,
+        mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200,
+        mmATC_MISC_CG, 0xffffffff, 0x000c0200,
+};
+
 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev);
 static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev);
 static void gfx_v8_0_set_gds_init(struct amdgpu_device *adev);
@@ -545,6 +595,17 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
                                                  cz_golden_common_all,
                                                  (const u32)ARRAY_SIZE(cz_golden_common_all));
                 break;
+        case CHIP_STONEY:
+                amdgpu_program_register_sequence(adev,
+                                                 stoney_mgcg_cgcg_init,
+                                                 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
+                amdgpu_program_register_sequence(adev,
+                                                 stoney_golden_settings_a11,
+                                                 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
+                amdgpu_program_register_sequence(adev,
+                                                 stoney_golden_common_all,
+                                                 (const u32)ARRAY_SIZE(stoney_golden_common_all));
+                break;
         default:
                 break;
         }
@@ -691,6 +752,9 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
         case CHIP_FIJI:
                 chip_name = "fiji";
                 break;
+        case CHIP_STONEY:
+                chip_name = "stoney";
+                break;
         default:
                 BUG();
         }
@@ -748,21 +812,23 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev)
         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 
-        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
-        err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
-        if (!err) {
-                err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
-                if (err)
-                        goto out;
-                cp_hdr = (const struct gfx_firmware_header_v1_0 *)
-                                                adev->gfx.mec2_fw->data;
-                adev->gfx.mec2_fw_version = le32_to_cpu(
-                                                cp_hdr->header.ucode_version);
-                adev->gfx.mec2_feature_version = le32_to_cpu(
-                                                cp_hdr->ucode_feature_version);
-        } else {
-                err = 0;
-                adev->gfx.mec2_fw = NULL;
+        if (adev->asic_type != CHIP_STONEY) {
+                snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
+                err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
+                if (!err) {
+                        err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
+                        if (err)
+                                goto out;
+                        cp_hdr = (const struct gfx_firmware_header_v1_0 *)
+                                adev->gfx.mec2_fw->data;
+                        adev->gfx.mec2_fw_version =
+                                le32_to_cpu(cp_hdr->header.ucode_version);
+                        adev->gfx.mec2_feature_version =
+                                le32_to_cpu(cp_hdr->ucode_feature_version);
+                } else {
+                        err = 0;
+                        adev->gfx.mec2_fw = NULL;
+                }
         }
 
         if (adev->firmware.smu_load) {
@@ -903,6 +969,232 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
         return 0;
 }
 
+static void gfx_v8_0_gpu_early_init(struct amdgpu_device *adev)
+{
+        u32 gb_addr_config;
+        u32 mc_shared_chmap, mc_arb_ramcfg;
+        u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
+        u32 tmp;
+
+        switch (adev->asic_type) {
+        case CHIP_TOPAZ:
+                adev->gfx.config.max_shader_engines = 1;
+                adev->gfx.config.max_tile_pipes = 2;
+                adev->gfx.config.max_cu_per_sh = 6;
+                adev->gfx.config.max_sh_per_se = 1;
+                adev->gfx.config.max_backends_per_se = 2;
+                adev->gfx.config.max_texture_channel_caches = 2;
+                adev->gfx.config.max_gprs = 256;
+                adev->gfx.config.max_gs_threads = 32;
+                adev->gfx.config.max_hw_contexts = 8;
+
+                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
+                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
+                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
+                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
+                break;
+        case CHIP_FIJI:
+                adev->gfx.config.max_shader_engines = 4;
+                adev->gfx.config.max_tile_pipes = 16;
+                adev->gfx.config.max_cu_per_sh = 16;
+                adev->gfx.config.max_sh_per_se = 1;
+                adev->gfx.config.max_backends_per_se = 4;
+                adev->gfx.config.max_texture_channel_caches = 8;
+                adev->gfx.config.max_gprs = 256;
+                adev->gfx.config.max_gs_threads = 32;
+                adev->gfx.config.max_hw_contexts = 8;
+
+                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
+                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
+                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
+                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
+                break;
+        case CHIP_TONGA:
+                adev->gfx.config.max_shader_engines = 4;
+                adev->gfx.config.max_tile_pipes = 8;
+                adev->gfx.config.max_cu_per_sh = 8;
+                adev->gfx.config.max_sh_per_se = 1;
+                adev->gfx.config.max_backends_per_se = 2;
+                adev->gfx.config.max_texture_channel_caches = 8;
+                adev->gfx.config.max_gprs = 256;
+                adev->gfx.config.max_gs_threads = 32;
+                adev->gfx.config.max_hw_contexts = 8;
+
+                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
+                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
+                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
+                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
+                break;
+        case CHIP_CARRIZO:
+                adev->gfx.config.max_shader_engines = 1;
+                adev->gfx.config.max_tile_pipes = 2;
+                adev->gfx.config.max_sh_per_se = 1;
+                adev->gfx.config.max_backends_per_se = 2;
+
+                switch (adev->pdev->revision) {
+                case 0xc4:
+                case 0x84:
+                case 0xc8:
+                case 0xcc:
+                case 0xe1:
+                case 0xe3:
+                        /* B10 */
+                        adev->gfx.config.max_cu_per_sh = 8;
+                        break;
+                case 0xc5:
+                case 0x81:
+                case 0x85:
+                case 0xc9:
+                case 0xcd:
+                case 0xe2:
+                case 0xe4:
+                        /* B8 */
+                        adev->gfx.config.max_cu_per_sh = 6;
+                        break;
+                case 0xc6:
+                case 0xca:
+                case 0xce:
+                case 0x88:
+                        /* B6 */
+                        adev->gfx.config.max_cu_per_sh = 6;
+                        break;
+                case 0xc7:
+                case 0x87:
+                case 0xcb:
+                case 0xe5:
+                case 0x89:
+                default:
+                        /* B4 */
+                        adev->gfx.config.max_cu_per_sh = 4;
+                        break;
+                }
+
+                adev->gfx.config.max_texture_channel_caches = 2;
+                adev->gfx.config.max_gprs = 256;
+                adev->gfx.config.max_gs_threads = 32;
+                adev->gfx.config.max_hw_contexts = 8;
+
+                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
+                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
+                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
+                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
+                break;
+        case CHIP_STONEY:
+                adev->gfx.config.max_shader_engines = 1;
+                adev->gfx.config.max_tile_pipes = 2;
+                adev->gfx.config.max_sh_per_se = 1;
+                adev->gfx.config.max_backends_per_se = 1;
+
+                switch (adev->pdev->revision) {
+                case 0xc0:
+                case 0xc1:
+                case 0xc2:
+                case 0xc4:
+                case 0xc8:
+                case 0xc9:
+                        adev->gfx.config.max_cu_per_sh = 3;
+                        break;
+                case 0xd0:
+                case 0xd1:
+                case 0xd2:
+                default:
+                        adev->gfx.config.max_cu_per_sh = 2;
+                        break;
+                }
+
+                adev->gfx.config.max_texture_channel_caches = 2;
+                adev->gfx.config.max_gprs = 256;
+                adev->gfx.config.max_gs_threads = 16;
+                adev->gfx.config.max_hw_contexts = 8;
+
+                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
+                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
+                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
+                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
+                break;
+        default:
+                adev->gfx.config.max_shader_engines = 2;
+                adev->gfx.config.max_tile_pipes = 4;
+                adev->gfx.config.max_cu_per_sh = 2;
+                adev->gfx.config.max_sh_per_se = 1;
+                adev->gfx.config.max_backends_per_se = 2;
+                adev->gfx.config.max_texture_channel_caches = 4;
+                adev->gfx.config.max_gprs = 256;
+                adev->gfx.config.max_gs_threads = 32;
+                adev->gfx.config.max_hw_contexts = 8;
+
+                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
+                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
+                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
+                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
+                gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
+                break;
+        }
+
+        mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
+        adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
+        mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
+
+        adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
+        adev->gfx.config.mem_max_burst_length_bytes = 256;
+        if (adev->flags & AMD_IS_APU) {
+                /* Get memory bank mapping mode. */
+                tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
+                dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
+                dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
+
+                tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
+                dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
+                dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
+
+                /* Validate settings in case only one DIMM installed. */
+                if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
+                        dimm00_addr_map = 0;
+                if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
+                        dimm01_addr_map = 0;
+                if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
+                        dimm10_addr_map = 0;
+                if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
+                        dimm11_addr_map = 0;
+
+                /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
+                /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
+                if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
+                        adev->gfx.config.mem_row_size_in_kb = 2;
+                else
+                        adev->gfx.config.mem_row_size_in_kb = 1;
+        } else {
+                tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
+                adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
+                if (adev->gfx.config.mem_row_size_in_kb > 4)
+                        adev->gfx.config.mem_row_size_in_kb = 4;
+        }
+
+        adev->gfx.config.shader_engine_tile_size = 32;
+        adev->gfx.config.num_gpus = 1;
+        adev->gfx.config.multi_gpu_tile_size = 64;
+
+        /* fix up row size */
+        switch (adev->gfx.config.mem_row_size_in_kb) {
+        case 1:
+        default:
+                gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
+                break;
+        case 2:
+                gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
+                break;
+        case 4:
+                gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
+                break;
+        }
+        adev->gfx.config.gb_addr_config = gb_addr_config;
+}
+
 static int gfx_v8_0_sw_init(void *handle)
 {
         int i, r;
@@ -1010,6 +1302,8 @@ static int gfx_v8_0_sw_init(void *handle)
 
         adev->gfx.ce_ram_size = 0x8000;
 
+        gfx_v8_0_gpu_early_init(adev);
+
         return 0;
 }
 
@@ -1610,6 +1904,273 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev)
                         WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
                 }
                 break;
+        case CHIP_STONEY:
+                for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
+                        switch (reg_offset) {
+                        case 0:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+                                break;
+                        case 1:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+                                break;
+                        case 2:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+                                break;
+                        case 3:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+                                break;
+                        case 4:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+                                break;
+                        case 5:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+                                break;
+                        case 6:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+                                break;
+                        case 8:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+                                                PIPE_CONFIG(ADDR_SURF_P2));
+                                break;
+                        case 9:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                                break;
+                        case 10:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                                break;
+                        case 11:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+                                break;
+                        case 13:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                                break;
+                        case 14:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                                break;
+                        case 15:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                                break;
+                        case 16:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+                                break;
+                        case 18:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+                                break;
+                        case 19:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THICK) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+                                break;
+                        case 20:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+                                break;
+                        case 21:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_THICK) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+                                break;
+                        case 22:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THICK) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+                                break;
+                        case 24:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THICK) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+                                break;
+                        case 25:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+                                break;
+                        case 26:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_3D_TILED_XTHICK) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THICK_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_1));
+                                break;
+                        case 27:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                                break;
+                        case 28:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+                                break;
+                        case 29:
+                                gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+                                                PIPE_CONFIG(ADDR_SURF_P2) |
+                                                MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+                                                SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_8));
+                                break;
+                        case 7:
+                        case 12:
+                        case 17:
+                        case 23:
+                                /* unused idx */
+                                continue;
+                        default:
+                                gb_tile_moden = 0;
+                                break;
+                        };
+                        adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
+                        WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);
+                }
+                for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
+                        switch (reg_offset) {
+                        case 0:
+                                gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_8_BANK));
+                                break;
+                        case 1:
+                                gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_8_BANK));
+                                break;
+                        case 2:
+                                gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+                                                NUM_BANKS(ADDR_SURF_8_BANK));
+                                break;
+                        case 3:
+                                gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+                                                NUM_BANKS(ADDR_SURF_8_BANK));
+                                break;
+                        case 4:
+                                gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+                                                NUM_BANKS(ADDR_SURF_8_BANK));
+                                break;
+                        case 5:
+                                gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+                                                NUM_BANKS(ADDR_SURF_8_BANK));
+                                break;
+                        case 6:
+                                gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+                                                NUM_BANKS(ADDR_SURF_8_BANK));
+                                break;
+                        case 8:
+                                gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                                break;
+                        case 9:
+                                gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                                break;
+                        case 10:
+                                gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                                break;
+                        case 11:
+                                gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                                break;
+                        case 12:
+                                gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                                break;
+                        case 13:
+                                gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+                                                NUM_BANKS(ADDR_SURF_16_BANK));
+                                break;
+                        case 14:
+                                gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+                                                BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+                                                MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+                                                NUM_BANKS(ADDR_SURF_8_BANK));
+                                break;
+                        case 7:
+                                /* unused idx */
+                                continue;
+                        default:
+                                gb_tile_moden = 0;
+                                break;
+                        };
+                        adev->gfx.config.macrotile_mode_array[reg_offset] = gb_tile_moden;
+                        WREG32(mmGB_MACROTILE_MODE0 + reg_offset, gb_tile_moden);
+                }
+                break;
         case CHIP_CARRIZO:
         default:
                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
@@ -2043,203 +2604,23 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
 
 static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
 {
-        u32 gb_addr_config;
-        u32 mc_shared_chmap, mc_arb_ramcfg;
-        u32 dimm00_addr_map, dimm01_addr_map, dimm10_addr_map, dimm11_addr_map;
         u32 tmp;
         int i;
 
-        switch (adev->asic_type) {
-        case CHIP_TOPAZ:
-                adev->gfx.config.max_shader_engines = 1;
-                adev->gfx.config.max_tile_pipes = 2;
-                adev->gfx.config.max_cu_per_sh = 6;
-                adev->gfx.config.max_sh_per_se = 1;
-                adev->gfx.config.max_backends_per_se = 2;
-                adev->gfx.config.max_texture_channel_caches = 2;
-                adev->gfx.config.max_gprs = 256;
-                adev->gfx.config.max_gs_threads = 32;
-                adev->gfx.config.max_hw_contexts = 8;
-
-                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-                gb_addr_config = TOPAZ_GB_ADDR_CONFIG_GOLDEN;
-                break;
-        case CHIP_FIJI:
-                adev->gfx.config.max_shader_engines = 4;
-                adev->gfx.config.max_tile_pipes = 16;
-                adev->gfx.config.max_cu_per_sh = 16;
-                adev->gfx.config.max_sh_per_se = 1;
-                adev->gfx.config.max_backends_per_se = 4;
-                adev->gfx.config.max_texture_channel_caches = 8;
-                adev->gfx.config.max_gprs = 256;
-                adev->gfx.config.max_gs_threads = 32;
-                adev->gfx.config.max_hw_contexts = 8;
-
-                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-                gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
-                break;
-        case CHIP_TONGA:
-                adev->gfx.config.max_shader_engines = 4;
-                adev->gfx.config.max_tile_pipes = 8;
-                adev->gfx.config.max_cu_per_sh = 8;
-                adev->gfx.config.max_sh_per_se = 1;
-                adev->gfx.config.max_backends_per_se = 2;
-                adev->gfx.config.max_texture_channel_caches = 8;
-                adev->gfx.config.max_gprs = 256;
-                adev->gfx.config.max_gs_threads = 32;
-                adev->gfx.config.max_hw_contexts = 8;
-
-                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-                gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
-                break;
-        case CHIP_CARRIZO:
-                adev->gfx.config.max_shader_engines = 1;
-                adev->gfx.config.max_tile_pipes = 2;
-                adev->gfx.config.max_sh_per_se = 1;
-                adev->gfx.config.max_backends_per_se = 2;
-
-                switch (adev->pdev->revision) {
-                case 0xc4:
-                case 0x84:
-                case 0xc8:
-                case 0xcc:
-                        /* B10 */
-                        adev->gfx.config.max_cu_per_sh = 8;
-                        break;
-                case 0xc5:
-                case 0x81:
-                case 0x85:
-                case 0xc9:
-                case 0xcd:
-                        /* B8 */
-                        adev->gfx.config.max_cu_per_sh = 6;
-                        break;
-                case 0xc6:
-                case 0xca:
-                case 0xce:
-                        /* B6 */
-                        adev->gfx.config.max_cu_per_sh = 6;
-                        break;
-                case 0xc7:
-                case 0x87:
-                case 0xcb:
-                default:
-                        /* B4 */
-                        adev->gfx.config.max_cu_per_sh = 4;
-                        break;
-                }
-
-                adev->gfx.config.max_texture_channel_caches = 2;
-                adev->gfx.config.max_gprs = 256;
-                adev->gfx.config.max_gs_threads = 32;
-                adev->gfx.config.max_hw_contexts = 8;
-
-                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-                gb_addr_config = CARRIZO_GB_ADDR_CONFIG_GOLDEN;
-                break;
-        default:
-                adev->gfx.config.max_shader_engines = 2;
-                adev->gfx.config.max_tile_pipes = 4;
-                adev->gfx.config.max_cu_per_sh = 2;
-                adev->gfx.config.max_sh_per_se = 1;
-                adev->gfx.config.max_backends_per_se = 2;
-                adev->gfx.config.max_texture_channel_caches = 4;
-                adev->gfx.config.max_gprs = 256;
-                adev->gfx.config.max_gs_threads = 32;
-                adev->gfx.config.max_hw_contexts = 8;
-
-                adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
-                adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
-                adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
-                adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
-                gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN;
-                break;
-        }
-
         tmp = RREG32(mmGRBM_CNTL);
         tmp = REG_SET_FIELD(tmp, GRBM_CNTL, READ_TIMEOUT, 0xff);
         WREG32(mmGRBM_CNTL, tmp);
 
-        mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
-        adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
-        mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
-
-        adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
-        adev->gfx.config.mem_max_burst_length_bytes = 256;
-        if (adev->flags & AMD_IS_APU) {
-                /* Get memory bank mapping mode. */
-                tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
-                dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
-                dimm01_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
-
-                tmp = RREG32(mmMC_FUS_DRAM1_BANK_ADDR_MAPPING);
-                dimm10_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
-                dimm11_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM1_BANK_ADDR_MAPPING, DIMM1ADDRMAP);
-
-                /* Validate settings in case only one DIMM installed. */
-                if ((dimm00_addr_map == 0) || (dimm00_addr_map == 3) || (dimm00_addr_map == 4) || (dimm00_addr_map > 12))
-                        dimm00_addr_map = 0;
-                if ((dimm01_addr_map == 0) || (dimm01_addr_map == 3) || (dimm01_addr_map == 4) || (dimm01_addr_map > 12))
-                        dimm01_addr_map = 0;
-                if ((dimm10_addr_map == 0) || (dimm10_addr_map == 3) || (dimm10_addr_map == 4) || (dimm10_addr_map > 12))
-                        dimm10_addr_map = 0;
-                if ((dimm11_addr_map == 0) || (dimm11_addr_map == 3) || (dimm11_addr_map == 4) || (dimm11_addr_map > 12))
-                        dimm11_addr_map = 0;
-
-                /* If DIMM Addr map is 8GB, ROW size should be 2KB. Otherwise 1KB. */
-                /* If ROW size(DIMM1) != ROW size(DMIMM0), ROW size should be larger one. */
-                if ((dimm00_addr_map == 11) || (dimm01_addr_map == 11) || (dimm10_addr_map == 11) || (dimm11_addr_map == 11))
-                        adev->gfx.config.mem_row_size_in_kb = 2;
-                else
-                        adev->gfx.config.mem_row_size_in_kb = 1;
-        } else {
-                tmp = REG_GET_FIELD(mc_arb_ramcfg, MC_ARB_RAMCFG, NOOFCOLS);
-                adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
-                if (adev->gfx.config.mem_row_size_in_kb > 4)
-                        adev->gfx.config.mem_row_size_in_kb = 4;
-        }
-
-        adev->gfx.config.shader_engine_tile_size = 32;
-        adev->gfx.config.num_gpus = 1;
-        adev->gfx.config.multi_gpu_tile_size = 64;
-
-        /* fix up row size */
-        switch (adev->gfx.config.mem_row_size_in_kb) {
-        case 1:
-        default:
-                gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 0);
-                break;
-        case 2:
-                gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 1);
-                break;
-        case 4:
-                gb_addr_config = REG_SET_FIELD(gb_addr_config, GB_ADDR_CONFIG, ROW_SIZE, 2);
-                break;
-        }
-        adev->gfx.config.gb_addr_config = gb_addr_config;
-
-        WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
-        WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
-        WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
+        WREG32(mmGB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
+        WREG32(mmHDP_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
+        WREG32(mmDMIF_ADDR_CALC, adev->gfx.config.gb_addr_config);
         WREG32(mmSDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET,
-               gb_addr_config & 0x70);
+               adev->gfx.config.gb_addr_config & 0x70);
         WREG32(mmSDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET,
-               gb_addr_config & 0x70);
-        WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
-        WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
-        WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
+               adev->gfx.config.gb_addr_config & 0x70);
+        WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
+        WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
+        WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
 
         gfx_v8_0_tiling_mode_table_init(adev);
 
@@ -2256,13 +2637,13 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
                 if (i == 0) {
                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_UC);
                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_UC);
-                        tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, 
+                        tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
                         WREG32(mmSH_MEM_CONFIG, tmp);
                 } else {
                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, DEFAULT_MTYPE, MTYPE_NC);
                         tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, APE1_MTYPE, MTYPE_NC);
-                        tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE, 
+                        tmp = REG_SET_FIELD(tmp, SH_MEM_CONFIG, ALIGNMENT_MODE,
                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
                         WREG32(mmSH_MEM_CONFIG, tmp);
                 }
@@ -2377,7 +2758,7 @@ static void gfx_v8_0_rlc_start(struct amdgpu_device *adev)
         WREG32(mmRLC_CNTL, tmp);
 
         /* carrizo do enable cp interrupt after cp inited */
-        if (adev->asic_type != CHIP_CARRIZO)
+        if (!(adev->flags & AMD_IS_APU))
                 gfx_v8_0_enable_gui_idle_interrupt(adev, true);
 
         udelay(50);
@@ -2599,6 +2980,10 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev)
                 amdgpu_ring_write(ring, 0x00000002);
                 amdgpu_ring_write(ring, 0x00000000);
                 break;
+        case CHIP_STONEY:
+                amdgpu_ring_write(ring, 0x00000000);
+                amdgpu_ring_write(ring, 0x00000000);
+                break;
         default:
                 BUG();
         }
@@ -3233,7 +3618,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
                 /* enable the doorbell if requested */
                 if (use_doorbell) {
                         if ((adev->asic_type == CHIP_CARRIZO) ||
-                            (adev->asic_type == CHIP_FIJI)) {
+                            (adev->asic_type == CHIP_FIJI) ||
+                            (adev->asic_type == CHIP_STONEY)) {
                                 WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER,
                                        AMDGPU_DOORBELL_KIQ << 2);
                                 WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER,
@@ -3305,7 +3691,7 @@ static int gfx_v8_0_cp_resume(struct amdgpu_device *adev)
 {
         int r;
 
-        if (adev->asic_type != CHIP_CARRIZO)
+        if (!(adev->flags & AMD_IS_APU))
                 gfx_v8_0_enable_gui_idle_interrupt(adev, false);
 
         if (!adev->firmware.smu_load) {
@@ -4068,15 +4454,6 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
         }
 }
 
-static bool gfx_v8_0_ring_is_lockup(struct amdgpu_ring *ring)
-{
-        if (gfx_v8_0_is_idle(ring->adev)) {
-                amdgpu_ring_lockup_update(ring);
-                return false;
-        }
-        return amdgpu_ring_test_lockup(ring);
-}
-
 static u32 gfx_v8_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
 {
         return ring->adev->wb.wb[ring->rptr_offs];
@@ -4107,6 +4484,7 @@ static void gfx_v8_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 5));
         amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
                                  EOP_TC_ACTION_EN |
+                                 EOP_TC_WB_ACTION_EN |
                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
                                  EVENT_INDEX(5)));
         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
@@ -4357,7 +4735,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
         .test_ring = gfx_v8_0_ring_test_ring,
         .test_ib = gfx_v8_0_ring_test_ib,
-        .is_lockup = gfx_v8_0_ring_is_lockup,
         .insert_nop = amdgpu_ring_insert_nop,
 };
 
@@ -4374,7 +4751,6 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = {
         .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush,
         .test_ring = gfx_v8_0_ring_test_ring,
         .test_ib = gfx_v8_0_ring_test_ib,
-        .is_lockup = gfx_v8_0_ring_is_lockup,
         .insert_nop = amdgpu_ring_insert_nop,
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index fab5471d25d7..85bbcdc73fff 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -436,6 +436,33 @@ static int gmc_v7_0_gart_set_pte_pde(struct amdgpu_device *adev,
 }
 
 /**
+ * gmc_v8_0_set_fault_enable_default - update VM fault handling
+ *
+ * @adev: amdgpu_device pointer
+ * @value: true redirects VM faults to the default page
+ */
+static void gmc_v7_0_set_fault_enable_default(struct amdgpu_device *adev,
+                                              bool value)
+{
+        u32 tmp;
+
+        tmp = RREG32(mmVM_CONTEXT1_CNTL);
+        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
+                            RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
+                            DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
+                            PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
+                            VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
+                            READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
+                            WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+        WREG32(mmVM_CONTEXT1_CNTL, tmp);
+}
+
+/**
  * gmc_v7_0_gart_enable - gart enable
  *
  * @adev: amdgpu_device pointer
@@ -523,15 +550,13 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
         tmp = RREG32(mmVM_CONTEXT1_CNTL);
         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH, 1);
-        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
-        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
-        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
-        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
-        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
-        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
                             amdgpu_vm_block_size - 9);
         WREG32(mmVM_CONTEXT1_CNTL, tmp);
+        if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
+                gmc_v7_0_set_fault_enable_default(adev, false);
+        else
+                gmc_v7_0_set_fault_enable_default(adev, true);
 
         if (adev->asic_type == CHIP_KAVERI) {
                 tmp = RREG32(mmCHUB_CONTROL);
@@ -940,7 +965,7 @@ static int gmc_v7_0_sw_fini(void *handle)
 
         if (adev->vm_manager.enabled) {
                 for (i = 0; i < AMDGPU_NUM_VM; ++i)
-                        amdgpu_fence_unref(&adev->vm_manager.active[i]);
+                        fence_put(adev->vm_manager.active[i]);
                 gmc_v7_0_vm_fini(adev);
                 adev->vm_manager.enabled = false;
         }
@@ -990,7 +1015,7 @@ static int gmc_v7_0_suspend(void *handle)
 
         if (adev->vm_manager.enabled) {
                 for (i = 0; i < AMDGPU_NUM_VM; ++i)
-                        amdgpu_fence_unref(&adev->vm_manager.active[i]);
+                        fence_put(adev->vm_manager.active[i]);
                 gmc_v7_0_vm_fini(adev);
                 adev->vm_manager.enabled = false;
         }
@@ -1268,6 +1293,9 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev,
         if (!addr && !status)
                 return 0;
 
+        if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
+                gmc_v7_0_set_fault_enable_default(adev, false);
+
         dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
                 entry->src_id, entry->src_data);
         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 7bc9e9fcf3d2..1bcc4e74e3b4 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -93,6 +93,12 @@ static const u32 cz_mgcg_cgcg_init[] =
         mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
 };
 
+static const u32 stoney_mgcg_cgcg_init[] =
+{
+        mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104
+};
+
+
 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
 {
         switch (adev->asic_type) {
@@ -125,6 +131,11 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
                                                  cz_mgcg_cgcg_init,
                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
                 break;
+        case CHIP_STONEY:
+                amdgpu_program_register_sequence(adev,
+                                                 stoney_mgcg_cgcg_init,
+                                                 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
+                break;
         default:
                 break;
         }
@@ -228,6 +239,7 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev)
                 chip_name = "fiji";
                 break;
         case CHIP_CARRIZO:
+        case CHIP_STONEY:
                 return 0;
         default: BUG();
         }
@@ -550,6 +562,35 @@ static int gmc_v8_0_gart_set_pte_pde(struct amdgpu_device *adev,
 }
 
 /**
+ * gmc_v8_0_set_fault_enable_default - update VM fault handling
+ *
+ * @adev: amdgpu_device pointer
+ * @value: true redirects VM faults to the default page
+ */
+static void gmc_v8_0_set_fault_enable_default(struct amdgpu_device *adev,
+                                              bool value)
+{
+        u32 tmp;
+
+        tmp = RREG32(mmVM_CONTEXT1_CNTL);
+        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
+                            RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
+                            DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
+                            PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
+                            VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
+                            READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
+                            WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+        tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
+                            EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
+        WREG32(mmVM_CONTEXT1_CNTL, tmp);
+}
+
+/**
  * gmc_v8_0_gart_enable - gart enable
  *
  * @adev: amdgpu_device pointer
@@ -663,6 +704,10 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
         tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_BLOCK_SIZE,
                             amdgpu_vm_block_size - 9);
         WREG32(mmVM_CONTEXT1_CNTL, tmp);
+        if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
+                gmc_v8_0_set_fault_enable_default(adev, false);
+        else
+                gmc_v8_0_set_fault_enable_default(adev, true);
 
         gmc_v8_0_gart_flush_gpu_tlb(adev, 0);
         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
@@ -939,7 +984,7 @@ static int gmc_v8_0_sw_fini(void *handle)
 
         if (adev->vm_manager.enabled) {
                 for (i = 0; i < AMDGPU_NUM_VM; ++i)
-                        amdgpu_fence_unref(&adev->vm_manager.active[i]);
+                        fence_put(adev->vm_manager.active[i]);
                 gmc_v8_0_vm_fini(adev);
                 adev->vm_manager.enabled = false;
         }
@@ -991,7 +1036,7 @@ static int gmc_v8_0_suspend(void *handle)
 
         if (adev->vm_manager.enabled) {
                 for (i = 0; i < AMDGPU_NUM_VM; ++i)
-                        amdgpu_fence_unref(&adev->vm_manager.active[i]);
+                        fence_put(adev->vm_manager.active[i]);
                 gmc_v8_0_vm_fini(adev);
                 adev->vm_manager.enabled = false;
         }
@@ -1268,6 +1313,9 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev,
         if (!addr && !status)
                 return 0;
 
+        if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST)
+                gmc_v8_0_set_fault_enable_default(adev, false);
+
         dev_err(adev->dev, "GPU fault detected: %d 0x%08x\n",
                 entry->src_id, entry->src_data);
         dev_err(adev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 14e87234171a..2cf50180cc51 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -118,7 +118,7 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
 {
         const char *chip_name;
         char fw_name[30];
-        int err, i;
+        int err = 0, i;
         struct amdgpu_firmware_info *info = NULL;
         const struct common_firmware_header *header = NULL;
         const struct sdma_firmware_header_v1_0 *hdr;
@@ -132,27 +132,27 @@ static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
         default: BUG();
         }
 
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
+        for (i = 0; i < adev->sdma.num_instances; i++) {
                 if (i == 0)
                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
                 else
                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
-                err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
+                err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
                 if (err)
                         goto out;
-                err = amdgpu_ucode_validate(adev->sdma[i].fw);
+                err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
                 if (err)
                         goto out;
-                hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
-                adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
-                adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
-                if (adev->sdma[i].feature_version >= 20)
-                        adev->sdma[i].burst_nop = true;
+                hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
+                adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
+                adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
+                if (adev->sdma.instance[i].feature_version >= 20)
+                        adev->sdma.instance[i].burst_nop = true;
 
                 if (adev->firmware.smu_load) {
                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
-                        info->fw = adev->sdma[i].fw;
+                        info->fw = adev->sdma.instance[i].fw;
                         header = (const struct common_firmware_header *)info->fw->data;
                         adev->firmware.fw_size +=
                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
@@ -164,9 +164,9 @@ out:
                 printk(KERN_ERR
                        "sdma_v2_4: Failed to load firmware \"%s\"\n",
                        fw_name);
-                for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
-                        release_firmware(adev->sdma[i].fw);
-                        adev->sdma[i].fw = NULL;
+                for (i = 0; i < adev->sdma.num_instances; i++) {
+                        release_firmware(adev->sdma.instance[i].fw);
+                        adev->sdma.instance[i].fw = NULL;
                 }
         }
         return err;
@@ -199,7 +199,7 @@ static uint32_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
-        int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
+        int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
         u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
 
         return wptr;
@@ -215,14 +215,14 @@ static uint32_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
 {
         struct amdgpu_device *adev = ring->adev;
-        int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
+        int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 
         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
 }
 
 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 {
-        struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ring);
+        struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
         int i;
 
         for (i = 0; i < count; i++)
@@ -284,7 +284,7 @@ static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 {
         u32 ref_and_mask = 0;
 
-        if (ring == &ring->adev->sdma[0].ring)
+        if (ring == &ring->adev->sdma.instance[0].ring)
                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
         else
                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
@@ -368,8 +368,8 @@ static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring,
  */
 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
 {
-        struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
-        struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
+        struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
+        struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
         u32 rb_cntl, ib_cntl;
         int i;
 
@@ -377,7 +377,7 @@ static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
             (adev->mman.buffer_funcs_ring == sdma1))
                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
+        for (i = 0; i < adev->sdma.num_instances; i++) {
                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
@@ -419,7 +419,7 @@ static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
                 sdma_v2_4_rlc_stop(adev);
         }
 
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
+        for (i = 0; i < adev->sdma.num_instances; i++) {
                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
                 if (enable)
                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
@@ -445,8 +445,8 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
         u32 wb_offset;
         int i, j, r;
 
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
-                ring = &adev->sdma[i].ring;
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                ring = &adev->sdma.instance[i].ring;
                 wb_offset = (ring->rptr_offs * 4);
 
                 mutex_lock(&adev->srbm_mutex);
@@ -545,29 +545,23 @@ static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
         const __le32 *fw_data;
         u32 fw_size;
         int i, j;
-        bool smc_loads_fw = false; /* XXX fix me */
-
-        if (!adev->sdma[0].fw || !adev->sdma[1].fw)
-                return -EINVAL;
 
         /* halt the MEs */
         sdma_v2_4_enable(adev, false);
 
-        if (smc_loads_fw) {
-                /* XXX query SMC for fw load complete */
-        } else {
-                for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
-                        hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
-                        amdgpu_ucode_print_sdma_hdr(&hdr->header);
-                        fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
-                        fw_data = (const __le32 *)
-                                (adev->sdma[i].fw->data +
-                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
-                        WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
-                        for (j = 0; j < fw_size; j++)
-                                WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
-                        WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
-                }
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                if (!adev->sdma.instance[i].fw)
+                        return -EINVAL;
+                hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
+                amdgpu_ucode_print_sdma_hdr(&hdr->header);
+                fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
+                fw_data = (const __le32 *)
+                        (adev->sdma.instance[i].fw->data +
+                         le32_to_cpu(hdr->header.ucode_array_offset_bytes));
+                WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
+                for (j = 0; j < fw_size; j++)
+                        WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
+                WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
         }
 
         return 0;
@@ -894,7 +888,7 @@ static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib,
  */
 static void sdma_v2_4_vm_pad_ib(struct amdgpu_ib *ib)
 {
-        struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ib->ring);
+        struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);
         u32 pad_count;
         int i;
 
@@ -952,6 +946,8 @@ static int sdma_v2_4_early_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+        adev->sdma.num_instances = SDMA_MAX_INSTANCE;
+
         sdma_v2_4_set_ring_funcs(adev);
         sdma_v2_4_set_buffer_funcs(adev);
         sdma_v2_4_set_vm_pte_funcs(adev);
@@ -963,21 +959,21 @@ static int sdma_v2_4_early_init(void *handle)
 static int sdma_v2_4_sw_init(void *handle)
 {
         struct amdgpu_ring *ring;
-        int r;
+        int r, i;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
         /* SDMA trap event */
-        r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
+        r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
         if (r)
                 return r;
 
         /* SDMA Privileged inst */
-        r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
+        r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
         if (r)
                 return r;
 
         /* SDMA Privileged inst */
-        r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
+        r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
         if (r)
                 return r;
 
@@ -987,31 +983,20 @@ static int sdma_v2_4_sw_init(void *handle)
                 return r;
         }
 
-        ring = &adev->sdma[0].ring;
-        ring->ring_obj = NULL;
-        ring->use_doorbell = false;
-
-        ring = &adev->sdma[1].ring;
-        ring->ring_obj = NULL;
-        ring->use_doorbell = false;
-
-        ring = &adev->sdma[0].ring;
-        sprintf(ring->name, "sdma0");
-        r = amdgpu_ring_init(adev, ring, 256 * 1024,
-                             SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
-                             &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
-                             AMDGPU_RING_TYPE_SDMA);
-        if (r)
-                return r;
-
-        ring = &adev->sdma[1].ring;
-        sprintf(ring->name, "sdma1");
-        r = amdgpu_ring_init(adev, ring, 256 * 1024,
-                             SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
-                             &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
-                             AMDGPU_RING_TYPE_SDMA);
-        if (r)
-                return r;
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                ring = &adev->sdma.instance[i].ring;
+                ring->ring_obj = NULL;
+                ring->use_doorbell = false;
+                sprintf(ring->name, "sdma%d", i);
+                r = amdgpu_ring_init(adev, ring, 256 * 1024,
+                                     SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
+                                     &adev->sdma.trap_irq,
+                                     (i == 0) ?
+                                     AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
+                                     AMDGPU_RING_TYPE_SDMA);
+                if (r)
+                        return r;
+        }
 
         return r;
 }
@@ -1019,9 +1004,10 @@ static int sdma_v2_4_sw_init(void *handle)
 static int sdma_v2_4_sw_fini(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        int i;
 
-        amdgpu_ring_fini(&adev->sdma[0].ring);
-        amdgpu_ring_fini(&adev->sdma[1].ring);
+        for (i = 0; i < adev->sdma.num_instances; i++)
+                amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 
         return 0;
 }
@@ -1100,7 +1086,7 @@ static void sdma_v2_4_print_status(void *handle)
         dev_info(adev->dev, "VI SDMA registers\n");
         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
                  RREG32(mmSRBM_STATUS2));
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
+        for (i = 0; i < adev->sdma.num_instances; i++) {
                 dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
                          i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
                 dev_info(adev->dev, "  SDMA%d_F32_CNTL=0x%08X\n",
@@ -1243,7 +1229,7 @@ static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
         case 0:
                 switch (queue_id) {
                 case 0:
-                        amdgpu_fence_process(&adev->sdma[0].ring);
+                        amdgpu_fence_process(&adev->sdma.instance[0].ring);
                         break;
                 case 1:
                         /* XXX compute */
@@ -1256,7 +1242,7 @@ static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
         case 1:
                 switch (queue_id) {
                 case 0:
-                        amdgpu_fence_process(&adev->sdma[1].ring);
+                        amdgpu_fence_process(&adev->sdma.instance[1].ring);
                         break;
                 case 1:
                         /* XXX compute */
@@ -1309,24 +1295,6 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
         .set_powergating_state = sdma_v2_4_set_powergating_state,
 };
 
-/**
- * sdma_v2_4_ring_is_lockup - Check if the DMA engine is locked up
- *
- * @ring: amdgpu_ring structure holding ring information
- *
- * Check if the async DMA engine is locked up (VI).
- * Returns true if the engine appears to be locked up, false if not.
- */
-static bool sdma_v2_4_ring_is_lockup(struct amdgpu_ring *ring)
-{
-
-        if (sdma_v2_4_is_idle(ring->adev)) {
-                amdgpu_ring_lockup_update(ring);
-                return false;
-        }
-        return amdgpu_ring_test_lockup(ring);
-}
-
 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
         .get_rptr = sdma_v2_4_ring_get_rptr,
         .get_wptr = sdma_v2_4_ring_get_wptr,
@@ -1339,14 +1307,15 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
         .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
         .test_ring = sdma_v2_4_ring_test_ring,
         .test_ib = sdma_v2_4_ring_test_ib,
-        .is_lockup = sdma_v2_4_ring_is_lockup,
         .insert_nop = sdma_v2_4_ring_insert_nop,
 };
 
 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
 {
-        adev->sdma[0].ring.funcs = &sdma_v2_4_ring_funcs;
-        adev->sdma[1].ring.funcs = &sdma_v2_4_ring_funcs;
+        int i;
+
+        for (i = 0; i < adev->sdma.num_instances; i++)
+                adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
 }
 
 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
@@ -1360,9 +1329,9 @@ static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
 
 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
 {
-        adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
-        adev->sdma_trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
-        adev->sdma_illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
+        adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
+        adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
+        adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
 }
 
 /**
@@ -1428,7 +1397,7 @@ static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
 {
         if (adev->mman.buffer_funcs == NULL) {
                 adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
-                adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
+                adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
         }
 }
 
@@ -1443,7 +1412,7 @@ static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
 {
         if (adev->vm_manager.vm_pte_funcs == NULL) {
                 adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
-                adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
+                adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
                 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
         }
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 9bfe92df15f7..7253132f04b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -55,6 +55,7 @@ MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
+MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
 
 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
 {
@@ -122,6 +123,19 @@ static const u32 cz_mgcg_cgcg_init[] =
         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 };
 
+static const u32 stoney_golden_settings_a11[] =
+{
+        mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
+        mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
+        mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
+        mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
+};
+
+static const u32 stoney_mgcg_cgcg_init[] =
+{
+        mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
+};
+
 /*
  * sDMA - System DMA
  * Starting with CIK, the GPU has new asynchronous
@@ -166,6 +180,14 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
                                                  cz_golden_settings_a11,
                                                  (const u32)ARRAY_SIZE(cz_golden_settings_a11));
                 break;
+        case CHIP_STONEY:
+                amdgpu_program_register_sequence(adev,
+                                                 stoney_mgcg_cgcg_init,
+                                                 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
+                amdgpu_program_register_sequence(adev,
+                                                 stoney_golden_settings_a11,
+                                                 (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
+                break;
         default:
                 break;
         }
@@ -184,7 +206,7 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 {
         const char *chip_name;
         char fw_name[30];
-        int err, i;
+        int err = 0, i;
         struct amdgpu_firmware_info *info = NULL;
         const struct common_firmware_header *header = NULL;
         const struct sdma_firmware_header_v1_0 *hdr;
@@ -201,30 +223,33 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
         case CHIP_CARRIZO:
                 chip_name = "carrizo";
                 break;
+        case CHIP_STONEY:
+                chip_name = "stoney";
+                break;
         default: BUG();
         }
 
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
+        for (i = 0; i < adev->sdma.num_instances; i++) {
                 if (i == 0)
                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
                 else
                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
-                err = request_firmware(&adev->sdma[i].fw, fw_name, adev->dev);
+                err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
                 if (err)
                         goto out;
-                err = amdgpu_ucode_validate(adev->sdma[i].fw);
+                err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
                 if (err)
                         goto out;
-                hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
-                adev->sdma[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
-                adev->sdma[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
-                if (adev->sdma[i].feature_version >= 20)
-                        adev->sdma[i].burst_nop = true;
+                hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
+                adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
+                adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
+                if (adev->sdma.instance[i].feature_version >= 20)
+                        adev->sdma.instance[i].burst_nop = true;
 
                 if (adev->firmware.smu_load) {
                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
-                        info->fw = adev->sdma[i].fw;
+                        info->fw = adev->sdma.instance[i].fw;
                         header = (const struct common_firmware_header *)info->fw->data;
                         adev->firmware.fw_size +=
                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
@@ -235,9 +260,9 @@ out:
                 printk(KERN_ERR
                        "sdma_v3_0: Failed to load firmware \"%s\"\n",
                        fw_name);
-                for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
-                        release_firmware(adev->sdma[i].fw);
-                        adev->sdma[i].fw = NULL;
+                for (i = 0; i < adev->sdma.num_instances; i++) {
+                        release_firmware(adev->sdma.instance[i].fw);
+                        adev->sdma.instance[i].fw = NULL;
                 }
         }
         return err;
@@ -276,7 +301,7 @@ static uint32_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
                 /* XXX check if swapping is necessary on BE */
                 wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2;
         } else {
-                int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
+                int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 
                 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me]) >> 2;
         }
@@ -300,7 +325,7 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
                 adev->wb.wb[ring->wptr_offs] = ring->wptr << 2;
                 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
         } else {
-                int me = (ring == &ring->adev->sdma[0].ring) ? 0 : 1;
+                int me = (ring == &ring->adev->sdma.instance[0].ring) ? 0 : 1;
 
                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], ring->wptr << 2);
         }
@@ -308,7 +333,7 @@ static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 
 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 {
-        struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ring);
+        struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
         int i;
 
         for (i = 0; i < count; i++)
@@ -369,7 +394,7 @@ static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 {
         u32 ref_and_mask = 0;
 
-        if (ring == &ring->adev->sdma[0].ring)
+        if (ring == &ring->adev->sdma.instance[0].ring)
                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
         else
                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
@@ -454,8 +479,8 @@ static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring,
  */
 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 {
-        struct amdgpu_ring *sdma0 = &adev->sdma[0].ring;
-        struct amdgpu_ring *sdma1 = &adev->sdma[1].ring;
+        struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
+        struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
         u32 rb_cntl, ib_cntl;
         int i;
 
@@ -463,7 +488,7 @@ static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
             (adev->mman.buffer_funcs_ring == sdma1))
                 amdgpu_ttm_set_active_vram_size(adev, adev->mc.visible_vram_size);
 
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
+        for (i = 0; i < adev->sdma.num_instances; i++) {
                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
@@ -500,7 +525,7 @@ static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
         u32 f32_cntl;
         int i;
 
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
+        for (i = 0; i < adev->sdma.num_instances; i++) {
                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
                 if (enable)
                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
@@ -530,7 +555,7 @@ static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
                 sdma_v3_0_rlc_stop(adev);
         }
 
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
+        for (i = 0; i < adev->sdma.num_instances; i++) {
                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
                 if (enable)
                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
@@ -557,8 +582,8 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
         u32 doorbell;
         int i, j, r;
 
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
-                ring = &adev->sdma[i].ring;
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                ring = &adev->sdma.instance[i].ring;
                 wb_offset = (ring->rptr_offs * 4);
 
                 mutex_lock(&adev->srbm_mutex);
@@ -669,23 +694,22 @@ static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
         u32 fw_size;
         int i, j;
 
-        if (!adev->sdma[0].fw || !adev->sdma[1].fw)
-                return -EINVAL;
-
         /* halt the MEs */
         sdma_v3_0_enable(adev, false);
 
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
-                hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma[i].fw->data;
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                if (!adev->sdma.instance[i].fw)
+                        return -EINVAL;
+                hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
                 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
                 fw_data = (const __le32 *)
-                        (adev->sdma[i].fw->data +
+                        (adev->sdma.instance[i].fw->data +
                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
                 WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
                 for (j = 0; j < fw_size; j++)
                         WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
-                WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma[i].fw_version);
+                WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
         }
 
         return 0;
@@ -701,21 +725,21 @@ static int sdma_v3_0_load_microcode(struct amdgpu_device *adev)
  */
 static int sdma_v3_0_start(struct amdgpu_device *adev)
 {
-        int r;
+        int r, i;
 
         if (!adev->firmware.smu_load) {
                 r = sdma_v3_0_load_microcode(adev);
                 if (r)
                         return r;
         } else {
-                r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-                                                AMDGPU_UCODE_ID_SDMA0);
-                if (r)
-                        return -EINVAL;
-                r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
-                                                AMDGPU_UCODE_ID_SDMA1);
-                if (r)
-                        return -EINVAL;
+                for (i = 0; i < adev->sdma.num_instances; i++) {
+                        r = adev->smu.smumgr_funcs->check_fw_load_finish(adev,
+                                                                         (i == 0) ?
+                                                                         AMDGPU_UCODE_ID_SDMA0 :
+                                                                         AMDGPU_UCODE_ID_SDMA1);
+                        if (r)
+                                return -EINVAL;
+                }
         }
 
         /* unhalt the MEs */
@@ -1013,7 +1037,7 @@ static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib,
  */
 static void sdma_v3_0_vm_pad_ib(struct amdgpu_ib *ib)
 {
-        struct amdgpu_sdma *sdma = amdgpu_get_sdma_instance(ib->ring);
+        struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ib->ring);
         u32 pad_count;
         int i;
 
@@ -1071,6 +1095,15 @@ static int sdma_v3_0_early_init(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+        switch (adev->asic_type) {
+        case CHIP_STONEY:
+                adev->sdma.num_instances = 1;
+                break;
+        default:
+                adev->sdma.num_instances = SDMA_MAX_INSTANCE;
+                break;
+        }
+
         sdma_v3_0_set_ring_funcs(adev);
         sdma_v3_0_set_buffer_funcs(adev);
         sdma_v3_0_set_vm_pte_funcs(adev);
@@ -1082,21 +1115,21 @@ static int sdma_v3_0_early_init(void *handle)
 static int sdma_v3_0_sw_init(void *handle)
 {
         struct amdgpu_ring *ring;
-        int r;
+        int r, i;
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
         /* SDMA trap event */
-        r = amdgpu_irq_add_id(adev, 224, &adev->sdma_trap_irq);
+        r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
         if (r)
                 return r;
 
         /* SDMA Privileged inst */
-        r = amdgpu_irq_add_id(adev, 241, &adev->sdma_illegal_inst_irq);
+        r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
         if (r)
                 return r;
 
         /* SDMA Privileged inst */
-        r = amdgpu_irq_add_id(adev, 247, &adev->sdma_illegal_inst_irq);
+        r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
         if (r)
                 return r;
 
@@ -1106,33 +1139,23 @@ static int sdma_v3_0_sw_init(void *handle)
                 return r;
         }
 
-        ring = &adev->sdma[0].ring;
-        ring->ring_obj = NULL;
-        ring->use_doorbell = true;
-        ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE0;
-
-        ring = &adev->sdma[1].ring;
-        ring->ring_obj = NULL;
-        ring->use_doorbell = true;
-        ring->doorbell_index = AMDGPU_DOORBELL_sDMA_ENGINE1;
-
-        ring = &adev->sdma[0].ring;
-        sprintf(ring->name, "sdma0");
-        r = amdgpu_ring_init(adev, ring, 256 * 1024,
-                             SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
-                             &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP0,
-                             AMDGPU_RING_TYPE_SDMA);
-        if (r)
-                return r;
-
-        ring = &adev->sdma[1].ring;
-        sprintf(ring->name, "sdma1");
-        r = amdgpu_ring_init(adev, ring, 256 * 1024,
-                             SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
-                             &adev->sdma_trap_irq, AMDGPU_SDMA_IRQ_TRAP1,
-                             AMDGPU_RING_TYPE_SDMA);
-        if (r)
-                return r;
+        for (i = 0; i < adev->sdma.num_instances; i++) {
+                ring = &adev->sdma.instance[i].ring;
+                ring->ring_obj = NULL;
+                ring->use_doorbell = true;
+                ring->doorbell_index = (i == 0) ?
+                        AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
+
+                sprintf(ring->name, "sdma%d", i);
+                r = amdgpu_ring_init(adev, ring, 256 * 1024,
+                                     SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
+                                     &adev->sdma.trap_irq,
+                                     (i == 0) ?
+                                     AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1,
+                                     AMDGPU_RING_TYPE_SDMA);
+                if (r)
+                        return r;
+        }
 
         return r;
 }
@@ -1140,9 +1163,10 @@ static int sdma_v3_0_sw_init(void *handle)
 static int sdma_v3_0_sw_fini(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        int i;
 
-        amdgpu_ring_fini(&adev->sdma[0].ring);
-        amdgpu_ring_fini(&adev->sdma[1].ring);
+        for (i = 0; i < adev->sdma.num_instances; i++)
+                amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 
         return 0;
 }
@@ -1222,7 +1246,7 @@ static void sdma_v3_0_print_status(void *handle)
         dev_info(adev->dev, "VI SDMA registers\n");
         dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
                  RREG32(mmSRBM_STATUS2));
-        for (i = 0; i < SDMA_MAX_INSTANCE; i++) {
+        for (i = 0; i < adev->sdma.num_instances; i++) {
                 dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
                          i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
                 dev_info(adev->dev, "  SDMA%d_F32_CNTL=0x%08X\n",
@@ -1367,7 +1391,7 @@ static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
         case 0:
                 switch (queue_id) {
                 case 0:
-                        amdgpu_fence_process(&adev->sdma[0].ring);
+                        amdgpu_fence_process(&adev->sdma.instance[0].ring);
                         break;
                 case 1:
                         /* XXX compute */
@@ -1380,7 +1404,7 @@ static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
         case 1:
                 switch (queue_id) {
                 case 0:
-                        amdgpu_fence_process(&adev->sdma[1].ring);
+                        amdgpu_fence_process(&adev->sdma.instance[1].ring);
                         break;
                 case 1:
                         /* XXX compute */
@@ -1432,24 +1456,6 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
         .set_powergating_state = sdma_v3_0_set_powergating_state,
 };
 
-/**
- * sdma_v3_0_ring_is_lockup - Check if the DMA engine is locked up
- *
- * @ring: amdgpu_ring structure holding ring information
- *
- * Check if the async DMA engine is locked up (VI).
- * Returns true if the engine appears to be locked up, false if not.
- */
-static bool sdma_v3_0_ring_is_lockup(struct amdgpu_ring *ring)
-{
-
-        if (sdma_v3_0_is_idle(ring->adev)) {
-                amdgpu_ring_lockup_update(ring);
-                return false;
-        }
-        return amdgpu_ring_test_lockup(ring);
-}
-
 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
         .get_rptr = sdma_v3_0_ring_get_rptr,
         .get_wptr = sdma_v3_0_ring_get_wptr,
@@ -1462,14 +1468,15 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
         .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
         .test_ring = sdma_v3_0_ring_test_ring,
         .test_ib = sdma_v3_0_ring_test_ib,
-        .is_lockup = sdma_v3_0_ring_is_lockup,
         .insert_nop = sdma_v3_0_ring_insert_nop,
 };
 
 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
 {
-        adev->sdma[0].ring.funcs = &sdma_v3_0_ring_funcs;
-        adev->sdma[1].ring.funcs = &sdma_v3_0_ring_funcs;
+        int i;
+
+        for (i = 0; i < adev->sdma.num_instances; i++)
+                adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
 }
 
 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
@@ -1483,9 +1490,9 @@ static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
 
 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
 {
-        adev->sdma_trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
-        adev->sdma_trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
-        adev->sdma_illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
+        adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
+        adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
+        adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
 }
 
 /**
@@ -1551,7 +1558,7 @@ static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
 {
         if (adev->mman.buffer_funcs == NULL) {
                 adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
-                adev->mman.buffer_funcs_ring = &adev->sdma[0].ring;
+                adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
         }
 }
 
@@ -1566,7 +1573,7 @@ static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
 {
         if (adev->vm_manager.vm_pte_funcs == NULL) {
                 adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
-                adev->vm_manager.vm_pte_funcs_ring = &adev->sdma[0].ring;
+                adev->vm_manager.vm_pte_funcs_ring = &adev->sdma.instance[0].ring;
                 adev->vm_manager.vm_pte_funcs_ring->is_pte_ring = true;
         }
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index ed50dd725788..5e9f73af83a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -885,7 +885,6 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = {
         .emit_semaphore = uvd_v4_2_ring_emit_semaphore,
         .test_ring = uvd_v4_2_ring_test_ring,
         .test_ib = uvd_v4_2_ring_test_ib,
-        .is_lockup = amdgpu_ring_test_lockup,
         .insert_nop = amdgpu_ring_insert_nop,
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 9ad8b9906c0b..38864f562981 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -824,7 +824,6 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = {
         .emit_semaphore = uvd_v5_0_ring_emit_semaphore,
         .test_ring = uvd_v5_0_ring_test_ring,
         .test_ib = uvd_v5_0_ring_test_ib,
-        .is_lockup = amdgpu_ring_test_lockup,
         .insert_nop = amdgpu_ring_insert_nop,
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 7e9934fa4193..121915bbc3b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -808,7 +808,6 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = {
         .emit_semaphore = uvd_v6_0_ring_emit_semaphore,
         .test_ring = uvd_v6_0_ring_test_ring,
         .test_ib = uvd_v6_0_ring_test_ib,
-        .is_lockup = amdgpu_ring_test_lockup,
         .insert_nop = amdgpu_ring_insert_nop,
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index cd16df543f64..52ac7a8f1e58 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -642,7 +642,6 @@ static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = {
         .emit_semaphore = amdgpu_vce_ring_emit_semaphore,
         .test_ring = amdgpu_vce_ring_test_ring,
         .test_ib = amdgpu_vce_ring_test_ib,
-        .is_lockup = amdgpu_ring_test_lockup,
         .insert_nop = amdgpu_ring_insert_nop,
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index f0656dfb53f3..6a52db6ad8d7 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -205,8 +205,9 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
         u32 tmp;
         unsigned ret;
 
-        /* Fiji is single pipe */
-        if (adev->asic_type == CHIP_FIJI) {
+        /* Fiji, Stoney are single pipe */
+        if ((adev->asic_type == CHIP_FIJI) ||
+            (adev->asic_type == CHIP_STONEY)){
                 ret = AMDGPU_VCE_HARVEST_VCE1;
                 return ret;
         }
@@ -643,7 +644,6 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = {
         .emit_semaphore = amdgpu_vce_ring_emit_semaphore,
         .test_ring = amdgpu_vce_ring_test_ring,
         .test_ib = amdgpu_vce_ring_test_ib,
-        .is_lockup = amdgpu_ring_test_lockup,
         .insert_nop = amdgpu_ring_insert_nop,
 };
 
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 0bac8702e934..2adc1c855e85 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -232,6 +232,13 @@ static const u32 cz_mgcg_cgcg_init[] =
         mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 };
 
+static const u32 stoney_mgcg_cgcg_init[] =
+{
+        mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00000100,
+        mmHDP_XDP_CGTT_BLK_CTRL, 0xffffffff, 0x00000104,
+        mmHDP_HOST_PATH_CNTL, 0xffffffff, 0x0f000027,
+};
+
 static void vi_init_golden_registers(struct amdgpu_device *adev)
 {
         /* Some of the registers might be dependent on GRBM_GFX_INDEX */
@@ -258,6 +265,11 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
                                                  cz_mgcg_cgcg_init,
                                                  (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
                 break;
+        case CHIP_STONEY:
+                amdgpu_program_register_sequence(adev,
+                                                 stoney_mgcg_cgcg_init,
+                                                 (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
+                break;
         default:
                 break;
         }
@@ -488,6 +500,7 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
         case CHIP_FIJI:
         case CHIP_TONGA:
         case CHIP_CARRIZO:
+        case CHIP_STONEY:
                 asic_register_table = cz_allowed_read_registers;
                 size = ARRAY_SIZE(cz_allowed_read_registers);
                 break;
@@ -543,8 +556,10 @@ static void vi_print_gpu_status_regs(struct amdgpu_device *adev)
                 RREG32(mmSRBM_STATUS2));
         dev_info(adev->dev, "  SDMA0_STATUS_REG   = 0x%08X\n",
                 RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
-        dev_info(adev->dev, "  SDMA1_STATUS_REG   = 0x%08X\n",
-                 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
+        if (adev->sdma.num_instances > 1) {
+                dev_info(adev->dev, "  SDMA1_STATUS_REG   = 0x%08X\n",
+                        RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
+        }
         dev_info(adev->dev, "  CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
         dev_info(adev->dev, "  CP_STALLED_STAT1 = 0x%08x\n",
                  RREG32(mmCP_STALLED_STAT1));
@@ -639,9 +654,11 @@ u32 vi_gpu_check_soft_reset(struct amdgpu_device *adev)
                 reset_mask |= AMDGPU_RESET_DMA;
 
         /* SDMA1_STATUS_REG */
-        tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
-        if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
-                reset_mask |= AMDGPU_RESET_DMA1;
+        if (adev->sdma.num_instances > 1) {
+                tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
+                if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
+                        reset_mask |= AMDGPU_RESET_DMA1;
+        }
 #if 0
         /* VCE_STATUS */
         if (adev->asic_type != CHIP_TOPAZ) {
@@ -1319,6 +1336,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
                 adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks);
                 break;
         case CHIP_CARRIZO:
+        case CHIP_STONEY:
                 adev->ip_blocks = cz_ip_blocks;
                 adev->num_ip_blocks = ARRAY_SIZE(cz_ip_blocks);
                 break;
@@ -1330,11 +1348,18 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
         return 0;
 }
 
+#define ATI_REV_ID_FUSE_MACRO__ADDRESS      0xC0014044
+#define ATI_REV_ID_FUSE_MACRO__SHIFT        9
+#define ATI_REV_ID_FUSE_MACRO__MASK         0x00001E00
+
 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
 {
         if (adev->asic_type == CHIP_TOPAZ)
                 return (RREG32(mmPCIE_EFUSE4) & PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID_MASK)
                         >> PCIE_EFUSE4__STRAP_BIF_ATI_REV_ID__SHIFT;
+        else if (adev->flags & AMD_IS_APU)
+                return (RREG32_SMC(ATI_REV_ID_FUSE_MACRO__ADDRESS) & ATI_REV_ID_FUSE_MACRO__MASK)
+                        >> ATI_REV_ID_FUSE_MACRO__SHIFT;
         else
                 return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK)
                         >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT;
@@ -1388,32 +1413,35 @@ static int vi_common_early_init(void *handle)
                 adev->cg_flags = 0;
                 adev->pg_flags = 0;
                 adev->external_rev_id = 0x1;
-                if (amdgpu_smc_load_fw && smc_enabled)
-                        adev->firmware.smu_load = true;
                 break;
         case CHIP_FIJI:
+                adev->has_uvd = true;
+                adev->cg_flags = 0;
+                adev->pg_flags = 0;
+                adev->external_rev_id = adev->rev_id + 0x3c;
+                break;
         case CHIP_TONGA:
                 adev->has_uvd = true;
                 adev->cg_flags = 0;
                 adev->pg_flags = 0;
                 adev->external_rev_id = adev->rev_id + 0x14;
-                if (amdgpu_smc_load_fw && smc_enabled)
-                        adev->firmware.smu_load = true;
                 break;
         case CHIP_CARRIZO:
+        case CHIP_STONEY:
                 adev->has_uvd = true;
                 adev->cg_flags = 0;
                 /* Disable UVD pg */
                 adev->pg_flags = /* AMDGPU_PG_SUPPORT_UVD | */AMDGPU_PG_SUPPORT_VCE;
                 adev->external_rev_id = adev->rev_id + 0x1;
-                if (amdgpu_smc_load_fw && smc_enabled)
-                        adev->firmware.smu_load = true;
                 break;
         default:
                 /* FIXME: not supported yet */
                 return -EINVAL;
         }
 
+        if (amdgpu_smc_load_fw && smc_enabled)
+                adev->firmware.smu_load = true;
+
         return 0;
 }