1 files changed, 108 insertions, 139 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 34b9c2a9d8d4..4f7b49a6dc50 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -229,46 +229,22 @@ static void dce_v8_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
  * @crtc_id: crtc to cleanup pageflip on
  * @crtc_base: new address of the crtc (GPU MC address)
  *
- * Does the actual pageflip (evergreen+).
- * During vblank we take the crtc lock and wait for the update_pending
- * bit to go high, when it does, we release the lock, and allow the
- * double buffered update to take place.
- * Returns the current update pending status.
+ * Triggers the actual pageflip by updating the primary
+ * surface base address.
  */
 static void dce_v8_0_page_flip(struct amdgpu_device *adev,
                               int crtc_id, u64 crtc_base)
 {
         struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
-        u32 tmp = RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset);
-        int i;
-
-        /* Lock the graphics update lock */
-        tmp |= GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK;
-        WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
-
-        /* update the scanout addresses */
-        WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
-               upper_32_bits(crtc_base));
-        WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
-               (u32)crtc_base);
 
+        /* update the primary scanout addresses */
         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
                upper_32_bits(crtc_base));
+        /* writing to the low address triggers the update */
         WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
-               (u32)crtc_base);
-
-        /* Wait for update_pending to go high. */
-        for (i = 0; i < adev->usec_timeout; i++) {
-                if (RREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset) &
-                                GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK)
-                        break;
-                udelay(1);
-        }
-        DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
-
-        /* Unlock the lock, so double-buffering can take place inside vblank */
-        tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK;
-        WREG32(mmGRPH_UPDATE + amdgpu_crtc->crtc_offset, tmp);
+               lower_32_bits(crtc_base));
+        /* post the write */
+        RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
 }
 
 static int dce_v8_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
@@ -2429,26 +2405,19 @@ static void dce_v8_0_show_cursor(struct drm_crtc *crtc)
         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
         struct amdgpu_device *adev = crtc->dev->dev_private;
 
+        WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
+               upper_32_bits(amdgpu_crtc->cursor_addr));
+        WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
+               lower_32_bits(amdgpu_crtc->cursor_addr));
+
         WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
                    CUR_CONTROL__CURSOR_EN_MASK |
                    (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
                    (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
 }
 
-static void dce_v8_0_set_cursor(struct drm_crtc *crtc, struct drm_gem_object *obj,
-                              uint64_t gpu_addr)
-{
-        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-        struct amdgpu_device *adev = crtc->dev->dev_private;
-
-        WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
-               upper_32_bits(gpu_addr));
-        WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
-               gpu_addr & 0xffffffff);
-}
-
-static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
-                                     int x, int y)
+static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
+                                       int x, int y)
 {
         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
         struct amdgpu_device *adev = crtc->dev->dev_private;
@@ -2468,26 +2437,40 @@ static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
                 y = 0;
         }
 
-        dce_v8_0_lock_cursor(crtc, true);
         WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
         WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
         WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
                ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
-        dce_v8_0_lock_cursor(crtc, false);
+
+        amdgpu_crtc->cursor_x = x;
+        amdgpu_crtc->cursor_y = y;
 
         return 0;
 }
 
-static int dce_v8_0_crtc_cursor_set(struct drm_crtc *crtc,
-                                    struct drm_file *file_priv,
-                                    uint32_t handle,
-                                    uint32_t width,
-                                    uint32_t height)
+static int dce_v8_0_crtc_cursor_move(struct drm_crtc *crtc,
+                                     int x, int y)
+{
+        int ret;
+
+        dce_v8_0_lock_cursor(crtc, true);
+        ret = dce_v8_0_cursor_move_locked(crtc, x, y);
+        dce_v8_0_lock_cursor(crtc, false);
+
+        return ret;
+}
+
+static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
+                                     struct drm_file *file_priv,
+                                     uint32_t handle,
+                                     uint32_t width,
+                                     uint32_t height,
+                                     int32_t hot_x,
+                                     int32_t hot_y)
 {
         struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
         struct drm_gem_object *obj;
-        struct amdgpu_bo *robj;
-        uint64_t gpu_addr;
+        struct amdgpu_bo *aobj;
         int ret;
 
         if (!handle) {
@@ -2509,41 +2492,71 @@ static int dce_v8_0_crtc_cursor_set(struct drm_crtc *crtc,
                 return -ENOENT;
         }
 
-        robj = gem_to_amdgpu_bo(obj);
-        ret = amdgpu_bo_reserve(robj, false);
-        if (unlikely(ret != 0))
-                goto fail;
-        ret = amdgpu_bo_pin_restricted(robj, AMDGPU_GEM_DOMAIN_VRAM,
-                                       0, 0, &gpu_addr);
-        amdgpu_bo_unreserve(robj);
-        if (ret)
-                goto fail;
+        aobj = gem_to_amdgpu_bo(obj);
+        ret = amdgpu_bo_reserve(aobj, false);
+        if (ret != 0) {
+                drm_gem_object_unreference_unlocked(obj);
+                return ret;
+        }
+
+        ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
+        amdgpu_bo_unreserve(aobj);
+        if (ret) {
+                DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
+                drm_gem_object_unreference_unlocked(obj);
+                return ret;
+        }
 
         amdgpu_crtc->cursor_width = width;
         amdgpu_crtc->cursor_height = height;
 
         dce_v8_0_lock_cursor(crtc, true);
-        dce_v8_0_set_cursor(crtc, obj, gpu_addr);
+
+        if (hot_x != amdgpu_crtc->cursor_hot_x ||
+            hot_y != amdgpu_crtc->cursor_hot_y) {
+                int x, y;
+
+                x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
+                y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
+
+                dce_v8_0_cursor_move_locked(crtc, x, y);
+
+                amdgpu_crtc->cursor_hot_x = hot_x;
+                amdgpu_crtc->cursor_hot_y = hot_y;
+        }
+
         dce_v8_0_show_cursor(crtc);
         dce_v8_0_lock_cursor(crtc, false);
 
 unpin:
         if (amdgpu_crtc->cursor_bo) {
-                robj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
-                ret = amdgpu_bo_reserve(robj, false);
+                struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
+                ret = amdgpu_bo_reserve(aobj, false);
                 if (likely(ret == 0)) {
-                        amdgpu_bo_unpin(robj);
-                        amdgpu_bo_unreserve(robj);
+                        amdgpu_bo_unpin(aobj);
+                        amdgpu_bo_unreserve(aobj);
                 }
                 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
         }
 
         amdgpu_crtc->cursor_bo = obj;
         return 0;
-fail:
-        drm_gem_object_unreference_unlocked(obj);
+}
 
-        return ret;
+static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
+{
+        struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
+
+        if (amdgpu_crtc->cursor_bo) {
+                dce_v8_0_lock_cursor(crtc, true);
+
+                dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
+                                            amdgpu_crtc->cursor_y);
+
+                dce_v8_0_show_cursor(crtc);
+
+                dce_v8_0_lock_cursor(crtc, false);
+        }
 }
 
 static void dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
@@ -2571,7 +2584,7 @@ static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc)
 }
 
 static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = {
-        .cursor_set = dce_v8_0_crtc_cursor_set,
+        .cursor_set2 = dce_v8_0_crtc_cursor_set2,
         .cursor_move = dce_v8_0_crtc_cursor_move,
         .gamma_set = dce_v8_0_crtc_gamma_set,
         .set_config = amdgpu_crtc_set_config,
@@ -2712,6 +2725,7 @@ static int dce_v8_0_crtc_mode_set(struct drm_crtc *crtc,
         dce_v8_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
         amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
         amdgpu_atombios_crtc_scaler_setup(crtc);
+        dce_v8_0_cursor_reset(crtc);
         /* update the hw version fpr dpm */
         amdgpu_crtc->hw_mode = *adjusted_mode;
 
@@ -2979,22 +2993,18 @@ static int dce_v8_0_suspend(void *handle)
 
         amdgpu_atombios_scratch_regs_save(adev);
 
-        dce_v8_0_hpd_fini(adev);
-
-        dce_v8_0_pageflip_interrupt_fini(adev);
-
-        return 0;
+        return dce_v8_0_hw_fini(handle);
 }
 
 static int dce_v8_0_resume(void *handle)
 {
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+        int ret;
+
+        ret = dce_v8_0_hw_init(handle);
 
         amdgpu_atombios_scratch_regs_restore(adev);
 
-        /* init dig PHYs, disp eng pll */
-        amdgpu_atombios_encoder_init_dig(adev);
-        amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
         /* turn on the BL */
         if (adev->mode_info.bl_encoder) {
                 u8 bl_level = amdgpu_display_backlight_get_level(adev,
@@ -3003,12 +3013,7 @@ static int dce_v8_0_resume(void *handle)
                                                     bl_level);
         }
 
-        /* initialize hpd */
-        dce_v8_0_hpd_init(adev);
-
-        dce_v8_0_pageflip_interrupt_init(adev);
-
-        return 0;
+        return ret;
 }
 
 static bool dce_v8_0_is_idle(void *handle)
@@ -3301,37 +3306,20 @@ static int dce_v8_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
                                                  unsigned type,
                                                  enum amdgpu_interrupt_state state)
 {
-        u32 reg, reg_block;
-        /* now deal with page flip IRQ */
-        switch (type) {
-                case AMDGPU_PAGEFLIP_IRQ_D1:
-                        reg_block = CRTC0_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D2:
-                        reg_block = CRTC1_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D3:
-                        reg_block = CRTC2_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D4:
-                        reg_block = CRTC3_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D5:
-                        reg_block = CRTC4_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D6:
-                        reg_block = CRTC5_REGISTER_OFFSET;
-                        break;
-                default:
-                        DRM_ERROR("invalid pageflip crtc %d\n", type);
-                        return -EINVAL;
+        u32 reg;
+
+        if (type >= adev->mode_info.num_crtc) {
+                DRM_ERROR("invalid pageflip crtc %d\n", type);
+                return -EINVAL;
         }
 
-        reg = RREG32(mmGRPH_INTERRUPT_CONTROL + reg_block);
+        reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
         if (state == AMDGPU_IRQ_STATE_DISABLE)
-                WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
+                WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
+                       reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
         else
-                WREG32(mmGRPH_INTERRUPT_CONTROL + reg_block, reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
+                WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
+                       reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
 
         return 0;
 }
@@ -3340,7 +3328,6 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
                                 struct amdgpu_irq_src *source,
                                 struct amdgpu_iv_entry *entry)
 {
-        int reg_block;
         unsigned long flags;
         unsigned crtc_id;
         struct amdgpu_crtc *amdgpu_crtc;
@@ -3349,33 +3336,15 @@ static int dce_v8_0_pageflip_irq(struct amdgpu_device *adev,
         crtc_id = (entry->src_id - 8) >> 1;
         amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
 
-        /* ack the interrupt */
-        switch(crtc_id){
-                case AMDGPU_PAGEFLIP_IRQ_D1:
-                        reg_block = CRTC0_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D2:
-                        reg_block = CRTC1_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D3:
-                        reg_block = CRTC2_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D4:
-                        reg_block = CRTC3_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D5:
-                        reg_block = CRTC4_REGISTER_OFFSET;
-                        break;
-                case AMDGPU_PAGEFLIP_IRQ_D6:
-                        reg_block = CRTC5_REGISTER_OFFSET;
-                        break;
-                default:
-                        DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
-                        return -EINVAL;
+        if (crtc_id >= adev->mode_info.num_crtc) {
+                DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
+                return -EINVAL;
         }
 
-        if (RREG32(mmGRPH_INTERRUPT_STATUS + reg_block) & GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
-                WREG32(mmGRPH_INTERRUPT_STATUS + reg_block, GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
+        if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
+            GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
+                WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
+                       GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
 
         /* IRQ could occur when in initial stage */
         if (amdgpu_crtc == NULL)