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authorHariprasad Shenai <hariprasad@chelsio.com>2015-01-05 06:00:46 -0500
committerDavid S. Miller <davem@davemloft.net>2015-01-05 16:34:48 -0500
commit837e4a42bbb5c41ce555bcd544a9c24c28134e24 (patch)
tree9808770c4befb023562841187f00df363fe71a26
parent89c3a86cc7e5e86b841dbd0c2a67ae7899e62fdb (diff)
cxgb4/csiostor: Cleanup TP, MPS and TCAM related register defines
This patch cleanups all TP, MPS and TCAM related macros/register defines that are defined in t4_regs.h and the affected files Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c70
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_hw.c154
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_regs.h607
-rw-r--r--drivers/scsi/csiostor/csio_hw.c113
-rw-r--r--drivers/scsi/csiostor/csio_wr.c4
5 files changed, 536 insertions, 412 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 16c633f4bf8b..53ad8d3d9e4c 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -359,8 +359,8 @@ MODULE_PARM_DESC(select_queue,
359 */ 359 */
360enum { 360enum {
361 TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC, 361 TP_VLAN_PRI_MAP_DEFAULT = HW_TPL_FR_MT_PR_IV_P_FC,
362 TP_VLAN_PRI_MAP_FIRST = FCOE_SHIFT, 362 TP_VLAN_PRI_MAP_FIRST = FCOE_S,
363 TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_SHIFT, 363 TP_VLAN_PRI_MAP_LAST = FRAGMENTATION_S,
364}; 364};
365 365
366static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT; 366static unsigned int tp_vlan_pri_map = TP_VLAN_PRI_MAP_DEFAULT;
@@ -1177,10 +1177,10 @@ freeout: t4_free_sge_resources(adap);
1177 } 1177 }
1178 1178
1179 t4_write_reg(adap, is_t4(adap->params.chip) ? 1179 t4_write_reg(adap, is_t4(adap->params.chip) ?
1180 MPS_TRC_RSS_CONTROL : 1180 MPS_TRC_RSS_CONTROL_A :
1181 MPS_T5_TRC_RSS_CONTROL, 1181 MPS_T5_TRC_RSS_CONTROL_A,
1182 RSSCONTROL(netdev2pinfo(adap->port[0])->tx_chan) | 1182 RSSCONTROL_V(netdev2pinfo(adap->port[0])->tx_chan) |
1183 QUEUENUMBER(s->ethrxq[0].rspq.abs_id)); 1183 QUEUENUMBER_V(s->ethrxq[0].rspq.abs_id));
1184 return 0; 1184 return 0;
1185} 1185}
1186 1186
@@ -4094,7 +4094,7 @@ static void uld_attach(struct adapter *adap, unsigned int uld)
4094 lli.nports = adap->params.nports; 4094 lli.nports = adap->params.nports;
4095 lli.wr_cred = adap->params.ofldq_wr_cred; 4095 lli.wr_cred = adap->params.ofldq_wr_cred;
4096 lli.adapter_type = adap->params.chip; 4096 lli.adapter_type = adap->params.chip;
4097 lli.iscsi_iolen = MAXRXDATA_GET(t4_read_reg(adap, TP_PARA_REG2)); 4097 lli.iscsi_iolen = MAXRXDATA_G(t4_read_reg(adap, TP_PARA_REG2_A));
4098 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk; 4098 lli.cclk_ps = 1000000000 / adap->params.vpd.cclk;
4099 lli.udb_density = 1 << adap->params.sge.eq_qpp; 4099 lli.udb_density = 1 << adap->params.sge.eq_qpp;
4100 lli.ucq_density = 1 << adap->params.sge.iq_qpp; 4100 lli.ucq_density = 1 << adap->params.sge.iq_qpp;
@@ -4949,11 +4949,11 @@ static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
4949 t4_sge_init(adap); 4949 t4_sge_init(adap);
4950 4950
4951 /* tweak some settings */ 4951 /* tweak some settings */
4952 t4_write_reg(adap, TP_SHIFT_CNT, 0x64f8849); 4952 t4_write_reg(adap, TP_SHIFT_CNT_A, 0x64f8849);
4953 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12)); 4953 t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(PAGE_SHIFT - 12));
4954 t4_write_reg(adap, TP_PIO_ADDR, TP_INGRESS_CONFIG); 4954 t4_write_reg(adap, TP_PIO_ADDR_A, TP_INGRESS_CONFIG_A);
4955 v = t4_read_reg(adap, TP_PIO_DATA); 4955 v = t4_read_reg(adap, TP_PIO_DATA_A);
4956 t4_write_reg(adap, TP_PIO_DATA, v & ~CSUM_HAS_PSEUDO_HDR); 4956 t4_write_reg(adap, TP_PIO_DATA_A, v & ~CSUM_HAS_PSEUDO_HDR_F);
4957 4957
4958 /* first 4 Tx modulation queues point to consecutive Tx channels */ 4958 /* first 4 Tx modulation queues point to consecutive Tx channels */
4959 adap->params.tp.tx_modq_map = 0xE4; 4959 adap->params.tp.tx_modq_map = 0xE4;
@@ -4962,11 +4962,11 @@ static int adap_init1(struct adapter *adap, struct fw_caps_config_cmd *c)
4962 4962
4963 /* associate each Tx modulation queue with consecutive Tx channels */ 4963 /* associate each Tx modulation queue with consecutive Tx channels */
4964 v = 0x84218421; 4964 v = 0x84218421;
4965 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA, 4965 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4966 &v, 1, A_TP_TX_SCHED_HDR); 4966 &v, 1, A_TP_TX_SCHED_HDR);
4967 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA, 4967 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4968 &v, 1, A_TP_TX_SCHED_FIFO); 4968 &v, 1, A_TP_TX_SCHED_FIFO);
4969 t4_write_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA, 4969 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4970 &v, 1, A_TP_TX_SCHED_PCMD); 4970 &v, 1, A_TP_TX_SCHED_PCMD);
4971 4971
4972#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */ 4972#define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
@@ -5034,8 +5034,8 @@ static int adap_init0_tweaks(struct adapter *adapter)
5034 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 5034 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
5035 * adds the pseudo header itself. 5035 * adds the pseudo header itself.
5036 */ 5036 */
5037 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG, 5037 t4_tp_wr_bits_indirect(adapter, TP_INGRESS_CONFIG_A,
5038 CSUM_HAS_PSEUDO_HDR, 0); 5038 CSUM_HAS_PSEUDO_HDR_F, 0);
5039 5039
5040 return 0; 5040 return 0;
5041} 5041}
@@ -5401,34 +5401,34 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
5401 case 0: 5401 case 0:
5402 /* compressed filter field not enabled */ 5402 /* compressed filter field not enabled */
5403 break; 5403 break;
5404 case FCOE_MASK: 5404 case FCOE_F:
5405 bits += 1; 5405 bits += 1;
5406 break; 5406 break;
5407 case PORT_MASK: 5407 case PORT_F:
5408 bits += 3; 5408 bits += 3;
5409 break; 5409 break;
5410 case VNIC_ID_MASK: 5410 case VNIC_F:
5411 bits += 17; 5411 bits += 17;
5412 break; 5412 break;
5413 case VLAN_MASK: 5413 case VLAN_F:
5414 bits += 17; 5414 bits += 17;
5415 break; 5415 break;
5416 case TOS_MASK: 5416 case TOS_F:
5417 bits += 8; 5417 bits += 8;
5418 break; 5418 break;
5419 case PROTOCOL_MASK: 5419 case PROTOCOL_F:
5420 bits += 8; 5420 bits += 8;
5421 break; 5421 break;
5422 case ETHERTYPE_MASK: 5422 case ETHERTYPE_F:
5423 bits += 16; 5423 bits += 16;
5424 break; 5424 break;
5425 case MACMATCH_MASK: 5425 case MACMATCH_F:
5426 bits += 9; 5426 bits += 9;
5427 break; 5427 break;
5428 case MPSHITTYPE_MASK: 5428 case MPSHITTYPE_F:
5429 bits += 3; 5429 bits += 3;
5430 break; 5430 break;
5431 case FRAGMENTATION_MASK: 5431 case FRAGMENTATION_F:
5432 bits += 1; 5432 bits += 1;
5433 break; 5433 break;
5434 } 5434 }
@@ -5442,8 +5442,8 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
5442 } 5442 }
5443 } 5443 }
5444 v = tp_vlan_pri_map; 5444 v = tp_vlan_pri_map;
5445 t4_write_indirect(adapter, TP_PIO_ADDR, TP_PIO_DATA, 5445 t4_write_indirect(adapter, TP_PIO_ADDR_A, TP_PIO_DATA_A,
5446 &v, 1, TP_VLAN_PRI_MAP); 5446 &v, 1, TP_VLAN_PRI_MAP_A);
5447 5447
5448 /* 5448 /*
5449 * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order 5449 * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
@@ -5456,17 +5456,17 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
5456 * performance impact). 5456 * performance impact).
5457 */ 5457 */
5458 if (tp_vlan_pri_map) 5458 if (tp_vlan_pri_map)
5459 t4_set_reg_field(adapter, TP_GLOBAL_CONFIG, 5459 t4_set_reg_field(adapter, TP_GLOBAL_CONFIG_A,
5460 FIVETUPLELOOKUP_MASK, 5460 FIVETUPLELOOKUP_V(FIVETUPLELOOKUP_M),
5461 FIVETUPLELOOKUP_MASK); 5461 FIVETUPLELOOKUP_V(FIVETUPLELOOKUP_M));
5462 5462
5463 /* 5463 /*
5464 * Tweak some settings. 5464 * Tweak some settings.
5465 */ 5465 */
5466 t4_write_reg(adapter, TP_SHIFT_CNT, SYNSHIFTMAX(6) | 5466 t4_write_reg(adapter, TP_SHIFT_CNT_A, SYNSHIFTMAX_V(6) |
5467 RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) | 5467 RXTSHIFTMAXR1_V(4) | RXTSHIFTMAXR2_V(15) |
5468 PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) | 5468 PERSHIFTBACKOFFMAX_V(8) | PERSHIFTMAX_V(8) |
5469 KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9)); 5469 KEEPALIVEMAXR1_V(4) | KEEPALIVEMAXR2_V(9));
5470 5470
5471 /* 5471 /*
5472 * Get basic stuff going by issuing the Firmware Initialize command. 5472 * Get basic stuff going by issuing the Firmware Initialize command.
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index c9777e00cea4..cf0bf79a6193 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -1486,11 +1486,11 @@ static void tp_intr_handler(struct adapter *adapter)
1486{ 1486{
1487 static const struct intr_info tp_intr_info[] = { 1487 static const struct intr_info tp_intr_info[] = {
1488 { 0x3fffffff, "TP parity error", -1, 1 }, 1488 { 0x3fffffff, "TP parity error", -1, 1 },
1489 { FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, 1489 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
1490 { 0 } 1490 { 0 }
1491 }; 1491 };
1492 1492
1493 if (t4_handle_intr_status(adapter, TP_INT_CAUSE, tp_intr_info)) 1493 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
1494 t4_fatal_err(adapter); 1494 t4_fatal_err(adapter);
1495} 1495}
1496 1496
@@ -1629,19 +1629,19 @@ static void ulprx_intr_handler(struct adapter *adapter)
1629static void ulptx_intr_handler(struct adapter *adapter) 1629static void ulptx_intr_handler(struct adapter *adapter)
1630{ 1630{
1631 static const struct intr_info ulptx_intr_info[] = { 1631 static const struct intr_info ulptx_intr_info[] = {
1632 { PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1, 1632 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
1633 0 }, 1633 0 },
1634 { PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1, 1634 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
1635 0 }, 1635 0 },
1636 { PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1, 1636 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
1637 0 }, 1637 0 },
1638 { PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1, 1638 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
1639 0 }, 1639 0 },
1640 { 0xfffffff, "ULPTX parity error", -1, 1 }, 1640 { 0xfffffff, "ULPTX parity error", -1, 1 },
1641 { 0 } 1641 { 0 }
1642 }; 1642 };
1643 1643
1644 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE, ulptx_intr_info)) 1644 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
1645 t4_fatal_err(adapter); 1645 t4_fatal_err(adapter);
1646} 1646}
1647 1647
@@ -1651,19 +1651,20 @@ static void ulptx_intr_handler(struct adapter *adapter)
1651static void pmtx_intr_handler(struct adapter *adapter) 1651static void pmtx_intr_handler(struct adapter *adapter)
1652{ 1652{
1653 static const struct intr_info pmtx_intr_info[] = { 1653 static const struct intr_info pmtx_intr_info[] = {
1654 { PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 }, 1654 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
1655 { PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 }, 1655 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
1656 { PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 }, 1656 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
1657 { ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 }, 1657 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
1658 { PMTX_FRAMING_ERROR, "PMTX framing error", -1, 1 }, 1658 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
1659 { OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 }, 1659 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
1660 { DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 1 }, 1660 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
1661 { ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 }, 1661 -1, 1 },
1662 { C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1}, 1662 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
1663 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
1663 { 0 } 1664 { 0 }
1664 }; 1665 };
1665 1666
1666 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE, pmtx_intr_info)) 1667 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
1667 t4_fatal_err(adapter); 1668 t4_fatal_err(adapter);
1668} 1669}
1669 1670
@@ -1673,16 +1674,17 @@ static void pmtx_intr_handler(struct adapter *adapter)
1673static void pmrx_intr_handler(struct adapter *adapter) 1674static void pmrx_intr_handler(struct adapter *adapter)
1674{ 1675{
1675 static const struct intr_info pmrx_intr_info[] = { 1676 static const struct intr_info pmrx_intr_info[] = {
1676 { ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, 1677 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
1677 { PMRX_FRAMING_ERROR, "PMRX framing error", -1, 1 }, 1678 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
1678 { OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 }, 1679 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
1679 { DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 1 }, 1680 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
1680 { IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 }, 1681 -1, 1 },
1681 { E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1}, 1682 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
1683 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
1682 { 0 } 1684 { 0 }
1683 }; 1685 };
1684 1686
1685 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE, pmrx_intr_info)) 1687 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
1686 t4_fatal_err(adapter); 1688 t4_fatal_err(adapter);
1687} 1689}
1688 1690
@@ -1733,19 +1735,22 @@ static void mps_intr_handler(struct adapter *adapter)
1733 { 0 } 1735 { 0 }
1734 }; 1736 };
1735 static const struct intr_info mps_tx_intr_info[] = { 1737 static const struct intr_info mps_tx_intr_info[] = {
1736 { TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 }, 1738 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
1737 { NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 }, 1739 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
1738 { TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 }, 1740 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
1739 { TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 }, 1741 -1, 1 },
1740 { BUBBLE, "MPS Tx underflow", -1, 1 }, 1742 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
1741 { SECNTERR, "MPS Tx SOP/EOP error", -1, 1 }, 1743 -1, 1 },
1742 { FRMERR, "MPS Tx framing error", -1, 1 }, 1744 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
1745 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
1746 { FRMERR_F, "MPS Tx framing error", -1, 1 },
1743 { 0 } 1747 { 0 }
1744 }; 1748 };
1745 static const struct intr_info mps_trc_intr_info[] = { 1749 static const struct intr_info mps_trc_intr_info[] = {
1746 { FILTMEM, "MPS TRC filter parity error", -1, 1 }, 1750 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
1747 { PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 }, 1751 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
1748 { MISCPERR, "MPS TRC misc parity error", -1, 1 }, 1752 -1, 1 },
1753 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
1749 { 0 } 1754 { 0 }
1750 }; 1755 };
1751 static const struct intr_info mps_stat_sram_intr_info[] = { 1756 static const struct intr_info mps_stat_sram_intr_info[] = {
@@ -1761,32 +1766,31 @@ static void mps_intr_handler(struct adapter *adapter)
1761 { 0 } 1766 { 0 }
1762 }; 1767 };
1763 static const struct intr_info mps_cls_intr_info[] = { 1768 static const struct intr_info mps_cls_intr_info[] = {
1764 { MATCHSRAM, "MPS match SRAM parity error", -1, 1 }, 1769 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
1765 { MATCHTCAM, "MPS match TCAM parity error", -1, 1 }, 1770 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
1766 { HASHSRAM, "MPS hash SRAM parity error", -1, 1 }, 1771 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
1767 { 0 } 1772 { 0 }
1768 }; 1773 };
1769 1774
1770 int fat; 1775 int fat;
1771 1776
1772 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE, 1777 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
1773 mps_rx_intr_info) + 1778 mps_rx_intr_info) +
1774 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE, 1779 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
1775 mps_tx_intr_info) + 1780 mps_tx_intr_info) +
1776 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE, 1781 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
1777 mps_trc_intr_info) + 1782 mps_trc_intr_info) +
1778 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM, 1783 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
1779 mps_stat_sram_intr_info) + 1784 mps_stat_sram_intr_info) +
1780 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 1785 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
1781 mps_stat_tx_intr_info) + 1786 mps_stat_tx_intr_info) +
1782 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 1787 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
1783 mps_stat_rx_intr_info) + 1788 mps_stat_rx_intr_info) +
1784 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE, 1789 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
1785 mps_cls_intr_info); 1790 mps_cls_intr_info);
1786 1791
1787 t4_write_reg(adapter, MPS_INT_CAUSE, CLSINT | TRCINT | 1792 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
1788 RXINT | TXINT | STATINT); 1793 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
1789 t4_read_reg(adapter, MPS_INT_CAUSE); /* flush */
1790 if (fat) 1794 if (fat)
1791 t4_fatal_err(adapter); 1795 t4_fatal_err(adapter);
1792} 1796}
@@ -2187,23 +2191,23 @@ int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
2187void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, 2191void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
2188 struct tp_tcp_stats *v6) 2192 struct tp_tcp_stats *v6)
2189{ 2193{
2190 u32 val[TP_MIB_TCP_RXT_SEG_LO - TP_MIB_TCP_OUT_RST + 1]; 2194 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
2191 2195
2192#define STAT_IDX(x) ((TP_MIB_TCP_##x) - TP_MIB_TCP_OUT_RST) 2196#define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
2193#define STAT(x) val[STAT_IDX(x)] 2197#define STAT(x) val[STAT_IDX(x)]
2194#define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO)) 2198#define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
2195 2199
2196 if (v4) { 2200 if (v4) {
2197 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val, 2201 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
2198 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST); 2202 ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST_A);
2199 v4->tcpOutRsts = STAT(OUT_RST); 2203 v4->tcpOutRsts = STAT(OUT_RST);
2200 v4->tcpInSegs = STAT64(IN_SEG); 2204 v4->tcpInSegs = STAT64(IN_SEG);
2201 v4->tcpOutSegs = STAT64(OUT_SEG); 2205 v4->tcpOutSegs = STAT64(OUT_SEG);
2202 v4->tcpRetransSegs = STAT64(RXT_SEG); 2206 v4->tcpRetransSegs = STAT64(RXT_SEG);
2203 } 2207 }
2204 if (v6) { 2208 if (v6) {
2205 t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val, 2209 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val,
2206 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST); 2210 ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST_A);
2207 v6->tcpOutRsts = STAT(OUT_RST); 2211 v6->tcpOutRsts = STAT(OUT_RST);
2208 v6->tcpInSegs = STAT64(IN_SEG); 2212 v6->tcpInSegs = STAT64(IN_SEG);
2209 v6->tcpOutSegs = STAT64(OUT_SEG); 2213 v6->tcpOutSegs = STAT64(OUT_SEG);
@@ -2228,12 +2232,12 @@ void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
2228 int i; 2232 int i;
2229 2233
2230 for (i = 0; i < NMTUS; ++i) { 2234 for (i = 0; i < NMTUS; ++i) {
2231 t4_write_reg(adap, TP_MTU_TABLE, 2235 t4_write_reg(adap, TP_MTU_TABLE_A,
2232 MTUINDEX(0xff) | MTUVALUE(i)); 2236 MTUINDEX_V(0xff) | MTUVALUE_V(i));
2233 v = t4_read_reg(adap, TP_MTU_TABLE); 2237 v = t4_read_reg(adap, TP_MTU_TABLE_A);
2234 mtus[i] = MTUVALUE_GET(v); 2238 mtus[i] = MTUVALUE_G(v);
2235 if (mtu_log) 2239 if (mtu_log)
2236 mtu_log[i] = MTUWIDTH_GET(v); 2240 mtu_log[i] = MTUWIDTH_G(v);
2237 } 2241 }
2238} 2242}
2239 2243
@@ -2249,9 +2253,9 @@ void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
2249void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, 2253void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
2250 unsigned int mask, unsigned int val) 2254 unsigned int mask, unsigned int val)
2251{ 2255{
2252 t4_write_reg(adap, TP_PIO_ADDR, addr); 2256 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
2253 val |= t4_read_reg(adap, TP_PIO_DATA) & ~mask; 2257 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
2254 t4_write_reg(adap, TP_PIO_DATA, val); 2258 t4_write_reg(adap, TP_PIO_DATA_A, val);
2255} 2259}
2256 2260
2257/** 2261/**
@@ -2330,8 +2334,8 @@ void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
2330 2334
2331 if (!(mtu & ((1 << log2) >> 2))) /* round */ 2335 if (!(mtu & ((1 << log2) >> 2))) /* round */
2332 log2--; 2336 log2--;
2333 t4_write_reg(adap, TP_MTU_TABLE, MTUINDEX(i) | 2337 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
2334 MTUWIDTH(log2) | MTUVALUE(mtu)); 2338 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
2335 2339
2336 for (w = 0; w < NCCTRL_WIN; ++w) { 2340 for (w = 0; w < NCCTRL_WIN; ++w) {
2337 unsigned int inc; 2341 unsigned int inc;
@@ -2339,7 +2343,7 @@ void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
2339 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w], 2343 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
2340 CC_MIN_INCR); 2344 CC_MIN_INCR);
2341 2345
2342 t4_write_reg(adap, TP_CCTRL_TABLE, (i << 21) | 2346 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
2343 (w << 16) | (beta[w] << 13) | inc); 2347 (w << 16) | (beta[w] << 13) | inc);
2344 } 2348 }
2345 } 2349 }
@@ -2356,7 +2360,7 @@ void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
2356 */ 2360 */
2357static unsigned int get_mps_bg_map(struct adapter *adap, int idx) 2361static unsigned int get_mps_bg_map(struct adapter *adap, int idx)
2358{ 2362{
2359 u32 n = NUMPORTS_GET(t4_read_reg(adap, MPS_CMN_CTL)); 2363 u32 n = NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
2360 2364
2361 if (n == 0) 2365 if (n == 0)
2362 return idx == 0 ? 0xf : 0; 2366 return idx == 0 ? 0xf : 0;
@@ -2498,7 +2502,7 @@ void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
2498 } else { 2502 } else {
2499 mag_id_reg_l = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_LO); 2503 mag_id_reg_l = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_LO);
2500 mag_id_reg_h = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_HI); 2504 mag_id_reg_h = T5_PORT_REG(port, MAC_PORT_MAGIC_MACID_HI);
2501 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2); 2505 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2_A);
2502 } 2506 }
2503 2507
2504 if (addr) { 2508 if (addr) {
@@ -2536,7 +2540,7 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
2536 if (is_t4(adap->params.chip)) 2540 if (is_t4(adap->params.chip))
2537 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2); 2541 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2);
2538 else 2542 else
2539 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2); 2543 port_cfg_reg = T5_PORT_REG(port, MAC_PORT_CFG2_A);
2540 2544
2541 if (!enable) { 2545 if (!enable) {
2542 t4_set_reg_field(adap, port_cfg_reg, PATEN, 0); 2546 t4_set_reg_field(adap, port_cfg_reg, PATEN, 0);
@@ -2547,7 +2551,7 @@ int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
2547 2551
2548#define EPIO_REG(name) \ 2552#define EPIO_REG(name) \
2549 (is_t4(adap->params.chip) ? PORT_REG(port, XGMAC_PORT_EPIO_##name) : \ 2553 (is_t4(adap->params.chip) ? PORT_REG(port, XGMAC_PORT_EPIO_##name) : \
2550 T5_PORT_REG(port, MAC_PORT_EPIO_##name)) 2554 T5_PORT_REG(port, MAC_PORT_EPIO_##name##_A))
2551 2555
2552 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32); 2556 t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
2553 t4_write_reg(adap, EPIO_REG(DATA2), mask1); 2557 t4_write_reg(adap, EPIO_REG(DATA2), mask1);
@@ -4171,9 +4175,9 @@ int t4_init_tp_params(struct adapter *adap)
4171 int chan; 4175 int chan;
4172 u32 v; 4176 u32 v;
4173 4177
4174 v = t4_read_reg(adap, TP_TIMER_RESOLUTION); 4178 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
4175 adap->params.tp.tre = TIMERRESOLUTION_GET(v); 4179 adap->params.tp.tre = TIMERRESOLUTION_G(v);
4176 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_GET(v); 4180 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
4177 4181
4178 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */ 4182 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4179 for (chan = 0; chan < NCHAN; chan++) 4183 for (chan = 0; chan < NCHAN; chan++)
@@ -4182,12 +4186,12 @@ int t4_init_tp_params(struct adapter *adap)
4182 /* Cache the adapter's Compressed Filter Mode and global Incress 4186 /* Cache the adapter's Compressed Filter Mode and global Incress
4183 * Configuration. 4187 * Configuration.
4184 */ 4188 */
4185 t4_read_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA, 4189 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4186 &adap->params.tp.vlan_pri_map, 1, 4190 &adap->params.tp.vlan_pri_map, 1,
4187 TP_VLAN_PRI_MAP); 4191 TP_VLAN_PRI_MAP_A);
4188 t4_read_indirect(adap, TP_PIO_ADDR, TP_PIO_DATA, 4192 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A,
4189 &adap->params.tp.ingress_config, 1, 4193 &adap->params.tp.ingress_config, 1,
4190 TP_INGRESS_CONFIG); 4194 TP_INGRESS_CONFIG_A);
4191 4195
4192 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field 4196 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4193 * shift positions of several elements of the Compressed Filter Tuple 4197 * shift positions of several elements of the Compressed Filter Tuple
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
index 4b6681812b8a..ec0addc85bb6 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h
@@ -1182,158 +1182,258 @@
1182#define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S) 1182#define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S)
1183#define RSVDSPACEINT_F RSVDSPACEINT_V(1U) 1183#define RSVDSPACEINT_F RSVDSPACEINT_V(1U)
1184 1184
1185#define TP_OUT_CONFIG 0x7d04 1185/* registers for module TP */
1186#define VLANEXTENABLE_MASK 0x0000f000U 1186#define TP_OUT_CONFIG_A 0x7d04
1187#define VLANEXTENABLE_SHIFT 12 1187#define TP_GLOBAL_CONFIG_A 0x7d08
1188 1188
1189#define TP_GLOBAL_CONFIG 0x7d08 1189#define FIVETUPLELOOKUP_S 17
1190#define FIVETUPLELOOKUP_SHIFT 17 1190#define FIVETUPLELOOKUP_M 0x3U
1191#define FIVETUPLELOOKUP_MASK 0x00060000U 1191#define FIVETUPLELOOKUP_V(x) ((x) << FIVETUPLELOOKUP_S)
1192#define FIVETUPLELOOKUP(x) ((x) << FIVETUPLELOOKUP_SHIFT) 1192#define FIVETUPLELOOKUP_G(x) (((x) >> FIVETUPLELOOKUP_S) & FIVETUPLELOOKUP_M)
1193#define FIVETUPLELOOKUP_GET(x) (((x) & FIVETUPLELOOKUP_MASK) >> \ 1193
1194 FIVETUPLELOOKUP_SHIFT) 1194#define TP_PARA_REG2_A 0x7d68
1195 1195
1196#define TP_PARA_REG2 0x7d68 1196#define MAXRXDATA_S 16
1197#define MAXRXDATA_MASK 0xffff0000U 1197#define MAXRXDATA_M 0xffffU
1198#define MAXRXDATA_SHIFT 16 1198#define MAXRXDATA_G(x) (((x) >> MAXRXDATA_S) & MAXRXDATA_M)
1199#define MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT) 1199
1200 1200#define TP_TIMER_RESOLUTION_A 0x7d90
1201#define TP_TIMER_RESOLUTION 0x7d90 1201
1202#define TIMERRESOLUTION_MASK 0x00ff0000U 1202#define TIMERRESOLUTION_S 16
1203#define TIMERRESOLUTION_SHIFT 16 1203#define TIMERRESOLUTION_M 0xffU
1204#define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT) 1204#define TIMERRESOLUTION_G(x) (((x) >> TIMERRESOLUTION_S) & TIMERRESOLUTION_M)
1205#define DELAYEDACKRESOLUTION_MASK 0x000000ffU 1205
1206#define DELAYEDACKRESOLUTION_SHIFT 0 1206#define DELAYEDACKRESOLUTION_S 0
1207#define DELAYEDACKRESOLUTION_GET(x) \ 1207#define DELAYEDACKRESOLUTION_M 0xffU
1208 (((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT) 1208#define DELAYEDACKRESOLUTION_G(x) \
1209 1209 (((x) >> DELAYEDACKRESOLUTION_S) & DELAYEDACKRESOLUTION_M)
1210#define TP_SHIFT_CNT 0x7dc0 1210
1211#define SYNSHIFTMAX_SHIFT 24 1211#define TP_SHIFT_CNT_A 0x7dc0
1212#define SYNSHIFTMAX_MASK 0xff000000U 1212
1213#define SYNSHIFTMAX(x) ((x) << SYNSHIFTMAX_SHIFT) 1213#define SYNSHIFTMAX_S 24
1214#define SYNSHIFTMAX_GET(x) (((x) & SYNSHIFTMAX_MASK) >> \ 1214#define SYNSHIFTMAX_M 0xffU
1215 SYNSHIFTMAX_SHIFT) 1215#define SYNSHIFTMAX_V(x) ((x) << SYNSHIFTMAX_S)
1216#define RXTSHIFTMAXR1_SHIFT 20 1216#define SYNSHIFTMAX_G(x) (((x) >> SYNSHIFTMAX_S) & SYNSHIFTMAX_M)
1217#define RXTSHIFTMAXR1_MASK 0x00f00000U 1217
1218#define RXTSHIFTMAXR1(x) ((x) << RXTSHIFTMAXR1_SHIFT) 1218#define RXTSHIFTMAXR1_S 20
1219#define RXTSHIFTMAXR1_GET(x) (((x) & RXTSHIFTMAXR1_MASK) >> \ 1219#define RXTSHIFTMAXR1_M 0xfU
1220 RXTSHIFTMAXR1_SHIFT) 1220#define RXTSHIFTMAXR1_V(x) ((x) << RXTSHIFTMAXR1_S)
1221#define RXTSHIFTMAXR2_SHIFT 16 1221#define RXTSHIFTMAXR1_G(x) (((x) >> RXTSHIFTMAXR1_S) & RXTSHIFTMAXR1_M)
1222#define RXTSHIFTMAXR2_MASK 0x000f0000U 1222
1223#define RXTSHIFTMAXR2(x) ((x) << RXTSHIFTMAXR2_SHIFT) 1223#define RXTSHIFTMAXR2_S 16
1224#define RXTSHIFTMAXR2_GET(x) (((x) & RXTSHIFTMAXR2_MASK) >> \ 1224#define RXTSHIFTMAXR2_M 0xfU
1225 RXTSHIFTMAXR2_SHIFT) 1225#define RXTSHIFTMAXR2_V(x) ((x) << RXTSHIFTMAXR2_S)
1226#define PERSHIFTBACKOFFMAX_SHIFT 12 1226#define RXTSHIFTMAXR2_G(x) (((x) >> RXTSHIFTMAXR2_S) & RXTSHIFTMAXR2_M)
1227#define PERSHIFTBACKOFFMAX_MASK 0x0000f000U 1227
1228#define PERSHIFTBACKOFFMAX(x) ((x) << PERSHIFTBACKOFFMAX_SHIFT) 1228#define PERSHIFTBACKOFFMAX_S 12
1229#define PERSHIFTBACKOFFMAX_GET(x) (((x) & PERSHIFTBACKOFFMAX_MASK) >> \ 1229#define PERSHIFTBACKOFFMAX_M 0xfU
1230 PERSHIFTBACKOFFMAX_SHIFT) 1230#define PERSHIFTBACKOFFMAX_V(x) ((x) << PERSHIFTBACKOFFMAX_S)
1231#define PERSHIFTMAX_SHIFT 8 1231#define PERSHIFTBACKOFFMAX_G(x) \
1232#define PERSHIFTMAX_MASK 0x00000f00U 1232 (((x) >> PERSHIFTBACKOFFMAX_S) & PERSHIFTBACKOFFMAX_M)
1233#define PERSHIFTMAX(x) ((x) << PERSHIFTMAX_SHIFT) 1233
1234#define PERSHIFTMAX_GET(x) (((x) & PERSHIFTMAX_MASK) >> \ 1234#define PERSHIFTMAX_S 8
1235 PERSHIFTMAX_SHIFT) 1235#define PERSHIFTMAX_M 0xfU
1236#define KEEPALIVEMAXR1_SHIFT 4 1236#define PERSHIFTMAX_V(x) ((x) << PERSHIFTMAX_S)
1237#define KEEPALIVEMAXR1_MASK 0x000000f0U 1237#define PERSHIFTMAX_G(x) (((x) >> PERSHIFTMAX_S) & PERSHIFTMAX_M)
1238#define KEEPALIVEMAXR1(x) ((x) << KEEPALIVEMAXR1_SHIFT) 1238
1239#define KEEPALIVEMAXR1_GET(x) (((x) & KEEPALIVEMAXR1_MASK) >> \ 1239#define KEEPALIVEMAXR1_S 4
1240 KEEPALIVEMAXR1_SHIFT) 1240#define KEEPALIVEMAXR1_M 0xfU
1241#define KEEPALIVEMAXR2_SHIFT 0 1241#define KEEPALIVEMAXR1_V(x) ((x) << KEEPALIVEMAXR1_S)
1242#define KEEPALIVEMAXR2_MASK 0x0000000fU 1242#define KEEPALIVEMAXR1_G(x) (((x) >> KEEPALIVEMAXR1_S) & KEEPALIVEMAXR1_M)
1243#define KEEPALIVEMAXR2(x) ((x) << KEEPALIVEMAXR2_SHIFT) 1243
1244#define KEEPALIVEMAXR2_GET(x) (((x) & KEEPALIVEMAXR2_MASK) >> \ 1244#define KEEPALIVEMAXR2_S 0
1245 KEEPALIVEMAXR2_SHIFT) 1245#define KEEPALIVEMAXR2_M 0xfU
1246 1246#define KEEPALIVEMAXR2_V(x) ((x) << KEEPALIVEMAXR2_S)
1247#define TP_CCTRL_TABLE 0x7ddc 1247#define KEEPALIVEMAXR2_G(x) (((x) >> KEEPALIVEMAXR2_S) & KEEPALIVEMAXR2_M)
1248#define TP_MTU_TABLE 0x7de4 1248
1249#define MTUINDEX_MASK 0xff000000U 1249#define TP_CCTRL_TABLE_A 0x7ddc
1250#define MTUINDEX_SHIFT 24 1250#define TP_MTU_TABLE_A 0x7de4
1251#define MTUINDEX(x) ((x) << MTUINDEX_SHIFT) 1251
1252#define MTUWIDTH_MASK 0x000f0000U 1252#define MTUINDEX_S 24
1253#define MTUWIDTH_SHIFT 16 1253#define MTUINDEX_V(x) ((x) << MTUINDEX_S)
1254#define MTUWIDTH(x) ((x) << MTUWIDTH_SHIFT) 1254
1255#define MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT) 1255#define MTUWIDTH_S 16
1256#define MTUVALUE_MASK 0x00003fffU 1256#define MTUWIDTH_M 0xfU
1257#define MTUVALUE_SHIFT 0 1257#define MTUWIDTH_V(x) ((x) << MTUWIDTH_S)
1258#define MTUVALUE(x) ((x) << MTUVALUE_SHIFT) 1258#define MTUWIDTH_G(x) (((x) >> MTUWIDTH_S) & MTUWIDTH_M)
1259#define MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT) 1259
1260 1260#define MTUVALUE_S 0
1261#define TP_RSS_LKP_TABLE 0x7dec 1261#define MTUVALUE_M 0x3fffU
1262#define LKPTBLROWVLD 0x80000000U 1262#define MTUVALUE_V(x) ((x) << MTUVALUE_S)
1263#define LKPTBLQUEUE1_MASK 0x000ffc00U 1263#define MTUVALUE_G(x) (((x) >> MTUVALUE_S) & MTUVALUE_M)
1264#define LKPTBLQUEUE1_SHIFT 10 1264
1265#define LKPTBLQUEUE1(x) ((x) << LKPTBLQUEUE1_SHIFT) 1265#define TP_RSS_LKP_TABLE_A 0x7dec
1266#define LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT) 1266
1267#define LKPTBLQUEUE0_MASK 0x000003ffU 1267#define LKPTBLROWVLD_S 31
1268#define LKPTBLQUEUE0_SHIFT 0 1268#define LKPTBLROWVLD_V(x) ((x) << LKPTBLROWVLD_S)
1269#define LKPTBLQUEUE0(x) ((x) << LKPTBLQUEUE0_SHIFT) 1269#define LKPTBLROWVLD_F LKPTBLROWVLD_V(1U)
1270#define LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT) 1270
1271 1271#define LKPTBLQUEUE1_S 10
1272#define TP_PIO_ADDR 0x7e40 1272#define LKPTBLQUEUE1_M 0x3ffU
1273#define TP_PIO_DATA 0x7e44 1273#define LKPTBLQUEUE1_G(x) (((x) >> LKPTBLQUEUE1_S) & LKPTBLQUEUE1_M)
1274#define TP_MIB_INDEX 0x7e50 1274
1275#define TP_MIB_DATA 0x7e54 1275#define LKPTBLQUEUE0_S 0
1276#define TP_INT_CAUSE 0x7e74 1276#define LKPTBLQUEUE0_M 0x3ffU
1277#define FLMTXFLSTEMPTY 0x40000000U 1277#define LKPTBLQUEUE0_G(x) (((x) >> LKPTBLQUEUE0_S) & LKPTBLQUEUE0_M)
1278 1278
1279#define TP_VLAN_PRI_MAP 0x140 1279#define TP_PIO_ADDR_A 0x7e40
1280#define FRAGMENTATION_SHIFT 9 1280#define TP_PIO_DATA_A 0x7e44
1281#define FRAGMENTATION_MASK 0x00000200U 1281#define TP_MIB_INDEX_A 0x7e50
1282#define MPSHITTYPE_MASK 0x00000100U 1282#define TP_MIB_DATA_A 0x7e54
1283#define MACMATCH_MASK 0x00000080U 1283#define TP_INT_CAUSE_A 0x7e74
1284#define ETHERTYPE_MASK 0x00000040U 1284
1285#define PROTOCOL_MASK 0x00000020U 1285#define FLMTXFLSTEMPTY_S 30
1286#define TOS_MASK 0x00000010U 1286#define FLMTXFLSTEMPTY_V(x) ((x) << FLMTXFLSTEMPTY_S)
1287#define VLAN_MASK 0x00000008U 1287#define FLMTXFLSTEMPTY_F FLMTXFLSTEMPTY_V(1U)
1288#define VNIC_ID_MASK 0x00000004U 1288
1289#define PORT_MASK 0x00000002U 1289#define TP_VLAN_PRI_MAP_A 0x140
1290#define FCOE_SHIFT 0 1290
1291#define FCOE_MASK 0x00000001U 1291#define FRAGMENTATION_S 9
1292 1292#define FRAGMENTATION_V(x) ((x) << FRAGMENTATION_S)
1293#define TP_INGRESS_CONFIG 0x141 1293#define FRAGMENTATION_F FRAGMENTATION_V(1U)
1294#define VNIC 0x00000800U 1294
1295#define CSUM_HAS_PSEUDO_HDR 0x00000400U 1295#define MPSHITTYPE_S 8
1296#define RM_OVLAN 0x00000200U 1296#define MPSHITTYPE_V(x) ((x) << MPSHITTYPE_S)
1297#define LOOKUPEVERYPKT 0x00000100U 1297#define MPSHITTYPE_F MPSHITTYPE_V(1U)
1298 1298
1299#define TP_MIB_MAC_IN_ERR_0 0x0 1299#define MACMATCH_S 7
1300#define TP_MIB_TCP_OUT_RST 0xc 1300#define MACMATCH_V(x) ((x) << MACMATCH_S)
1301#define TP_MIB_TCP_IN_SEG_HI 0x10 1301#define MACMATCH_F MACMATCH_V(1U)
1302#define TP_MIB_TCP_IN_SEG_LO 0x11 1302
1303#define TP_MIB_TCP_OUT_SEG_HI 0x12 1303#define ETHERTYPE_S 6
1304#define TP_MIB_TCP_OUT_SEG_LO 0x13 1304#define ETHERTYPE_V(x) ((x) << ETHERTYPE_S)
1305#define TP_MIB_TCP_RXT_SEG_HI 0x14 1305#define ETHERTYPE_F ETHERTYPE_V(1U)
1306#define TP_MIB_TCP_RXT_SEG_LO 0x15 1306
1307#define TP_MIB_TNL_CNG_DROP_0 0x18 1307#define PROTOCOL_S 5
1308#define TP_MIB_TCP_V6IN_ERR_0 0x28 1308#define PROTOCOL_V(x) ((x) << PROTOCOL_S)
1309#define TP_MIB_TCP_V6OUT_RST 0x2c 1309#define PROTOCOL_F PROTOCOL_V(1U)
1310#define TP_MIB_OFD_ARP_DROP 0x36 1310
1311#define TP_MIB_TNL_DROP_0 0x44 1311#define TOS_S 4
1312#define TP_MIB_OFD_VLN_DROP_0 0x58 1312#define TOS_V(x) ((x) << TOS_S)
1313 1313#define TOS_F TOS_V(1U)
1314#define ULP_TX_INT_CAUSE 0x8dcc 1314
1315#define PBL_BOUND_ERR_CH3 0x80000000U 1315#define VLAN_S 3
1316#define PBL_BOUND_ERR_CH2 0x40000000U 1316#define VLAN_V(x) ((x) << VLAN_S)
1317#define PBL_BOUND_ERR_CH1 0x20000000U 1317#define VLAN_F VLAN_V(1U)
1318#define PBL_BOUND_ERR_CH0 0x10000000U 1318
1319 1319#define VNIC_ID_S 2
1320#define PM_RX_INT_CAUSE 0x8fdc 1320#define VNIC_ID_V(x) ((x) << VNIC_ID_S)
1321#define ZERO_E_CMD_ERROR 0x00400000U 1321#define VNIC_ID_F VNIC_ID_V(1U)
1322#define PMRX_FRAMING_ERROR 0x003ffff0U 1322
1323#define OCSPI_PAR_ERROR 0x00000008U 1323#define PORT_S 1
1324#define DB_OPTIONS_PAR_ERROR 0x00000004U 1324#define PORT_V(x) ((x) << PORT_S)
1325#define IESPI_PAR_ERROR 0x00000002U 1325#define PORT_F PORT_V(1U)
1326#define E_PCMD_PAR_ERROR 0x00000001U 1326
1327 1327#define FCOE_S 0
1328#define PM_TX_INT_CAUSE 0x8ffc 1328#define FCOE_V(x) ((x) << FCOE_S)
1329#define PCMD_LEN_OVFL0 0x80000000U 1329#define FCOE_F FCOE_V(1U)
1330#define PCMD_LEN_OVFL1 0x40000000U 1330
1331#define PCMD_LEN_OVFL2 0x20000000U 1331#define FILTERMODE_S 15
1332#define ZERO_C_CMD_ERROR 0x10000000U 1332#define FILTERMODE_V(x) ((x) << FILTERMODE_S)
1333#define PMTX_FRAMING_ERROR 0x0ffffff0U 1333#define FILTERMODE_F FILTERMODE_V(1U)
1334#define OESPI_PAR_ERROR 0x00000008U 1334
1335#define ICSPI_PAR_ERROR 0x00000002U 1335#define FCOEMASK_S 14
1336#define C_PCMD_PAR_ERROR 0x00000001U 1336#define FCOEMASK_V(x) ((x) << FCOEMASK_S)
1337#define FCOEMASK_F FCOEMASK_V(1U)
1338
1339#define TP_INGRESS_CONFIG_A 0x141
1340
1341#define VNIC_S 11
1342#define VNIC_V(x) ((x) << VNIC_S)
1343#define VNIC_F VNIC_V(1U)
1344
1345#define CSUM_HAS_PSEUDO_HDR_S 10
1346#define CSUM_HAS_PSEUDO_HDR_V(x) ((x) << CSUM_HAS_PSEUDO_HDR_S)
1347#define CSUM_HAS_PSEUDO_HDR_F CSUM_HAS_PSEUDO_HDR_V(1U)
1348
1349#define TP_MIB_MAC_IN_ERR_0_A 0x0
1350#define TP_MIB_TCP_OUT_RST_A 0xc
1351#define TP_MIB_TCP_IN_SEG_HI_A 0x10
1352#define TP_MIB_TCP_IN_SEG_LO_A 0x11
1353#define TP_MIB_TCP_OUT_SEG_HI_A 0x12
1354#define TP_MIB_TCP_OUT_SEG_LO_A 0x13
1355#define TP_MIB_TCP_RXT_SEG_HI_A 0x14
1356#define TP_MIB_TCP_RXT_SEG_LO_A 0x15
1357#define TP_MIB_TNL_CNG_DROP_0_A 0x18
1358#define TP_MIB_TCP_V6IN_ERR_0_A 0x28
1359#define TP_MIB_TCP_V6OUT_RST_A 0x2c
1360#define TP_MIB_OFD_ARP_DROP_A 0x36
1361#define TP_MIB_TNL_DROP_0_A 0x44
1362#define TP_MIB_OFD_VLN_DROP_0_A 0x58
1363
1364#define ULP_TX_INT_CAUSE_A 0x8dcc
1365
1366#define PBL_BOUND_ERR_CH3_S 31
1367#define PBL_BOUND_ERR_CH3_V(x) ((x) << PBL_BOUND_ERR_CH3_S)
1368#define PBL_BOUND_ERR_CH3_F PBL_BOUND_ERR_CH3_V(1U)
1369
1370#define PBL_BOUND_ERR_CH2_S 30
1371#define PBL_BOUND_ERR_CH2_V(x) ((x) << PBL_BOUND_ERR_CH2_S)
1372#define PBL_BOUND_ERR_CH2_F PBL_BOUND_ERR_CH2_V(1U)
1373
1374#define PBL_BOUND_ERR_CH1_S 29
1375#define PBL_BOUND_ERR_CH1_V(x) ((x) << PBL_BOUND_ERR_CH1_S)
1376#define PBL_BOUND_ERR_CH1_F PBL_BOUND_ERR_CH1_V(1U)
1377
1378#define PBL_BOUND_ERR_CH0_S 28
1379#define PBL_BOUND_ERR_CH0_V(x) ((x) << PBL_BOUND_ERR_CH0_S)
1380#define PBL_BOUND_ERR_CH0_F PBL_BOUND_ERR_CH0_V(1U)
1381
1382#define PM_RX_INT_CAUSE_A 0x8fdc
1383
1384#define PMRX_FRAMING_ERROR_F 0x003ffff0U
1385
1386#define ZERO_E_CMD_ERROR_S 22
1387#define ZERO_E_CMD_ERROR_V(x) ((x) << ZERO_E_CMD_ERROR_S)
1388#define ZERO_E_CMD_ERROR_F ZERO_E_CMD_ERROR_V(1U)
1389
1390#define OCSPI_PAR_ERROR_S 3
1391#define OCSPI_PAR_ERROR_V(x) ((x) << OCSPI_PAR_ERROR_S)
1392#define OCSPI_PAR_ERROR_F OCSPI_PAR_ERROR_V(1U)
1393
1394#define DB_OPTIONS_PAR_ERROR_S 2
1395#define DB_OPTIONS_PAR_ERROR_V(x) ((x) << DB_OPTIONS_PAR_ERROR_S)
1396#define DB_OPTIONS_PAR_ERROR_F DB_OPTIONS_PAR_ERROR_V(1U)
1397
1398#define IESPI_PAR_ERROR_S 1
1399#define IESPI_PAR_ERROR_V(x) ((x) << IESPI_PAR_ERROR_S)
1400#define IESPI_PAR_ERROR_F IESPI_PAR_ERROR_V(1U)
1401
1402#define PMRX_E_PCMD_PAR_ERROR_S 0
1403#define PMRX_E_PCMD_PAR_ERROR_V(x) ((x) << PMRX_E_PCMD_PAR_ERROR_S)
1404#define PMRX_E_PCMD_PAR_ERROR_F PMRX_E_PCMD_PAR_ERROR_V(1U)
1405
1406#define PM_TX_INT_CAUSE_A 0x8ffc
1407
1408#define PCMD_LEN_OVFL0_S 31
1409#define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S)
1410#define PCMD_LEN_OVFL0_F PCMD_LEN_OVFL0_V(1U)
1411
1412#define PCMD_LEN_OVFL1_S 30
1413#define PCMD_LEN_OVFL1_V(x) ((x) << PCMD_LEN_OVFL1_S)
1414#define PCMD_LEN_OVFL1_F PCMD_LEN_OVFL1_V(1U)
1415
1416#define PCMD_LEN_OVFL2_S 29
1417#define PCMD_LEN_OVFL2_V(x) ((x) << PCMD_LEN_OVFL2_S)
1418#define PCMD_LEN_OVFL2_F PCMD_LEN_OVFL2_V(1U)
1419
1420#define ZERO_C_CMD_ERROR_S 28
1421#define ZERO_C_CMD_ERROR_V(x) ((x) << ZERO_C_CMD_ERROR_S)
1422#define ZERO_C_CMD_ERROR_F ZERO_C_CMD_ERROR_V(1U)
1423
1424#define PMTX_FRAMING_ERROR_F 0x0ffffff0U
1425
1426#define OESPI_PAR_ERROR_S 3
1427#define OESPI_PAR_ERROR_V(x) ((x) << OESPI_PAR_ERROR_S)
1428#define OESPI_PAR_ERROR_F OESPI_PAR_ERROR_V(1U)
1429
1430#define ICSPI_PAR_ERROR_S 1
1431#define ICSPI_PAR_ERROR_V(x) ((x) << ICSPI_PAR_ERROR_S)
1432#define ICSPI_PAR_ERROR_F ICSPI_PAR_ERROR_V(1U)
1433
1434#define PMTX_C_PCMD_PAR_ERROR_S 0
1435#define PMTX_C_PCMD_PAR_ERROR_V(x) ((x) << PMTX_C_PCMD_PAR_ERROR_S)
1436#define PMTX_C_PCMD_PAR_ERROR_F PMTX_C_PCMD_PAR_ERROR_V(1U)
1337 1437
1338#define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 1438#define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
1339#define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 1439#define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
@@ -1462,41 +1562,57 @@
1462#define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c 1562#define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
1463#define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 1563#define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
1464#define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 1564#define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
1465#define MAC_PORT_CFG2 0x818
1466#define MAC_PORT_MAGIC_MACID_LO 0x824 1565#define MAC_PORT_MAGIC_MACID_LO 0x824
1467#define MAC_PORT_MAGIC_MACID_HI 0x828 1566#define MAC_PORT_MAGIC_MACID_HI 0x828
1468#define MAC_PORT_EPIO_DATA0 0x8c0 1567
1469#define MAC_PORT_EPIO_DATA1 0x8c4 1568#define MAC_PORT_EPIO_DATA0_A 0x8c0
1470#define MAC_PORT_EPIO_DATA2 0x8c8 1569#define MAC_PORT_EPIO_DATA1_A 0x8c4
1471#define MAC_PORT_EPIO_DATA3 0x8cc 1570#define MAC_PORT_EPIO_DATA2_A 0x8c8
1472#define MAC_PORT_EPIO_OP 0x8d0 1571#define MAC_PORT_EPIO_DATA3_A 0x8cc
1473 1572#define MAC_PORT_EPIO_OP_A 0x8d0
1474#define MPS_CMN_CTL 0x9000 1573
1475#define NUMPORTS_MASK 0x00000003U 1574#define MAC_PORT_CFG2_A 0x818
1476#define NUMPORTS_SHIFT 0 1575
1477#define NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT) 1576#define MPS_CMN_CTL_A 0x9000
1478 1577
1479#define MPS_INT_CAUSE 0x9008 1578#define NUMPORTS_S 0
1480#define STATINT 0x00000020U 1579#define NUMPORTS_M 0x3U
1481#define TXINT 0x00000010U 1580#define NUMPORTS_G(x) (((x) >> NUMPORTS_S) & NUMPORTS_M)
1482#define RXINT 0x00000008U 1581
1483#define TRCINT 0x00000004U 1582#define MPS_INT_CAUSE_A 0x9008
1484#define CLSINT 0x00000002U 1583#define MPS_TX_INT_CAUSE_A 0x9408
1485#define PLINT 0x00000001U 1584
1486 1585#define FRMERR_S 15
1487#define MPS_TX_INT_CAUSE 0x9408 1586#define FRMERR_V(x) ((x) << FRMERR_S)
1488#define PORTERR 0x00010000U 1587#define FRMERR_F FRMERR_V(1U)
1489#define FRMERR 0x00008000U 1588
1490#define SECNTERR 0x00004000U 1589#define SECNTERR_S 14
1491#define BUBBLE 0x00002000U 1590#define SECNTERR_V(x) ((x) << SECNTERR_S)
1492#define TXDESCFIFO 0x00001e00U 1591#define SECNTERR_F SECNTERR_V(1U)
1493#define TXDATAFIFO 0x000001e0U 1592
1494#define NCSIFIFO 0x00000010U 1593#define BUBBLE_S 13
1495#define TPFIFO 0x0000000fU 1594#define BUBBLE_V(x) ((x) << BUBBLE_S)
1496 1595#define BUBBLE_F BUBBLE_V(1U)
1497#define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614 1596
1498#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620 1597#define TXDESCFIFO_S 9
1499#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c 1598#define TXDESCFIFO_M 0xfU
1599#define TXDESCFIFO_V(x) ((x) << TXDESCFIFO_S)
1600
1601#define TXDATAFIFO_S 5
1602#define TXDATAFIFO_M 0xfU
1603#define TXDATAFIFO_V(x) ((x) << TXDATAFIFO_S)
1604
1605#define NCSIFIFO_S 4
1606#define NCSIFIFO_V(x) ((x) << NCSIFIFO_S)
1607#define NCSIFIFO_F NCSIFIFO_V(1U)
1608
1609#define TPFIFO_S 0
1610#define TPFIFO_M 0xfU
1611#define TPFIFO_V(x) ((x) << TPFIFO_S)
1612
1613#define MPS_STAT_PERR_INT_CAUSE_SRAM_A 0x9614
1614#define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A 0x9620
1615#define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A 0x962c
1500 1616
1501#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 1617#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
1502#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 1618#define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
@@ -1530,66 +1646,67 @@
1530#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 1646#define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
1531#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 1647#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
1532#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc 1648#define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
1533#define MPS_TRC_CFG 0x9800 1649
1534#define TRCFIFOEMPTY 0x00000010U 1650#define MPS_TRC_CFG_A 0x9800
1535#define TRCIGNOREDROPINPUT 0x00000008U 1651
1536#define TRCKEEPDUPLICATES 0x00000004U 1652#define TRCFIFOEMPTY_S 4
1537#define TRCEN 0x00000002U 1653#define TRCFIFOEMPTY_V(x) ((x) << TRCFIFOEMPTY_S)
1538#define TRCMULTIFILTER 0x00000001U 1654#define TRCFIFOEMPTY_F TRCFIFOEMPTY_V(1U)
1539 1655
1540#define MPS_TRC_RSS_CONTROL 0x9808 1656#define TRCIGNOREDROPINPUT_S 3
1541#define MPS_T5_TRC_RSS_CONTROL 0xa00c 1657#define TRCIGNOREDROPINPUT_V(x) ((x) << TRCIGNOREDROPINPUT_S)
1542#define RSSCONTROL_MASK 0x00ff0000U 1658#define TRCIGNOREDROPINPUT_F TRCIGNOREDROPINPUT_V(1U)
1543#define RSSCONTROL_SHIFT 16 1659
1544#define RSSCONTROL(x) ((x) << RSSCONTROL_SHIFT) 1660#define TRCKEEPDUPLICATES_S 2
1545#define QUEUENUMBER_MASK 0x0000ffffU 1661#define TRCKEEPDUPLICATES_V(x) ((x) << TRCKEEPDUPLICATES_S)
1546#define QUEUENUMBER_SHIFT 0 1662#define TRCKEEPDUPLICATES_F TRCKEEPDUPLICATES_V(1U)
1547#define QUEUENUMBER(x) ((x) << QUEUENUMBER_SHIFT) 1663
1548 1664#define TRCEN_S 1
1549#define MPS_TRC_FILTER_MATCH_CTL_A 0x9810 1665#define TRCEN_V(x) ((x) << TRCEN_S)
1550#define TFINVERTMATCH 0x01000000U 1666#define TRCEN_F TRCEN_V(1U)
1551#define TFPKTTOOLARGE 0x00800000U 1667
1552#define TFEN 0x00400000U 1668#define TRCMULTIFILTER_S 0
1553#define TFPORT_MASK 0x003c0000U 1669#define TRCMULTIFILTER_V(x) ((x) << TRCMULTIFILTER_S)
1554#define TFPORT_SHIFT 18 1670#define TRCMULTIFILTER_F TRCMULTIFILTER_V(1U)
1555#define TFPORT(x) ((x) << TFPORT_SHIFT) 1671
1556#define TFPORT_GET(x) (((x) & TFPORT_MASK) >> TFPORT_SHIFT) 1672#define MPS_TRC_RSS_CONTROL_A 0x9808
1557#define TFDROP 0x00020000U 1673#define MPS_T5_TRC_RSS_CONTROL_A 0xa00c
1558#define TFSOPEOPERR 0x00010000U 1674
1559#define TFLENGTH_MASK 0x00001f00U 1675#define RSSCONTROL_S 16
1560#define TFLENGTH_SHIFT 8 1676#define RSSCONTROL_V(x) ((x) << RSSCONTROL_S)
1561#define TFLENGTH(x) ((x) << TFLENGTH_SHIFT) 1677
1562#define TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT) 1678#define QUEUENUMBER_S 0
1563#define TFOFFSET_MASK 0x0000001fU 1679#define QUEUENUMBER_V(x) ((x) << QUEUENUMBER_S)
1564#define TFOFFSET_SHIFT 0 1680
1565#define TFOFFSET(x) ((x) << TFOFFSET_SHIFT) 1681#define MPS_TRC_INT_CAUSE_A 0x985c
1566#define TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT) 1682
1567 1683#define MISCPERR_S 8
1568#define MPS_TRC_FILTER_MATCH_CTL_B 0x9820 1684#define MISCPERR_V(x) ((x) << MISCPERR_S)
1569#define TFMINPKTSIZE_MASK 0x01ff0000U 1685#define MISCPERR_F MISCPERR_V(1U)
1570#define TFMINPKTSIZE_SHIFT 16 1686
1571#define TFMINPKTSIZE(x) ((x) << TFMINPKTSIZE_SHIFT) 1687#define PKTFIFO_S 4
1572#define TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT) 1688#define PKTFIFO_M 0xfU
1573#define TFCAPTUREMAX_MASK 0x00003fffU 1689#define PKTFIFO_V(x) ((x) << PKTFIFO_S)
1574#define TFCAPTUREMAX_SHIFT 0 1690
1575#define TFCAPTUREMAX(x) ((x) << TFCAPTUREMAX_SHIFT) 1691#define FILTMEM_S 0
1576#define TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT) 1692#define FILTMEM_M 0xfU
1577 1693#define FILTMEM_V(x) ((x) << FILTMEM_S)
1578#define MPS_TRC_INT_CAUSE 0x985c 1694
1579#define MISCPERR 0x00000100U 1695#define MPS_CLS_INT_CAUSE_A 0xd028
1580#define PKTFIFO 0x000000f0U 1696
1581#define FILTMEM 0x0000000fU 1697#define HASHSRAM_S 2
1582 1698#define HASHSRAM_V(x) ((x) << HASHSRAM_S)
1583#define MPS_TRC_FILTER0_MATCH 0x9c00 1699#define HASHSRAM_F HASHSRAM_V(1U)
1584#define MPS_TRC_FILTER0_DONT_CARE 0x9c80 1700
1585#define MPS_TRC_FILTER1_MATCH 0x9d00 1701#define MATCHTCAM_S 1
1586#define MPS_CLS_INT_CAUSE 0xd028 1702#define MATCHTCAM_V(x) ((x) << MATCHTCAM_S)
1587#define PLERRENB 0x00000008U 1703#define MATCHTCAM_F MATCHTCAM_V(1U)
1588#define HASHSRAM 0x00000004U 1704
1589#define MATCHTCAM 0x00000002U 1705#define MATCHSRAM_S 0
1590#define MATCHSRAM 0x00000001U 1706#define MATCHSRAM_V(x) ((x) << MATCHSRAM_S)
1591 1707#define MATCHSRAM_F MATCHSRAM_V(1U)
1592#define MPS_RX_PERR_INT_CAUSE 0x11074 1708
1709#define MPS_RX_PERR_INT_CAUSE_A 0x11074
1593 1710
1594#define CPL_INTR_CAUSE 0x19054 1711#define CPL_INTR_CAUSE 0x19054
1595#define CIM_OP_MAP_PERR 0x00000020U 1712#define CIM_OP_MAP_PERR 0x00000020U
diff --git a/drivers/scsi/csiostor/csio_hw.c b/drivers/scsi/csiostor/csio_hw.c
index 257dc8d56510..c641931d4ae1 100644
--- a/drivers/scsi/csiostor/csio_hw.c
+++ b/drivers/scsi/csiostor/csio_hw.c
@@ -188,9 +188,9 @@ void
188csio_hw_tp_wr_bits_indirect(struct csio_hw *hw, unsigned int addr, 188csio_hw_tp_wr_bits_indirect(struct csio_hw *hw, unsigned int addr,
189 unsigned int mask, unsigned int val) 189 unsigned int mask, unsigned int val)
190{ 190{
191 csio_wr_reg32(hw, addr, TP_PIO_ADDR); 191 csio_wr_reg32(hw, addr, TP_PIO_ADDR_A);
192 val |= csio_rd_reg32(hw, TP_PIO_DATA) & ~mask; 192 val |= csio_rd_reg32(hw, TP_PIO_DATA_A) & ~mask;
193 csio_wr_reg32(hw, val, TP_PIO_DATA); 193 csio_wr_reg32(hw, val, TP_PIO_DATA_A);
194} 194}
195 195
196void 196void
@@ -2683,11 +2683,11 @@ static void csio_tp_intr_handler(struct csio_hw *hw)
2683{ 2683{
2684 static struct intr_info tp_intr_info[] = { 2684 static struct intr_info tp_intr_info[] = {
2685 { 0x3fffffff, "TP parity error", -1, 1 }, 2685 { 0x3fffffff, "TP parity error", -1, 1 },
2686 { FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, 2686 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
2687 { 0, NULL, 0, 0 } 2687 { 0, NULL, 0, 0 }
2688 }; 2688 };
2689 2689
2690 if (csio_handle_intr_status(hw, TP_INT_CAUSE, tp_intr_info)) 2690 if (csio_handle_intr_status(hw, TP_INT_CAUSE_A, tp_intr_info))
2691 csio_hw_fatal_err(hw); 2691 csio_hw_fatal_err(hw);
2692} 2692}
2693 2693
@@ -2824,19 +2824,19 @@ static void csio_ulprx_intr_handler(struct csio_hw *hw)
2824static void csio_ulptx_intr_handler(struct csio_hw *hw) 2824static void csio_ulptx_intr_handler(struct csio_hw *hw)
2825{ 2825{
2826 static struct intr_info ulptx_intr_info[] = { 2826 static struct intr_info ulptx_intr_info[] = {
2827 { PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1, 2827 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
2828 0 }, 2828 0 },
2829 { PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1, 2829 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
2830 0 }, 2830 0 },
2831 { PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1, 2831 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
2832 0 }, 2832 0 },
2833 { PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1, 2833 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
2834 0 }, 2834 0 },
2835 { 0xfffffff, "ULPTX parity error", -1, 1 }, 2835 { 0xfffffff, "ULPTX parity error", -1, 1 },
2836 { 0, NULL, 0, 0 } 2836 { 0, NULL, 0, 0 }
2837 }; 2837 };
2838 2838
2839 if (csio_handle_intr_status(hw, ULP_TX_INT_CAUSE, ulptx_intr_info)) 2839 if (csio_handle_intr_status(hw, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
2840 csio_hw_fatal_err(hw); 2840 csio_hw_fatal_err(hw);
2841} 2841}
2842 2842
@@ -2846,20 +2846,20 @@ static void csio_ulptx_intr_handler(struct csio_hw *hw)
2846static void csio_pmtx_intr_handler(struct csio_hw *hw) 2846static void csio_pmtx_intr_handler(struct csio_hw *hw)
2847{ 2847{
2848 static struct intr_info pmtx_intr_info[] = { 2848 static struct intr_info pmtx_intr_info[] = {
2849 { PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 }, 2849 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
2850 { PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 }, 2850 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
2851 { PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 }, 2851 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
2852 { ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 }, 2852 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
2853 { 0xffffff0, "PMTX framing error", -1, 1 }, 2853 { 0xffffff0, "PMTX framing error", -1, 1 },
2854 { OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 }, 2854 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
2855 { DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 2855 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error", -1,
2856 1 }, 2856 1 },
2857 { ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 }, 2857 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
2858 { C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1}, 2858 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
2859 { 0, NULL, 0, 0 } 2859 { 0, NULL, 0, 0 }
2860 }; 2860 };
2861 2861
2862 if (csio_handle_intr_status(hw, PM_TX_INT_CAUSE, pmtx_intr_info)) 2862 if (csio_handle_intr_status(hw, PM_TX_INT_CAUSE_A, pmtx_intr_info))
2863 csio_hw_fatal_err(hw); 2863 csio_hw_fatal_err(hw);
2864} 2864}
2865 2865
@@ -2869,17 +2869,17 @@ static void csio_pmtx_intr_handler(struct csio_hw *hw)
2869static void csio_pmrx_intr_handler(struct csio_hw *hw) 2869static void csio_pmrx_intr_handler(struct csio_hw *hw)
2870{ 2870{
2871 static struct intr_info pmrx_intr_info[] = { 2871 static struct intr_info pmrx_intr_info[] = {
2872 { ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, 2872 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
2873 { 0x3ffff0, "PMRX framing error", -1, 1 }, 2873 { 0x3ffff0, "PMRX framing error", -1, 1 },
2874 { OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 }, 2874 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
2875 { DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 2875 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error", -1,
2876 1 }, 2876 1 },
2877 { IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 }, 2877 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
2878 { E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1}, 2878 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
2879 { 0, NULL, 0, 0 } 2879 { 0, NULL, 0, 0 }
2880 }; 2880 };
2881 2881
2882 if (csio_handle_intr_status(hw, PM_RX_INT_CAUSE, pmrx_intr_info)) 2882 if (csio_handle_intr_status(hw, PM_RX_INT_CAUSE_A, pmrx_intr_info))
2883 csio_hw_fatal_err(hw); 2883 csio_hw_fatal_err(hw);
2884} 2884}
2885 2885
@@ -2930,19 +2930,22 @@ static void csio_mps_intr_handler(struct csio_hw *hw)
2930 { 0, NULL, 0, 0 } 2930 { 0, NULL, 0, 0 }
2931 }; 2931 };
2932 static struct intr_info mps_tx_intr_info[] = { 2932 static struct intr_info mps_tx_intr_info[] = {
2933 { TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 }, 2933 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
2934 { NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 }, 2934 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
2935 { TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 }, 2935 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
2936 { TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 }, 2936 -1, 1 },
2937 { BUBBLE, "MPS Tx underflow", -1, 1 }, 2937 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
2938 { SECNTERR, "MPS Tx SOP/EOP error", -1, 1 }, 2938 -1, 1 },
2939 { FRMERR, "MPS Tx framing error", -1, 1 }, 2939 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
2940 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
2941 { FRMERR_F, "MPS Tx framing error", -1, 1 },
2940 { 0, NULL, 0, 0 } 2942 { 0, NULL, 0, 0 }
2941 }; 2943 };
2942 static struct intr_info mps_trc_intr_info[] = { 2944 static struct intr_info mps_trc_intr_info[] = {
2943 { FILTMEM, "MPS TRC filter parity error", -1, 1 }, 2945 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
2944 { PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 }, 2946 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
2945 { MISCPERR, "MPS TRC misc parity error", -1, 1 }, 2947 -1, 1 },
2948 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
2946 { 0, NULL, 0, 0 } 2949 { 0, NULL, 0, 0 }
2947 }; 2950 };
2948 static struct intr_info mps_stat_sram_intr_info[] = { 2951 static struct intr_info mps_stat_sram_intr_info[] = {
@@ -2958,31 +2961,31 @@ static void csio_mps_intr_handler(struct csio_hw *hw)
2958 { 0, NULL, 0, 0 } 2961 { 0, NULL, 0, 0 }
2959 }; 2962 };
2960 static struct intr_info mps_cls_intr_info[] = { 2963 static struct intr_info mps_cls_intr_info[] = {
2961 { MATCHSRAM, "MPS match SRAM parity error", -1, 1 }, 2964 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
2962 { MATCHTCAM, "MPS match TCAM parity error", -1, 1 }, 2965 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
2963 { HASHSRAM, "MPS hash SRAM parity error", -1, 1 }, 2966 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
2964 { 0, NULL, 0, 0 } 2967 { 0, NULL, 0, 0 }
2965 }; 2968 };
2966 2969
2967 int fat; 2970 int fat;
2968 2971
2969 fat = csio_handle_intr_status(hw, MPS_RX_PERR_INT_CAUSE, 2972 fat = csio_handle_intr_status(hw, MPS_RX_PERR_INT_CAUSE_A,
2970 mps_rx_intr_info) + 2973 mps_rx_intr_info) +
2971 csio_handle_intr_status(hw, MPS_TX_INT_CAUSE, 2974 csio_handle_intr_status(hw, MPS_TX_INT_CAUSE_A,
2972 mps_tx_intr_info) + 2975 mps_tx_intr_info) +
2973 csio_handle_intr_status(hw, MPS_TRC_INT_CAUSE, 2976 csio_handle_intr_status(hw, MPS_TRC_INT_CAUSE_A,
2974 mps_trc_intr_info) + 2977 mps_trc_intr_info) +
2975 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_SRAM, 2978 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
2976 mps_stat_sram_intr_info) + 2979 mps_stat_sram_intr_info) +
2977 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 2980 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
2978 mps_stat_tx_intr_info) + 2981 mps_stat_tx_intr_info) +
2979 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 2982 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
2980 mps_stat_rx_intr_info) + 2983 mps_stat_rx_intr_info) +
2981 csio_handle_intr_status(hw, MPS_CLS_INT_CAUSE, 2984 csio_handle_intr_status(hw, MPS_CLS_INT_CAUSE_A,
2982 mps_cls_intr_info); 2985 mps_cls_intr_info);
2983 2986
2984 csio_wr_reg32(hw, 0, MPS_INT_CAUSE); 2987 csio_wr_reg32(hw, 0, MPS_INT_CAUSE_A);
2985 csio_rd_reg32(hw, MPS_INT_CAUSE); /* flush */ 2988 csio_rd_reg32(hw, MPS_INT_CAUSE_A); /* flush */
2986 if (fat) 2989 if (fat)
2987 csio_hw_fatal_err(hw); 2990 csio_hw_fatal_err(hw);
2988} 2991}
diff --git a/drivers/scsi/csiostor/csio_wr.c b/drivers/scsi/csiostor/csio_wr.c
index 12697c6f2519..e22503b011cd 100644
--- a/drivers/scsi/csiostor/csio_wr.c
+++ b/drivers/scsi/csiostor/csio_wr.c
@@ -1350,8 +1350,8 @@ csio_wr_fixup_host_params(struct csio_hw *hw)
1350 PKTSHIFT_V(PKTSHIFT_M), 1350 PKTSHIFT_V(PKTSHIFT_M),
1351 PKTSHIFT_V(CSIO_SGE_RX_DMA_OFFSET)); 1351 PKTSHIFT_V(CSIO_SGE_RX_DMA_OFFSET));
1352 1352
1353 csio_hw_tp_wr_bits_indirect(hw, TP_INGRESS_CONFIG, 1353 csio_hw_tp_wr_bits_indirect(hw, TP_INGRESS_CONFIG_A,
1354 CSUM_HAS_PSEUDO_HDR, 0); 1354 CSUM_HAS_PSEUDO_HDR_F, 0);
1355} 1355}
1356 1356
1357static void 1357static void
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-27 12:37:52 -0400