diff options
Diffstat (limited to 'drivers/net/ethernet/chelsio/cxgb4/t4_regs.h')
-rw-r--r-- | drivers/net/ethernet/chelsio/cxgb4/t4_regs.h | 607 |
1 files changed, 362 insertions, 245 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h index 4b6681812b8a..ec0addc85bb6 100644 --- a/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h +++ b/drivers/net/ethernet/chelsio/cxgb4/t4_regs.h | |||
@@ -1182,158 +1182,258 @@ | |||
1182 | #define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S) | 1182 | #define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S) |
1183 | #define RSVDSPACEINT_F RSVDSPACEINT_V(1U) | 1183 | #define RSVDSPACEINT_F RSVDSPACEINT_V(1U) |
1184 | 1184 | ||
1185 | #define TP_OUT_CONFIG 0x7d04 | 1185 | /* registers for module TP */ |
1186 | #define VLANEXTENABLE_MASK 0x0000f000U | 1186 | #define TP_OUT_CONFIG_A 0x7d04 |
1187 | #define VLANEXTENABLE_SHIFT 12 | 1187 | #define TP_GLOBAL_CONFIG_A 0x7d08 |
1188 | 1188 | ||
1189 | #define TP_GLOBAL_CONFIG 0x7d08 | 1189 | #define FIVETUPLELOOKUP_S 17 |
1190 | #define FIVETUPLELOOKUP_SHIFT 17 | 1190 | #define FIVETUPLELOOKUP_M 0x3U |
1191 | #define FIVETUPLELOOKUP_MASK 0x00060000U | 1191 | #define FIVETUPLELOOKUP_V(x) ((x) << FIVETUPLELOOKUP_S) |
1192 | #define FIVETUPLELOOKUP(x) ((x) << FIVETUPLELOOKUP_SHIFT) | 1192 | #define FIVETUPLELOOKUP_G(x) (((x) >> FIVETUPLELOOKUP_S) & FIVETUPLELOOKUP_M) |
1193 | #define FIVETUPLELOOKUP_GET(x) (((x) & FIVETUPLELOOKUP_MASK) >> \ | 1193 | |
1194 | FIVETUPLELOOKUP_SHIFT) | 1194 | #define TP_PARA_REG2_A 0x7d68 |
1195 | 1195 | ||
1196 | #define TP_PARA_REG2 0x7d68 | 1196 | #define MAXRXDATA_S 16 |
1197 | #define MAXRXDATA_MASK 0xffff0000U | 1197 | #define MAXRXDATA_M 0xffffU |
1198 | #define MAXRXDATA_SHIFT 16 | 1198 | #define MAXRXDATA_G(x) (((x) >> MAXRXDATA_S) & MAXRXDATA_M) |
1199 | #define MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT) | 1199 | |
1200 | 1200 | #define TP_TIMER_RESOLUTION_A 0x7d90 | |
1201 | #define TP_TIMER_RESOLUTION 0x7d90 | 1201 | |
1202 | #define TIMERRESOLUTION_MASK 0x00ff0000U | 1202 | #define TIMERRESOLUTION_S 16 |
1203 | #define TIMERRESOLUTION_SHIFT 16 | 1203 | #define TIMERRESOLUTION_M 0xffU |
1204 | #define TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT) | 1204 | #define TIMERRESOLUTION_G(x) (((x) >> TIMERRESOLUTION_S) & TIMERRESOLUTION_M) |
1205 | #define DELAYEDACKRESOLUTION_MASK 0x000000ffU | 1205 | |
1206 | #define DELAYEDACKRESOLUTION_SHIFT 0 | 1206 | #define DELAYEDACKRESOLUTION_S 0 |
1207 | #define DELAYEDACKRESOLUTION_GET(x) \ | 1207 | #define DELAYEDACKRESOLUTION_M 0xffU |
1208 | (((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT) | 1208 | #define DELAYEDACKRESOLUTION_G(x) \ |
1209 | 1209 | (((x) >> DELAYEDACKRESOLUTION_S) & DELAYEDACKRESOLUTION_M) | |
1210 | #define TP_SHIFT_CNT 0x7dc0 | 1210 | |
1211 | #define SYNSHIFTMAX_SHIFT 24 | 1211 | #define TP_SHIFT_CNT_A 0x7dc0 |
1212 | #define SYNSHIFTMAX_MASK 0xff000000U | 1212 | |
1213 | #define SYNSHIFTMAX(x) ((x) << SYNSHIFTMAX_SHIFT) | 1213 | #define SYNSHIFTMAX_S 24 |
1214 | #define SYNSHIFTMAX_GET(x) (((x) & SYNSHIFTMAX_MASK) >> \ | 1214 | #define SYNSHIFTMAX_M 0xffU |
1215 | SYNSHIFTMAX_SHIFT) | 1215 | #define SYNSHIFTMAX_V(x) ((x) << SYNSHIFTMAX_S) |
1216 | #define RXTSHIFTMAXR1_SHIFT 20 | 1216 | #define SYNSHIFTMAX_G(x) (((x) >> SYNSHIFTMAX_S) & SYNSHIFTMAX_M) |
1217 | #define RXTSHIFTMAXR1_MASK 0x00f00000U | 1217 | |
1218 | #define RXTSHIFTMAXR1(x) ((x) << RXTSHIFTMAXR1_SHIFT) | 1218 | #define RXTSHIFTMAXR1_S 20 |
1219 | #define RXTSHIFTMAXR1_GET(x) (((x) & RXTSHIFTMAXR1_MASK) >> \ | 1219 | #define RXTSHIFTMAXR1_M 0xfU |
1220 | RXTSHIFTMAXR1_SHIFT) | 1220 | #define RXTSHIFTMAXR1_V(x) ((x) << RXTSHIFTMAXR1_S) |
1221 | #define RXTSHIFTMAXR2_SHIFT 16 | 1221 | #define RXTSHIFTMAXR1_G(x) (((x) >> RXTSHIFTMAXR1_S) & RXTSHIFTMAXR1_M) |
1222 | #define RXTSHIFTMAXR2_MASK 0x000f0000U | 1222 | |
1223 | #define RXTSHIFTMAXR2(x) ((x) << RXTSHIFTMAXR2_SHIFT) | 1223 | #define RXTSHIFTMAXR2_S 16 |
1224 | #define RXTSHIFTMAXR2_GET(x) (((x) & RXTSHIFTMAXR2_MASK) >> \ | 1224 | #define RXTSHIFTMAXR2_M 0xfU |
1225 | RXTSHIFTMAXR2_SHIFT) | 1225 | #define RXTSHIFTMAXR2_V(x) ((x) << RXTSHIFTMAXR2_S) |
1226 | #define PERSHIFTBACKOFFMAX_SHIFT 12 | 1226 | #define RXTSHIFTMAXR2_G(x) (((x) >> RXTSHIFTMAXR2_S) & RXTSHIFTMAXR2_M) |
1227 | #define PERSHIFTBACKOFFMAX_MASK 0x0000f000U | 1227 | |
1228 | #define PERSHIFTBACKOFFMAX(x) ((x) << PERSHIFTBACKOFFMAX_SHIFT) | 1228 | #define PERSHIFTBACKOFFMAX_S 12 |
1229 | #define PERSHIFTBACKOFFMAX_GET(x) (((x) & PERSHIFTBACKOFFMAX_MASK) >> \ | 1229 | #define PERSHIFTBACKOFFMAX_M 0xfU |
1230 | PERSHIFTBACKOFFMAX_SHIFT) | 1230 | #define PERSHIFTBACKOFFMAX_V(x) ((x) << PERSHIFTBACKOFFMAX_S) |
1231 | #define PERSHIFTMAX_SHIFT 8 | 1231 | #define PERSHIFTBACKOFFMAX_G(x) \ |
1232 | #define PERSHIFTMAX_MASK 0x00000f00U | 1232 | (((x) >> PERSHIFTBACKOFFMAX_S) & PERSHIFTBACKOFFMAX_M) |
1233 | #define PERSHIFTMAX(x) ((x) << PERSHIFTMAX_SHIFT) | 1233 | |
1234 | #define PERSHIFTMAX_GET(x) (((x) & PERSHIFTMAX_MASK) >> \ | 1234 | #define PERSHIFTMAX_S 8 |
1235 | PERSHIFTMAX_SHIFT) | 1235 | #define PERSHIFTMAX_M 0xfU |
1236 | #define KEEPALIVEMAXR1_SHIFT 4 | 1236 | #define PERSHIFTMAX_V(x) ((x) << PERSHIFTMAX_S) |
1237 | #define KEEPALIVEMAXR1_MASK 0x000000f0U | 1237 | #define PERSHIFTMAX_G(x) (((x) >> PERSHIFTMAX_S) & PERSHIFTMAX_M) |
1238 | #define KEEPALIVEMAXR1(x) ((x) << KEEPALIVEMAXR1_SHIFT) | 1238 | |
1239 | #define KEEPALIVEMAXR1_GET(x) (((x) & KEEPALIVEMAXR1_MASK) >> \ | 1239 | #define KEEPALIVEMAXR1_S 4 |
1240 | KEEPALIVEMAXR1_SHIFT) | 1240 | #define KEEPALIVEMAXR1_M 0xfU |
1241 | #define KEEPALIVEMAXR2_SHIFT 0 | 1241 | #define KEEPALIVEMAXR1_V(x) ((x) << KEEPALIVEMAXR1_S) |
1242 | #define KEEPALIVEMAXR2_MASK 0x0000000fU | 1242 | #define KEEPALIVEMAXR1_G(x) (((x) >> KEEPALIVEMAXR1_S) & KEEPALIVEMAXR1_M) |
1243 | #define KEEPALIVEMAXR2(x) ((x) << KEEPALIVEMAXR2_SHIFT) | 1243 | |
1244 | #define KEEPALIVEMAXR2_GET(x) (((x) & KEEPALIVEMAXR2_MASK) >> \ | 1244 | #define KEEPALIVEMAXR2_S 0 |
1245 | KEEPALIVEMAXR2_SHIFT) | 1245 | #define KEEPALIVEMAXR2_M 0xfU |
1246 | 1246 | #define KEEPALIVEMAXR2_V(x) ((x) << KEEPALIVEMAXR2_S) | |
1247 | #define TP_CCTRL_TABLE 0x7ddc | 1247 | #define KEEPALIVEMAXR2_G(x) (((x) >> KEEPALIVEMAXR2_S) & KEEPALIVEMAXR2_M) |
1248 | #define TP_MTU_TABLE 0x7de4 | 1248 | |
1249 | #define MTUINDEX_MASK 0xff000000U | 1249 | #define TP_CCTRL_TABLE_A 0x7ddc |
1250 | #define MTUINDEX_SHIFT 24 | 1250 | #define TP_MTU_TABLE_A 0x7de4 |
1251 | #define MTUINDEX(x) ((x) << MTUINDEX_SHIFT) | 1251 | |
1252 | #define MTUWIDTH_MASK 0x000f0000U | 1252 | #define MTUINDEX_S 24 |
1253 | #define MTUWIDTH_SHIFT 16 | 1253 | #define MTUINDEX_V(x) ((x) << MTUINDEX_S) |
1254 | #define MTUWIDTH(x) ((x) << MTUWIDTH_SHIFT) | 1254 | |
1255 | #define MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT) | 1255 | #define MTUWIDTH_S 16 |
1256 | #define MTUVALUE_MASK 0x00003fffU | 1256 | #define MTUWIDTH_M 0xfU |
1257 | #define MTUVALUE_SHIFT 0 | 1257 | #define MTUWIDTH_V(x) ((x) << MTUWIDTH_S) |
1258 | #define MTUVALUE(x) ((x) << MTUVALUE_SHIFT) | 1258 | #define MTUWIDTH_G(x) (((x) >> MTUWIDTH_S) & MTUWIDTH_M) |
1259 | #define MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT) | 1259 | |
1260 | 1260 | #define MTUVALUE_S 0 | |
1261 | #define TP_RSS_LKP_TABLE 0x7dec | 1261 | #define MTUVALUE_M 0x3fffU |
1262 | #define LKPTBLROWVLD 0x80000000U | 1262 | #define MTUVALUE_V(x) ((x) << MTUVALUE_S) |
1263 | #define LKPTBLQUEUE1_MASK 0x000ffc00U | 1263 | #define MTUVALUE_G(x) (((x) >> MTUVALUE_S) & MTUVALUE_M) |
1264 | #define LKPTBLQUEUE1_SHIFT 10 | 1264 | |
1265 | #define LKPTBLQUEUE1(x) ((x) << LKPTBLQUEUE1_SHIFT) | 1265 | #define TP_RSS_LKP_TABLE_A 0x7dec |
1266 | #define LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT) | 1266 | |
1267 | #define LKPTBLQUEUE0_MASK 0x000003ffU | 1267 | #define LKPTBLROWVLD_S 31 |
1268 | #define LKPTBLQUEUE0_SHIFT 0 | 1268 | #define LKPTBLROWVLD_V(x) ((x) << LKPTBLROWVLD_S) |
1269 | #define LKPTBLQUEUE0(x) ((x) << LKPTBLQUEUE0_SHIFT) | 1269 | #define LKPTBLROWVLD_F LKPTBLROWVLD_V(1U) |
1270 | #define LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT) | 1270 | |
1271 | 1271 | #define LKPTBLQUEUE1_S 10 | |
1272 | #define TP_PIO_ADDR 0x7e40 | 1272 | #define LKPTBLQUEUE1_M 0x3ffU |
1273 | #define TP_PIO_DATA 0x7e44 | 1273 | #define LKPTBLQUEUE1_G(x) (((x) >> LKPTBLQUEUE1_S) & LKPTBLQUEUE1_M) |
1274 | #define TP_MIB_INDEX 0x7e50 | 1274 | |
1275 | #define TP_MIB_DATA 0x7e54 | 1275 | #define LKPTBLQUEUE0_S 0 |
1276 | #define TP_INT_CAUSE 0x7e74 | 1276 | #define LKPTBLQUEUE0_M 0x3ffU |
1277 | #define FLMTXFLSTEMPTY 0x40000000U | 1277 | #define LKPTBLQUEUE0_G(x) (((x) >> LKPTBLQUEUE0_S) & LKPTBLQUEUE0_M) |
1278 | 1278 | ||
1279 | #define TP_VLAN_PRI_MAP 0x140 | 1279 | #define TP_PIO_ADDR_A 0x7e40 |
1280 | #define FRAGMENTATION_SHIFT 9 | 1280 | #define TP_PIO_DATA_A 0x7e44 |
1281 | #define FRAGMENTATION_MASK 0x00000200U | 1281 | #define TP_MIB_INDEX_A 0x7e50 |
1282 | #define MPSHITTYPE_MASK 0x00000100U | 1282 | #define TP_MIB_DATA_A 0x7e54 |
1283 | #define MACMATCH_MASK 0x00000080U | 1283 | #define TP_INT_CAUSE_A 0x7e74 |
1284 | #define ETHERTYPE_MASK 0x00000040U | 1284 | |
1285 | #define PROTOCOL_MASK 0x00000020U | 1285 | #define FLMTXFLSTEMPTY_S 30 |
1286 | #define TOS_MASK 0x00000010U | 1286 | #define FLMTXFLSTEMPTY_V(x) ((x) << FLMTXFLSTEMPTY_S) |
1287 | #define VLAN_MASK 0x00000008U | 1287 | #define FLMTXFLSTEMPTY_F FLMTXFLSTEMPTY_V(1U) |
1288 | #define VNIC_ID_MASK 0x00000004U | 1288 | |
1289 | #define PORT_MASK 0x00000002U | 1289 | #define TP_VLAN_PRI_MAP_A 0x140 |
1290 | #define FCOE_SHIFT 0 | 1290 | |
1291 | #define FCOE_MASK 0x00000001U | 1291 | #define FRAGMENTATION_S 9 |
1292 | 1292 | #define FRAGMENTATION_V(x) ((x) << FRAGMENTATION_S) | |
1293 | #define TP_INGRESS_CONFIG 0x141 | 1293 | #define FRAGMENTATION_F FRAGMENTATION_V(1U) |
1294 | #define VNIC 0x00000800U | 1294 | |
1295 | #define CSUM_HAS_PSEUDO_HDR 0x00000400U | 1295 | #define MPSHITTYPE_S 8 |
1296 | #define RM_OVLAN 0x00000200U | 1296 | #define MPSHITTYPE_V(x) ((x) << MPSHITTYPE_S) |
1297 | #define LOOKUPEVERYPKT 0x00000100U | 1297 | #define MPSHITTYPE_F MPSHITTYPE_V(1U) |
1298 | 1298 | ||
1299 | #define TP_MIB_MAC_IN_ERR_0 0x0 | 1299 | #define MACMATCH_S 7 |
1300 | #define TP_MIB_TCP_OUT_RST 0xc | 1300 | #define MACMATCH_V(x) ((x) << MACMATCH_S) |
1301 | #define TP_MIB_TCP_IN_SEG_HI 0x10 | 1301 | #define MACMATCH_F MACMATCH_V(1U) |
1302 | #define TP_MIB_TCP_IN_SEG_LO 0x11 | 1302 | |
1303 | #define TP_MIB_TCP_OUT_SEG_HI 0x12 | 1303 | #define ETHERTYPE_S 6 |
1304 | #define TP_MIB_TCP_OUT_SEG_LO 0x13 | 1304 | #define ETHERTYPE_V(x) ((x) << ETHERTYPE_S) |
1305 | #define TP_MIB_TCP_RXT_SEG_HI 0x14 | 1305 | #define ETHERTYPE_F ETHERTYPE_V(1U) |
1306 | #define TP_MIB_TCP_RXT_SEG_LO 0x15 | 1306 | |
1307 | #define TP_MIB_TNL_CNG_DROP_0 0x18 | 1307 | #define PROTOCOL_S 5 |
1308 | #define TP_MIB_TCP_V6IN_ERR_0 0x28 | 1308 | #define PROTOCOL_V(x) ((x) << PROTOCOL_S) |
1309 | #define TP_MIB_TCP_V6OUT_RST 0x2c | 1309 | #define PROTOCOL_F PROTOCOL_V(1U) |
1310 | #define TP_MIB_OFD_ARP_DROP 0x36 | 1310 | |
1311 | #define TP_MIB_TNL_DROP_0 0x44 | 1311 | #define TOS_S 4 |
1312 | #define TP_MIB_OFD_VLN_DROP_0 0x58 | 1312 | #define TOS_V(x) ((x) << TOS_S) |
1313 | 1313 | #define TOS_F TOS_V(1U) | |
1314 | #define ULP_TX_INT_CAUSE 0x8dcc | 1314 | |
1315 | #define PBL_BOUND_ERR_CH3 0x80000000U | 1315 | #define VLAN_S 3 |
1316 | #define PBL_BOUND_ERR_CH2 0x40000000U | 1316 | #define VLAN_V(x) ((x) << VLAN_S) |
1317 | #define PBL_BOUND_ERR_CH1 0x20000000U | 1317 | #define VLAN_F VLAN_V(1U) |
1318 | #define PBL_BOUND_ERR_CH0 0x10000000U | 1318 | |
1319 | 1319 | #define VNIC_ID_S 2 | |
1320 | #define PM_RX_INT_CAUSE 0x8fdc | 1320 | #define VNIC_ID_V(x) ((x) << VNIC_ID_S) |
1321 | #define ZERO_E_CMD_ERROR 0x00400000U | 1321 | #define VNIC_ID_F VNIC_ID_V(1U) |
1322 | #define PMRX_FRAMING_ERROR 0x003ffff0U | 1322 | |
1323 | #define OCSPI_PAR_ERROR 0x00000008U | 1323 | #define PORT_S 1 |
1324 | #define DB_OPTIONS_PAR_ERROR 0x00000004U | 1324 | #define PORT_V(x) ((x) << PORT_S) |
1325 | #define IESPI_PAR_ERROR 0x00000002U | 1325 | #define PORT_F PORT_V(1U) |
1326 | #define E_PCMD_PAR_ERROR 0x00000001U | 1326 | |
1327 | 1327 | #define FCOE_S 0 | |
1328 | #define PM_TX_INT_CAUSE 0x8ffc | 1328 | #define FCOE_V(x) ((x) << FCOE_S) |
1329 | #define PCMD_LEN_OVFL0 0x80000000U | 1329 | #define FCOE_F FCOE_V(1U) |
1330 | #define PCMD_LEN_OVFL1 0x40000000U | 1330 | |
1331 | #define PCMD_LEN_OVFL2 0x20000000U | 1331 | #define FILTERMODE_S 15 |
1332 | #define ZERO_C_CMD_ERROR 0x10000000U | 1332 | #define FILTERMODE_V(x) ((x) << FILTERMODE_S) |
1333 | #define PMTX_FRAMING_ERROR 0x0ffffff0U | 1333 | #define FILTERMODE_F FILTERMODE_V(1U) |
1334 | #define OESPI_PAR_ERROR 0x00000008U | 1334 | |
1335 | #define ICSPI_PAR_ERROR 0x00000002U | 1335 | #define FCOEMASK_S 14 |
1336 | #define C_PCMD_PAR_ERROR 0x00000001U | 1336 | #define FCOEMASK_V(x) ((x) << FCOEMASK_S) |
1337 | #define FCOEMASK_F FCOEMASK_V(1U) | ||
1338 | |||
1339 | #define TP_INGRESS_CONFIG_A 0x141 | ||
1340 | |||
1341 | #define VNIC_S 11 | ||
1342 | #define VNIC_V(x) ((x) << VNIC_S) | ||
1343 | #define VNIC_F VNIC_V(1U) | ||
1344 | |||
1345 | #define CSUM_HAS_PSEUDO_HDR_S 10 | ||
1346 | #define CSUM_HAS_PSEUDO_HDR_V(x) ((x) << CSUM_HAS_PSEUDO_HDR_S) | ||
1347 | #define CSUM_HAS_PSEUDO_HDR_F CSUM_HAS_PSEUDO_HDR_V(1U) | ||
1348 | |||
1349 | #define TP_MIB_MAC_IN_ERR_0_A 0x0 | ||
1350 | #define TP_MIB_TCP_OUT_RST_A 0xc | ||
1351 | #define TP_MIB_TCP_IN_SEG_HI_A 0x10 | ||
1352 | #define TP_MIB_TCP_IN_SEG_LO_A 0x11 | ||
1353 | #define TP_MIB_TCP_OUT_SEG_HI_A 0x12 | ||
1354 | #define TP_MIB_TCP_OUT_SEG_LO_A 0x13 | ||
1355 | #define TP_MIB_TCP_RXT_SEG_HI_A 0x14 | ||
1356 | #define TP_MIB_TCP_RXT_SEG_LO_A 0x15 | ||
1357 | #define TP_MIB_TNL_CNG_DROP_0_A 0x18 | ||
1358 | #define TP_MIB_TCP_V6IN_ERR_0_A 0x28 | ||
1359 | #define TP_MIB_TCP_V6OUT_RST_A 0x2c | ||
1360 | #define TP_MIB_OFD_ARP_DROP_A 0x36 | ||
1361 | #define TP_MIB_TNL_DROP_0_A 0x44 | ||
1362 | #define TP_MIB_OFD_VLN_DROP_0_A 0x58 | ||
1363 | |||
1364 | #define ULP_TX_INT_CAUSE_A 0x8dcc | ||
1365 | |||
1366 | #define PBL_BOUND_ERR_CH3_S 31 | ||
1367 | #define PBL_BOUND_ERR_CH3_V(x) ((x) << PBL_BOUND_ERR_CH3_S) | ||
1368 | #define PBL_BOUND_ERR_CH3_F PBL_BOUND_ERR_CH3_V(1U) | ||
1369 | |||
1370 | #define PBL_BOUND_ERR_CH2_S 30 | ||
1371 | #define PBL_BOUND_ERR_CH2_V(x) ((x) << PBL_BOUND_ERR_CH2_S) | ||
1372 | #define PBL_BOUND_ERR_CH2_F PBL_BOUND_ERR_CH2_V(1U) | ||
1373 | |||
1374 | #define PBL_BOUND_ERR_CH1_S 29 | ||
1375 | #define PBL_BOUND_ERR_CH1_V(x) ((x) << PBL_BOUND_ERR_CH1_S) | ||
1376 | #define PBL_BOUND_ERR_CH1_F PBL_BOUND_ERR_CH1_V(1U) | ||
1377 | |||
1378 | #define PBL_BOUND_ERR_CH0_S 28 | ||
1379 | #define PBL_BOUND_ERR_CH0_V(x) ((x) << PBL_BOUND_ERR_CH0_S) | ||
1380 | #define PBL_BOUND_ERR_CH0_F PBL_BOUND_ERR_CH0_V(1U) | ||
1381 | |||
1382 | #define PM_RX_INT_CAUSE_A 0x8fdc | ||
1383 | |||
1384 | #define PMRX_FRAMING_ERROR_F 0x003ffff0U | ||
1385 | |||
1386 | #define ZERO_E_CMD_ERROR_S 22 | ||
1387 | #define ZERO_E_CMD_ERROR_V(x) ((x) << ZERO_E_CMD_ERROR_S) | ||
1388 | #define ZERO_E_CMD_ERROR_F ZERO_E_CMD_ERROR_V(1U) | ||
1389 | |||
1390 | #define OCSPI_PAR_ERROR_S 3 | ||
1391 | #define OCSPI_PAR_ERROR_V(x) ((x) << OCSPI_PAR_ERROR_S) | ||
1392 | #define OCSPI_PAR_ERROR_F OCSPI_PAR_ERROR_V(1U) | ||
1393 | |||
1394 | #define DB_OPTIONS_PAR_ERROR_S 2 | ||
1395 | #define DB_OPTIONS_PAR_ERROR_V(x) ((x) << DB_OPTIONS_PAR_ERROR_S) | ||
1396 | #define DB_OPTIONS_PAR_ERROR_F DB_OPTIONS_PAR_ERROR_V(1U) | ||
1397 | |||
1398 | #define IESPI_PAR_ERROR_S 1 | ||
1399 | #define IESPI_PAR_ERROR_V(x) ((x) << IESPI_PAR_ERROR_S) | ||
1400 | #define IESPI_PAR_ERROR_F IESPI_PAR_ERROR_V(1U) | ||
1401 | |||
1402 | #define PMRX_E_PCMD_PAR_ERROR_S 0 | ||
1403 | #define PMRX_E_PCMD_PAR_ERROR_V(x) ((x) << PMRX_E_PCMD_PAR_ERROR_S) | ||
1404 | #define PMRX_E_PCMD_PAR_ERROR_F PMRX_E_PCMD_PAR_ERROR_V(1U) | ||
1405 | |||
1406 | #define PM_TX_INT_CAUSE_A 0x8ffc | ||
1407 | |||
1408 | #define PCMD_LEN_OVFL0_S 31 | ||
1409 | #define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S) | ||
1410 | #define PCMD_LEN_OVFL0_F PCMD_LEN_OVFL0_V(1U) | ||
1411 | |||
1412 | #define PCMD_LEN_OVFL1_S 30 | ||
1413 | #define PCMD_LEN_OVFL1_V(x) ((x) << PCMD_LEN_OVFL1_S) | ||
1414 | #define PCMD_LEN_OVFL1_F PCMD_LEN_OVFL1_V(1U) | ||
1415 | |||
1416 | #define PCMD_LEN_OVFL2_S 29 | ||
1417 | #define PCMD_LEN_OVFL2_V(x) ((x) << PCMD_LEN_OVFL2_S) | ||
1418 | #define PCMD_LEN_OVFL2_F PCMD_LEN_OVFL2_V(1U) | ||
1419 | |||
1420 | #define ZERO_C_CMD_ERROR_S 28 | ||
1421 | #define ZERO_C_CMD_ERROR_V(x) ((x) << ZERO_C_CMD_ERROR_S) | ||
1422 | #define ZERO_C_CMD_ERROR_F ZERO_C_CMD_ERROR_V(1U) | ||
1423 | |||
1424 | #define PMTX_FRAMING_ERROR_F 0x0ffffff0U | ||
1425 | |||
1426 | #define OESPI_PAR_ERROR_S 3 | ||
1427 | #define OESPI_PAR_ERROR_V(x) ((x) << OESPI_PAR_ERROR_S) | ||
1428 | #define OESPI_PAR_ERROR_F OESPI_PAR_ERROR_V(1U) | ||
1429 | |||
1430 | #define ICSPI_PAR_ERROR_S 1 | ||
1431 | #define ICSPI_PAR_ERROR_V(x) ((x) << ICSPI_PAR_ERROR_S) | ||
1432 | #define ICSPI_PAR_ERROR_F ICSPI_PAR_ERROR_V(1U) | ||
1433 | |||
1434 | #define PMTX_C_PCMD_PAR_ERROR_S 0 | ||
1435 | #define PMTX_C_PCMD_PAR_ERROR_V(x) ((x) << PMTX_C_PCMD_PAR_ERROR_S) | ||
1436 | #define PMTX_C_PCMD_PAR_ERROR_F PMTX_C_PCMD_PAR_ERROR_V(1U) | ||
1337 | 1437 | ||
1338 | #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 | 1438 | #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400 |
1339 | #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 | 1439 | #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404 |
@@ -1462,41 +1562,57 @@ | |||
1462 | #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c | 1562 | #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c |
1463 | #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 | 1563 | #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610 |
1464 | #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 | 1564 | #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614 |
1465 | #define MAC_PORT_CFG2 0x818 | ||
1466 | #define MAC_PORT_MAGIC_MACID_LO 0x824 | 1565 | #define MAC_PORT_MAGIC_MACID_LO 0x824 |
1467 | #define MAC_PORT_MAGIC_MACID_HI 0x828 | 1566 | #define MAC_PORT_MAGIC_MACID_HI 0x828 |
1468 | #define MAC_PORT_EPIO_DATA0 0x8c0 | 1567 | |
1469 | #define MAC_PORT_EPIO_DATA1 0x8c4 | 1568 | #define MAC_PORT_EPIO_DATA0_A 0x8c0 |
1470 | #define MAC_PORT_EPIO_DATA2 0x8c8 | 1569 | #define MAC_PORT_EPIO_DATA1_A 0x8c4 |
1471 | #define MAC_PORT_EPIO_DATA3 0x8cc | 1570 | #define MAC_PORT_EPIO_DATA2_A 0x8c8 |
1472 | #define MAC_PORT_EPIO_OP 0x8d0 | 1571 | #define MAC_PORT_EPIO_DATA3_A 0x8cc |
1473 | 1572 | #define MAC_PORT_EPIO_OP_A 0x8d0 | |
1474 | #define MPS_CMN_CTL 0x9000 | 1573 | |
1475 | #define NUMPORTS_MASK 0x00000003U | 1574 | #define MAC_PORT_CFG2_A 0x818 |
1476 | #define NUMPORTS_SHIFT 0 | 1575 | |
1477 | #define NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT) | 1576 | #define MPS_CMN_CTL_A 0x9000 |
1478 | 1577 | ||
1479 | #define MPS_INT_CAUSE 0x9008 | 1578 | #define NUMPORTS_S 0 |
1480 | #define STATINT 0x00000020U | 1579 | #define NUMPORTS_M 0x3U |
1481 | #define TXINT 0x00000010U | 1580 | #define NUMPORTS_G(x) (((x) >> NUMPORTS_S) & NUMPORTS_M) |
1482 | #define RXINT 0x00000008U | 1581 | |
1483 | #define TRCINT 0x00000004U | 1582 | #define MPS_INT_CAUSE_A 0x9008 |
1484 | #define CLSINT 0x00000002U | 1583 | #define MPS_TX_INT_CAUSE_A 0x9408 |
1485 | #define PLINT 0x00000001U | 1584 | |
1486 | 1585 | #define FRMERR_S 15 | |
1487 | #define MPS_TX_INT_CAUSE 0x9408 | 1586 | #define FRMERR_V(x) ((x) << FRMERR_S) |
1488 | #define PORTERR 0x00010000U | 1587 | #define FRMERR_F FRMERR_V(1U) |
1489 | #define FRMERR 0x00008000U | 1588 | |
1490 | #define SECNTERR 0x00004000U | 1589 | #define SECNTERR_S 14 |
1491 | #define BUBBLE 0x00002000U | 1590 | #define SECNTERR_V(x) ((x) << SECNTERR_S) |
1492 | #define TXDESCFIFO 0x00001e00U | 1591 | #define SECNTERR_F SECNTERR_V(1U) |
1493 | #define TXDATAFIFO 0x000001e0U | 1592 | |
1494 | #define NCSIFIFO 0x00000010U | 1593 | #define BUBBLE_S 13 |
1495 | #define TPFIFO 0x0000000fU | 1594 | #define BUBBLE_V(x) ((x) << BUBBLE_S) |
1496 | 1595 | #define BUBBLE_F BUBBLE_V(1U) | |
1497 | #define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614 | 1596 | |
1498 | #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620 | 1597 | #define TXDESCFIFO_S 9 |
1499 | #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c | 1598 | #define TXDESCFIFO_M 0xfU |
1599 | #define TXDESCFIFO_V(x) ((x) << TXDESCFIFO_S) | ||
1600 | |||
1601 | #define TXDATAFIFO_S 5 | ||
1602 | #define TXDATAFIFO_M 0xfU | ||
1603 | #define TXDATAFIFO_V(x) ((x) << TXDATAFIFO_S) | ||
1604 | |||
1605 | #define NCSIFIFO_S 4 | ||
1606 | #define NCSIFIFO_V(x) ((x) << NCSIFIFO_S) | ||
1607 | #define NCSIFIFO_F NCSIFIFO_V(1U) | ||
1608 | |||
1609 | #define TPFIFO_S 0 | ||
1610 | #define TPFIFO_M 0xfU | ||
1611 | #define TPFIFO_V(x) ((x) << TPFIFO_S) | ||
1612 | |||
1613 | #define MPS_STAT_PERR_INT_CAUSE_SRAM_A 0x9614 | ||
1614 | #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A 0x9620 | ||
1615 | #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A 0x962c | ||
1500 | 1616 | ||
1501 | #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 | 1617 | #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640 |
1502 | #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 | 1618 | #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644 |
@@ -1530,66 +1646,67 @@ | |||
1530 | #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 | 1646 | #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4 |
1531 | #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 | 1647 | #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8 |
1532 | #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc | 1648 | #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc |
1533 | #define MPS_TRC_CFG 0x9800 | 1649 | |
1534 | #define TRCFIFOEMPTY 0x00000010U | 1650 | #define MPS_TRC_CFG_A 0x9800 |
1535 | #define TRCIGNOREDROPINPUT 0x00000008U | 1651 | |
1536 | #define TRCKEEPDUPLICATES 0x00000004U | 1652 | #define TRCFIFOEMPTY_S 4 |
1537 | #define TRCEN 0x00000002U | 1653 | #define TRCFIFOEMPTY_V(x) ((x) << TRCFIFOEMPTY_S) |
1538 | #define TRCMULTIFILTER 0x00000001U | 1654 | #define TRCFIFOEMPTY_F TRCFIFOEMPTY_V(1U) |
1539 | 1655 | ||
1540 | #define MPS_TRC_RSS_CONTROL 0x9808 | 1656 | #define TRCIGNOREDROPINPUT_S 3 |
1541 | #define MPS_T5_TRC_RSS_CONTROL 0xa00c | 1657 | #define TRCIGNOREDROPINPUT_V(x) ((x) << TRCIGNOREDROPINPUT_S) |
1542 | #define RSSCONTROL_MASK 0x00ff0000U | 1658 | #define TRCIGNOREDROPINPUT_F TRCIGNOREDROPINPUT_V(1U) |
1543 | #define RSSCONTROL_SHIFT 16 | 1659 | |
1544 | #define RSSCONTROL(x) ((x) << RSSCONTROL_SHIFT) | 1660 | #define TRCKEEPDUPLICATES_S 2 |
1545 | #define QUEUENUMBER_MASK 0x0000ffffU | 1661 | #define TRCKEEPDUPLICATES_V(x) ((x) << TRCKEEPDUPLICATES_S) |
1546 | #define QUEUENUMBER_SHIFT 0 | 1662 | #define TRCKEEPDUPLICATES_F TRCKEEPDUPLICATES_V(1U) |
1547 | #define QUEUENUMBER(x) ((x) << QUEUENUMBER_SHIFT) | 1663 | |
1548 | 1664 | #define TRCEN_S 1 | |
1549 | #define MPS_TRC_FILTER_MATCH_CTL_A 0x9810 | 1665 | #define TRCEN_V(x) ((x) << TRCEN_S) |
1550 | #define TFINVERTMATCH 0x01000000U | 1666 | #define TRCEN_F TRCEN_V(1U) |
1551 | #define TFPKTTOOLARGE 0x00800000U | 1667 | |
1552 | #define TFEN 0x00400000U | 1668 | #define TRCMULTIFILTER_S 0 |
1553 | #define TFPORT_MASK 0x003c0000U | 1669 | #define TRCMULTIFILTER_V(x) ((x) << TRCMULTIFILTER_S) |
1554 | #define TFPORT_SHIFT 18 | 1670 | #define TRCMULTIFILTER_F TRCMULTIFILTER_V(1U) |
1555 | #define TFPORT(x) ((x) << TFPORT_SHIFT) | 1671 | |
1556 | #define TFPORT_GET(x) (((x) & TFPORT_MASK) >> TFPORT_SHIFT) | 1672 | #define MPS_TRC_RSS_CONTROL_A 0x9808 |
1557 | #define TFDROP 0x00020000U | 1673 | #define MPS_T5_TRC_RSS_CONTROL_A 0xa00c |
1558 | #define TFSOPEOPERR 0x00010000U | 1674 | |
1559 | #define TFLENGTH_MASK 0x00001f00U | 1675 | #define RSSCONTROL_S 16 |
1560 | #define TFLENGTH_SHIFT 8 | 1676 | #define RSSCONTROL_V(x) ((x) << RSSCONTROL_S) |
1561 | #define TFLENGTH(x) ((x) << TFLENGTH_SHIFT) | 1677 | |
1562 | #define TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT) | 1678 | #define QUEUENUMBER_S 0 |
1563 | #define TFOFFSET_MASK 0x0000001fU | 1679 | #define QUEUENUMBER_V(x) ((x) << QUEUENUMBER_S) |
1564 | #define TFOFFSET_SHIFT 0 | 1680 | |
1565 | #define TFOFFSET(x) ((x) << TFOFFSET_SHIFT) | 1681 | #define MPS_TRC_INT_CAUSE_A 0x985c |
1566 | #define TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT) | 1682 | |
1567 | 1683 | #define MISCPERR_S 8 | |
1568 | #define MPS_TRC_FILTER_MATCH_CTL_B 0x9820 | 1684 | #define MISCPERR_V(x) ((x) << MISCPERR_S) |
1569 | #define TFMINPKTSIZE_MASK 0x01ff0000U | 1685 | #define MISCPERR_F MISCPERR_V(1U) |
1570 | #define TFMINPKTSIZE_SHIFT 16 | 1686 | |
1571 | #define TFMINPKTSIZE(x) ((x) << TFMINPKTSIZE_SHIFT) | 1687 | #define PKTFIFO_S 4 |
1572 | #define TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT) | 1688 | #define PKTFIFO_M 0xfU |
1573 | #define TFCAPTUREMAX_MASK 0x00003fffU | 1689 | #define PKTFIFO_V(x) ((x) << PKTFIFO_S) |
1574 | #define TFCAPTUREMAX_SHIFT 0 | 1690 | |
1575 | #define TFCAPTUREMAX(x) ((x) << TFCAPTUREMAX_SHIFT) | 1691 | #define FILTMEM_S 0 |
1576 | #define TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT) | 1692 | #define FILTMEM_M 0xfU |
1577 | 1693 | #define FILTMEM_V(x) ((x) << FILTMEM_S) | |
1578 | #define MPS_TRC_INT_CAUSE 0x985c | 1694 | |
1579 | #define MISCPERR 0x00000100U | 1695 | #define MPS_CLS_INT_CAUSE_A 0xd028 |
1580 | #define PKTFIFO 0x000000f0U | 1696 | |
1581 | #define FILTMEM 0x0000000fU | 1697 | #define HASHSRAM_S 2 |
1582 | 1698 | #define HASHSRAM_V(x) ((x) << HASHSRAM_S) | |
1583 | #define MPS_TRC_FILTER0_MATCH 0x9c00 | 1699 | #define HASHSRAM_F HASHSRAM_V(1U) |
1584 | #define MPS_TRC_FILTER0_DONT_CARE 0x9c80 | 1700 | |
1585 | #define MPS_TRC_FILTER1_MATCH 0x9d00 | 1701 | #define MATCHTCAM_S 1 |
1586 | #define MPS_CLS_INT_CAUSE 0xd028 | 1702 | #define MATCHTCAM_V(x) ((x) << MATCHTCAM_S) |
1587 | #define PLERRENB 0x00000008U | 1703 | #define MATCHTCAM_F MATCHTCAM_V(1U) |
1588 | #define HASHSRAM 0x00000004U | 1704 | |
1589 | #define MATCHTCAM 0x00000002U | 1705 | #define MATCHSRAM_S 0 |
1590 | #define MATCHSRAM 0x00000001U | 1706 | #define MATCHSRAM_V(x) ((x) << MATCHSRAM_S) |
1591 | 1707 | #define MATCHSRAM_F MATCHSRAM_V(1U) | |
1592 | #define MPS_RX_PERR_INT_CAUSE 0x11074 | 1708 | |
1709 | #define MPS_RX_PERR_INT_CAUSE_A 0x11074 | ||
1593 | 1710 | ||
1594 | #define CPL_INTR_CAUSE 0x19054 | 1711 | #define CPL_INTR_CAUSE 0x19054 |
1595 | #define CIM_OP_MAP_PERR 0x00000020U | 1712 | #define CIM_OP_MAP_PERR 0x00000020U |