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-rw-r--r--drivers/gpu/nvgpu/Makefile.nvgpu4
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c2
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.h3
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c2
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.h3
-rw-r--r--drivers/gpu/nvgpu/vgpu/ce2_vgpu.c7
-rw-r--r--drivers/gpu/nvgpu/vgpu/css_vgpu.c22
-rw-r--r--drivers/gpu/nvgpu/vgpu/css_vgpu.h (renamed from drivers/gpu/nvgpu/vgpu/debug_vgpu.c)27
-rw-r--r--drivers/gpu/nvgpu/vgpu/dbg_vgpu.c29
-rw-r--r--drivers/gpu/nvgpu/vgpu/dbg_vgpu.h47
-rw-r--r--drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c41
-rw-r--r--drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.h23
-rw-r--r--drivers/gpu/nvgpu/vgpu/fifo_vgpu.c61
-rw-r--r--drivers/gpu/nvgpu/vgpu/fifo_vgpu.h65
-rw-r--r--drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c9
-rw-r--r--drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.h4
-rw-r--r--drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c579
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c21
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h19
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c624
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c15
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h19
-rw-r--r--drivers/gpu/nvgpu/vgpu/gr_vgpu.c69
-rw-r--r--drivers/gpu/nvgpu/vgpu/gr_vgpu.h44
-rw-r--r--drivers/gpu/nvgpu/vgpu/ltc_vgpu.c17
-rw-r--r--drivers/gpu/nvgpu/vgpu/ltc_vgpu.h (renamed from drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h)13
-rw-r--r--drivers/gpu/nvgpu/vgpu/mm_vgpu.c33
-rw-r--r--drivers/gpu/nvgpu/vgpu/mm_vgpu.h56
-rw-r--r--drivers/gpu/nvgpu/vgpu/tsg_vgpu.c17
-rw-r--r--drivers/gpu/nvgpu/vgpu/vgpu.c23
-rw-r--r--drivers/gpu/nvgpu/vgpu/vgpu.h40
31 files changed, 1582 insertions, 356 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu
index fa774566..9ba6f49a 100644
--- a/drivers/gpu/nvgpu/Makefile.nvgpu
+++ b/drivers/gpu/nvgpu/Makefile.nvgpu
@@ -153,7 +153,6 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
153 vgpu/fifo_vgpu.o \ 153 vgpu/fifo_vgpu.o \
154 vgpu/ce2_vgpu.o \ 154 vgpu/ce2_vgpu.o \
155 vgpu/mm_vgpu.o \ 155 vgpu/mm_vgpu.o \
156 vgpu/debug_vgpu.o \
157 vgpu/vgpu.o \ 156 vgpu/vgpu.o \
158 vgpu/dbg_vgpu.o \ 157 vgpu/dbg_vgpu.o \
159 vgpu/fecs_trace_vgpu.o \ 158 vgpu/fecs_trace_vgpu.o \
@@ -245,8 +244,7 @@ nvgpu-$(CONFIG_TEGRA_GK20A) += common/linux/platform_gp10b_tegra.o
245nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ 244nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \
246 vgpu/gp10b/vgpu_hal_gp10b.o \ 245 vgpu/gp10b/vgpu_hal_gp10b.o \
247 vgpu/gp10b/vgpu_gr_gp10b.o \ 246 vgpu/gp10b/vgpu_gr_gp10b.o \
248 vgpu/gp10b/vgpu_mm_gp10b.o \ 247 vgpu/gp10b/vgpu_mm_gp10b.o
249 vgpu/gp10b/vgpu_fifo_gp10b.o
250endif 248endif
251 249
252ifeq ($(CONFIG_ARCH_TEGRA_19x_SOC),y) 250ifeq ($(CONFIG_ARCH_TEGRA_19x_SOC),y)
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 76c87c00..39d05978 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -71,7 +71,7 @@
71 71
72#define PRIV_SECURITY_DISABLE 0x01 72#define PRIV_SECURITY_DISABLE 0x01
73 73
74static int gm20b_get_litter_value(struct gk20a *g, int value) 74int gm20b_get_litter_value(struct gk20a *g, int value)
75{ 75{
76 int ret = EINVAL; 76 int ret = EINVAL;
77 switch (value) { 77 switch (value) {
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.h b/drivers/gpu/nvgpu/gm20b/hal_gm20b.h
index 1e149ce2..22eae182 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GM20B Graphics 2 * GM20B Graphics
3 * 3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -27,4 +27,5 @@
27struct gk20a; 27struct gk20a;
28 28
29int gm20b_init_hal(struct gk20a *g); 29int gm20b_init_hal(struct gk20a *g);
30int gm20b_get_litter_value(struct gk20a *g, int value);
30#endif 31#endif
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index f298f26c..61284225 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -80,7 +80,7 @@
80#include <nvgpu/hw/gp10b/hw_pram_gp10b.h> 80#include <nvgpu/hw/gp10b/hw_pram_gp10b.h>
81#include <nvgpu/hw/gp10b/hw_pwr_gp10b.h> 81#include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
82 82
83static int gp10b_get_litter_value(struct gk20a *g, int value) 83int gp10b_get_litter_value(struct gk20a *g, int value)
84{ 84{
85 int ret = EINVAL; 85 int ret = EINVAL;
86 switch (value) { 86 switch (value) {
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
index f2924809..cf3c295d 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GP10B Tegra HAL interface 2 * GP10B Tegra HAL interface
3 * 3 *
4 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -27,4 +27,5 @@
27struct gk20a; 27struct gk20a;
28 28
29int gp10b_init_hal(struct gk20a *gops); 29int gp10b_init_hal(struct gk20a *gops);
30int gp10b_get_litter_value(struct gk20a *g, int value);
30#endif 31#endif
diff --git a/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c b/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c
index e53a3c18..bd225f0c 100644
--- a/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c
@@ -43,14 +43,9 @@ int vgpu_ce2_nonstall_isr(struct gk20a *g,
43 return 0; 43 return 0;
44} 44}
45 45
46static u32 vgpu_ce_get_num_pce(struct gk20a *g) 46u32 vgpu_ce_get_num_pce(struct gk20a *g)
47{ 47{
48 struct vgpu_priv_data *priv = vgpu_get_priv_data(g); 48 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
49 49
50 return priv->constants.num_pce; 50 return priv->constants.num_pce;
51} 51}
52
53void vgpu_init_ce2_ops(struct gpu_ops *gops)
54{
55 gops->ce2.get_num_pce = vgpu_ce_get_num_pce;
56}
diff --git a/drivers/gpu/nvgpu/vgpu/css_vgpu.c b/drivers/gpu/nvgpu/vgpu/css_vgpu.c
index 0b3c6a25..bcb01fac 100644
--- a/drivers/gpu/nvgpu/vgpu/css_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/css_vgpu.c
@@ -29,6 +29,7 @@
29#include "gk20a/platform_gk20a.h" 29#include "gk20a/platform_gk20a.h"
30#include "gk20a/css_gr_gk20a.h" 30#include "gk20a/css_gr_gk20a.h"
31#include "vgpu.h" 31#include "vgpu.h"
32#include "css_vgpu.h"
32 33
33static struct tegra_hv_ivm_cookie *css_cookie; 34static struct tegra_hv_ivm_cookie *css_cookie;
34 35
@@ -93,7 +94,7 @@ fail:
93 return err; 94 return err;
94} 95}
95 96
96static void vgpu_css_release_snapshot_buffer(struct gr_gk20a *gr) 97void vgpu_css_release_snapshot_buffer(struct gr_gk20a *gr)
97{ 98{
98 struct gk20a_cs_snapshot *data = gr->cs_data; 99 struct gk20a_cs_snapshot *data = gr->cs_data;
99 100
@@ -108,7 +109,7 @@ static void vgpu_css_release_snapshot_buffer(struct gr_gk20a *gr)
108 gk20a_dbg_info("cyclestats(vgpu): buffer for snapshots released\n"); 109 gk20a_dbg_info("cyclestats(vgpu): buffer for snapshots released\n");
109} 110}
110 111
111static int vgpu_css_flush_snapshots(struct channel_gk20a *ch, 112int vgpu_css_flush_snapshots(struct channel_gk20a *ch,
112 u32 *pending, bool *hw_overflow) 113 u32 *pending, bool *hw_overflow)
113{ 114{
114 struct gk20a *g = ch->g; 115 struct gk20a *g = ch->g;
@@ -164,7 +165,7 @@ static int vgpu_css_attach(struct channel_gk20a *ch,
164 return err; 165 return err;
165} 166}
166 167
167static int vgpu_css_detach(struct channel_gk20a *ch, 168int vgpu_css_detach(struct channel_gk20a *ch,
168 struct gk20a_cs_snapshot_client *cs_client) 169 struct gk20a_cs_snapshot_client *cs_client)
169{ 170{
170 struct gk20a *g = ch->g; 171 struct gk20a *g = ch->g;
@@ -190,7 +191,7 @@ static int vgpu_css_detach(struct channel_gk20a *ch,
190 return err; 191 return err;
191} 192}
192 193
193static int vgpu_css_enable_snapshot_buffer(struct channel_gk20a *ch, 194int vgpu_css_enable_snapshot_buffer(struct channel_gk20a *ch,
194 struct gk20a_cs_snapshot_client *cs_client) 195 struct gk20a_cs_snapshot_client *cs_client)
195{ 196{
196 int ret; 197 int ret;
@@ -202,17 +203,4 @@ static int vgpu_css_enable_snapshot_buffer(struct channel_gk20a *ch,
202 ret = vgpu_css_init_snapshot_buffer(&ch->g->gr); 203 ret = vgpu_css_init_snapshot_buffer(&ch->g->gr);
203 return ret; 204 return ret;
204} 205}
205
206void vgpu_init_css_ops(struct gpu_ops *gops)
207{
208 gops->css.enable_snapshot = vgpu_css_enable_snapshot_buffer;
209 gops->css.disable_snapshot = vgpu_css_release_snapshot_buffer;
210 gops->css.check_data_available = vgpu_css_flush_snapshots;
211 gops->css.detach_snapshot = vgpu_css_detach;
212
213 /* Following entries are not used when virtual, NULL them */
214 gops->css.set_handled_snapshots = NULL;
215 gops->css.allocate_perfmon_ids = NULL;
216 gops->css.release_perfmon_ids = NULL;
217}
218#endif /* CONFIG_GK20A_CYCLE_STATS */ 206#endif /* CONFIG_GK20A_CYCLE_STATS */
diff --git a/drivers/gpu/nvgpu/vgpu/debug_vgpu.c b/drivers/gpu/nvgpu/vgpu/css_vgpu.h
index cb858c22..b61c9862 100644
--- a/drivers/gpu/nvgpu/vgpu/debug_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/css_vgpu.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2015 NVIDIA Corporation. All rights reserved. 2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -20,14 +20,21 @@
20 * DEALINGS IN THE SOFTWARE. 20 * DEALINGS IN THE SOFTWARE.
21 */ 21 */
22 22
23#include "vgpu/vgpu.h" 23#ifndef _CSS_VGPU_H_
24#define _CSS_VGPU_H_
24 25
25static void vgpu_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o) 26#include <nvgpu/types.h>
26{
27 /* debug dump not supported */
28}
29 27
30void vgpu_init_debug_ops(struct gpu_ops *gops) 28struct gr_gk20a;
31{ 29struct channel_gk20a;
32 gops->debug.show_dump = vgpu_debug_show_dump; 30struct gk20a_cs_snapshot_client;
33} 31
32void vgpu_css_release_snapshot_buffer(struct gr_gk20a *gr);
33int vgpu_css_flush_snapshots(struct channel_gk20a *ch,
34 u32 *pending, bool *hw_overflow);
35int vgpu_css_detach(struct channel_gk20a *ch,
36 struct gk20a_cs_snapshot_client *cs_client);
37int vgpu_css_enable_snapshot_buffer(struct channel_gk20a *ch,
38 struct gk20a_cs_snapshot_client *cs_client);
39
40#endif
diff --git a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c
index 416b8903..6e8ab561 100644
--- a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.c
@@ -27,10 +27,11 @@
27#include "gk20a/channel_gk20a.h" 27#include "gk20a/channel_gk20a.h"
28#include "gk20a/dbg_gpu_gk20a.h" 28#include "gk20a/dbg_gpu_gk20a.h"
29#include "vgpu.h" 29#include "vgpu.h"
30#include "dbg_vgpu.h"
30 31
31#include <nvgpu/bug.h> 32#include <nvgpu/bug.h>
32 33
33static int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s, 34int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s,
34 struct nvgpu_dbg_gpu_reg_op *ops, 35 struct nvgpu_dbg_gpu_reg_op *ops,
35 u64 num_ops) 36 u64 num_ops)
36{ 37{
@@ -76,7 +77,7 @@ fail:
76 return err; 77 return err;
77} 78}
78 79
79static int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, __u32 mode) 80int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, __u32 mode)
80{ 81{
81 struct tegra_vgpu_cmd_msg msg; 82 struct tegra_vgpu_cmd_msg msg;
82 struct tegra_vgpu_set_powergate_params *p = &msg.params.set_powergate; 83 struct tegra_vgpu_set_powergate_params *p = &msg.params.set_powergate;
@@ -124,7 +125,7 @@ static int vgpu_sendrecv_prof_cmd(struct dbg_session_gk20a *dbg_s, u32 mode)
124 return err; 125 return err;
125} 126}
126 127
127static bool vgpu_check_and_set_global_reservation( 128bool vgpu_check_and_set_global_reservation(
128 struct dbg_session_gk20a *dbg_s, 129 struct dbg_session_gk20a *dbg_s,
129 struct dbg_profiler_object_data *prof_obj) 130 struct dbg_profiler_object_data *prof_obj)
130{ 131{
@@ -144,7 +145,7 @@ static bool vgpu_check_and_set_global_reservation(
144 return false; 145 return false;
145} 146}
146 147
147static bool vgpu_check_and_set_context_reservation( 148bool vgpu_check_and_set_context_reservation(
148 struct dbg_session_gk20a *dbg_s, 149 struct dbg_session_gk20a *dbg_s,
149 struct dbg_profiler_object_data *prof_obj) 150 struct dbg_profiler_object_data *prof_obj)
150{ 151{
@@ -167,7 +168,7 @@ static bool vgpu_check_and_set_context_reservation(
167 return false; 168 return false;
168} 169}
169 170
170static void vgpu_release_profiler_reservation( 171void vgpu_release_profiler_reservation(
171 struct dbg_session_gk20a *dbg_s, 172 struct dbg_session_gk20a *dbg_s,
172 struct dbg_profiler_object_data *prof_obj) 173 struct dbg_profiler_object_data *prof_obj)
173{ 174{
@@ -205,26 +206,12 @@ static int vgpu_sendrecv_perfbuf_cmd(struct gk20a *g, u64 offset, u32 size)
205 return err; 206 return err;
206} 207}
207 208
208static int vgpu_perfbuffer_enable(struct gk20a *g, u64 offset, u32 size) 209int vgpu_perfbuffer_enable(struct gk20a *g, u64 offset, u32 size)
209{ 210{
210 return vgpu_sendrecv_perfbuf_cmd(g, offset, size); 211 return vgpu_sendrecv_perfbuf_cmd(g, offset, size);
211} 212}
212 213
213static int vgpu_perfbuffer_disable(struct gk20a *g) 214int vgpu_perfbuffer_disable(struct gk20a *g)
214{ 215{
215 return vgpu_sendrecv_perfbuf_cmd(g, 0, 0); 216 return vgpu_sendrecv_perfbuf_cmd(g, 0, 0);
216} 217}
217
218void vgpu_init_dbg_session_ops(struct gpu_ops *gops)
219{
220 gops->dbg_session_ops.exec_reg_ops = vgpu_exec_regops;
221 gops->dbg_session_ops.dbg_set_powergate = vgpu_dbg_set_powergate;
222 gops->dbg_session_ops.check_and_set_global_reservation =
223 vgpu_check_and_set_global_reservation;
224 gops->dbg_session_ops.check_and_set_context_reservation =
225 vgpu_check_and_set_context_reservation;
226 gops->dbg_session_ops.release_profiler_reservation =
227 vgpu_release_profiler_reservation;
228 gops->dbg_session_ops.perfbuffer_enable = vgpu_perfbuffer_enable;
229 gops->dbg_session_ops.perfbuffer_disable = vgpu_perfbuffer_disable;
230}
diff --git a/drivers/gpu/nvgpu/vgpu/dbg_vgpu.h b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.h
new file mode 100644
index 00000000..fcdea931
--- /dev/null
+++ b/drivers/gpu/nvgpu/vgpu/dbg_vgpu.h
@@ -0,0 +1,47 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef _DBG_VGPU_H_
24#define _DBG_VGPU_H_
25
26struct dbg_session_gk20a;
27struct nvgpu_dbg_gpu_reg_op;
28struct dbg_profiler_object_data;
29struct gk20a;
30
31int vgpu_exec_regops(struct dbg_session_gk20a *dbg_s,
32 struct nvgpu_dbg_gpu_reg_op *ops,
33 u64 num_ops);
34int vgpu_dbg_set_powergate(struct dbg_session_gk20a *dbg_s, __u32 mode);
35bool vgpu_check_and_set_global_reservation(
36 struct dbg_session_gk20a *dbg_s,
37 struct dbg_profiler_object_data *prof_obj);
38bool vgpu_check_and_set_context_reservation(
39 struct dbg_session_gk20a *dbg_s,
40 struct dbg_profiler_object_data *prof_obj);
41
42void vgpu_release_profiler_reservation(
43 struct dbg_session_gk20a *dbg_s,
44 struct dbg_profiler_object_data *prof_obj);
45int vgpu_perfbuffer_enable(struct gk20a *g, u64 offset, u32 size);
46int vgpu_perfbuffer_disable(struct gk20a *g);
47#endif
diff --git a/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c b/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c
index 84de9d0b..762cc10a 100644
--- a/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c
@@ -41,7 +41,7 @@ struct vgpu_fecs_trace {
41 void *buf; 41 void *buf;
42}; 42};
43 43
44static int vgpu_fecs_trace_init(struct gk20a *g) 44int vgpu_fecs_trace_init(struct gk20a *g)
45{ 45{
46 struct device *dev = dev_from_gk20a(g); 46 struct device *dev = dev_from_gk20a(g);
47 struct device_node *np = dev->of_node; 47 struct device_node *np = dev->of_node;
@@ -102,7 +102,7 @@ fail:
102 return err; 102 return err;
103} 103}
104 104
105static int vgpu_fecs_trace_deinit(struct gk20a *g) 105int vgpu_fecs_trace_deinit(struct gk20a *g)
106{ 106{
107 struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; 107 struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace;
108 108
@@ -112,7 +112,7 @@ static int vgpu_fecs_trace_deinit(struct gk20a *g)
112 return 0; 112 return 0;
113} 113}
114 114
115static int vgpu_fecs_trace_enable(struct gk20a *g) 115int vgpu_fecs_trace_enable(struct gk20a *g)
116{ 116{
117 struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; 117 struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace;
118 struct tegra_vgpu_cmd_msg msg = { 118 struct tegra_vgpu_cmd_msg msg = {
@@ -128,7 +128,7 @@ static int vgpu_fecs_trace_enable(struct gk20a *g)
128 return err; 128 return err;
129} 129}
130 130
131static int vgpu_fecs_trace_disable(struct gk20a *g) 131int vgpu_fecs_trace_disable(struct gk20a *g)
132{ 132{
133 struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; 133 struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace;
134 struct tegra_vgpu_cmd_msg msg = { 134 struct tegra_vgpu_cmd_msg msg = {
@@ -144,14 +144,14 @@ static int vgpu_fecs_trace_disable(struct gk20a *g)
144 return err; 144 return err;
145} 145}
146 146
147static bool vpgpu_fecs_trace_is_enabled(struct gk20a *g) 147bool vgpu_fecs_trace_is_enabled(struct gk20a *g)
148{ 148{
149 struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; 149 struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace;
150 150
151 return (vcst && vcst->enabled); 151 return (vcst && vcst->enabled);
152} 152}
153 153
154static int vgpu_fecs_trace_poll(struct gk20a *g) 154int vgpu_fecs_trace_poll(struct gk20a *g)
155{ 155{
156 struct tegra_vgpu_cmd_msg msg = { 156 struct tegra_vgpu_cmd_msg msg = {
157 .cmd = TEGRA_VGPU_CMD_FECS_TRACE_POLL, 157 .cmd = TEGRA_VGPU_CMD_FECS_TRACE_POLL,
@@ -165,7 +165,7 @@ static int vgpu_fecs_trace_poll(struct gk20a *g)
165 return err; 165 return err;
166} 166}
167 167
168static int vgpu_alloc_user_buffer(struct gk20a *g, void **buf, size_t *size) 168int vgpu_alloc_user_buffer(struct gk20a *g, void **buf, size_t *size)
169{ 169{
170 struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; 170 struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace;
171 171
@@ -174,12 +174,12 @@ static int vgpu_alloc_user_buffer(struct gk20a *g, void **buf, size_t *size)
174 return 0; 174 return 0;
175} 175}
176 176
177static int vgpu_free_user_buffer(struct gk20a *g) 177int vgpu_free_user_buffer(struct gk20a *g)
178{ 178{
179 return 0; 179 return 0;
180} 180}
181 181
182static int vgpu_mmap_user_buffer(struct gk20a *g, struct vm_area_struct *vma) 182int vgpu_mmap_user_buffer(struct gk20a *g, struct vm_area_struct *vma)
183{ 183{
184 struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; 184 struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace;
185 unsigned long size = vcst->cookie->size; 185 unsigned long size = vcst->cookie->size;
@@ -194,7 +194,7 @@ static int vgpu_mmap_user_buffer(struct gk20a *g, struct vm_area_struct *vma)
194 vma->vm_page_prot); 194 vma->vm_page_prot);
195} 195}
196 196
197static int vgpu_fecs_trace_max_entries(struct gk20a *g, 197int vgpu_fecs_trace_max_entries(struct gk20a *g,
198 struct nvgpu_ctxsw_trace_filter *filter) 198 struct nvgpu_ctxsw_trace_filter *filter)
199{ 199{
200 struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace; 200 struct vgpu_fecs_trace *vcst = (struct vgpu_fecs_trace *)g->fecs_trace;
@@ -206,7 +206,7 @@ static int vgpu_fecs_trace_max_entries(struct gk20a *g,
206#error "FECS trace filter size mismatch!" 206#error "FECS trace filter size mismatch!"
207#endif 207#endif
208 208
209static int vgpu_fecs_trace_set_filter(struct gk20a *g, 209int vgpu_fecs_trace_set_filter(struct gk20a *g,
210 struct nvgpu_ctxsw_trace_filter *filter) 210 struct nvgpu_ctxsw_trace_filter *filter)
211{ 211{
212 struct tegra_vgpu_cmd_msg msg = { 212 struct tegra_vgpu_cmd_msg msg = {
@@ -223,25 +223,6 @@ static int vgpu_fecs_trace_set_filter(struct gk20a *g,
223 return err; 223 return err;
224} 224}
225 225
226void vgpu_init_fecs_trace_ops(struct gpu_ops *ops)
227{
228 ops->fecs_trace.init = vgpu_fecs_trace_init;
229 ops->fecs_trace.deinit = vgpu_fecs_trace_deinit;
230 ops->fecs_trace.enable = vgpu_fecs_trace_enable;
231 ops->fecs_trace.disable = vgpu_fecs_trace_disable;
232 ops->fecs_trace.is_enabled = vpgpu_fecs_trace_is_enabled;
233 ops->fecs_trace.reset = NULL;
234 ops->fecs_trace.flush = NULL;
235 ops->fecs_trace.poll = vgpu_fecs_trace_poll;
236 ops->fecs_trace.bind_channel = NULL;
237 ops->fecs_trace.unbind_channel = NULL;
238 ops->fecs_trace.max_entries = vgpu_fecs_trace_max_entries;
239 ops->fecs_trace.alloc_user_buffer = vgpu_alloc_user_buffer;
240 ops->fecs_trace.free_user_buffer = vgpu_free_user_buffer;
241 ops->fecs_trace.mmap_user_buffer = vgpu_mmap_user_buffer;
242 ops->fecs_trace.set_filter = vgpu_fecs_trace_set_filter;
243}
244
245void vgpu_fecs_trace_data_update(struct gk20a *g) 226void vgpu_fecs_trace_data_update(struct gk20a *g)
246{ 227{
247 gk20a_ctxsw_trace_wake_up(g, 0); 228 gk20a_ctxsw_trace_wake_up(g, 0);
diff --git a/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.h b/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.h
index d20de773..392b344c 100644
--- a/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -23,8 +23,25 @@
23#ifndef __FECS_TRACE_VGPU_H 23#ifndef __FECS_TRACE_VGPU_H
24#define __FECS_TRACE_VGPU_H 24#define __FECS_TRACE_VGPU_H
25 25
26struct gpu_ops; 26#include <nvgpu/types.h>
27void vgpu_init_fecs_trace_ops(struct gpu_ops *ops); 27
28struct gk20a;
29struct vm_area_struct;
30struct nvgpu_ctxsw_trace_filter;
31
28void vgpu_fecs_trace_data_update(struct gk20a *g); 32void vgpu_fecs_trace_data_update(struct gk20a *g);
33int vgpu_fecs_trace_init(struct gk20a *g);
34int vgpu_fecs_trace_deinit(struct gk20a *g);
35int vgpu_fecs_trace_enable(struct gk20a *g);
36int vgpu_fecs_trace_disable(struct gk20a *g);
37bool vgpu_fecs_trace_is_enabled(struct gk20a *g);
38int vgpu_fecs_trace_poll(struct gk20a *g);
39int vgpu_alloc_user_buffer(struct gk20a *g, void **buf, size_t *size);
40int vgpu_free_user_buffer(struct gk20a *g);
41int vgpu_mmap_user_buffer(struct gk20a *g, struct vm_area_struct *vma);
42int vgpu_fecs_trace_max_entries(struct gk20a *g,
43 struct nvgpu_ctxsw_trace_filter *filter);
44int vgpu_fecs_trace_set_filter(struct gk20a *g,
45 struct nvgpu_ctxsw_trace_filter *filter);
29 46
30#endif /* __FECS_TRACE_VGPU_H */ 47#endif /* __FECS_TRACE_VGPU_H */
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index 73a67d91..582894b9 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -32,12 +32,13 @@
32#include <nvgpu/barrier.h> 32#include <nvgpu/barrier.h>
33 33
34#include "vgpu/vgpu.h" 34#include "vgpu/vgpu.h"
35#include "vgpu/fifo_vgpu.h"
35#include "gk20a/ctxsw_trace_gk20a.h" 36#include "gk20a/ctxsw_trace_gk20a.h"
36 37
37#include <nvgpu/hw/gk20a/hw_fifo_gk20a.h> 38#include <nvgpu/hw/gk20a/hw_fifo_gk20a.h>
38#include <nvgpu/hw/gk20a/hw_ram_gk20a.h> 39#include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
39 40
40static void vgpu_channel_bind(struct channel_gk20a *ch) 41void vgpu_channel_bind(struct channel_gk20a *ch)
41{ 42{
42 struct tegra_vgpu_cmd_msg msg; 43 struct tegra_vgpu_cmd_msg msg;
43 struct tegra_vgpu_channel_config_params *p = 44 struct tegra_vgpu_channel_config_params *p =
@@ -56,7 +57,7 @@ static void vgpu_channel_bind(struct channel_gk20a *ch)
56 nvgpu_atomic_set(&ch->bound, true); 57 nvgpu_atomic_set(&ch->bound, true);
57} 58}
58 59
59static void vgpu_channel_unbind(struct channel_gk20a *ch) 60void vgpu_channel_unbind(struct channel_gk20a *ch)
60{ 61{
61 62
62 gk20a_dbg_fn(""); 63 gk20a_dbg_fn("");
@@ -76,7 +77,7 @@ static void vgpu_channel_unbind(struct channel_gk20a *ch)
76 77
77} 78}
78 79
79static int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch) 80int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch)
80{ 81{
81 struct tegra_vgpu_cmd_msg msg; 82 struct tegra_vgpu_cmd_msg msg;
82 struct tegra_vgpu_channel_hwctx_params *p = &msg.params.channel_hwctx; 83 struct tegra_vgpu_channel_hwctx_params *p = &msg.params.channel_hwctx;
@@ -99,7 +100,7 @@ static int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch)
99 return 0; 100 return 0;
100} 101}
101 102
102static void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch) 103void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch)
103{ 104{
104 struct tegra_vgpu_cmd_msg msg; 105 struct tegra_vgpu_cmd_msg msg;
105 struct tegra_vgpu_channel_hwctx_params *p = &msg.params.channel_hwctx; 106 struct tegra_vgpu_channel_hwctx_params *p = &msg.params.channel_hwctx;
@@ -114,7 +115,7 @@ static void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch)
114 WARN_ON(err || msg.ret); 115 WARN_ON(err || msg.ret);
115} 116}
116 117
117static void vgpu_channel_enable(struct channel_gk20a *ch) 118void vgpu_channel_enable(struct channel_gk20a *ch)
118{ 119{
119 struct tegra_vgpu_cmd_msg msg; 120 struct tegra_vgpu_cmd_msg msg;
120 struct tegra_vgpu_channel_config_params *p = 121 struct tegra_vgpu_channel_config_params *p =
@@ -130,7 +131,7 @@ static void vgpu_channel_enable(struct channel_gk20a *ch)
130 WARN_ON(err || msg.ret); 131 WARN_ON(err || msg.ret);
131} 132}
132 133
133static void vgpu_channel_disable(struct channel_gk20a *ch) 134void vgpu_channel_disable(struct channel_gk20a *ch)
134{ 135{
135 struct tegra_vgpu_cmd_msg msg; 136 struct tegra_vgpu_cmd_msg msg;
136 struct tegra_vgpu_channel_config_params *p = 137 struct tegra_vgpu_channel_config_params *p =
@@ -146,7 +147,7 @@ static void vgpu_channel_disable(struct channel_gk20a *ch)
146 WARN_ON(err || msg.ret); 147 WARN_ON(err || msg.ret);
147} 148}
148 149
149static int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base, 150int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base,
150 u32 gpfifo_entries, 151 u32 gpfifo_entries,
151 unsigned long acquire_timeout, u32 flags) 152 unsigned long acquire_timeout, u32 flags)
152{ 153{
@@ -170,7 +171,7 @@ static int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base,
170 return (err || msg.ret) ? -ENOMEM : 0; 171 return (err || msg.ret) ? -ENOMEM : 0;
171} 172}
172 173
173static int vgpu_fifo_init_engine_info(struct fifo_gk20a *f) 174int vgpu_fifo_init_engine_info(struct fifo_gk20a *f)
174{ 175{
175 struct vgpu_priv_data *priv = vgpu_get_priv_data(f->g); 176 struct vgpu_priv_data *priv = vgpu_get_priv_data(f->g);
176 struct tegra_vgpu_engines_info *engines = &priv->constants.engines_info; 177 struct tegra_vgpu_engines_info *engines = &priv->constants.engines_info;
@@ -377,7 +378,7 @@ clean_up:
377 return err; 378 return err;
378} 379}
379 380
380static int vgpu_init_fifo_setup_hw(struct gk20a *g) 381int vgpu_init_fifo_setup_hw(struct gk20a *g)
381{ 382{
382 gk20a_dbg_fn(""); 383 gk20a_dbg_fn("");
383 384
@@ -440,7 +441,7 @@ int vgpu_init_fifo_support(struct gk20a *g)
440 return err; 441 return err;
441} 442}
442 443
443static int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid) 444int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid)
444{ 445{
445 struct fifo_gk20a *f = &g->fifo; 446 struct fifo_gk20a *f = &g->fifo;
446 struct channel_gk20a *ch = &f->channel[chid]; 447 struct channel_gk20a *ch = &f->channel[chid];
@@ -468,7 +469,7 @@ static int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid)
468 return err; 469 return err;
469} 470}
470 471
471static int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) 472int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid)
472{ 473{
473 struct tegra_vgpu_cmd_msg msg; 474 struct tegra_vgpu_cmd_msg msg;
474 struct tegra_vgpu_tsg_preempt_params *p = 475 struct tegra_vgpu_tsg_preempt_params *p =
@@ -579,7 +580,7 @@ static int vgpu_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id,
579 special cases below: runlist->active_channels will NOT be changed. 580 special cases below: runlist->active_channels will NOT be changed.
580 (chid == ~0 && !add) means remove all active channels from runlist. 581 (chid == ~0 && !add) means remove all active channels from runlist.
581 (chid == ~0 && add) means restore all active channels on runlist. */ 582 (chid == ~0 && add) means restore all active channels on runlist. */
582static int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, 583int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id,
583 u32 chid, bool add, bool wait_for_finish) 584 u32 chid, bool add, bool wait_for_finish)
584{ 585{
585 struct fifo_runlist_info_gk20a *runlist = NULL; 586 struct fifo_runlist_info_gk20a *runlist = NULL;
@@ -599,14 +600,14 @@ static int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id,
599 return ret; 600 return ret;
600} 601}
601 602
602static int vgpu_fifo_wait_engine_idle(struct gk20a *g) 603int vgpu_fifo_wait_engine_idle(struct gk20a *g)
603{ 604{
604 gk20a_dbg_fn(""); 605 gk20a_dbg_fn("");
605 606
606 return 0; 607 return 0;
607} 608}
608 609
609static int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority) 610int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority)
610{ 611{
611 struct tegra_vgpu_cmd_msg msg; 612 struct tegra_vgpu_cmd_msg msg;
612 struct tegra_vgpu_channel_priority_params *p = 613 struct tegra_vgpu_channel_priority_params *p =
@@ -646,7 +647,7 @@ static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g,
646 return err ? err : msg.ret; 647 return err ? err : msg.ret;
647} 648}
648 649
649static int vgpu_fifo_set_runlist_interleave(struct gk20a *g, 650int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
650 u32 id, 651 u32 id,
651 bool is_tsg, 652 bool is_tsg,
652 u32 runlist_id, 653 u32 runlist_id,
@@ -674,7 +675,7 @@ static int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
674 return err ? err : msg.ret; 675 return err ? err : msg.ret;
675} 676}
676 677
677static int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) 678int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice)
678{ 679{
679 struct tegra_vgpu_cmd_msg msg; 680 struct tegra_vgpu_cmd_msg msg;
680 struct tegra_vgpu_channel_timeslice_params *p = 681 struct tegra_vgpu_channel_timeslice_params *p =
@@ -695,7 +696,7 @@ static int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice)
695 return err; 696 return err;
696} 697}
697 698
698static int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, 699int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
699 u32 err_code, bool verbose) 700 u32 err_code, bool verbose)
700{ 701{
701 struct tsg_gk20a *tsg = NULL; 702 struct tsg_gk20a *tsg = NULL;
@@ -818,29 +819,3 @@ u32 vgpu_fifo_default_timeslice_us(struct gk20a *g)
818 819
819 return priv->constants.default_timeslice_us; 820 return priv->constants.default_timeslice_us;
820} 821}
821
822void vgpu_init_fifo_ops(struct gpu_ops *gops)
823{
824 gops->fifo.init_fifo_setup_hw = vgpu_init_fifo_setup_hw;
825 gops->fifo.bind_channel = vgpu_channel_bind;
826 gops->fifo.unbind_channel = vgpu_channel_unbind;
827 gops->fifo.enable_channel = vgpu_channel_enable;
828 gops->fifo.disable_channel = vgpu_channel_disable;
829 gops->fifo.alloc_inst = vgpu_channel_alloc_inst;
830 gops->fifo.free_inst = vgpu_channel_free_inst;
831 gops->fifo.setup_ramfc = vgpu_channel_setup_ramfc;
832 gops->fifo.preempt_channel = vgpu_fifo_preempt_channel;
833 gops->fifo.preempt_tsg = vgpu_fifo_preempt_tsg;
834 gops->fifo.enable_tsg = gk20a_enable_tsg;
835 gops->fifo.disable_tsg = gk20a_disable_tsg;
836 /* Not supported yet for vgpu */
837 gops->fifo.tsg_verify_channel_status = NULL;
838 gops->fifo.update_runlist = vgpu_fifo_update_runlist;
839 gops->fifo.wait_engine_idle = vgpu_fifo_wait_engine_idle;
840 gops->fifo.channel_set_priority = vgpu_channel_set_priority;
841 gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave;
842 gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice;
843 gops->fifo.force_reset_ch = vgpu_fifo_force_reset_ch;
844 gops->fifo.init_engine_info = vgpu_fifo_init_engine_info;
845 gops->fifo.default_timeslice_us = vgpu_fifo_default_timeslice_us;
846}
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
new file mode 100644
index 00000000..c5a51f97
--- /dev/null
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h
@@ -0,0 +1,65 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef _FIFO_VGPU_H_
24#define _FIFO_VGPU_H_
25
26#include <nvgpu/types.h>
27
28struct gk20a;
29struct channel_gk20a;
30struct fifo_gk20a;
31struct tsg_gk20a;
32
33int vgpu_init_fifo_setup_hw(struct gk20a *g);
34void vgpu_channel_bind(struct channel_gk20a *ch);
35void vgpu_channel_unbind(struct channel_gk20a *ch);
36int vgpu_channel_alloc_inst(struct gk20a *g, struct channel_gk20a *ch);
37void vgpu_channel_free_inst(struct gk20a *g, struct channel_gk20a *ch);
38void vgpu_channel_enable(struct channel_gk20a *ch);
39void vgpu_channel_disable(struct channel_gk20a *ch);
40int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base,
41 u32 gpfifo_entries,
42 unsigned long acquire_timeout, u32 flags);
43int vgpu_fifo_init_engine_info(struct fifo_gk20a *f);
44int vgpu_fifo_preempt_channel(struct gk20a *g, u32 chid);
45int vgpu_fifo_preempt_tsg(struct gk20a *g, u32 tsgid);
46int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id,
47 u32 chid, bool add, bool wait_for_finish);
48int vgpu_fifo_wait_engine_idle(struct gk20a *g);
49int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority);
50int vgpu_fifo_set_runlist_interleave(struct gk20a *g,
51 u32 id,
52 bool is_tsg,
53 u32 runlist_id,
54 u32 new_level);
55int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice);
56int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch,
57 u32 err_code, bool verbose);
58u32 vgpu_fifo_default_timeslice_us(struct gk20a *g);
59int vgpu_tsg_open(struct tsg_gk20a *tsg);
60int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
61 struct channel_gk20a *ch);
62int vgpu_tsg_unbind_channel(struct channel_gk20a *ch);
63int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice);
64
65#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c
index 0acafa8e..06962a86 100644
--- a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c
+++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -23,7 +23,7 @@
23#include "gk20a/gk20a.h" 23#include "gk20a/gk20a.h"
24#include "vgpu_gr_gm20b.h" 24#include "vgpu_gr_gm20b.h"
25 25
26static int vgpu_gm20b_init_fs_state(struct gk20a *g) 26int vgpu_gm20b_init_fs_state(struct gk20a *g)
27{ 27{
28 struct gr_gk20a *gr = &g->gr; 28 struct gr_gk20a *gr = &g->gr;
29 u32 tpc_index, gpc_index; 29 u32 tpc_index, gpc_index;
@@ -44,8 +44,3 @@ static int vgpu_gm20b_init_fs_state(struct gk20a *g)
44 gr->no_of_sm = sm_id; 44 gr->no_of_sm = sm_id;
45 return 0; 45 return 0;
46} 46}
47
48void vgpu_gm20b_init_gr_ops(struct gpu_ops *gops)
49{
50 gops->gr.init_fs_state = vgpu_gm20b_init_fs_state;
51}
diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.h b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.h
index dda0de7b..993a8f3d 100644
--- a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_gr_gm20b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,6 @@
25 25
26#include "gk20a/gk20a.h" 26#include "gk20a/gk20a.h"
27 27
28void vgpu_gm20b_init_gr_ops(struct gpu_ops *gops); 28int vgpu_gm20b_init_fs_state(struct gk20a *g);
29 29
30#endif 30#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c
index 348510df..618c80f8 100644
--- a/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c
+++ b/drivers/gpu/nvgpu/vgpu/gm20b/vgpu_hal_gm20b.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -22,17 +22,582 @@
22 22
23#include "gm20b/hal_gm20b.h" 23#include "gm20b/hal_gm20b.h"
24#include "vgpu/vgpu.h" 24#include "vgpu/vgpu.h"
25#include "vgpu/fifo_vgpu.h"
26#include "vgpu/gr_vgpu.h"
27#include "vgpu/ltc_vgpu.h"
28#include "vgpu/mm_vgpu.h"
29#include "vgpu/dbg_vgpu.h"
30#include "vgpu/fecs_trace_vgpu.h"
31#include "vgpu/css_vgpu.h"
25#include "vgpu_gr_gm20b.h" 32#include "vgpu_gr_gm20b.h"
26 33
34#include "gk20a/bus_gk20a.h"
35#include "gk20a/flcn_gk20a.h"
36#include "gk20a/mc_gk20a.h"
37#include "gk20a/fb_gk20a.h"
38
39#include "gm20b/gr_gm20b.h"
40#include "gm20b/fifo_gm20b.h"
41#include "gm20b/acr_gm20b.h"
42#include "gm20b/pmu_gm20b.h"
43#include "gm20b/fb_gm20b.h"
44#include "gm20b/bus_gm20b.h"
45#include "gm20b/cde_gm20b.h"
46#include "gm20b/regops_gm20b.h"
47#include "gm20b/clk_gm20b.h"
48#include "gm20b/therm_gm20b.h"
49#include "gm20b/mm_gm20b.h"
50#include "gm20b/gr_ctx_gm20b.h"
51#include "gm20b/gm20b_gating_reglist.h"
52#include "gm20b/ltc_gm20b.h"
53
54#include <nvgpu/enabled.h>
55
56#include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
57#include <nvgpu/hw/gm20b/hw_pwr_gm20b.h>
58#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
59#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
60
61static const struct gpu_ops vgpu_gm20b_ops = {
62 .ltc = {
63 .determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
64 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
65 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
66 .init_cbc = gm20b_ltc_init_cbc,
67 .init_fs_state = vgpu_ltc_init_fs_state,
68 .init_comptags = vgpu_ltc_init_comptags,
69 .cbc_ctrl = NULL,
70 .isr = gm20b_ltc_isr,
71 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
72 .flush = gm20b_flush_ltc,
73 .set_enabled = gm20b_ltc_set_enabled,
74 },
75 .ce2 = {
76 .isr_stall = gk20a_ce2_isr,
77 .isr_nonstall = gk20a_ce2_nonstall_isr,
78 .get_num_pce = vgpu_ce_get_num_pce,
79 },
80 .gr = {
81 .init_gpc_mmu = gr_gm20b_init_gpc_mmu,
82 .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
83 .cb_size_default = gr_gm20b_cb_size_default,
84 .calc_global_ctx_buffer_size =
85 gr_gm20b_calc_global_ctx_buffer_size,
86 .commit_global_attrib_cb = gr_gm20b_commit_global_attrib_cb,
87 .commit_global_bundle_cb = gr_gm20b_commit_global_bundle_cb,
88 .commit_global_cb_manager = gr_gm20b_commit_global_cb_manager,
89 .commit_global_pagepool = gr_gm20b_commit_global_pagepool,
90 .handle_sw_method = gr_gm20b_handle_sw_method,
91 .set_alpha_circular_buffer_size =
92 gr_gm20b_set_alpha_circular_buffer_size,
93 .set_circular_buffer_size = gr_gm20b_set_circular_buffer_size,
94 .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
95 .is_valid_class = gr_gm20b_is_valid_class,
96 .is_valid_gfx_class = gr_gm20b_is_valid_gfx_class,
97 .is_valid_compute_class = gr_gm20b_is_valid_compute_class,
98 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
99 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
100 .init_fs_state = vgpu_gm20b_init_fs_state,
101 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
102 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
103 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
104 .set_gpc_tpc_mask = gr_gm20b_set_gpc_tpc_mask,
105 .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
106 .free_channel_ctx = vgpu_gr_free_channel_ctx,
107 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
108 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
109 .get_zcull_info = vgpu_gr_get_zcull_info,
110 .is_tpc_addr = gr_gm20b_is_tpc_addr,
111 .get_tpc_num = gr_gm20b_get_tpc_num,
112 .detect_sm_arch = vgpu_gr_detect_sm_arch,
113 .add_zbc_color = gr_gk20a_add_zbc_color,
114 .add_zbc_depth = gr_gk20a_add_zbc_depth,
115 .zbc_set_table = vgpu_gr_add_zbc,
116 .zbc_query_table = vgpu_gr_query_zbc,
117 .pmu_save_zbc = gk20a_pmu_save_zbc,
118 .add_zbc = gr_gk20a_add_zbc,
119 .pagepool_default_size = gr_gm20b_pagepool_default_size,
120 .init_ctx_state = vgpu_gr_init_ctx_state,
121 .alloc_gr_ctx = vgpu_gr_alloc_gr_ctx,
122 .free_gr_ctx = vgpu_gr_free_gr_ctx,
123 .update_ctxsw_preemption_mode =
124 gr_gm20b_update_ctxsw_preemption_mode,
125 .dump_gr_regs = NULL,
126 .update_pc_sampling = gr_gm20b_update_pc_sampling,
127 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
128 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
129 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
130 .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
131 .get_max_fbps_count = vgpu_gr_get_max_fbps_count,
132 .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
133 .wait_empty = gr_gk20a_wait_idle,
134 .init_cyclestats = gr_gm20b_init_cyclestats,
135 .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
136 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
137 .bpt_reg_info = gr_gm20b_bpt_reg_info,
138 .get_access_map = gr_gm20b_get_access_map,
139 .handle_fecs_error = gk20a_gr_handle_fecs_error,
140 .handle_sm_exception = gr_gk20a_handle_sm_exception,
141 .handle_tex_exception = gr_gk20a_handle_tex_exception,
142 .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions,
143 .enable_exceptions = gk20a_gr_enable_exceptions,
144 .get_lrf_tex_ltc_dram_override = NULL,
145 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
146 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
147 .record_sm_error_state = gm20b_gr_record_sm_error_state,
148 .update_sm_error_state = gm20b_gr_update_sm_error_state,
149 .clear_sm_error_state = vgpu_gr_clear_sm_error_state,
150 .suspend_contexts = vgpu_gr_suspend_contexts,
151 .resume_contexts = vgpu_gr_resume_contexts,
152 .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags,
153 .fuse_override = gm20b_gr_fuse_override,
154 .init_sm_id_table = gr_gk20a_init_sm_id_table,
155 .load_smid_config = gr_gm20b_load_smid_config,
156 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
157 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
158 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
159 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
160 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
161 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
162 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
163 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
164 .commit_inst = vgpu_gr_commit_inst,
165 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
166 .write_pm_ptr = gr_gk20a_write_pm_ptr,
167 .init_elcg_mode = gr_gk20a_init_elcg_mode,
168 .load_tpc_mask = gr_gm20b_load_tpc_mask,
169 .inval_icache = gr_gk20a_inval_icache,
170 .trigger_suspend = gr_gk20a_trigger_suspend,
171 .wait_for_pause = gr_gk20a_wait_for_pause,
172 .resume_from_pause = gr_gk20a_resume_from_pause,
173 .clear_sm_errors = gr_gk20a_clear_sm_errors,
174 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
175 .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
176 .sm_debugger_attached = gk20a_gr_sm_debugger_attached,
177 .suspend_single_sm = gk20a_gr_suspend_single_sm,
178 .suspend_all_sms = gk20a_gr_suspend_all_sms,
179 .resume_single_sm = gk20a_gr_resume_single_sm,
180 .resume_all_sms = gk20a_gr_resume_all_sms,
181 .get_sm_hww_warp_esr = gk20a_gr_get_sm_hww_warp_esr,
182 .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr,
183 .get_sm_no_lock_down_hww_global_esr_mask =
184 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
185 .lock_down_sm = gk20a_gr_lock_down_sm,
186 .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down,
187 .clear_sm_hww = gm20b_gr_clear_sm_hww,
188 .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
189 .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
190 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
191 .init_ctxsw_hdr_data = gk20a_gr_init_ctxsw_hdr_data,
192 .set_boosted_ctx = NULL,
193 .update_boosted_ctx = NULL,
194 },
195 .fb = {
196 .reset = fb_gk20a_reset,
197 .init_hw = gk20a_fb_init_hw,
198 .init_fs_state = fb_gm20b_init_fs_state,
199 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
200 .set_use_full_comp_tag_line =
201 gm20b_fb_set_use_full_comp_tag_line,
202 .compression_page_size = gm20b_fb_compression_page_size,
203 .compressible_page_size = gm20b_fb_compressible_page_size,
204 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
205 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
206 .read_wpr_info = gm20b_fb_read_wpr_info,
207 .is_debug_mode_enabled = NULL,
208 .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
209 .tlb_invalidate = vgpu_mm_tlb_invalidate,
210 },
211 .clock_gating = {
212 .slcg_bus_load_gating_prod =
213 gm20b_slcg_bus_load_gating_prod,
214 .slcg_ce2_load_gating_prod =
215 gm20b_slcg_ce2_load_gating_prod,
216 .slcg_chiplet_load_gating_prod =
217 gm20b_slcg_chiplet_load_gating_prod,
218 .slcg_ctxsw_firmware_load_gating_prod =
219 gm20b_slcg_ctxsw_firmware_load_gating_prod,
220 .slcg_fb_load_gating_prod =
221 gm20b_slcg_fb_load_gating_prod,
222 .slcg_fifo_load_gating_prod =
223 gm20b_slcg_fifo_load_gating_prod,
224 .slcg_gr_load_gating_prod =
225 gr_gm20b_slcg_gr_load_gating_prod,
226 .slcg_ltc_load_gating_prod =
227 ltc_gm20b_slcg_ltc_load_gating_prod,
228 .slcg_perf_load_gating_prod =
229 gm20b_slcg_perf_load_gating_prod,
230 .slcg_priring_load_gating_prod =
231 gm20b_slcg_priring_load_gating_prod,
232 .slcg_pmu_load_gating_prod =
233 gm20b_slcg_pmu_load_gating_prod,
234 .slcg_therm_load_gating_prod =
235 gm20b_slcg_therm_load_gating_prod,
236 .slcg_xbar_load_gating_prod =
237 gm20b_slcg_xbar_load_gating_prod,
238 .blcg_bus_load_gating_prod =
239 gm20b_blcg_bus_load_gating_prod,
240 .blcg_ctxsw_firmware_load_gating_prod =
241 gm20b_blcg_ctxsw_firmware_load_gating_prod,
242 .blcg_fb_load_gating_prod =
243 gm20b_blcg_fb_load_gating_prod,
244 .blcg_fifo_load_gating_prod =
245 gm20b_blcg_fifo_load_gating_prod,
246 .blcg_gr_load_gating_prod =
247 gm20b_blcg_gr_load_gating_prod,
248 .blcg_ltc_load_gating_prod =
249 gm20b_blcg_ltc_load_gating_prod,
250 .blcg_pwr_csb_load_gating_prod =
251 gm20b_blcg_pwr_csb_load_gating_prod,
252 .blcg_xbar_load_gating_prod =
253 gm20b_blcg_xbar_load_gating_prod,
254 .blcg_pmu_load_gating_prod =
255 gm20b_blcg_pmu_load_gating_prod,
256 .pg_gr_load_gating_prod =
257 gr_gm20b_pg_gr_load_gating_prod,
258 },
259 .fifo = {
260 .init_fifo_setup_hw = vgpu_init_fifo_setup_hw,
261 .bind_channel = vgpu_channel_bind,
262 .unbind_channel = vgpu_channel_unbind,
263 .disable_channel = vgpu_channel_disable,
264 .enable_channel = vgpu_channel_enable,
265 .alloc_inst = vgpu_channel_alloc_inst,
266 .free_inst = vgpu_channel_free_inst,
267 .setup_ramfc = vgpu_channel_setup_ramfc,
268 .channel_set_priority = vgpu_channel_set_priority,
269 .channel_set_timeslice = vgpu_channel_set_timeslice,
270 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
271 .setup_userd = gk20a_fifo_setup_userd,
272 .userd_gp_get = gk20a_fifo_userd_gp_get,
273 .userd_gp_put = gk20a_fifo_userd_gp_put,
274 .userd_pb_get = gk20a_fifo_userd_pb_get,
275 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
276 .preempt_channel = vgpu_fifo_preempt_channel,
277 .preempt_tsg = vgpu_fifo_preempt_tsg,
278 .enable_tsg = gk20a_enable_tsg,
279 .disable_tsg = gk20a_disable_tsg,
280 .tsg_verify_channel_status = NULL,
281 .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload,
282 .update_runlist = vgpu_fifo_update_runlist,
283 .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
284 .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info,
285 .wait_engine_idle = vgpu_fifo_wait_engine_idle,
286 .get_num_fifos = gm20b_fifo_get_num_fifos,
287 .get_pbdma_signature = gk20a_fifo_get_pbdma_signature,
288 .set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
289 .tsg_set_timeslice = vgpu_tsg_set_timeslice,
290 .tsg_open = vgpu_tsg_open,
291 .force_reset_ch = vgpu_fifo_force_reset_ch,
292 .engine_enum_from_type = gk20a_fifo_engine_enum_from_type,
293 .device_info_data_parse = gm20b_device_info_data_parse,
294 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
295 .init_engine_info = vgpu_fifo_init_engine_info,
296 .runlist_entry_size = ram_rl_entry_size_v,
297 .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
298 .get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
299 .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
300 .dump_pbdma_status = gk20a_dump_pbdma_status,
301 .dump_eng_status = gk20a_dump_eng_status,
302 .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
303 .intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
304 .is_preempt_pending = gk20a_fifo_is_preempt_pending,
305 .init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs,
306 .reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
307 .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
308 .handle_sched_error = gk20a_fifo_handle_sched_error,
309 .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
310 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
311 .tsg_bind_channel = vgpu_tsg_bind_channel,
312 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
313#ifdef CONFIG_TEGRA_GK20A_NVHOST
314 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
315 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
316 .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
317 .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
318 .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
319 .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
320#endif
321 },
322 .gr_ctx = {
323 .get_netlist_name = gr_gm20b_get_netlist_name,
324 .is_fw_defined = gr_gm20b_is_firmware_defined,
325 },
326 .mm = {
327 .support_sparse = gm20b_mm_support_sparse,
328 .gmmu_map = vgpu_locked_gmmu_map,
329 .gmmu_unmap = vgpu_locked_gmmu_unmap,
330 .vm_bind_channel = vgpu_vm_bind_channel,
331 .fb_flush = vgpu_mm_fb_flush,
332 .l2_invalidate = vgpu_mm_l2_invalidate,
333 .l2_flush = vgpu_mm_l2_flush,
334 .cbc_clean = gk20a_mm_cbc_clean,
335 .set_big_page_size = gm20b_mm_set_big_page_size,
336 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
337 .get_default_big_page_size = gm20b_mm_get_default_big_page_size,
338 .gpu_phys_addr = gm20b_gpu_phys_addr,
339 .get_iommu_bit = gk20a_mm_get_iommu_bit,
340 .get_mmu_levels = gk20a_mm_get_mmu_levels,
341 .init_pdb = gk20a_mm_init_pdb,
342 .init_mm_setup_hw = NULL,
343 .is_bar1_supported = gm20b_mm_is_bar1_supported,
344 .init_inst_block = gk20a_init_inst_block,
345 .mmu_fault_pending = gk20a_fifo_mmu_fault_pending,
346 },
347 .therm = {
348 .init_therm_setup_hw = gm20b_init_therm_setup_hw,
349 .elcg_init_idle_filters = gk20a_elcg_init_idle_filters,
350 },
351 .pmu = {
352 .pmu_setup_elpg = gm20b_pmu_setup_elpg,
353 .pmu_get_queue_head = pwr_pmu_queue_head_r,
354 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
355 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
356 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
357 .pmu_queue_head = gk20a_pmu_queue_head,
358 .pmu_queue_tail = gk20a_pmu_queue_tail,
359 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
360 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
361 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
362 .pmu_mutex_release = gk20a_pmu_mutex_release,
363 .write_dmatrfbase = gm20b_write_dmatrfbase,
364 .pmu_elpg_statistics = gk20a_pmu_elpg_statistics,
365 .pmu_pg_init_param = NULL,
366 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
367 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
368 .pmu_is_lpwr_feature_supported = NULL,
369 .pmu_lpwr_enable_pg = NULL,
370 .pmu_lpwr_disable_pg = NULL,
371 .pmu_pg_param_post_init = NULL,
372 .dump_secure_fuses = pmu_dump_security_fuses_gm20b,
373 .reset_engine = gk20a_pmu_engine_reset,
374 .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
375 },
376 .clk = {
377 .init_clk_support = gm20b_init_clk_support,
378 .suspend_clk_support = gm20b_suspend_clk_support,
379#ifdef CONFIG_DEBUG_FS
380 .init_debugfs = gm20b_clk_init_debugfs,
381#endif
382 .get_voltage = gm20b_clk_get_voltage,
383 .get_gpcclk_clock_counter = gm20b_clk_get_gpcclk_clock_counter,
384 .pll_reg_write = gm20b_clk_pll_reg_write,
385 .get_pll_debug_data = gm20b_clk_get_pll_debug_data,
386 },
387 .regops = {
388 .get_global_whitelist_ranges =
389 gm20b_get_global_whitelist_ranges,
390 .get_global_whitelist_ranges_count =
391 gm20b_get_global_whitelist_ranges_count,
392 .get_context_whitelist_ranges =
393 gm20b_get_context_whitelist_ranges,
394 .get_context_whitelist_ranges_count =
395 gm20b_get_context_whitelist_ranges_count,
396 .get_runcontrol_whitelist = gm20b_get_runcontrol_whitelist,
397 .get_runcontrol_whitelist_count =
398 gm20b_get_runcontrol_whitelist_count,
399 .get_runcontrol_whitelist_ranges =
400 gm20b_get_runcontrol_whitelist_ranges,
401 .get_runcontrol_whitelist_ranges_count =
402 gm20b_get_runcontrol_whitelist_ranges_count,
403 .get_qctl_whitelist = gm20b_get_qctl_whitelist,
404 .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count,
405 .get_qctl_whitelist_ranges = gm20b_get_qctl_whitelist_ranges,
406 .get_qctl_whitelist_ranges_count =
407 gm20b_get_qctl_whitelist_ranges_count,
408 .apply_smpc_war = gm20b_apply_smpc_war,
409 },
410 .mc = {
411 .intr_enable = mc_gk20a_intr_enable,
412 .intr_unit_config = mc_gk20a_intr_unit_config,
413 .isr_stall = mc_gk20a_isr_stall,
414 .intr_stall = mc_gk20a_intr_stall,
415 .intr_stall_pause = mc_gk20a_intr_stall_pause,
416 .intr_stall_resume = mc_gk20a_intr_stall_resume,
417 .intr_nonstall = mc_gk20a_intr_nonstall,
418 .intr_nonstall_pause = mc_gk20a_intr_nonstall_pause,
419 .intr_nonstall_resume = mc_gk20a_intr_nonstall_resume,
420 .enable = gk20a_mc_enable,
421 .disable = gk20a_mc_disable,
422 .reset = gk20a_mc_reset,
423 .boot_0 = gk20a_mc_boot_0,
424 .is_intr1_pending = mc_gk20a_is_intr1_pending,
425 },
426 .debug = {
427 .show_dump = NULL,
428 },
429 .dbg_session_ops = {
430 .exec_reg_ops = vgpu_exec_regops,
431 .dbg_set_powergate = vgpu_dbg_set_powergate,
432 .check_and_set_global_reservation =
433 vgpu_check_and_set_global_reservation,
434 .check_and_set_context_reservation =
435 vgpu_check_and_set_context_reservation,
436 .release_profiler_reservation =
437 vgpu_release_profiler_reservation,
438 .perfbuffer_enable = vgpu_perfbuffer_enable,
439 .perfbuffer_disable = vgpu_perfbuffer_disable,
440 },
441 .cde = {
442 .get_program_numbers = gm20b_cde_get_program_numbers,
443 },
444 .bus = {
445 .init_hw = gk20a_bus_init_hw,
446 .isr = gk20a_bus_isr,
447 .read_ptimer = vgpu_read_ptimer,
448 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
449 .bar1_bind = gm20b_bus_bar1_bind,
450 },
451#if defined(CONFIG_GK20A_CYCLE_STATS)
452 .css = {
453 .enable_snapshot = vgpu_css_enable_snapshot_buffer,
454 .disable_snapshot = vgpu_css_release_snapshot_buffer,
455 .check_data_available = vgpu_css_flush_snapshots,
456 .detach_snapshot = vgpu_css_detach,
457 .set_handled_snapshots = NULL,
458 .allocate_perfmon_ids = NULL,
459 .release_perfmon_ids = NULL,
460 },
461#endif
462 .falcon = {
463 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
464 },
465 .priv_ring = {
466 .isr = gk20a_priv_ring_isr,
467 },
468 .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
469 .get_litter_value = gm20b_get_litter_value,
470};
471
27int vgpu_gm20b_init_hal(struct gk20a *g) 472int vgpu_gm20b_init_hal(struct gk20a *g)
28{ 473{
29 int err; 474 struct gpu_ops *gops = &g->ops;
475 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
476 u32 val;
477
478 gops->ltc = vgpu_gm20b_ops.ltc;
479 gops->ce2 = vgpu_gm20b_ops.ce2;
480 gops->gr = vgpu_gm20b_ops.gr;
481 gops->fb = vgpu_gm20b_ops.fb;
482 gops->clock_gating = vgpu_gm20b_ops.clock_gating;
483 gops->fifo = vgpu_gm20b_ops.fifo;
484 gops->gr_ctx = vgpu_gm20b_ops.gr_ctx;
485 gops->mm = vgpu_gm20b_ops.mm;
486 gops->therm = vgpu_gm20b_ops.therm;
487 gops->pmu = vgpu_gm20b_ops.pmu;
488 /*
489 * clk must be assigned member by member
490 * since some clk ops are assigned during probe prior to HAL init
491 */
492 gops->clk.init_clk_support = vgpu_gm20b_ops.clk.init_clk_support;
493 gops->clk.suspend_clk_support = vgpu_gm20b_ops.clk.suspend_clk_support;
494 gops->clk.get_voltage = vgpu_gm20b_ops.clk.get_voltage;
495 gops->clk.get_gpcclk_clock_counter =
496 vgpu_gm20b_ops.clk.get_gpcclk_clock_counter;
497 gops->clk.pll_reg_write = vgpu_gm20b_ops.clk.pll_reg_write;
498 gops->clk.get_pll_debug_data = vgpu_gm20b_ops.clk.get_pll_debug_data;
499
500 gops->regops = vgpu_gm20b_ops.regops;
501 gops->mc = vgpu_gm20b_ops.mc;
502 gops->dbg_session_ops = vgpu_gm20b_ops.dbg_session_ops;
503 gops->debug = vgpu_gm20b_ops.debug;
504 gops->cde = vgpu_gm20b_ops.cde;
505 gops->bus = vgpu_gm20b_ops.bus;
506#if defined(CONFIG_GK20A_CYCLE_STATS)
507 gops->css = vgpu_gm20b_ops.css;
508#endif
509 gops->falcon = vgpu_gm20b_ops.falcon;
510
511 gops->priv_ring = vgpu_gm20b_ops.priv_ring;
512
513 /* Lone functions */
514 gops->chip_init_gpu_characteristics =
515 vgpu_gm20b_ops.chip_init_gpu_characteristics;
516 gops->get_litter_value = vgpu_gm20b_ops.get_litter_value;
517
518 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
519 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
520 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
521
522#ifdef CONFIG_TEGRA_ACR
523 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
524 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
525 } else {
526 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
527 if (!val) {
528 gk20a_dbg_info("priv security is disabled in HW");
529 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
530 } else {
531 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
532 }
533 }
534#else
535 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
536 gk20a_dbg_info("running ASIM with PRIV security disabled");
537 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
538 } else {
539 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
540 if (!val) {
541 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
542 } else {
543 gk20a_dbg_info("priv security is not supported but enabled");
544 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
545 return -EPERM;
546 }
547 }
548#endif
549
550 /* priv security dependent ops */
551 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
552 /* Add in ops from gm20b acr */
553 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported;
554 gops->pmu.prepare_ucode = prepare_ucode_blob;
555 gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn;
556 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap;
557 gops->pmu.is_priv_load = gm20b_is_priv_load;
558 gops->pmu.get_wpr = gm20b_wpr_info;
559 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space;
560 gops->pmu.pmu_populate_loader_cfg =
561 gm20b_pmu_populate_loader_cfg;
562 gops->pmu.flcn_populate_bl_dmem_desc =
563 gm20b_flcn_populate_bl_dmem_desc;
564 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt;
565 gops->pmu.falcon_clear_halt_interrupt_status =
566 clear_halt_interrupt_status;
567 gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1;
568
569 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
570 gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode;
571
572 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
573 } else {
574 /* Inherit from gk20a */
575 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported;
576 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob;
577 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1;
578 gops->pmu.pmu_nsbootstrap = pmu_bootstrap;
579
580 gops->pmu.load_lsfalcon_ucode = NULL;
581 gops->pmu.init_wpr_region = NULL;
582
583 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
584 }
585
586 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
587 g->pmu_lsf_pmu_wpr_init_done = 0;
588 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
589
590 gm20b_init_uncompressed_kind_map();
591 gm20b_init_kind_attr();
592
593 g->name = "gm20b";
30 594
31 err = gm20b_init_hal(g); 595 c->twod_class = FERMI_TWOD_A;
32 if (err) 596 c->threed_class = MAXWELL_B;
33 return err; 597 c->compute_class = MAXWELL_COMPUTE_B;
34 vgpu_init_hal_common(g); 598 c->gpfifo_class = MAXWELL_CHANNEL_GPFIFO_A;
35 vgpu_gm20b_init_gr_ops(&g->ops); 599 c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
600 c->dma_copy_class = MAXWELL_DMA_COPY_A;
36 601
37 return 0; 602 return 0;
38} 603}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
index ec2fcd8e..fa6109ad 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
@@ -31,7 +31,7 @@
31 31
32#include <nvgpu/hw/gp10b/hw_gr_gp10b.h> 32#include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
33 33
34static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, 34void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
35 struct gr_ctx_desc *gr_ctx) 35 struct gr_ctx_desc *gr_ctx)
36{ 36{
37 struct tegra_vgpu_cmd_msg msg = {0}; 37 struct tegra_vgpu_cmd_msg msg = {0};
@@ -59,7 +59,7 @@ static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
59 nvgpu_kfree(g, gr_ctx); 59 nvgpu_kfree(g, gr_ctx);
60} 60}
61 61
62static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, 62int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
63 struct gr_ctx_desc **__gr_ctx, 63 struct gr_ctx_desc **__gr_ctx,
64 struct vm_gk20a *vm, 64 struct vm_gk20a *vm,
65 u32 class, 65 u32 class,
@@ -115,7 +115,7 @@ fail:
115 return err; 115 return err;
116} 116}
117 117
118static int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, 118int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
119 struct gr_ctx_desc *gr_ctx, 119 struct gr_ctx_desc *gr_ctx,
120 struct vm_gk20a *vm, u32 class, 120 struct vm_gk20a *vm, u32 class,
121 u32 graphics_preempt_mode, 121 u32 graphics_preempt_mode,
@@ -267,7 +267,7 @@ fail:
267 return err; 267 return err;
268} 268}
269 269
270static int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, 270int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
271 u32 graphics_preempt_mode, 271 u32 graphics_preempt_mode,
272 u32 compute_preempt_mode) 272 u32 compute_preempt_mode)
273{ 273{
@@ -316,7 +316,7 @@ static int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
316 return err; 316 return err;
317} 317}
318 318
319static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) 319int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g)
320{ 320{
321 struct vgpu_priv_data *priv = vgpu_get_priv_data(g); 321 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
322 int err; 322 int err;
@@ -334,14 +334,3 @@ static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g)
334 334
335 return 0; 335 return 0;
336} 336}
337
338void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops)
339{
340 vgpu_gm20b_init_gr_ops(gops);
341 gops->gr.alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx;
342 gops->gr.free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx;
343 gops->gr.init_ctx_state = vgpu_gr_gp10b_init_ctx_state;
344 gops->gr.set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode;
345 gops->gr.set_ctxsw_preemption_mode =
346 vgpu_gr_gp10b_set_ctxsw_preemption_mode;
347}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h
index 9505749e..baf5a8e9 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,21 @@
25 25
26#include "gk20a/gk20a.h" 26#include "gk20a/gk20a.h"
27 27
28void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops); 28void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
29 struct gr_ctx_desc *gr_ctx);
30int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
31 struct gr_ctx_desc **__gr_ctx,
32 struct vm_gk20a *vm,
33 u32 class,
34 u32 flags);
35int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
36 struct gr_ctx_desc *gr_ctx,
37 struct vm_gk20a *vm, u32 class,
38 u32 graphics_preempt_mode,
39 u32 compute_preempt_mode);
40int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
41 u32 graphics_preempt_mode,
42 u32 compute_preempt_mode);
43int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g);
29 44
30#endif 45#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 8a367f94..aae74e3f 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -21,24 +21,626 @@
21 */ 21 */
22 22
23#include "vgpu/vgpu.h" 23#include "vgpu/vgpu.h"
24#include "vgpu/fifo_vgpu.h"
25#include "vgpu/gr_vgpu.h"
26#include "vgpu/ltc_vgpu.h"
27#include "vgpu/mm_vgpu.h"
28#include "vgpu/dbg_vgpu.h"
29#include "vgpu/fecs_trace_vgpu.h"
30#include "vgpu/css_vgpu.h"
31#include "gp10b/gp10b.h"
24#include "gp10b/hal_gp10b.h" 32#include "gp10b/hal_gp10b.h"
33#include "vgpu/gm20b/vgpu_gr_gm20b.h"
25#include "vgpu_gr_gp10b.h" 34#include "vgpu_gr_gp10b.h"
26#include "vgpu_fifo_gp10b.h"
27#include "vgpu_mm_gp10b.h" 35#include "vgpu_mm_gp10b.h"
28 36
37#include "gk20a/bus_gk20a.h"
38#include "gk20a/pramin_gk20a.h"
39#include "gk20a/flcn_gk20a.h"
40#include "gk20a/mc_gk20a.h"
41#include "gk20a/fb_gk20a.h"
42
43#include "gp10b/mc_gp10b.h"
44#include "gp10b/ltc_gp10b.h"
45#include "gp10b/mm_gp10b.h"
46#include "gp10b/ce_gp10b.h"
47#include "gp10b/fb_gp10b.h"
48#include "gp10b/pmu_gp10b.h"
49#include "gp10b/gr_ctx_gp10b.h"
50#include "gp10b/fifo_gp10b.h"
51#include "gp10b/gp10b_gating_reglist.h"
52#include "gp10b/regops_gp10b.h"
53#include "gp10b/cde_gp10b.h"
54#include "gp10b/therm_gp10b.h"
55#include "gp10b/priv_ring_gp10b.h"
56
57#include "gm20b/ltc_gm20b.h"
58#include "gm20b/gr_gm20b.h"
59#include "gm20b/fifo_gm20b.h"
60#include "gm20b/acr_gm20b.h"
61#include "gm20b/pmu_gm20b.h"
62#include "gm20b/fb_gm20b.h"
63#include "gm20b/mm_gm20b.h"
64
65#include <nvgpu/enabled.h>
66
67#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
68#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
69#include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
70#include <nvgpu/hw/gp10b/hw_top_gp10b.h>
71#include <nvgpu/hw/gp10b/hw_pram_gp10b.h>
72#include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
73
74static const struct gpu_ops vgpu_gp10b_ops = {
75 .ltc = {
76 .determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
77 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
78 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
79 .init_cbc = gm20b_ltc_init_cbc,
80 .init_fs_state = vgpu_ltc_init_fs_state,
81 .init_comptags = vgpu_ltc_init_comptags,
82 .cbc_ctrl = NULL,
83 .isr = gp10b_ltc_isr,
84 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
85 .flush = gm20b_flush_ltc,
86 .set_enabled = gp10b_ltc_set_enabled,
87 },
88 .ce2 = {
89 .isr_stall = gp10b_ce_isr,
90 .isr_nonstall = gp10b_ce_nonstall_isr,
91 .get_num_pce = vgpu_ce_get_num_pce,
92 },
93 .gr = {
94 .init_gpc_mmu = gr_gm20b_init_gpc_mmu,
95 .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
96 .cb_size_default = gr_gp10b_cb_size_default,
97 .calc_global_ctx_buffer_size =
98 gr_gp10b_calc_global_ctx_buffer_size,
99 .commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb,
100 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
101 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
102 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
103 .handle_sw_method = gr_gp10b_handle_sw_method,
104 .set_alpha_circular_buffer_size =
105 gr_gp10b_set_alpha_circular_buffer_size,
106 .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size,
107 .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
108 .is_valid_class = gr_gp10b_is_valid_class,
109 .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class,
110 .is_valid_compute_class = gr_gp10b_is_valid_compute_class,
111 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
112 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
113 .init_fs_state = vgpu_gm20b_init_fs_state,
114 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
115 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
116 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
117 .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask,
118 .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
119 .free_channel_ctx = vgpu_gr_free_channel_ctx,
120 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
121 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
122 .get_zcull_info = vgpu_gr_get_zcull_info,
123 .is_tpc_addr = gr_gm20b_is_tpc_addr,
124 .get_tpc_num = gr_gm20b_get_tpc_num,
125 .detect_sm_arch = vgpu_gr_detect_sm_arch,
126 .add_zbc_color = gr_gp10b_add_zbc_color,
127 .add_zbc_depth = gr_gp10b_add_zbc_depth,
128 .zbc_set_table = vgpu_gr_add_zbc,
129 .zbc_query_table = vgpu_gr_query_zbc,
130 .pmu_save_zbc = gk20a_pmu_save_zbc,
131 .add_zbc = gr_gk20a_add_zbc,
132 .pagepool_default_size = gr_gp10b_pagepool_default_size,
133 .init_ctx_state = vgpu_gr_gp10b_init_ctx_state,
134 .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx,
135 .free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx,
136 .update_ctxsw_preemption_mode =
137 gr_gp10b_update_ctxsw_preemption_mode,
138 .dump_gr_regs = NULL,
139 .update_pc_sampling = gr_gm20b_update_pc_sampling,
140 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
141 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
142 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
143 .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
144 .get_max_fbps_count = vgpu_gr_get_max_fbps_count,
145 .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
146 .wait_empty = gr_gp10b_wait_empty,
147 .init_cyclestats = gr_gp10b_init_cyclestats,
148 .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
149 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
150 .bpt_reg_info = gr_gm20b_bpt_reg_info,
151 .get_access_map = gr_gp10b_get_access_map,
152 .handle_fecs_error = gr_gp10b_handle_fecs_error,
153 .handle_sm_exception = gr_gp10b_handle_sm_exception,
154 .handle_tex_exception = gr_gp10b_handle_tex_exception,
155 .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions,
156 .enable_exceptions = gk20a_gr_enable_exceptions,
157 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
158 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
159 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
160 .record_sm_error_state = gm20b_gr_record_sm_error_state,
161 .update_sm_error_state = gm20b_gr_update_sm_error_state,
162 .clear_sm_error_state = vgpu_gr_clear_sm_error_state,
163 .suspend_contexts = vgpu_gr_suspend_contexts,
164 .resume_contexts = vgpu_gr_resume_contexts,
165 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
166 .fuse_override = gp10b_gr_fuse_override,
167 .init_sm_id_table = gr_gk20a_init_sm_id_table,
168 .load_smid_config = gr_gp10b_load_smid_config,
169 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
170 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
171 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
172 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
173 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
174 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
175 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
176 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
177 .commit_inst = vgpu_gr_commit_inst,
178 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
179 .write_pm_ptr = gr_gk20a_write_pm_ptr,
180 .init_elcg_mode = gr_gk20a_init_elcg_mode,
181 .load_tpc_mask = gr_gm20b_load_tpc_mask,
182 .inval_icache = gr_gk20a_inval_icache,
183 .trigger_suspend = gr_gk20a_trigger_suspend,
184 .wait_for_pause = gr_gk20a_wait_for_pause,
185 .resume_from_pause = gr_gk20a_resume_from_pause,
186 .clear_sm_errors = gr_gk20a_clear_sm_errors,
187 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
188 .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
189 .sm_debugger_attached = gk20a_gr_sm_debugger_attached,
190 .suspend_single_sm = gk20a_gr_suspend_single_sm,
191 .suspend_all_sms = gk20a_gr_suspend_all_sms,
192 .resume_single_sm = gk20a_gr_resume_single_sm,
193 .resume_all_sms = gk20a_gr_resume_all_sms,
194 .get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr,
195 .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr,
196 .get_sm_no_lock_down_hww_global_esr_mask =
197 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
198 .lock_down_sm = gk20a_gr_lock_down_sm,
199 .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down,
200 .clear_sm_hww = gm20b_gr_clear_sm_hww,
201 .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
202 .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
203 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
204 .set_boosted_ctx = NULL,
205 .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode,
206 .set_czf_bypass = gr_gp10b_set_czf_bypass,
207 .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception,
208 .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
209 .init_preemption_state = gr_gp10b_init_preemption_state,
210 .update_boosted_ctx = NULL,
211 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
212 .create_gr_sysfs = gr_gp10b_create_sysfs,
213 .set_ctxsw_preemption_mode =
214 vgpu_gr_gp10b_set_ctxsw_preemption_mode,
215 .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data,
216 },
217 .fb = {
218 .reset = fb_gk20a_reset,
219 .init_hw = gk20a_fb_init_hw,
220 .init_fs_state = fb_gm20b_init_fs_state,
221 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
222 .set_use_full_comp_tag_line =
223 gm20b_fb_set_use_full_comp_tag_line,
224 .compression_page_size = gp10b_fb_compression_page_size,
225 .compressible_page_size = gp10b_fb_compressible_page_size,
226 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
227 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
228 .read_wpr_info = gm20b_fb_read_wpr_info,
229 .is_debug_mode_enabled = NULL,
230 .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
231 .tlb_invalidate = vgpu_mm_tlb_invalidate,
232 },
233 .clock_gating = {
234 .slcg_bus_load_gating_prod =
235 gp10b_slcg_bus_load_gating_prod,
236 .slcg_ce2_load_gating_prod =
237 gp10b_slcg_ce2_load_gating_prod,
238 .slcg_chiplet_load_gating_prod =
239 gp10b_slcg_chiplet_load_gating_prod,
240 .slcg_ctxsw_firmware_load_gating_prod =
241 gp10b_slcg_ctxsw_firmware_load_gating_prod,
242 .slcg_fb_load_gating_prod =
243 gp10b_slcg_fb_load_gating_prod,
244 .slcg_fifo_load_gating_prod =
245 gp10b_slcg_fifo_load_gating_prod,
246 .slcg_gr_load_gating_prod =
247 gr_gp10b_slcg_gr_load_gating_prod,
248 .slcg_ltc_load_gating_prod =
249 ltc_gp10b_slcg_ltc_load_gating_prod,
250 .slcg_perf_load_gating_prod =
251 gp10b_slcg_perf_load_gating_prod,
252 .slcg_priring_load_gating_prod =
253 gp10b_slcg_priring_load_gating_prod,
254 .slcg_pmu_load_gating_prod =
255 gp10b_slcg_pmu_load_gating_prod,
256 .slcg_therm_load_gating_prod =
257 gp10b_slcg_therm_load_gating_prod,
258 .slcg_xbar_load_gating_prod =
259 gp10b_slcg_xbar_load_gating_prod,
260 .blcg_bus_load_gating_prod =
261 gp10b_blcg_bus_load_gating_prod,
262 .blcg_ce_load_gating_prod =
263 gp10b_blcg_ce_load_gating_prod,
264 .blcg_ctxsw_firmware_load_gating_prod =
265 gp10b_blcg_ctxsw_firmware_load_gating_prod,
266 .blcg_fb_load_gating_prod =
267 gp10b_blcg_fb_load_gating_prod,
268 .blcg_fifo_load_gating_prod =
269 gp10b_blcg_fifo_load_gating_prod,
270 .blcg_gr_load_gating_prod =
271 gp10b_blcg_gr_load_gating_prod,
272 .blcg_ltc_load_gating_prod =
273 gp10b_blcg_ltc_load_gating_prod,
274 .blcg_pwr_csb_load_gating_prod =
275 gp10b_blcg_pwr_csb_load_gating_prod,
276 .blcg_pmu_load_gating_prod =
277 gp10b_blcg_pmu_load_gating_prod,
278 .blcg_xbar_load_gating_prod =
279 gp10b_blcg_xbar_load_gating_prod,
280 .pg_gr_load_gating_prod =
281 gr_gp10b_pg_gr_load_gating_prod,
282 },
283 .fifo = {
284 .init_fifo_setup_hw = vgpu_init_fifo_setup_hw,
285 .bind_channel = vgpu_channel_bind,
286 .unbind_channel = vgpu_channel_unbind,
287 .disable_channel = vgpu_channel_disable,
288 .enable_channel = vgpu_channel_enable,
289 .alloc_inst = vgpu_channel_alloc_inst,
290 .free_inst = vgpu_channel_free_inst,
291 .setup_ramfc = vgpu_channel_setup_ramfc,
292 .channel_set_priority = vgpu_channel_set_priority,
293 .channel_set_timeslice = vgpu_channel_set_timeslice,
294 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
295 .setup_userd = gk20a_fifo_setup_userd,
296 .userd_gp_get = gk20a_fifo_userd_gp_get,
297 .userd_gp_put = gk20a_fifo_userd_gp_put,
298 .userd_pb_get = gk20a_fifo_userd_pb_get,
299 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
300 .preempt_channel = vgpu_fifo_preempt_channel,
301 .preempt_tsg = vgpu_fifo_preempt_tsg,
302 .enable_tsg = gk20a_enable_tsg,
303 .disable_tsg = gk20a_disable_tsg,
304 .tsg_verify_channel_status = NULL,
305 .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload,
306 .reschedule_runlist = NULL,
307 .update_runlist = vgpu_fifo_update_runlist,
308 .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
309 .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info,
310 .wait_engine_idle = vgpu_fifo_wait_engine_idle,
311 .get_num_fifos = gm20b_fifo_get_num_fifos,
312 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
313 .set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
314 .tsg_set_timeslice = vgpu_tsg_set_timeslice,
315 .tsg_open = vgpu_tsg_open,
316 .force_reset_ch = vgpu_fifo_force_reset_ch,
317 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
318 .device_info_data_parse = gp10b_device_info_data_parse,
319 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
320 .init_engine_info = vgpu_fifo_init_engine_info,
321 .runlist_entry_size = ram_rl_entry_size_v,
322 .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
323 .get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
324 .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
325 .dump_pbdma_status = gk20a_dump_pbdma_status,
326 .dump_eng_status = gk20a_dump_eng_status,
327 .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
328 .intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
329 .is_preempt_pending = gk20a_fifo_is_preempt_pending,
330 .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs,
331 .reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
332 .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
333 .handle_sched_error = gk20a_fifo_handle_sched_error,
334 .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
335 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
336 .tsg_bind_channel = vgpu_tsg_bind_channel,
337 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
338#ifdef CONFIG_TEGRA_GK20A_NVHOST
339 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
340 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
341 .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
342 .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
343 .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
344 .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
345#endif
346 .resetup_ramfc = NULL,
347 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
348 },
349 .gr_ctx = {
350 .get_netlist_name = gr_gp10b_get_netlist_name,
351 .is_fw_defined = gr_gp10b_is_firmware_defined,
352 },
353#ifdef CONFIG_GK20A_CTXSW_TRACE
354 .fecs_trace = {
355 .alloc_user_buffer = vgpu_alloc_user_buffer,
356 .free_user_buffer = vgpu_free_user_buffer,
357 .mmap_user_buffer = vgpu_mmap_user_buffer,
358 .init = vgpu_fecs_trace_init,
359 .deinit = vgpu_fecs_trace_deinit,
360 .enable = vgpu_fecs_trace_enable,
361 .disable = vgpu_fecs_trace_disable,
362 .is_enabled = vgpu_fecs_trace_is_enabled,
363 .reset = NULL,
364 .flush = NULL,
365 .poll = vgpu_fecs_trace_poll,
366 .bind_channel = NULL,
367 .unbind_channel = NULL,
368 .max_entries = vgpu_fecs_trace_max_entries,
369 .set_filter = vgpu_fecs_trace_set_filter,
370 },
371#endif /* CONFIG_GK20A_CTXSW_TRACE */
372 .mm = {
373 /* FIXME: add support for sparse mappings */
374 .support_sparse = NULL,
375 .gmmu_map = vgpu_gp10b_locked_gmmu_map,
376 .gmmu_unmap = vgpu_locked_gmmu_unmap,
377 .vm_bind_channel = vgpu_vm_bind_channel,
378 .fb_flush = vgpu_mm_fb_flush,
379 .l2_invalidate = vgpu_mm_l2_invalidate,
380 .l2_flush = vgpu_mm_l2_flush,
381 .cbc_clean = gk20a_mm_cbc_clean,
382 .set_big_page_size = gm20b_mm_set_big_page_size,
383 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
384 .get_default_big_page_size = gp10b_mm_get_default_big_page_size,
385 .gpu_phys_addr = gm20b_gpu_phys_addr,
386 .get_iommu_bit = gk20a_mm_get_iommu_bit,
387 .get_mmu_levels = gp10b_mm_get_mmu_levels,
388 .init_pdb = gp10b_mm_init_pdb,
389 .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw,
390 .is_bar1_supported = gm20b_mm_is_bar1_supported,
391 .init_inst_block = gk20a_init_inst_block,
392 .mmu_fault_pending = gk20a_fifo_mmu_fault_pending,
393 .init_bar2_vm = gb10b_init_bar2_vm,
394 .init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup,
395 .remove_bar2_vm = gp10b_remove_bar2_vm,
396 },
397 .pramin = {
398 .enter = gk20a_pramin_enter,
399 .exit = gk20a_pramin_exit,
400 .data032_r = pram_data032_r,
401 },
402 .therm = {
403 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
404 .elcg_init_idle_filters = gp10b_elcg_init_idle_filters,
405 },
406 .pmu = {
407 .pmu_setup_elpg = gp10b_pmu_setup_elpg,
408 .pmu_get_queue_head = pwr_pmu_queue_head_r,
409 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
410 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
411 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
412 .pmu_queue_head = gk20a_pmu_queue_head,
413 .pmu_queue_tail = gk20a_pmu_queue_tail,
414 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
415 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
416 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
417 .pmu_mutex_release = gk20a_pmu_mutex_release,
418 .write_dmatrfbase = gp10b_write_dmatrfbase,
419 .pmu_elpg_statistics = gp10b_pmu_elpg_statistics,
420 .pmu_pg_init_param = gp10b_pg_gr_init,
421 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
422 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
423 .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
424 .reset_engine = gk20a_pmu_engine_reset,
425 .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
426 },
427 .regops = {
428 .get_global_whitelist_ranges =
429 gp10b_get_global_whitelist_ranges,
430 .get_global_whitelist_ranges_count =
431 gp10b_get_global_whitelist_ranges_count,
432 .get_context_whitelist_ranges =
433 gp10b_get_context_whitelist_ranges,
434 .get_context_whitelist_ranges_count =
435 gp10b_get_context_whitelist_ranges_count,
436 .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist,
437 .get_runcontrol_whitelist_count =
438 gp10b_get_runcontrol_whitelist_count,
439 .get_runcontrol_whitelist_ranges =
440 gp10b_get_runcontrol_whitelist_ranges,
441 .get_runcontrol_whitelist_ranges_count =
442 gp10b_get_runcontrol_whitelist_ranges_count,
443 .get_qctl_whitelist = gp10b_get_qctl_whitelist,
444 .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count,
445 .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges,
446 .get_qctl_whitelist_ranges_count =
447 gp10b_get_qctl_whitelist_ranges_count,
448 .apply_smpc_war = gp10b_apply_smpc_war,
449 },
450 .mc = {
451 .intr_enable = mc_gp10b_intr_enable,
452 .intr_unit_config = mc_gp10b_intr_unit_config,
453 .isr_stall = mc_gp10b_isr_stall,
454 .intr_stall = mc_gp10b_intr_stall,
455 .intr_stall_pause = mc_gp10b_intr_stall_pause,
456 .intr_stall_resume = mc_gp10b_intr_stall_resume,
457 .intr_nonstall = mc_gp10b_intr_nonstall,
458 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
459 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
460 .enable = gk20a_mc_enable,
461 .disable = gk20a_mc_disable,
462 .reset = gk20a_mc_reset,
463 .boot_0 = gk20a_mc_boot_0,
464 .is_intr1_pending = mc_gp10b_is_intr1_pending,
465 },
466 .debug = {
467 .show_dump = NULL,
468 },
469 .dbg_session_ops = {
470 .exec_reg_ops = vgpu_exec_regops,
471 .dbg_set_powergate = vgpu_dbg_set_powergate,
472 .check_and_set_global_reservation =
473 vgpu_check_and_set_global_reservation,
474 .check_and_set_context_reservation =
475 vgpu_check_and_set_context_reservation,
476 .release_profiler_reservation =
477 vgpu_release_profiler_reservation,
478 .perfbuffer_enable = vgpu_perfbuffer_enable,
479 .perfbuffer_disable = vgpu_perfbuffer_disable,
480 },
481 .cde = {
482 .get_program_numbers = gp10b_cde_get_program_numbers,
483 .need_scatter_buffer = gp10b_need_scatter_buffer,
484 .populate_scatter_buffer = gp10b_populate_scatter_buffer,
485 },
486 .bus = {
487 .init_hw = gk20a_bus_init_hw,
488 .isr = gk20a_bus_isr,
489 .read_ptimer = vgpu_read_ptimer,
490 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
491 .bar1_bind = gk20a_bus_bar1_bind,
492 },
493#if defined(CONFIG_GK20A_CYCLE_STATS)
494 .css = {
495 .enable_snapshot = vgpu_css_enable_snapshot_buffer,
496 .disable_snapshot = vgpu_css_release_snapshot_buffer,
497 .check_data_available = vgpu_css_flush_snapshots,
498 .detach_snapshot = vgpu_css_detach,
499 .set_handled_snapshots = NULL,
500 .allocate_perfmon_ids = NULL,
501 .release_perfmon_ids = NULL,
502 },
503#endif
504 .falcon = {
505 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
506 },
507 .priv_ring = {
508 .isr = gp10b_priv_ring_isr,
509 },
510 .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
511 .get_litter_value = gp10b_get_litter_value,
512};
513
29int vgpu_gp10b_init_hal(struct gk20a *g) 514int vgpu_gp10b_init_hal(struct gk20a *g)
30{ 515{
31 int err; 516 struct gpu_ops *gops = &g->ops;
517 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
518 u32 val;
519
520 gops->ltc = vgpu_gp10b_ops.ltc;
521 gops->ce2 = vgpu_gp10b_ops.ce2;
522 gops->gr = vgpu_gp10b_ops.gr;
523 gops->fb = vgpu_gp10b_ops.fb;
524 gops->clock_gating = vgpu_gp10b_ops.clock_gating;
525 gops->fifo = vgpu_gp10b_ops.fifo;
526 gops->gr_ctx = vgpu_gp10b_ops.gr_ctx;
527 gops->fecs_trace = vgpu_gp10b_ops.fecs_trace;
528 gops->mm = vgpu_gp10b_ops.mm;
529 gops->pramin = vgpu_gp10b_ops.pramin;
530 gops->therm = vgpu_gp10b_ops.therm;
531 gops->pmu = vgpu_gp10b_ops.pmu;
532 gops->regops = vgpu_gp10b_ops.regops;
533 gops->mc = vgpu_gp10b_ops.mc;
534 gops->debug = vgpu_gp10b_ops.debug;
535 gops->dbg_session_ops = vgpu_gp10b_ops.dbg_session_ops;
536 gops->cde = vgpu_gp10b_ops.cde;
537 gops->bus = vgpu_gp10b_ops.bus;
538#if defined(CONFIG_GK20A_CYCLE_STATS)
539 gops->css = vgpu_gp10b_ops.css;
540#endif
541 gops->falcon = vgpu_gp10b_ops.falcon;
542
543 gops->priv_ring = vgpu_gp10b_ops.priv_ring;
544
545 /* Lone Functions */
546 gops->chip_init_gpu_characteristics =
547 vgpu_gp10b_ops.chip_init_gpu_characteristics;
548 gops->get_litter_value = vgpu_gp10b_ops.get_litter_value;
549
550 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
551 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
552
553#ifdef CONFIG_TEGRA_ACR
554 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
555 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
556 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
557 } else if (g->is_virtual) {
558 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
559 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
560 } else {
561 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
562 if (val) {
563 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
564 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
565 } else {
566 gk20a_dbg_info("priv security is disabled in HW");
567 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
568 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
569 }
570 }
571#else
572 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
573 gk20a_dbg_info("running simulator with PRIV security disabled");
574 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
575 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
576 } else {
577 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
578 if (val) {
579 gk20a_dbg_info("priv security is not supported but enabled");
580 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
581 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
582 return -EPERM;
583 } else {
584 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
585 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
586 }
587 }
588#endif
589
590 /* priv security dependent ops */
591 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
592 /* Add in ops from gm20b acr */
593 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported,
594 gops->pmu.prepare_ucode = prepare_ucode_blob,
595 gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn,
596 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap,
597 gops->pmu.is_priv_load = gm20b_is_priv_load,
598 gops->pmu.get_wpr = gm20b_wpr_info,
599 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space,
600 gops->pmu.pmu_populate_loader_cfg =
601 gm20b_pmu_populate_loader_cfg,
602 gops->pmu.flcn_populate_bl_dmem_desc =
603 gm20b_flcn_populate_bl_dmem_desc,
604 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt,
605 gops->pmu.falcon_clear_halt_interrupt_status =
606 clear_halt_interrupt_status,
607 gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1,
608
609 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
610 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
611 gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap;
612 gops->pmu.is_priv_load = gp10b_is_priv_load;
613
614 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
615 } else {
616 /* Inherit from gk20a */
617 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported,
618 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
619 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1,
620 gops->pmu.pmu_nsbootstrap = pmu_bootstrap,
621
622 gops->pmu.load_lsfalcon_ucode = NULL;
623 gops->pmu.init_wpr_region = NULL;
624 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
625
626 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
627 }
628
629 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
630 g->pmu_lsf_pmu_wpr_init_done = 0;
631 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
632
633 gp10b_init_uncompressed_kind_map();
634 gp10b_init_kind_attr();
32 635
33 gk20a_dbg_fn(""); 636 g->name = "gp10b";
34 637
35 err = gp10b_init_hal(g); 638 c->twod_class = FERMI_TWOD_A;
36 if (err) 639 c->threed_class = PASCAL_A;
37 return err; 640 c->compute_class = PASCAL_COMPUTE_A;
641 c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A;
642 c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
643 c->dma_copy_class = PASCAL_DMA_COPY_A;
38 644
39 vgpu_init_hal_common(g);
40 vgpu_gp10b_init_gr_ops(&g->ops);
41 vgpu_gp10b_init_fifo_ops(&g->ops);
42 vgpu_gp10b_init_mm_ops(&g->ops);
43 return 0; 645 return 0;
44} 646}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c
index cb7008ba..f063961f 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c
@@ -28,7 +28,7 @@
28 28
29#include <nvgpu/bug.h> 29#include <nvgpu/bug.h>
30 30
31static int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g) 31int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g)
32{ 32{
33 g->mm.bypass_smmu = true; 33 g->mm.bypass_smmu = true;
34 g->mm.disable_bigpage = true; 34 g->mm.disable_bigpage = true;
@@ -47,7 +47,7 @@ static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc,
47 return 0; 47 return 0;
48} 48}
49 49
50static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, 50u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm,
51 u64 map_offset, 51 u64 map_offset,
52 struct nvgpu_sgt *sgt, 52 struct nvgpu_sgt *sgt,
53 u64 buffer_offset, 53 u64 buffer_offset,
@@ -200,14 +200,3 @@ fail:
200 200
201 return 0; 201 return 0;
202} 202}
203
204void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops)
205{
206 gk20a_dbg_fn("");
207
208 gops->mm.gmmu_map = vgpu_gp10b_locked_gmmu_map;
209 gops->mm.init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw;
210
211 /* FIXME: add support for sparse mappings */
212 gops->mm.support_sparse = NULL;
213}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h
index a8f0b7bc..fd6760ff 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,21 @@
25 25
26#include "gk20a/gk20a.h" 26#include "gk20a/gk20a.h"
27 27
28void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops); 28u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm,
29 u64 map_offset,
30 struct nvgpu_sgt *sgt,
31 u64 buffer_offset,
32 u64 size,
33 int pgsz_idx,
34 u8 kind_v,
35 u32 ctag_offset,
36 u32 flags,
37 int rw_flag,
38 bool clear_ctags,
39 bool sparse,
40 bool priv,
41 struct vm_gk20a_mapping_batch *batch,
42 enum nvgpu_aperture aperture);
43int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g);
29 44
30#endif 45#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index 7f267f26..96d21c0a 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -26,11 +26,12 @@
26#include <nvgpu/bug.h> 26#include <nvgpu/bug.h>
27 27
28#include "vgpu/vgpu.h" 28#include "vgpu/vgpu.h"
29#include "vgpu/gr_vgpu.h"
29#include "gk20a/dbg_gpu_gk20a.h" 30#include "gk20a/dbg_gpu_gk20a.h"
30 31
31#include <nvgpu/hw/gk20a/hw_gr_gk20a.h> 32#include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
32 33
33static void vgpu_gr_detect_sm_arch(struct gk20a *g) 34void vgpu_gr_detect_sm_arch(struct gk20a *g)
34{ 35{
35 struct vgpu_priv_data *priv = vgpu_get_priv_data(g); 36 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
36 37
@@ -427,7 +428,7 @@ static void vgpu_gr_free_channel_pm_ctx(struct channel_gk20a *c)
427 pm_ctx->mem.gpu_va = 0; 428 pm_ctx->mem.gpu_va = 0;
428} 429}
429 430
430static void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg) 431void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg)
431{ 432{
432 gk20a_dbg_fn(""); 433 gk20a_dbg_fn("");
433 434
@@ -484,7 +485,7 @@ static int vgpu_gr_tsg_bind_gr_ctx(struct tsg_gk20a *tsg)
484 return err; 485 return err;
485} 486}
486 487
487static int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, 488int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c,
488 struct nvgpu_alloc_obj_ctx_args *args) 489 struct nvgpu_alloc_obj_ctx_args *args)
489{ 490{
490 struct gk20a *g = c->g; 491 struct gk20a *g = c->g;
@@ -666,7 +667,7 @@ cleanup:
666 return -ENOMEM; 667 return -ENOMEM;
667} 668}
668 669
669static int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr, 670int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr,
670 struct channel_gk20a *c, u64 zcull_va, 671 struct channel_gk20a *c, u64 zcull_va,
671 u32 mode) 672 u32 mode)
672{ 673{
@@ -686,7 +687,7 @@ static int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr,
686 return (err || msg.ret) ? -ENOMEM : 0; 687 return (err || msg.ret) ? -ENOMEM : 0;
687} 688}
688 689
689static int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr, 690int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr,
690 struct gr_zcull_info *zcull_params) 691 struct gr_zcull_info *zcull_params)
691{ 692{
692 struct tegra_vgpu_cmd_msg msg; 693 struct tegra_vgpu_cmd_msg msg;
@@ -717,14 +718,14 @@ static int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr,
717 return 0; 718 return 0;
718} 719}
719 720
720static u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) 721u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
721{ 722{
722 struct vgpu_priv_data *priv = vgpu_get_priv_data(g); 723 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
723 724
724 return priv->constants.gpc_tpc_mask[gpc_index]; 725 return priv->constants.gpc_tpc_mask[gpc_index];
725} 726}
726 727
727static u32 vgpu_gr_get_max_fbps_count(struct gk20a *g) 728u32 vgpu_gr_get_max_fbps_count(struct gk20a *g)
728{ 729{
729 struct vgpu_priv_data *priv = vgpu_get_priv_data(g); 730 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
730 731
@@ -733,7 +734,7 @@ static u32 vgpu_gr_get_max_fbps_count(struct gk20a *g)
733 return priv->constants.num_fbps; 734 return priv->constants.num_fbps;
734} 735}
735 736
736static u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g) 737u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g)
737{ 738{
738 struct vgpu_priv_data *priv = vgpu_get_priv_data(g); 739 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
739 740
@@ -742,7 +743,7 @@ static u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g)
742 return priv->constants.fbp_en_mask; 743 return priv->constants.fbp_en_mask;
743} 744}
744 745
745static u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g) 746u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g)
746{ 747{
747 struct vgpu_priv_data *priv = vgpu_get_priv_data(g); 748 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
748 749
@@ -751,7 +752,7 @@ static u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g)
751 return priv->constants.ltc_per_fbp; 752 return priv->constants.ltc_per_fbp;
752} 753}
753 754
754static u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g) 755u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g)
755{ 756{
756 struct vgpu_priv_data *priv = vgpu_get_priv_data(g); 757 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
757 758
@@ -760,13 +761,13 @@ static u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g)
760 return priv->constants.max_lts_per_ltc; 761 return priv->constants.max_lts_per_ltc;
761} 762}
762 763
763static u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g) 764u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g)
764{ 765{
765 /* no one use it yet */ 766 /* no one use it yet */
766 return NULL; 767 return NULL;
767} 768}
768 769
769static int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr, 770int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
770 struct zbc_entry *zbc_val) 771 struct zbc_entry *zbc_val)
771{ 772{
772 struct tegra_vgpu_cmd_msg msg = {0}; 773 struct tegra_vgpu_cmd_msg msg = {0};
@@ -797,7 +798,7 @@ static int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
797 return (err || msg.ret) ? -ENOMEM : 0; 798 return (err || msg.ret) ? -ENOMEM : 0;
798} 799}
799 800
800static int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr, 801int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr,
801 struct zbc_query_params *query_params) 802 struct zbc_query_params *query_params)
802{ 803{
803 struct tegra_vgpu_cmd_msg msg = {0}; 804 struct tegra_vgpu_cmd_msg msg = {0};
@@ -997,7 +998,7 @@ int vgpu_gr_nonstall_isr(struct gk20a *g,
997 return 0; 998 return 0;
998} 999}
999 1000
1000static int vgpu_gr_set_sm_debug_mode(struct gk20a *g, 1001int vgpu_gr_set_sm_debug_mode(struct gk20a *g,
1001 struct channel_gk20a *ch, u64 sms, bool enable) 1002 struct channel_gk20a *ch, u64 sms, bool enable)
1002{ 1003{
1003 struct tegra_vgpu_cmd_msg msg; 1004 struct tegra_vgpu_cmd_msg msg;
@@ -1017,7 +1018,7 @@ static int vgpu_gr_set_sm_debug_mode(struct gk20a *g,
1017 return err ? err : msg.ret; 1018 return err ? err : msg.ret;
1018} 1019}
1019 1020
1020static int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g, 1021int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g,
1021 struct channel_gk20a *ch, bool enable) 1022 struct channel_gk20a *ch, bool enable)
1022{ 1023{
1023 struct tegra_vgpu_cmd_msg msg; 1024 struct tegra_vgpu_cmd_msg msg;
@@ -1041,7 +1042,7 @@ static int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g,
1041 return err ? err : msg.ret; 1042 return err ? err : msg.ret;
1042} 1043}
1043 1044
1044static int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, 1045int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
1045 struct channel_gk20a *ch, bool enable) 1046 struct channel_gk20a *ch, bool enable)
1046{ 1047{
1047 struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx; 1048 struct channel_ctx_gk20a *ch_ctx = &ch->ch_ctx;
@@ -1079,7 +1080,7 @@ static int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
1079 return err ? err : msg.ret; 1080 return err ? err : msg.ret;
1080} 1081}
1081 1082
1082static int vgpu_gr_clear_sm_error_state(struct gk20a *g, 1083int vgpu_gr_clear_sm_error_state(struct gk20a *g,
1083 struct channel_gk20a *ch, u32 sm_id) 1084 struct channel_gk20a *ch, u32 sm_id)
1084{ 1085{
1085 struct gr_gk20a *gr = &g->gr; 1086 struct gr_gk20a *gr = &g->gr;
@@ -1172,7 +1173,7 @@ done:
1172 return err; 1173 return err;
1173} 1174}
1174 1175
1175static int vgpu_gr_suspend_contexts(struct gk20a *g, 1176int vgpu_gr_suspend_contexts(struct gk20a *g,
1176 struct dbg_session_gk20a *dbg_s, 1177 struct dbg_session_gk20a *dbg_s,
1177 int *ctx_resident_ch_fd) 1178 int *ctx_resident_ch_fd)
1178{ 1179{
@@ -1180,7 +1181,7 @@ static int vgpu_gr_suspend_contexts(struct gk20a *g,
1180 ctx_resident_ch_fd, TEGRA_VGPU_CMD_SUSPEND_CONTEXTS); 1181 ctx_resident_ch_fd, TEGRA_VGPU_CMD_SUSPEND_CONTEXTS);
1181} 1182}
1182 1183
1183static int vgpu_gr_resume_contexts(struct gk20a *g, 1184int vgpu_gr_resume_contexts(struct gk20a *g,
1184 struct dbg_session_gk20a *dbg_s, 1185 struct dbg_session_gk20a *dbg_s,
1185 int *ctx_resident_ch_fd) 1186 int *ctx_resident_ch_fd)
1186{ 1187{
@@ -1213,33 +1214,3 @@ void vgpu_gr_handle_sm_esr_event(struct gk20a *g,
1213 1214
1214 nvgpu_mutex_release(&g->dbg_sessions_lock); 1215 nvgpu_mutex_release(&g->dbg_sessions_lock);
1215} 1216}
1216
1217void vgpu_init_gr_ops(struct gpu_ops *gops)
1218{
1219 gops->gr.detect_sm_arch = vgpu_gr_detect_sm_arch;
1220 gops->gr.free_channel_ctx = vgpu_gr_free_channel_ctx;
1221 gops->gr.alloc_obj_ctx = vgpu_gr_alloc_obj_ctx;
1222 gops->gr.alloc_gr_ctx = vgpu_gr_alloc_gr_ctx;
1223 gops->gr.free_gr_ctx = vgpu_gr_free_gr_ctx;
1224 gops->gr.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull;
1225 gops->gr.get_zcull_info = vgpu_gr_get_zcull_info;
1226 gops->gr.get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask;
1227 gops->gr.get_max_fbps_count = vgpu_gr_get_max_fbps_count;
1228 gops->gr.get_fbp_en_mask = vgpu_gr_get_fbp_en_mask;
1229 gops->gr.get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp;
1230 gops->gr.get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc;
1231 gops->gr.get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask;
1232 gops->gr.zbc_set_table = vgpu_gr_add_zbc;
1233 gops->gr.zbc_query_table = vgpu_gr_query_zbc;
1234 gops->gr.init_ctx_state = vgpu_gr_init_ctx_state;
1235 gops->gr.set_sm_debug_mode = vgpu_gr_set_sm_debug_mode;
1236 gops->gr.update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode;
1237 gops->gr.update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode;
1238 gops->gr.clear_sm_error_state = vgpu_gr_clear_sm_error_state;
1239 gops->gr.suspend_contexts = vgpu_gr_suspend_contexts;
1240 gops->gr.resume_contexts = vgpu_gr_resume_contexts;
1241 gops->gr.commit_inst = vgpu_gr_commit_inst;
1242 gops->gr.dump_gr_regs = NULL;
1243 gops->gr.set_boosted_ctx = NULL;
1244 gops->gr.update_boosted_ctx = NULL;
1245}
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
index b6df991e..5a5e0928 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.h
@@ -23,6 +23,50 @@
23#ifndef _GR_VGPU_H_ 23#ifndef _GR_VGPU_H_
24#define _GR_VGPU_H_ 24#define _GR_VGPU_H_
25 25
26#include <nvgpu/types.h>
27
28struct gk20a;
29struct channel_gk20a;
30struct nvgpu_alloc_obj_ctx_args;
31struct gr_gk20a;
32struct gr_zcull_info;
33struct zbc_entry;
34struct zbc_query_params;
35struct dbg_session_gk20a;
36
37void vgpu_gr_detect_sm_arch(struct gk20a *g);
38void vgpu_gr_free_channel_ctx(struct channel_gk20a *c, bool is_tsg);
39int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c,
40 struct nvgpu_alloc_obj_ctx_args *args);
41int vgpu_gr_bind_ctxsw_zcull(struct gk20a *g, struct gr_gk20a *gr,
42 struct channel_gk20a *c, u64 zcull_va,
43 u32 mode);
44int vgpu_gr_get_zcull_info(struct gk20a *g, struct gr_gk20a *gr,
45 struct gr_zcull_info *zcull_params);
46u32 vgpu_gr_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
47u32 vgpu_gr_get_max_fbps_count(struct gk20a *g);
48u32 vgpu_gr_get_fbp_en_mask(struct gk20a *g);
49u32 vgpu_gr_get_max_ltc_per_fbp(struct gk20a *g);
50u32 vgpu_gr_get_max_lts_per_ltc(struct gk20a *g);
51u32 *vgpu_gr_rop_l2_en_mask(struct gk20a *g);
52int vgpu_gr_add_zbc(struct gk20a *g, struct gr_gk20a *gr,
53 struct zbc_entry *zbc_val);
54int vgpu_gr_query_zbc(struct gk20a *g, struct gr_gk20a *gr,
55 struct zbc_query_params *query_params);
56int vgpu_gr_set_sm_debug_mode(struct gk20a *g,
57 struct channel_gk20a *ch, u64 sms, bool enable);
58int vgpu_gr_update_smpc_ctxsw_mode(struct gk20a *g,
59 struct channel_gk20a *ch, bool enable);
60int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g,
61 struct channel_gk20a *ch, bool enable);
62int vgpu_gr_clear_sm_error_state(struct gk20a *g,
63 struct channel_gk20a *ch, u32 sm_id);
64int vgpu_gr_suspend_contexts(struct gk20a *g,
65 struct dbg_session_gk20a *dbg_s,
66 int *ctx_resident_ch_fd);
67int vgpu_gr_resume_contexts(struct gk20a *g,
68 struct dbg_session_gk20a *dbg_s,
69 int *ctx_resident_ch_fd);
26int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va); 70int vgpu_gr_commit_inst(struct channel_gk20a *c, u64 gpu_va);
27 71
28#endif 72#endif
diff --git a/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c b/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c
index db39b309..a6848872 100644
--- a/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/ltc_vgpu.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * Virtualized GPU L2 2 * Virtualized GPU L2
3 * 3 *
4 * Copyright (c) 2014-2016 NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2017 NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -23,8 +23,9 @@
23 */ 23 */
24 24
25#include "vgpu/vgpu.h" 25#include "vgpu/vgpu.h"
26#include "vgpu/ltc_vgpu.h"
26 27
27static int vgpu_determine_L2_size_bytes(struct gk20a *g) 28int vgpu_determine_L2_size_bytes(struct gk20a *g)
28{ 29{
29 struct vgpu_priv_data *priv = vgpu_get_priv_data(g); 30 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
30 31
@@ -33,7 +34,7 @@ static int vgpu_determine_L2_size_bytes(struct gk20a *g)
33 return priv->constants.l2_size; 34 return priv->constants.l2_size;
34} 35}
35 36
36static int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) 37int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
37{ 38{
38 struct vgpu_priv_data *priv = vgpu_get_priv_data(g); 39 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
39 u32 max_comptag_lines = 0; 40 u32 max_comptag_lines = 0;
@@ -56,7 +57,7 @@ static int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
56 return 0; 57 return 0;
57} 58}
58 59
59static void vgpu_ltc_init_fs_state(struct gk20a *g) 60void vgpu_ltc_init_fs_state(struct gk20a *g)
60{ 61{
61 struct vgpu_priv_data *priv = vgpu_get_priv_data(g); 62 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
62 63
@@ -64,11 +65,3 @@ static void vgpu_ltc_init_fs_state(struct gk20a *g)
64 65
65 g->ltc_count = priv->constants.ltc_count; 66 g->ltc_count = priv->constants.ltc_count;
66} 67}
67
68void vgpu_init_ltc_ops(struct gpu_ops *gops)
69{
70 gops->ltc.determine_L2_size_bytes = vgpu_determine_L2_size_bytes;
71 gops->ltc.init_comptags = vgpu_ltc_init_comptags;
72 gops->ltc.init_fs_state = vgpu_ltc_init_fs_state;
73 gops->ltc.cbc_ctrl = NULL;
74}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h b/drivers/gpu/nvgpu/vgpu/ltc_vgpu.h
index 8dd016aa..3437b4cb 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h
+++ b/drivers/gpu/nvgpu/vgpu/ltc_vgpu.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -20,11 +20,14 @@
20 * DEALINGS IN THE SOFTWARE. 20 * DEALINGS IN THE SOFTWARE.
21 */ 21 */
22 22
23#ifndef __VGPU_FIFO_GP10B_H__ 23#ifndef _LTC_VGPU_H_
24#define __VGPU_FIFO_GP10B_H__ 24#define _LTC_VGPU_H_
25 25
26#include "gk20a/gk20a.h" 26struct gk20a;
27struct gr_gk20a;
27 28
28void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops); 29int vgpu_determine_L2_size_bytes(struct gk20a *g);
30int vgpu_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr);
31void vgpu_ltc_init_fs_state(struct gk20a *g);
29 32
30#endif 33#endif
diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
index 49517b9a..8dcca0a1 100644
--- a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
@@ -35,6 +35,7 @@
35#include <nvgpu/linux/nvgpu_mem.h> 35#include <nvgpu/linux/nvgpu_mem.h>
36 36
37#include "vgpu/vgpu.h" 37#include "vgpu/vgpu.h"
38#include "vgpu/mm_vgpu.h"
38#include "gk20a/mm_gk20a.h" 39#include "gk20a/mm_gk20a.h"
39#include "gm20b/mm_gm20b.h" 40#include "gm20b/mm_gm20b.h"
40 41
@@ -85,7 +86,7 @@ int vgpu_init_mm_support(struct gk20a *g)
85 return err; 86 return err;
86} 87}
87 88
88static u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm, 89u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm,
89 u64 map_offset, 90 u64 map_offset,
90 struct nvgpu_sgt *sgt, 91 struct nvgpu_sgt *sgt,
91 u64 buffer_offset, 92 u64 buffer_offset,
@@ -171,7 +172,7 @@ fail:
171 return 0; 172 return 0;
172} 173}
173 174
174static void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm, 175void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm,
175 u64 vaddr, 176 u64 vaddr,
176 u64 size, 177 u64 size,
177 int pgsz_idx, 178 int pgsz_idx,
@@ -274,7 +275,7 @@ u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, u64 size)
274 return addr; 275 return addr;
275} 276}
276 277
277static int vgpu_vm_bind_channel(struct gk20a_as_share *as_share, 278int vgpu_vm_bind_channel(struct gk20a_as_share *as_share,
278 struct channel_gk20a *ch) 279 struct channel_gk20a *ch)
279{ 280{
280 struct vm_gk20a *vm = as_share->vm; 281 struct vm_gk20a *vm = as_share->vm;
@@ -315,7 +316,7 @@ static void vgpu_cache_maint(u64 handle, u8 op)
315 WARN_ON(err || msg.ret); 316 WARN_ON(err || msg.ret);
316} 317}
317 318
318static int vgpu_mm_fb_flush(struct gk20a *g) 319int vgpu_mm_fb_flush(struct gk20a *g)
319{ 320{
320 321
321 gk20a_dbg_fn(""); 322 gk20a_dbg_fn("");
@@ -324,7 +325,7 @@ static int vgpu_mm_fb_flush(struct gk20a *g)
324 return 0; 325 return 0;
325} 326}
326 327
327static void vgpu_mm_l2_invalidate(struct gk20a *g) 328void vgpu_mm_l2_invalidate(struct gk20a *g)
328{ 329{
329 330
330 gk20a_dbg_fn(""); 331 gk20a_dbg_fn("");
@@ -332,7 +333,7 @@ static void vgpu_mm_l2_invalidate(struct gk20a *g)
332 vgpu_cache_maint(vgpu_get_handle(g), TEGRA_VGPU_L2_MAINT_INV); 333 vgpu_cache_maint(vgpu_get_handle(g), TEGRA_VGPU_L2_MAINT_INV);
333} 334}
334 335
335static void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate) 336void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate)
336{ 337{
337 u8 op; 338 u8 op;
338 339
@@ -346,14 +347,14 @@ static void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate)
346 vgpu_cache_maint(vgpu_get_handle(g), op); 347 vgpu_cache_maint(vgpu_get_handle(g), op);
347} 348}
348 349
349static void vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb) 350void vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb)
350{ 351{
351 gk20a_dbg_fn(""); 352 gk20a_dbg_fn("");
352 353
353 nvgpu_err(g, "call to RM server not supported"); 354 nvgpu_err(g, "call to RM server not supported");
354} 355}
355 356
356static void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) 357void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable)
357{ 358{
358 struct tegra_vgpu_cmd_msg msg; 359 struct tegra_vgpu_cmd_msg msg;
359 struct tegra_vgpu_mmu_debug_mode *p = &msg.params.mmu_debug_mode; 360 struct tegra_vgpu_mmu_debug_mode *p = &msg.params.mmu_debug_mode;
@@ -367,19 +368,3 @@ static void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable)
367 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); 368 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
368 WARN_ON(err || msg.ret); 369 WARN_ON(err || msg.ret);
369} 370}
370
371void vgpu_init_mm_ops(struct gpu_ops *gops)
372{
373 gops->fb.is_debug_mode_enabled = NULL;
374 gops->fb.set_debug_mode = vgpu_mm_mmu_set_debug_mode;
375 gops->mm.gmmu_map = vgpu_locked_gmmu_map;
376 gops->mm.gmmu_unmap = vgpu_locked_gmmu_unmap;
377 gops->mm.vm_bind_channel = vgpu_vm_bind_channel;
378 gops->mm.fb_flush = vgpu_mm_fb_flush;
379 gops->mm.l2_invalidate = vgpu_mm_l2_invalidate;
380 gops->mm.l2_flush = vgpu_mm_l2_flush;
381 gops->fb.tlb_invalidate = vgpu_mm_tlb_invalidate;
382 gops->mm.get_iommu_bit = gk20a_mm_get_iommu_bit;
383 gops->mm.gpu_phys_addr = gm20b_gpu_phys_addr;
384 gops->mm.init_mm_setup_hw = NULL;
385}
diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.h b/drivers/gpu/nvgpu/vgpu/mm_vgpu.h
new file mode 100644
index 00000000..ed66282c
--- /dev/null
+++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.h
@@ -0,0 +1,56 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef _MM_VGPU_H_
24#define _MM_VGPU_H_
25
26u64 vgpu_locked_gmmu_map(struct vm_gk20a *vm,
27 u64 map_offset,
28 struct nvgpu_sgt *sgt,
29 u64 buffer_offset,
30 u64 size,
31 int pgsz_idx,
32 u8 kind_v,
33 u32 ctag_offset,
34 u32 flags,
35 int rw_flag,
36 bool clear_ctags,
37 bool sparse,
38 bool priv,
39 struct vm_gk20a_mapping_batch *batch,
40 enum nvgpu_aperture aperture);
41void vgpu_locked_gmmu_unmap(struct vm_gk20a *vm,
42 u64 vaddr,
43 u64 size,
44 int pgsz_idx,
45 bool va_allocated,
46 int rw_flag,
47 bool sparse,
48 struct vm_gk20a_mapping_batch *batch);
49int vgpu_vm_bind_channel(struct gk20a_as_share *as_share,
50 struct channel_gk20a *ch);
51int vgpu_mm_fb_flush(struct gk20a *g);
52void vgpu_mm_l2_invalidate(struct gk20a *g);
53void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate);
54void vgpu_mm_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
55void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable);
56#endif
diff --git a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
index 39d78983..2be102e3 100644
--- a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c
@@ -27,10 +27,11 @@
27#include "gk20a/platform_gk20a.h" 27#include "gk20a/platform_gk20a.h"
28#include "gk20a/tsg_gk20a.h" 28#include "gk20a/tsg_gk20a.h"
29#include "vgpu.h" 29#include "vgpu.h"
30#include "fifo_vgpu.h"
30 31
31#include <nvgpu/bug.h> 32#include <nvgpu/bug.h>
32 33
33static int vgpu_tsg_open(struct tsg_gk20a *tsg) 34int vgpu_tsg_open(struct tsg_gk20a *tsg)
34{ 35{
35 struct tegra_vgpu_cmd_msg msg = {}; 36 struct tegra_vgpu_cmd_msg msg = {};
36 struct tegra_vgpu_tsg_open_params *p = 37 struct tegra_vgpu_tsg_open_params *p =
@@ -52,7 +53,7 @@ static int vgpu_tsg_open(struct tsg_gk20a *tsg)
52 return err; 53 return err;
53} 54}
54 55
55static int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, 56int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
56 struct channel_gk20a *ch) 57 struct channel_gk20a *ch)
57{ 58{
58 struct tegra_vgpu_cmd_msg msg = {}; 59 struct tegra_vgpu_cmd_msg msg = {};
@@ -82,7 +83,7 @@ static int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg,
82 return err; 83 return err;
83} 84}
84 85
85static int vgpu_tsg_unbind_channel(struct channel_gk20a *ch) 86int vgpu_tsg_unbind_channel(struct channel_gk20a *ch)
86{ 87{
87 struct tegra_vgpu_cmd_msg msg = {}; 88 struct tegra_vgpu_cmd_msg msg = {};
88 struct tegra_vgpu_tsg_bind_unbind_channel_params *p = 89 struct tegra_vgpu_tsg_bind_unbind_channel_params *p =
@@ -105,7 +106,7 @@ static int vgpu_tsg_unbind_channel(struct channel_gk20a *ch)
105 return err; 106 return err;
106} 107}
107 108
108static int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice) 109int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice)
109{ 110{
110 struct tegra_vgpu_cmd_msg msg = {0}; 111 struct tegra_vgpu_cmd_msg msg = {0};
111 struct tegra_vgpu_tsg_timeslice_params *p = 112 struct tegra_vgpu_tsg_timeslice_params *p =
@@ -126,11 +127,3 @@ static int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice)
126 127
127 return err; 128 return err;
128} 129}
129
130void vgpu_init_tsg_ops(struct gpu_ops *gops)
131{
132 gops->fifo.tsg_bind_channel = vgpu_tsg_bind_channel;
133 gops->fifo.tsg_unbind_channel = vgpu_tsg_unbind_channel;
134 gops->fifo.tsg_set_timeslice = vgpu_tsg_set_timeslice;
135 gops->fifo.tsg_open = vgpu_tsg_open;
136}
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c
index b63202c1..7949ff24 100644
--- a/drivers/gpu/nvgpu/vgpu/vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/vgpu.c
@@ -378,7 +378,7 @@ int vgpu_init_gpu_characteristics(struct gk20a *g)
378 return 0; 378 return 0;
379} 379}
380 380
381static int vgpu_read_ptimer(struct gk20a *g, u64 *value) 381int vgpu_read_ptimer(struct gk20a *g, u64 *value)
382{ 382{
383 struct tegra_vgpu_cmd_msg msg = {0}; 383 struct tegra_vgpu_cmd_msg msg = {0};
384 struct tegra_vgpu_read_ptimer_params *p = &msg.params.read_ptimer; 384 struct tegra_vgpu_read_ptimer_params *p = &msg.params.read_ptimer;
@@ -441,27 +441,6 @@ int vgpu_get_timestamps_zipper(struct gk20a *g,
441 return err; 441 return err;
442} 442}
443 443
444void vgpu_init_hal_common(struct gk20a *g)
445{
446 struct gpu_ops *gops = &g->ops;
447
448 vgpu_init_fifo_ops(gops);
449 vgpu_init_gr_ops(gops);
450 vgpu_init_ltc_ops(gops);
451 vgpu_init_mm_ops(gops);
452 vgpu_init_debug_ops(gops);
453 vgpu_init_dbg_session_ops(gops);
454 vgpu_init_fecs_trace_ops(gops);
455 vgpu_init_tsg_ops(gops);
456#if defined(CONFIG_GK20A_CYCLE_STATS)
457 vgpu_init_css_ops(gops);
458#endif
459 vgpu_init_ce2_ops(gops);
460 gops->chip_init_gpu_characteristics = vgpu_init_gpu_characteristics;
461 gops->bus.read_ptimer = vgpu_read_ptimer;
462 gops->bus.get_timestamps_zipper = vgpu_get_timestamps_zipper;
463}
464
465static int vgpu_init_hal(struct gk20a *g) 444static int vgpu_init_hal(struct gk20a *g)
466{ 445{
467 u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; 446 u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl;
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/vgpu/vgpu.h
index 7364a8d9..d5c49c0f 100644
--- a/drivers/gpu/nvgpu/vgpu/vgpu.h
+++ b/drivers/gpu/nvgpu/vgpu/vgpu.h
@@ -94,16 +94,7 @@ int vgpu_fifo_nonstall_isr(struct gk20a *g,
94 struct tegra_vgpu_fifo_nonstall_intr_info *info); 94 struct tegra_vgpu_fifo_nonstall_intr_info *info);
95int vgpu_ce2_nonstall_isr(struct gk20a *g, 95int vgpu_ce2_nonstall_isr(struct gk20a *g,
96 struct tegra_vgpu_ce2_nonstall_intr_info *info); 96 struct tegra_vgpu_ce2_nonstall_intr_info *info);
97void vgpu_init_fifo_ops(struct gpu_ops *gops); 97u32 vgpu_ce_get_num_pce(struct gk20a *g);
98void vgpu_init_gr_ops(struct gpu_ops *gops);
99void vgpu_init_ltc_ops(struct gpu_ops *gops);
100void vgpu_init_mm_ops(struct gpu_ops *gops);
101void vgpu_init_debug_ops(struct gpu_ops *gops);
102void vgpu_init_tsg_ops(struct gpu_ops *gops);
103#if defined(CONFIG_GK20A_CYCLE_STATS)
104void vgpu_init_css_ops(struct gpu_ops *gops);
105#endif
106void vgpu_init_ce2_ops(struct gpu_ops *gops);
107int vgpu_init_mm_support(struct gk20a *g); 98int vgpu_init_mm_support(struct gk20a *g);
108int vgpu_init_gr_support(struct gk20a *g); 99int vgpu_init_gr_support(struct gk20a *g);
109int vgpu_init_fifo_support(struct gk20a *g); 100int vgpu_init_fifo_support(struct gk20a *g);
@@ -112,15 +103,17 @@ int vgpu_get_attribute(u64 handle, u32 attrib, u32 *value);
112int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in, 103int vgpu_comm_sendrecv(struct tegra_vgpu_cmd_msg *msg, size_t size_in,
113 size_t size_out); 104 size_t size_out);
114 105
115void vgpu_init_hal_common(struct gk20a *g);
116int vgpu_gm20b_init_hal(struct gk20a *g); 106int vgpu_gm20b_init_hal(struct gk20a *g);
117int vgpu_gp10b_init_hal(struct gk20a *g); 107int vgpu_gp10b_init_hal(struct gk20a *g);
118 108
119void vgpu_init_dbg_session_ops(struct gpu_ops *gops);
120int vgpu_init_gpu_characteristics(struct gk20a *g); 109int vgpu_init_gpu_characteristics(struct gk20a *g);
121 110
122void vgpu_create_sysfs(struct device *dev); 111void vgpu_create_sysfs(struct device *dev);
123void vgpu_remove_sysfs(struct device *dev); 112void vgpu_remove_sysfs(struct device *dev);
113int vgpu_read_ptimer(struct gk20a *g, u64 *value);
114int vgpu_get_timestamps_zipper(struct gk20a *g,
115 u32 source_id, u32 count,
116 struct nvgpu_cpu_time_correlation_sample *samples);
124#else 117#else
125static inline int vgpu_pm_prepare_poweroff(struct device *dev) 118static inline int vgpu_pm_prepare_poweroff(struct device *dev)
126{ 119{
@@ -169,29 +162,6 @@ static inline int vgpu_fifo_isr(struct gk20a *g,
169{ 162{
170 return 0; 163 return 0;
171} 164}
172static inline void vgpu_init_fifo_ops(struct gpu_ops *gops)
173{
174}
175static inline void vgpu_init_gr_ops(struct gpu_ops *gops)
176{
177}
178static inline void vgpu_init_ltc_ops(struct gpu_ops *gops)
179{
180}
181static inline void vgpu_init_mm_ops(struct gpu_ops *gops)
182{
183}
184static inline void vgpu_init_debug_ops(struct gpu_ops *gops)
185{
186}
187#if defined(CONFIG_GK20A_CYCLE_STATS)
188static inline void vgpu_init_css_ops(struct gpu_ops *gops)
189{
190}
191#endif
192static inline void vgpu_init_ce2_ops(struct gpu_ops *gops)
193{
194}
195static inline int vgpu_init_mm_support(struct gk20a *g) 165static inline int vgpu_init_mm_support(struct gk20a *g)
196{ 166{
197 return -ENOSYS; 167 return -ENOSYS;
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-05 02:41:38 -0400