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authorPeter Daifuku <pdaifuku@nvidia.com>2017-10-06 19:27:14 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-10-13 18:20:18 -0400
commit57fb527a7e33384341fc18f1f918d5a8225057f5 (patch)
tree23bb49f879ac495834237c99564f0589d637f07e /drivers/gpu/nvgpu/vgpu/gp10b
parent3d343c9eeaa3415851d1c71b8815eb7dc2677b5a (diff)
gpu: nvgpu: vgpu: flatten out vgpu hal
Instead of calling the native HAL init function then adding multiple layers of modification for VGPU, flatten out the sequence so that all entry points are set statically and visible in a single file. JIRA ESRM-30 Change-Id: Ie424abb48bce5038874851d399baac5e4bb7d27c Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1574616 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/vgpu/gp10b')
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h30
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c21
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h19
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c624
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c15
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h19
6 files changed, 654 insertions, 74 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h
deleted file mode 100644
index 8dd016aa..00000000
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __VGPU_FIFO_GP10B_H__
24#define __VGPU_FIFO_GP10B_H__
25
26#include "gk20a/gk20a.h"
27
28void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops);
29
30#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
index ec2fcd8e..fa6109ad 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c
@@ -31,7 +31,7 @@
31 31
32#include <nvgpu/hw/gp10b/hw_gr_gp10b.h> 32#include <nvgpu/hw/gp10b/hw_gr_gp10b.h>
33 33
34static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, 34void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
35 struct gr_ctx_desc *gr_ctx) 35 struct gr_ctx_desc *gr_ctx)
36{ 36{
37 struct tegra_vgpu_cmd_msg msg = {0}; 37 struct tegra_vgpu_cmd_msg msg = {0};
@@ -59,7 +59,7 @@ static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
59 nvgpu_kfree(g, gr_ctx); 59 nvgpu_kfree(g, gr_ctx);
60} 60}
61 61
62static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, 62int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
63 struct gr_ctx_desc **__gr_ctx, 63 struct gr_ctx_desc **__gr_ctx,
64 struct vm_gk20a *vm, 64 struct vm_gk20a *vm,
65 u32 class, 65 u32 class,
@@ -115,7 +115,7 @@ fail:
115 return err; 115 return err;
116} 116}
117 117
118static int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g, 118int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
119 struct gr_ctx_desc *gr_ctx, 119 struct gr_ctx_desc *gr_ctx,
120 struct vm_gk20a *vm, u32 class, 120 struct vm_gk20a *vm, u32 class,
121 u32 graphics_preempt_mode, 121 u32 graphics_preempt_mode,
@@ -267,7 +267,7 @@ fail:
267 return err; 267 return err;
268} 268}
269 269
270static int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch, 270int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
271 u32 graphics_preempt_mode, 271 u32 graphics_preempt_mode,
272 u32 compute_preempt_mode) 272 u32 compute_preempt_mode)
273{ 273{
@@ -316,7 +316,7 @@ static int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
316 return err; 316 return err;
317} 317}
318 318
319static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) 319int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g)
320{ 320{
321 struct vgpu_priv_data *priv = vgpu_get_priv_data(g); 321 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
322 int err; 322 int err;
@@ -334,14 +334,3 @@ static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g)
334 334
335 return 0; 335 return 0;
336} 336}
337
338void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops)
339{
340 vgpu_gm20b_init_gr_ops(gops);
341 gops->gr.alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx;
342 gops->gr.free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx;
343 gops->gr.init_ctx_state = vgpu_gr_gp10b_init_ctx_state;
344 gops->gr.set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode;
345 gops->gr.set_ctxsw_preemption_mode =
346 vgpu_gr_gp10b_set_ctxsw_preemption_mode;
347}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h
index 9505749e..baf5a8e9 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,21 @@
25 25
26#include "gk20a/gk20a.h" 26#include "gk20a/gk20a.h"
27 27
28void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops); 28void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm,
29 struct gr_ctx_desc *gr_ctx);
30int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g,
31 struct gr_ctx_desc **__gr_ctx,
32 struct vm_gk20a *vm,
33 u32 class,
34 u32 flags);
35int vgpu_gr_gp10b_set_ctxsw_preemption_mode(struct gk20a *g,
36 struct gr_ctx_desc *gr_ctx,
37 struct vm_gk20a *vm, u32 class,
38 u32 graphics_preempt_mode,
39 u32 compute_preempt_mode);
40int vgpu_gr_gp10b_set_preemption_mode(struct channel_gk20a *ch,
41 u32 graphics_preempt_mode,
42 u32 compute_preempt_mode);
43int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g);
29 44
30#endif 45#endif
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 8a367f94..aae74e3f 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -21,24 +21,626 @@
21 */ 21 */
22 22
23#include "vgpu/vgpu.h" 23#include "vgpu/vgpu.h"
24#include "vgpu/fifo_vgpu.h"
25#include "vgpu/gr_vgpu.h"
26#include "vgpu/ltc_vgpu.h"
27#include "vgpu/mm_vgpu.h"
28#include "vgpu/dbg_vgpu.h"
29#include "vgpu/fecs_trace_vgpu.h"
30#include "vgpu/css_vgpu.h"
31#include "gp10b/gp10b.h"
24#include "gp10b/hal_gp10b.h" 32#include "gp10b/hal_gp10b.h"
33#include "vgpu/gm20b/vgpu_gr_gm20b.h"
25#include "vgpu_gr_gp10b.h" 34#include "vgpu_gr_gp10b.h"
26#include "vgpu_fifo_gp10b.h"
27#include "vgpu_mm_gp10b.h" 35#include "vgpu_mm_gp10b.h"
28 36
37#include "gk20a/bus_gk20a.h"
38#include "gk20a/pramin_gk20a.h"
39#include "gk20a/flcn_gk20a.h"
40#include "gk20a/mc_gk20a.h"
41#include "gk20a/fb_gk20a.h"
42
43#include "gp10b/mc_gp10b.h"
44#include "gp10b/ltc_gp10b.h"
45#include "gp10b/mm_gp10b.h"
46#include "gp10b/ce_gp10b.h"
47#include "gp10b/fb_gp10b.h"
48#include "gp10b/pmu_gp10b.h"
49#include "gp10b/gr_ctx_gp10b.h"
50#include "gp10b/fifo_gp10b.h"
51#include "gp10b/gp10b_gating_reglist.h"
52#include "gp10b/regops_gp10b.h"
53#include "gp10b/cde_gp10b.h"
54#include "gp10b/therm_gp10b.h"
55#include "gp10b/priv_ring_gp10b.h"
56
57#include "gm20b/ltc_gm20b.h"
58#include "gm20b/gr_gm20b.h"
59#include "gm20b/fifo_gm20b.h"
60#include "gm20b/acr_gm20b.h"
61#include "gm20b/pmu_gm20b.h"
62#include "gm20b/fb_gm20b.h"
63#include "gm20b/mm_gm20b.h"
64
65#include <nvgpu/enabled.h>
66
67#include <nvgpu/hw/gp10b/hw_fuse_gp10b.h>
68#include <nvgpu/hw/gp10b/hw_fifo_gp10b.h>
69#include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
70#include <nvgpu/hw/gp10b/hw_top_gp10b.h>
71#include <nvgpu/hw/gp10b/hw_pram_gp10b.h>
72#include <nvgpu/hw/gp10b/hw_pwr_gp10b.h>
73
74static const struct gpu_ops vgpu_gp10b_ops = {
75 .ltc = {
76 .determine_L2_size_bytes = vgpu_determine_L2_size_bytes,
77 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
78 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
79 .init_cbc = gm20b_ltc_init_cbc,
80 .init_fs_state = vgpu_ltc_init_fs_state,
81 .init_comptags = vgpu_ltc_init_comptags,
82 .cbc_ctrl = NULL,
83 .isr = gp10b_ltc_isr,
84 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
85 .flush = gm20b_flush_ltc,
86 .set_enabled = gp10b_ltc_set_enabled,
87 },
88 .ce2 = {
89 .isr_stall = gp10b_ce_isr,
90 .isr_nonstall = gp10b_ce_nonstall_isr,
91 .get_num_pce = vgpu_ce_get_num_pce,
92 },
93 .gr = {
94 .init_gpc_mmu = gr_gm20b_init_gpc_mmu,
95 .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
96 .cb_size_default = gr_gp10b_cb_size_default,
97 .calc_global_ctx_buffer_size =
98 gr_gp10b_calc_global_ctx_buffer_size,
99 .commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb,
100 .commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb,
101 .commit_global_cb_manager = gr_gp10b_commit_global_cb_manager,
102 .commit_global_pagepool = gr_gp10b_commit_global_pagepool,
103 .handle_sw_method = gr_gp10b_handle_sw_method,
104 .set_alpha_circular_buffer_size =
105 gr_gp10b_set_alpha_circular_buffer_size,
106 .set_circular_buffer_size = gr_gp10b_set_circular_buffer_size,
107 .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
108 .is_valid_class = gr_gp10b_is_valid_class,
109 .is_valid_gfx_class = gr_gp10b_is_valid_gfx_class,
110 .is_valid_compute_class = gr_gp10b_is_valid_compute_class,
111 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
112 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
113 .init_fs_state = vgpu_gm20b_init_fs_state,
114 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
115 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
116 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
117 .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask,
118 .get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask,
119 .free_channel_ctx = vgpu_gr_free_channel_ctx,
120 .alloc_obj_ctx = vgpu_gr_alloc_obj_ctx,
121 .bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull,
122 .get_zcull_info = vgpu_gr_get_zcull_info,
123 .is_tpc_addr = gr_gm20b_is_tpc_addr,
124 .get_tpc_num = gr_gm20b_get_tpc_num,
125 .detect_sm_arch = vgpu_gr_detect_sm_arch,
126 .add_zbc_color = gr_gp10b_add_zbc_color,
127 .add_zbc_depth = gr_gp10b_add_zbc_depth,
128 .zbc_set_table = vgpu_gr_add_zbc,
129 .zbc_query_table = vgpu_gr_query_zbc,
130 .pmu_save_zbc = gk20a_pmu_save_zbc,
131 .add_zbc = gr_gk20a_add_zbc,
132 .pagepool_default_size = gr_gp10b_pagepool_default_size,
133 .init_ctx_state = vgpu_gr_gp10b_init_ctx_state,
134 .alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx,
135 .free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx,
136 .update_ctxsw_preemption_mode =
137 gr_gp10b_update_ctxsw_preemption_mode,
138 .dump_gr_regs = NULL,
139 .update_pc_sampling = gr_gm20b_update_pc_sampling,
140 .get_fbp_en_mask = vgpu_gr_get_fbp_en_mask,
141 .get_max_ltc_per_fbp = vgpu_gr_get_max_ltc_per_fbp,
142 .get_max_lts_per_ltc = vgpu_gr_get_max_lts_per_ltc,
143 .get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask,
144 .get_max_fbps_count = vgpu_gr_get_max_fbps_count,
145 .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
146 .wait_empty = gr_gp10b_wait_empty,
147 .init_cyclestats = gr_gp10b_init_cyclestats,
148 .set_sm_debug_mode = vgpu_gr_set_sm_debug_mode,
149 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
150 .bpt_reg_info = gr_gm20b_bpt_reg_info,
151 .get_access_map = gr_gp10b_get_access_map,
152 .handle_fecs_error = gr_gp10b_handle_fecs_error,
153 .handle_sm_exception = gr_gp10b_handle_sm_exception,
154 .handle_tex_exception = gr_gp10b_handle_tex_exception,
155 .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions,
156 .enable_exceptions = gk20a_gr_enable_exceptions,
157 .get_lrf_tex_ltc_dram_override = get_ecc_override_val,
158 .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode,
159 .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode,
160 .record_sm_error_state = gm20b_gr_record_sm_error_state,
161 .update_sm_error_state = gm20b_gr_update_sm_error_state,
162 .clear_sm_error_state = vgpu_gr_clear_sm_error_state,
163 .suspend_contexts = vgpu_gr_suspend_contexts,
164 .resume_contexts = vgpu_gr_resume_contexts,
165 .get_preemption_mode_flags = gr_gp10b_get_preemption_mode_flags,
166 .fuse_override = gp10b_gr_fuse_override,
167 .init_sm_id_table = gr_gk20a_init_sm_id_table,
168 .load_smid_config = gr_gp10b_load_smid_config,
169 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
170 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
171 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
172 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
173 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
174 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
175 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
176 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
177 .commit_inst = vgpu_gr_commit_inst,
178 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
179 .write_pm_ptr = gr_gk20a_write_pm_ptr,
180 .init_elcg_mode = gr_gk20a_init_elcg_mode,
181 .load_tpc_mask = gr_gm20b_load_tpc_mask,
182 .inval_icache = gr_gk20a_inval_icache,
183 .trigger_suspend = gr_gk20a_trigger_suspend,
184 .wait_for_pause = gr_gk20a_wait_for_pause,
185 .resume_from_pause = gr_gk20a_resume_from_pause,
186 .clear_sm_errors = gr_gk20a_clear_sm_errors,
187 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
188 .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
189 .sm_debugger_attached = gk20a_gr_sm_debugger_attached,
190 .suspend_single_sm = gk20a_gr_suspend_single_sm,
191 .suspend_all_sms = gk20a_gr_suspend_all_sms,
192 .resume_single_sm = gk20a_gr_resume_single_sm,
193 .resume_all_sms = gk20a_gr_resume_all_sms,
194 .get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr,
195 .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr,
196 .get_sm_no_lock_down_hww_global_esr_mask =
197 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
198 .lock_down_sm = gk20a_gr_lock_down_sm,
199 .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down,
200 .clear_sm_hww = gm20b_gr_clear_sm_hww,
201 .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
202 .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
203 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
204 .set_boosted_ctx = NULL,
205 .set_preemption_mode = vgpu_gr_gp10b_set_preemption_mode,
206 .set_czf_bypass = gr_gp10b_set_czf_bypass,
207 .pre_process_sm_exception = gr_gp10b_pre_process_sm_exception,
208 .set_preemption_buffer_va = gr_gp10b_set_preemption_buffer_va,
209 .init_preemption_state = gr_gp10b_init_preemption_state,
210 .update_boosted_ctx = NULL,
211 .set_bes_crop_debug3 = gr_gp10b_set_bes_crop_debug3,
212 .create_gr_sysfs = gr_gp10b_create_sysfs,
213 .set_ctxsw_preemption_mode =
214 vgpu_gr_gp10b_set_ctxsw_preemption_mode,
215 .init_ctxsw_hdr_data = gr_gp10b_init_ctxsw_hdr_data,
216 },
217 .fb = {
218 .reset = fb_gk20a_reset,
219 .init_hw = gk20a_fb_init_hw,
220 .init_fs_state = fb_gm20b_init_fs_state,
221 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
222 .set_use_full_comp_tag_line =
223 gm20b_fb_set_use_full_comp_tag_line,
224 .compression_page_size = gp10b_fb_compression_page_size,
225 .compressible_page_size = gp10b_fb_compressible_page_size,
226 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
227 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
228 .read_wpr_info = gm20b_fb_read_wpr_info,
229 .is_debug_mode_enabled = NULL,
230 .set_debug_mode = vgpu_mm_mmu_set_debug_mode,
231 .tlb_invalidate = vgpu_mm_tlb_invalidate,
232 },
233 .clock_gating = {
234 .slcg_bus_load_gating_prod =
235 gp10b_slcg_bus_load_gating_prod,
236 .slcg_ce2_load_gating_prod =
237 gp10b_slcg_ce2_load_gating_prod,
238 .slcg_chiplet_load_gating_prod =
239 gp10b_slcg_chiplet_load_gating_prod,
240 .slcg_ctxsw_firmware_load_gating_prod =
241 gp10b_slcg_ctxsw_firmware_load_gating_prod,
242 .slcg_fb_load_gating_prod =
243 gp10b_slcg_fb_load_gating_prod,
244 .slcg_fifo_load_gating_prod =
245 gp10b_slcg_fifo_load_gating_prod,
246 .slcg_gr_load_gating_prod =
247 gr_gp10b_slcg_gr_load_gating_prod,
248 .slcg_ltc_load_gating_prod =
249 ltc_gp10b_slcg_ltc_load_gating_prod,
250 .slcg_perf_load_gating_prod =
251 gp10b_slcg_perf_load_gating_prod,
252 .slcg_priring_load_gating_prod =
253 gp10b_slcg_priring_load_gating_prod,
254 .slcg_pmu_load_gating_prod =
255 gp10b_slcg_pmu_load_gating_prod,
256 .slcg_therm_load_gating_prod =
257 gp10b_slcg_therm_load_gating_prod,
258 .slcg_xbar_load_gating_prod =
259 gp10b_slcg_xbar_load_gating_prod,
260 .blcg_bus_load_gating_prod =
261 gp10b_blcg_bus_load_gating_prod,
262 .blcg_ce_load_gating_prod =
263 gp10b_blcg_ce_load_gating_prod,
264 .blcg_ctxsw_firmware_load_gating_prod =
265 gp10b_blcg_ctxsw_firmware_load_gating_prod,
266 .blcg_fb_load_gating_prod =
267 gp10b_blcg_fb_load_gating_prod,
268 .blcg_fifo_load_gating_prod =
269 gp10b_blcg_fifo_load_gating_prod,
270 .blcg_gr_load_gating_prod =
271 gp10b_blcg_gr_load_gating_prod,
272 .blcg_ltc_load_gating_prod =
273 gp10b_blcg_ltc_load_gating_prod,
274 .blcg_pwr_csb_load_gating_prod =
275 gp10b_blcg_pwr_csb_load_gating_prod,
276 .blcg_pmu_load_gating_prod =
277 gp10b_blcg_pmu_load_gating_prod,
278 .blcg_xbar_load_gating_prod =
279 gp10b_blcg_xbar_load_gating_prod,
280 .pg_gr_load_gating_prod =
281 gr_gp10b_pg_gr_load_gating_prod,
282 },
283 .fifo = {
284 .init_fifo_setup_hw = vgpu_init_fifo_setup_hw,
285 .bind_channel = vgpu_channel_bind,
286 .unbind_channel = vgpu_channel_unbind,
287 .disable_channel = vgpu_channel_disable,
288 .enable_channel = vgpu_channel_enable,
289 .alloc_inst = vgpu_channel_alloc_inst,
290 .free_inst = vgpu_channel_free_inst,
291 .setup_ramfc = vgpu_channel_setup_ramfc,
292 .channel_set_priority = vgpu_channel_set_priority,
293 .channel_set_timeslice = vgpu_channel_set_timeslice,
294 .default_timeslice_us = vgpu_fifo_default_timeslice_us,
295 .setup_userd = gk20a_fifo_setup_userd,
296 .userd_gp_get = gk20a_fifo_userd_gp_get,
297 .userd_gp_put = gk20a_fifo_userd_gp_put,
298 .userd_pb_get = gk20a_fifo_userd_pb_get,
299 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
300 .preempt_channel = vgpu_fifo_preempt_channel,
301 .preempt_tsg = vgpu_fifo_preempt_tsg,
302 .enable_tsg = gk20a_enable_tsg,
303 .disable_tsg = gk20a_disable_tsg,
304 .tsg_verify_channel_status = NULL,
305 .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload,
306 .reschedule_runlist = NULL,
307 .update_runlist = vgpu_fifo_update_runlist,
308 .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
309 .get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info,
310 .wait_engine_idle = vgpu_fifo_wait_engine_idle,
311 .get_num_fifos = gm20b_fifo_get_num_fifos,
312 .get_pbdma_signature = gp10b_fifo_get_pbdma_signature,
313 .set_runlist_interleave = vgpu_fifo_set_runlist_interleave,
314 .tsg_set_timeslice = vgpu_tsg_set_timeslice,
315 .tsg_open = vgpu_tsg_open,
316 .force_reset_ch = vgpu_fifo_force_reset_ch,
317 .engine_enum_from_type = gp10b_fifo_engine_enum_from_type,
318 .device_info_data_parse = gp10b_device_info_data_parse,
319 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
320 .init_engine_info = vgpu_fifo_init_engine_info,
321 .runlist_entry_size = ram_rl_entry_size_v,
322 .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
323 .get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
324 .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
325 .dump_pbdma_status = gk20a_dump_pbdma_status,
326 .dump_eng_status = gk20a_dump_eng_status,
327 .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
328 .intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
329 .is_preempt_pending = gk20a_fifo_is_preempt_pending,
330 .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs,
331 .reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
332 .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
333 .handle_sched_error = gk20a_fifo_handle_sched_error,
334 .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
335 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
336 .tsg_bind_channel = vgpu_tsg_bind_channel,
337 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
338#ifdef CONFIG_TEGRA_GK20A_NVHOST
339 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
340 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
341 .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
342 .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
343 .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
344 .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
345#endif
346 .resetup_ramfc = NULL,
347 .device_info_fault_id = top_device_info_data_fault_id_enum_v,
348 },
349 .gr_ctx = {
350 .get_netlist_name = gr_gp10b_get_netlist_name,
351 .is_fw_defined = gr_gp10b_is_firmware_defined,
352 },
353#ifdef CONFIG_GK20A_CTXSW_TRACE
354 .fecs_trace = {
355 .alloc_user_buffer = vgpu_alloc_user_buffer,
356 .free_user_buffer = vgpu_free_user_buffer,
357 .mmap_user_buffer = vgpu_mmap_user_buffer,
358 .init = vgpu_fecs_trace_init,
359 .deinit = vgpu_fecs_trace_deinit,
360 .enable = vgpu_fecs_trace_enable,
361 .disable = vgpu_fecs_trace_disable,
362 .is_enabled = vgpu_fecs_trace_is_enabled,
363 .reset = NULL,
364 .flush = NULL,
365 .poll = vgpu_fecs_trace_poll,
366 .bind_channel = NULL,
367 .unbind_channel = NULL,
368 .max_entries = vgpu_fecs_trace_max_entries,
369 .set_filter = vgpu_fecs_trace_set_filter,
370 },
371#endif /* CONFIG_GK20A_CTXSW_TRACE */
372 .mm = {
373 /* FIXME: add support for sparse mappings */
374 .support_sparse = NULL,
375 .gmmu_map = vgpu_gp10b_locked_gmmu_map,
376 .gmmu_unmap = vgpu_locked_gmmu_unmap,
377 .vm_bind_channel = vgpu_vm_bind_channel,
378 .fb_flush = vgpu_mm_fb_flush,
379 .l2_invalidate = vgpu_mm_l2_invalidate,
380 .l2_flush = vgpu_mm_l2_flush,
381 .cbc_clean = gk20a_mm_cbc_clean,
382 .set_big_page_size = gm20b_mm_set_big_page_size,
383 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
384 .get_default_big_page_size = gp10b_mm_get_default_big_page_size,
385 .gpu_phys_addr = gm20b_gpu_phys_addr,
386 .get_iommu_bit = gk20a_mm_get_iommu_bit,
387 .get_mmu_levels = gp10b_mm_get_mmu_levels,
388 .init_pdb = gp10b_mm_init_pdb,
389 .init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw,
390 .is_bar1_supported = gm20b_mm_is_bar1_supported,
391 .init_inst_block = gk20a_init_inst_block,
392 .mmu_fault_pending = gk20a_fifo_mmu_fault_pending,
393 .init_bar2_vm = gb10b_init_bar2_vm,
394 .init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup,
395 .remove_bar2_vm = gp10b_remove_bar2_vm,
396 },
397 .pramin = {
398 .enter = gk20a_pramin_enter,
399 .exit = gk20a_pramin_exit,
400 .data032_r = pram_data032_r,
401 },
402 .therm = {
403 .init_therm_setup_hw = gp10b_init_therm_setup_hw,
404 .elcg_init_idle_filters = gp10b_elcg_init_idle_filters,
405 },
406 .pmu = {
407 .pmu_setup_elpg = gp10b_pmu_setup_elpg,
408 .pmu_get_queue_head = pwr_pmu_queue_head_r,
409 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
410 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
411 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
412 .pmu_queue_head = gk20a_pmu_queue_head,
413 .pmu_queue_tail = gk20a_pmu_queue_tail,
414 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
415 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
416 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
417 .pmu_mutex_release = gk20a_pmu_mutex_release,
418 .write_dmatrfbase = gp10b_write_dmatrfbase,
419 .pmu_elpg_statistics = gp10b_pmu_elpg_statistics,
420 .pmu_pg_init_param = gp10b_pg_gr_init,
421 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
422 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
423 .dump_secure_fuses = pmu_dump_security_fuses_gp10b,
424 .reset_engine = gk20a_pmu_engine_reset,
425 .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
426 },
427 .regops = {
428 .get_global_whitelist_ranges =
429 gp10b_get_global_whitelist_ranges,
430 .get_global_whitelist_ranges_count =
431 gp10b_get_global_whitelist_ranges_count,
432 .get_context_whitelist_ranges =
433 gp10b_get_context_whitelist_ranges,
434 .get_context_whitelist_ranges_count =
435 gp10b_get_context_whitelist_ranges_count,
436 .get_runcontrol_whitelist = gp10b_get_runcontrol_whitelist,
437 .get_runcontrol_whitelist_count =
438 gp10b_get_runcontrol_whitelist_count,
439 .get_runcontrol_whitelist_ranges =
440 gp10b_get_runcontrol_whitelist_ranges,
441 .get_runcontrol_whitelist_ranges_count =
442 gp10b_get_runcontrol_whitelist_ranges_count,
443 .get_qctl_whitelist = gp10b_get_qctl_whitelist,
444 .get_qctl_whitelist_count = gp10b_get_qctl_whitelist_count,
445 .get_qctl_whitelist_ranges = gp10b_get_qctl_whitelist_ranges,
446 .get_qctl_whitelist_ranges_count =
447 gp10b_get_qctl_whitelist_ranges_count,
448 .apply_smpc_war = gp10b_apply_smpc_war,
449 },
450 .mc = {
451 .intr_enable = mc_gp10b_intr_enable,
452 .intr_unit_config = mc_gp10b_intr_unit_config,
453 .isr_stall = mc_gp10b_isr_stall,
454 .intr_stall = mc_gp10b_intr_stall,
455 .intr_stall_pause = mc_gp10b_intr_stall_pause,
456 .intr_stall_resume = mc_gp10b_intr_stall_resume,
457 .intr_nonstall = mc_gp10b_intr_nonstall,
458 .intr_nonstall_pause = mc_gp10b_intr_nonstall_pause,
459 .intr_nonstall_resume = mc_gp10b_intr_nonstall_resume,
460 .enable = gk20a_mc_enable,
461 .disable = gk20a_mc_disable,
462 .reset = gk20a_mc_reset,
463 .boot_0 = gk20a_mc_boot_0,
464 .is_intr1_pending = mc_gp10b_is_intr1_pending,
465 },
466 .debug = {
467 .show_dump = NULL,
468 },
469 .dbg_session_ops = {
470 .exec_reg_ops = vgpu_exec_regops,
471 .dbg_set_powergate = vgpu_dbg_set_powergate,
472 .check_and_set_global_reservation =
473 vgpu_check_and_set_global_reservation,
474 .check_and_set_context_reservation =
475 vgpu_check_and_set_context_reservation,
476 .release_profiler_reservation =
477 vgpu_release_profiler_reservation,
478 .perfbuffer_enable = vgpu_perfbuffer_enable,
479 .perfbuffer_disable = vgpu_perfbuffer_disable,
480 },
481 .cde = {
482 .get_program_numbers = gp10b_cde_get_program_numbers,
483 .need_scatter_buffer = gp10b_need_scatter_buffer,
484 .populate_scatter_buffer = gp10b_populate_scatter_buffer,
485 },
486 .bus = {
487 .init_hw = gk20a_bus_init_hw,
488 .isr = gk20a_bus_isr,
489 .read_ptimer = vgpu_read_ptimer,
490 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
491 .bar1_bind = gk20a_bus_bar1_bind,
492 },
493#if defined(CONFIG_GK20A_CYCLE_STATS)
494 .css = {
495 .enable_snapshot = vgpu_css_enable_snapshot_buffer,
496 .disable_snapshot = vgpu_css_release_snapshot_buffer,
497 .check_data_available = vgpu_css_flush_snapshots,
498 .detach_snapshot = vgpu_css_detach,
499 .set_handled_snapshots = NULL,
500 .allocate_perfmon_ids = NULL,
501 .release_perfmon_ids = NULL,
502 },
503#endif
504 .falcon = {
505 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
506 },
507 .priv_ring = {
508 .isr = gp10b_priv_ring_isr,
509 },
510 .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics,
511 .get_litter_value = gp10b_get_litter_value,
512};
513
29int vgpu_gp10b_init_hal(struct gk20a *g) 514int vgpu_gp10b_init_hal(struct gk20a *g)
30{ 515{
31 int err; 516 struct gpu_ops *gops = &g->ops;
517 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
518 u32 val;
519
520 gops->ltc = vgpu_gp10b_ops.ltc;
521 gops->ce2 = vgpu_gp10b_ops.ce2;
522 gops->gr = vgpu_gp10b_ops.gr;
523 gops->fb = vgpu_gp10b_ops.fb;
524 gops->clock_gating = vgpu_gp10b_ops.clock_gating;
525 gops->fifo = vgpu_gp10b_ops.fifo;
526 gops->gr_ctx = vgpu_gp10b_ops.gr_ctx;
527 gops->fecs_trace = vgpu_gp10b_ops.fecs_trace;
528 gops->mm = vgpu_gp10b_ops.mm;
529 gops->pramin = vgpu_gp10b_ops.pramin;
530 gops->therm = vgpu_gp10b_ops.therm;
531 gops->pmu = vgpu_gp10b_ops.pmu;
532 gops->regops = vgpu_gp10b_ops.regops;
533 gops->mc = vgpu_gp10b_ops.mc;
534 gops->debug = vgpu_gp10b_ops.debug;
535 gops->dbg_session_ops = vgpu_gp10b_ops.dbg_session_ops;
536 gops->cde = vgpu_gp10b_ops.cde;
537 gops->bus = vgpu_gp10b_ops.bus;
538#if defined(CONFIG_GK20A_CYCLE_STATS)
539 gops->css = vgpu_gp10b_ops.css;
540#endif
541 gops->falcon = vgpu_gp10b_ops.falcon;
542
543 gops->priv_ring = vgpu_gp10b_ops.priv_ring;
544
545 /* Lone Functions */
546 gops->chip_init_gpu_characteristics =
547 vgpu_gp10b_ops.chip_init_gpu_characteristics;
548 gops->get_litter_value = vgpu_gp10b_ops.get_litter_value;
549
550 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
551 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
552
553#ifdef CONFIG_TEGRA_ACR
554 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
555 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
556 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
557 } else if (g->is_virtual) {
558 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
559 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
560 } else {
561 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
562 if (val) {
563 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
564 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
565 } else {
566 gk20a_dbg_info("priv security is disabled in HW");
567 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
568 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
569 }
570 }
571#else
572 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
573 gk20a_dbg_info("running simulator with PRIV security disabled");
574 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
575 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
576 } else {
577 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
578 if (val) {
579 gk20a_dbg_info("priv security is not supported but enabled");
580 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
581 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true);
582 return -EPERM;
583 } else {
584 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
585 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
586 }
587 }
588#endif
589
590 /* priv security dependent ops */
591 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
592 /* Add in ops from gm20b acr */
593 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported,
594 gops->pmu.prepare_ucode = prepare_ucode_blob,
595 gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn,
596 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap,
597 gops->pmu.is_priv_load = gm20b_is_priv_load,
598 gops->pmu.get_wpr = gm20b_wpr_info,
599 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space,
600 gops->pmu.pmu_populate_loader_cfg =
601 gm20b_pmu_populate_loader_cfg,
602 gops->pmu.flcn_populate_bl_dmem_desc =
603 gm20b_flcn_populate_bl_dmem_desc,
604 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt,
605 gops->pmu.falcon_clear_halt_interrupt_status =
606 clear_halt_interrupt_status,
607 gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1,
608
609 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
610 gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode;
611 gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap;
612 gops->pmu.is_priv_load = gp10b_is_priv_load;
613
614 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
615 } else {
616 /* Inherit from gk20a */
617 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported,
618 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob,
619 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1,
620 gops->pmu.pmu_nsbootstrap = pmu_bootstrap,
621
622 gops->pmu.load_lsfalcon_ucode = NULL;
623 gops->pmu.init_wpr_region = NULL;
624 gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1;
625
626 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
627 }
628
629 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
630 g->pmu_lsf_pmu_wpr_init_done = 0;
631 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
632
633 gp10b_init_uncompressed_kind_map();
634 gp10b_init_kind_attr();
32 635
33 gk20a_dbg_fn(""); 636 g->name = "gp10b";
34 637
35 err = gp10b_init_hal(g); 638 c->twod_class = FERMI_TWOD_A;
36 if (err) 639 c->threed_class = PASCAL_A;
37 return err; 640 c->compute_class = PASCAL_COMPUTE_A;
641 c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A;
642 c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
643 c->dma_copy_class = PASCAL_DMA_COPY_A;
38 644
39 vgpu_init_hal_common(g);
40 vgpu_gp10b_init_gr_ops(&g->ops);
41 vgpu_gp10b_init_fifo_ops(&g->ops);
42 vgpu_gp10b_init_mm_ops(&g->ops);
43 return 0; 645 return 0;
44} 646}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c
index cb7008ba..f063961f 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c
@@ -28,7 +28,7 @@
28 28
29#include <nvgpu/bug.h> 29#include <nvgpu/bug.h>
30 30
31static int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g) 31int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g)
32{ 32{
33 g->mm.bypass_smmu = true; 33 g->mm.bypass_smmu = true;
34 g->mm.disable_bigpage = true; 34 g->mm.disable_bigpage = true;
@@ -47,7 +47,7 @@ static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc,
47 return 0; 47 return 0;
48} 48}
49 49
50static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, 50u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm,
51 u64 map_offset, 51 u64 map_offset,
52 struct nvgpu_sgt *sgt, 52 struct nvgpu_sgt *sgt,
53 u64 buffer_offset, 53 u64 buffer_offset,
@@ -200,14 +200,3 @@ fail:
200 200
201 return 0; 201 return 0;
202} 202}
203
204void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops)
205{
206 gk20a_dbg_fn("");
207
208 gops->mm.gmmu_map = vgpu_gp10b_locked_gmmu_map;
209 gops->mm.init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw;
210
211 /* FIXME: add support for sparse mappings */
212 gops->mm.support_sparse = NULL;
213}
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h
index a8f0b7bc..fd6760ff 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,21 @@
25 25
26#include "gk20a/gk20a.h" 26#include "gk20a/gk20a.h"
27 27
28void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops); 28u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm,
29 u64 map_offset,
30 struct nvgpu_sgt *sgt,
31 u64 buffer_offset,
32 u64 size,
33 int pgsz_idx,
34 u8 kind_v,
35 u32 ctag_offset,
36 u32 flags,
37 int rw_flag,
38 bool clear_ctags,
39 bool sparse,
40 bool priv,
41 struct vm_gk20a_mapping_batch *batch,
42 enum nvgpu_aperture aperture);
43int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g);
29 44
30#endif 45#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-04 01:13:49 -0400