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-rw-r--r--include/nvgpu/vgpu/tegra_vgpu.h817
-rw-r--r--include/nvgpu/vgpu/vgpu.h110
-rw-r--r--include/nvgpu/vgpu/vgpu_ivc.h45
-rw-r--r--include/nvgpu/vgpu/vgpu_ivm.h37
-rw-r--r--include/nvgpu/vgpu/vm.h31
5 files changed, 1040 insertions, 0 deletions
diff --git a/include/nvgpu/vgpu/tegra_vgpu.h b/include/nvgpu/vgpu/tegra_vgpu.h
new file mode 100644
index 0000000..e33dce9
--- /dev/null
+++ b/include/nvgpu/vgpu/tegra_vgpu.h
@@ -0,0 +1,817 @@
1/*
2 * Tegra GPU Virtualization Interfaces to Server
3 *
4 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef TEGRA_VGPU_H
26#define TEGRA_VGPU_H
27
28#include <nvgpu/types.h>
29#include <nvgpu/ecc.h> /* For NVGPU_ECC_STAT_NAME_MAX_SIZE */
30
31enum {
32 TEGRA_VGPU_MODULE_GPU = 0,
33};
34
35enum {
36 /* Needs to follow last entry in TEGRA_VHOST_QUEUE_* list,
37 * in tegra_vhost.h
38 */
39 TEGRA_VGPU_QUEUE_CMD = 3,
40 TEGRA_VGPU_QUEUE_INTR
41};
42
43enum {
44 TEGRA_VGPU_CMD_CONNECT = 0,
45 TEGRA_VGPU_CMD_DISCONNECT = 1,
46 TEGRA_VGPU_CMD_ABORT = 2,
47 TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX = 3,
48 TEGRA_VGPU_CMD_CHANNEL_FREE_HWCTX = 4,
49 TEGRA_VGPU_CMD_GET_ATTRIBUTE = 5,
50 TEGRA_VGPU_CMD_MAP_BAR1 = 6,
51 TEGRA_VGPU_CMD_AS_ALLOC_SHARE = 7,
52 TEGRA_VGPU_CMD_AS_BIND_SHARE = 8,
53 TEGRA_VGPU_CMD_AS_FREE_SHARE = 9,
54 TEGRA_VGPU_CMD_AS_UNMAP = 11,
55 TEGRA_VGPU_CMD_CHANNEL_BIND = 13,
56 TEGRA_VGPU_CMD_CHANNEL_UNBIND = 14,
57 TEGRA_VGPU_CMD_CHANNEL_DISABLE = 15,
58 TEGRA_VGPU_CMD_CHANNEL_PREEMPT = 16,
59 TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC = 17,
60 TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX = 20,
61 TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX = 21,
62 TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX = 22,
63 TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX = 23,
64 TEGRA_VGPU_CMD_CHANNEL_UNMAP_GR_GLOBAL_CTX = 24,
65 TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_GLOBAL_CTX = 25,
66 TEGRA_VGPU_CMD_CHANNEL_LOAD_GR_GOLDEN_CTX = 26,
67 TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL = 27,
68 TEGRA_VGPU_CMD_CACHE_MAINT = 28,
69 TEGRA_VGPU_CMD_SUBMIT_RUNLIST = 29,
70 TEGRA_VGPU_CMD_GET_ZCULL_INFO = 30,
71 TEGRA_VGPU_CMD_ZBC_SET_TABLE = 31,
72 TEGRA_VGPU_CMD_ZBC_QUERY_TABLE = 32,
73 TEGRA_VGPU_CMD_AS_MAP_EX = 33,
74 TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS = 34,
75 TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE = 35,
76 TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE = 36,
77 TEGRA_VGPU_CMD_REG_OPS = 37,
78 TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY = 38,
79 TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE = 39,
80 TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE = 40,
81 TEGRA_VGPU_CMD_FECS_TRACE_ENABLE = 41,
82 TEGRA_VGPU_CMD_FECS_TRACE_DISABLE = 42,
83 TEGRA_VGPU_CMD_FECS_TRACE_POLL = 43,
84 TEGRA_VGPU_CMD_FECS_TRACE_SET_FILTER = 44,
85 TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE = 45,
86 TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE = 46,
87 TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX = 47,
88 TEGRA_VGPU_CMD_GR_CTX_ALLOC = 48,
89 TEGRA_VGPU_CMD_GR_CTX_FREE = 49,
90 TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX = 50,
91 TEGRA_VGPU_CMD_TSG_BIND_GR_CTX = 51,
92 TEGRA_VGPU_CMD_TSG_BIND_CHANNEL = 52,
93 TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL = 53,
94 TEGRA_VGPU_CMD_TSG_PREEMPT = 54,
95 TEGRA_VGPU_CMD_TSG_SET_TIMESLICE = 55,
96 TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE = 56,
97 TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET = 57,
98 TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58,
99 TEGRA_VGPU_CMD_READ_PTIMER = 59,
100 TEGRA_VGPU_CMD_SET_POWERGATE = 60,
101 TEGRA_VGPU_CMD_SET_GPU_CLK_RATE = 61,
102 TEGRA_VGPU_CMD_GET_CONSTANTS = 62,
103 TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT = 63,
104 TEGRA_VGPU_CMD_TSG_OPEN = 64,
105 TEGRA_VGPU_CMD_GET_GPU_LOAD = 65,
106 TEGRA_VGPU_CMD_SUSPEND_CONTEXTS = 66,
107 TEGRA_VGPU_CMD_RESUME_CONTEXTS = 67,
108 TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE = 68,
109 TEGRA_VGPU_CMD_GET_GPU_CLK_RATE = 69,
110 TEGRA_VGPU_CMD_GET_GPU_FREQ_TABLE = 70,
111 TEGRA_VGPU_CMD_CAP_GPU_CLK_RATE = 71,
112 TEGRA_VGPU_CMD_PROF_MGT = 72,
113 TEGRA_VGPU_CMD_PERFBUF_MGT = 73,
114 TEGRA_VGPU_CMD_GET_TIMESTAMPS_ZIPPER = 74,
115 TEGRA_VGPU_CMD_TSG_RELEASE = 75,
116 TEGRA_VGPU_CMD_GET_VSMS_MAPPING = 76,
117 TEGRA_VGPU_CMD_ALLOC_CTX_HEADER = 77,
118 TEGRA_VGPU_CMD_FREE_CTX_HEADER = 78,
119 TEGRA_VGPU_CMD_MAP_SYNCPT = 79,
120 TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX = 80,
121 TEGRA_VGPU_CMD_UPDATE_PC_SAMPLING = 81,
122 TEGRA_VGPU_CMD_SUSPEND = 82,
123 TEGRA_VGPU_CMD_RESUME = 83,
124 TEGRA_VGPU_CMD_GET_ECC_INFO = 84,
125 TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85,
126 TEGRA_VGPU_CMD_FB_SET_MMU_DEBUG_MODE = 88,
127 TEGRA_VGPU_CMD_GR_SET_MMU_DEBUG_MODE = 89,
128};
129
130struct tegra_vgpu_connect_params {
131 u32 module;
132 u64 handle;
133};
134
135struct tegra_vgpu_channel_hwctx_params {
136 u32 id;
137 u64 pid;
138 u64 handle;
139};
140
141struct tegra_vgpu_attrib_params {
142 u32 attrib;
143 u32 value;
144};
145
146struct tegra_vgpu_as_share_params {
147 u64 size;
148 u64 handle;
149 u32 big_page_size;
150};
151
152struct tegra_vgpu_as_bind_share_params {
153 u64 as_handle;
154 u64 chan_handle;
155};
156
157enum {
158 TEGRA_VGPU_MAP_PROT_NONE = 0,
159 TEGRA_VGPU_MAP_PROT_READ_ONLY,
160 TEGRA_VGPU_MAP_PROT_WRITE_ONLY
161};
162
163struct tegra_vgpu_as_map_params {
164 u64 handle;
165 u64 addr;
166 u64 gpu_va;
167 u64 size;
168 u8 pgsz_idx;
169 u8 iova;
170 u8 kind;
171 u8 cacheable;
172 u8 clear_ctags;
173 u8 prot;
174 u32 ctag_offset;
175};
176
177#define TEGRA_VGPU_MAP_CACHEABLE (1 << 0)
178#define TEGRA_VGPU_MAP_IO_COHERENT (1 << 1)
179#define TEGRA_VGPU_MAP_L3_ALLOC (1 << 2)
180#define TEGRA_VGPU_MAP_PLATFORM_ATOMIC (1 << 3)
181
182struct tegra_vgpu_as_map_ex_params {
183 u64 handle;
184 u64 gpu_va;
185 u64 size;
186 u32 mem_desc_count;
187 u8 pgsz_idx;
188 u8 iova;
189 u8 kind;
190 u32 flags;
191 u8 clear_ctags;
192 u8 prot;
193 u32 ctag_offset;
194};
195
196struct tegra_vgpu_mem_desc {
197 u64 addr;
198 u64 length;
199};
200
201struct tegra_vgpu_channel_config_params {
202 u64 handle;
203};
204
205struct tegra_vgpu_ramfc_params {
206 u64 handle;
207 u64 gpfifo_va;
208 u32 num_entries;
209 u64 userd_addr;
210 u8 iova;
211};
212
213struct tegra_vgpu_ch_ctx_params {
214 u64 handle;
215 u64 gr_ctx_va;