Include nvgpu headers

These are needed to build on NVIDIA's Jetson boards for the time
being. Only a couple structs are required, so it should be fairly
easy to remove this dependency at some point in the future.

5 files changed, 1040 insertions, 0 deletions

diff --git a/include/nvgpu/vgpu/tegra_vgpu.h b/include/nvgpu/vgpu/tegra_vgpu.h
new file mode 100644
index 0000000..e33dce9
--- /dev/null
+++ b/include/nvgpu/vgpu/tegra_vgpu.h
@@ -0,0 +1,817 @@
+/*
+ * Tegra GPU Virtualization Interfaces to Server
+ *
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef TEGRA_VGPU_H
+#define TEGRA_VGPU_H
+
+#include <nvgpu/types.h>
+#include <nvgpu/ecc.h>  /* For NVGPU_ECC_STAT_NAME_MAX_SIZE */
+
+enum {
+        TEGRA_VGPU_MODULE_GPU = 0,
+};
+
+enum {
+        /* Needs to follow last entry in TEGRA_VHOST_QUEUE_* list,
+         * in tegra_vhost.h
+         */
+        TEGRA_VGPU_QUEUE_CMD = 3,
+        TEGRA_VGPU_QUEUE_INTR
+};
+
+enum {
+        TEGRA_VGPU_CMD_CONNECT = 0,
+        TEGRA_VGPU_CMD_DISCONNECT = 1,
+        TEGRA_VGPU_CMD_ABORT = 2,
+        TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX = 3,
+        TEGRA_VGPU_CMD_CHANNEL_FREE_HWCTX = 4,
+        TEGRA_VGPU_CMD_GET_ATTRIBUTE = 5,
+        TEGRA_VGPU_CMD_MAP_BAR1 = 6,
+        TEGRA_VGPU_CMD_AS_ALLOC_SHARE = 7,
+        TEGRA_VGPU_CMD_AS_BIND_SHARE = 8,
+        TEGRA_VGPU_CMD_AS_FREE_SHARE = 9,
+        TEGRA_VGPU_CMD_AS_UNMAP = 11,
+        TEGRA_VGPU_CMD_CHANNEL_BIND = 13,
+        TEGRA_VGPU_CMD_CHANNEL_UNBIND = 14,
+        TEGRA_VGPU_CMD_CHANNEL_DISABLE = 15,
+        TEGRA_VGPU_CMD_CHANNEL_PREEMPT = 16,
+        TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC = 17,
+        TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX = 20,
+        TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX = 21,
+        TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX = 22,
+        TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX = 23,
+        TEGRA_VGPU_CMD_CHANNEL_UNMAP_GR_GLOBAL_CTX = 24,
+        TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_GLOBAL_CTX = 25,
+        TEGRA_VGPU_CMD_CHANNEL_LOAD_GR_GOLDEN_CTX = 26,
+        TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL = 27,
+        TEGRA_VGPU_CMD_CACHE_MAINT = 28,
+        TEGRA_VGPU_CMD_SUBMIT_RUNLIST = 29,
+        TEGRA_VGPU_CMD_GET_ZCULL_INFO = 30,
+        TEGRA_VGPU_CMD_ZBC_SET_TABLE = 31,
+        TEGRA_VGPU_CMD_ZBC_QUERY_TABLE = 32,
+        TEGRA_VGPU_CMD_AS_MAP_EX = 33,
+        TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS = 34,
+        TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE = 35,
+        TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE = 36,
+        TEGRA_VGPU_CMD_REG_OPS = 37,
+        TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY = 38,
+        TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE = 39,
+        TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE = 40,
+        TEGRA_VGPU_CMD_FECS_TRACE_ENABLE = 41,
+        TEGRA_VGPU_CMD_FECS_TRACE_DISABLE = 42,
+        TEGRA_VGPU_CMD_FECS_TRACE_POLL = 43,
+        TEGRA_VGPU_CMD_FECS_TRACE_SET_FILTER = 44,
+        TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE = 45,
+        TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE = 46,
+        TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX = 47,
+        TEGRA_VGPU_CMD_GR_CTX_ALLOC = 48,
+        TEGRA_VGPU_CMD_GR_CTX_FREE = 49,
+        TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX = 50,
+        TEGRA_VGPU_CMD_TSG_BIND_GR_CTX = 51,
+        TEGRA_VGPU_CMD_TSG_BIND_CHANNEL = 52,
+        TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL = 53,
+        TEGRA_VGPU_CMD_TSG_PREEMPT = 54,
+        TEGRA_VGPU_CMD_TSG_SET_TIMESLICE = 55,
+        TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE = 56,
+        TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET = 57,
+        TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58,
+        TEGRA_VGPU_CMD_READ_PTIMER = 59,
+        TEGRA_VGPU_CMD_SET_POWERGATE = 60,
+        TEGRA_VGPU_CMD_SET_GPU_CLK_RATE = 61,
+        TEGRA_VGPU_CMD_GET_CONSTANTS = 62,
+        TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT = 63,
+        TEGRA_VGPU_CMD_TSG_OPEN = 64,
+        TEGRA_VGPU_CMD_GET_GPU_LOAD = 65,
+        TEGRA_VGPU_CMD_SUSPEND_CONTEXTS = 66,
+        TEGRA_VGPU_CMD_RESUME_CONTEXTS = 67,
+        TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE = 68,
+        TEGRA_VGPU_CMD_GET_GPU_CLK_RATE = 69,
+        TEGRA_VGPU_CMD_GET_GPU_FREQ_TABLE = 70,
+        TEGRA_VGPU_CMD_CAP_GPU_CLK_RATE = 71,
+        TEGRA_VGPU_CMD_PROF_MGT = 72,
+        TEGRA_VGPU_CMD_PERFBUF_MGT = 73,
+        TEGRA_VGPU_CMD_GET_TIMESTAMPS_ZIPPER = 74,
+        TEGRA_VGPU_CMD_TSG_RELEASE = 75,
+        TEGRA_VGPU_CMD_GET_VSMS_MAPPING = 76,
+        TEGRA_VGPU_CMD_ALLOC_CTX_HEADER = 77,
+        TEGRA_VGPU_CMD_FREE_CTX_HEADER = 78,
+        TEGRA_VGPU_CMD_MAP_SYNCPT = 79,
+        TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX = 80,
+        TEGRA_VGPU_CMD_UPDATE_PC_SAMPLING = 81,
+        TEGRA_VGPU_CMD_SUSPEND = 82,
+        TEGRA_VGPU_CMD_RESUME = 83,
+        TEGRA_VGPU_CMD_GET_ECC_INFO = 84,
+        TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85,
+        TEGRA_VGPU_CMD_FB_SET_MMU_DEBUG_MODE = 88,
+        TEGRA_VGPU_CMD_GR_SET_MMU_DEBUG_MODE = 89,
+};
+
+struct tegra_vgpu_connect_params {
+        u32 module;
+        u64 handle;
+};
+
+struct tegra_vgpu_channel_hwctx_params {
+        u32 id;
+        u64 pid;
+        u64 handle;
+};
+
+struct tegra_vgpu_attrib_params {
+        u32 attrib;
+        u32 value;
+};
+
+struct tegra_vgpu_as_share_params {
+        u64 size;
+        u64 handle;
+        u32 big_page_size;
+};
+
+struct tegra_vgpu_as_bind_share_params {
+        u64 as_handle;
+        u64 chan_handle;
+};
+
+enum {
+        TEGRA_VGPU_MAP_PROT_NONE = 0,
+        TEGRA_VGPU_MAP_PROT_READ_ONLY,
+        TEGRA_VGPU_MAP_PROT_WRITE_ONLY
+};
+
+struct tegra_vgpu_as_map_params {
+        u64 handle;
+        u64 addr;
+        u64 gpu_va;
+        u64 size;
+        u8 pgsz_idx;
+        u8 iova;
+        u8 kind;
+        u8 cacheable;
+        u8 clear_ctags;
+        u8 prot;
+        u32 ctag_offset;
+};
+
+#define TEGRA_VGPU_MAP_CACHEABLE        (1 << 0)
+#define TEGRA_VGPU_MAP_IO_COHERENT      (1 << 1)
+#define TEGRA_VGPU_MAP_L3_ALLOC         (1 << 2)
+#define TEGRA_VGPU_MAP_PLATFORM_ATOMIC  (1 << 3)
+
+struct tegra_vgpu_as_map_ex_params {
+        u64 handle;
+        u64 gpu_va;
+        u64 size;
+        u32 mem_desc_count;
+        u8 pgsz_idx;
+        u8 iova;
+        u8 kind;
+        u32 flags;
+        u8 clear_ctags;
+        u8 prot;
+        u32 ctag_offset;
+};
+
+struct tegra_vgpu_mem_desc {
+        u64 addr;
+        u64 length;
+};
+
+struct tegra_vgpu_channel_config_params {
+        u64 handle;
+};
+
+struct tegra_vgpu_ramfc_params {
+        u64 handle;
+        u64 gpfifo_va;
+        u32 num_entries;
+        u64 userd_addr;