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-rw-r--r--include/nvgpu/acr/acr_flcnbl.h144
-rw-r--r--include/nvgpu/acr/acr_lsfm.h328
-rw-r--r--include/nvgpu/acr/acr_objflcn.h91
-rw-r--r--include/nvgpu/acr/acr_objlsfm.h97
-rw-r--r--include/nvgpu/acr/nvgpu_acr.h188
5 files changed, 848 insertions, 0 deletions
diff --git a/include/nvgpu/acr/acr_flcnbl.h b/include/nvgpu/acr/acr_flcnbl.h
new file mode 100644
index 0000000..ad697b2
--- /dev/null
+++ b/include/nvgpu/acr/acr_flcnbl.h
@@ -0,0 +1,144 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_ACR_FLCNBL_H
23#define NVGPU_ACR_FLCNBL_H
24
25#include <nvgpu/flcnif_cmn.h>
26
27#ifndef NVGPU_ACR_H
28#warning "acr_flcnbl.h not included from nvgpu_acr.h!" \
29 "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
30#endif
31
32/*
33 * Structure used by the boot-loader to load the rest of the code. This has
34 * to be filled by NVGPU and copied into DMEM at offset provided in the
35 * hsflcn_bl_desc.bl_desc_dmem_load_off.
36 */
37struct flcn_bl_dmem_desc {
38 u32 reserved[4]; /*Should be the first element..*/
39 u32 signature[4]; /*Should be the first element..*/
40 u32 ctx_dma;
41 u32 code_dma_base;
42 u32 non_sec_code_off;
43 u32 non_sec_code_size;
44 u32 sec_code_off;
45 u32 sec_code_size;
46 u32 code_entry_point;
47 u32 data_dma_base;
48 u32 data_size;
49 u32 code_dma_base1;
50 u32 data_dma_base1;
51};
52
53struct flcn_bl_dmem_desc_v1 {
54 u32 reserved[4]; /*Should be the first element..*/
55 u32 signature[4]; /*Should be the first element..*/
56 u32 ctx_dma;
57 struct falc_u64 code_dma_base;
58 u32 non_sec_code_off;
59 u32 non_sec_code_size;
60 u32 sec_code_off;
61 u32 sec_code_size;
62 u32 code_entry_point;
63 struct falc_u64 data_dma_base;
64 u32 data_size;
65 u32 argc;
66 u32 argv;
67};
68
69/*
70 * The header used by NVGPU to figure out code and data sections of bootloader
71 *
72 * bl_code_off - Offset of code section in the image
73 * bl_code_size - Size of code section in the image
74 * bl_data_off - Offset of data section in the image
75 * bl_data_size - Size of data section in the image
76 */
77struct flcn_bl_img_hdr {
78 u32 bl_code_off;
79 u32 bl_code_size;
80 u32 bl_data_off;
81 u32 bl_data_size;
82};
83
84/*
85 * The descriptor used by NVGPU to figure out the requirements of bootloader
86 *
87 * bl_start_tag - Starting tag of bootloader
88 * bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc
89 * to be loaded
90 * bl_img_hdr - Description of the image
91 */
92struct hsflcn_bl_desc {
93 u32 bl_start_tag;
94 u32 bl_desc_dmem_load_off;
95 struct flcn_bl_img_hdr bl_img_hdr;
96};
97
98/*
99 * Legacy structure used by the current PMU/DPU bootloader.
100 */
101struct loader_config {
102 u32 dma_idx;
103 u32 code_dma_base; /* upper 32-bits of 40-bit dma address */
104 u32 code_size_total;
105 u32 code_size_to_load;
106 u32 code_entry_point;
107 u32 data_dma_base; /* upper 32-bits of 40-bit dma address */
108 u32 data_size; /* initialized data of the application */
109 u32 overlay_dma_base; /* upper 32-bits of the 40-bit dma address */
110 u32 argc;
111 u32 argv;
112 u16 code_dma_base1; /* upper 7 bits of 47-bit dma address */
113 u16 data_dma_base1; /* upper 7 bits of 47-bit dma address */
114 u16 overlay_dma_base1; /* upper 7 bits of the 47-bit dma address */
115};
116
117struct loader_config_v1 {
118 u32 reserved;
119 u32 dma_idx;
120 struct falc_u64 code_dma_base;
121 u32 code_size_total;
122 u32 code_size_to_load;
123 u32 code_entry_point;
124 struct falc_u64 data_dma_base;
125 u32 data_size;
126 struct falc_u64 overlay_dma_base;
127 u32 argc;
128 u32 argv;
129};
130
131/*
132 * Union of all supported structures used by bootloaders.
133 */
134union flcn_bl_generic_desc {
135 struct flcn_bl_dmem_desc bl_dmem_desc;
136 struct loader_config loader_cfg;
137};
138
139union flcn_bl_generic_desc_v1 {
140 struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1;
141 struct loader_config_v1 loader_cfg_v1;
142};
143
144#endif /* NVGPU_ACR_FLCNBL_H */
diff --git a/include/nvgpu/acr/acr_lsfm.h b/include/nvgpu/acr/acr_lsfm.h
new file mode 100644
index 0000000..ed58552
--- /dev/null
+++ b/include/nvgpu/acr/acr_lsfm.h
@@ -0,0 +1,328 @@
1/*
2 * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22#ifndef NVGPU_ACR_LSFM_H
23#define NVGPU_ACR_LSFM_H
24
25#ifndef NVGPU_ACR_H
26#warning "acr_lsfm.h not included from nvgpu_acr.h!" \
27 "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces"
28#endif
29
30/*
31 * READ/WRITE masks for WPR region
32 */
33/* Readable only from level 2 and 3 client */
34#define LSF_WPR_REGION_RMASK (0xC)
35/* Writable only from level 2 and 3 client */
36#define LSF_WPR_REGION_WMASK (0xC)
37/* Readable only from level 3 client */
38#define LSF_WPR_REGION_RMASK_SUB_WPR_ENABLED (0x8)
39/* Writable only from level 3 client */
40#define LSF_WPR_REGION_WMASK_SUB_WPR_ENABLED (0x8)
41/* Disallow read mis-match for all clients */
42#define LSF_WPR_REGION_ALLOW_READ_MISMATCH_NO (0x0)
43/* Disallow write mis-match for all clients */
44#define LSF_WPR_REGION_ALLOW_WRITE_MISMATCH_NO (0x0)
45
46/*
47 * Falcon Id Defines
48 * Defines a common Light Secure Falcon identifier.
49 */
50#define LSF_FALCON_ID_PMU (0)
51#define LSF_FALCON_ID_GSPLITE (1)
52#define LSF_FALCON_ID_FECS (2)
53#define LSF_FALCON_ID_GPCCS (3)
54#define LSF_FALCON_ID_SEC2 (7)
55#define LSF_FALCON_ID_END (11)
56#define LSF_FALCON_ID_INVALID (0xFFFFFFFF)
57
58/*
59 * Light Secure Falcon Ucode Description Defines
60 * This structure is prelim and may change as the ucode signing flow evolves.
61 */
62struct lsf_ucode_desc {
63 u8 prd_keys[2][16];
64 u8 dbg_keys[2][16];
65 u32 b_prd_present;
66 u32 b_dbg_present;
67 u32 falcon_id;
68};
69
70struct lsf_ucode_desc_v1 {