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-rw-r--r--include/nvgpu/acr/nvgpu_acr.h188
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diff --git a/include/nvgpu/acr/nvgpu_acr.h b/include/nvgpu/acr/nvgpu_acr.h
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1/*
2 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef NVGPU_ACR_H
24#define NVGPU_ACR_H
25
26#include <nvgpu/falcon.h>
27
28#include "gk20a/mm_gk20a.h"
29
30#include "acr_lsfm.h"
31#include "acr_flcnbl.h"
32#include "acr_objlsfm.h"
33#include "acr_objflcn.h"
34
35struct nvgpu_firmware;
36struct gk20a;
37struct hs_acr_ops;
38struct hs_acr;
39struct nvgpu_acr;
40
41#define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin"
42#define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin"
43#define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin"
44#define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin"
45#define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin"
46#define HSBIN_ACR_ASB_DBG_UCODE "acr_asb_dbg_ucode.bin"
47
48#define LSF_SEC2_UCODE_IMAGE_BIN "sec2_ucode_image.bin"
49#define LSF_SEC2_UCODE_DESC_BIN "sec2_ucode_desc.bin"
50#define LSF_SEC2_UCODE_SIG_BIN "sec2_sig.bin"
51
52#define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/
53
54#define ACR_COMPLETION_TIMEOUT_MS 10000 /*in msec */
55
56#define PMU_SECURE_MODE (0x1)
57#define PMU_LSFM_MANAGED (0x2)
58
59struct bin_hdr {
60 /* 0x10de */
61 u32 bin_magic;
62 /* versioning of bin format */
63 u32 bin_ver;
64 /* Entire image size including this header */
65 u32 bin_size;
66 /*
67 * Header offset of executable binary metadata,
68 * start @ offset- 0x100 *
69 */
70 u32 header_offset;
71 /*
72 * Start of executable binary data, start @
73 * offset- 0x200
74 */
75 u32 data_offset;
76 /* Size of executable binary */
77 u32 data_size;
78};
79
80struct acr_fw_header {
81 u32 sig_dbg_offset;
82 u32 sig_dbg_size;
83 u32 sig_prod_offset;
84 u32 sig_prod_size;
85 u32 patch_loc;
86 u32 patch_sig;
87 u32 hdr_offset; /* This header points to acr_ucode_header_t210_load */
88 u32 hdr_size; /* Size of above header */
89};
90
91struct wpr_carveout_info {
92 u64 wpr_base;
93 u64 nonwpr_base;
94 u64 size;
95};
96
97/* ACR interfaces */
98
99struct hs_flcn_bl {
100 char *bl_fw_name;
101 struct nvgpu_firmware *hs_bl_fw;
102 struct hsflcn_bl_desc *hs_bl_desc;
103 struct bin_hdr *hs_bl_bin_hdr;
104 struct nvgpu_mem hs_bl_ucode;
105};
106
107struct hs_acr {
108 u32 acr_type;
109
110 /* HS bootloader to validate & load ACR ucode */
111 struct hs_flcn_bl acr_hs_bl;
112
113 /* ACR ucode */
114 char *acr_fw_name;
115 struct nvgpu_firmware *acr_fw;
116 struct nvgpu_mem acr_ucode;
117
118 union {
119 struct flcn_bl_dmem_desc bl_dmem_desc;
120 struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1;
121 };
122
123 void *ptr_bl_dmem_desc;
124 u32 bl_dmem_desc_size;
125
126 union{
127 struct flcn_acr_desc *acr_dmem_desc;
128 struct flcn_acr_desc_v1 *acr_dmem_desc_v1;
129 };
130
131 /* Falcon used to execute ACR ucode */
132 struct nvgpu_falcon *acr_flcn;
133
134 int (*acr_flcn_setup_hw_and_bl_bootstrap)(struct gk20a *g,
135 struct hs_acr *acr_desc,
136 struct nvgpu_falcon_bl_info *bl_info);
137};
138
139#define ACR_DEFAULT 0U
140#define ACR_AHESASC 1U
141#define ACR_ASB 2U
142
143struct nvgpu_acr {
144 struct gk20a *g;
145
146 u32 bootstrap_owner;
147 u32 max_supported_lsfm;
148 u32 capabilities;
149
150 /*
151 * non-wpr space to hold LSF ucodes,
152 * ACR does copy ucode from non-wpr to wpr
153 */
154 struct nvgpu_mem ucode_blob;
155 /*
156 * Even though this mem_desc wouldn't be used,
157 * the wpr region needs to be reserved in the
158 * allocator in dGPU case.
159 */
160 struct nvgpu_mem wpr_dummy;
161
162 /* ACR member for different types of ucode */
163 /* For older dgpu/tegra ACR cuode */
164 struct hs_acr acr;
165 /* ACR load split feature support */
166 struct hs_acr acr_ahesasc;
167 struct hs_acr acr_asb;
168
169 u32 pmu_args;
170 struct nvgpu_firmware *pmu_fw;
171 struct nvgpu_firmware *pmu_desc;
172
173 int (*prepare_ucode_blob)(struct gk20a *g, struct nvgpu_acr *acr);
174 void (*get_wpr_info)(struct gk20a *g, struct wpr_carveout_info *inf);
175 int (*alloc_blob_space)(struct gk20a *g, size_t size,
176 struct nvgpu_mem *mem);
177 int (*patch_wpr_info_to_ucode)(struct gk20a *g, struct nvgpu_acr *acr,
178 struct hs_acr *acr_desc, bool is_recovery);
179 int (*acr_fill_bl_dmem_desc)(struct gk20a *g,
180 struct nvgpu_acr *acr, struct hs_acr *acr_desc,
181 u32 *acr_ucode_header);
182 int (*bootstrap_hs_acr)(struct gk20a *g, struct nvgpu_acr *acr,
183 struct hs_acr *acr_desc);
184
185 void (*remove_support)(struct nvgpu_acr *acr);
186};
187#endif /* NVGPU_ACR_H */
188
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