Update includes to L4T r32.7.4 and drop nvgpu/gk20a.h dependency

Also add instructions for updating `include/`. These files are now
only needed to build on Linux 4.9-based Tegra platforms.

13 files changed, 618 insertions, 98 deletions

diff --git a/include/os/linux/debug.c b/include/os/linux/debug.c
index 5f0703c..b8c4596 100644
--- a/include/os/linux/debug.c
+++ b/include/os/linux/debug.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2017-2018 NVIDIA Corporation.  All rights reserved.
+ * Copyright (C) 2017-2021 NVIDIA Corporation.  All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -224,7 +224,7 @@ static int railgate_residency_show(struct seq_file *s, void *data)
         unsigned long total_rail_gate_time_ms;
         unsigned long total_rail_ungate_time_ms;
 
-        if (platform->is_railgated(dev_from_gk20a(g))) {
+        if (platform && platform->is_railgated && platform->is_railgated(dev_from_gk20a(g))) {
                 time_since_last_state_transition_ms =
                                 jiffies_to_msecs(jiffies -
                                 g->pstats.last_rail_gate_complete);
diff --git a/include/os/linux/driver_common.c b/include/os/linux/driver_common.c
index c76dabe..8f5872d 100644
--- a/include/os/linux/driver_common.c
+++ b/include/os/linux/driver_common.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2022, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -18,6 +18,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/mm.h>
 #include <linux/slab.h>
+#include <linux/of_platform.h>
 #include <uapi/linux/nvgpu.h>
 
 #include <nvgpu/defaults.h>
@@ -241,6 +242,8 @@ int nvgpu_probe(struct gk20a *g,
         struct device *dev = dev_from_gk20a(g);
         struct gk20a_platform *platform = dev_get_drvdata(dev);
         int err = 0;
+        struct device_node *np = dev->of_node;
+        bool disable_l3_alloc = false;
 
         nvgpu_init_vars(g);
         nvgpu_init_gr_vars(g);
@@ -265,6 +268,12 @@ int nvgpu_probe(struct gk20a *g,
                 return err;
         }
 
+        disable_l3_alloc = of_property_read_bool(np, "disable_l3_alloc");
+        if (disable_l3_alloc) {
+                nvgpu_log_info(g, "L3 alloc is disabled\n");
+                __nvgpu_set_enabled(g, NVGPU_DISABLE_L3_SUPPORT, true);
+        }
+
         nvgpu_init_mm_vars(g);
 
         /* platform probe can defer do user init only if probe succeeds */
@@ -312,30 +321,70 @@ static int cyclic_delta(int a, int b)
 }
 
 /**
- * nvgpu_wait_for_deferred_interrupts - Wait for interrupts to complete
+ * nvgpu_wait_for_stall_interrupts - Wait for the stalling interrupts to
+ *                                   complete.
  *
  * @g - The GPU to wait on.
+ * @timeout - maximum time period to wait for.
  *
- * Waits until all interrupt handlers that have been scheduled to run have
- * completed.
+ * Waits until all stalling interrupt handlers that have been scheduled to run
+ * have completed.
  */
-void nvgpu_wait_for_deferred_interrupts(struct gk20a *g)
+int nvgpu_wait_for_stall_interrupts(struct gk20a *g, u32 timeout)
 {
         struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
         int stall_irq_threshold = atomic_read(&l->hw_irq_stall_count);
-        int nonstall_irq_threshold = atomic_read(&l->hw_irq_nonstall_count);
 
         /* wait until all stalling irqs are handled */
-        NVGPU_COND_WAIT(&l->sw_irq_stall_last_handled_wq,
+        return NVGPU_COND_WAIT(&l->sw_irq_stall_last_handled_wq,
                    cyclic_delta(stall_irq_threshold,
                                 atomic_read(&l->sw_irq_stall_last_handled))
-                   <= 0, 0);
+                   <= 0, timeout);
+}
+
+/**
+ * nvgpu_wait_for_nonstall_interrupts - Wait for the nonstalling interrupts to
+ *                                      complete.
+ *
+ * @g - The GPU to wait on.
+ * @timeout - maximum time period to wait for.
+ *
+ * Waits until all non-stalling interrupt handlers that have been scheduled to
+ * run have completed.
+ */
+int nvgpu_wait_for_nonstall_interrupts(struct gk20a *g, u32 timeout)
+{
+        struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
+        int nonstall_irq_threshold = atomic_read(&l->hw_irq_nonstall_count);
 
         /* wait until all non-stalling irqs are handled */
-        NVGPU_COND_WAIT(&l->sw_irq_nonstall_last_handled_wq,
+        return NVGPU_COND_WAIT(&l->sw_irq_nonstall_last_handled_wq,
                    cyclic_delta(nonstall_irq_threshold,
                                 atomic_read(&l->sw_irq_nonstall_last_handled))
-                   <= 0, 0);
+                   <= 0, timeout);
+}
+
+/**
+ * nvgpu_wait_for_deferred_interrupts - Wait for interrupts to complete
+ *
+ * @g - The GPU to wait on.
+ *
+ * Waits until all interrupt handlers that have been scheduled to run have
+ * completed.
+ */
+void nvgpu_wait_for_deferred_interrupts(struct gk20a *g)
+{
+        int ret;
+
+        ret = nvgpu_wait_for_stall_interrupts(g, 0U);
+        if (ret != 0) {
+                nvgpu_err(g, "wait for stall interrupts failed %d", ret);
+        }
+
+        ret = nvgpu_wait_for_nonstall_interrupts(g, 0U);
+        if (ret != 0) {
+                nvgpu_err(g, "wait for nonstall interrupts failed %d", ret);
+        }
 }
 
 static void nvgpu_free_gk20a(struct gk20a *g)
diff --git a/include/os/linux/ecc_linux.h b/include/os/linux/ecc_linux.h
new file mode 100644
index 0000000..7e0f650
--- /dev/null
+++ b/include/os/linux/ecc_linux.h
@@ -0,0 +1,49 @@
+/*
+ *
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef NVGPU_OS_ECC_LINUX_H
+#define NVGPU_OS_ECC_LINUX_H
+
+#ifdef CONFIG_NVGPU_SUPPORT_LINUX_ECC_ERROR_REPORTING
+
+#include <linux/tegra_l1ss_kernel_interface.h>
+#include <linux/tegra_l1ss_ioctl.h>
+#include <linux/tegra_nv_guard_service_id.h>
+#include <linux/tegra_nv_guard_group_id.h>