Update includes to L4T r32.7.4 and drop nvgpu/gk20a.h dependency

Also add instructions for updating `include/`. These files are now
only needed to build on Linux 4.9-based Tegra platforms.

63 files changed, 1305 insertions, 11354 deletions

diff --git a/include/HOW_TO_REBUILD_THIS.md b/include/HOW_TO_REBUILD_THIS.md
new file mode 100644
index 0000000..dcb1084
--- /dev/null
+++ b/include/HOW_TO_REBUILD_THIS.md
@@ -0,0 +1,22 @@
+First the internal `include` and `os` directories:
+```
+cp -r /playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/include/nvgpu/
+cp -r /playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/os include/
+```
+
+Then every directory needed by either of those includes:
+```
+cp -r /playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/os include/
+/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/gk20a include/
+/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/ctrl include/
+/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/clk include/
+/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/boardobj include/
+/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/pmu_perf include/
+/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/pstate include/
+/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/volt include/
+/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/lpwr include/
+/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/pmgr include/
+/playpen/Linux_for_Tegra/source/public/kernel/nvgpu/drivers/gpu/nvgpu/therm include/
+```
+
+Make sure to pull the same version of L4T that you're building on! The structure layout is highly dependant on the version.
diff --git a/include/clk/clk_arb.c b/include/clk/clk_arb.c
index 6cf005c..8e9fb41 100644
--- a/include/clk/clk_arb.c
+++ b/include/clk/clk_arb.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -886,8 +886,8 @@ void nvgpu_clk_arb_free_session(struct nvgpu_ref *refcount)
         nvgpu_spinlock_acquire(&session->session_lock);
         nvgpu_list_for_each_entry_safe(dev, tmp, &session->targets,
                         nvgpu_clk_dev, node) {
-                nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd);
                 nvgpu_list_del(&dev->node);
+                nvgpu_ref_put(&dev->refcount, nvgpu_clk_arb_free_fd);
         }
         nvgpu_spinlock_release(&session->session_lock);
 
diff --git a/include/gk20a/fifo_gk20a.c b/include/gk20a/fifo_gk20a.c
index 4477f7c..77babc7 100644
--- a/include/gk20a/fifo_gk20a.c
+++ b/include/gk20a/fifo_gk20a.c
@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics FIFO (gr host)
  *
- * Copyright (c) 2011-2020, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2021, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -58,8 +58,6 @@
 #include <nvgpu/hw/gk20a/hw_top_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 
-#include <os/linux/os_linux.h>
-
 #define FECS_METHOD_WFI_RESTORE 0x80000
 #define FECS_MAILBOX_0_ACK_RESTORE 0x4
 
@@ -1409,6 +1407,7 @@ static void gk20a_fifo_handle_chsw_fault(struct gk20a *g)
         intr = gk20a_readl(g, fifo_intr_chsw_error_r());
         nvgpu_err(g, "chsw: %08x", intr);
         gk20a_fecs_dump_falcon_stats(g);
+        gk20a_gpccs_dump_falcon_stats(g);
         gk20a_writel(g, fifo_intr_chsw_error_r(), intr);
 }
 
@@ -1604,6 +1603,7 @@ int gk20a_fifo_deferred_reset(struct gk20a *g, struct channel_gk20a *ch)
                 engines = gk20a_fifo_engines_on_id(g, tsg->tsgid, true);
         } else {
                 nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid);
+                engines = g->fifo.deferred_fault_engines;
         }
 
         if (engines == 0U) {
@@ -1724,6 +1724,7 @@ static bool gk20a_fifo_handle_mmu_fault_locked(
 
                 if (ctxsw) {
                         gk20a_fecs_dump_falcon_stats(g);
+                        gk20a_gpccs_dump_falcon_stats(g);
                         nvgpu_err(g, "gr_status_r : 0x%x",
                                         gk20a_readl(g, gr_status_r()));
                 }
@@ -2198,9 +2199,9 @@ int gk20a_fifo_tsg_unbind_channel_verify_status(struct channel_gk20a *ch)
         struct gk20a *g = ch->g;
 
         if (gk20a_fifo_channel_status_is_next(g, ch->chid)) {
-                nvgpu_err(g, "Channel %d to be removed from TSG %d has NEXT set!",
+                nvgpu_log_info(g, "Channel %d to be removed from TSG %d has NEXT set!",
                         ch->chid, ch->tsgid);
-                return -EINVAL;
+                return -EAGAIN;