diff options
author | Joshua Bakita <bakitajoshua@gmail.com> | 2023-06-28 18:24:25 -0400 |
---|---|---|
committer | Joshua Bakita <bakitajoshua@gmail.com> | 2023-06-28 18:24:25 -0400 |
commit | 01e6fac4d61fdd7fff5433942ec93fc2ea1e4df1 (patch) | |
tree | 4ef34501728a087be24f4ba0af90f91486bf780b /include/nvgpu/pmuif/gpmuifpmgr.h | |
parent | 306a03d18b305e4e573be3b2931978fa10679eb9 (diff) |
Include nvgpu headers
These are needed to build on NVIDIA's Jetson boards for the time
being. Only a couple structs are required, so it should be fairly
easy to remove this dependency at some point in the future.
Diffstat (limited to 'include/nvgpu/pmuif/gpmuifpmgr.h')
-rw-r--r-- | include/nvgpu/pmuif/gpmuifpmgr.h | 443 |
1 files changed, 443 insertions, 0 deletions
diff --git a/include/nvgpu/pmuif/gpmuifpmgr.h b/include/nvgpu/pmuif/gpmuifpmgr.h new file mode 100644 index 0000000..a0e6c82 --- /dev/null +++ b/include/nvgpu/pmuif/gpmuifpmgr.h | |||
@@ -0,0 +1,443 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_PMUIF_GPMUIFPMGR_H | ||
24 | #define NVGPU_PMUIF_GPMUIFPMGR_H | ||
25 | |||
26 | #include "ctrl/ctrlpmgr.h" | ||
27 | #include "gpmuifboardobj.h" | ||
28 | #include <nvgpu/flcnif_cmn.h> | ||
29 | |||
30 | struct nv_pmu_pmgr_i2c_device_desc { | ||
31 | struct nv_pmu_boardobj super; | ||
32 | u8 dcb_index; | ||
33 | u16 i2c_address; | ||
34 | u32 i2c_flags; | ||
35 | u8 i2c_port; | ||
36 | }; | ||
37 | |||
38 | #define NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES (32U) | ||
39 | |||
40 | struct nv_pmu_pmgr_i2c_device_desc_table { | ||
41 | u32 dev_mask; | ||
42 | struct nv_pmu_pmgr_i2c_device_desc | ||
43 | devices[NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES]; | ||
44 | }; | ||
45 | |||
46 | struct nv_pmu_pmgr_pwr_device_desc { | ||
47 | struct nv_pmu_boardobj super; | ||
48 | u32 power_corr_factor; | ||
49 | }; | ||
50 | |||
51 | #define NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM 0x03U | ||
52 | |||
53 | struct nv_pmu_pmgr_pwr_device_desc_ina3221 { | ||
54 | struct nv_pmu_pmgr_pwr_device_desc super; | ||
55 | u8 i2c_dev_idx; | ||
56 | struct ctrl_pmgr_pwr_device_info_rshunt | ||
57 | r_shuntm_ohm[NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM]; | ||
58 | u16 configuration; | ||
59 | u16 mask_enable; | ||
60 | u32 event_mask; | ||
61 | u16 curr_correct_m; | ||
62 | s16 curr_correct_b; | ||
63 | }; | ||
64 | |||
65 | union nv_pmu_pmgr_pwr_device_desc_union { | ||
66 | struct nv_pmu_boardobj board_obj; | ||
67 | struct nv_pmu_pmgr_pwr_device_desc pwr_dev; | ||
68 | struct nv_pmu_pmgr_pwr_device_desc_ina3221 ina3221; | ||
69 | }; | ||
70 | |||
71 | struct nv_pmu_pmgr_pwr_device_ba_info { | ||
72 | bool b_initialized_and_used; | ||
73 | }; | ||
74 | |||
75 | struct nv_pmu_pmgr_pwr_device_desc_table_header { | ||
76 | struct nv_pmu_boardobjgrp_e32 super; | ||
77 | struct nv_pmu_pmgr_pwr_device_ba_info ba_info; | ||
78 | }; | ||
79 | |||
80 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_device_desc_table_header, | ||
81 | sizeof(struct nv_pmu_pmgr_pwr_device_desc_table_header)); | ||
82 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_device_desc_union, | ||
83 | sizeof(union nv_pmu_pmgr_pwr_device_desc_union)); | ||
84 | |||
85 | struct nv_pmu_pmgr_pwr_device_desc_table { | ||
86 | union nv_pmu_pmgr_pwr_device_desc_table_header_aligned hdr; | ||
87 | union nv_pmu_pmgr_pwr_device_desc_union_aligned | ||
88 | devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES]; | ||
89 | }; | ||
90 | |||
91 | union nv_pmu_pmgr_pwr_device_dmem_size { | ||
92 | union nv_pmu_pmgr_pwr_device_desc_table_header_aligned pwr_device_hdr; | ||
93 | union nv_pmu_pmgr_pwr_device_desc_union_aligned pwr_device; | ||
94 | }; | ||
95 | |||
96 | struct nv_pmu_pmgr_pwr_channel { | ||
97 | struct nv_pmu_boardobj super; | ||
98 | u8 pwr_rail; | ||
99 | u8 ch_idx; | ||
100 | u32 volt_fixedu_v; | ||
101 | u32 pwr_corr_slope; | ||
102 | s32 pwr_corr_offsetm_w; | ||
103 | u32 curr_corr_slope; | ||
104 | s32 curr_corr_offsetm_a; | ||
105 | u32 dependent_ch_mask; | ||
106 | }; | ||
107 | |||
108 | #define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS 16U | ||
109 | |||
110 | #define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS 16U | ||
111 | |||
112 | struct nv_pmu_pmgr_pwr_channel_sensor { | ||
113 | struct nv_pmu_pmgr_pwr_channel super; | ||
114 | u8 pwr_dev_idx; | ||
115 | u8 pwr_dev_prov_idx; | ||
116 | }; | ||
117 | |||
118 | struct nv_pmu_pmgr_pwr_channel_pmu_compactible { | ||
119 | u8 pmu_compactible_data[56]; | ||
120 | }; | ||
121 | |||
122 | union nv_pmu_pmgr_pwr_channel_union { | ||
123 | struct nv_pmu_boardobj board_obj; | ||
124 | struct nv_pmu_pmgr_pwr_channel pwr_channel; | ||
125 | struct nv_pmu_pmgr_pwr_channel_sensor sensor; | ||
126 | struct nv_pmu_pmgr_pwr_channel_pmu_compactible pmu_pwr_channel; | ||
127 | }; | ||
128 | |||
129 | #define NV_PMU_PMGR_PWR_MONITOR_TYPE_NO_POLLING 0x02U | ||
130 | |||
131 | struct nv_pmu_pmgr_pwr_monitor_pstate { | ||
132 | u32 hw_channel_mask; | ||
133 | }; | ||
134 | |||
135 | union nv_pmu_pmgr_pwr_monitor_type_specific { | ||
136 | struct nv_pmu_pmgr_pwr_monitor_pstate pstate; | ||
137 | }; | ||
138 | |||
139 | struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible { | ||
140 | u8 pmu_compactible_data[28]; | ||
141 | }; | ||
142 | |||
143 | union nv_pmu_pmgr_pwr_chrelationship_union { | ||
144 | struct nv_pmu_boardobj board_obj; | ||
145 | struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible pmu_pwr_chrelationship; | ||
146 | }; | ||
147 | |||
148 | struct nv_pmu_pmgr_pwr_channel_header { | ||
149 | struct nv_pmu_boardobjgrp_e32 super; | ||
150 | u8 type; | ||
151 | union nv_pmu_pmgr_pwr_monitor_type_specific type_specific; | ||
152 | u8 sample_count; | ||
153 | u16 sampling_periodms; | ||
154 | u16 sampling_period_low_powerms; | ||
155 | u32 total_gpu_power_channel_mask; | ||
156 | u32 physical_channel_mask; | ||
157 | }; | ||
158 | |||
159 | struct nv_pmu_pmgr_pwr_chrelationship_header { | ||
160 | struct nv_pmu_boardobjgrp_e32 super; | ||
161 | }; | ||
162 | |||
163 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_channel_header, | ||
164 | sizeof(struct nv_pmu_pmgr_pwr_channel_header)); | ||
165 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_chrelationship_header, | ||
166 | sizeof(struct nv_pmu_pmgr_pwr_chrelationship_header)); | ||
167 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_chrelationship_union, | ||
168 | sizeof(union nv_pmu_pmgr_pwr_chrelationship_union)); | ||
169 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_channel_union, | ||
170 | sizeof(union nv_pmu_pmgr_pwr_channel_union)); | ||
171 | |||
172 | struct nv_pmu_pmgr_pwr_channel_desc { | ||
173 | union nv_pmu_pmgr_pwr_channel_header_aligned hdr; | ||
174 | union nv_pmu_pmgr_pwr_channel_union_aligned | ||
175 | channels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS]; | ||
176 | }; | ||
177 | |||
178 | struct nv_pmu_pmgr_pwr_chrelationship_desc { | ||
179 | union nv_pmu_pmgr_pwr_chrelationship_header_aligned hdr; | ||
180 | union nv_pmu_pmgr_pwr_chrelationship_union_aligned | ||
181 | ch_rels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS]; | ||
182 | }; | ||
183 | |||
184 | union nv_pmu_pmgr_pwr_monitor_dmem_size { | ||
185 | union nv_pmu_pmgr_pwr_channel_header_aligned channel_hdr; | ||
186 | union nv_pmu_pmgr_pwr_channel_union_aligned channel; | ||
187 | union nv_pmu_pmgr_pwr_chrelationship_header_aligned ch_rels_hdr; | ||
188 | union nv_pmu_pmgr_pwr_chrelationship_union_aligned ch_rels; | ||
189 | }; | ||
190 | |||
191 | struct nv_pmu_pmgr_pwr_monitor_pack { | ||
192 | struct nv_pmu_pmgr_pwr_channel_desc channels; | ||
193 | struct nv_pmu_pmgr_pwr_chrelationship_desc ch_rels; | ||
194 | }; | ||
195 | |||
196 | #define NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES 32U | ||
197 | |||
198 | #define NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS 32U | ||
199 | |||
200 | struct nv_pmu_pmgr_pwr_policy { | ||
201 | struct nv_pmu_boardobj super; | ||
202 | u8 ch_idx; | ||
203 | u8 num_limit_inputs; | ||
204 | u8 limit_unit; | ||
205 | u8 sample_mult; | ||
206 | u32 limit_curr; | ||
207 | u32 limit_min; | ||
208 | u32 limit_max; | ||
209 | struct ctrl_pmgr_pwr_policy_info_integral integral; | ||
210 | enum ctrl_pmgr_pwr_policy_filter_type filter_type; | ||
211 | union ctrl_pmgr_pwr_policy_filter_param filter_param; | ||
212 | }; | ||
213 | |||
214 | struct nv_pmu_pmgr_pwr_policy_hw_threshold { | ||
215 | struct nv_pmu_pmgr_pwr_policy super; | ||
216 | u8 threshold_idx; | ||
217 | u8 low_threshold_idx; | ||
218 | bool b_use_low_threshold; | ||
219 | u16 low_threshold_value; | ||
220 | }; | ||
221 | |||
222 | struct nv_pmu_pmgr_pwr_policy_sw_threshold { | ||
223 | struct nv_pmu_pmgr_pwr_policy super; | ||
224 | u8 threshold_idx; | ||
225 | u8 low_threshold_idx; | ||
226 | bool b_use_low_threshold; | ||
227 | u16 low_threshold_value; | ||
228 | u8 event_id; | ||
229 | }; | ||
230 | |||
231 | struct nv_pmu_pmgr_pwr_policy_pmu_compactible { | ||
232 | u8 pmu_compactible_data[68]; | ||
233 | }; | ||
234 | |||
235 | union nv_pmu_pmgr_pwr_policy_union { | ||
236 | struct nv_pmu_boardobj board_obj; | ||
237 | struct nv_pmu_pmgr_pwr_policy pwr_policy; | ||
238 | struct nv_pmu_pmgr_pwr_policy_hw_threshold hw_threshold; | ||
239 | struct nv_pmu_pmgr_pwr_policy_sw_threshold sw_threshold; | ||
240 | struct nv_pmu_pmgr_pwr_policy_pmu_compactible pmu_pwr_policy; | ||
241 | }; | ||
242 | |||
243 | struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible { | ||
244 | u8 pmu_compactible_data[24]; | ||
245 | }; | ||
246 | |||
247 | union nv_pmu_pmgr_pwr_policy_relationship_union { | ||
248 | struct nv_pmu_boardobj board_obj; | ||
249 | struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible pmu_pwr_relationship; | ||
250 | }; | ||
251 | |||
252 | struct nv_pmu_pmgr_pwr_violation_pmu_compactible { | ||
253 | u8 pmu_compactible_data[16]; | ||
254 | }; | ||
255 | |||
256 | union nv_pmu_pmgr_pwr_violation_union { | ||
257 | struct nv_pmu_boardobj board_obj; | ||
258 | struct nv_pmu_pmgr_pwr_violation_pmu_compactible violation; | ||
259 | }; | ||
260 | |||
261 | #define NV_PMU_PMGR_PWR_POLICY_DESC_TABLE_VERSION_3X 0x30U | ||
262 | |||
263 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_union, | ||
264 | sizeof(union nv_pmu_pmgr_pwr_policy_union)); | ||
265 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_relationship_union, | ||
266 | sizeof(union nv_pmu_pmgr_pwr_policy_relationship_union)); | ||
267 | |||
268 | #define NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS 2U | ||
269 | |||
270 | struct nv_pmu_perf_domain_group_limits | ||
271 | { | ||
272 | u32 values[NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS]; | ||
273 | } ; | ||
274 | |||
275 | #define NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT 0x6U | ||
276 | |||
277 | struct nv_pmu_pmgr_pwr_policy_desc_header { | ||
278 | struct nv_pmu_boardobjgrp_e32 super; | ||
279 | u8 version; | ||
280 | bool b_enabled; | ||
281 | u8 low_sampling_mult; | ||
282 | u8 semantic_policy_tbl[CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES]; | ||
283 | u16 base_sample_period; | ||
284 | u16 min_client_sample_period; | ||
285 | u32 reserved_pmu_policy_mask[NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT]; | ||
286 | struct nv_pmu_perf_domain_group_limits global_ceiling; | ||
287 | }; | ||
288 | |||
289 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policy_desc_header , | ||
290 | sizeof(struct nv_pmu_pmgr_pwr_policy_desc_header )); | ||
291 | |||
292 | struct nv_pmu_pmgr_pwr_policyrel_desc_header { | ||
293 | struct nv_pmu_boardobjgrp_e32 super; | ||
294 | }; | ||
295 | |||
296 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policyrel_desc_header, | ||
297 | sizeof(struct nv_pmu_pmgr_pwr_policyrel_desc_header)); | ||
298 | |||
299 | struct nv_pmu_pmgr_pwr_violation_desc_header { | ||
300 | struct nv_pmu_boardobjgrp_e32 super; | ||
301 | }; | ||
302 | |||
303 | NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_violation_desc_header, | ||
304 | sizeof(struct nv_pmu_pmgr_pwr_violation_desc_header)); | ||
305 | NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_violation_union, | ||
306 | sizeof(union nv_pmu_pmgr_pwr_violation_union)); | ||
307 | |||
308 | struct nv_pmu_pmgr_pwr_policy_desc { | ||
309 | union nv_pmu_pmgr_pwr_policy_desc_header_aligned hdr; | ||
310 | union nv_pmu_pmgr_pwr_policy_union_aligned | ||
311 | policies[NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES]; | ||
312 | }; | ||
313 | |||
314 | struct nv_pmu_pmgr_pwr_policyrel_desc { | ||
315 | union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned hdr; | ||
316 | union nv_pmu_pmgr_pwr_policy_relationship_union_aligned | ||
317 | policy_rels[NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS]; | ||
318 | }; | ||
319 | |||
320 | struct nv_pmu_pmgr_pwr_violation_desc { | ||
321 | union nv_pmu_pmgr_pwr_violation_desc_header_aligned hdr; | ||
322 | union nv_pmu_pmgr_pwr_violation_union_aligned | ||
323 | violations[CTRL_PMGR_PWR_VIOLATION_MAX]; | ||
324 | }; | ||
325 | |||
326 | union nv_pmu_pmgr_pwr_policy_dmem_size { | ||
327 | union nv_pmu_pmgr_pwr_policy_desc_header_aligned policy_hdr; | ||
328 | union nv_pmu_pmgr_pwr_policy_union_aligned policy; | ||
329 | union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned policy_rels_hdr; | ||
330 | union nv_pmu_pmgr_pwr_policy_relationship_union_aligned policy_rels; | ||
331 | union nv_pmu_pmgr_pwr_violation_desc_header_aligned violation_hdr; | ||
332 | union nv_pmu_pmgr_pwr_violation_union_aligned violation; | ||
333 | }; | ||
334 | |||
335 | struct nv_pmu_pmgr_pwr_policy_pack { | ||
336 | struct nv_pmu_pmgr_pwr_policy_desc policies; | ||
337 | struct nv_pmu_pmgr_pwr_policyrel_desc policy_rels; | ||
338 | struct nv_pmu_pmgr_pwr_violation_desc violations; | ||
339 | }; | ||
340 | |||
341 | #define NV_PMU_PMGR_CMD_ID_SET_OBJECT (0x00000000U) | ||
342 | |||
343 | #define NV_PMU_PMGR_MSG_ID_QUERY (0x00000002U) | ||
344 | |||
345 | #define NV_PMU_PMGR_CMD_ID_PWR_DEVICES_QUERY (0x00000001U) | ||
346 | |||
347 | #define NV_PMU_PMGR_CMD_ID_LOAD (0x00000006U) | ||
348 | |||
349 | #define NV_PMU_PMGR_CMD_ID_UNLOAD (0x00000007U) | ||
350 | |||
351 | struct nv_pmu_pmgr_cmd_set_object { | ||
352 | u8 cmd_type; | ||
353 | u8 pad[2]; | ||
354 | u8 object_type; | ||
355 | struct nv_pmu_allocation object; | ||
356 | }; | ||
357 | |||
358 | #define NV_PMU_PMGR_SET_OBJECT_ALLOC_OFFSET (0x04U) | ||
359 | |||
360 | #define NV_PMU_PMGR_OBJECT_I2C_DEVICE_DESC_TABLE (0x00000000U) | ||
361 | |||
362 | #define NV_PMU_PMGR_OBJECT_PWR_DEVICE_DESC_TABLE (0x00000001U) | ||
363 | |||
364 | #define NV_PMU_PMGR_OBJECT_PWR_MONITOR (0x00000002U) | ||
365 | |||
366 | #define NV_PMU_PMGR_OBJECT_PWR_POLICY (0x00000005U) | ||
367 | |||
368 | struct nv_pmu_pmgr_pwr_devices_query_payload { | ||
369 | struct { | ||
370 | u32 powerm_w; | ||
371 | u32 voltageu_v; | ||
372 | u32 currentm_a; | ||
373 | } devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES]; | ||
374 | }; | ||
375 | |||
376 | struct nv_pmu_pmgr_cmd_pwr_devices_query { | ||
377 | u8 cmd_type; | ||
378 | u8 pad[3]; | ||
379 | u32 dev_mask; | ||
380 | struct nv_pmu_allocation payload; | ||
381 | }; | ||
382 | |||
383 | #define NV_PMU_PMGR_PWR_DEVICES_QUERY_ALLOC_OFFSET (0x08U) | ||
384 | |||
385 | struct nv_pmu_pmgr_cmd_load { | ||
386 | u8 cmd_type; | ||
387 | }; | ||
388 | |||
389 | struct nv_pmu_pmgr_cmd_unload { | ||
390 | u8 cmd_type; | ||
391 | }; | ||
392 | |||
393 | struct nv_pmu_pmgr_cmd { | ||
394 | union { | ||
395 | u8 cmd_type; | ||
396 | struct nv_pmu_pmgr_cmd_set_object set_object; | ||
397 | struct nv_pmu_pmgr_cmd_pwr_devices_query pwr_dev_query; | ||
398 | struct nv_pmu_pmgr_cmd_load load; | ||
399 | struct nv_pmu_pmgr_cmd_unload unload; | ||
400 | }; | ||
401 | }; | ||
402 | |||
403 | #define NV_PMU_PMGR_MSG_ID_SET_OBJECT (0x00000000U) | ||
404 | |||
405 | #define NV_PMU_PMGR_MSG_ID_LOAD (0x00000004U) | ||
406 | |||
407 | #define NV_PMU_PMGR_MSG_ID_UNLOAD (0x00000005U) | ||
408 | |||
409 | struct nv_pmu_pmgr_msg_set_object { | ||
410 | u8 msg_type; | ||
411 | bool b_success; | ||
412 | flcn_status flcnstatus; | ||
413 | u8 object_type; | ||
414 | }; | ||
415 | |||
416 | struct nv_pmu_pmgr_msg_query { | ||
417 | u8 msg_type; | ||
418 | bool b_success; | ||
419 | flcn_status flcnstatus; | ||
420 | u8 cmd_type; | ||
421 | }; | ||
422 | |||
423 | struct nv_pmu_pmgr_msg_load { | ||
424 | u8 msg_type; | ||
425 | bool b_success; | ||
426 | flcn_status flcnstatus; | ||
427 | }; | ||
428 | |||
429 | struct nv_pmu_pmgr_msg_unload { | ||
430 | u8 msg_type; | ||
431 | }; | ||
432 | |||
433 | struct nv_pmu_pmgr_msg { | ||
434 | union { | ||
435 | u8 msg_type; | ||
436 | struct nv_pmu_pmgr_msg_set_object set_object; | ||
437 | struct nv_pmu_pmgr_msg_query query; | ||
438 | struct nv_pmu_pmgr_msg_load load; | ||
439 | struct nv_pmu_pmgr_msg_unload unload; | ||
440 | }; | ||
441 | }; | ||
442 | |||
443 | #endif /* NVGPU_PMUIF_GPMUIFPMGR_H */ | ||