Include nvgpu headers

These are needed to build on NVIDIA's Jetson boards for the time
being. Only a couple structs are required, so it should be fairly
easy to remove this dependency at some point in the future.

37 files changed, 18975 insertions, 0 deletions

diff --git a/include/nvgpu/hw/gv100/hw_bus_gv100.h b/include/nvgpu/hw/gv100/hw_bus_gv100.h
new file mode 100644
index 0000000..7771f1e
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_bus_gv100.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_bus_gv100_h_
+#define _hw_bus_gv100_h_
+
+static inline u32 bus_sw_scratch_r(u32 i)
+{
+        return 0x00001580U + i*4U;
+}
+static inline u32 bus_bar0_window_r(void)
+{
+        return 0x00001700U;
+}
+static inline u32 bus_bar0_window_base_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 bus_bar0_window_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void)
+{
+        return 0x3000000U;
+}
+static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 bus_bar1_block_r(void)
+{
+        return 0x00001704U;
+}
+static inline u32 bus_bar1_block_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 bus_bar1_block_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bar1_block_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 bus_bar1_block_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 bus_bar1_block_mode_virtual_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 bus_bar2_block_r(void)
+{
+        return 0x00001714U;
+}
+static inline u32 bus_bar2_block_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 bus_bar2_block_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bar2_block_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 bus_bar2_block_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 bus_bar2_block_mode_virtual_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 bus_bar1_block_ptr_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 bus_bar2_block_ptr_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 bus_bind_status_r(void)
+{
+        return 0x00001710U;
+}
+static inline u32 bus_bind_status_bar1_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar1_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar1_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 bus_bind_status_bar1_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar1_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar1_outstanding_true_f(void)
+{
+        return 0x2U;
+}
+static inline u32 bus_bind_status_bar2_pending_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar2_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar2_pending_busy_f(void)
+{
+        return 0x4U;
+}
+static inline u32 bus_bind_status_bar2_outstanding_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 bus_bind_status_bar2_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 bus_bind_status_bar2_outstanding_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 bus_intr_0_r(void)
+{
+        return 0x00001100U;
+}
+static inline u32 bus_intr_0_pri_squash_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 bus_intr_0_pri_fecserr_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 bus_intr_0_pri_timeout_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 bus_intr_en_0_r(void)
+{
+        return 0x00001140U;
+}
+static inline u32 bus_intr_en_0_pri_squash_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 bus_intr_en_0_pri_fecserr_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 bus_intr_en_0_pri_timeout_m(void)
+{
+        return 0x1U << 3U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/include/nvgpu/hw/gv100/hw_ccsr_gv100.h
new file mode 100644
index 0000000..b147803
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_ccsr_gv100.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ccsr_gv100_h_
+#define _hw_ccsr_gv100_h_
+
+static inline u32 ccsr_channel_inst_r(u32 i)
+{
+        return 0x00800000U + i*8U;
+}
+static inline u32 ccsr_channel_inst__size_1_v(void)
+{
+        return 0x00001000U;
+}
+static inline u32 ccsr_channel_inst_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 ccsr_channel_inst_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ccsr_channel_inst_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 ccsr_channel_inst_bind_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ccsr_channel_inst_bind_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 ccsr_channel_r(u32 i)
+{
+        return 0x00800004U + i*8U;
+}
+static inline u32 ccsr_channel__size_1_v(void)
+{
+        return 0x00001000U;
+}
+static inline u32 ccsr_channel_enable_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ccsr_channel_enable_set_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
+static inline u32 ccsr_channel_enable_set_true_f(void)
+{
+        return 0x400U;
+}
+static inline u32 ccsr_channel_enable_clr_true_f(void)
+{
+        return 0x800U;
+}
+static inline u32 ccsr_channel_status_v(u32 r)
+{
+        return (r >> 24U) & 0xfU;
+}
+static inline u32 ccsr_channel_status_pending_ctx_reload_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void)
+{
+        return 0x0000000dU;
+}
+static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void)
+{
+        return 0x0000000eU;
+}
+static inline u32 ccsr_channel_next_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 ccsr_channel_next_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ccsr_channel_force_ctx_reload_true_f(void)
+{
+        return 0x100U;
+}
+static inline u32 ccsr_channel_pbdma_faulted_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 ccsr_channel_pbdma_faulted_reset_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 ccsr_channel_eng_faulted_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 ccsr_channel_eng_faulted_v(u32 r)
+{
+        return (r >> 23U) & 0x1U;
+}
+static inline u32 ccsr_channel_eng_faulted_reset_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 ccsr_channel_eng_faulted_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ccsr_channel_busy_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_ce_gv100.h b/include/nvgpu/hw/gv100/hw_ce_gv100.h
new file mode 100644
index 0000000..18b5fc6
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_ce_gv100.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ce_gv100_h_
+#define _hw_ce_gv100_h_
+
+static inline u32 ce_intr_status_r(u32 i)
+{
+        return 0x00104410U + i*128U;
+}
+static inline u32 ce_intr_status_blockpipe_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ce_intr_status_blockpipe_reset_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ce_intr_status_nonblockpipe_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ce_intr_status_nonblockpipe_reset_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ce_intr_status_launcherr_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ce_intr_status_launcherr_reset_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ce_intr_status_invalid_config_pending_f(void)
+{
+        return 0x8U;
+}
+static inline u32 ce_intr_status_invalid_config_reset_f(void)
+{
+        return 0x8U;
+}
+static inline u32 ce_intr_status_mthd_buffer_fault_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 ce_intr_status_mthd_buffer_fault_reset_f(void)
+{
+        return 0x10U;
+}
+static inline u32 ce_pce_map_r(void)
+{
+        return 0x00104028U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h b/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h
new file mode 100644
index 0000000..b7f3df2
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h
@@ -0,0 +1,459 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ctxsw_prog_gv100_h_
+#define _hw_ctxsw_prog_gv100_h_
+
+static inline u32 ctxsw_prog_fecs_header_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ctxsw_prog_main_image_ctl_o(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ctxsw_prog_main_image_ctl_type_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_ctl_type_undefined_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ctxsw_prog_main_image_ctl_type_opengl_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ctxsw_prog_main_image_ctl_type_dx9_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 ctxsw_prog_main_image_ctl_type_dx10_v(void)
+{
+        return 0x00000011U;
+}
+static inline u32 ctxsw_prog_main_image_ctl_type_dx11_v(void)
+{
+        return 0x00000012U;
+}
+static inline u32 ctxsw_prog_main_image_ctl_type_compute_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 ctxsw_prog_main_image_ctl_type_per_veid_header_v(void)
+{
+        return 0x00000021U;
+}
+static inline u32 ctxsw_prog_main_image_patch_count_o(void)
+{
+        return 0x00000010U;
+}
+static inline u32 ctxsw_prog_main_image_context_id_o(void)
+{
+        return 0x000000f0U;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void)
+{
+        return 0x00000014U;
+}
+static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void)
+{
+        return 0x00000018U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_o(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void)
+{
+        return 0x00000020U;
+}
+static inline u32 ctxsw_prog_main_image_pm_o(void)
+{
+        return 0x00000028U;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
+{
+        return 0x7U << 3U;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void)
+{
+        return 0x8U;
+}
+static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_ptr_o(void)
+{
+        return 0x0000002cU;
+}
+static inline u32 ctxsw_prog_main_image_num_save_ops_o(void)
+{
+        return 0x000000f4U;
+}
+static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void)
+{
+        return 0x000000d0U;
+}
+static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void)
+{
+        return 0x000000d4U;
+}
+static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void)
+{
+        return 0x000000d8U;
+}
+static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void)
+{
+        return 0x000000dcU;
+}
+static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void)
+{
+        return 0x000000f8U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_o(void)
+{
+        return 0x00000060U;
+}
+static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void)
+{
+        return 0x00000094U;
+}
+static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void)
+{
+        return 0x00000064U;
+}
+static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_v_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void)
+{
+        return 0x00000068U;
+}
+static inline u32 ctxsw_prog_main_image_full_preemption_ptr_v_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_o(void)
+{
+        return 0x00000070U;
+}
+static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_hi_v_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_o(void)
+{
+        return 0x00000074U;
+}
+static inline u32 ctxsw_prog_main_image_full_preemption_ptr_veid0_v_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_o(void)
+{
+        return 0x00000078U;
+}
+static inline u32 ctxsw_prog_main_image_context_buffer_ptr_hi_v_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_context_buffer_ptr_o(void)
+{
+        return 0x0000007cU;
+}
+static inline u32 ctxsw_prog_main_image_context_buffer_ptr_v_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_o(void)
+{
+        return 0x000000fcU;
+}
+static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void)
+{
+        return 0x600dc0deU;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_o(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_main_image_global_cb_ptr_o(void)
+{
+        return 0x000000b8U;
+}
+static inline u32 ctxsw_prog_main_image_global_cb_ptr_v_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_o(void)
+{
+        return 0x000000bcU;
+}
+static inline u32 ctxsw_prog_main_image_global_cb_ptr_hi_v_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_o(void)
+{
+        return 0x000000c0U;
+}
+static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_v_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_o(void)
+{
+        return 0x000000c4U;
+}
+static inline u32 ctxsw_prog_main_image_global_pagepool_ptr_hi_v_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_control_block_ptr_o(void)
+{
+        return 0x000000c8U;
+}
+static inline u32 ctxsw_prog_main_image_control_block_ptr_v_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_o(void)
+{
+        return 0x000000ccU;
+}
+static inline u32 ctxsw_prog_main_image_control_block_ptr_hi_v_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_o(void)
+{
+        return 0x000000e0U;
+}
+static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_lo_v_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_o(void)
+{
+        return 0x000000e4U;
+}
+static inline u32 ctxsw_prog_main_image_context_ramchain_buffer_addr_hi_v_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_o(void)
+{
+        return 0x000000f4U;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r)
+{
+        return (r >> 16U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_local_image_num_tpcs_o(void)
+{
+        return 0x000000f8U;
+}
+static inline u32 ctxsw_prog_local_magic_value_o(void)
+{
+        return 0x000000fcU;
+}
+static inline u32 ctxsw_prog_local_magic_value_v_value_v(void)
+{
+        return 0xad0becabU;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void)
+{
+        return 0x000000ecU;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void)
+{
+        return 0x000000a0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void)
+{
+        return 2U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void)
+{
+        return 0x000000a4U;
+}
+static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void)
+{
+        return 0x000000a8U;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_o(void)
+{
+        return 0x0000003cU;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void)
+{
+        return 0x00000080U;
+}
+static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void)
+{
+        return 0x00000084U;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void)
+{
+        return 0x2U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_falcon_gv100.h b/include/nvgpu/hw/gv100/hw_falcon_gv100.h
new file mode 100644
index 0000000..3492d68
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_falcon_gv100.h
@@ -0,0 +1,603 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_falcon_gv100_h_
+#define _hw_falcon_gv100_h_
+
+static inline u32 falcon_falcon_irqsset_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 falcon_falcon_irqsset_swgen0_set_f(void)
+{
+        return 0x40U;
+}
+static inline u32 falcon_falcon_irqsclr_r(void)
+{
+        return 0x00000004U;
+}
+static inline u32 falcon_falcon_irqstat_r(void)
+{
+        return 0x00000008U;
+}
+static inline u32 falcon_falcon_irqstat_halt_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 falcon_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 falcon_falcon_irqstat_swgen0_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 falcon_falcon_irqmode_r(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 falcon_falcon_irqmset_r(void)
+{
+        return 0x00000010U;
+}
+static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_irqmset_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_irqmset_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_irqmset_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 falcon_falcon_irqmclr_r(void)
+{
+        return 0x00000014U;
+}
+static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_irqmclr_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 falcon_falcon_irqmclr_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_irqmask_r(void)
+{
+        return 0x00000018U;
+}
+static inline u32 falcon_falcon_irqdest_r(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 19U;
+}
+static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 falcon_falcon_curctx_r(void)
+{
+        return 0x00000050U;
+}
+static inline u32 falcon_falcon_nxtctx_r(void)
+{
+        return 0x00000054U;
+}
+static inline u32 falcon_falcon_mailbox0_r(void)
+{
+        return 0x00000040U;
+}
+static inline u32 falcon_falcon_mailbox1_r(void)
+{
+        return 0x00000044U;
+}
+static inline u32 falcon_falcon_itfen_r(void)
+{
+        return 0x00000048U;
+}
+static inline u32 falcon_falcon_itfen_ctxen_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 falcon_falcon_idlestate_r(void)
+{
+        return 0x0000004cU;
+}
+static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r)
+{
+        return (r >> 1U) & 0x7fffU;
+}
+static inline u32 falcon_falcon_os_r(void)
+{
+        return 0x00000080U;
+}
+static inline u32 falcon_falcon_engctl_r(void)
+{
+        return 0x000000a4U;
+}
+static inline u32 falcon_falcon_cpuctl_r(void)
+{
+        return 0x00000100U;
+}
+static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_cpuctl_sreset_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 falcon_falcon_cpuctl_hreset_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_cpuctl_halt_intr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 falcon_falcon_cpuctl_stopped_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 falcon_falcon_cpuctl_alias_r(void)
+{
+        return 0x00000130U;
+}
+static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 falcon_falcon_imemc_r(u32 i)
+{
+        return 0x00000180U + i*16U;
+}
+static inline u32 falcon_falcon_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 falcon_falcon_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 falcon_falcon_imemc_secure_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 falcon_falcon_imemd_r(u32 i)
+{
+        return 0x00000184U + i*16U;
+}
+static inline u32 falcon_falcon_imemt_r(u32 i)
+{
+        return 0x00000188U + i*16U;
+}
+static inline u32 falcon_falcon_sctl_r(void)
+{
+        return 0x00000240U;
+}
+static inline u32 falcon_falcon_mmu_phys_sec_r(void)
+{
+        return 0x00100ce4U;
+}
+static inline u32 falcon_falcon_bootvec_r(void)
+{
+        return 0x00000104U;
+}
+static inline u32 falcon_falcon_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 falcon_falcon_dmactl_r(void)
+{
+        return 0x0000010cU;
+}
+static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 falcon_falcon_hwcfg_r(void)
+{
+        return 0x00000108U;
+}
+static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r)
+{
+        return (r >> 0U) & 0x1ffU;
+}
+static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r)
+{
+        return (r >> 9U) & 0x1ffU;
+}
+static inline u32 falcon_falcon_dmatrfbase_r(void)
+{
+        return 0x00000110U;
+}
+static inline u32 falcon_falcon_dmatrfbase1_r(void)
+{
+        return 0x00000128U;
+}
+static inline u32 falcon_falcon_dmatrfmoffs_r(void)
+{
+        return 0x00000114U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_r(void)
+{
+        return 0x00000118U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 falcon_falcon_dmatrffboffs_r(void)
+{
+        return 0x0000011cU;
+}
+static inline u32 falcon_falcon_imctl_debug_r(void)
+{
+        return 0x0000015cU;
+}
+static inline u32 falcon_falcon_imctl_debug_addr_blk_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 falcon_falcon_imctl_debug_cmd_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 falcon_falcon_imstat_r(void)
+{
+        return 0x00000144U;
+}
+static inline u32 falcon_falcon_traceidx_r(void)
+{
+        return 0x00000148U;
+}
+static inline u32 falcon_falcon_traceidx_maxidx_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 falcon_falcon_traceidx_idx_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 falcon_falcon_tracepc_r(void)
+{
+        return 0x0000014cU;
+}
+static inline u32 falcon_falcon_tracepc_pc_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 falcon_falcon_exterraddr_r(void)
+{
+        return 0x00000168U;
+}
+static inline u32 falcon_falcon_exterrstat_r(void)
+{
+        return 0x0000016cU;
+}
+static inline u32 falcon_falcon_exterrstat_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 falcon_falcon_exterrstat_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 falcon_falcon_exterrstat_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 falcon_falcon_icd_cmd_r(void)
+{
+        return 0x00000200U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 falcon_falcon_icd_rdata_r(void)
+{
+        return 0x0000020cU;
+}
+static inline u32 falcon_falcon_dmemc_r(u32 i)
+{
+        return 0x000001c0U + i*8U;
+}
+static inline u32 falcon_falcon_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 falcon_falcon_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 falcon_falcon_dmemc_blk_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 falcon_falcon_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 falcon_falcon_dmemc_aincr_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 falcon_falcon_dmemd_r(u32 i)
+{
+        return 0x000001c4U + i*8U;
+}
+static inline u32 falcon_falcon_debug1_r(void)
+{
+        return 0x00000090U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void)
+{
+        return 1U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 falcon_falcon_debuginfo_r(void)
+{
+        return 0x00000094U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_fb_gv100.h b/include/nvgpu/hw/gv100/hw_fb_gv100.h
new file mode 100644
index 0000000..ac248b5
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_fb_gv100.h
@@ -0,0 +1,1923 @@
+/*
+ * Copyright (c) 2017-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fb_gv100_h_
+#define _hw_fb_gv100_h_
+
+static inline u32 fb_fbhub_num_active_ltcs_r(void)
+{
+        return 0x00100800U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_m(void)
+{
+        return 0xffU << 16U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (16U + i*1U);
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_m(u32 i)
+{
+        return 0x1U << (16U + i*1U);
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i)
+{
+        return (r >> (16U + i*1U)) & 0x1U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer___size_1_f(u32 i)
+{
+        return 0x0U << (32U + i*1U);
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_enabled_f(u32 i)
+{
+        return 0x1U << (32U + i*1U);
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_use_nvlink_peer_disabled_f(u32 i)
+{
+        return 0x0U << (32U + i*1U);
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_m(void)
+{
+        return 0x1U << 25U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r)
+{
+        return (r >> 25U) & 0x1U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_fbhub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 fb_mmu_ctrl_r(void)
+{
+        return 0x00100c80U;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_f(u32 v)
+{
+        return (v & 0x3U) << 24U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_m(void)
+{
+        return 0x3U << 24U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_v(u32 r)
+{
+        return (r >> 24U) & 0x3U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_l2_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_atomic_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_atomic_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_rmw_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_power_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 fb_mmu_ctrl_atomic_capability_mode_power_f(void)
+{
+        return 0x3000000U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_r(void)
+{
+        return 0x001fac80U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_f(u32 v)
+{
+        return (v & 0x3U) << 24U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_m(void)
+{
+        return 0x3U << 24U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_v(u32 r)
+{
+        return (r >> 24U) & 0x3U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_l2_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_atomic_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_rmw_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 fb_hsmmu_pri_mmu_ctrl_atomic_capability_mode_power_f(void)
+{
+        return 0x3000000U;
+}
+static inline u32 fb_hsmmu_pri_mmu_debug_ctrl_r(void)
+{
+        return 0x001facc4U;
+}
+static inline u32 fb_hsmmu_pri_mmu_debug_ctrl_debug_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 fb_hsmmu_pri_mmu_debug_ctrl_debug_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 fb_hsmmu_pri_mmu_debug_ctrl_debug_enabled_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 fb_hsmmu_pri_mmu_debug_ctrl_debug_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_hshub_num_active_ltcs_r(void)
+{
+        return 0x001fbc20U;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_m(void)
+{
+        return 0xffU << 16U;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (16U + i*1U);
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_m(u32 i)
+{
+        return 0x1U << (16U + i*1U);
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_v(u32 r, u32 i)
+{
+        return (r >> (16U + i*1U)) & 0x1U;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer___size_1_f(u32 i)
+{
+        return 0x0U << (32U + i*1U);
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_enabled_f(u32 i)
+{
+        return 0x1U << (32U + i*1U);
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_hshub_num_active_ltcs_use_nvlink_peer_disabled_f(u32 i)
+{
+        return 0x0U << (32U + i*1U);
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_m(void)
+{
+        return 0x1U << 25U;
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_v(u32 r)
+{
+        return (r >> 25U) & 0x1U;
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_read_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_hshub_num_active_ltcs_hub_sys_atomic_mode_use_rmw_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 fb_priv_mmu_phy_secure_r(void)
+{
+        return 0x00100ce4U;
+}
+static inline u32 fb_mmu_invalidate_pdb_r(void)
+{
+        return 0x00100cb8U;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_pdb_aperture_sys_mem_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 fb_mmu_invalidate_r(void)
+{
+        return 0x00100cbcU;
+}
+static inline u32 fb_mmu_invalidate_all_va_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_mmu_invalidate_all_pdb_true_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_s(void)
+{
+        return 1U;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 fb_mmu_invalidate_replay_s(void)
+{
+        return 3U;
+}
+static inline u32 fb_mmu_invalidate_replay_f(u32 v)
+{
+        return (v & 0x7U) << 3U;
+}
+static inline u32 fb_mmu_invalidate_replay_m(void)
+{
+        return 0x7U << 3U;
+}
+static inline u32 fb_mmu_invalidate_replay_v(u32 r)
+{
+        return (r >> 3U) & 0x7U;
+}
+static inline u32 fb_mmu_invalidate_replay_none_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_replay_start_f(void)
+{
+        return 0x8U;
+}
+static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void)
+{
+        return 0x10U;
+}
+static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void)
+{
+        return 0x20U;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_s(void)
+{
+        return 1U;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 fb_mmu_invalidate_sys_membar_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 fb_mmu_invalidate_ack_s(void)
+{
+        return 2U;
+}
+static inline u32 fb_mmu_invalidate_ack_f(u32 v)
+{
+        return (v & 0x3U) << 7U;
+}
+static inline u32 fb_mmu_invalidate_ack_m(void)
+{
+        return 0x3U << 7U;
+}
+static inline u32 fb_mmu_invalidate_ack_v(u32 r)
+{
+        return (r >> 7U) & 0x3U;
+}
+static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void)
+{
+        return 0x100U;
+}
+static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void)
+{
+        return 0x80U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_s(void)
+{
+        return 6U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v)
+{
+        return (v & 0x3fU) << 9U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_m(void)
+{
+        return 0x3fU << 9U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r)
+{
+        return (r >> 9U) & 0x3fU;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void)
+{
+        return 5U;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v)
+{
+        return (v & 0x1fU) << 15U;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void)
+{
+        return 0x1fU << 15U;
+}
+static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r)
+{
+        return (r >> 15U) & 0x1fU;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_s(void)
+{
+        return 1U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void)
+{
+        return 3U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void)
+{
+        return 0x7U << 24U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r)
+{
+        return (r >> 24U) & 0x7U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void)
+{
+        return 0x3000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void)
+{
+        return 0x4000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void)
+{
+        return 0x5000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void)
+{
+        return 0x6000000U;
+}
+static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void)
+{
+        return 0x7000000U;
+}
+static inline u32 fb_mmu_invalidate_trigger_s(void)
+{
+        return 1U;
+}
+static inline u32 fb_mmu_invalidate_trigger_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 fb_mmu_invalidate_trigger_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 fb_mmu_invalidate_trigger_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 fb_mmu_invalidate_trigger_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fb_mmu_debug_wr_r(void)
+{
+        return 0x00100cc8U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_s(void)
+{
+        return 2U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_debug_wr_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 fb_mmu_debug_wr_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_debug_wr_vol_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 fb_mmu_debug_wr_addr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 fb_mmu_debug_wr_addr_alignment_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fb_mmu_debug_rd_r(void)
+{
+        return 0x00100cccU;
+}
+static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_debug_rd_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 fb_mmu_debug_rd_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_debug_rd_addr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 fb_mmu_debug_rd_addr_alignment_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fb_mmu_debug_ctrl_r(void)
+{
+        return 0x00100cc4U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_enabled_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_mmu_debug_ctrl_debug_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_niso_cfg1_r(void)
+{
+        return 0x00100c14U;
+}
+static inline u32 fb_niso_cfg1_sysmem_nvlink_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 fb_niso_cfg1_sysmem_nvlink_m(void)
+{
+        return 0x1U << 17U;
+}
+static inline u32 fb_niso_cfg1_sysmem_nvlink_v(u32 r)
+{
+        return (r >> 17U) & 0x1U;
+}
+static inline u32 fb_niso_cfg1_sysmem_nvlink_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_niso_cfg1_sysmem_nvlink_enabled_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 fb_niso_flush_sysmem_addr_r(void)
+{
+        return 0x00100c10U;
+}
+static inline u32 fb_niso_intr_r(void)
+{
+        return 0x00100a20U;
+}
+static inline u32 fb_niso_intr_hub_access_counter_notify_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 fb_niso_intr_hub_access_counter_notify_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_niso_intr_hub_access_counter_error_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 fb_niso_intr_hub_access_counter_error_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_niso_intr_mmu_replayable_fault_notify_m(void)
+{
+        return 0x1U << 27U;
+}
+static inline u32 fb_niso_intr_mmu_replayable_fault_notify_pending_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_m(void)
+{
+        return 0x1U << 28U;
+}
+static inline u32 fb_niso_intr_mmu_replayable_fault_overflow_pending_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_m(void)
+{
+        return 0x1U << 29U;
+}
+static inline u32 fb_niso_intr_mmu_nonreplayable_fault_notify_pending_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 fb_niso_intr_mmu_nonreplayable_fault_overflow_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 fb_niso_intr_mmu_other_fault_notify_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 fb_niso_intr_mmu_other_fault_notify_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fb_niso_intr_en_r(u32 i)
+{
+        return 0x00100a24U + i*4U;
+}
+static inline u32 fb_niso_intr_en__size_1_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_niso_intr_en_hub_access_counter_notify_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 fb_niso_intr_en_hub_access_counter_notify_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_niso_intr_en_hub_access_counter_error_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 fb_niso_intr_en_hub_access_counter_error_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_f(u32 v)
+{
+        return (v & 0x1U) << 27U;
+}
+static inline u32 fb_niso_intr_en_mmu_replayable_fault_notify_enabled_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 fb_niso_intr_en_mmu_replayable_fault_overflow_enabled_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_f(u32 v)
+{
+        return (v & 0x1U) << 29U;
+}
+static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_notify_enabled_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 fb_niso_intr_en_mmu_nonreplayable_fault_overflow_enabled_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 fb_niso_intr_en_mmu_other_fault_notify_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 fb_niso_intr_en_mmu_other_fault_notify_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fb_niso_intr_en_set_r(u32 i)
+{
+        return 0x00100a2cU + i*4U;
+}
+static inline u32 fb_niso_intr_en_set__size_1_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 fb_niso_intr_en_set_hub_access_counter_notify_set_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_niso_intr_en_set_hub_access_counter_error_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 fb_niso_intr_en_set_hub_access_counter_error_set_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_m(void)
+{
+        return 0x1U << 27U;
+}
+static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_notify_set_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_m(void)
+{
+        return 0x1U << 28U;
+}
+static inline u32 fb_niso_intr_en_set_mmu_replayable_fault_overflow_set_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_m(void)
+{
+        return 0x1U << 29U;
+}
+static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_notify_set_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 fb_niso_intr_en_set_mmu_nonreplayable_fault_overflow_set_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 fb_niso_intr_en_set_mmu_other_fault_notify_set_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fb_niso_intr_en_clr_r(u32 i)
+{
+        return 0x00100a34U + i*4U;
+}
+static inline u32 fb_niso_intr_en_clr__size_1_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 fb_niso_intr_en_clr_hub_access_counter_notify_set_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 fb_niso_intr_en_clr_hub_access_counter_error_set_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_m(void)
+{
+        return 0x1U << 27U;
+}
+static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_notify_set_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_m(void)
+{
+        return 0x1U << 28U;
+}
+static inline u32 fb_niso_intr_en_clr_mmu_replayable_fault_overflow_set_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_m(void)
+{
+        return 0x1U << 29U;
+}
+static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_notify_set_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 fb_niso_intr_en_clr_mmu_nonreplayable_fault_overflow_set_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 fb_niso_intr_en_clr_mmu_other_fault_notify_set_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fb_niso_intr_en_clr_mmu_non_replay_fault_buffer_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_niso_intr_en_clr_mmu_replay_fault_buffer_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_r(u32 i)
+{
+        return 0x00100e24U + i*20U;
+}
+static inline u32 fb_mmu_fault_buffer_lo__size_1_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_addr_mode_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_addr_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_addr_mode_virtual_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_addr_mode_physical_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_f(u32 v)
+{
+        return (v & 0x3U) << 1U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_v(u32 r)
+{
+        return (r >> 1U) & 0x3U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_coh_f(void)
+{
+        return 0x4U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_phys_aperture_sys_nocoh_f(void)
+{
+        return 0x6U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_phys_vol_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_phys_vol_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_addr_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 fb_mmu_fault_buffer_lo_addr_v(u32 r)
+{
+        return (r >> 12U) & 0xfffffU;
+}
+static inline u32 fb_mmu_fault_buffer_hi_r(u32 i)
+{
+        return 0x00100e28U + i*20U;
+}
+static inline u32 fb_mmu_fault_buffer_hi__size_1_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_mmu_fault_buffer_hi_addr_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 fb_mmu_fault_buffer_hi_addr_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 fb_mmu_fault_buffer_get_r(u32 i)
+{
+        return 0x00100e2cU + i*20U;
+}
+static inline u32 fb_mmu_fault_buffer_get__size_1_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_mmu_fault_buffer_get_ptr_f(u32 v)
+{
+        return (v & 0xfffffU) << 0U;
+}
+static inline u32 fb_mmu_fault_buffer_get_ptr_m(void)
+{
+        return 0xfffffU << 0U;
+}
+static inline u32 fb_mmu_fault_buffer_get_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffU;
+}
+static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_buffer_get_getptr_corrupted_clear_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 fb_mmu_fault_buffer_get_overflow_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 fb_mmu_fault_buffer_get_overflow_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 fb_mmu_fault_buffer_get_overflow_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_buffer_get_overflow_clear_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fb_mmu_fault_buffer_put_r(u32 i)
+{
+        return 0x00100e30U + i*20U;
+}
+static inline u32 fb_mmu_fault_buffer_put__size_1_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_mmu_fault_buffer_put_ptr_f(u32 v)
+{
+        return (v & 0xfffffU) << 0U;
+}
+static inline u32 fb_mmu_fault_buffer_put_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffU;
+}
+static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_yes_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fb_mmu_fault_buffer_put_getptr_corrupted_no_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_fault_buffer_put_overflow_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 fb_mmu_fault_buffer_put_overflow_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 fb_mmu_fault_buffer_put_overflow_yes_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_buffer_put_overflow_yes_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fb_mmu_fault_buffer_size_r(u32 i)
+{
+        return 0x00100e34U + i*20U;
+}
+static inline u32 fb_mmu_fault_buffer_size__size_1_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_mmu_fault_buffer_size_val_f(u32 v)
+{
+        return (v & 0xfffffU) << 0U;
+}
+static inline u32 fb_mmu_fault_buffer_size_val_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffU;
+}
+static inline u32 fb_mmu_fault_buffer_size_overflow_intr_f(u32 v)
+{
+        return (v & 0x1U) << 29U;
+}
+static inline u32 fb_mmu_fault_buffer_size_overflow_intr_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_buffer_size_overflow_intr_enable_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 fb_mmu_fault_buffer_size_set_default_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 fb_mmu_fault_buffer_size_set_default_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 fb_mmu_fault_buffer_size_set_default_yes_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_buffer_size_set_default_yes_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 fb_mmu_fault_buffer_size_enable_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 fb_mmu_fault_buffer_size_enable_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 fb_mmu_fault_buffer_size_enable_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 fb_mmu_fault_buffer_size_enable_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_buffer_size_enable_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fb_mmu_fault_addr_lo_r(void)
+{
+        return 0x00100e4cU;
+}
+static inline u32 fb_mmu_fault_addr_lo_phys_aperture_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 fb_mmu_fault_addr_lo_phys_aperture_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 fb_mmu_fault_addr_lo_phys_aperture_sys_nocoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 fb_mmu_fault_addr_lo_addr_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 fb_mmu_fault_addr_lo_addr_v(u32 r)
+{
+        return (r >> 12U) & 0xfffffU;
+}
+static inline u32 fb_mmu_fault_addr_hi_r(void)
+{
+        return 0x00100e50U;
+}
+static inline u32 fb_mmu_fault_addr_hi_addr_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 fb_mmu_fault_addr_hi_addr_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 fb_mmu_fault_inst_lo_r(void)
+{
+        return 0x00100e54U;
+}
+static inline u32 fb_mmu_fault_inst_lo_engine_id_v(u32 r)
+{
+        return (r >> 0U) & 0x1ffU;
+}
+static inline u32 fb_mmu_fault_inst_lo_aperture_v(u32 r)
+{
+        return (r >> 10U) & 0x3U;
+}
+static inline u32 fb_mmu_fault_inst_lo_aperture_sys_coh_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 fb_mmu_fault_inst_lo_aperture_sys_nocoh_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 fb_mmu_fault_inst_lo_addr_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 fb_mmu_fault_inst_lo_addr_v(u32 r)
+{
+        return (r >> 12U) & 0xfffffU;
+}
+static inline u32 fb_mmu_fault_inst_hi_r(void)
+{
+        return 0x00100e58U;
+}
+static inline u32 fb_mmu_fault_inst_hi_addr_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 fb_mmu_fault_info_r(void)
+{
+        return 0x00100e5cU;
+}
+static inline u32 fb_mmu_fault_info_fault_type_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 fb_mmu_fault_info_replayable_fault_v(u32 r)
+{
+        return (r >> 7U) & 0x1U;
+}
+static inline u32 fb_mmu_fault_info_client_v(u32 r)
+{
+        return (r >> 8U) & 0x7fU;
+}
+static inline u32 fb_mmu_fault_info_access_type_v(u32 r)
+{
+        return (r >> 16U) & 0xfU;
+}
+static inline u32 fb_mmu_fault_info_client_type_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 fb_mmu_fault_info_gpc_id_v(u32 r)
+{
+        return (r >> 24U) & 0x1fU;
+}
+static inline u32 fb_mmu_fault_info_protected_mode_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 fb_mmu_fault_info_replayable_fault_en_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 fb_mmu_fault_info_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 fb_mmu_fault_status_r(void)
+{
+        return 0x00100e60U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar1_phys_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar1_phys_set_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar1_phys_clear_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar1_virt_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar1_virt_set_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar1_virt_clear_f(void)
+{
+        return 0x2U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar2_phys_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar2_phys_set_f(void)
+{
+        return 0x4U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar2_phys_clear_f(void)
+{
+        return 0x4U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar2_virt_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar2_virt_set_f(void)
+{
+        return 0x8U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_bar2_virt_clear_f(void)
+{
+        return 0x8U;
+}
+static inline u32 fb_mmu_fault_status_dropped_ifb_phys_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_ifb_phys_set_f(void)
+{
+        return 0x10U;
+}
+static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_ifb_phys_clear_f(void)
+{
+        return 0x10U;
+}
+static inline u32 fb_mmu_fault_status_dropped_ifb_virt_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_ifb_virt_set_f(void)
+{
+        return 0x20U;
+}
+static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_ifb_virt_clear_f(void)
+{
+        return 0x20U;
+}
+static inline u32 fb_mmu_fault_status_dropped_other_phys_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 fb_mmu_fault_status_dropped_other_phys_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_other_phys_set_f(void)
+{
+        return 0x40U;
+}
+static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_other_phys_clear_f(void)
+{
+        return 0x40U;
+}
+static inline u32 fb_mmu_fault_status_dropped_other_virt_m(void)
+{
+        return 0x1U << 7U;
+}
+static inline u32 fb_mmu_fault_status_dropped_other_virt_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_other_virt_set_f(void)
+{
+        return 0x80U;
+}
+static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_dropped_other_virt_clear_f(void)
+{
+        return 0x80U;
+}
+static inline u32 fb_mmu_fault_status_replayable_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 fb_mmu_fault_status_replayable_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_replayable_set_f(void)
+{
+        return 0x100U;
+}
+static inline u32 fb_mmu_fault_status_replayable_reset_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_fault_status_non_replayable_m(void)
+{
+        return 0x1U << 9U;
+}
+static inline u32 fb_mmu_fault_status_non_replayable_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_non_replayable_set_f(void)
+{
+        return 0x200U;
+}
+static inline u32 fb_mmu_fault_status_non_replayable_reset_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_fault_status_replayable_error_m(void)
+{
+        return 0x1U << 10U;
+}
+static inline u32 fb_mmu_fault_status_replayable_error_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_replayable_error_set_f(void)
+{
+        return 0x400U;
+}
+static inline u32 fb_mmu_fault_status_replayable_error_reset_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_fault_status_non_replayable_error_m(void)
+{
+        return 0x1U << 11U;
+}
+static inline u32 fb_mmu_fault_status_non_replayable_error_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_non_replayable_error_set_f(void)
+{
+        return 0x800U;
+}
+static inline u32 fb_mmu_fault_status_non_replayable_error_reset_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_fault_status_replayable_overflow_m(void)
+{
+        return 0x1U << 12U;
+}
+static inline u32 fb_mmu_fault_status_replayable_overflow_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_replayable_overflow_set_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 fb_mmu_fault_status_replayable_overflow_reset_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_fault_status_non_replayable_overflow_m(void)
+{
+        return 0x1U << 13U;
+}
+static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_non_replayable_overflow_set_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 fb_mmu_fault_status_non_replayable_overflow_reset_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_m(void)
+{
+        return 0x1U << 14U;
+}
+static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_replayable_getptr_corrupted_set_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_m(void)
+{
+        return 0x1U << 15U;
+}
+static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_non_replayable_getptr_corrupted_set_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 fb_mmu_fault_status_busy_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 fb_mmu_fault_status_busy_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_busy_true_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 fb_mmu_fault_status_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 fb_mmu_fault_status_valid_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_valid_set_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fb_mmu_fault_status_valid_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fb_mmu_fault_status_valid_clear_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fb_mmu_local_memory_range_r(void)
+{
+        return 0x00100ce0U;
+}
+static inline u32 fb_mmu_local_memory_range_lower_scale_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 fb_mmu_local_memory_range_lower_mag_v(u32 r)
+{
+        return (r >> 4U) & 0x3fU;
+}
+static inline u32 fb_mmu_local_memory_range_ecc_mode_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 fb_niso_scrub_status_r(void)
+{
+        return 0x00100b20U;
+}
+static inline u32 fb_niso_scrub_status_flag_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 fb_mmu_priv_level_mask_r(void)
+{
+        return 0x00100cdcU;
+}
+static inline u32 fb_mmu_priv_level_mask_write_violation_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 fb_mmu_priv_level_mask_write_violation_m(void)
+{
+        return 0x1U << 7U;
+}
+static inline u32 fb_mmu_priv_level_mask_write_violation_v(u32 r)
+{
+        return (r >> 7U) & 0x1U;
+}
+static inline u32 fb_hshub_config0_r(void)
+{
+        return 0x001fbc00U;
+}
+static inline u32 fb_hshub_config0_sysmem_nvlink_mask_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 fb_hshub_config0_sysmem_nvlink_mask_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 fb_hshub_config0_sysmem_nvlink_mask_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 fb_hshub_config0_peer_pcie_mask_f(u32 v)
+{
+        return (v & 0xffffU) << 16U;
+}
+static inline u32 fb_hshub_config0_peer_pcie_mask_v(u32 r)
+{
+        return (r >> 16U) & 0xffffU;
+}
+static inline u32 fb_hshub_config1_r(void)
+{
+        return 0x001fbc04U;
+}
+static inline u32 fb_hshub_config1_peer_0_nvlink_mask_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 fb_hshub_config1_peer_0_nvlink_mask_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 fb_hshub_config1_peer_1_nvlink_mask_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 fb_hshub_config1_peer_1_nvlink_mask_v(u32 r)
+{
+        return (r >> 8U) & 0xffU;
+}
+static inline u32 fb_hshub_config1_peer_2_nvlink_mask_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 fb_hshub_config1_peer_2_nvlink_mask_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 fb_hshub_config1_peer_3_nvlink_mask_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 fb_hshub_config1_peer_3_nvlink_mask_v(u32 r)
+{
+        return (r >> 24U) & 0xffU;
+}
+static inline u32 fb_hshub_config2_r(void)
+{
+        return 0x001fbc08U;
+}
+static inline u32 fb_hshub_config2_peer_4_nvlink_mask_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 fb_hshub_config2_peer_4_nvlink_mask_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 fb_hshub_config2_peer_5_nvlink_mask_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 fb_hshub_config2_peer_5_nvlink_mask_v(u32 r)
+{
+        return (r >> 8U) & 0xffU;
+}
+static inline u32 fb_hshub_config2_peer_6_nvlink_mask_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 fb_hshub_config2_peer_6_nvlink_mask_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 fb_hshub_config2_peer_7_nvlink_mask_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 fb_hshub_config2_peer_7_nvlink_mask_v(u32 r)
+{
+        return (r >> 24U) & 0xffU;
+}
+static inline u32 fb_hshub_config6_r(void)
+{
+        return 0x001fbc18U;
+}
+static inline u32 fb_hshub_config7_r(void)
+{
+        return 0x001fbc1cU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_0_physical_portmap_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_0_physical_portmap_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_1_physical_portmap_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_1_physical_portmap_v(u32 r)
+{
+        return (r >> 4U) & 0xfU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_2_physical_portmap_f(u32 v)
+{
+        return (v & 0xfU) << 8U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_2_physical_portmap_v(u32 r)
+{
+        return (r >> 8U) & 0xfU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_3_physical_portmap_f(u32 v)
+{
+        return (v & 0xfU) << 12U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_3_physical_portmap_v(u32 r)
+{
+        return (r >> 12U) & 0xfU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_4_physical_portmap_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_4_physical_portmap_v(u32 r)
+{
+        return (r >> 16U) & 0xfU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_5_physical_portmap_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_5_physical_portmap_v(u32 r)
+{
+        return (r >> 20U) & 0xfU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_6_physical_portmap_f(u32 v)
+{
+        return (v & 0xfU) << 24U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_6_physical_portmap_v(u32 r)
+{
+        return (r >> 24U) & 0xfU;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_7_physical_portmap_f(u32 v)
+{
+        return (v & 0xfU) << 28U;
+}
+static inline u32 fb_hshub_config7_nvlink_logical_7_physical_portmap_v(u32 r)
+{
+        return (r >> 28U) & 0xfU;
+}
+static inline u32 fb_hshub_nvl_cfg_priv_level_mask_r(void)
+{
+        return 0x001fbc50U;
+}
+static inline u32 fb_hshub_nvl_cfg_priv_level_mask_write_protection_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 fb_hshub_nvl_cfg_priv_level_mask_write_protection_v(u32 r)
+{
+        return (r >> 4U) & 0x7U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_fifo_gv100.h b/include/nvgpu/hw/gv100/hw_fifo_gv100.h
new file mode 100644
index 0000000..4e9b590
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_fifo_gv100.h
@@ -0,0 +1,531 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fifo_gv100_h_
+#define _hw_fifo_gv100_h_
+
+static inline u32 fifo_bar1_base_r(void)
+{
+        return 0x00002254U;
+}
+static inline u32 fifo_bar1_base_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 fifo_bar1_base_ptr_align_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 fifo_bar1_base_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_bar1_base_valid_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fifo_userd_writeback_r(void)
+{
+        return 0x0000225cU;
+}
+static inline u32 fifo_userd_writeback_timer_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 fifo_userd_writeback_timer_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_userd_writeback_timer_shorter_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 fifo_userd_writeback_timer_100us_v(void)
+{
+        return 0x00000064U;
+}
+static inline u32 fifo_userd_writeback_timescale_f(u32 v)
+{
+        return (v & 0xfU) << 12U;
+}
+static inline u32 fifo_userd_writeback_timescale_0_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_runlist_base_r(void)
+{
+        return 0x00002270U;
+}
+static inline u32 fifo_runlist_base_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 fifo_runlist_base_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 fifo_runlist_r(void)
+{
+        return 0x00002274U;
+}
+static inline u32 fifo_runlist_engine_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 fifo_eng_runlist_base_r(u32 i)
+{
+        return 0x00002280U + i*8U;
+}
+static inline u32 fifo_eng_runlist_base__size_1_v(void)
+{
+        return 0x0000000dU;
+}
+static inline u32 fifo_eng_runlist_r(u32 i)
+{
+        return 0x00002284U + i*8U;
+}
+static inline u32 fifo_eng_runlist__size_1_v(void)
+{
+        return 0x0000000dU;
+}
+static inline u32 fifo_eng_runlist_length_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 fifo_eng_runlist_length_max_v(void)
+{
+        return 0x0000ffffU;
+}
+static inline u32 fifo_eng_runlist_pending_true_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 fifo_pb_timeslice_r(u32 i)
+{
+        return 0x00002350U + i*4U;
+}
+static inline u32 fifo_pb_timeslice_timeout_16_f(void)
+{
+        return 0x10U;
+}
+static inline u32 fifo_pb_timeslice_timescale_0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_pb_timeslice_enable_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 fifo_pbdma_map_r(u32 i)
+{
+        return 0x00002390U + i*4U;
+}
+static inline u32 fifo_intr_0_r(void)
+{
+        return 0x00002100U;
+}
+static inline u32 fifo_intr_0_bind_error_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fifo_intr_0_bind_error_reset_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fifo_intr_0_sched_error_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 fifo_intr_0_sched_error_reset_f(void)
+{
+        return 0x100U;
+}
+static inline u32 fifo_intr_0_chsw_error_pending_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 fifo_intr_0_chsw_error_reset_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 fifo_intr_0_memop_timeout_pending_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 fifo_intr_0_memop_timeout_reset_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 fifo_intr_0_lb_error_pending_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fifo_intr_0_lb_error_reset_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fifo_intr_0_pbdma_intr_pending_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 fifo_intr_0_runlist_event_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 fifo_intr_0_channel_intr_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 fifo_intr_en_0_r(void)
+{
+        return 0x00002140U;
+}
+static inline u32 fifo_intr_en_0_sched_error_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 fifo_intr_en_0_sched_error_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 fifo_intr_en_1_r(void)
+{
+        return 0x00002528U;
+}
+static inline u32 fifo_intr_bind_error_r(void)
+{
+        return 0x0000252cU;
+}
+static inline u32 fifo_intr_sched_error_r(void)
+{
+        return 0x0000254cU;
+}
+static inline u32 fifo_intr_sched_error_code_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 fifo_intr_chsw_error_r(void)
+{
+        return 0x0000256cU;
+}
+static inline u32 fifo_intr_pbdma_id_r(void)
+{
+        return 0x000025a0U;
+}
+static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i)
+{
+        return (r >> (0U + i*1U)) & 0x1U;
+}
+static inline u32 fifo_intr_pbdma_id_status__size_1_v(void)
+{
+        return 0x0000000eU;
+}
+static inline u32 fifo_intr_runlist_r(void)
+{
+        return 0x00002a00U;
+}
+static inline u32 fifo_fb_timeout_r(void)
+{
+        return 0x00002a04U;
+}
+static inline u32 fifo_fb_timeout_period_m(void)
+{
+        return 0x3fffffffU << 0U;
+}
+static inline u32 fifo_fb_timeout_period_max_f(void)
+{
+        return 0x3fffffffU;
+}
+static inline u32 fifo_fb_timeout_period_init_f(void)
+{
+        return 0x3c00U;
+}
+static inline u32 fifo_sched_disable_r(void)
+{
+        return 0x00002630U;
+}
+static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+static inline u32 fifo_sched_disable_runlist_m(u32 i)
+{
+        return 0x1U << (0U + i*1U);
+}
+static inline u32 fifo_sched_disable_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_runlist_preempt_r(void)
+{
+        return 0x00002638U;
+}
+static inline u32 fifo_runlist_preempt_runlist_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+static inline u32 fifo_runlist_preempt_runlist_m(u32 i)
+{
+        return 0x1U << (0U + i*1U);
+}
+static inline u32 fifo_runlist_preempt_runlist_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_preempt_r(void)
+{
+        return 0x00002634U;
+}
+static inline u32 fifo_preempt_pending_true_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 fifo_preempt_type_channel_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fifo_preempt_type_tsg_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 fifo_preempt_chid_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 fifo_preempt_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 fifo_engine_status_r(u32 i)
+{
+        return 0x00002640U + i*8U;
+}
+static inline u32 fifo_engine_status__size_1_v(void)
+{
+        return 0x0000000fU;
+}
+static inline u32 fifo_engine_status_id_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 fifo_engine_status_id_type_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 fifo_engine_status_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_id_type_tsgid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctx_status_v(u32 r)
+{
+        return (r >> 13U) & 0x7U;
+}
+static inline u32 fifo_engine_status_ctx_status_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 fifo_engine_status_next_id_v(u32 r)
+{
+        return (r >> 16U) & 0xfffU;
+}
+static inline u32 fifo_engine_status_next_id_type_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 fifo_engine_status_next_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_eng_reload_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 fifo_engine_status_faulted_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 fifo_engine_status_faulted_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_engine_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 fifo_engine_status_engine_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_engine_status_engine_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctxsw_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_engine_status_ctxsw_in_progress_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 fifo_pbdma_status_r(u32 i)
+{
+        return 0x00003080U + i*4U;
+}
+static inline u32 fifo_pbdma_status__size_1_v(void)
+{
+        return 0x0000000eU;
+}
+static inline u32 fifo_pbdma_status_id_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 fifo_pbdma_status_id_type_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 fifo_pbdma_status_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_pbdma_status_id_type_tsgid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_pbdma_status_chan_status_v(u32 r)
+{
+        return (r >> 13U) & 0x7U;
+}
+static inline u32 fifo_pbdma_status_chan_status_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 fifo_pbdma_status_next_id_v(u32 r)
+{
+        return (r >> 16U) & 0xfffU;
+}
+static inline u32 fifo_pbdma_status_next_id_type_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 fifo_pbdma_status_next_id_type_chid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 fifo_pbdma_status_chsw_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 fifo_pbdma_status_chsw_in_progress_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 fifo_cfg0_r(void)
+{
+        return 0x00002004U;
+}
+static inline u32 fifo_cfg0_num_pbdma_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 fifo_cfg0_pbdma_fault_id_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_flush_gv100.h b/include/nvgpu/hw/gv100/hw_flush_gv100.h
new file mode 100644
index 0000000..b604562
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_flush_gv100.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_flush_gv100_h_
+#define _hw_flush_gv100_h_
+
+static inline u32 flush_l2_system_invalidate_r(void)
+{
+        return 0x00070004U;
+}
+static inline u32 flush_l2_system_invalidate_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_system_invalidate_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_l2_system_invalidate_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_flush_dirty_r(void)
+{
+        return 0x00070010U;
+}
+static inline u32 flush_l2_flush_dirty_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_flush_dirty_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_flush_dirty_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_flush_dirty_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_clean_comptags_r(void)
+{
+        return 0x0007000cU;
+}
+static inline u32 flush_l2_clean_comptags_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_clean_comptags_pending_empty_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_l2_clean_comptags_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 flush_l2_clean_comptags_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_fb_flush_r(void)
+{
+        return 0x00070000U;
+}
+static inline u32 flush_fb_flush_pending_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 flush_fb_flush_pending_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 flush_fb_flush_pending_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 flush_fb_flush_outstanding_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 flush_fb_flush_outstanding_true_v(void)
+{
+        return 0x00000001U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_fuse_gv100.h b/include/nvgpu/hw/gv100/hw_fuse_gv100.h
new file mode 100644
index 0000000..48194ea
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_fuse_gv100.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_fuse_gv100_h_
+#define _hw_fuse_gv100_h_
+
+static inline u32 fuse_status_opt_gpc_r(void)
+{
+        return 0x00021c1cU;
+}
+static inline u32 fuse_status_opt_tpc_gpc_r(u32 i)
+{
+        return 0x00021c38U + i*4U;
+}
+static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i)
+{
+        return 0x00021838U + i*4U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void)
+{
+        return 0x00021944U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void)
+{
+        return 0x00021948U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void)
+{
+        return 0x1U;
+}
+static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void)
+{
+        return 0x0U;
+}
+static inline u32 fuse_status_opt_fbio_r(void)
+{
+        return 0x00021c14U;
+}
+static inline u32 fuse_status_opt_fbio_data_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 fuse_status_opt_fbio_data_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 fuse_status_opt_fbio_data_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i)
+{
+        return 0x00021d70U + i*4U;
+}
+static inline u32 fuse_status_opt_fbp_r(void)
+{
+        return 0x00021d38U;
+}
+static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i)
+{
+        return (r >> (0U + i*1U)) & 0x1U;
+}
+static inline u32 fuse_opt_ecc_en_r(void)
+{
+        return 0x00021228U;
+}
+static inline u32 fuse_opt_feature_fuses_override_disable_r(void)
+{
+        return 0x000213f0U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_gmmu_gv100.h b/include/nvgpu/hw/gv100/hw_gmmu_gv100.h
new file mode 100644
index 0000000..8cccfa9
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_gmmu_gv100.h
@@ -0,0 +1,355 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gmmu_gv100_h_
+#define _hw_gmmu_gv100_h_
+
+static inline u32 gmmu_new_pde_is_pte_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pde_is_pte_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pde_aperture_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pde_aperture_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pde_aperture_video_memory_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gmmu_new_pde_aperture_sys_mem_coh_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_new_pde_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x6U;
+}
+static inline u32 gmmu_new_pde_address_sys_f(u32 v)
+{
+        return (v & 0xffffffU) << 8U;
+}
+static inline u32 gmmu_new_pde_address_sys_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pde_vol_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pde_vol_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gmmu_new_pde_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pde_address_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_new_pde__size_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_new_dual_pde_is_pte_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_dual_pde_is_pte_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_coh_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_big_sys_mem_ncoh_f(void)
+{
+        return 0x6U;
+}
+static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 gmmu_new_dual_pde_address_big_sys_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_w(void)
+{
+        return 2U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_coh_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_new_dual_pde_aperture_small_sys_mem_ncoh_f(void)
+{
+        return 0x6U;
+}
+static inline u32 gmmu_new_dual_pde_vol_small_w(void)
+{
+        return 2U;
+}
+static inline u32 gmmu_new_dual_pde_vol_small_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gmmu_new_dual_pde_vol_small_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_dual_pde_vol_big_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_dual_pde_vol_big_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gmmu_new_dual_pde_vol_big_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v)
+{
+        return (v & 0xffffffU) << 8U;
+}
+static inline u32 gmmu_new_dual_pde_address_small_sys_w(void)
+{
+        return 2U;
+}
+static inline u32 gmmu_new_dual_pde_address_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_new_dual_pde_address_big_shift_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_new_dual_pde__size_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gmmu_new_pte__size_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gmmu_new_pte_valid_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_valid_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gmmu_new_pte_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pte_privilege_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_privilege_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gmmu_new_pte_privilege_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pte_address_sys_f(u32 v)
+{
+        return (v & 0xffffffU) << 8U;
+}
+static inline u32 gmmu_new_pte_address_sys_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_address_vid_f(u32 v)
+{
+        return (v & 0xffffffU) << 8U;
+}
+static inline u32 gmmu_new_pte_address_vid_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_vol_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_vol_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gmmu_new_pte_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pte_aperture_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_aperture_video_memory_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gmmu_new_pte_aperture_sys_mem_coh_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gmmu_new_pte_aperture_sys_mem_ncoh_f(void)
+{
+        return 0x6U;
+}
+static inline u32 gmmu_new_pte_read_only_w(void)
+{
+        return 0U;
+}
+static inline u32 gmmu_new_pte_read_only_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gmmu_new_pte_comptagline_f(u32 v)
+{
+        return (v & 0x3ffffU) << 4U;
+}
+static inline u32 gmmu_new_pte_comptagline_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_new_pte_kind_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 gmmu_new_pte_kind_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_new_pte_address_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gmmu_pte_kind_f(u32 v)
+{
+        return (v & 0xffU) << 4U;
+}
+static inline u32 gmmu_pte_kind_w(void)
+{
+        return 1U;
+}
+static inline u32 gmmu_pte_kind_invalid_v(void)
+{
+        return 0x000000ffU;
+}
+static inline u32 gmmu_pte_kind_pitch_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gmmu_fault_client_type_gpc_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gmmu_fault_client_type_hub_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gmmu_fault_type_unbound_inst_block_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gmmu_fault_mmu_eng_id_bar2_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 gmmu_fault_mmu_eng_id_physical_v(void)
+{
+        return 0x0000001fU;
+}
+static inline u32 gmmu_fault_mmu_eng_id_ce0_v(void)
+{
+        return 0x0000000fU;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_gr_gv100.h b/include/nvgpu/hw/gv100/hw_gr_gv100.h
new file mode 100644
index 0000000..0f83d6b
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_gr_gv100.h
@@ -0,0 +1,4119 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_gr_gv100_h_
+#define _hw_gr_gv100_h_
+
+static inline u32 gr_intr_r(void)
+{
+        return 0x00400100U;
+}
+static inline u32 gr_intr_notify_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_intr_notify_reset_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_intr_semaphore_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_intr_semaphore_reset_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_intr_illegal_method_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_intr_illegal_method_reset_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_intr_illegal_notify_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_intr_illegal_notify_reset_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_intr_firmware_method_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 gr_intr_firmware_method_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_intr_firmware_method_reset_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_intr_illegal_class_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_intr_illegal_class_reset_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_intr_fecs_error_pending_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_intr_fecs_error_reset_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_intr_class_error_pending_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_intr_class_error_reset_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_intr_exception_pending_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 gr_intr_exception_reset_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 gr_fecs_intr_r(void)
+{
+        return 0x00400144U;
+}
+static inline u32 gr_class_error_r(void)
+{
+        return 0x00400110U;
+}
+static inline u32 gr_class_error_code_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_intr_nonstall_r(void)
+{
+        return 0x00400120U;
+}
+static inline u32 gr_intr_nonstall_trap_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_intr_en_r(void)
+{
+        return 0x0040013cU;
+}
+static inline u32 gr_exception_r(void)
+{
+        return 0x00400108U;
+}
+static inline u32 gr_exception_fe_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_exception_gpc_m(void)
+{
+        return 0x1U << 24U;
+}
+static inline u32 gr_exception_memfmt_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_exception_ds_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_exception_sked_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 gr_exception_pd_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_exception_scc_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 gr_exception_ssync_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 gr_exception_mme_m(void)
+{
+        return 0x1U << 7U;
+}
+static inline u32 gr_exception1_r(void)
+{
+        return 0x00400118U;
+}
+static inline u32 gr_exception1_gpc_0_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_exception2_r(void)
+{
+        return 0x0040011cU;
+}
+static inline u32 gr_exception_en_r(void)
+{
+        return 0x00400138U;
+}
+static inline u32 gr_exception_en_fe_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_exception_en_fe_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_exception_en_gpc_m(void)
+{
+        return 0x1U << 24U;
+}
+static inline u32 gr_exception_en_gpc_enabled_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 gr_exception_en_memfmt_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_exception_en_memfmt_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_exception_en_ds_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_exception_en_ds_enabled_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_exception_en_pd_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_exception_en_pd_enabled_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_exception_en_scc_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 gr_exception_en_scc_enabled_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_exception_en_ssync_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 gr_exception_en_ssync_enabled_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_exception_en_mme_m(void)
+{
+        return 0x1U << 7U;
+}
+static inline u32 gr_exception_en_mme_enabled_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_exception_en_sked_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 gr_exception_en_sked_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_exception1_en_r(void)
+{
+        return 0x00400130U;
+}
+static inline u32 gr_exception2_en_r(void)
+{
+        return 0x00400134U;
+}
+static inline u32 gr_gpfifo_ctl_r(void)
+{
+        return 0x00400500U;
+}
+static inline u32 gr_gpfifo_ctl_access_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpfifo_ctl_access_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpfifo_ctl_access_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_gpfifo_status_r(void)
+{
+        return 0x00400504U;
+}
+static inline u32 gr_trapped_addr_r(void)
+{
+        return 0x00400704U;
+}
+static inline u32 gr_trapped_addr_mthd_v(u32 r)
+{
+        return (r >> 2U) & 0xfffU;
+}
+static inline u32 gr_trapped_addr_subch_v(u32 r)
+{
+        return (r >> 16U) & 0x7U;
+}
+static inline u32 gr_trapped_addr_mme_generated_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 gr_trapped_addr_datahigh_v(u32 r)
+{
+        return (r >> 24U) & 0x1U;
+}
+static inline u32 gr_trapped_addr_priv_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 gr_trapped_addr_status_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_trapped_data_lo_r(void)
+{
+        return 0x00400708U;
+}
+static inline u32 gr_trapped_data_hi_r(void)
+{
+        return 0x0040070cU;
+}
+static inline u32 gr_trapped_data_mme_r(void)
+{
+        return 0x00400710U;
+}
+static inline u32 gr_trapped_data_mme_pc_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 gr_status_r(void)
+{
+        return 0x00400700U;
+}
+static inline u32 gr_status_fe_method_upper_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_status_fe_method_lower_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 gr_status_fe_method_lower_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_status_fe_gi_v(u32 r)
+{
+        return (r >> 21U) & 0x1U;
+}
+static inline u32 gr_status_mask_r(void)
+{
+        return 0x00400610U;
+}
+static inline u32 gr_status_1_r(void)
+{
+        return 0x00400604U;
+}
+static inline u32 gr_status_2_r(void)
+{
+        return 0x00400608U;
+}
+static inline u32 gr_engine_status_r(void)
+{
+        return 0x0040060cU;
+}
+static inline u32 gr_engine_status_value_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_pri_be0_becs_be_exception_r(void)
+{
+        return 0x00410204U;
+}
+static inline u32 gr_pri_be0_becs_be_exception_en_r(void)
+{
+        return 0x00410208U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void)
+{
+        return 0x00502c90U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void)
+{
+        return 0x00502c94U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void)
+{
+        return 0x00504508U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+        return 0x0050450cU;
+}
+static inline u32 gr_activity_0_r(void)
+{
+        return 0x00400380U;
+}
+static inline u32 gr_activity_1_r(void)
+{
+        return 0x00400384U;
+}
+static inline u32 gr_activity_2_r(void)
+{
+        return 0x00400388U;
+}
+static inline u32 gr_activity_4_r(void)
+{
+        return 0x00400390U;
+}
+static inline u32 gr_activity_4_gpc0_s(void)
+{
+        return 3U;
+}
+static inline u32 gr_activity_4_gpc0_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_activity_4_gpc0_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 gr_activity_4_gpc0_v(u32 r)
+{
+        return (r >> 0U) & 0x7U;
+}
+static inline u32 gr_activity_4_gpc0_empty_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_activity_4_gpc0_preempted_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_pri_gpc0_gcc_dbg_r(void)
+{
+        return 0x00501000U;
+}
+static inline u32 gr_pri_gpcs_gcc_dbg_r(void)
+{
+        return 0x00419000U;
+}
+static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void)
+{
+        return 0x0050433cU;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void)
+{
+        return 0x00419b3cU;
+}
+static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_pri_sked_activity_r(void)
+{
+        return 0x00407054U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void)
+{
+        return 0x00502c80U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void)
+{
+        return 0x00502c84U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void)
+{
+        return 0x00502c88U;
+}
+static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void)
+{
+        return 0x00502c8cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00504500U;
+}
+static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00504d00U;
+}
+static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00501d00U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void)
+{
+        return 0x0041ac80U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void)
+{
+        return 0x0041ac84U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void)
+{
+        return 0x0041ac88U;
+}
+static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void)
+{
+        return 0x0041ac8cU;
+}
+static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void)
+{
+        return 0x0041c500U;
+}
+static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void)
+{
+        return 0x0041cd00U;
+}
+static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void)
+{
+        return 0x00419d00U;
+}
+static inline u32 gr_pri_be0_becs_be_activity0_r(void)
+{
+        return 0x00410200U;
+}
+static inline u32 gr_pri_be1_becs_be_activity0_r(void)
+{
+        return 0x00410600U;
+}
+static inline u32 gr_pri_bes_becs_be_activity0_r(void)
+{
+        return 0x00408a00U;
+}
+static inline u32 gr_pri_ds_mpipe_status_r(void)
+{
+        return 0x00405858U;
+}
+static inline u32 gr_pri_fe_go_idle_info_r(void)
+{
+        return 0x00404194U;
+}
+static inline u32 gr_pri_fe_chip_def_info_r(void)
+{
+        return 0x00404030U;
+}
+static inline u32 gr_pri_fe_chip_def_info_max_veid_count_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 gr_pri_fe_chip_def_info_max_veid_count_init_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void)
+{
+        return 0x00504238U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void)
+{
+        return 0x00504358U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void)
+{
+        return 0x1U << 7U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void)
+{
+        return 0x1U << 9U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void)
+{
+        return 0x1U << 10U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void)
+{
+        return 0x1U << 11U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void)
+{
+        return 0x1U << 12U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void)
+{
+        return 0x1U << 13U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void)
+{
+        return 0x1U << 14U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void)
+{
+        return 0x1U << 15U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
+{
+        return (r >> 24U) & 0x1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r)
+{
+        return (r >> 26U) & 0x1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void)
+{
+        return 0x0050435cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void)
+{
+        return 16U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void)
+{
+        return 0x00504360U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void)
+{
+        return 16U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void)
+{
+        return 0x0050436cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
+{
+        return (r >> 8U) & 0x1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r)
+{
+        return (r >> 10U) & 0x1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void)
+{
+        return 0x00504370U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void)
+{
+        return 16U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void)
+{
+        return 0x00504374U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void)
+{
+        return 16U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void)
+{
+        return 0x00504638U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void)
+{
+        return 0x1U << 7U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r)
+{
+        return (r >> 18U) & 0x1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void)
+{
+        return 0x0050463cU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void)
+{
+        return 16U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void)
+{
+        return 0x00504640U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void)
+{
+        return 16U;
+}
+static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void)
+{
+        return 0x005042c4U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpc0_tpc0_mpc_hww_esr_r(void)
+{
+        return 0x00504430U;
+}
+static inline u32 gr_gpc0_tpc0_mpc_hww_esr_reset_trigger_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_r(void)
+{
+        return 0x00504434U;
+}
+static inline u32 gr_gpc0_tpc0_mpc_hww_esr_info_veid_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_pri_be0_crop_status1_r(void)
+{
+        return 0x00410134U;
+}
+static inline u32 gr_pri_bes_crop_status1_r(void)
+{
+        return 0x00408934U;
+}
+static inline u32 gr_pri_be0_zrop_status_r(void)
+{
+        return 0x00410048U;
+}
+static inline u32 gr_pri_be0_zrop_status2_r(void)
+{
+        return 0x0041004cU;
+}
+static inline u32 gr_pri_bes_zrop_status_r(void)
+{
+        return 0x00408848U;
+}
+static inline u32 gr_pri_bes_zrop_status2_r(void)
+{
+        return 0x0040884cU;
+}
+static inline u32 gr_pipe_bundle_address_r(void)
+{
+        return 0x00400200U;
+}
+static inline u32 gr_pipe_bundle_address_value_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_pipe_bundle_address_veid_f(u32 v)
+{
+        return (v & 0x3fU) << 20U;
+}
+static inline u32 gr_pipe_bundle_address_veid_w(void)
+{
+        return 0U;
+}
+static inline u32 gr_pipe_bundle_data_r(void)
+{
+        return 0x00400204U;
+}
+static inline u32 gr_pipe_bundle_config_r(void)
+{
+        return 0x00400208U;
+}
+static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_fe_hww_esr_r(void)
+{
+        return 0x00404000U;
+}
+static inline u32 gr_fe_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_fe_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_fe_hww_esr_info_r(void)
+{
+        return 0x004041b0U;
+}
+static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(void)
+{
+        return 0x00419eacU;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r(void)
+{
+        return 0x0050472cU;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_int_report_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_error_in_trap_report_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_gpcs_tpcs_sms_hww_global_esr_r(void)
+{
+        return 0x00419eb4U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void)
+{
+        return 0x00504734U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_error_in_trap_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_fe_go_idle_timeout_r(void)
+{
+        return 0x00404154U;
+}
+static inline u32 gr_fe_go_idle_timeout_count_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fe_go_idle_timeout_count_prod_f(void)
+{
+        return 0x1800U;
+}
+static inline u32 gr_fe_object_table_r(u32 i)
+{
+        return 0x00404200U + i*4U;
+}
+static inline u32 gr_fe_object_table_nvclass_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_fe_tpc_fs_r(u32 i)
+{
+        return 0x0040a200U + i*4U;
+}
+static inline u32 gr_pri_mme_shadow_raw_index_r(void)
+{
+        return 0x00404488U;
+}
+static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pri_mme_shadow_raw_data_r(void)
+{
+        return 0x0040448cU;
+}
+static inline u32 gr_mme_hww_esr_r(void)
+{
+        return 0x00404490U;
+}
+static inline u32 gr_mme_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_mme_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_mme_hww_esr_info_r(void)
+{
+        return 0x00404494U;
+}
+static inline u32 gr_memfmt_hww_esr_r(void)
+{
+        return 0x00404600U;
+}
+static inline u32 gr_memfmt_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_memfmt_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_fecs_cpuctl_r(void)
+{
+        return 0x00409100U;
+}
+static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_fecs_cpuctl_alias_r(void)
+{
+        return 0x00409130U;
+}
+static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_fecs_dmactl_r(void)
+{
+        return 0x0040910cU;
+}
+static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_fecs_os_r(void)
+{
+        return 0x00409080U;
+}
+static inline u32 gr_fecs_idlestate_r(void)
+{
+        return 0x0040904cU;
+}
+static inline u32 gr_fecs_mailbox0_r(void)
+{
+        return 0x00409040U;
+}
+static inline u32 gr_fecs_mailbox1_r(void)
+{
+        return 0x00409044U;
+}
+static inline u32 gr_fecs_irqstat_r(void)
+{
+        return 0x00409008U;
+}
+static inline u32 gr_fecs_irqmode_r(void)
+{
+        return 0x0040900cU;
+}
+static inline u32 gr_fecs_irqmask_r(void)
+{
+        return 0x00409018U;
+}
+static inline u32 gr_fecs_irqdest_r(void)
+{
+        return 0x0040901cU;
+}
+static inline u32 gr_fecs_curctx_r(void)
+{
+        return 0x00409050U;
+}
+static inline u32 gr_fecs_nxtctx_r(void)
+{
+        return 0x00409054U;
+}
+static inline u32 gr_fecs_engctl_r(void)
+{
+        return 0x004090a4U;
+}
+static inline u32 gr_fecs_debug1_r(void)
+{
+        return 0x00409090U;
+}
+static inline u32 gr_fecs_debuginfo_r(void)
+{
+        return 0x00409094U;
+}
+static inline u32 gr_fecs_icd_cmd_r(void)
+{
+        return 0x00409200U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 gr_fecs_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 gr_fecs_icd_rdata_r(void)
+{
+        return 0x0040920cU;
+}
+static inline u32 gr_fecs_imemc_r(u32 i)
+{
+        return 0x00409180U + i*16U;
+}
+static inline u32 gr_fecs_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_fecs_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_fecs_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_fecs_imemd_r(u32 i)
+{
+        return 0x00409184U + i*16U;
+}
+static inline u32 gr_fecs_imemt_r(u32 i)
+{
+        return 0x00409188U + i*16U;
+}
+static inline u32 gr_fecs_imemt_tag_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_fecs_dmemc_r(u32 i)
+{
+        return 0x004091c0U + i*8U;
+}
+static inline u32 gr_fecs_dmemc_offs_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_fecs_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_fecs_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 gr_fecs_dmemc_offs_v(u32 r)
+{
+        return (r >> 2U) & 0x3fU;
+}
+static inline u32 gr_fecs_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_fecs_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_fecs_dmemd_r(u32 i)
+{
+        return 0x004091c4U + i*8U;
+}
+static inline u32 gr_fecs_dmatrfbase_r(void)
+{
+        return 0x00409110U;
+}
+static inline u32 gr_fecs_dmatrfmoffs_r(void)
+{
+        return 0x00409114U;
+}
+static inline u32 gr_fecs_dmatrffboffs_r(void)
+{
+        return 0x0040911cU;
+}
+static inline u32 gr_fecs_dmatrfcmd_r(void)
+{
+        return 0x00409118U;
+}
+static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_fecs_bootvec_r(void)
+{
+        return 0x00409104U;
+}
+static inline u32 gr_fecs_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_falcon_hwcfg_r(void)
+{
+        return 0x00409108U;
+}
+static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void)
+{
+        return 0x0041a108U;
+}
+static inline u32 gr_fecs_falcon_rm_r(void)
+{
+        return 0x00409084U;
+}
+static inline u32 gr_fecs_current_ctx_r(void)
+{
+        return 0x00409b00U;
+}
+static inline u32 gr_fecs_current_ctx_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_fecs_current_ctx_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 gr_fecs_current_ctx_target_s(void)
+{
+        return 2U;
+}
+static inline u32 gr_fecs_current_ctx_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 gr_fecs_current_ctx_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_fecs_current_ctx_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_current_ctx_target_sys_mem_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 gr_fecs_current_ctx_target_sys_mem_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 gr_fecs_current_ctx_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_current_ctx_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_fecs_current_ctx_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_fecs_current_ctx_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_fecs_current_ctx_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_method_data_r(void)
+{
+        return 0x00409500U;
+}
+static inline u32 gr_fecs_method_push_r(void)
+{
+        return 0x00409504U;
+}
+static inline u32 gr_fecs_method_push_adr_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void)
+{
+        return 0x3U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 gr_fecs_method_push_adr_restore_golden_v(void)
+{
+        return 0x00000015U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void)
+{
+        return 0x00000016U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void)
+{
+        return 0x00000025U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void)
+{
+        return 0x00000030U;
+}
+static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void)
+{
+        return 0x00000031U;
+}
+static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void)
+{
+        return 0x00000032U;
+}
+static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void)
+{
+        return 0x00000038U;
+}
+static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void)
+{
+        return 0x00000039U;
+}
+static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
+{
+        return 0x21U;
+}
+static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void)
+{
+        return 0x0000001aU;
+}
+static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void)
+{
+        return 0x0000003aU;
+}
+static inline u32 gr_fecs_host_int_status_r(void)
+{
+        return 0x00409c18U;
+}
+static inline u32 gr_fecs_host_int_status_fault_during_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_fecs_host_int_clear_r(void)
+{
+        return 0x00409c20U;
+}
+static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_fecs_host_int_enable_r(void)
+{
+        return 0x00409c24U;
+}
+static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_r(void)
+{
+        return 0x00409614U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void)
+{
+        return 0x1U << 10U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r)
+{
+        return (r >> 10U) & 0x1U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void)
+{
+        return 0x0040960cU;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i)
+{
+        return 0x00409800U + i*4U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i)
+{
+        return 0x004098c0U + i*4U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i)
+{
+        return 0x00409840U + i*4U;
+}
+static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fecs_fs_r(void)
+{
+        return 0x00409604U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_s(void)
+{
+        return 5U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_m(void)
+{
+        return 0x1fU << 0U;
+}
+static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_s(void)
+{
+        return 5U;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_m(void)
+{
+        return 0x1fU << 16U;
+}
+static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r)
+{
+        return (r >> 16U) & 0x1fU;
+}
+static inline u32 gr_fecs_cfg_r(void)
+{
+        return 0x00409620U;
+}
+static inline u32 gr_fecs_cfg_imem_sz_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_fecs_rc_lanes_r(void)
+{
+        return 0x00409880U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_fecs_ctxsw_status_1_r(void)
+{
+        return 0x00409400U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v)
+{
+        return (v & 0x1U) << 12U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void)
+{
+        return 0x1U << 12U;
+}
+static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 gr_fecs_arb_ctx_adr_r(void)
+{
+        return 0x00409a24U;
+}
+static inline u32 gr_fecs_new_ctx_r(void)
+{
+        return 0x00409b04U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_s(void)
+{
+        return 28U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_m(void)
+{
+        return 0xfffffffU << 0U;
+}
+static inline u32 gr_fecs_new_ctx_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 gr_fecs_new_ctx_target_s(void)
+{
+        return 2U;
+}
+static inline u32 gr_fecs_new_ctx_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 gr_fecs_new_ctx_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_fecs_new_ctx_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 gr_fecs_new_ctx_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_fecs_new_ctx_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_fecs_new_ctx_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_fecs_new_ctx_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_r(void)
+{
+        return 0x00409a0cU;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void)
+{
+        return 28U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void)
+{
+        return 0xfffffffU << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r)
+{
+        return (r >> 0U) & 0xfffffffU;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_s(void)
+{
+        return 2U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_r(void)
+{
+        return 0x00409a10U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void)
+{
+        return 5U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void)
+{
+        return 0x1fU << 0U;
+}
+static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 gr_fecs_ctxsw_status_fe_0_r(void)
+{
+        return 0x00409c00U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void)
+{
+        return 0x00502c04U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void)
+{
+        return 0x00502400U;
+}
+static inline u32 gr_fecs_ctxsw_idlestate_r(void)
+{
+        return 0x00409420U;
+}
+static inline u32 gr_fecs_feature_override_ecc_r(void)
+{
+        return 0x00409658U;
+}
+static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void)
+{
+        return 0x00502420U;
+}
+static inline u32 gr_rstr2d_gpc_map_r(u32 i)
+{
+        return 0x0040780cU + i*4U;
+}
+static inline u32 gr_rstr2d_map_table_cfg_r(void)
+{
+        return 0x004078bcU;
+}
+static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_pd_hww_esr_r(void)
+{
+        return 0x00406018U;
+}
+static inline u32 gr_pd_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_pd_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i)
+{
+        return 0x00406028U + i*4U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v)
+{
+        return (v & 0xfU) << 8U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v)
+{
+        return (v & 0xfU) << 12U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v)
+{
+        return (v & 0xfU) << 24U;
+}
+static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v)
+{
+        return (v & 0xfU) << 28U;
+}
+static inline u32 gr_pd_ab_dist_cfg0_r(void)
+{
+        return 0x004064c0U;
+}
+static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_r(void)
+{
+        return 0x004064c4U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void)
+{
+        return 0xffffU;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v)
+{
+        return (v & 0xffffU) << 16U;
+}
+static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_r(void)
+{
+        return 0x004064c8U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v)
+{
+        return (v & 0x1fffU) << 0U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void)
+{
+        return 0x00001680U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v)
+{
+        return (v & 0x1fffU) << 16U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void)
+{
+        return 0x00001680U;
+}
+static inline u32 gr_pd_dist_skip_table_r(u32 i)
+{
+        return 0x004064d0U + i*4U;
+}
+static inline u32 gr_pd_dist_skip_table__size_1_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 gr_ds_debug_r(void)
+{
+        return 0x00405800U;
+}
+static inline u32 gr_ds_debug_timeslice_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_debug_timeslice_mode_enable_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 gr_ds_zbc_color_r_r(void)
+{
+        return 0x00405804U;
+}
+static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_g_r(void)
+{
+        return 0x00405808U;
+}
+static inline u32 gr_ds_zbc_color_g_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_b_r(void)
+{
+        return 0x0040580cU;
+}
+static inline u32 gr_ds_zbc_color_b_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_a_r(void)
+{
+        return 0x00405810U;
+}
+static inline u32 gr_ds_zbc_color_a_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_fmt_r(void)
+{
+        return 0x00405814U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v)
+{
+        return (v & 0x7fU) << 0U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
+{
+        return 0x00000028U;
+}
+static inline u32 gr_ds_zbc_z_r(void)
+{
+        return 0x00405818U;
+}
+static inline u32 gr_ds_zbc_z_val_s(void)
+{
+        return 32U;
+}
+static inline u32 gr_ds_zbc_z_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_ds_zbc_z_val_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 gr_ds_zbc_z_val_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 gr_ds_zbc_z_val__init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_ds_zbc_z_val__init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_z_fmt_r(void)
+{
+        return 0x0040581cU;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_zbc_tbl_index_r(void)
+{
+        return 0x00405820U;
+}
+static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_r(void)
+{
+        return 0x00405824U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_ds_tga_constraintlogic_beta_r(void)
+{
+        return 0x00405830U;
+}
+static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v)
+{
+        return (v & 0x3fffffU) << 0U;
+}
+static inline u32 gr_ds_tga_constraintlogic_alpha_r(void)
+{
+        return 0x0040585cU;
+}
+static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_ds_hww_esr_r(void)
+{
+        return 0x00405840U;
+}
+static inline u32 gr_ds_hww_esr_reset_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_ds_hww_esr_reset_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 gr_ds_hww_esr_reset_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_ds_hww_esr_reset_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 gr_ds_hww_esr_reset_task_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_hww_esr_reset_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_ds_hww_esr_en_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_ds_hww_esr_2_r(void)
+{
+        return 0x00405848U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_task_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_ds_hww_esr_2_reset_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_ds_hww_esr_2_en_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_ds_hww_report_mask_r(void)
+{
+        return 0x00405844U;
+}
+static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void)
+{
+        return 0x400U;
+}
+static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void)
+{
+        return 0x800U;
+}
+static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 gr_ds_hww_report_mask_2_r(void)
+{
+        return 0x0040584cU;
+}
+static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i)
+{
+        return 0x00405870U + i*4U;
+}
+static inline u32 gr_scc_bundle_cb_base_r(void)
+{
+        return 0x00408004U;
+}
+static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_scc_bundle_cb_size_r(void)
+{
+        return 0x00408008U;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v)
+{
+        return (v & 0x7ffU) << 0U;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void)
+{
+        return 0x00000030U;
+}
+static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_scc_bundle_cb_size_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_scc_pagepool_base_r(void)
+{
+        return 0x0040800cU;
+}
+static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_scc_pagepool_r(void)
+{
+        return 0x00408010U;
+}
+static inline u32 gr_scc_pagepool_total_pages_f(u32 v)
+{
+        return (v & 0x3ffU) << 0U;
+}
+static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_s(void)
+{
+        return 10U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v)
+{
+        return (v & 0x3ffU) << 10U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_m(void)
+{
+        return 0x3ffU << 10U;
+}
+static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r)
+{
+        return (r >> 10U) & 0x3ffU;
+}
+static inline u32 gr_scc_pagepool_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_scc_init_r(void)
+{
+        return 0x0040802cU;
+}
+static inline u32 gr_scc_init_ram_trigger_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_scc_hww_esr_r(void)
+{
+        return 0x00408030U;
+}
+static inline u32 gr_scc_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_scc_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_ssync_hww_esr_r(void)
+{
+        return 0x00405a14U;
+}
+static inline u32 gr_ssync_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_ssync_hww_esr_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_sked_hww_esr_r(void)
+{
+        return 0x00407020U;
+}
+static inline u32 gr_sked_hww_esr_reset_active_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_sked_hww_esr_en_r(void)
+{
+        return 0x00407024U;
+}
+static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_m(void)
+{
+        return 0x1U << 25U;
+}
+static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_sked_hww_esr_en_skedcheck18_l1_config_too_small_enabled_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 gr_cwd_fs_r(void)
+{
+        return 0x00405b00U;
+}
+static inline u32 gr_cwd_fs_num_gpcs_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_cwd_fs_num_tpcs_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_r(u32 i)
+{
+        return 0x00405b60U + i*4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc0_s(void)
+{
+        return 4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_gpc0_s(void)
+{
+        return 4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_gpc0_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v)
+{
+        return (v & 0xfU) << 8U;
+}
+static inline u32 gr_cwd_sm_id_r(u32 i)
+{
+        return 0x00405ba0U + i*4U;
+}
+static inline u32 gr_cwd_sm_id__size_1_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_cwd_sm_id_tpc0_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_cwd_sm_id_tpc1_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpc0_fs_gpc_r(void)
+{
+        return 0x00502608U;
+}
+static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r)
+{
+        return (r >> 16U) & 0x1fU;
+}
+static inline u32 gr_gpc0_cfg_r(void)
+{
+        return 0x00502620U;
+}
+static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_gpccs_rc_lanes_r(void)
+{
+        return 0x00502880U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_gpccs_rc_lane_size_r(void)
+{
+        return 0x00502910U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_s(void)
+{
+        return 24U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_m(void)
+{
+        return 0xffffffU << 0U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_0_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpccs_rc_lane_size_v_0_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_zcull_fs_r(void)
+{
+        return 0x00500910U;
+}
+static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v)
+{
+        return (v & 0x1ffU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_r(void)
+{
+        return 0x00500914U;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v)
+{
+        return (v & 0xfU) << 8U;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void)
+{
+        return 0x00500918U;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void)
+{
+        return 0x00800000U;
+}
+static inline u32 gr_gpc0_zcull_total_ram_size_r(void)
+{
+        return 0x00500920U;
+}
+static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_zcull_zcsize_r(u32 i)
+{
+        return 0x00500a04U + i*32U;
+}
+static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i)
+{
+        return 0x00500c10U + i*4U;
+}
+static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i)
+{
+        return 0x00500c30U + i*4U;
+}
+static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void)
+{
+        return 0x00504088U;
+}
+static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_r(void)
+{
+        return 0x00504608U;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_r(void)
+{
+        return 0x00504330U;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r)
+{
+        return (r >> 8U) & 0xfffU;
+}
+static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r)
+{
+        return (r >> 20U) & 0xfffU;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void)
+{
+        return 0x00503018U;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void)
+{
+        return 0x005030c0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v)
+{
+        return (v & 0x3fffffU) << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void)
+{
+        return 0x3fffffU << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void)
+{
+        return 0x00000480U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void)
+{
+        return 0x00000d10U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void)
+{
+        return 0x005030f4U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void)
+{
+        return 0x005030e4U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void)
+{
+        return 0xffffU << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void)
+{
+        return 0x00000800U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void)
+{
+        return 0x005030f8U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void)
+{
+        return 0x005030f0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
+{
+        return (v & 0x3fffffU) << 0U;
+}
+static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
+{
+        return 0x00000480U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void)
+{
+        return 0x00419e00U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void)
+{
+        return 0x00419e04U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void)
+{
+        return 21U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v)
+{
+        return (v & 0x1fffffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void)
+{
+        return 0x1fffffU << 0U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r)
+{
+        return (r >> 0U) & 0x1fffffU;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void)
+{
+        return 0x80U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpccs_falcon_addr_r(void)
+{
+        return 0x0041a0acU;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_s(void)
+{
+        return 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v)
+{
+        return (v & 0x3fU) << 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_m(void)
+{
+        return 0x3fU << 6U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r)
+{
+        return (r >> 6U) & 0x3fU;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpccs_falcon_addr_msb_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_s(void)
+{
+        return 12U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_m(void)
+{
+        return 0xfffU << 0U;
+}
+static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r)
+{
+        return (r >> 0U) & 0xfffU;
+}
+static inline u32 gr_gpccs_cpuctl_r(void)
+{
+        return 0x0041a100U;
+}
+static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 gr_gpccs_dmactl_r(void)
+{
+        return 0x0041a10cU;
+}
+static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpccs_imemc_r(u32 i)
+{
+        return 0x0041a180U + i*16U;
+}
+static inline u32 gr_gpccs_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_gpccs_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpccs_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_gpccs_imemd_r(u32 i)
+{
+        return 0x0041a184U + i*16U;
+}
+static inline u32 gr_gpccs_imemt_r(u32 i)
+{
+        return 0x0041a188U + i*16U;
+}
+static inline u32 gr_gpccs_imemt__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 gr_gpccs_imemt_tag_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpccs_dmemc_r(u32 i)
+{
+        return 0x0041a1c0U + i*8U;
+}
+static inline u32 gr_gpccs_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 gr_gpccs_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpccs_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 gr_gpccs_dmemd_r(u32 i)
+{
+        return 0x0041a1c4U + i*8U;
+}
+static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i)
+{
+        return 0x0041a800U + i*4U;
+}
+static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void)
+{
+        return 0x00418e24U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void)
+{
+        return 32U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void)
+{
+        return 0x00418e28U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void)
+{
+        return 11U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v)
+{
+        return (v & 0x7ffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void)
+{
+        return 0x7ffU << 0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r)
+{
+        return (r >> 0U) & 0x7ffU;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void)
+{
+        return 0x00000030U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void)
+{
+        return 0x30U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void)
+{
+        return 1U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void)
+{
+        return 0x005001dcU;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void)
+{
+        return 0x000004b0U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void)
+{
+        return 0x005001d8U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void)
+{
+        return 0x004181e4U;
+}
+static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void)
+{
+        return 0x0041befcU;
+}
+static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i)
+{
+        return 0x00418ea0U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v)
+{
+        return (v & 0x3fffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void)
+{
+        return 0x3fffffU << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i)
+{
+        return 0x00418010U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i)
+{
+        return 0x0041804cU + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i)
+{
+        return 0x00418088U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i)
+{
+        return 0x004180c4U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void)
+{
+        return 0x00418100U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i)
+{
+        return 0x00418110U + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void)
+{
+        return 0x0041814cU;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_s_r(u32 i)
+{
+        return 0x0041815cU + i*4U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_s_val_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_gpcs_swdx_dss_zbc_s_01_to_04_format_r(void)
+{
+        return 0x00418198U;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_r(void)
+{
+        return 0x00418810U;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_crstr_gpc_map_r(u32 i)
+{
+        return 0x00418b08U + i*4U;
+}
+static inline u32 gr_crstr_gpc_map_tile0_f(u32 v)
+{
+        return (v & 0x1fU) << 0U;
+}
+static inline u32 gr_crstr_gpc_map_tile1_f(u32 v)
+{
+        return (v & 0x1fU) << 5U;
+}
+static inline u32 gr_crstr_gpc_map_tile2_f(u32 v)
+{
+        return (v & 0x1fU) << 10U;
+}
+static inline u32 gr_crstr_gpc_map_tile3_f(u32 v)
+{
+        return (v & 0x1fU) << 15U;
+}
+static inline u32 gr_crstr_gpc_map_tile4_f(u32 v)
+{
+        return (v & 0x1fU) << 20U;
+}
+static inline u32 gr_crstr_gpc_map_tile5_f(u32 v)
+{
+        return (v & 0x1fU) << 25U;
+}
+static inline u32 gr_crstr_map_table_cfg_r(void)
+{
+        return 0x00418bb8U;
+}
+static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i)
+{
+        return 0x00418980U + i*4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v)
+{
+        return (v & 0x7U) << 4U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v)
+{
+        return (v & 0x7U) << 28U;
+}
+static inline u32 gr_gpcs_gpm_pd_cfg_r(void)
+{
+        return 0x00418c6cU;
+}
+static inline u32 gr_gpcs_gcc_pagepool_base_r(void)
+{
+        return 0x00419004U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_r(void)
+{
+        return 0x00419008U;
+}
+static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v)
+{
+        return (v & 0x3ffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_pe_vaf_r(void)
+{
+        return 0x0041980cU;
+}
+static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void)
+{
+        return 0x00419848U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void)
+{
+        return 0x00419c00U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void)
+{
+        return 0x00419c2cU;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(void)
+{
+        return 0x00419ea8U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r(void)
+{
+        return 0x00504728U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void)
+{
+        return 0x40U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void)
+{
+        return 0x200U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void)
+{
+        return 0x800U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_nack_report_f(void)
+{
+        return 0x4000000U;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void)
+{
+        return 0x00419d0cU;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_mpc_enabled_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void)
+{
+        return 0x0050450cU;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_mpc_enabled_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void)
+{
+        return 0x0041ac94U;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_en_gcc_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_r(void)
+{
+        return 0x00502c90U;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_gcc_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void)
+{
+        return 0x00504508U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_mpc_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void)
+{
+        return 0x00504704U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_0_r(void)
+{
+        return 0x00504708U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_1_r(void)
+{
+        return 0x0050470cU;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_0_r(void)
+{
+        return 0x00504710U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_1_r(void)
+{
+        return 0x00504714U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r(void)
+{
+        return 0x00504718U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_1_r(void)
+{
+        return 0x0050471cU;
+}
+static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_0_r(void)
+{
+        return 0x00419e90U;
+}
+static inline u32 gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_1_r(void)
+{
+        return 0x00419e94U;
+}
+static inline u32 gr_gpcs_tpcs_sms_dbgr_status0_r(void)
+{
+        return 0x00419e80U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void)
+{
+        return 0x00504700U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void)
+{
+        return 0x00504730U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_error_f(void)
+{
+        return 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_api_stack_error_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_wrap_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_pc_f(void)
+{
+        return 0x5U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_pc_overflow_f(void)
+{
+        return 0x6U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_reg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_encoding_f(void)
+{
+        return 0x9U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_illegal_instr_param_f(void)
+{
+        return 0xbU;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_reg_f(void)
+{
+        return 0xdU;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_oor_addr_f(void)
+{
+        return 0xeU;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_misaligned_addr_f(void)
+{
+        return 0xfU;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_addr_space_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_invalid_const_addr_ldc_f(void)
+{
+        return 0x12U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_stack_overflow_f(void)
+{
+        return 0x16U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_fault_f(void)
+{
+        return 0x17U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_format_f(void)
+{
+        return 0x18U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_tex_layout_f(void)
+{
+        return 0x19U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f(void)
+{
+        return 0x20U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void)
+{
+        return 0xffU << 16U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void)
+{
+        return 0xfU << 24U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_r(void)
+{
+        return 0x0050460cU;
+}
+static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void)
+{
+        return 0x00504738U;
+}
+static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r(void)
+{
+        return 0x0050473cU;
+}
+static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void)
+{
+        return 0x005043a0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void)
+{
+        return 0x00419ba0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void)
+{
+        return 0x005043b0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void)
+{
+        return 0x00419bb0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void)
+{
+        return 0x0041be08U;
+}
+static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i)
+{
+        return 0x0041bf00U + i*4U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void)
+{
+        return 0x0041bfd0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v)
+{
+        return (v & 0x7U) << 21U;
+}
+static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void)
+{
+        return 0x0041bfd4U;
+}
+static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i)
+{
+        return 0x0041bfb0U + i*4U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff__size_1_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 gr_bes_zrop_settings_r(void)
+{
+        return 0x00408850U;
+}
+static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_be0_crop_debug3_r(void)
+{
+        return 0x00410108U;
+}
+static inline u32 gr_bes_crop_debug3_r(void)
+{
+        return 0x00408908U;
+}
+static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_read_suppress_enabled_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_fill_override_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_fill_override_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_bes_crop_debug3_blendopt_fill_override_enabled_f(void)
+{
+        return 0x4U;
+}
+static inline u32 gr_bes_crop_debug4_r(void)
+{
+        return 0x0040894cU;
+}
+static inline u32 gr_bes_crop_debug4_clamp_fp_blend_m(void)
+{
+        return 0x1U << 18U;
+}
+static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_inf_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_bes_crop_debug4_clamp_fp_blend_to_maxval_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 gr_bes_crop_settings_r(void)
+{
+        return 0x00408958U;
+}
+static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void)
+{
+        return 0x000000c0U;
+}
+static inline u32 gr_zcull_subregion_qty_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 gr_gpcs_tpcs_tex_in_dbg_r(void)
+{
+        return 0x00419a00U;
+}
+static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_f(u32 v)
+{
+        return (v & 0x1U) << 19U;
+}
+static inline u32 gr_gpcs_tpcs_tex_in_dbg_tsl1_rvch_invalidate_m(void)
+{
+        return 0x1U << 19U;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_r(void)
+{
+        return 0x00419bf0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_ld_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void)
+{
+        return 0x1U << 10U;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(void)
+{
+        return 0x1U << 28U;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 gr_fe_pwr_mode_r(void)
+{
+        return 0x00404170U;
+}
+static inline u32 gr_fe_pwr_mode_mode_auto_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_fe_pwr_mode_mode_force_on_f(void)
+{
+        return 0x2U;
+}
+static inline u32 gr_fe_pwr_mode_req_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 gr_fe_pwr_mode_req_send_f(void)
+{
+        return 0x10U;
+}
+static inline u32 gr_fe_pwr_mode_req_done_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_r(void)
+{
+        return 0x00418880U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void)
+{
+        return 0x1U << 11U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void)
+{
+        return 0x3U << 3U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void)
+{
+        return 0x3U << 5U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void)
+{
+        return 0x3U << 28U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void)
+{
+        return 0x00418890U;
+}
+static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void)
+{
+        return 0x00418894U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
+{
+        return 0x004188b0U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
+{
+        return 0x004188b4U;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void)
+{
+        return 0x004188b8U;
+}
+static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void)
+{
+        return 0x004188acU;
+}
+static inline u32 gr_gpcs_tpcs_sms_dbgr_control0_r(void)
+{
+        return 0x00419e84U;
+}
+static inline u32 gr_fe_gfxp_wfi_timeout_r(void)
+{
+        return 0x004041c0U;
+}
+static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void)
+{
+        return 0x00419bd8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void)
+{
+        return 0x7U << 8U;
+}
+static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void)
+{
+        return 0x100U;
+}
+static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void)
+{
+        return 0x00419ba4U;
+}
+static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void)
+{
+        return 0x3U << 11U;
+}
+static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 gr_gpcs_tc_debug0_r(void)
+{
+        return 0x00418708U;
+}
+static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v)
+{
+        return (v & 0x1ffU) << 0U;
+}
+static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void)
+{
+        return 0x1ffU << 0U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h b/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h
new file mode 100644
index 0000000..c27e607
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h
@@ -0,0 +1,331 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ioctrl_gv100_h_
+#define _hw_ioctrl_gv100_h_
+
+static inline u32 ioctrl_reset_r(void)
+{
+        return 0x00000140U;
+}
+static inline u32 ioctrl_reset_sw_post_reset_delay_microseconds_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ioctrl_reset_linkreset_f(u32 v)
+{
+        return (v & 0x3fU) << 8U;
+}
+static inline u32 ioctrl_reset_linkreset_m(void)
+{
+        return 0x3fU << 8U;
+}
+static inline u32 ioctrl_reset_linkreset_v(u32 r)
+{
+        return (r >> 8U) & 0x3fU;
+}
+static inline u32 ioctrl_debug_reset_r(void)
+{
+        return 0x00000144U;
+}
+static inline u32 ioctrl_debug_reset_link_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 ioctrl_debug_reset_link_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 ioctrl_debug_reset_link_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 ioctrl_debug_reset_common_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 ioctrl_debug_reset_common_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 ioctrl_debug_reset_common_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 ioctrl_clock_control_r(u32 i)
+{
+        return 0x00000180U + i*4U;
+}
+static inline u32 ioctrl_clock_control__size_1_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 ioctrl_clock_control_clkdis_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrl_clock_control_clkdis_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 ioctrl_clock_control_clkdis_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrl_top_intr_0_status_r(void)
+{
+        return 0x00000200U;
+}
+static inline u32 ioctrl_top_intr_0_status_link_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 ioctrl_top_intr_0_status_link_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 ioctrl_top_intr_0_status_link_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 ioctrl_top_intr_0_status_common_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 ioctrl_top_intr_0_status_common_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 ioctrl_top_intr_0_status_common_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_mask_r(void)
+{
+        return 0x00000220U;
+}
+static inline u32 ioctrl_common_intr_0_mask_fatal_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrl_common_intr_0_mask_fatal_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_mask_nonfatal_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrl_common_intr_0_mask_nonfatal_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_mask_correctable_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 ioctrl_common_intr_0_mask_correctable_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_mask_intra_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrl_common_intr_0_mask_intra_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_mask_intrb_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrl_common_intr_0_mask_intrb_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_status_r(void)
+{
+        return 0x00000224U;
+}
+static inline u32 ioctrl_common_intr_0_status_fatal_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrl_common_intr_0_status_fatal_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_status_nonfatal_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrl_common_intr_0_status_nonfatal_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_status_correctable_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 ioctrl_common_intr_0_status_correctable_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_status_intra_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrl_common_intr_0_status_intra_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrl_common_intr_0_status_intrb_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrl_common_intr_0_status_intrb_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_mask_r(u32 i)
+{
+        return 0x00000240U + i*20U;
+}
+static inline u32 ioctrl_link_intr_0_mask_fatal_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrl_link_intr_0_mask_fatal_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_mask_nonfatal_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrl_link_intr_0_mask_nonfatal_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_mask_correctable_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 ioctrl_link_intr_0_mask_correctable_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_mask_intra_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrl_link_intr_0_mask_intra_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_mask_intrb_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrl_link_intr_0_mask_intrb_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_status_r(u32 i)
+{
+        return 0x00000244U + i*20U;
+}
+static inline u32 ioctrl_link_intr_0_status_fatal_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrl_link_intr_0_status_fatal_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_status_nonfatal_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrl_link_intr_0_status_nonfatal_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_status_correctable_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 ioctrl_link_intr_0_status_correctable_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_status_intra_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrl_link_intr_0_status_intra_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrl_link_intr_0_status_intrb_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrl_link_intr_0_status_intrb_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h b/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h
new file mode 100644
index 0000000..5747a9b
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_ioctrlmif_gv100.h
@@ -0,0 +1,331 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ioctrlmif_gv100_h_
+#define _hw_ioctrlmif_gv100_h_
+
+static inline u32 ioctrlmif_rx_err_contain_en_0_r(void)
+{
+        return 0x00000e0cU;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramdataparityerr__prod_f(void)
+{
+        return 0x8U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ioctrlmif_rx_err_contain_en_0_rxramhdrparityerr__prod_f(void)
+{
+        return 0x10U;
+}
+static inline u32 ioctrlmif_rx_err_log_en_0_r(void)
+{
+        return 0x00000e04U;
+}
+static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 ioctrlmif_rx_err_log_en_0_rxramdataparityerr_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 ioctrlmif_rx_err_log_en_0_rxramhdrparityerr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_report_en_0_r(void)
+{
+        return 0x00000e08U;
+}
+static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 ioctrlmif_rx_err_report_en_0_rxramdataparityerr_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 ioctrlmif_rx_err_report_en_0_rxramhdrparityerr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_status_0_r(void)
+{
+        return 0x00000e00U;
+}
+static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 ioctrlmif_rx_err_status_0_rxramdataparityerr_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 ioctrlmif_rx_err_status_0_rxramhdrparityerr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 ioctrlmif_rx_err_first_0_r(void)
+{
+        return 0x00000e14U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_r(void)
+{
+        return 0x00000a90U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramdataparityerr__prod_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ioctrlmif_tx_err_contain_en_0_txramhdrparityerr__prod_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ioctrlmif_tx_err_log_en_0_r(void)
+{
+        return 0x00000a88U;
+}
+static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 ioctrlmif_tx_err_log_en_0_txramdataparityerr_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 ioctrlmif_tx_err_log_en_0_txramhdrparityerr_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_report_en_0_r(void)
+{
+        return 0x00000e08U;
+}
+static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 ioctrlmif_tx_err_report_en_0_txramdataparityerr_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 ioctrlmif_tx_err_report_en_0_txramhdrparityerr_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_status_0_r(void)
+{
+        return 0x00000a84U;
+}
+static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 ioctrlmif_tx_err_status_0_txramdataparityerr_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 ioctrlmif_tx_err_status_0_txramhdrparityerr_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 ioctrlmif_tx_err_first_0_r(void)
+{
+        return 0x00000a98U;
+}
+static inline u32 ioctrlmif_tx_ctrl_buffer_ready_r(void)
+{
+        return 0x00000a7cU;
+}
+static inline u32 ioctrlmif_rx_ctrl_buffer_ready_r(void)
+{
+        return 0x00000dfcU;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_ltc_gv100.h b/include/nvgpu/hw/gv100/hw_ltc_gv100.h
new file mode 100644
index 0000000..042cb7d
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_ltc_gv100.h
@@ -0,0 +1,631 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ltc_gv100_h_
+#define _hw_ltc_gv100_h_
+
+static inline u32 ltc_pltcg_base_v(void)
+{
+        return 0x00140000U;
+}
+static inline u32 ltc_pltcg_extent_v(void)
+{
+        return 0x0017ffffU;
+}
+static inline u32 ltc_ltc0_ltss_v(void)
+{
+        return 0x00140200U;
+}
+static inline u32 ltc_ltc0_lts0_v(void)
+{
+        return 0x00140400U;
+}
+static inline u32 ltc_ltcs_ltss_v(void)
+{
+        return 0x0017e200U;
+}
+static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void)
+{
+        return 0x0014046cU;
+}
+static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void)
+{
+        return 0x00140518U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void)
+{
+        return 0x0017e318U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void)
+{
+        return 0x1U << 15U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void)
+{
+        return 0x00140494U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r)
+{
+        return (r >> 16U) & 0x3U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void)
+{
+        return 0x0017e26cU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void)
+{
+        return 0x0014046cU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void)
+{
+        return 0x0017e270U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v)
+{
+        return (v & 0x3ffffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void)
+{
+        return 0x0017e274U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v)
+{
+        return (v & 0x3ffffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void)
+{
+        return 0x0003ffffU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_r(void)
+{
+        return 0x0017e278U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r)
+{
+        return (r >> 0U) & 0x3ffffffU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void)
+{
+        return 0x0017e27cU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs__v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_nvlink_peer_through_l2_v(u32 r)
+{
+        return (r >> 24U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_serialize_v(u32 r)
+{
+        return (r >> 25U) & 0x1U;
+}
+static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void)
+{
+        return 0x0017e000U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_r(void)
+{
+        return 0x0017e280U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r)
+{
+        return (r >> 24U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r)
+{
+        return (r >> 28U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param2_r(void)
+{
+        return 0x0017e3f4U;
+}
+static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void)
+{
+        return 0x0017e2acU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void)
+{
+        return 0x0017e338U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i)
+{
+        return 0x0017e33cU + i*4U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void)
+{
+        return 0x0017e34cU;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void)
+{
+        return 32U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_r(void)
+{
+        return 0x0017e204U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_s(void)
+{
+        return 8U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 ltc_ltcs_ltss_dstg_zbc_stencil_clear_value_field_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void)
+{
+        return 0x0017e2b0U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_r(void)
+{
+        return 0x0017e214U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_r(void)
+{
+        return 0x00140214U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_r(void)
+{
+        return 0x00142214U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_intr_r(void)
+{
+        return 0x0017e20cU;
+}
+static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void)
+{
+        return 0x200U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_m(void)
+{
+        return 0x1U << 21U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_enabled_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 ltc_ltc0_lts0_intr_r(void)
+{
+        return 0x0014040cU;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void)
+{
+        return 0x0014051cU;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void)
+{
+        return 0xffU << 16U;
+}
+static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x0017e2a0U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r)
+{
+        return (r >> 8U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void)
+{
+        return 0x300U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x0017e2a4U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r)
+{
+        return (r >> 8U) & 0xfU;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void)
+{
+        return 0x300U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x001402a0U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x001402a4U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void)
+{
+        return 0x001422a0U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void)
+{
+        return 0x001422a4U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void)
+{
+        return 0x0014058cU;
+}
+static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r)
+{
+        return (r >> 0U) & 0xffffU;
+}
+static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r)
+{
+        return (r >> 16U) & 0x1fU;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_mc_gv100.h b/include/nvgpu/hw/gv100/hw_mc_gv100.h
new file mode 100644
index 0000000..cf406c3
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_mc_gv100.h
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_mc_gv100_h_
+#define _hw_mc_gv100_h_
+
+static inline u32 mc_boot_0_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 mc_boot_0_architecture_v(u32 r)
+{
+        return (r >> 24U) & 0x1fU;
+}
+static inline u32 mc_boot_0_implementation_v(u32 r)
+{
+        return (r >> 20U) & 0xfU;
+}
+static inline u32 mc_boot_0_major_revision_v(u32 r)
+{
+        return (r >> 4U) & 0xfU;
+}
+static inline u32 mc_boot_0_minor_revision_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 mc_intr_r(u32 i)
+{
+        return 0x00000100U + i*4U;
+}
+static inline u32 mc_intr_pfifo_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 mc_intr_hub_pending_f(void)
+{
+        return 0x200U;
+}
+static inline u32 mc_intr_pgraph_pending_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 mc_intr_pmu_pending_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 mc_intr_ltc_pending_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 mc_intr_priv_ring_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 mc_intr_pbus_pending_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 mc_intr_nvlink_pending_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 mc_intr_en_r(u32 i)
+{
+        return 0x00000140U + i*4U;
+}
+static inline u32 mc_intr_en_set_r(u32 i)
+{
+        return 0x00000160U + i*4U;
+}
+static inline u32 mc_intr_en_clear_r(u32 i)
+{
+        return 0x00000180U + i*4U;
+}
+static inline u32 mc_enable_r(void)
+{
+        return 0x00000200U;
+}
+static inline u32 mc_enable_xbar_enabled_f(void)
+{
+        return 0x4U;
+}
+static inline u32 mc_enable_l2_enabled_f(void)
+{
+        return 0x8U;
+}
+static inline u32 mc_enable_pmedia_s(void)
+{
+        return 1U;
+}
+static inline u32 mc_enable_pmedia_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 mc_enable_pmedia_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 mc_enable_pmedia_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 mc_enable_ce0_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 mc_enable_pfifo_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 mc_enable_pgraph_enabled_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 mc_enable_pwr_v(u32 r)
+{
+        return (r >> 13U) & 0x1U;
+}
+static inline u32 mc_enable_pwr_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 mc_enable_pwr_enabled_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 mc_enable_pfb_enabled_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 mc_enable_ce2_m(void)
+{
+        return 0x1U << 21U;
+}
+static inline u32 mc_enable_ce2_enabled_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 mc_enable_blg_enabled_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 mc_enable_perfmon_enabled_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 mc_enable_hub_enabled_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 mc_enable_nvdec_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 mc_enable_nvdec_enabled_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 mc_enable_nvlink_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 mc_enable_nvlink_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 mc_enable_nvlink_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 mc_enable_nvlink_enabled_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 mc_intr_ltc_r(void)
+{
+        return 0x000001c0U;
+}
+static inline u32 mc_enable_pb_r(void)
+{
+        return 0x00000204U;
+}
+static inline u32 mc_enable_pb_0_s(void)
+{
+        return 1U;
+}
+static inline u32 mc_enable_pb_0_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 mc_enable_pb_0_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 mc_enable_pb_0_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 mc_enable_pb_0_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 mc_enable_pb_sel_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (0U + i*1U);
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_minion_gv100.h b/include/nvgpu/hw/gv100/hw_minion_gv100.h
new file mode 100644
index 0000000..e4bbf23
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_minion_gv100.h
@@ -0,0 +1,943 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_minion_gv100_h_
+#define _hw_minion_gv100_h_
+
+static inline u32 minion_minion_status_r(void)
+{
+        return 0x00000830U;
+}
+static inline u32 minion_minion_status_status_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 minion_minion_status_status_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 minion_minion_status_status_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 minion_minion_status_status_boot_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_minion_status_status_boot_f(void)
+{
+        return 0x1U;
+}
+static inline u32 minion_minion_status_intr_code_f(u32 v)
+{
+        return (v & 0xffffffU) << 8U;
+}
+static inline u32 minion_minion_status_intr_code_m(void)
+{
+        return 0xffffffU << 8U;
+}
+static inline u32 minion_minion_status_intr_code_v(u32 r)
+{
+        return (r >> 8U) & 0xffffffU;
+}
+static inline u32 minion_falcon_irqstat_r(void)
+{
+        return 0x00000008U;
+}
+static inline u32 minion_falcon_irqstat_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 minion_falcon_irqstat_halt_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 minion_falcon_irqstat_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 minion_falcon_irqstat_exterr_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 minion_falcon_irqstat_exterr_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 minion_falcon_irqmask_r(void)
+{
+        return 0x00000018U;
+}
+static inline u32 minion_falcon_irqsclr_r(void)
+{
+        return 0x00000004U;
+}
+static inline u32 minion_falcon_irqsset_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 minion_falcon_irqmset_r(void)
+{
+        return 0x00000010U;
+}
+static inline u32 minion_falcon_irqmset_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 minion_falcon_irqmset_wdtmr_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 minion_falcon_irqmset_wdtmr_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 minion_falcon_irqmset_wdtmr_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_falcon_irqmset_wdtmr_set_f(void)
+{
+        return 0x2U;
+}
+static inline u32 minion_falcon_irqmset_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 minion_falcon_irqmset_halt_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 minion_falcon_irqmset_halt_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 minion_falcon_irqmset_halt_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_falcon_irqmset_halt_set_f(void)
+{
+        return 0x10U;
+}
+static inline u32 minion_falcon_irqmset_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 minion_falcon_irqmset_exterr_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 minion_falcon_irqmset_exterr_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 minion_falcon_irqmset_exterr_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_falcon_irqmset_exterr_set_f(void)
+{
+        return 0x20U;
+}
+static inline u32 minion_falcon_irqmset_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 minion_falcon_irqmset_swgen0_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 minion_falcon_irqmset_swgen0_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 minion_falcon_irqmset_swgen0_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_falcon_irqmset_swgen0_set_f(void)
+{
+        return 0x40U;
+}
+static inline u32 minion_falcon_irqmset_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 minion_falcon_irqmset_swgen1_m(void)
+{
+        return 0x1U << 7U;
+}
+static inline u32 minion_falcon_irqmset_swgen1_v(u32 r)
+{
+        return (r >> 7U) & 0x1U;
+}
+static inline u32 minion_falcon_irqmset_swgen1_set_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_falcon_irqmset_swgen1_set_f(void)
+{
+        return 0x80U;
+}
+static inline u32 minion_falcon_irqdest_r(void)
+{
+        return 0x0000001cU;
+}
+static inline u32 minion_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 minion_falcon_irqdest_host_wdtmr_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 minion_falcon_irqdest_host_wdtmr_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_host_wdtmr_host_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_falcon_irqdest_host_wdtmr_host_f(void)
+{
+        return 0x2U;
+}
+static inline u32 minion_falcon_irqdest_host_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 minion_falcon_irqdest_host_halt_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 minion_falcon_irqdest_host_halt_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_host_halt_host_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_falcon_irqdest_host_halt_host_f(void)
+{
+        return 0x10U;
+}
+static inline u32 minion_falcon_irqdest_host_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 minion_falcon_irqdest_host_exterr_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 minion_falcon_irqdest_host_exterr_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_host_exterr_host_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_falcon_irqdest_host_exterr_host_f(void)
+{
+        return 0x20U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen0_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen0_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen0_host_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen0_host_f(void)
+{
+        return 0x40U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen1_m(void)
+{
+        return 0x1U << 7U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen1_v(u32 r)
+{
+        return (r >> 7U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen1_host_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_falcon_irqdest_host_swgen1_host_f(void)
+{
+        return 0x80U;
+}
+static inline u32 minion_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 minion_falcon_irqdest_target_wdtmr_m(void)
+{
+        return 0x1U << 17U;
+}
+static inline u32 minion_falcon_irqdest_target_wdtmr_v(u32 r)
+{
+        return (r >> 17U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_target_wdtmr_host_normal_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 minion_falcon_irqdest_target_wdtmr_host_normal_f(void)
+{
+        return 0x0U;
+}
+static inline u32 minion_falcon_irqdest_target_halt_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 minion_falcon_irqdest_target_halt_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 minion_falcon_irqdest_target_halt_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_target_halt_host_normal_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 minion_falcon_irqdest_target_halt_host_normal_f(void)
+{
+        return 0x0U;
+}
+static inline u32 minion_falcon_irqdest_target_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 minion_falcon_irqdest_target_exterr_m(void)
+{
+        return 0x1U << 21U;
+}
+static inline u32 minion_falcon_irqdest_target_exterr_v(u32 r)
+{
+        return (r >> 21U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_target_exterr_host_normal_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 minion_falcon_irqdest_target_exterr_host_normal_f(void)
+{
+        return 0x0U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen0_m(void)
+{
+        return 0x1U << 22U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen0_v(u32 r)
+{
+        return (r >> 22U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen0_host_normal_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen0_host_normal_f(void)
+{
+        return 0x0U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen1_m(void)
+{
+        return 0x1U << 23U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen1_v(u32 r)
+{
+        return (r >> 23U) & 0x1U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen1_host_normal_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 minion_falcon_irqdest_target_swgen1_host_normal_f(void)
+{
+        return 0x0U;
+}
+static inline u32 minion_falcon_os_r(void)
+{
+        return 0x00000080U;
+}
+static inline u32 minion_falcon_mailbox1_r(void)
+{
+        return 0x00000044U;
+}
+static inline u32 minion_minion_intr_r(void)
+{
+        return 0x00000810U;
+}
+static inline u32 minion_minion_intr_fatal_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 minion_minion_intr_fatal_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 minion_minion_intr_fatal_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 minion_minion_intr_nonfatal_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 minion_minion_intr_nonfatal_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 minion_minion_intr_nonfatal_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 minion_minion_intr_falcon_stall_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 minion_minion_intr_falcon_stall_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 minion_minion_intr_falcon_stall_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 minion_minion_intr_falcon_nostall_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 minion_minion_intr_falcon_nostall_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 minion_minion_intr_falcon_nostall_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 minion_minion_intr_link_f(u32 v)
+{
+        return (v & 0xffffU) << 16U;
+}
+static inline u32 minion_minion_intr_link_m(void)
+{
+        return 0xffffU << 16U;
+}
+static inline u32 minion_minion_intr_link_v(u32 r)
+{
+        return (r >> 16U) & 0xffffU;
+}
+static inline u32 minion_minion_intr_nonstall_en_r(void)
+{
+        return 0x0000081cU;
+}
+static inline u32 minion_minion_intr_stall_en_r(void)
+{
+        return 0x00000818U;
+}
+static inline u32 minion_minion_intr_stall_en_fatal_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 minion_minion_intr_stall_en_fatal_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 minion_minion_intr_stall_en_fatal_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 minion_minion_intr_stall_en_fatal_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_minion_intr_stall_en_fatal_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 minion_minion_intr_stall_en_fatal_disable_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 minion_minion_intr_stall_en_fatal_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 minion_minion_intr_stall_en_nonfatal_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 minion_minion_intr_stall_en_nonfatal_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 minion_minion_intr_stall_en_nonfatal_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 minion_minion_intr_stall_en_nonfatal_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_minion_intr_stall_en_nonfatal_enable_f(void)
+{
+        return 0x2U;
+}
+static inline u32 minion_minion_intr_stall_en_nonfatal_disable_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 minion_minion_intr_stall_en_nonfatal_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_stall_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_stall_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_stall_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_stall_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_stall_enable_f(void)
+{
+        return 0x4U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_stall_disable_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_stall_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_nostall_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_nostall_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_nostall_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_nostall_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_nostall_enable_f(void)
+{
+        return 0x8U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_nostall_disable_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 minion_minion_intr_stall_en_falcon_nostall_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 minion_minion_intr_stall_en_link_f(u32 v)
+{
+        return (v & 0xffffU) << 16U;
+}
+static inline u32 minion_minion_intr_stall_en_link_m(void)
+{
+        return 0xffffU << 16U;
+}
+static inline u32 minion_minion_intr_stall_en_link_v(u32 r)
+{
+        return (r >> 16U) & 0xffffU;
+}
+static inline u32 minion_nvlink_dl_cmd_r(u32 i)
+{
+        return 0x00000900U + i*4U;
+}
+static inline u32 minion_nvlink_dl_cmd___size_1_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 minion_nvlink_dl_cmd_command_configeom_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_configeom_f(void)
+{
+        return 0x40U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_nop_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_nop_f(void)
+{
+        return 0x0U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initphy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initphy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initlaneenable_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initlaneenable_f(void)
+{
+        return 0x3U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initdlpl_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initdlpl_f(void)
+{
+        return 0x4U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_lanedisable_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_lanedisable_f(void)
+{
+        return 0x8U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_fastlanedisable_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_fastlanedisable_f(void)
+{
+        return 0x9U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_laneshutdown_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 minion_nvlink_dl_cmd_command_laneshutdown_f(void)
+{
+        return 0xcU;
+}
+static inline u32 minion_nvlink_dl_cmd_command_setacmode_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 minion_nvlink_dl_cmd_command_setacmode_f(void)
+{
+        return 0xaU;
+}
+static inline u32 minion_nvlink_dl_cmd_command_clracmode_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 minion_nvlink_dl_cmd_command_clracmode_f(void)
+{
+        return 0xbU;
+}
+static inline u32 minion_nvlink_dl_cmd_command_enablepm_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_enablepm_f(void)
+{
+        return 0x10U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_disablepm_v(void)
+{
+        return 0x00000011U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_disablepm_f(void)
+{
+        return 0x11U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_savestate_v(void)
+{
+        return 0x00000018U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_savestate_f(void)
+{
+        return 0x18U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_restorestate_v(void)
+{
+        return 0x00000019U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_restorestate_f(void)
+{
+        return 0x19U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_0_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_0_f(void)
+{
+        return 0x20U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_1_v(void)
+{
+        return 0x00000021U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_1_f(void)
+{
+        return 0x21U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_2_v(void)
+{
+        return 0x00000022U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_2_f(void)
+{
+        return 0x22U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_3_v(void)
+{
+        return 0x00000023U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_3_f(void)
+{
+        return 0x23U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_4_v(void)
+{
+        return 0x00000024U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_4_f(void)
+{
+        return 0x24U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_5_v(void)
+{
+        return 0x00000025U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_5_f(void)
+{
+        return 0x25U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_6_v(void)
+{
+        return 0x00000026U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_6_f(void)
+{
+        return 0x26U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_7_v(void)
+{
+        return 0x00000027U;
+}
+static inline u32 minion_nvlink_dl_cmd_command_initpll_7_f(void)
+{
+        return 0x27U;
+}
+static inline u32 minion_nvlink_dl_cmd_fault_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 minion_nvlink_dl_cmd_fault_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 minion_nvlink_dl_cmd_ready_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 minion_nvlink_dl_cmd_ready_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 minion_misc_0_r(void)
+{
+        return 0x000008b0U;
+}
+static inline u32 minion_misc_0_scratch_swrw_0_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 minion_misc_0_scratch_swrw_0_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 minion_nvlink_link_intr_r(u32 i)
+{
+        return 0x00000a00U + i*4U;
+}
+static inline u32 minion_nvlink_link_intr___size_1_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 minion_nvlink_link_intr_code_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 minion_nvlink_link_intr_code_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 minion_nvlink_link_intr_code_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 minion_nvlink_link_intr_code_na_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 minion_nvlink_link_intr_code_na_f(void)
+{
+        return 0x0U;
+}
+static inline u32 minion_nvlink_link_intr_code_swreq_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 minion_nvlink_link_intr_code_swreq_f(void)
+{
+        return 0x1U;
+}
+static inline u32 minion_nvlink_link_intr_code_dlreq_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 minion_nvlink_link_intr_code_dlreq_f(void)
+{
+        return 0x2U;
+}
+static inline u32 minion_nvlink_link_intr_code_pmdisabled_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 minion_nvlink_link_intr_code_pmdisabled_f(void)
+{
+        return 0x3U;
+}
+static inline u32 minion_nvlink_link_intr_subcode_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 minion_nvlink_link_intr_subcode_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 minion_nvlink_link_intr_subcode_v(u32 r)
+{
+        return (r >> 8U) & 0xffU;
+}
+static inline u32 minion_nvlink_link_intr_state_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 minion_nvlink_link_intr_state_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 minion_nvlink_link_intr_state_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_nvl_gv100.h b/include/nvgpu/hw/gv100/hw_nvl_gv100.h
new file mode 100644
index 0000000..2e4ec16
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_nvl_gv100.h
@@ -0,0 +1,1571 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_nvl_gv100_h_
+#define _hw_nvl_gv100_h_
+
+static inline u32 nvl_link_state_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 nvl_link_state_state_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 nvl_link_state_state_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 nvl_link_state_state_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 nvl_link_state_state_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 nvl_link_state_state_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 nvl_link_state_state_hwcfg_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_link_state_state_hwcfg_f(void)
+{
+        return 0x1U;
+}
+static inline u32 nvl_link_state_state_swcfg_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 nvl_link_state_state_swcfg_f(void)
+{
+        return 0x2U;
+}
+static inline u32 nvl_link_state_state_active_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 nvl_link_state_state_active_f(void)
+{
+        return 0x3U;
+}
+static inline u32 nvl_link_state_state_fault_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 nvl_link_state_state_fault_f(void)
+{
+        return 0x4U;
+}
+static inline u32 nvl_link_state_state_rcvy_ac_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 nvl_link_state_state_rcvy_ac_f(void)
+{
+        return 0x8U;
+}
+static inline u32 nvl_link_state_state_rcvy_sw_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 nvl_link_state_state_rcvy_sw_f(void)
+{
+        return 0x9U;
+}
+static inline u32 nvl_link_state_state_rcvy_rx_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 nvl_link_state_state_rcvy_rx_f(void)
+{
+        return 0xaU;
+}
+static inline u32 nvl_link_state_an0_busy_f(u32 v)
+{
+        return (v & 0x1U) << 12U;
+}
+static inline u32 nvl_link_state_an0_busy_m(void)
+{
+        return 0x1U << 12U;
+}
+static inline u32 nvl_link_state_an0_busy_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 nvl_link_state_tl_busy_f(u32 v)
+{
+        return (v & 0x1U) << 13U;
+}
+static inline u32 nvl_link_state_tl_busy_m(void)
+{
+        return 0x1U << 13U;
+}
+static inline u32 nvl_link_state_tl_busy_v(u32 r)
+{
+        return (r >> 13U) & 0x1U;
+}
+static inline u32 nvl_link_state_dbg_substate_f(u32 v)
+{
+        return (v & 0xffffU) << 16U;
+}
+static inline u32 nvl_link_state_dbg_substate_m(void)
+{
+        return 0xffffU << 16U;
+}
+static inline u32 nvl_link_state_dbg_substate_v(u32 r)
+{
+        return (r >> 16U) & 0xffffU;
+}
+static inline u32 nvl_link_activity_r(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 nvl_link_activity_blkact_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 nvl_link_activity_blkact_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 nvl_link_activity_blkact_v(u32 r)
+{
+        return (r >> 0U) & 0x7U;
+}
+static inline u32 nvl_sublink_activity_r(u32 i)
+{
+        return 0x00000010U + i*4U;
+}
+static inline u32 nvl_sublink_activity_blkact0_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 nvl_sublink_activity_blkact0_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 nvl_sublink_activity_blkact0_v(u32 r)
+{
+        return (r >> 0U) & 0x7U;
+}
+static inline u32 nvl_sublink_activity_blkact1_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 nvl_sublink_activity_blkact1_m(void)
+{
+        return 0x7U << 8U;
+}
+static inline u32 nvl_sublink_activity_blkact1_v(u32 r)
+{
+        return (r >> 8U) & 0x7U;
+}
+static inline u32 nvl_link_config_r(void)
+{
+        return 0x00000018U;
+}
+static inline u32 nvl_link_config_ac_safe_en_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 nvl_link_config_ac_safe_en_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 nvl_link_config_ac_safe_en_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 nvl_link_config_ac_safe_en_on_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_link_config_ac_safe_en_on_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 nvl_link_config_link_en_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 nvl_link_config_link_en_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 nvl_link_config_link_en_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 nvl_link_config_link_en_on_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_link_config_link_en_on_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 nvl_link_change_r(void)
+{
+        return 0x00000040U;
+}
+static inline u32 nvl_link_change_oldstate_mask_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 nvl_link_change_oldstate_mask_m(void)
+{
+        return 0xfU << 16U;
+}
+static inline u32 nvl_link_change_oldstate_mask_v(u32 r)
+{
+        return (r >> 16U) & 0xfU;
+}
+static inline u32 nvl_link_change_oldstate_mask_dontcare_v(void)
+{
+        return 0x0000000fU;
+}
+static inline u32 nvl_link_change_oldstate_mask_dontcare_f(void)
+{
+        return 0xf0000U;
+}
+static inline u32 nvl_link_change_newstate_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 nvl_link_change_newstate_m(void)
+{
+        return 0xfU << 4U;
+}
+static inline u32 nvl_link_change_newstate_v(u32 r)
+{
+        return (r >> 4U) & 0xfU;
+}
+static inline u32 nvl_link_change_newstate_hwcfg_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_link_change_newstate_hwcfg_f(void)
+{
+        return 0x10U;
+}
+static inline u32 nvl_link_change_newstate_swcfg_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 nvl_link_change_newstate_swcfg_f(void)
+{
+        return 0x20U;
+}
+static inline u32 nvl_link_change_newstate_active_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 nvl_link_change_newstate_active_f(void)
+{
+        return 0x30U;
+}
+static inline u32 nvl_link_change_action_f(u32 v)
+{
+        return (v & 0x3U) << 2U;
+}
+static inline u32 nvl_link_change_action_m(void)
+{
+        return 0x3U << 2U;
+}
+static inline u32 nvl_link_change_action_v(u32 r)
+{
+        return (r >> 2U) & 0x3U;
+}
+static inline u32 nvl_link_change_action_ltssm_change_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_link_change_action_ltssm_change_f(void)
+{
+        return 0x4U;
+}
+static inline u32 nvl_link_change_status_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 nvl_link_change_status_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 nvl_link_change_status_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 nvl_link_change_status_done_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 nvl_link_change_status_done_f(void)
+{
+        return 0x0U;
+}
+static inline u32 nvl_link_change_status_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_link_change_status_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 nvl_link_change_status_fault_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 nvl_link_change_status_fault_f(void)
+{
+        return 0x2U;
+}
+static inline u32 nvl_sublink_change_r(void)
+{
+        return 0x00000044U;
+}
+static inline u32 nvl_sublink_change_countdown_f(u32 v)
+{
+        return (v & 0xfffU) << 20U;
+}
+static inline u32 nvl_sublink_change_countdown_m(void)
+{
+        return 0xfffU << 20U;
+}
+static inline u32 nvl_sublink_change_countdown_v(u32 r)
+{
+        return (r >> 20U) & 0xfffU;
+}
+static inline u32 nvl_sublink_change_oldstate_mask_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 nvl_sublink_change_oldstate_mask_m(void)
+{
+        return 0xfU << 16U;
+}
+static inline u32 nvl_sublink_change_oldstate_mask_v(u32 r)
+{
+        return (r >> 16U) & 0xfU;
+}
+static inline u32 nvl_sublink_change_oldstate_mask_dontcare_v(void)
+{
+        return 0x0000000fU;
+}
+static inline u32 nvl_sublink_change_oldstate_mask_dontcare_f(void)
+{
+        return 0xf0000U;
+}
+static inline u32 nvl_sublink_change_sublink_f(u32 v)
+{
+        return (v & 0xfU) << 12U;
+}
+static inline u32 nvl_sublink_change_sublink_m(void)
+{
+        return 0xfU << 12U;
+}
+static inline u32 nvl_sublink_change_sublink_v(u32 r)
+{
+        return (r >> 12U) & 0xfU;
+}
+static inline u32 nvl_sublink_change_sublink_tx_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 nvl_sublink_change_sublink_tx_f(void)
+{
+        return 0x0U;
+}
+static inline u32 nvl_sublink_change_sublink_rx_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_sublink_change_sublink_rx_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 nvl_sublink_change_newstate_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 nvl_sublink_change_newstate_m(void)
+{
+        return 0xfU << 4U;
+}
+static inline u32 nvl_sublink_change_newstate_v(u32 r)
+{
+        return (r >> 4U) & 0xfU;
+}
+static inline u32 nvl_sublink_change_newstate_hs_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 nvl_sublink_change_newstate_hs_f(void)
+{
+        return 0x0U;
+}
+static inline u32 nvl_sublink_change_newstate_eighth_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 nvl_sublink_change_newstate_eighth_f(void)
+{
+        return 0x40U;
+}
+static inline u32 nvl_sublink_change_newstate_train_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 nvl_sublink_change_newstate_train_f(void)
+{
+        return 0x50U;
+}
+static inline u32 nvl_sublink_change_newstate_safe_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 nvl_sublink_change_newstate_safe_f(void)
+{
+        return 0x60U;
+}
+static inline u32 nvl_sublink_change_newstate_off_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 nvl_sublink_change_newstate_off_f(void)
+{
+        return 0x70U;
+}
+static inline u32 nvl_sublink_change_action_f(u32 v)
+{
+        return (v & 0x3U) << 2U;
+}
+static inline u32 nvl_sublink_change_action_m(void)
+{
+        return 0x3U << 2U;
+}
+static inline u32 nvl_sublink_change_action_v(u32 r)
+{
+        return (r >> 2U) & 0x3U;
+}
+static inline u32 nvl_sublink_change_action_slsm_change_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_sublink_change_action_slsm_change_f(void)
+{
+        return 0x4U;
+}
+static inline u32 nvl_sublink_change_status_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 nvl_sublink_change_status_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 nvl_sublink_change_status_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 nvl_sublink_change_status_done_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 nvl_sublink_change_status_done_f(void)
+{
+        return 0x0U;
+}
+static inline u32 nvl_sublink_change_status_busy_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_sublink_change_status_busy_f(void)
+{
+        return 0x1U;
+}
+static inline u32 nvl_sublink_change_status_fault_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 nvl_sublink_change_status_fault_f(void)
+{
+        return 0x2U;
+}
+static inline u32 nvl_link_test_r(void)
+{
+        return 0x00000048U;
+}
+static inline u32 nvl_link_test_mode_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 nvl_link_test_mode_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 nvl_link_test_mode_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 nvl_link_test_mode_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_link_test_mode_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 nvl_link_test_auto_hwcfg_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 nvl_link_test_auto_hwcfg_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 nvl_link_test_auto_hwcfg_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 nvl_link_test_auto_hwcfg_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_link_test_auto_hwcfg_enable_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 nvl_link_test_auto_nvhs_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 nvl_link_test_auto_nvhs_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 nvl_link_test_auto_nvhs_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 nvl_link_test_auto_nvhs_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_link_test_auto_nvhs_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_r(void)
+{
+        return 0x00002024U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_substate_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_substate_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_substate_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_m(void)
+{
+        return 0xfU << 4U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_v(u32 r)
+{
+        return (r >> 4U) & 0xfU;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_hs_f(void)
+{
+        return 0x0U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_eighth_f(void)
+{
+        return 0x40U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_train_f(void)
+{
+        return 0x50U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_off_f(void)
+{
+        return 0x70U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 nvl_sl0_slsm_status_tx_primary_state_safe_f(void)
+{
+        return 0x60U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_r(void)
+{
+        return 0x00003014U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_substate_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_substate_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_substate_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_f(u32 v)
+{
+        return (v & 0xfU) << 4U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_m(void)
+{
+        return 0xfU << 4U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_v(u32 r)
+{
+        return (r >> 4U) & 0xfU;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_hs_f(void)
+{
+        return 0x0U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_eighth_f(void)
+{
+        return 0x40U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_train_f(void)
+{
+        return 0x50U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_off_f(void)
+{
+        return 0x70U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 nvl_sl1_slsm_status_rx_primary_state_safe_f(void)
+{
+        return 0x60U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_r(void)
+{
+        return 0x00002008U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_f(u32 v)
+{
+        return (v & 0x7ffU) << 0U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_m(void)
+{
+        return 0x7ffU << 0U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_v(u32 r)
+{
+        return (r >> 0U) & 0x7ffU;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_v(void)
+{
+        return 0x00000728U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_init_init_f(void)
+{
+        return 0x728U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_f(u32 v)
+{
+        return (v & 0x1fU) << 11U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_m(void)
+{
+        return 0x1fU << 11U;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_v(u32 r)
+{
+        return (r >> 11U) & 0x1fU;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_v(void)
+{
+        return 0x0000000fU;
+}
+static inline u32 nvl_sl0_safe_ctrl2_tx_ctr_initscl_init_f(void)
+{
+        return 0x7800U;
+}
+static inline u32 nvl_sl1_error_rate_ctrl_r(void)
+{
+        return 0x00003284U;
+}
+static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 nvl_sl1_error_rate_ctrl_short_threshold_man_v(u32 r)
+{
+        return (r >> 0U) & 0x7U;
+}
+static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_f(u32 v)
+{
+        return (v & 0x7U) << 16U;
+}
+static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_m(void)
+{
+        return 0x7U << 16U;
+}
+static inline u32 nvl_sl1_error_rate_ctrl_long_threshold_man_v(u32 r)
+{
+        return (r >> 16U) & 0x7U;
+}
+static inline u32 nvl_sl1_rxslsm_timeout_2_r(void)
+{
+        return 0x00003034U;
+}
+static inline u32 nvl_txiobist_configreg_r(void)
+{
+        return 0x00002e14U;
+}
+static inline u32 nvl_txiobist_configreg_io_bist_mode_in_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 nvl_txiobist_configreg_io_bist_mode_in_m(void)
+{
+        return 0x1U << 17U;
+}
+static inline u32 nvl_txiobist_configreg_io_bist_mode_in_v(u32 r)
+{
+        return (r >> 17U) & 0x1U;
+}
+static inline u32 nvl_txiobist_config_r(void)
+{
+        return 0x00002e10U;
+}
+static inline u32 nvl_txiobist_config_dpg_prbsseedld_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 nvl_txiobist_config_dpg_prbsseedld_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 nvl_txiobist_config_dpg_prbsseedld_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 nvl_intr_r(void)
+{
+        return 0x00000050U;
+}
+static inline u32 nvl_intr_tx_replay_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 nvl_intr_tx_replay_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 nvl_intr_tx_replay_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 nvl_intr_tx_recovery_short_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 nvl_intr_tx_recovery_short_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 nvl_intr_tx_recovery_short_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 nvl_intr_tx_recovery_long_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 nvl_intr_tx_recovery_long_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 nvl_intr_tx_recovery_long_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 nvl_intr_tx_fault_ram_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 nvl_intr_tx_fault_ram_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 nvl_intr_tx_fault_ram_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 nvl_intr_tx_fault_interface_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 nvl_intr_tx_fault_interface_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 nvl_intr_tx_fault_interface_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 nvl_intr_tx_fault_sublink_change_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 nvl_intr_tx_fault_sublink_change_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 nvl_intr_tx_fault_sublink_change_v(u32 r)
+{
+        return (r >> 8U) & 0x1U;
+}
+static inline u32 nvl_intr_rx_fault_sublink_change_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 nvl_intr_rx_fault_sublink_change_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 nvl_intr_rx_fault_sublink_change_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 nvl_intr_rx_fault_dl_protocol_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 nvl_intr_rx_fault_dl_protocol_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 nvl_intr_rx_fault_dl_protocol_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 nvl_intr_rx_short_error_rate_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 nvl_intr_rx_short_error_rate_m(void)
+{
+        return 0x1U << 21U;
+}
+static inline u32 nvl_intr_rx_short_error_rate_v(u32 r)
+{
+        return (r >> 21U) & 0x1U;
+}
+static inline u32 nvl_intr_rx_long_error_rate_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 nvl_intr_rx_long_error_rate_m(void)
+{
+        return 0x1U << 22U;
+}
+static inline u32 nvl_intr_rx_long_error_rate_v(u32 r)
+{
+        return (r >> 22U) & 0x1U;
+}
+static inline u32 nvl_intr_rx_ila_trigger_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 nvl_intr_rx_ila_trigger_m(void)
+{
+        return 0x1U << 23U;
+}
+static inline u32 nvl_intr_rx_ila_trigger_v(u32 r)
+{
+        return (r >> 23U) & 0x1U;
+}
+static inline u32 nvl_intr_rx_crc_counter_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 nvl_intr_rx_crc_counter_m(void)
+{
+        return 0x1U << 24U;
+}
+static inline u32 nvl_intr_rx_crc_counter_v(u32 r)
+{
+        return (r >> 24U) & 0x1U;
+}
+static inline u32 nvl_intr_ltssm_fault_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 nvl_intr_ltssm_fault_m(void)
+{
+        return 0x1U << 28U;
+}
+static inline u32 nvl_intr_ltssm_fault_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 nvl_intr_ltssm_protocol_f(u32 v)
+{
+        return (v & 0x1U) << 29U;
+}
+static inline u32 nvl_intr_ltssm_protocol_m(void)
+{
+        return 0x1U << 29U;
+}
+static inline u32 nvl_intr_ltssm_protocol_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_request_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 nvl_intr_minion_request_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 nvl_intr_minion_request_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 nvl_intr_sw2_r(void)
+{
+        return 0x00000054U;
+}
+static inline u32 nvl_intr_minion_r(void)
+{
+        return 0x00000060U;
+}
+static inline u32 nvl_intr_minion_tx_replay_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 nvl_intr_minion_tx_replay_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 nvl_intr_minion_tx_replay_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_tx_recovery_short_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 nvl_intr_minion_tx_recovery_short_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 nvl_intr_minion_tx_recovery_short_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_tx_recovery_long_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 nvl_intr_minion_tx_recovery_long_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 nvl_intr_minion_tx_recovery_long_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_tx_fault_ram_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 nvl_intr_minion_tx_fault_ram_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 nvl_intr_minion_tx_fault_ram_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_tx_fault_interface_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 nvl_intr_minion_tx_fault_interface_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 nvl_intr_minion_tx_fault_interface_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_tx_fault_sublink_change_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 nvl_intr_minion_tx_fault_sublink_change_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 nvl_intr_minion_tx_fault_sublink_change_v(u32 r)
+{
+        return (r >> 8U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_rx_fault_sublink_change_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 nvl_intr_minion_rx_fault_sublink_change_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 nvl_intr_minion_rx_fault_sublink_change_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_rx_fault_dl_protocol_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 nvl_intr_minion_rx_fault_dl_protocol_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 nvl_intr_minion_rx_fault_dl_protocol_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_rx_short_error_rate_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 nvl_intr_minion_rx_short_error_rate_m(void)
+{
+        return 0x1U << 21U;
+}
+static inline u32 nvl_intr_minion_rx_short_error_rate_v(u32 r)
+{
+        return (r >> 21U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_rx_long_error_rate_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 nvl_intr_minion_rx_long_error_rate_m(void)
+{
+        return 0x1U << 22U;
+}
+static inline u32 nvl_intr_minion_rx_long_error_rate_v(u32 r)
+{
+        return (r >> 22U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_rx_ila_trigger_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 nvl_intr_minion_rx_ila_trigger_m(void)
+{
+        return 0x1U << 23U;
+}
+static inline u32 nvl_intr_minion_rx_ila_trigger_v(u32 r)
+{
+        return (r >> 23U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_rx_crc_counter_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 nvl_intr_minion_rx_crc_counter_m(void)
+{
+        return 0x1U << 24U;
+}
+static inline u32 nvl_intr_minion_rx_crc_counter_v(u32 r)
+{
+        return (r >> 24U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_ltssm_fault_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 nvl_intr_minion_ltssm_fault_m(void)
+{
+        return 0x1U << 28U;
+}
+static inline u32 nvl_intr_minion_ltssm_fault_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_ltssm_protocol_f(u32 v)
+{
+        return (v & 0x1U) << 29U;
+}
+static inline u32 nvl_intr_minion_ltssm_protocol_m(void)
+{
+        return 0x1U << 29U;
+}
+static inline u32 nvl_intr_minion_ltssm_protocol_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 nvl_intr_minion_minion_request_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 nvl_intr_minion_minion_request_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 nvl_intr_minion_minion_request_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 nvl_intr_nonstall_en_r(void)
+{
+        return 0x0000005cU;
+}
+static inline u32 nvl_intr_stall_en_r(void)
+{
+        return 0x00000058U;
+}
+static inline u32 nvl_intr_stall_en_tx_replay_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 nvl_intr_stall_en_tx_replay_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 nvl_intr_stall_en_tx_replay_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_short_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_short_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_short_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_short_enable_f(void)
+{
+        return 0x2U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_long_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_long_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_long_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_tx_recovery_long_enable_f(void)
+{
+        return 0x4U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_ram_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_ram_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_ram_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_ram_enable_f(void)
+{
+        return 0x10U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_interface_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_interface_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_interface_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_interface_enable_f(void)
+{
+        return 0x20U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_v(u32 r)
+{
+        return (r >> 8U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_tx_fault_sublink_change_enable_f(void)
+{
+        return 0x100U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_sublink_change_enable_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_rx_fault_dl_protocol_enable_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 nvl_intr_stall_en_rx_short_error_rate_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 nvl_intr_stall_en_rx_short_error_rate_m(void)
+{
+        return 0x1U << 21U;
+}
+static inline u32 nvl_intr_stall_en_rx_short_error_rate_v(u32 r)
+{
+        return (r >> 21U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_rx_short_error_rate_enable_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 nvl_intr_stall_en_rx_long_error_rate_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 nvl_intr_stall_en_rx_long_error_rate_m(void)
+{
+        return 0x1U << 22U;
+}
+static inline u32 nvl_intr_stall_en_rx_long_error_rate_v(u32 r)
+{
+        return (r >> 22U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_rx_long_error_rate_enable_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 nvl_intr_stall_en_rx_ila_trigger_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 nvl_intr_stall_en_rx_ila_trigger_m(void)
+{
+        return 0x1U << 23U;
+}
+static inline u32 nvl_intr_stall_en_rx_ila_trigger_v(u32 r)
+{
+        return (r >> 23U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_rx_ila_trigger_enable_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 nvl_intr_stall_en_rx_crc_counter_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 nvl_intr_stall_en_rx_crc_counter_m(void)
+{
+        return 0x1U << 24U;
+}
+static inline u32 nvl_intr_stall_en_rx_crc_counter_v(u32 r)
+{
+        return (r >> 24U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_rx_crc_counter_enable_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_fault_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_fault_m(void)
+{
+        return 0x1U << 28U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_fault_v(u32 r)
+{
+        return (r >> 28U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_fault_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_fault_enable_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_protocol_f(u32 v)
+{
+        return (v & 0x1U) << 29U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_protocol_m(void)
+{
+        return 0x1U << 29U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_protocol_v(u32 r)
+{
+        return (r >> 29U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_ltssm_protocol_enable_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 nvl_intr_stall_en_minion_request_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 nvl_intr_stall_en_minion_request_m(void)
+{
+        return 0x1U << 30U;
+}
+static inline u32 nvl_intr_stall_en_minion_request_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 nvl_intr_stall_en_minion_request_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_intr_stall_en_minion_request_enable_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 nvl_br0_cfg_cal_r(void)
+{
+        return 0x0000281cU;
+}
+static inline u32 nvl_br0_cfg_cal_rxcal_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 nvl_br0_cfg_cal_rxcal_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 nvl_br0_cfg_cal_rxcal_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 nvl_br0_cfg_cal_rxcal_on_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvl_br0_cfg_cal_rxcal_on_f(void)
+{
+        return 0x1U;
+}
+static inline u32 nvl_br0_cfg_status_cal_r(void)
+{
+        return 0x00002838U;
+}
+static inline u32 nvl_br0_cfg_status_cal_rxcal_done_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 nvl_br0_cfg_status_cal_rxcal_done_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 nvl_br0_cfg_status_cal_rxcal_done_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h b/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h
new file mode 100644
index 0000000..9d33a9f
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_nvlinkip_discovery_gv100.h
@@ -0,0 +1,311 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_nvlinkip_discovery_gv100_h_
+#define _hw_nvlinkip_discovery_gv100_h_
+
+static inline u32 nvlinkip_discovery_common_r(void)
+{
+        return 0x00000000U;
+}
+static inline u32 nvlinkip_discovery_common_entry_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 nvlinkip_discovery_common_entry_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 nvlinkip_discovery_common_entry_invalid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 nvlinkip_discovery_common_entry_enum_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvlinkip_discovery_common_entry_data1_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 nvlinkip_discovery_common_entry_data2_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 nvlinkip_discovery_common_contents_f(u32 v)
+{
+        return (v & 0x1fffffffU) << 2U;
+}
+static inline u32 nvlinkip_discovery_common_contents_v(u32 r)
+{
+        return (r >> 2U) & 0x1fffffffU;
+}
+static inline u32 nvlinkip_discovery_common_chain_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 nvlinkip_discovery_common_chain_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 nvlinkip_discovery_common_chain_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvlinkip_discovery_common_device_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 nvlinkip_discovery_common_device_v(u32 r)
+{
+        return (r >> 2U) & 0x3fU;
+}
+static inline u32 nvlinkip_discovery_common_device_invalid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 nvlinkip_discovery_common_device_ioctrl_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvlinkip_discovery_common_device_nvltl_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 nvlinkip_discovery_common_device_nvlink_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 nvlinkip_discovery_common_device_minion_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 nvlinkip_discovery_common_device_nvlipt_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 nvlinkip_discovery_common_device_nvltlc_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 nvlinkip_discovery_common_device_dlpl_v(void)
+{
+        return 0x0000000bU;
+}
+static inline u32 nvlinkip_discovery_common_device_ioctrlmif_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 nvlinkip_discovery_common_device_dlpl_multicast_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 nvlinkip_discovery_common_device_nvltlc_multicast_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 nvlinkip_discovery_common_device_ioctrlmif_multicast_v(void)
+{
+        return 0x0000000aU;
+}
+static inline u32 nvlinkip_discovery_common_device_sioctrl_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 nvlinkip_discovery_common_device_tioctrl_v(void)
+{
+        return 0x0000000dU;
+}
+static inline u32 nvlinkip_discovery_common_id_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 nvlinkip_discovery_common_id_v(u32 r)
+{
+        return (r >> 8U) & 0xffU;
+}
+static inline u32 nvlinkip_discovery_common_version_f(u32 v)
+{
+        return (v & 0x7ffU) << 20U;
+}
+static inline u32 nvlinkip_discovery_common_version_v(u32 r)
+{
+        return (r >> 20U) & 0x7ffU;
+}
+static inline u32 nvlinkip_discovery_common_pri_base_f(u32 v)
+{
+        return (v & 0xfffU) << 12U;
+}
+static inline u32 nvlinkip_discovery_common_pri_base_v(u32 r)
+{
+        return (r >> 12U) & 0xfffU;
+}
+static inline u32 nvlinkip_discovery_common_intr_f(u32 v)
+{
+        return (v & 0x1fU) << 7U;
+}
+static inline u32 nvlinkip_discovery_common_intr_v(u32 r)
+{
+        return (r >> 7U) & 0x1fU;
+}
+static inline u32 nvlinkip_discovery_common_reset_f(u32 v)
+{
+        return (v & 0x1fU) << 2U;
+}
+static inline u32 nvlinkip_discovery_common_reset_v(u32 r)
+{
+        return (r >> 2U) & 0x1fU;
+}
+static inline u32 nvlinkip_discovery_common_ioctrl_length_f(u32 v)
+{
+        return (v & 0x3fU) << 24U;
+}
+static inline u32 nvlinkip_discovery_common_ioctrl_length_v(u32 r)
+{
+        return (r >> 24U) & 0x3fU;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_num_tx_f(u32 v)
+{
+        return (v & 0x7U) << 24U;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_num_tx_v(u32 r)
+{
+        return (r >> 24U) & 0x7U;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_num_rx_f(u32 v)
+{
+        return (v & 0x7U) << 27U;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_num_rx_v(u32 r)
+{
+        return (r >> 27U) & 0x7U;
+}
+static inline u32 nvlinkip_discovery_common_data1_ioctrl_length_f(u32 v)
+{
+        return (v & 0x7ffffU) << 12U;
+}
+static inline u32 nvlinkip_discovery_common_data1_ioctrl_length_v(u32 r)
+{
+        return (r >> 12U) & 0x7ffffU;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_f(u32 v)
+{
+        return (v & 0x1fU) << 26U;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_v(u32 r)
+{
+        return (r >> 26U) & 0x1fU;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_invalid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_pllcontrol_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_resetreg_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_intrreg_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_discovery_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_unicast_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 nvlinkip_discovery_common_data2_type_broadcast_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 nvlinkip_discovery_common_data2_addr_f(u32 v)
+{
+        return (v & 0xffffffU) << 2U;
+}
+static inline u32 nvlinkip_discovery_common_data2_addr_v(u32 r)
+{
+        return (r >> 2U) & 0xffffffU;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_data2_type_f(u32 v)
+{
+        return (v & 0x1fU) << 26U;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_data2_type_v(u32 r)
+{
+        return (r >> 26U) & 0x1fU;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_data2_master_f(u32 v)
+{
+        return (v & 0x1U) << 15U;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_data2_master_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_data2_masterid_f(u32 v)
+{
+        return (v & 0x7fU) << 8U;
+}
+static inline u32 nvlinkip_discovery_common_dlpl_data2_masterid_v(u32 r)
+{
+        return (r >> 8U) & 0x7fU;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h b/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h
new file mode 100644
index 0000000..5f73fab
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_nvlipt_gv100.h
@@ -0,0 +1,279 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_nvlipt_gv100_h_
+#define _hw_nvlipt_gv100_h_
+
+static inline u32 nvlipt_intr_control_link0_r(void)
+{
+        return 0x000004b4U;
+}
+static inline u32 nvlipt_intr_control_link0_stallenable_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 nvlipt_intr_control_link0_stallenable_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 nvlipt_intr_control_link0_stallenable_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 nvlipt_intr_control_link0_nostallenable_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 nvlipt_intr_control_link0_nostallenable_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 nvlipt_intr_control_link0_nostallenable_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_r(void)
+{
+        return 0x00000524U;
+}
+static inline u32 nvlipt_err_uc_status_link0_dlprotocol_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 nvlipt_err_uc_status_link0_dlprotocol_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_datapoisoned_f(u32 v)
+{
+        return (v & 0x1U) << 12U;
+}
+static inline u32 nvlipt_err_uc_status_link0_datapoisoned_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_flowcontrol_f(u32 v)
+{
+        return (v & 0x1U) << 13U;
+}
+static inline u32 nvlipt_err_uc_status_link0_flowcontrol_v(u32 r)
+{
+        return (r >> 13U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_responsetimeout_f(u32 v)
+{
+        return (v & 0x1U) << 14U;
+}
+static inline u32 nvlipt_err_uc_status_link0_responsetimeout_v(u32 r)
+{
+        return (r >> 14U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_targeterror_f(u32 v)
+{
+        return (v & 0x1U) << 15U;
+}
+static inline u32 nvlipt_err_uc_status_link0_targeterror_v(u32 r)
+{
+        return (r >> 15U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_unexpectedresponse_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 nvlipt_err_uc_status_link0_unexpectedresponse_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_receiveroverflow_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 nvlipt_err_uc_status_link0_receiveroverflow_v(u32 r)
+{
+        return (r >> 17U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_malformedpacket_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 nvlipt_err_uc_status_link0_malformedpacket_v(u32 r)
+{
+        return (r >> 18U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_stompedpacketreceived_f(u32 v)
+{
+        return (v & 0x1U) << 19U;
+}
+static inline u32 nvlipt_err_uc_status_link0_stompedpacketreceived_v(u32 r)
+{
+        return (r >> 19U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_unsupportedrequest_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 nvlipt_err_uc_status_link0_unsupportedrequest_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_status_link0_ucinternal_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 nvlipt_err_uc_status_link0_ucinternal_v(u32 r)
+{
+        return (r >> 22U) & 0x1U;
+}
+static inline u32 nvlipt_err_uc_mask_link0_r(void)
+{
+        return 0x00000528U;
+}
+static inline u32 nvlipt_err_uc_severity_link0_r(void)
+{
+        return 0x0000052cU;
+}
+static inline u32 nvlipt_err_uc_first_link0_r(void)
+{
+        return 0x00000530U;
+}
+static inline u32 nvlipt_err_uc_advisory_link0_r(void)
+{
+        return 0x00000534U;
+}
+static inline u32 nvlipt_err_c_status_link0_r(void)
+{
+        return 0x00000538U;
+}
+static inline u32 nvlipt_err_c_mask_link0_r(void)
+{
+        return 0x0000053cU;
+}
+static inline u32 nvlipt_err_c_first_link0_r(void)
+{
+        return 0x00000540U;
+}
+static inline u32 nvlipt_err_control_link0_r(void)
+{
+        return 0x00000544U;
+}
+static inline u32 nvlipt_err_control_link0_fatalenable_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 nvlipt_err_control_link0_fatalenable_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 nvlipt_err_control_link0_fatalenable_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 nvlipt_err_control_link0_nonfatalenable_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 nvlipt_err_control_link0_nonfatalenable_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 nvlipt_err_control_link0_nonfatalenable_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 nvlipt_intr_control_common_r(void)
+{
+        return 0x000004b0U;
+}
+static inline u32 nvlipt_intr_control_common_stallenable_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 nvlipt_intr_control_common_stallenable_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 nvlipt_intr_control_common_stallenable_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 nvlipt_intr_control_common_nonstallenable_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 nvlipt_intr_control_common_nonstallenable_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 nvlipt_intr_control_common_nonstallenable_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 nvlipt_scratch_cold_r(void)
+{
+        return 0x000007d4U;
+}
+static inline u32 nvlipt_scratch_cold_data_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 nvlipt_scratch_cold_data_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 nvlipt_scratch_cold_data_init_v(void)
+{
+        return 0xdeadbaadU;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h b/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h
new file mode 100644
index 0000000..cc31b12
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_nvtlc_gv100.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_nvtlc_gv100_h_
+#define _hw_nvtlc_gv100_h_
+
+static inline u32 nvtlc_tx_err_report_en_0_r(void)
+{
+        return 0x00000708U;
+}
+static inline u32 nvtlc_rx_err_report_en_0_r(void)
+{
+        return 0x00000f08U;
+}
+static inline u32 nvtlc_rx_err_report_en_1_r(void)
+{
+        return 0x00000f20U;
+}
+static inline u32 nvtlc_tx_err_status_0_r(void)
+{
+        return 0x00000700U;
+}
+static inline u32 nvtlc_rx_err_status_0_r(void)
+{
+        return 0x00000f00U;
+}
+static inline u32 nvtlc_rx_err_status_1_r(void)
+{
+        return 0x00000f18U;
+}
+static inline u32 nvtlc_tx_err_first_0_r(void)
+{
+        return 0x00000714U;
+}
+static inline u32 nvtlc_rx_err_first_0_r(void)
+{
+        return 0x00000f14U;
+}
+static inline u32 nvtlc_rx_err_first_1_r(void)
+{
+        return 0x00000f2cU;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_pbdma_gv100.h b/include/nvgpu/hw/gv100/hw_pbdma_gv100.h
new file mode 100644
index 0000000..41d7d1b
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_pbdma_gv100.h
@@ -0,0 +1,651 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pbdma_gv100_h_
+#define _hw_pbdma_gv100_h_
+
+static inline u32 pbdma_gp_entry1_r(void)
+{
+        return 0x10000004U;
+}
+static inline u32 pbdma_gp_entry1_get_hi_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 pbdma_gp_entry1_length_f(u32 v)
+{
+        return (v & 0x1fffffU) << 10U;
+}
+static inline u32 pbdma_gp_entry1_length_v(u32 r)
+{
+        return (r >> 10U) & 0x1fffffU;
+}
+static inline u32 pbdma_gp_base_r(u32 i)
+{
+        return 0x00040048U + i*8192U;
+}
+static inline u32 pbdma_gp_base__size_1_v(void)
+{
+        return 0x0000000eU;
+}
+static inline u32 pbdma_gp_base_offset_f(u32 v)
+{
+        return (v & 0x1fffffffU) << 3U;
+}
+static inline u32 pbdma_gp_base_rsvd_s(void)
+{
+        return 3U;
+}
+static inline u32 pbdma_gp_base_hi_r(u32 i)
+{
+        return 0x0004004cU + i*8192U;
+}
+static inline u32 pbdma_gp_base_hi_offset_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pbdma_gp_base_hi_limit2_f(u32 v)
+{
+        return (v & 0x1fU) << 16U;
+}
+static inline u32 pbdma_gp_fetch_r(u32 i)
+{
+        return 0x00040050U + i*8192U;
+}
+static inline u32 pbdma_gp_get_r(u32 i)
+{
+        return 0x00040014U + i*8192U;
+}
+static inline u32 pbdma_gp_put_r(u32 i)
+{
+        return 0x00040000U + i*8192U;
+}
+static inline u32 pbdma_pb_fetch_r(u32 i)
+{
+        return 0x00040054U + i*8192U;
+}
+static inline u32 pbdma_pb_fetch_hi_r(u32 i)
+{
+        return 0x00040058U + i*8192U;
+}
+static inline u32 pbdma_get_r(u32 i)
+{
+        return 0x00040018U + i*8192U;
+}
+static inline u32 pbdma_get_hi_r(u32 i)
+{
+        return 0x0004001cU + i*8192U;
+}
+static inline u32 pbdma_put_r(u32 i)
+{
+        return 0x0004005cU + i*8192U;
+}
+static inline u32 pbdma_put_hi_r(u32 i)
+{
+        return 0x00040060U + i*8192U;
+}
+static inline u32 pbdma_pb_header_r(u32 i)
+{
+        return 0x00040084U + i*8192U;
+}
+static inline u32 pbdma_pb_header_priv_user_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_method_zero_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_subchannel_zero_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_level_main_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_pb_header_first_true_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 pbdma_pb_header_type_inc_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_pb_header_type_non_inc_f(void)
+{
+        return 0x60000000U;
+}
+static inline u32 pbdma_hdr_shadow_r(u32 i)
+{
+        return 0x00040118U + i*8192U;
+}
+static inline u32 pbdma_gp_shadow_0_r(u32 i)
+{
+        return 0x00040110U + i*8192U;
+}
+static inline u32 pbdma_gp_shadow_1_r(u32 i)
+{
+        return 0x00040114U + i*8192U;
+}
+static inline u32 pbdma_subdevice_r(u32 i)
+{
+        return 0x00040094U + i*8192U;
+}
+static inline u32 pbdma_subdevice_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 pbdma_subdevice_status_active_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 pbdma_subdevice_channel_dma_enable_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_method0_r(u32 i)
+{
+        return 0x000400c0U + i*8192U;
+}
+static inline u32 pbdma_method0_fifo_size_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pbdma_method0_addr_f(u32 v)
+{
+        return (v & 0xfffU) << 2U;
+}
+static inline u32 pbdma_method0_addr_v(u32 r)
+{
+        return (r >> 2U) & 0xfffU;
+}
+static inline u32 pbdma_method0_subch_v(u32 r)
+{
+        return (r >> 16U) & 0x7U;
+}
+static inline u32 pbdma_method0_first_true_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 pbdma_method0_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_method1_r(u32 i)
+{
+        return 0x000400c8U + i*8192U;
+}
+static inline u32 pbdma_method2_r(u32 i)
+{
+        return 0x000400d0U + i*8192U;
+}
+static inline u32 pbdma_method3_r(u32 i)
+{
+        return 0x000400d8U + i*8192U;
+}
+static inline u32 pbdma_data0_r(u32 i)
+{
+        return 0x000400c4U + i*8192U;
+}
+static inline u32 pbdma_acquire_r(u32 i)
+{
+        return 0x00040030U + i*8192U;
+}
+static inline u32 pbdma_acquire_retry_man_2_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pbdma_acquire_retry_exp_2_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_acquire_timeout_exp_f(u32 v)
+{
+        return (v & 0xfU) << 11U;
+}
+static inline u32 pbdma_acquire_timeout_exp_max_v(void)
+{
+        return 0x0000000fU;
+}
+static inline u32 pbdma_acquire_timeout_exp_max_f(void)
+{
+        return 0x7800U;
+}
+static inline u32 pbdma_acquire_timeout_man_f(u32 v)
+{
+        return (v & 0xffffU) << 15U;
+}
+static inline u32 pbdma_acquire_timeout_man_max_v(void)
+{
+        return 0x0000ffffU;
+}
+static inline u32 pbdma_acquire_timeout_man_max_f(void)
+{
+        return 0x7fff8000U;
+}
+static inline u32 pbdma_acquire_timeout_en_enable_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_acquire_timeout_en_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_status_r(u32 i)
+{
+        return 0x00040100U + i*8192U;
+}
+static inline u32 pbdma_channel_r(u32 i)
+{
+        return 0x00040120U + i*8192U;
+}
+static inline u32 pbdma_signature_r(u32 i)
+{
+        return 0x00040010U + i*8192U;
+}
+static inline u32 pbdma_signature_hw_valid_f(void)
+{
+        return 0xfaceU;
+}
+static inline u32 pbdma_signature_sw_zero_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_userd_r(u32 i)
+{
+        return 0x00040008U + i*8192U;
+}
+static inline u32 pbdma_userd_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_userd_target_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pbdma_userd_target_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 pbdma_userd_addr_f(u32 v)
+{
+        return (v & 0x7fffffU) << 9U;
+}
+static inline u32 pbdma_config_r(u32 i)
+{
+        return 0x000400f4U + i*8192U;
+}
+static inline u32 pbdma_config_l2_evict_first_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_config_l2_evict_normal_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pbdma_config_ce_split_enable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_config_ce_split_disable_f(void)
+{
+        return 0x10U;
+}
+static inline u32 pbdma_config_auth_level_non_privileged_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_config_auth_level_privileged_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_config_userd_writeback_disable_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_config_userd_writeback_enable_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 pbdma_userd_hi_r(u32 i)
+{
+        return 0x0004000cU + i*8192U;
+}
+static inline u32 pbdma_userd_hi_addr_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pbdma_hce_ctrl_r(u32 i)
+{
+        return 0x000400e4U + i*8192U;
+}
+static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pbdma_intr_0_r(u32 i)
+{
+        return 0x00040108U + i*8192U;
+}
+static inline u32 pbdma_intr_0_memreq_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pbdma_intr_0_memreq_pending_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pbdma_intr_0_memack_timeout_pending_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pbdma_intr_0_memack_extra_pending_f(void)
+{
+        return 0x4U;
+}
+static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void)
+{
+        return 0x8U;
+}
+static inline u32 pbdma_intr_0_memdat_extra_pending_f(void)
+{
+        return 0x10U;
+}
+static inline u32 pbdma_intr_0_memflush_pending_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pbdma_intr_0_memop_pending_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pbdma_intr_0_lbconnect_pending_f(void)
+{
+        return 0x80U;
+}
+static inline u32 pbdma_intr_0_lbreq_pending_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_intr_0_lback_timeout_pending_f(void)
+{
+        return 0x200U;
+}
+static inline u32 pbdma_intr_0_lback_extra_pending_f(void)
+{
+        return 0x400U;
+}
+static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void)
+{
+        return 0x800U;
+}
+static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void)
+{
+        return 0x1000U;
+}
+static inline u32 pbdma_intr_0_gpfifo_pending_f(void)
+{
+        return 0x2000U;
+}
+static inline u32 pbdma_intr_0_gpptr_pending_f(void)
+{
+        return 0x4000U;
+}
+static inline u32 pbdma_intr_0_gpentry_pending_f(void)
+{
+        return 0x8000U;
+}
+static inline u32 pbdma_intr_0_gpcrc_pending_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 pbdma_intr_0_pbptr_pending_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 pbdma_intr_0_pbentry_pending_f(void)
+{
+        return 0x40000U;
+}
+static inline u32 pbdma_intr_0_pbcrc_pending_f(void)
+{
+        return 0x80000U;
+}
+static inline u32 pbdma_intr_0_clear_faulted_error_pending_f(void)
+{
+        return 0x100000U;
+}
+static inline u32 pbdma_intr_0_method_pending_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 pbdma_intr_0_methodcrc_pending_f(void)
+{
+        return 0x400000U;
+}
+static inline u32 pbdma_intr_0_device_pending_f(void)
+{
+        return 0x800000U;
+}
+static inline u32 pbdma_intr_0_eng_reset_pending_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 pbdma_intr_0_semaphore_pending_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 pbdma_intr_0_acquire_pending_f(void)
+{
+        return 0x4000000U;
+}
+static inline u32 pbdma_intr_0_pri_pending_f(void)
+{
+        return 0x8000000U;
+}
+static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_intr_0_pbseg_pending_f(void)
+{
+        return 0x40000000U;
+}
+static inline u32 pbdma_intr_0_signature_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_intr_1_r(u32 i)
+{
+        return 0x00040148U + i*8192U;
+}
+static inline u32 pbdma_intr_1_ctxnotvalid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_intr_en_0_r(u32 i)
+{
+        return 0x0004010cU + i*8192U;
+}
+static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_intr_en_1_r(u32 i)
+{
+        return 0x0004014cU + i*8192U;
+}
+static inline u32 pbdma_intr_stall_r(u32 i)
+{
+        return 0x0004013cU + i*8192U;
+}
+static inline u32 pbdma_intr_stall_lbreq_enabled_f(void)
+{
+        return 0x100U;
+}
+static inline u32 pbdma_intr_stall_1_r(u32 i)
+{
+        return 0x00040140U + i*8192U;
+}
+static inline u32 pbdma_intr_stall_1_hce_illegal_op_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pbdma_udma_nop_r(void)
+{
+        return 0x00000008U;
+}
+static inline u32 pbdma_runlist_timeslice_r(u32 i)
+{
+        return 0x000400f8U + i*8192U;
+}
+static inline u32 pbdma_runlist_timeslice_timeout_128_f(void)
+{
+        return 0x80U;
+}
+static inline u32 pbdma_runlist_timeslice_timescale_3_f(void)
+{
+        return 0x3000U;
+}
+static inline u32 pbdma_runlist_timeslice_enable_true_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 pbdma_target_r(u32 i)
+{
+        return 0x000400acU + i*8192U;
+}
+static inline u32 pbdma_target_engine_sw_f(void)
+{
+        return 0x1fU;
+}
+static inline u32 pbdma_target_eng_ctx_valid_true_f(void)
+{
+        return 0x10000U;
+}
+static inline u32 pbdma_target_eng_ctx_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_target_ce_ctx_valid_true_f(void)
+{
+        return 0x20000U;
+}
+static inline u32 pbdma_target_ce_ctx_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_target_host_tsg_event_reason_pbdma_idle_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_target_host_tsg_event_reason_semaphore_acquire_failure_f(void)
+{
+        return 0x1000000U;
+}
+static inline u32 pbdma_target_host_tsg_event_reason_tsg_yield_f(void)
+{
+        return 0x2000000U;
+}
+static inline u32 pbdma_target_host_tsg_event_reason_host_subchannel_switch_f(void)
+{
+        return 0x3000000U;
+}
+static inline u32 pbdma_target_should_send_tsg_event_true_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pbdma_target_should_send_tsg_event_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_target_needs_host_tsg_event_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 pbdma_target_needs_host_tsg_event_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pbdma_set_channel_info_r(u32 i)
+{
+        return 0x000400fcU + i*8192U;
+}
+static inline u32 pbdma_set_channel_info_veid_f(u32 v)
+{
+        return (v & 0x3fU) << 8U;
+}
+static inline u32 pbdma_timeout_r(u32 i)
+{
+        return 0x0004012cU + i*8192U;
+}
+static inline u32 pbdma_timeout_period_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 pbdma_timeout_period_max_f(void)
+{
+        return 0xffffffffU;
+}
+static inline u32 pbdma_timeout_period_init_f(void)
+{
+        return 0x10000U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_perf_gv100.h b/include/nvgpu/hw/gv100/hw_perf_gv100.h
new file mode 100644
index 0000000..40107ee
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_perf_gv100.h
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_perf_gv100_h_
+#define _hw_perf_gv100_h_
+
+static inline u32 perf_pmmgpc_perdomain_offset_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 perf_pmmsys_perdomain_offset_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 perf_pmmgpc_base_v(void)
+{
+        return 0x00180000U;
+}
+static inline u32 perf_pmmgpc_extent_v(void)
+{
+        return 0x00183fffU;
+}
+static inline u32 perf_pmmsys_base_v(void)
+{
+        return 0x00240000U;
+}
+static inline u32 perf_pmmsys_extent_v(void)
+{
+        return 0x00243fffU;
+}
+static inline u32 perf_pmmfbp_base_v(void)
+{
+        return 0x00200000U;
+}
+static inline u32 perf_pmasys_control_r(void)
+{
+        return 0x0024a000U;
+}
+static inline u32 perf_pmasys_control_membuf_status_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void)
+{
+        return 0x10U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void)
+{
+        return 0x20U;
+}
+static inline u32 perf_pmasys_mem_block_r(void)
+{
+        return 0x0024a070U;
+}
+static inline u32 perf_pmasys_mem_block_base_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 perf_pmasys_mem_block_target_f(u32 v)
+{
+        return (v & 0x3U) << 28U;
+}
+static inline u32 perf_pmasys_mem_block_target_v(u32 r)
+{
+        return (r >> 28U) & 0x3U;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 perf_pmasys_mem_block_target_lfb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 perf_pmasys_mem_block_valid_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 perf_pmasys_mem_block_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_mem_block_valid_true_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 perf_pmasys_mem_block_valid_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 perf_pmasys_outbase_r(void)
+{
+        return 0x0024a074U;
+}
+static inline u32 perf_pmasys_outbase_ptr_f(u32 v)
+{
+        return (v & 0x7ffffffU) << 5U;
+}
+static inline u32 perf_pmasys_outbaseupper_r(void)
+{
+        return 0x0024a078U;
+}
+static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 perf_pmasys_outsize_r(void)
+{
+        return 0x0024a07cU;
+}
+static inline u32 perf_pmasys_outsize_numbytes_f(u32 v)
+{
+        return (v & 0x7ffffffU) << 5U;
+}
+static inline u32 perf_pmasys_mem_bytes_r(void)
+{
+        return 0x0024a084U;
+}
+static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 perf_pmasys_mem_bump_r(void)
+{
+        return 0x0024a088U;
+}
+static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v)
+{
+        return (v & 0xfffffffU) << 4U;
+}
+static inline u32 perf_pmasys_enginestatus_r(void)
+{
+        return 0x0024a0a4U;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void)
+{
+        return 0x10U;
+}
+static inline u32 perf_pmmsys_engine_sel_r(u32 i)
+{
+        return 0x0024006cU + i*512U;
+}
+static inline u32 perf_pmmsys_engine_sel__size_1_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 perf_pmmfbp_engine_sel_r(u32 i)
+{
+        return 0x0020006cU + i*512U;
+}
+static inline u32 perf_pmmfbp_engine_sel__size_1_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 perf_pmmgpc_engine_sel_r(u32 i)
+{
+        return 0x0018006cU + i*512U;
+}
+static inline u32 perf_pmmgpc_engine_sel__size_1_v(void)
+{
+        return 0x00000020U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_pgsp_gv100.h b/include/nvgpu/hw/gv100/hw_pgsp_gv100.h
new file mode 100644
index 0000000..34d0eae
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_pgsp_gv100.h
@@ -0,0 +1,643 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pgsp_gv100_h_
+#define _hw_pgsp_gv100_h_
+
+static inline u32 pgsp_falcon_irqsset_r(void)
+{
+        return 0x00110000U;
+}
+static inline u32 pgsp_falcon_irqsset_swgen0_set_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pgsp_falcon_irqsclr_r(void)
+{
+        return 0x00110004U;
+}
+static inline u32 pgsp_falcon_irqstat_r(void)
+{
+        return 0x00110008U;
+}
+static inline u32 pgsp_falcon_irqstat_halt_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 pgsp_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pgsp_falcon_irqstat_swgen0_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pgsp_falcon_irqmode_r(void)
+{
+        return 0x0011000cU;
+}
+static inline u32 pgsp_falcon_irqmset_r(void)
+{
+        return 0x00110010U;
+}
+static inline u32 pgsp_falcon_irqmset_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pgsp_falcon_irqmset_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pgsp_falcon_irqmset_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pgsp_falcon_irqmset_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pgsp_falcon_irqmset_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pgsp_falcon_irqmset_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pgsp_falcon_irqmset_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pgsp_falcon_irqmset_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pgsp_falcon_irqmclr_r(void)
+{
+        return 0x00110014U;
+}
+static inline u32 pgsp_falcon_irqmclr_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pgsp_falcon_irqmclr_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pgsp_falcon_irqmclr_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pgsp_falcon_irqmclr_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pgsp_falcon_irqmclr_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pgsp_falcon_irqmclr_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pgsp_falcon_irqmclr_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pgsp_falcon_irqmclr_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pgsp_falcon_irqmclr_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pgsp_falcon_irqmask_r(void)
+{
+        return 0x00110018U;
+}
+static inline u32 pgsp_falcon_irqdest_r(void)
+{
+        return 0x0011001cU;
+}
+static inline u32 pgsp_falcon_irqdest_host_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pgsp_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pgsp_falcon_irqdest_host_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pgsp_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pgsp_falcon_irqdest_host_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pgsp_falcon_irqdest_host_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pgsp_falcon_irqdest_host_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pgsp_falcon_irqdest_host_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pgsp_falcon_irqdest_host_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pgsp_falcon_irqdest_target_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 pgsp_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 pgsp_falcon_irqdest_target_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 pgsp_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 19U;
+}
+static inline u32 pgsp_falcon_irqdest_target_halt_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 pgsp_falcon_irqdest_target_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 pgsp_falcon_irqdest_target_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 pgsp_falcon_irqdest_target_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 pgsp_falcon_irqdest_target_ext_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 pgsp_falcon_curctx_r(void)
+{
+        return 0x00110050U;
+}
+static inline u32 pgsp_falcon_nxtctx_r(void)
+{
+        return 0x00110054U;
+}
+static inline u32 pgsp_falcon_nxtctx_ctxptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 pgsp_falcon_nxtctx_ctxtgt_fb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pgsp_falcon_nxtctx_ctxtgt_sys_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 pgsp_falcon_nxtctx_ctxvalid_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 pgsp_falcon_mailbox0_r(void)
+{
+        return 0x00110040U;
+}
+static inline u32 pgsp_falcon_mailbox1_r(void)
+{
+        return 0x00110044U;
+}
+static inline u32 pgsp_falcon_itfen_r(void)
+{
+        return 0x00110048U;
+}
+static inline u32 pgsp_falcon_itfen_ctxen_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pgsp_falcon_idlestate_r(void)
+{
+        return 0x0011004cU;
+}
+static inline u32 pgsp_falcon_idlestate_falcon_busy_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pgsp_falcon_idlestate_ext_busy_v(u32 r)
+{
+        return (r >> 1U) & 0x7fffU;
+}
+static inline u32 pgsp_falcon_os_r(void)
+{
+        return 0x00110080U;
+}
+static inline u32 pgsp_falcon_engctl_r(void)
+{
+        return 0x001100a4U;
+}
+static inline u32 pgsp_falcon_engctl_switch_context_true_f(void)
+{
+        return 0x8U;
+}
+static inline u32 pgsp_falcon_engctl_switch_context_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pgsp_falcon_cpuctl_r(void)
+{
+        return 0x00110100U;
+}
+static inline u32 pgsp_falcon_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pgsp_falcon_cpuctl_halt_intr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pgsp_falcon_cpuctl_halt_intr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 pgsp_falcon_cpuctl_halt_intr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 pgsp_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pgsp_falcon_cpuctl_cpuctl_alias_en_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 pgsp_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 pgsp_falcon_cpuctl_alias_r(void)
+{
+        return 0x00110130U;
+}
+static inline u32 pgsp_falcon_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pgsp_falcon_imemc_r(u32 i)
+{
+        return 0x00110180U + i*16U;
+}
+static inline u32 pgsp_falcon_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 pgsp_falcon_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pgsp_falcon_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 pgsp_falcon_imemd_r(u32 i)
+{
+        return 0x00110184U + i*16U;
+}
+static inline u32 pgsp_falcon_imemt_r(u32 i)
+{
+        return 0x00110188U + i*16U;
+}
+static inline u32 pgsp_falcon_sctl_r(void)
+{
+        return 0x00110240U;
+}
+static inline u32 pgsp_falcon_mmu_phys_sec_r(void)
+{
+        return 0x00100ce4U;
+}
+static inline u32 pgsp_falcon_bootvec_r(void)
+{
+        return 0x00110104U;
+}
+static inline u32 pgsp_falcon_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pgsp_falcon_dmactl_r(void)
+{
+        return 0x0011010cU;
+}
+static inline u32 pgsp_falcon_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 pgsp_falcon_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pgsp_falcon_dmactl_require_ctx_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pgsp_falcon_hwcfg_r(void)
+{
+        return 0x00110108U;
+}
+static inline u32 pgsp_falcon_hwcfg_imem_size_v(u32 r)
+{
+        return (r >> 0U) & 0x1ffU;
+}
+static inline u32 pgsp_falcon_hwcfg_dmem_size_v(u32 r)
+{
+        return (r >> 9U) & 0x1ffU;
+}
+static inline u32 pgsp_falcon_dmatrfbase_r(void)
+{
+        return 0x00110110U;
+}
+static inline u32 pgsp_falcon_dmatrfbase1_r(void)
+{
+        return 0x00110128U;
+}
+static inline u32 pgsp_falcon_dmatrfmoffs_r(void)
+{
+        return 0x00110114U;
+}
+static inline u32 pgsp_falcon_dmatrfcmd_r(void)
+{
+        return 0x00110118U;
+}
+static inline u32 pgsp_falcon_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pgsp_falcon_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pgsp_falcon_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 pgsp_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 pgsp_falcon_dmatrffboffs_r(void)
+{
+        return 0x0011011cU;
+}
+static inline u32 pgsp_falcon_exterraddr_r(void)
+{
+        return 0x00110168U;
+}
+static inline u32 pgsp_falcon_exterrstat_r(void)
+{
+        return 0x0011016cU;
+}
+static inline u32 pgsp_falcon_exterrstat_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 pgsp_falcon_exterrstat_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 pgsp_falcon_exterrstat_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pgsp_sec2_falcon_icd_cmd_r(void)
+{
+        return 0x00110200U;
+}
+static inline u32 pgsp_sec2_falcon_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 pgsp_sec2_falcon_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 pgsp_sec2_falcon_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 pgsp_sec2_falcon_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 pgsp_sec2_falcon_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 pgsp_sec2_falcon_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 pgsp_sec2_falcon_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 pgsp_sec2_falcon_icd_rdata_r(void)
+{
+        return 0x0011020cU;
+}
+static inline u32 pgsp_falcon_dmemc_r(u32 i)
+{
+        return 0x001101c0U + i*8U;
+}
+static inline u32 pgsp_falcon_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 pgsp_falcon_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 pgsp_falcon_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pgsp_falcon_dmemc_blk_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 pgsp_falcon_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 pgsp_falcon_dmemc_aincr_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 pgsp_falcon_dmemd_r(u32 i)
+{
+        return 0x001101c4U + i*8U;
+}
+static inline u32 pgsp_falcon_debug1_r(void)
+{
+        return 0x00110090U;
+}
+static inline u32 pgsp_falcon_debug1_ctxsw_mode_s(void)
+{
+        return 1U;
+}
+static inline u32 pgsp_falcon_debug1_ctxsw_mode_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 pgsp_falcon_debug1_ctxsw_mode_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 pgsp_falcon_debug1_ctxsw_mode_v(u32 r)
+{
+        return (r >> 16U) & 0x1U;
+}
+static inline u32 pgsp_falcon_debug1_ctxsw_mode_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pgsp_fbif_transcfg_r(u32 i)
+{
+        return 0x00110600U + i*4U;
+}
+static inline u32 pgsp_fbif_transcfg_target_local_fb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pgsp_fbif_transcfg_target_coherent_sysmem_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pgsp_fbif_transcfg_target_noncoherent_sysmem_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pgsp_fbif_transcfg_mem_type_s(void)
+{
+        return 1U;
+}
+static inline u32 pgsp_fbif_transcfg_mem_type_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pgsp_fbif_transcfg_mem_type_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pgsp_fbif_transcfg_mem_type_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 pgsp_fbif_transcfg_mem_type_virtual_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pgsp_fbif_transcfg_mem_type_physical_f(void)
+{
+        return 0x4U;
+}
+static inline u32 pgsp_falcon_engine_r(void)
+{
+        return 0x001103c0U;
+}
+static inline u32 pgsp_falcon_engine_reset_true_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pgsp_falcon_engine_reset_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pgsp_fbif_ctl_r(void)
+{
+        return 0x00110624U;
+}
+static inline u32 pgsp_fbif_ctl_allow_phys_no_ctx_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pgsp_fbif_ctl_allow_phys_no_ctx_disallow_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pgsp_fbif_ctl_allow_phys_no_ctx_allow_f(void)
+{
+        return 0x80U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_pram_gv100.h b/include/nvgpu/hw/gv100/hw_pram_gv100.h
new file mode 100644
index 0000000..8f005a2
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_pram_gv100.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pram_gv100_h_
+#define _hw_pram_gv100_h_
+
+static inline u32 pram_data032_r(u32 i)
+{
+        return 0x00700000U + i*4U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h b/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h
new file mode 100644
index 0000000..5eca93c
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_pri_ringmaster_gv100.h
@@ -0,0 +1,167 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringmaster_gv100_h_
+#define _hw_pri_ringmaster_gv100_h_
+
+static inline u32 pri_ringmaster_command_r(void)
+{
+        return 0x0012004cU;
+}
+static inline u32 pri_ringmaster_command_cmd_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 pri_ringmaster_command_cmd_v(u32 r)
+{
+        return (r >> 0U) & 0x3fU;
+}
+static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pri_ringmaster_command_cmd_start_ring_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void)
+{
+        return 0x3U;
+}
+static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pri_ringmaster_command_data_r(void)
+{
+        return 0x00120048U;
+}
+static inline u32 pri_ringmaster_start_results_r(void)
+{
+        return 0x00120050U;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pri_ringmaster_intr_status0_r(void)
+{
+        return 0x00120058U;
+}
+static inline u32 pri_ringmaster_intr_status0_ring_start_conn_fault_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status0_disconnect_fault_v(u32 r)
+{
+        return (r >> 1U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status0_overflow_fault_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status0_gbl_write_error_sys_v(u32 r)
+{
+        return (r >> 8U) & 0x1U;
+}
+static inline u32 pri_ringmaster_intr_status1_r(void)
+{
+        return 0x0012005cU;
+}
+static inline u32 pri_ringmaster_global_ctl_r(void)
+{
+        return 0x00120060U;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pri_ringmaster_enum_fbp_r(void)
+{
+        return 0x00120074U;
+}
+static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 pri_ringmaster_enum_gpc_r(void)
+{
+        return 0x00120078U;
+}
+static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 pri_ringmaster_enum_ltc_r(void)
+{
+        return 0x0012006cU;
+}
+static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h b/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h
new file mode 100644
index 0000000..fc522d5
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_pri_ringstation_gpc_gv100.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_gpc_gv100_h_
+#define _hw_pri_ringstation_gpc_gv100_h_
+
+static inline u32 pri_ringstation_gpc_master_config_r(u32 i)
+{
+        return 0x00128300U + i*4U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_adr_r(void)
+{
+        return 0x00128120U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_wrdat_r(void)
+{
+        return 0x00128124U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_info_r(void)
+{
+        return 0x00128128U;
+}
+static inline u32 pri_ringstation_gpc_gpc0_priv_error_code_r(void)
+{
+        return 0x0012812cU;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h b/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h
new file mode 100644
index 0000000..885ea30
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_pri_ringstation_sys_gv100.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pri_ringstation_sys_gv100_h_
+#define _hw_pri_ringstation_sys_gv100_h_
+
+static inline u32 pri_ringstation_sys_master_config_r(u32 i)
+{
+        return 0x00122300U + i*4U;
+}
+static inline u32 pri_ringstation_sys_decode_config_r(void)
+{
+        return 0x00122204U;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pri_ringstation_sys_priv_error_adr_r(void)
+{
+        return 0x00122120U;
+}
+static inline u32 pri_ringstation_sys_priv_error_wrdat_r(void)
+{
+        return 0x00122124U;
+}
+static inline u32 pri_ringstation_sys_priv_error_info_r(void)
+{
+        return 0x00122128U;
+}
+static inline u32 pri_ringstation_sys_priv_error_code_r(void)
+{
+        return 0x0012212cU;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_proj_gv100.h b/include/nvgpu/hw/gv100/hw_proj_gv100.h
new file mode 100644
index 0000000..f46eaa0
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_proj_gv100.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_proj_gv100_h_
+#define _hw_proj_gv100_h_
+
+static inline u32 proj_gpc_base_v(void)
+{
+        return 0x00500000U;
+}
+static inline u32 proj_gpc_shared_base_v(void)
+{
+        return 0x00418000U;
+}
+static inline u32 proj_gpc_stride_v(void)
+{
+        return 0x00008000U;
+}
+static inline u32 proj_gpc_priv_stride_v(void)
+{
+        return 0x00000800U;
+}
+static inline u32 proj_ltc_stride_v(void)
+{
+        return 0x00002000U;
+}
+static inline u32 proj_lts_stride_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 proj_fbpa_base_v(void)
+{
+        return 0x00900000U;
+}
+static inline u32 proj_fbpa_shared_base_v(void)
+{
+        return 0x009a0000U;
+}
+static inline u32 proj_fbpa_stride_v(void)
+{
+        return 0x00004000U;
+}
+static inline u32 proj_ppc_in_gpc_base_v(void)
+{
+        return 0x00003000U;
+}
+static inline u32 proj_ppc_in_gpc_shared_base_v(void)
+{
+        return 0x00003e00U;
+}
+static inline u32 proj_ppc_in_gpc_stride_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 proj_rop_base_v(void)
+{
+        return 0x00410000U;
+}
+static inline u32 proj_rop_shared_base_v(void)
+{
+        return 0x00408800U;
+}
+static inline u32 proj_rop_stride_v(void)
+{
+        return 0x00000400U;
+}
+static inline u32 proj_tpc_in_gpc_base_v(void)
+{
+        return 0x00004000U;
+}
+static inline u32 proj_tpc_in_gpc_stride_v(void)
+{
+        return 0x00000800U;
+}
+static inline u32 proj_tpc_in_gpc_shared_base_v(void)
+{
+        return 0x00001800U;
+}
+static inline u32 proj_smpc_base_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 proj_smpc_shared_base_v(void)
+{
+        return 0x00000300U;
+}
+static inline u32 proj_smpc_unique_base_v(void)
+{
+        return 0x00000600U;
+}
+static inline u32 proj_smpc_stride_v(void)
+{
+        return 0x00000100U;
+}
+static inline u32 proj_host_num_engines_v(void)
+{
+        return 0x0000000fU;
+}
+static inline u32 proj_host_num_pbdma_v(void)
+{
+        return 0x0000000eU;
+}
+static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 proj_scal_litter_num_fbps_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 proj_scal_litter_num_fbpas_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 proj_scal_litter_num_gpcs_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 proj_scal_litter_num_pes_per_gpc_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 proj_scal_litter_num_zcull_banks_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 proj_scal_litter_num_sm_per_tpc_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 proj_scal_max_gpcs_v(void)
+{
+        return 0x00000020U;
+}
+static inline u32 proj_scal_max_tpc_per_gpc_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 proj_sm_stride_v(void)
+{
+        return 0x00000080U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_pwr_gv100.h b/include/nvgpu/hw/gv100/hw_pwr_gv100.h
new file mode 100644
index 0000000..c719226
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_pwr_gv100.h
@@ -0,0 +1,983 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_pwr_gv100_h_
+#define _hw_pwr_gv100_h_
+
+static inline u32 pwr_falcon_irqsset_r(void)
+{
+        return 0x0010a000U;
+}
+static inline u32 pwr_falcon_irqsset_swgen0_set_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pwr_falcon_irqsclr_r(void)
+{
+        return 0x0010a004U;
+}
+static inline u32 pwr_falcon_irqstat_r(void)
+{
+        return 0x0010a008U;
+}
+static inline u32 pwr_falcon_irqstat_halt_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 pwr_falcon_irqstat_exterr_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 pwr_falcon_irqstat_swgen0_true_f(void)
+{
+        return 0x40U;
+}
+static inline u32 pwr_falcon_irqstat_ext_second_true_f(void)
+{
+        return 0x800U;
+}
+static inline u32 pwr_falcon_irqmode_r(void)
+{
+        return 0x0010a00cU;
+}
+static inline u32 pwr_falcon_irqmset_r(void)
+{
+        return 0x0010a010U;
+}
+static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_irqmset_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pwr_falcon_irqmset_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_irqmset_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pwr_falcon_irqmset_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_irqmset_ext_ctxe_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 pwr_falcon_irqmset_ext_limitv_f(u32 v)
+{
+        return (v & 0x1U) << 9U;
+}
+static inline u32 pwr_falcon_irqmset_ext_second_f(u32 v)
+{
+        return (v & 0x1U) << 11U;
+}
+static inline u32 pwr_falcon_irqmset_ext_therm_f(u32 v)
+{
+        return (v & 0x1U) << 12U;
+}
+static inline u32 pwr_falcon_irqmset_ext_miscio_f(u32 v)
+{
+        return (v & 0x1U) << 13U;
+}
+static inline u32 pwr_falcon_irqmset_ext_rttimer_f(u32 v)
+{
+        return (v & 0x1U) << 14U;
+}
+static inline u32 pwr_falcon_irqmclr_r(void)
+{
+        return 0x0010a014U;
+}
+static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pwr_falcon_irqmclr_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pwr_falcon_irqmclr_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_irqmclr_ext_ctxe_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 pwr_falcon_irqmclr_ext_limitv_f(u32 v)
+{
+        return (v & 0x1U) << 9U;
+}
+static inline u32 pwr_falcon_irqmclr_ext_second_f(u32 v)
+{
+        return (v & 0x1U) << 11U;
+}
+static inline u32 pwr_falcon_irqmclr_ext_therm_f(u32 v)
+{
+        return (v & 0x1U) << 12U;
+}
+static inline u32 pwr_falcon_irqmclr_ext_miscio_f(u32 v)
+{
+        return (v & 0x1U) << 13U;
+}
+static inline u32 pwr_falcon_irqmclr_ext_rttimer_f(u32 v)
+{
+        return (v & 0x1U) << 14U;
+}
+static inline u32 pwr_falcon_irqmask_r(void)
+{
+        return 0x0010a018U;
+}
+static inline u32 pwr_falcon_irqdest_r(void)
+{
+        return 0x0010a01cU;
+}
+static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_ctxe_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_limitv_f(u32 v)
+{
+        return (v & 0x1U) << 9U;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_second_f(u32 v)
+{
+        return (v & 0x1U) << 11U;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_therm_f(u32 v)
+{
+        return (v & 0x1U) << 12U;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_miscio_f(u32 v)
+{
+        return (v & 0x1U) << 13U;
+}
+static inline u32 pwr_falcon_irqdest_host_ext_rttimer_f(u32 v)
+{
+        return (v & 0x1U) << 14U;
+}
+static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v)
+{
+        return (v & 0x1U) << 17U;
+}
+static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v)
+{
+        return (v & 0x1U) << 18U;
+}
+static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v)
+{
+        return (v & 0x1U) << 19U;
+}
+static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v)
+{
+        return (v & 0x1U) << 21U;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v)
+{
+        return (v & 0x1U) << 22U;
+}
+static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v)
+{
+        return (v & 0x1U) << 23U;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_ctxe_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_limitv_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_second_f(u32 v)
+{
+        return (v & 0x1U) << 27U;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_therm_f(u32 v)
+{
+        return (v & 0x1U) << 28U;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_miscio_f(u32 v)
+{
+        return (v & 0x1U) << 29U;
+}
+static inline u32 pwr_falcon_irqdest_target_ext_rttimer_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 pwr_falcon_curctx_r(void)
+{
+        return 0x0010a050U;
+}
+static inline u32 pwr_falcon_nxtctx_r(void)
+{
+        return 0x0010a054U;
+}
+static inline u32 pwr_falcon_mailbox0_r(void)
+{
+        return 0x0010a040U;
+}
+static inline u32 pwr_falcon_mailbox1_r(void)
+{
+        return 0x0010a044U;
+}
+static inline u32 pwr_falcon_itfen_r(void)
+{
+        return 0x0010a048U;
+}
+static inline u32 pwr_falcon_itfen_ctxen_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_falcon_idlestate_r(void)
+{
+        return 0x0010a04cU;
+}
+static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r)
+{
+        return (r >> 1U) & 0x7fffU;
+}
+static inline u32 pwr_falcon_os_r(void)
+{
+        return 0x0010a080U;
+}
+static inline u32 pwr_falcon_engctl_r(void)
+{
+        return 0x0010a0a4U;
+}
+static inline u32 pwr_falcon_cpuctl_r(void)
+{
+        return 0x0010a100U;
+}
+static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
+{
+        return (v & 0x1U) << 6U;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void)
+{
+        return 0x1U << 6U;
+}
+static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
+{
+        return (r >> 6U) & 0x1U;
+}
+static inline u32 pwr_falcon_cpuctl_alias_r(void)
+{
+        return 0x0010a130U;
+}
+static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 pwr_pmu_scpctl_stat_r(void)
+{
+        return 0x0010ac08U;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v)
+{
+        return (v & 0x1U) << 20U;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void)
+{
+        return 0x1U << 20U;
+}
+static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r)
+{
+        return (r >> 20U) & 0x1U;
+}
+static inline u32 pwr_falcon_imemc_r(u32 i)
+{
+        return 0x0010a180U + i*16U;
+}
+static inline u32 pwr_falcon_imemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 pwr_falcon_imemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_imemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 pwr_falcon_imemd_r(u32 i)
+{
+        return 0x0010a184U + i*16U;
+}
+static inline u32 pwr_falcon_imemt_r(u32 i)
+{
+        return 0x0010a188U + i*16U;
+}
+static inline u32 pwr_falcon_sctl_r(void)
+{
+        return 0x0010a240U;
+}
+static inline u32 pwr_falcon_mmu_phys_sec_r(void)
+{
+        return 0x00100ce4U;
+}
+static inline u32 pwr_falcon_bootvec_r(void)
+{
+        return 0x0010a104U;
+}
+static inline u32 pwr_falcon_bootvec_vec_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_falcon_dmactl_r(void)
+{
+        return 0x0010a10cU;
+}
+static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pwr_falcon_hwcfg_r(void)
+{
+        return 0x0010a108U;
+}
+static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r)
+{
+        return (r >> 0U) & 0x1ffU;
+}
+static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r)
+{
+        return (r >> 9U) & 0x1ffU;
+}
+static inline u32 pwr_falcon_dmatrfbase_r(void)
+{
+        return 0x0010a110U;
+}
+static inline u32 pwr_falcon_dmatrfbase1_r(void)
+{
+        return 0x0010a128U;
+}
+static inline u32 pwr_falcon_dmatrfmoffs_r(void)
+{
+        return 0x0010a114U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_r(void)
+{
+        return 0x0010a118U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v)
+{
+        return (v & 0x7U) << 8U;
+}
+static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v)
+{
+        return (v & 0x7U) << 12U;
+}
+static inline u32 pwr_falcon_dmatrffboffs_r(void)
+{
+        return 0x0010a11cU;
+}
+static inline u32 pwr_falcon_exterraddr_r(void)
+{
+        return 0x0010a168U;
+}
+static inline u32 pwr_falcon_exterrstat_r(void)
+{
+        return 0x0010a16cU;
+}
+static inline u32 pwr_falcon_exterrstat_valid_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 pwr_falcon_exterrstat_valid_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 pwr_falcon_exterrstat_valid_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_r(void)
+{
+        return 0x0010a200U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void)
+{
+        return 4U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r)
+{
+        return (r >> 0U) & 0xfU;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void)
+{
+        return 0xeU;
+}
+static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 pwr_pmu_falcon_icd_rdata_r(void)
+{
+        return 0x0010a20cU;
+}
+static inline u32 pwr_falcon_dmemc_r(u32 i)
+{
+        return 0x0010a1c0U + i*8U;
+}
+static inline u32 pwr_falcon_dmemc_offs_f(u32 v)
+{
+        return (v & 0x3fU) << 2U;
+}
+static inline u32 pwr_falcon_dmemc_offs_m(void)
+{
+        return 0x3fU << 2U;
+}
+static inline u32 pwr_falcon_dmemc_blk_f(u32 v)
+{
+        return (v & 0xffU) << 8U;
+}
+static inline u32 pwr_falcon_dmemc_blk_m(void)
+{
+        return 0xffU << 8U;
+}
+static inline u32 pwr_falcon_dmemc_aincw_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 pwr_falcon_dmemc_aincr_f(u32 v)
+{
+        return (v & 0x1U) << 25U;
+}
+static inline u32 pwr_falcon_dmemd_r(u32 i)
+{
+        return 0x0010a1c4U + i*8U;
+}
+static inline u32 pwr_pmu_new_instblk_r(void)
+{
+        return 0x0010a480U;
+}
+static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v)
+{
+        return (v & 0xfffffffU) << 0U;
+}
+static inline u32 pwr_pmu_new_instblk_target_fb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 pwr_pmu_new_instblk_target_sys_ncoh_f(void)
+{
+        return 0x30000000U;
+}
+static inline u32 pwr_pmu_new_instblk_valid_f(u32 v)
+{
+        return (v & 0x1U) << 30U;
+}
+static inline u32 pwr_pmu_mutex_id_r(void)
+{
+        return 0x0010a488U;
+}
+static inline u32 pwr_pmu_mutex_id_value_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 pwr_pmu_mutex_id_value_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void)
+{
+        return 0x000000ffU;
+}
+static inline u32 pwr_pmu_mutex_id_release_r(void)
+{
+        return 0x0010a48cU;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_m(void)
+{
+        return 0xffU << 0U;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_mutex_id_release_value_init_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_mutex_r(u32 i)
+{
+        return 0x0010a580U + i*4U;
+}
+static inline u32 pwr_pmu_mutex__size_1_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 pwr_pmu_mutex_value_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 pwr_pmu_mutex_value_v(u32 r)
+{
+        return (r >> 0U) & 0xffU;
+}
+static inline u32 pwr_pmu_mutex_value_initial_lock_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_queue_head_r(u32 i)
+{
+        return 0x0010a800U + i*4U;
+}
+static inline u32 pwr_pmu_queue_head__size_1_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 pwr_pmu_queue_head_address_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_queue_head_address_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_queue_tail_r(u32 i)
+{
+        return 0x0010a820U + i*4U;
+}
+static inline u32 pwr_pmu_queue_tail__size_1_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 pwr_pmu_queue_tail_address_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_queue_tail_address_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_msgq_head_r(void)
+{
+        return 0x0010a4c8U;
+}
+static inline u32 pwr_pmu_msgq_head_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_msgq_head_val_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_msgq_tail_r(void)
+{
+        return 0x0010a4ccU;
+}
+static inline u32 pwr_pmu_msgq_tail_val_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 pwr_pmu_msgq_tail_val_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffffU;
+}
+static inline u32 pwr_pmu_idle_mask_r(u32 i)
+{
+        return 0x0010a504U + i*16U;
+}
+static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void)
+{
+        return 0x200000U;
+}
+static inline u32 pwr_pmu_idle_count_r(u32 i)
+{
+        return 0x0010a508U + i*16U;
+}
+static inline u32 pwr_pmu_idle_count_value_f(u32 v)
+{
+        return (v & 0x7fffffffU) << 0U;
+}
+static inline u32 pwr_pmu_idle_count_value_v(u32 r)
+{
+        return (r >> 0U) & 0x7fffffffU;
+}
+static inline u32 pwr_pmu_idle_count_reset_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 pwr_pmu_idle_ctrl_r(u32 i)
+{
+        return 0x0010a50cU + i*16U;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pwr_pmu_idle_ctrl_value_always_f(void)
+{
+        return 0x3U;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_pmu_idle_threshold_r(u32 i)
+{
+        return 0x0010a8a0U + i*4U;
+}
+static inline u32 pwr_pmu_idle_threshold_value_f(u32 v)
+{
+        return (v & 0x7fffffffU) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_r(void)
+{
+        return 0x0010a9e8U;
+}
+static inline u32 pwr_pmu_idle_intr_en_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_en_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 pwr_pmu_idle_intr_en_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_idle_intr_status_r(void)
+{
+        return 0x0010a9ecU;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_m(void)
+{
+        return U32(0x1U) << 0U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_pending_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_idle_intr_status_intr_clear_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 pwr_pmu_idle_mask_supp_r(u32 i)
+{
+        return 0x0010a9f0U + i*8U;
+}
+static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i)
+{
+        return 0x0010a9f4U + i*8U;
+}
+static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i)
+{
+        return 0x0010aa30U + i*8U;
+}
+static inline u32 pwr_pmu_debug_r(u32 i)
+{
+        return 0x0010a5c0U + i*4U;
+}
+static inline u32 pwr_pmu_debug__size_1_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 pwr_pmu_mailbox_r(u32 i)
+{
+        return 0x0010a450U + i*4U;
+}
+static inline u32 pwr_pmu_mailbox__size_1_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 pwr_pmu_bar0_addr_r(void)
+{
+        return 0x0010a7a0U;
+}
+static inline u32 pwr_pmu_bar0_data_r(void)
+{
+        return 0x0010a7a4U;
+}
+static inline u32 pwr_pmu_bar0_ctl_r(void)
+{
+        return 0x0010a7acU;
+}
+static inline u32 pwr_pmu_bar0_timeout_r(void)
+{
+        return 0x0010a7a8U;
+}
+static inline u32 pwr_pmu_bar0_fecs_error_r(void)
+{
+        return 0x0010a988U;
+}
+static inline u32 pwr_pmu_bar0_error_status_r(void)
+{
+        return 0x0010a7b0U;
+}
+static inline u32 pwr_pmu_pg_idlefilth_r(u32 i)
+{
+        return 0x0010a6c0U + i*4U;
+}
+static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i)
+{
+        return 0x0010a6e8U + i*4U;
+}
+static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i)
+{
+        return 0x0010a710U + i*4U;
+}
+static inline u32 pwr_pmu_pg_intren_r(u32 i)
+{
+        return 0x0010a760U + i*4U;
+}
+static inline u32 pwr_fbif_transcfg_r(u32 i)
+{
+        return 0x0010ae00U + i*4U;
+}
+static inline u32 pwr_fbif_transcfg_target_local_fb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void)
+{
+        return 0x1U;
+}
+static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void)
+{
+        return 0x2U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_s(void)
+{
+        return 1U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void)
+{
+        return 0x0U;
+}
+static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void)
+{
+        return 0x4U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_ram_gv100.h b/include/nvgpu/hw/gv100/hw_ram_gv100.h
new file mode 100644
index 0000000..55aa25f
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_ram_gv100.h
@@ -0,0 +1,791 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_ram_gv100_h_
+#define _hw_ram_gv100_h_
+
+static inline u32 ram_in_ramfc_s(void)
+{
+        return 4096U;
+}
+static inline u32 ram_in_ramfc_w(void)
+{
+        return 0U;
+}
+static inline u32 ram_in_page_dir_base_target_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ram_in_page_dir_base_target_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_target_vid_mem_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_coh_f(void)
+{
+        return 0x2U;
+}
+static inline u32 ram_in_page_dir_base_target_sys_mem_ncoh_f(void)
+{
+        return 0x3U;
+}
+static inline u32 ram_in_page_dir_base_vol_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_vol_true_f(void)
+{
+        return 0x4U;
+}
+static inline u32 ram_in_page_dir_base_vol_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void)
+{
+        return 0x10U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void)
+{
+        return 0x20U;
+}
+static inline u32 ram_in_use_ver2_pt_format_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
+static inline u32 ram_in_use_ver2_pt_format_m(void)
+{
+        return 0x1U << 10U;
+}
+static inline u32 ram_in_use_ver2_pt_format_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_use_ver2_pt_format_true_f(void)
+{
+        return 0x400U;
+}
+static inline u32 ram_in_use_ver2_pt_format_false_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_big_page_size_f(u32 v)
+{
+        return (v & 0x1U) << 11U;
+}
+static inline u32 ram_in_big_page_size_m(void)
+{
+        return 0x1U << 11U;
+}
+static inline u32 ram_in_big_page_size_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_big_page_size_128kb_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_big_page_size_64kb_f(void)
+{
+        return 0x800U;
+}
+static inline u32 ram_in_page_dir_base_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_in_page_dir_base_lo_w(void)
+{
+        return 128U;
+}
+static inline u32 ram_in_page_dir_base_hi_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ram_in_page_dir_base_hi_w(void)
+{
+        return 129U;
+}
+static inline u32 ram_in_engine_cs_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_engine_cs_wfi_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_engine_cs_wfi_f(void)
+{
+        return 0x0U;
+}
+static inline u32 ram_in_engine_cs_fg_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_engine_cs_fg_f(void)
+{
+        return 0x8U;
+}
+static inline u32 ram_in_engine_wfi_mode_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 ram_in_engine_wfi_mode_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_engine_wfi_mode_physical_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_engine_wfi_mode_virtual_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_engine_wfi_target_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ram_in_engine_wfi_target_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ram_in_engine_wfi_target_sys_mem_ncoh_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ram_in_engine_wfi_target_local_mem_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_in_engine_wfi_ptr_lo_w(void)
+{
+        return 132U;
+}
+static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 ram_in_engine_wfi_ptr_hi_w(void)
+{
+        return 133U;
+}
+static inline u32 ram_in_engine_wfi_veid_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 ram_in_engine_wfi_veid_w(void)
+{
+        return 134U;
+}
+static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ram_in_eng_method_buffer_addr_lo_w(void)
+{
+        return 136U;
+}
+static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 ram_in_eng_method_buffer_addr_hi_w(void)
+{
+        return 137U;
+}
+static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i)
+{
+        return (v & 0x3U) << (0U + i*0U);
+}
+static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (2U + i*0U);
+}
+static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 ram_in_sc_page_dir_base_vol_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_sc_page_dir_base_vol_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (4U + i*0U);
+}
+static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (5U + i*0U);
+}
+static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (10U + i*0U);
+}
+static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i)
+{
+        return (v & 0x1U) << (11U + i*0U);
+}
+static inline u32 ram_in_sc_big_page_size__size_1_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 ram_in_sc_big_page_size_64kb_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i)
+{
+        return (v & 0xfffffU) << (12U + i*0U);
+}
+static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i)
+{
+        return (v & 0xffffffffU) << (0U + i*0U);
+}
+static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 ram_in_sc_page_dir_base_target_0_w(void)
+{
+        return 168U;
+}
+static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 ram_in_sc_page_dir_base_vol_0_w(void)
+{
+        return 168U;
+}
+static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void)
+{
+        return 168U;
+}
+static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void)
+{
+        return 168U;
+}
+static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v)
+{
+        return (v & 0x1U) << 10U;
+}
+static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void)
+{
+        return 168U;
+}
+static inline u32 ram_in_sc_big_page_size_0_f(u32 v)
+{
+        return (v & 0x1U) << 11U;
+}
+static inline u32 ram_in_sc_big_page_size_0_w(void)
+{
+        return 168U;
+}
+static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_in_sc_page_dir_base_lo_0_w(void)
+{
+        return 168U;
+}
+static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ram_in_sc_page_dir_base_hi_0_w(void)
+{
+        return 169U;
+}
+static inline u32 ram_in_base_shift_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 ram_in_alloc_size_v(void)
+{
+        return 0x00001000U;
+}
+static inline u32 ram_fc_size_val_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 ram_fc_gp_put_w(void)
+{
+        return 0U;
+}
+static inline u32 ram_fc_userd_w(void)
+{
+        return 2U;
+}
+static inline u32 ram_fc_userd_hi_w(void)
+{
+        return 3U;
+}
+static inline u32 ram_fc_signature_w(void)
+{
+        return 4U;
+}
+static inline u32 ram_fc_gp_get_w(void)
+{
+        return 5U;
+}
+static inline u32 ram_fc_pb_get_w(void)
+{
+        return 6U;
+}
+static inline u32 ram_fc_pb_get_hi_w(void)
+{
+        return 7U;
+}
+static inline u32 ram_fc_pb_top_level_get_w(void)
+{
+        return 8U;
+}
+static inline u32 ram_fc_pb_top_level_get_hi_w(void)
+{
+        return 9U;
+}
+static inline u32 ram_fc_acquire_w(void)
+{
+        return 12U;
+}
+static inline u32 ram_fc_sem_addr_hi_w(void)
+{
+        return 14U;
+}
+static inline u32 ram_fc_sem_addr_lo_w(void)
+{
+        return 15U;
+}
+static inline u32 ram_fc_sem_payload_lo_w(void)
+{
+        return 16U;
+}
+static inline u32 ram_fc_sem_payload_hi_w(void)
+{
+        return 39U;
+}
+static inline u32 ram_fc_sem_execute_w(void)
+{
+        return 17U;
+}
+static inline u32 ram_fc_gp_base_w(void)
+{
+        return 18U;
+}
+static inline u32 ram_fc_gp_base_hi_w(void)
+{
+        return 19U;
+}
+static inline u32 ram_fc_gp_fetch_w(void)
+{
+        return 20U;
+}
+static inline u32 ram_fc_pb_fetch_w(void)
+{
+        return 21U;
+}
+static inline u32 ram_fc_pb_fetch_hi_w(void)
+{
+        return 22U;
+}
+static inline u32 ram_fc_pb_put_w(void)
+{
+        return 23U;
+}
+static inline u32 ram_fc_pb_put_hi_w(void)
+{
+        return 24U;
+}
+static inline u32 ram_fc_pb_header_w(void)
+{
+        return 33U;
+}
+static inline u32 ram_fc_pb_count_w(void)
+{
+        return 34U;
+}
+static inline u32 ram_fc_subdevice_w(void)
+{
+        return 37U;
+}
+static inline u32 ram_fc_target_w(void)
+{
+        return 43U;
+}
+static inline u32 ram_fc_hce_ctrl_w(void)
+{
+        return 57U;
+}
+static inline u32 ram_fc_chid_w(void)
+{
+        return 58U;
+}
+static inline u32 ram_fc_chid_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_fc_chid_id_w(void)
+{
+        return 0U;
+}
+static inline u32 ram_fc_config_w(void)
+{
+        return 61U;
+}
+static inline u32 ram_fc_runlist_timeslice_w(void)
+{
+        return 62U;
+}
+static inline u32 ram_fc_set_channel_info_w(void)
+{
+        return 63U;
+}
+static inline u32 ram_userd_base_shift_v(void)
+{
+        return 0x00000009U;
+}
+static inline u32 ram_userd_chan_size_v(void)
+{
+        return 0x00000200U;
+}
+static inline u32 ram_userd_put_w(void)
+{
+        return 16U;
+}
+static inline u32 ram_userd_get_w(void)
+{
+        return 17U;
+}
+static inline u32 ram_userd_ref_w(void)
+{
+        return 18U;
+}
+static inline u32 ram_userd_put_hi_w(void)
+{
+        return 19U;
+}
+static inline u32 ram_userd_ref_threshold_w(void)
+{
+        return 20U;
+}
+static inline u32 ram_userd_top_level_get_w(void)
+{
+        return 22U;
+}
+static inline u32 ram_userd_top_level_get_hi_w(void)
+{
+        return 23U;
+}
+static inline u32 ram_userd_get_hi_w(void)
+{
+        return 24U;
+}
+static inline u32 ram_userd_gp_get_w(void)
+{
+        return 34U;
+}
+static inline u32 ram_userd_gp_put_w(void)
+{
+        return 35U;
+}
+static inline u32 ram_userd_gp_top_level_get_w(void)
+{
+        return 22U;
+}
+static inline u32 ram_userd_gp_top_level_get_hi_w(void)
+{
+        return 23U;
+}
+static inline u32 ram_rl_entry_size_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 ram_rl_entry_type_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 ram_rl_entry_type_channel_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_rl_entry_type_tsg_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_rl_entry_id_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v)
+{
+        return (v & 0x1U) << 1U;
+}
+static inline u32 ram_rl_entry_chan_inst_target_f(u32 v)
+{
+        return (v & 0x3U) << 4U;
+}
+static inline u32 ram_rl_entry_chan_inst_target_sys_mem_ncoh_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ram_rl_entry_chan_inst_target_sys_mem_coh_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ram_rl_entry_chan_inst_target_vid_mem_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_rl_entry_chan_userd_target_f(u32 v)
+{
+        return (v & 0x3U) << 6U;
+}
+static inline u32 ram_rl_entry_chan_userd_target_vid_mem_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_rl_entry_chan_userd_target_vid_mem_nvlink_coh_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_rl_entry_chan_userd_target_sys_mem_coh_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v)
+{
+        return (v & 0xffffffU) << 8U;
+}
+static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ram_rl_entry_chid_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v)
+{
+        return (v & 0xfffffU) << 12U;
+}
+static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 ram_rl_entry_tsg_timeslice_scale_3_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v)
+{
+        return (v & 0xffU) << 24U;
+}
+static inline u32 ram_rl_entry_tsg_timeslice_timeout_128_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 ram_rl_entry_tsg_length_f(u32 v)
+{
+        return (v & 0xffU) << 0U;
+}
+static inline u32 ram_rl_entry_tsg_length_init_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 ram_rl_entry_tsg_length_min_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 ram_rl_entry_tsg_length_max_v(void)
+{
+        return 0x00000080U;
+}
+static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v)
+{
+        return (v & 0xfffU) << 0U;
+}
+static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ram_rl_entry_chan_userd_align_shift_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void)
+{
+        return 0x0000000cU;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_therm_gv100.h b/include/nvgpu/hw/gv100/hw_therm_gv100.h
new file mode 100644
index 0000000..2ea71ef
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_therm_gv100.h
@@ -0,0 +1,299 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_therm_gv100_h_
+#define _hw_therm_gv100_h_
+
+static inline u32 therm_weight_1_r(void)
+{
+        return 0x00020024U;
+}
+static inline u32 therm_config1_r(void)
+{
+        return 0x00020050U;
+}
+static inline u32 therm_config2_r(void)
+{
+        return 0x00020130U;
+}
+static inline u32 therm_config2_slowdown_factor_extended_f(u32 v)
+{
+        return (v & 0x1U) << 24U;
+}
+static inline u32 therm_config2_grad_enable_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 therm_gate_ctrl_r(u32 i)
+{
+        return 0x00020200U + i*4U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_run_f(void)
+{
+        return 0x0U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_auto_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_gate_ctrl_eng_clk_stop_f(void)
+{
+        return 0x2U;
+}
+static inline u32 therm_gate_ctrl_blk_clk_m(void)
+{
+        return 0x3U << 2U;
+}
+static inline u32 therm_gate_ctrl_blk_clk_run_f(void)
+{
+        return 0x0U;
+}
+static inline u32 therm_gate_ctrl_blk_clk_auto_f(void)
+{
+        return 0x4U;
+}
+static inline u32 therm_gate_ctrl_idle_holdoff_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 therm_gate_ctrl_idle_holdoff_off_f(void)
+{
+        return 0x0U;
+}
+static inline u32 therm_gate_ctrl_idle_holdoff_on_f(void)
+{
+        return 0x10U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v)
+{
+        return (v & 0x1fU) << 8U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void)
+{
+        return 0x1fU << 8U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v)
+{
+        return (v & 0x7U) << 13U;
+}
+static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void)
+{
+        return 0x7U << 13U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v)
+{
+        return (v & 0xfU) << 16U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_before_m(void)
+{
+        return 0xfU << 16U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v)
+{
+        return (v & 0xfU) << 20U;
+}
+static inline u32 therm_gate_ctrl_eng_delay_after_m(void)
+{
+        return 0xfU << 20U;
+}
+static inline u32 therm_fecs_idle_filter_r(void)
+{
+        return 0x00020288U;
+}
+static inline u32 therm_fecs_idle_filter_value_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 therm_hubmmu_idle_filter_r(void)
+{
+        return 0x0002028cU;
+}
+static inline u32 therm_hubmmu_idle_filter_value_m(void)
+{
+        return 0xffffffffU << 0U;
+}
+static inline u32 therm_clk_slowdown_r(u32 i)
+{
+        return 0x00020160U + i*4U;
+}
+static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
+{
+        return (v & 0x3fU) << 16U;
+}
+static inline u32 therm_clk_slowdown_idle_factor_m(void)
+{
+        return 0x3fU << 16U;
+}
+static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
+{
+        return (r >> 16U) & 0x3fU;
+}
+static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 therm_grad_stepping_table_r(u32 i)
+{
+        return 0x000202c8U + i*4U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v)
+{
+        return (v & 0x3fU) << 0U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void)
+{
+        return 0x3fU << 0U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void)
+{
+        return 0x2U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void)
+{
+        return 0x6U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void)
+{
+        return 0xeU;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v)
+{
+        return (v & 0x3fU) << 6U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void)
+{
+        return 0x3fU << 6U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v)
+{
+        return (v & 0x3fU) << 12U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void)
+{
+        return 0x3fU << 12U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v)
+{
+        return (v & 0x3fU) << 18U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void)
+{
+        return 0x3fU << 18U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v)
+{
+        return (v & 0x3fU) << 24U;
+}
+static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void)
+{
+        return 0x3fU << 24U;
+}
+static inline u32 therm_grad_stepping0_r(void)
+{
+        return 0x000202c0U;
+}
+static inline u32 therm_grad_stepping0_feature_s(void)
+{
+        return 1U;
+}
+static inline u32 therm_grad_stepping0_feature_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 therm_grad_stepping0_feature_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 therm_grad_stepping0_feature_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 therm_grad_stepping0_feature_enable_f(void)
+{
+        return 0x1U;
+}
+static inline u32 therm_grad_stepping1_r(void)
+{
+        return 0x000202c4U;
+}
+static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v)
+{
+        return (v & 0x1ffffU) << 0U;
+}
+static inline u32 therm_clk_timing_r(u32 i)
+{
+        return 0x000203c0U + i*4U;
+}
+static inline u32 therm_clk_timing_grad_slowdown_f(u32 v)
+{
+        return (v & 0x1U) << 16U;
+}
+static inline u32 therm_clk_timing_grad_slowdown_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void)
+{
+        return 0x10000U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_timer_gv100.h b/include/nvgpu/hw/gv100/hw_timer_gv100.h
new file mode 100644
index 0000000..9d76e24
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_timer_gv100.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_timer_gv100_h_
+#define _hw_timer_gv100_h_
+
+static inline u32 timer_pri_timeout_r(void)
+{
+        return 0x00009080U;
+}
+static inline u32 timer_pri_timeout_period_f(u32 v)
+{
+        return (v & 0xffffffU) << 0U;
+}
+static inline u32 timer_pri_timeout_period_m(void)
+{
+        return 0xffffffU << 0U;
+}
+static inline u32 timer_pri_timeout_period_v(u32 r)
+{
+        return (r >> 0U) & 0xffffffU;
+}
+static inline u32 timer_pri_timeout_en_f(u32 v)
+{
+        return (v & 0x1U) << 31U;
+}
+static inline u32 timer_pri_timeout_en_m(void)
+{
+        return 0x1U << 31U;
+}
+static inline u32 timer_pri_timeout_en_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 timer_pri_timeout_en_en_enabled_f(void)
+{
+        return 0x80000000U;
+}
+static inline u32 timer_pri_timeout_en_en_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 timer_pri_timeout_save_0_r(void)
+{
+        return 0x00009084U;
+}
+static inline u32 timer_pri_timeout_save_1_r(void)
+{
+        return 0x00009088U;
+}
+static inline u32 timer_pri_timeout_fecs_errcode_r(void)
+{
+        return 0x0000908cU;
+}
+static inline u32 timer_time_0_r(void)
+{
+        return 0x00009400U;
+}
+static inline u32 timer_time_1_r(void)
+{
+        return 0x00009410U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_top_gv100.h b/include/nvgpu/hw/gv100/hw_top_gv100.h
new file mode 100644
index 0000000..506a818
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_top_gv100.h
@@ -0,0 +1,343 @@
+/*
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_top_gv100_h_
+#define _hw_top_gv100_h_
+
+static inline u32 top_num_gpcs_r(void)
+{
+        return 0x00022430U;
+}
+static inline u32 top_num_gpcs_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_tpc_per_gpc_r(void)
+{
+        return 0x00022434U;
+}
+static inline u32 top_tpc_per_gpc_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_num_fbps_r(void)
+{
+        return 0x00022438U;
+}
+static inline u32 top_num_fbps_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_num_fbpas_r(void)
+{
+        return 0x0002243cU;
+}
+static inline u32 top_num_fbpas_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_ltc_per_fbp_r(void)
+{
+        return 0x00022450U;
+}
+static inline u32 top_ltc_per_fbp_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_slices_per_ltc_r(void)
+{
+        return 0x0002245cU;
+}
+static inline u32 top_slices_per_ltc_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_num_ltcs_r(void)
+{
+        return 0x00022454U;
+}
+static inline u32 top_num_ces_r(void)
+{
+        return 0x00022444U;
+}
+static inline u32 top_num_ces_value_v(u32 r)
+{
+        return (r >> 0U) & 0x1fU;
+}
+static inline u32 top_device_info_r(u32 i)
+{
+        return 0x00022700U + i*4U;
+}
+static inline u32 top_device_info__size_1_v(void)
+{
+        return 0x00000040U;
+}
+static inline u32 top_device_info_chain_v(u32 r)
+{
+        return (r >> 31U) & 0x1U;
+}
+static inline u32 top_device_info_chain_enable_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_device_info_engine_enum_v(u32 r)
+{
+        return (r >> 26U) & 0xfU;
+}
+static inline u32 top_device_info_runlist_enum_v(u32 r)
+{
+        return (r >> 21U) & 0xfU;
+}
+static inline u32 top_device_info_intr_enum_v(u32 r)
+{
+        return (r >> 15U) & 0x1fU;
+}
+static inline u32 top_device_info_reset_enum_v(u32 r)
+{
+        return (r >> 9U) & 0x1fU;
+}
+static inline u32 top_device_info_type_enum_v(u32 r)
+{
+        return (r >> 2U) & 0x1fffffffU;
+}
+static inline u32 top_device_info_type_enum_graphics_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 top_device_info_type_enum_graphics_f(void)
+{
+        return 0x0U;
+}
+static inline u32 top_device_info_type_enum_copy2_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 top_device_info_type_enum_copy2_f(void)
+{
+        return 0xcU;
+}
+static inline u32 top_device_info_type_enum_lce_v(void)
+{
+        return 0x00000013U;
+}
+static inline u32 top_device_info_type_enum_lce_f(void)
+{
+        return 0x4cU;
+}
+static inline u32 top_device_info_type_enum_ioctrl_v(void)
+{
+        return 0x00000012U;
+}
+static inline u32 top_device_info_type_enum_ioctrl_f(void)
+{
+        return 0x48U;
+}
+static inline u32 top_device_info_engine_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 top_device_info_runlist_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 top_device_info_intr_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 top_device_info_reset_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 top_device_info_entry_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 top_device_info_entry_not_valid_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 top_device_info_entry_enum_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 top_device_info_entry_data_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_device_info_entry_engine_type_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 top_device_info_data_type_v(u32 r)
+{
+        return (r >> 30U) & 0x1U;
+}
+static inline u32 top_device_info_data_type_enum2_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 top_device_info_data_inst_id_v(u32 r)
+{
+        return (r >> 26U) & 0xfU;
+}
+static inline u32 top_device_info_data_pri_base_v(u32 r)
+{
+        return (r >> 12U) & 0xfffU;
+}
+static inline u32 top_device_info_data_pri_base_align_v(void)
+{
+        return 0x0000000cU;
+}
+static inline u32 top_device_info_data_fault_id_enum_v(u32 r)
+{
+        return (r >> 3U) & 0x7fU;
+}
+static inline u32 top_device_info_data_fault_id_v(u32 r)
+{
+        return (r >> 2U) & 0x1U;
+}
+static inline u32 top_device_info_data_fault_id_valid_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 top_nvhsclk_ctrl_r(void)
+{
+        return 0x00022424U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_nvl_f(u32 v)
+{
+        return (v & 0x7U) << 0U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_nvl_m(void)
+{
+        return 0x7U << 0U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_nvl_v(u32 r)
+{
+        return (r >> 0U) & 0x7U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_pcie_f(u32 v)
+{
+        return (v & 0x1U) << 3U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_pcie_m(void)
+{
+        return 0x1U << 3U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_pcie_v(u32 r)
+{
+        return (r >> 3U) & 0x1U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_core_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_core_m(void)
+{
+        return 0x1U << 4U;
+}
+static inline u32 top_nvhsclk_ctrl_e_clk_core_v(u32 r)
+{
+        return (r >> 4U) & 0x1U;
+}
+static inline u32 top_nvhsclk_ctrl_rfu_f(u32 v)
+{
+        return (v & 0xfU) << 5U;
+}
+static inline u32 top_nvhsclk_ctrl_rfu_m(void)
+{
+        return 0xfU << 5U;
+}
+static inline u32 top_nvhsclk_ctrl_rfu_v(u32 r)
+{
+        return (r >> 5U) & 0xfU;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_f(u32 v)
+{
+        return (v & 0x7U) << 10U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_m(void)
+{
+        return 0x7U << 10U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_nvl_v(u32 r)
+{
+        return (r >> 10U) & 0x7U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_f(u32 v)
+{
+        return (v & 0x1U) << 9U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_m(void)
+{
+        return 0x1U << 9U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_pcie_v(u32 r)
+{
+        return (r >> 9U) & 0x1U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_core_f(u32 v)
+{
+        return (v & 0x1U) << 13U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_core_m(void)
+{
+        return 0x1U << 13U;
+}
+static inline u32 top_nvhsclk_ctrl_swap_clk_core_v(u32 r)
+{
+        return (r >> 13U) & 0x1U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_trim_gv100.h b/include/nvgpu/hw/gv100/hw_trim_gv100.h
new file mode 100644
index 0000000..f1b6da2
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_trim_gv100.h
@@ -0,0 +1,247 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_trim_gv100_h_
+#define _hw_trim_gv100_h_
+
+static inline u32 trim_sys_nvlink_uphy_cfg_r(void)
+{
+        return 0x00132410U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_f(u32 v)
+{
+        return (v & 0x3ffU) << 0U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_m(void)
+{
+        return 0x3ffU << 0U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_lockdect_wait_dly_length_v(u32 r)
+{
+        return (r >> 0U) & 0x3ffU;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(u32 v)
+{
+        return (v & 0x1U) << 12U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_m(void)
+{
+        return 0x1U << 12U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_v(u32 r)
+{
+        return (r >> 12U) & 0x1U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_f(u32 v)
+{
+        return (v & 0xffU) << 16U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_m(void)
+{
+        return 0xffU << 16U;
+}
+static inline u32 trim_sys_nvlink_uphy_cfg_nvlink_wait_dly_v(u32 r)
+{
+        return (r >> 16U) & 0xffU;
+}
+static inline u32 trim_sys_nvlink0_ctrl_r(void)
+{
+        return 0x00132420U;
+}
+static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 trim_sys_nvlink0_ctrl_unit2clks_pll_turn_off_v(u32 r)
+{
+        return (r >> 0U) & 0x1U;
+}
+static inline u32 trim_sys_nvlink0_status_r(void)
+{
+        return 0x00132424U;
+}
+static inline u32 trim_sys_nvlink0_status_pll_off_f(u32 v)
+{
+        return (v & 0x1U) << 5U;
+}
+static inline u32 trim_sys_nvlink0_status_pll_off_m(void)
+{
+        return 0x1U << 5U;
+}
+static inline u32 trim_sys_nvlink0_status_pll_off_v(u32 r)
+{
+        return (r >> 5U) & 0x1U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_r(void)
+{
+        return 0x001371c4U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_f(u32 v)
+{
+        return (v & 0x3U) << 16U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_m(void)
+{
+        return 0x3U << 16U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_v(u32 r)
+{
+        return (r >> 16U) & 0x3U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal4x_f(void)
+{
+        return 0x30000U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_slowclk_xtal_in_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_f(u32 v)
+{
+        return (v & 0x3U) << 0U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_m(void)
+{
+        return 0x3U << 0U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_v(u32 r)
+{
+        return (r >> 0U) & 0x3U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_slowclk_f(void)
+{
+        return 0x0U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_miscclk_f(void)
+{
+        return 0x2U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 trim_sys_nvl_common_clk_alt_switch_finalsel_onesrcclk_f(void)
+{
+        return 0x3U;
+}
+static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_r(void)
+{
+        return 0x00132a70U;
+}
+static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cfg_source_gpcclk_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt0_r(void)
+{
+        return 0x00132a74U;
+}
+static inline u32 trim_gpc_bcast_fr_clk_cntr_ncgpcclk_cnt1_r(void)
+{
+        return 0x00132a78U;
+}
+static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cfg_r(void)
+{
+        return 0x00136470U;
+}
+static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cfg_source_xbarclk_f(void)
+{
+        return 0x10000000U;
+}
+static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cntr0_r(void)
+{
+        return 0x00136474U;
+}
+static inline u32 trim_sys_nafll_fr_clk_cntr_xbarclk_cntr1_r(void)
+{
+        return 0x00136478U;
+}
+static inline u32 trim_sys_fr_clk_cntr_sysclk_cfg_r(void)
+{
+        return 0x0013762cU;
+}
+static inline u32 trim_sys_fr_clk_cntr_sysclk_cfg_source_sysclk_f(void)
+{
+        return 0x20000000U;
+}
+static inline u32 trim_sys_fr_clk_cntr_sysclk_cntr0_r(void)
+{
+        return 0x00137630U;
+}
+static inline u32 trim_sys_fr_clk_cntr_sysclk_cntr1_r(void)
+{
+        return 0x00137634U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_usermode_gv100.h b/include/nvgpu/hw/gv100/hw_usermode_gv100.h
new file mode 100644
index 0000000..7b1d861
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_usermode_gv100.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_usermode_gv100_h_
+#define _hw_usermode_gv100_h_
+
+static inline u32 usermode_cfg0_r(void)
+{
+        return 0x00810000U;
+}
+static inline u32 usermode_cfg0_class_id_f(u32 v)
+{
+        return (v & 0xffffU) << 0U;
+}
+static inline u32 usermode_cfg0_class_id_value_v(void)
+{
+        return 0x0000c361U;
+}
+static inline u32 usermode_time_0_r(void)
+{
+        return 0x00810080U;
+}
+static inline u32 usermode_time_0_nsec_f(u32 v)
+{
+        return (v & 0x7ffffffU) << 5U;
+}
+static inline u32 usermode_time_1_r(void)
+{
+        return 0x00810084U;
+}
+static inline u32 usermode_time_1_nsec_f(u32 v)
+{
+        return (v & 0x1fffffffU) << 0U;
+}
+static inline u32 usermode_notify_channel_pending_r(void)
+{
+        return 0x00810090U;
+}
+static inline u32 usermode_notify_channel_pending_id_f(u32 v)
+{
+        return (v & 0xffffffffU) << 0U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_xp_gv100.h b/include/nvgpu/hw/gv100/hw_xp_gv100.h
new file mode 100644
index 0000000..4296e04
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_xp_gv100.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_xp_gv100_h_
+#define _hw_xp_gv100_h_
+
+static inline u32 xp_dl_mgr_r(u32 i)
+{
+        return 0x0008b8c0U + i*4U;
+}
+static inline u32 xp_dl_mgr_safe_timing_f(u32 v)
+{
+        return (v & 0x1U) << 2U;
+}
+static inline u32 xp_pl_link_config_r(u32 i)
+{
+        return 0x0008c040U + i*4U;
+}
+static inline u32 xp_pl_link_config_ltssm_status_f(u32 v)
+{
+        return (v & 0x1U) << 4U;
+}
+static inline u32 xp_pl_link_config_ltssm_status_idle_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_f(u32 v)
+{
+        return (v & 0xfU) << 0U;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_m(void)
+{
+        return 0xfU << 0U;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_normal_operations_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 xp_pl_link_config_ltssm_directive_change_speed_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 xp_pl_link_config_max_link_rate_f(u32 v)
+{
+        return (v & 0x3U) << 18U;
+}
+static inline u32 xp_pl_link_config_max_link_rate_m(void)
+{
+        return 0x3U << 18U;
+}
+static inline u32 xp_pl_link_config_max_link_rate_2500_mtps_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 xp_pl_link_config_max_link_rate_5000_mtps_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 xp_pl_link_config_max_link_rate_8000_mtps_v(void)
+{
+        return 0x00000000U;
+}
+static inline u32 xp_pl_link_config_target_tx_width_f(u32 v)
+{
+        return (v & 0x7U) << 20U;
+}
+static inline u32 xp_pl_link_config_target_tx_width_m(void)
+{
+        return 0x7U << 20U;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x1_v(void)
+{
+        return 0x00000007U;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x2_v(void)
+{
+        return 0x00000006U;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x4_v(void)
+{
+        return 0x00000005U;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x8_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 xp_pl_link_config_target_tx_width_x16_v(void)
+{
+        return 0x00000000U;
+}
+#endif
diff --git a/include/nvgpu/hw/gv100/hw_xve_gv100.h b/include/nvgpu/hw/gv100/hw_xve_gv100.h
new file mode 100644
index 0000000..fc7aa72
--- /dev/null
+++ b/include/nvgpu/hw/gv100/hw_xve_gv100.h
@@ -0,0 +1,207 @@
+/*
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+/*
+ * Function naming determines intended use:
+ *
+ *     <x>_r(void) : Returns the offset for register <x>.
+ *
+ *     <x>_o(void) : Returns the offset for element <x>.
+ *
+ *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
+ *
+ *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
+ *
+ *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
+ *         and masked to place it at field <y> of register <x>.  This value
+ *         can be |'d with others to produce a full register value for
+ *         register <x>.
+ *
+ *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
+ *         value can be ~'d and then &'d to clear the value of field <y> for
+ *         register <x>.
+ *
+ *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
+ *         to place it at field <y> of register <x>.  This value can be |'d
+ *         with others to produce a full register value for <x>.
+ *
+ *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
+ *         <x> value 'r' after being shifted to place its LSB at bit 0.
+ *         This value is suitable for direct comparison with other unshifted
+ *         values appropriate for use in field <y> of register <x>.
+ *
+ *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
+ *         field <y> of register <x>.  This value is suitable for direct
+ *         comparison with unshifted values appropriate for use in field <y>
+ *         of register <x>.
+ */
+#ifndef _hw_xve_gv100_h_
+#define _hw_xve_gv100_h_
+
+static inline u32 xve_rom_ctrl_r(void)
+{
+        return 0x00000050U;
+}
+static inline u32 xve_rom_ctrl_rom_shadow_f(u32 v)
+{
+        return (v & 0x1U) << 0U;
+}
+static inline u32 xve_rom_ctrl_rom_shadow_disabled_f(void)
+{
+        return 0x0U;
+}
+static inline u32 xve_rom_ctrl_rom_shadow_enabled_f(void)
+{
+        return 0x1U;
+}
+static inline u32 xve_link_control_status_r(void)
+{
+        return 0x00000088U;
+}
+static inline u32 xve_link_control_status_link_speed_m(void)
+{
+        return 0xfU << 16U;
+}
+static inline u32 xve_link_control_status_link_speed_v(u32 r)
+{
+        return (r >> 16U) & 0xfU;
+}
+static inline u32 xve_link_control_status_link_speed_link_speed_2p5_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 xve_link_control_status_link_speed_link_speed_5p0_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 xve_link_control_status_link_speed_link_speed_8p0_v(void)
+{
+        return 0x00000003U;
+}
+static inline u32 xve_link_control_status_link_width_m(void)
+{
+        return 0x3fU << 20U;
+}
+static inline u32 xve_link_control_status_link_width_v(u32 r)
+{
+        return (r >> 20U) & 0x3fU;
+}
+static inline u32 xve_link_control_status_link_width_x1_v(void)
+{
+        return 0x00000001U;
+}
+static inline u32 xve_link_control_status_link_width_x2_v(void)
+{
+        return 0x00000002U;
+}
+static inline u32 xve_link_control_status_link_width_x4_v(void)
+{
+        return 0x00000004U;
+}
+static inline u32 xve_link_control_status_link_width_x8_v(void)
+{
+        return 0x00000008U;
+}
+static inline u32 xve_link_control_status_link_width_x16_v(void)
+{
+        return 0x00000010U;
+}
+static inline u32 xve_priv_xv_r(void)
+{
+        return 0x00000150U;
+}
+static inline u32 xve_priv_xv_cya_l0s_enable_f(u32 v)
+{
+        return (v & 0x1U) << 7U;
+}
+static inline u32 xve_priv_xv_cya_l0s_enable_m(void)
+{
+        return 0x1U << 7U;
+}
+static inline u32 xve_priv_xv_cya_l0s_enable_v(u32 r)
+{
+        return (r >> 7U) & 0x1U;
+}
+static inline u32 xve_priv_xv_cya_l1_enable_f(u32 v)
+{
+        return (v & 0x1U) << 8U;
+}
+static inline u32 xve_priv_xv_cya_l1_enable_m(void)
+{
+        return 0x1U << 8U;
+}
+static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r)
+{
+        return (r >> 8U) & 0x1U;
+}
+static inline u32 xve_cya_2_r(void)
+{
+        return 0x00000704U;
+}
+static inline u32 xve_reset_r(void)
+{
+        return 0x00000718U;
+}
+static inline u32 xve_reset_reset_m(void)
+{
+        return 0x1U << 0U;
+}
+static inline u32 xve_reset_gpu_on_sw_reset_m(void)
+{
+        return 0x1U << 1U;
+}
+static inline u32 xve_reset_counter_en_m(void)
+{
+        return 0x1U << 2U;
+}
+static inline u32 xve_reset_counter_val_f(u32 v)
+{
+        return (v & 0x7ffU) << 4U;
+}
+static inline u32 xve_reset_counter_val_m(void)
+{
+        return 0x7ffU << 4U;
+}
+static inline u32 xve_reset_counter_val_v(u32 r)
+{
+        return (r >> 4U) & 0x7ffU;
+}
+static inline u32 xve_reset_clock_on_sw_reset_m(void)
+{
+        return 0x1U << 15U;
+}
+static inline u32 xve_reset_clock_counter_en_m(void)
+{
+        return 0x1U << 16U;
+}
+static inline u32 xve_reset_clock_counter_val_f(u32 v)
+{
+        return (v & 0x7ffU) << 17U;
+}
+static inline u32 xve_reset_clock_counter_val_m(void)
+{
+        return 0x7ffU << 17U;
+}
+static inline u32 xve_reset_clock_counter_val_v(u32 r)
+{
+        return (r >> 17U) & 0x7ffU;
+}
+#endif