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diff --git a/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h b/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h
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+++ b/include/nvgpu/hw/gv100/hw_ioctrl_gv100.h
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1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22/*
23 * Function naming determines intended use:
24 *
25 * <x>_r(void) : Returns the offset for register <x>.
26 *
27 * <x>_o(void) : Returns the offset for element <x>.
28 *
29 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
30 *
31 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
32 *
33 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
34 * and masked to place it at field <y> of register <x>. This value
35 * can be |'d with others to produce a full register value for
36 * register <x>.
37 *
38 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
39 * value can be ~'d and then &'d to clear the value of field <y> for
40 * register <x>.
41 *
42 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
43 * to place it at field <y> of register <x>. This value can be |'d
44 * with others to produce a full register value for <x>.
45 *
46 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
47 * <x> value 'r' after being shifted to place its LSB at bit 0.
48 * This value is suitable for direct comparison with other unshifted
49 * values appropriate for use in field <y> of register <x>.
50 *
51 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
52 * field <y> of register <x>. This value is suitable for direct
53 * comparison with unshifted values appropriate for use in field <y>
54 * of register <x>.
55 */
56#ifndef _hw_ioctrl_gv100_h_
57#define _hw_ioctrl_gv100_h_
58
59static inline u32 ioctrl_reset_r(void)
60{
61 return 0x00000140U;
62}
63static inline u32 ioctrl_reset_sw_post_reset_delay_microseconds_v(void)
64{
65 return 0x00000008U;
66}
67static inline u32 ioctrl_reset_linkreset_f(u32 v)
68{
69 return (v & 0x3fU) << 8U;
70}
71static inline u32 ioctrl_reset_linkreset_m(void)
72{
73 return 0x3fU << 8U;
74}
75static inline u32 ioctrl_reset_linkreset_v(u32 r)
76{
77 return (r >> 8U) & 0x3fU;
78}
79static inline u32 ioctrl_debug_reset_r(void)
80{
81 return 0x00000144U;
82}
83static inline u32 ioctrl_debug_reset_link_f(u32 v)
84{
85 return (v & 0x3fU) << 0U;
86}
87static inline u32 ioctrl_debug_reset_link_m(void)
88{
89 return 0x3fU << 0U;
90}
91static inline u32 ioctrl_debug_reset_link_v(u32 r)
92{
93 return (r >> 0U) & 0x3fU;
94}
95static inline u32 ioctrl_debug_reset_common_f(u32 v)
96{
97 return (v & 0x1U) << 31U;
98}
99static inline u32 ioctrl_debug_reset_common_m(void)
100{
101 return 0x1U << 31U;
102}
103static inline u32 ioctrl_debug_reset_common_v(u32 r)
104{
105 return (r >> 31U) & 0x1U;
106}
107static inline u32 ioctrl_clock_control_r(u32 i)
108{
109 return 0x00000180U + i*4U;
110}
111static inline u32 ioctrl_clock_control__size_1_v(void)
112{
113 return 0x00000006U;
114}
115static inline u32 ioctrl_clock_control_clkdis_f(u32 v)
116{
117 return (v & 0x1U) << 0U;
118}
119static inline u32 ioctrl_clock_control_clkdis_m(void)
120{
121 return 0x1U << 0U;
122}
123static inline u32 ioctrl_clock_control_clkdis_v(u32 r)
124{
125 return (r >> 0U) & 0x1U;
126}
127static inline u32 ioctrl_top_intr_0_status_r(void)
128{
129 return 0x00000200U;
130}
131static inline u32 ioctrl_top_intr_0_status_link_f(u32 v)
132{
133 return (v & 0x3fU) << 0U;
134}
135static inline u32 ioctrl_top_intr_0_status_link_m(void)
136{
137 return 0x3fU << 0U;
138}
139static inline u32 ioctrl_top_intr_0_status_link_v(u32 r)
140{
141 return (r >> 0U) & 0x3fU;
142}
143static inline u32 ioctrl_top_intr_0_status_common_f(u32 v)
144{
145 return (v & 0x1U) << 31U;
146}
147static inline u32 ioctrl_top_intr_0_status_common_m(void)
148{
149 return 0x1U << 31U;
150}
151static inline u32 ioctrl_top_intr_0_status_common_v(u32 r)
152{
153 return (r >> 31U) & 0x1U;
154}
155static inline u32 ioctrl_common_intr_0_mask_r(void)
156{
157 return 0x00000220U;
158}
159static inline u32 ioctrl_common_intr_0_mask_fatal_f(u32 v)
160{
161 return (v & 0x1U) << 0U;
162}
163static inline u32 ioctrl_common_intr_0_mask_fatal_v(u32 r)
164{
165 return (r >> 0U) & 0x1U;
166}
167static inline u32 ioctrl_common_intr_0_mask_nonfatal_f(u32 v)
168{
169 return (v & 0x1U) << 1U;
170}
171static inline u32 ioctrl_common_intr_0_mask_nonfatal_v(u32 r)
172{
173 return (r >> 1U) & 0x1U;
174}
175static inline u32 ioctrl_common_intr_0_mask_correctable_f(u32 v)
176{
177 return (v & 0x1U) << 2U;
178}
179static inline u32 ioctrl_common_intr_0_mask_correctable_v(u32 r)
180{
181 return (r >> 2U) & 0x1U;
182}
183static inline u32 ioctrl_common_intr_0_mask_intra_f(u32 v)
184{
185 return (v & 0x1U) << 3U;
186}
187static inline u32 ioctrl_common_intr_0_mask_intra_v(u32 r)
188{
189 return (r >> 3U) & 0x1U;
190}
191static inline u32 ioctrl_common_intr_0_mask_intrb_f(u32 v)
192{
193 return (v & 0x1U) << 4U;
194}
195static inline u32 ioctrl_common_intr_0_mask_intrb_v(u32 r)
196{
197 return (r >> 4U) & 0x1U;
198}
199static inline u32 ioctrl_common_intr_0_status_r(void)
200{
201 return 0x00000224U;
202}
203static inline u32 ioctrl_common_intr_0_status_fatal_f(u32 v)
204{
205 return (v & 0x1U) << 0U;
206}
207static inline u32 ioctrl_common_intr_0_status_fatal_v(u32 r)
208{
209 return (r >> 0U) & 0x1U;
210}
211static inline u32 ioctrl_common_intr_0_status_nonfatal_f(u32 v)
212{
213 return (v & 0x1U) << 1U;
214}
215static inline u32 ioctrl_common_intr_0_status_nonfatal_v(u32 r)
216{
217 return (r >> 1U) & 0x1U;
218}
219static inline u32 ioctrl_common_intr_0_status_correctable_f(u32 v)
220{
221 return (v & 0x1U) << 2U;
222}
223static inline u32 ioctrl_common_intr_0_status_correctable_v(u32 r)
224{
225 return (r >> 2U) & 0x1U;
226}
227static inline u32 ioctrl_common_intr_0_status_intra_f(u32 v)
228{
229 return (v & 0x1U) << 3U;
230}
231static inline u32 ioctrl_common_intr_0_status_intra_v(u32 r)
232{
233 return (r >> 3U) & 0x1U;
234}
235static inline u32 ioctrl_common_intr_0_status_intrb_f(u32 v)
236{
237 return (v & 0x1U) << 4U;
238}
239static inline u32 ioctrl_common_intr_0_status_intrb_v(u32 r)
240{
241 return (r >> 4U) & 0x1U;
242}
243static inline u32 ioctrl_link_intr_0_mask_r(u32 i)
244{
245 return 0x00000240U + i*20U;
246}
247static inline u32 ioctrl_link_intr_0_mask_fatal_f(u32 v)
248{
249 return (v & 0x1U) << 0U;
250}
251static inline u32 ioctrl_link_intr_0_mask_fatal_v(u32 r)
252{
253 return (r >> 0U) & 0x1U;
254}
255static inline u32 ioctrl_link_intr_0_mask_nonfatal_f(u32 v)
256{
257 return (v & 0x1U) << 1U;
258}
259static inline u32 ioctrl_link_intr_0_mask_nonfatal_v(u32 r)
260{
261 return (r >> 1U) & 0x1U;
262}
263static inline u32 ioctrl_link_intr_0_mask_correctable_f(u32 v)
264{
265 return (v & 0x1U) << 2U;
266}
267static inline u32 ioctrl_link_intr_0_mask_correctable_v(u32 r)
268{
269 return (r >> 2U) & 0x1U;
270}
271static inline u32 ioctrl_link_intr_0_mask_intra_f(u32 v)
272{
273 return (v & 0x1U) << 3U;
274}
275static inline u32 ioctrl_link_intr_0_mask_intra_v(u32 r)
276{
277 return (r >> 3U) & 0x1U;
278}
279static inline u32 ioctrl_link_intr_0_mask_intrb_f(u32 v)
280{
281 return (v & 0x1U) << 4U;
282}
283static inline u32 ioctrl_link_intr_0_mask_intrb_v(u32 r)
284{
285 return (r >> 4U) & 0x1U;
286}
287static inline u32 ioctrl_link_intr_0_status_r(u32 i)
288{
289 return 0x00000244U + i*20U;
290}
291static inline u32 ioctrl_link_intr_0_status_fatal_f(u32 v)
292{
293 return (v & 0x1U) << 0U;
294}
295static inline u32 ioctrl_link_intr_0_status_fatal_v(u32 r)
296{
297 return (r >> 0U) & 0x1U;
298}
299static inline u32 ioctrl_link_intr_0_status_nonfatal_f(u32 v)
300{
301 return (v & 0x1U) << 1U;
302}
303static inline u32 ioctrl_link_intr_0_status_nonfatal_v(u32 r)
304{
305 return (r >> 1U) & 0x1U;
306}
307static inline u32 ioctrl_link_intr_0_status_correctable_f(u32 v)
308{
309 return (v & 0x1U) << 2U;
310}
311static inline u32 ioctrl_link_intr_0_status_correctable_v(u32 r)
312{
313 return (r >> 2U) & 0x1U;
314}
315static inline u32 ioctrl_link_intr_0_status_intra_f(u32 v)
316{
317 return (v & 0x1U) << 3U;
318}
319static inline u32 ioctrl_link_intr_0_status_intra_v(u32 r)
320{
321 return (r >> 3U) & 0x1U;
322}
323static inline u32 ioctrl_link_intr_0_status_intrb_f(u32 v)
324{
325 return (v & 0x1U) << 4U;
326}
327static inline u32 ioctrl_link_intr_0_status_intrb_v(u32 r)
328{
329 return (r >> 4U) & 0x1U;
330}
331#endif